repo_name
stringlengths
6
79
path
stringlengths
6
236
copies
int64
1
472
size
int64
137
1.04M
content
stringlengths
137
1.04M
license
stringclasses
15 values
hash
stringlengths
32
32
alpha_frac
float64
0.25
0.96
ratio
float64
1.51
17.5
autogenerated
bool
1 class
config_or_test
bool
2 classes
has_no_keywords
bool
1 class
has_few_assignments
bool
1 class
wsoltys/AtomFpga
src/ps2kybrd/keyboard.vhd
1
9,266
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.std_logic_unsigned.all; entity keyboard is port ( CLOCK : in std_logic; nRESET : in std_logic; CLKEN_1MHZ : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; KEYOUT : out std_logic_vector(5 downto 0); ROW : in std_logic_vector(3 downto 0); ESC_IN : in std_logic; BREAK_IN : in std_logic; SHIFT_OUT : out std_logic; CTRL_OUT : out std_logic; REPEAT_OUT : out std_logic; BREAK_OUT : out std_logic; TURBO : out std_logic_vector(1 downto 0); ESC_OUT : out std_logic); end entity; architecture rtl of keyboard is component ps2_intf is generic (filter_length : positive := 8); port( CLK : in std_logic; nRESET : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; DATA : out std_logic_vector(7 downto 0); VALID : out std_logic; error : out std_logic ); end component; signal keyb_data : std_logic_vector(7 downto 0); signal keyb_valid : std_logic; signal keyb_error : std_logic; type key_matrix is array(0 to 15) of std_logic_vector(7 downto 0); signal keys : key_matrix; signal col : unsigned(3 downto 0); signal release : std_logic; signal extended : std_logic; signal key_data : std_logic_vector(7 downto 0); signal ESC_IN1 : std_logic; signal BREAK_IN1 : std_logic; begin ps2 : ps2_intf port map ( CLOCK, nRESET, PS2_CLK, PS2_DATA, keyb_data, keyb_valid, keyb_error); process(keys, ROW) begin key_data <= keys(conv_integer(ROW(3 downto 0))); KEYOUT <= key_data(5 downto 0); end process; process(CLOCK, nRESET) begin if nRESET = '0' then release <= '0'; extended <= '0'; TURBO <= "00"; BREAK_OUT <= '1'; SHIFT_OUT <= '1'; CTRL_OUT <= '1'; REPEAT_OUT <= '1'; ESC_IN1 <= ESC_IN; BREAK_IN1 <= BREAK_IN; keys(0) <= (others => '1'); keys(1) <= (others => '1'); keys(2) <= (others => '1'); keys(3) <= (others => '1'); keys(4) <= (others => '1'); keys(5) <= (others => '1'); keys(6) <= (others => '1'); keys(7) <= (others => '1'); keys(8) <= (others => '1'); keys(9) <= (others => '1'); keys(10) <= (others => '1'); keys(11) <= (others => '1'); keys(12) <= (others => '1'); keys(13) <= (others => '1'); keys(14) <= (others => '1'); keys(15) <= (others => '1'); elsif rising_edge(CLOCK) then -- handle the escape key seperately, as it's value also depends on ESC_IN if keyb_valid = '1' and keyb_data = X"76" then keys(0)(5) <= release; elsif ESC_IN /= ESC_IN1 then keys(0)(5) <= ESC_IN; end if; ESC_IN1 <= ESC_IN; -- handle the break key seperately, as it's value also depends on BREAK_IN if keyb_valid = '1' and keyb_data = X"09" then BREAK_OUT <= release; elsif BREAK_IN /= BREAK_IN1 then BREAK_OUT <= BREAK_IN; end if; BREAK_IN1 <= BREAK_IN; if keyb_valid = '1' then if keyb_data = X"e0" then extended <= '1'; elsif keyb_data = X"f0" then release <= '1'; else release <= '0'; extended <= '0'; case keyb_data is when X"05" => TURBO <= "00"; -- F1 (1MHz) when X"06" => TURBO <= "01"; -- F2 (2MMz) when X"04" => TURBO <= "10"; -- F3 (4MHz) when X"0C" => TURBO <= "11"; -- F4 (8MHz) -- when X"09" => BREAK_OUT <= release; -- F10 (BREAK) when X"11" => REPEAT_OUT <= release; -- LEFT ALT (SHIFT LOCK) when X"12" | X"59" => if (extended = '0') then -- Ignore fake shifts SHIFT_OUT <= release; -- Left SHIFT -- Right SHIFT end if; when X"14" => CTRL_OUT <= release; -- LEFT/RIGHT CTRL (CTRL) ----------------------------------------------------- -- process matrix ----------------------------------------------------- when X"29" => keys(9)(0) <= release; -- SPACE when X"54" => keys(8)(0) <= release; -- [ when X"5D" => keys(7)(0) <= release; -- \ when X"5B" => keys(6)(0) <= release; -- ] when X"0D" => keys(5)(0) <= release; -- UP when X"58" => keys(4)(0) <= release; -- CAPS LOCK when X"74" => keys(3)(0) <= release; -- RIGHT when X"75" => keys(2)(0) <= release; -- UP when X"5A" => keys(6)(1) <= release; -- RETURN when X"69" => keys(5)(1) <= release; -- END (COPY) when X"66" => keys(4)(1) <= release; -- BACKSPACE (DELETE) when X"45" => keys(3)(1) <= release; -- 0 when X"16" => keys(2)(1) <= release; -- 1 when X"1E" => keys(1)(1) <= release; -- 2 when X"26" => keys(0)(1) <= release; -- 3 when X"25" => keys(9)(2) <= release; -- 4 when X"2E" => keys(8)(2) <= release; -- 5 when X"36" => keys(7)(2) <= release; -- 6 when X"3D" => keys(6)(2) <= release; -- 7 when X"3E" => keys(5)(2) <= release; -- 8 when X"46" => keys(4)(2) <= release; -- 9 when X"52" => keys(3)(2) <= release; -- ' full colon substitute when X"4C" => keys(2)(2) <= release; -- ; when X"41" => keys(1)(2) <= release; -- , when X"4E" => keys(0)(2) <= release; -- - when X"49" => keys(9)(3) <= release; -- . when X"4A" => keys(8)(3) <= release; -- / when X"55" => keys(7)(3) <= release; -- @ (TAB) when X"1C" => keys(6)(3) <= release; -- A when X"32" => keys(5)(3) <= release; -- B when X"21" => keys(4)(3) <= release; -- C when X"23" => keys(3)(3) <= release; -- D when X"24" => keys(2)(3) <= release; -- E when X"2B" => keys(1)(3) <= release; -- F when X"34" => keys(0)(3) <= release; -- G when X"33" => keys(9)(4) <= release; -- H when X"43" => keys(8)(4) <= release; -- I when X"3B" => keys(7)(4) <= release; -- J when X"42" => keys(6)(4) <= release; -- K when X"4B" => keys(5)(4) <= release; -- L when X"3A" => keys(4)(4) <= release; -- M when X"31" => keys(3)(4) <= release; -- N when X"44" => keys(2)(4) <= release; -- O when X"4D" => keys(1)(4) <= release; -- P when X"15" => keys(0)(4) <= release; -- Q when X"2D" => keys(9)(5) <= release; -- R when X"1B" => keys(8)(5) <= release; -- S when X"2C" => keys(7)(5) <= release; -- T when X"3C" => keys(6)(5) <= release; -- U when X"2A" => keys(5)(5) <= release; -- V when X"1D" => keys(4)(5) <= release; -- W when X"22" => keys(3)(5) <= release; -- X when X"35" => keys(2)(5) <= release; -- Y when X"1A" => keys(1)(5) <= release; -- Z -- when X"76" => keys(0)(5) <= release; -- ESCAPE when others => null; end case; end if; end if; end if; end process; ESC_OUT <= keys(0)(5); end architecture;
apache-2.0
c1b3842df5577b64f7097d3479960cb4
0.365746
3.785131
false
false
false
false
grwlf/vsim
vhdl_ct/pro000013.vhd
1
4,015
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00010_Test_Bench is end ENT00010_Test_Bench; architecture ARCH00010_Test_Bench of ENT00010_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b2 : byte2 := x"00"; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal ea : enum_array(0 to 3) := (others => a_v); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; type BoolVector is array (integer range <>) of boolean; signal bool : BoolVector(1 to 60); begin bool(1) <= bv'Stable(20 ns); bool(2) <= ra'Stable(20 ns); bool(3) <= r'Stable(20 ns); bool(4) <= ea'Stable(20 ns); bool(5) <= e'Stable(20 ns); bool(6) <= I_sa'Stable(20 ns); bool(7) <= I_baa'Stable(20 ns); bool(8) <= I_saa'Stable(20 ns); bool(9) <= b1'Stable(20 ns); bool(10) <= b2'Stable(20 ns); bool(11) <= clk'Stable(20 ns); bool(12) <= clk2'Stable(20 ns); clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00010_Test_Bench ;
gpl-3.0
17682324538c61f37a2172a16fbcf02a
0.544707
2.46319
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/syn/vhdl/sample_iterator_get_offset.vhd
1
7,145
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_req_din : OUT STD_LOGIC; indices_req_full_n : IN STD_LOGIC; indices_req_write : OUT STD_LOGIC; indices_rsp_empty_n : IN STD_LOGIC; indices_rsp_read : OUT STD_LOGIC; indices_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_datain : IN STD_LOGIC_VECTOR (55 downto 0); indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0); indices_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000"; constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111"; constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal tmp_4_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_4_reg_134 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_load_new_reg_139 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_fu_113_p0 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_s_fu_113_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_s_fu_113_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_17_cast_fu_119_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0); signal tmp_s_fu_113_p00 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_s_fu_113_p10 : STD_LOGIC_VECTOR (23 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then indices_stride_load_new_reg_139 <= indices_datain(55 downto 48); tmp_4_reg_134 <= tmp_4_fu_92_p1; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , indices_rsp_empty_n) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => if (not((indices_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st4_fsm_3; else ap_NS_fsm <= ap_ST_st3_fsm_2; end if; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st4_fsm_3 = ap_CS_fsm))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= std_logic_vector(unsigned(tmp_17_cast_fu_119_p1) + unsigned(tmp_4_reg_134)); indices_address <= tmp_fu_81_p1(32 - 1 downto 0); indices_dataout <= ap_const_lv56_0; indices_req_din <= ap_const_logic_0; -- indices_req_write assign process. -- indices_req_write_assign_proc : process(ap_start, ap_CS_fsm) begin if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then indices_req_write <= ap_const_logic_1; else indices_req_write <= ap_const_logic_0; end if; end process; -- indices_rsp_read assign process. -- indices_rsp_read_assign_proc : process(ap_CS_fsm, indices_rsp_empty_n) begin if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then indices_rsp_read <= ap_const_logic_1; else indices_rsp_read <= ap_const_logic_0; end if; end process; indices_size <= ap_const_lv32_1; tmp_17_cast_fu_119_p1 <= std_logic_vector(resize(unsigned(tmp_s_fu_113_p2),32)); tmp_4_fu_92_p1 <= indices_datain(32 - 1 downto 0); tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64)); tmp_s_fu_113_p0 <= tmp_s_fu_113_p00(16 - 1 downto 0); tmp_s_fu_113_p00 <= std_logic_vector(resize(unsigned(i_sample),24)); tmp_s_fu_113_p1 <= tmp_s_fu_113_p10(8 - 1 downto 0); tmp_s_fu_113_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_139),24)); tmp_s_fu_113_p2 <= std_logic_vector(resize(unsigned(tmp_s_fu_113_p0) * unsigned(tmp_s_fu_113_p1), 24)); end behav;
lgpl-3.0
0b5ae29ca5a35a53a4402c9d69dbfdd8
0.574248
3.065208
false
false
false
false
dcliche/mdsynth
rtl/src/trap.vhd
1
10,706
--===========================================================================-- -- -- -- Synthesizable Hardware Breakpoint Trap -- -- -- --===========================================================================-- -- -- File name : trap.vhd -- -- Entity name : trap -- -- Purpose : Implements a 8 bit address and data hardware breakpoint comparator -- which generates an interrupt output on qualified match conditions -- -- Dependencies : ieee.Std_Logic_1164 -- ieee.std_logic_unsigned -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- Description : Register Memory Map -- -- Base + $00 - Address Comparitor High Byte -- Base + $01 - Address Comparitor Low byte -- Base + $02 - Data Comparitor -- Base + $03 - Control Comparitor -- Base + $04 - Address Qualifier High Byte -- Base + $05 - Address Qualifier Low byte -- Base + $06 - Data Qualifier -- Base + $07 - Control Qualifier -- -- Address, Data and Control signals -- must match in the Comparitor registers -- Matches are qualified by setting a bit -- in the Qualifier registers -- -- Control Comparitor / Control Qualify (write) -- b0 - r/w 1=read 0=write -- b1 - vma 1=valid 0=invalid -- b7 - irq output 1=match 0=mismatch -- -- Control Qualifier Read -- b7 - match flag -- -- Copyright (C) 2003 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- Version Author Date Description -- 0.1 John Kent 2003-05-05 Initial version -- 0.2 John kent 2010-08-09 Updated header & GPL information -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity trap is port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; rw : in std_logic; vma : in std_logic; addr : in std_logic_vector(15 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic ); end; architecture trap_arch of trap is -- -- Trap registers -- signal comp_addr_hi : std_logic_vector(7 downto 0); signal comp_addr_lo : std_logic_vector(7 downto 0); signal qual_addr_hi : std_logic_vector(7 downto 0); signal qual_addr_lo : std_logic_vector(7 downto 0); signal comp_data : std_logic_vector(7 downto 0); signal qual_data : std_logic_vector(7 downto 0); signal comp_ctrl : std_logic_vector(7 downto 0); signal qual_ctrl : std_logic_vector(7 downto 0); signal match_flag : std_logic; begin -------------------------------- -- -- write control registers -- -------------------------------- trap_write : process( clk, rst, cs, rw, addr, data_in, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl ) begin if clk'event and clk = '0' then if rst = '1' then comp_addr_hi <= "00000000"; comp_addr_lo <= "00000000"; comp_data <= "00000000"; comp_ctrl <= "00000000"; qual_addr_hi <= "00000000"; qual_addr_lo <= "00000000"; qual_data <= "00000000"; qual_ctrl <= "00000000"; elsif cs = '1' and rw = '0' then case addr(2 downto 0) is when "000" => comp_addr_hi <= data_in; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "001" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= data_in; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "010" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= data_in; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "011" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= data_in; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "100" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= data_in; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "101" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= data_in; qual_data <= qual_data; qual_ctrl <= qual_ctrl; when "110" => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= data_in; qual_ctrl <= qual_ctrl; -- when "111" => when others => comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= data_in; end case; else comp_addr_hi <= comp_addr_hi; comp_addr_lo <= comp_addr_lo; comp_data <= comp_data; comp_ctrl <= comp_ctrl; qual_addr_hi <= qual_addr_hi; qual_addr_lo <= qual_addr_lo; qual_data <= qual_data; qual_ctrl <= qual_ctrl; end if; end if; end process; -- -- trap data output mux -- trap_read : process( addr, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl, match_flag ) begin case addr(2 downto 0) is when "000" => data_out <= comp_addr_hi; when "001" => data_out <= comp_addr_lo; when "010" => data_out <= comp_data; when "011" => data_out <= comp_ctrl; when "100" => data_out <= qual_addr_hi; when "101" => data_out <= qual_addr_lo; when "110" => data_out <= qual_data; -- when "111" => when others => data_out(6 downto 0) <= qual_ctrl(6 downto 0); data_out(7) <= match_flag; end case; end process; -- -- Trap hardware -- trap_match : process( Clk, rst, cs, rw, addr, vma, match_flag, data_in, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl) variable match : std_logic; variable match_addr_hi : std_logic; variable match_addr_lo : std_logic; variable match_data : std_logic; variable match_ctrl : std_logic; begin match_addr_hi := ((comp_addr_hi(7) xor addr(15) ) and qual_addr_hi(7) ) or ((comp_addr_hi(6) xor addr(14) ) and qual_addr_hi(6) ) or ((comp_addr_hi(5) xor addr(13) ) and qual_addr_hi(5) ) or ((comp_addr_hi(4) xor addr(12) ) and qual_addr_hi(4) ) or ((comp_addr_hi(3) xor addr(11) ) and qual_addr_hi(3) ) or ((comp_addr_hi(2) xor addr(10) ) and qual_addr_hi(2) ) or ((comp_addr_hi(1) xor addr( 9) ) and qual_addr_hi(1) ) or ((comp_addr_hi(0) xor addr( 8) ) and qual_addr_hi(0) ); match_addr_lo := ((comp_addr_lo(7) xor addr( 7) ) and qual_addr_lo(7) ) or ((comp_addr_lo(6) xor addr( 6) ) and qual_addr_lo(6) ) or ((comp_addr_lo(5) xor addr( 5) ) and qual_addr_lo(5) ) or ((comp_addr_lo(4) xor addr( 4) ) and qual_addr_lo(4) ) or ((comp_addr_lo(3) xor addr( 3) ) and qual_addr_lo(3) ) or ((comp_addr_lo(2) xor addr( 2) ) and qual_addr_lo(2) ) or ((comp_addr_lo(1) xor addr( 1) ) and qual_addr_lo(1) ) or ((comp_addr_lo(0) xor addr( 0) ) and qual_addr_lo(0) ); match_data := ((comp_data(7) xor data_in(7)) and qual_data(7) ) or ((comp_data(6) xor data_in(6)) and qual_data(6) ) or ((comp_data(5) xor data_in(5)) and qual_data(5) ) or ((comp_data(4) xor data_in(4)) and qual_data(4) ) or ((comp_data(3) xor data_in(3)) and qual_data(3) ) or ((comp_data(2) xor data_in(2)) and qual_data(2) ) or ((comp_data(1) xor data_in(1)) and qual_data(1) ) or ((comp_data(0) xor data_in(0)) and qual_data(0) ); match_ctrl := ((comp_ctrl(0) xor rw ) and qual_ctrl(0) ) or ((comp_ctrl(1) xor vma ) and qual_ctrl(1) ); match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl); if rst = '1' then match_flag <= '0'; elsif clk'event and clk = '0' then if cs = '1' and rw = '0' then match_flag <= '0'; else if match = comp_ctrl(7) then match_flag <= '1'; end if; end if; end if; irq <= match_flag and qual_ctrl(7); end process; end trap_arch;
gpl-3.0
29eea322bf3643f4586386b14ae92c36
0.515038
3.259056
false
false
false
false
grwlf/vsim
vhdl_ct/ct00224.vhd
1
4,968
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00224 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.1 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00224(ARCH00224) -- ENT00224_Test_Bench(ARCH00224_Test_Bench) -- -- REVISION HISTORY: -- -- 10-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00224 is generic (G : integer) ; -- constant CG : integer := G+1; attribute attr : integer ; attribute attr of CG : constant is CG+1; -- end ENT00224 ; -- -- architecture ARCH00224 of ENT00224 is signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_st_rec3_vector : inout st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec3_vector(1).f1 <= transport c_st_rec3_vector_2(1).f1 ; s_st_rec3_vector(2).f2 <= transport c_st_rec3_vector_2(2).f2 after 10 ns ; wait until s_st_rec3_vector(2).f2 = c_st_rec3_vector_2(2).f2 ; Test_Report ( "ENT00224", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_rec3_vector(2).f2 = c_st_rec3_vector_2(2).f2 )) ; -- when 1 => s_st_rec3_vector(1).f1 <= transport c_st_rec3_vector_1(1).f1 ; s_st_rec3_vector(G).f2 <= transport c_st_rec3_vector_2(G).f2 after 10 ns ; wait until s_st_rec3_vector(G).f2 = c_st_rec3_vector_2(G).f2 ; Test_Report ( "ENT00224", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_rec3_vector(G).f2 = c_st_rec3_vector_2(G).f2 )) ; -- when 2 => s_st_rec3_vector(1).f1 <= transport c_st_rec3_vector_2(1).f1 ; s_st_rec3_vector(CG).f2 <= transport c_st_rec3_vector_2(CG).f2 after 10 ns ; wait until s_st_rec3_vector(CG).f2 = c_st_rec3_vector_2(CG).f2 ; Test_Report ( "ENT00224", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_rec3_vector(CG).f2 = c_st_rec3_vector_2(CG).f2 )) ; -- when 3 => s_st_rec3_vector(1).f1 <= transport c_st_rec3_vector_1(1).f1 ; s_st_rec3_vector(CG'Attr).f2 <= transport c_st_rec3_vector_2(CG'Attr).f2 after 10 ns ; wait until s_st_rec3_vector(CG'Attr).f2 = c_st_rec3_vector_2(CG'Attr).f2 ; Test_Report ( "ENT00224", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_rec3_vector(CG'Attr).f2 = c_st_rec3_vector_2(CG'Attr).f2 )) ; -- when others => wait ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time := 0 ns ; begin Proc1 ( s_st_rec3_vector , counter , correct , savtime , chk_st_rec3_vector ) ; end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Wait longest static prefix test completed", chk_st_rec3_vector = 3 ) ; end if ; end process PGEN_CHKP_1 ; -- -- end ARCH00224 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00224_Test_Bench is end ENT00224_Test_Bench ; -- -- architecture ARCH00224_Test_Bench of ENT00224_Test_Bench is begin L1: block component UUT generic (G : integer) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00224 ( ARCH00224 ) ; begin CIS1 : UUT generic map (lowb+2) ; end block L1 ; end ARCH00224_Test_Bench ;
gpl-3.0
5243fe5c55f84414b28d8521a19fd6c0
0.494767
3.407407
false
true
false
false
grwlf/vsim
vhdl/entity4.vhd
1
875
entity test is end entity test; entity unit1 is generic (n : integer := 100); port ( inum : in integer; oled : out integer); end entity unit1; architecture unit1_a of unit1 is signal a : integer := 0; begin oled <= inum + a + n; end architecture unit1_a; architecture test_arch of test is constant CYCLES : integer := 100; signal clk : integer := 0; signal i : integer := 0; signal o1 : integer; signal o2 : integer; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; u1:entity unit1(unit1_a) generic map (n=>200) port map(inum=>i, oled=>o1); u2:entity unit1(unit1_a) port map(inum=>i, oled=>o2); clk <= clk + 1 after 1 us; end architecture test_arch;
gpl-3.0
6a9cffe8647c96f04a1f096cd7d23486
0.617143
3.240741
false
true
false
false
grwlf/vsim
vhdl_ct/ct00349.vhd
1
39,275
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00349 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.2 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00349(ARCH00349) -- ENT00349_Test_Bench(ARCH00349_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00349 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; -- end ENT00349 ; -- -- architecture ARCH00349 of ENT00349 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; -- begin CHG1 : process ( s_st_boolean_vector ) variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns, -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_boolean_vector_select <= transport 2 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; st_boolean_vector_select <= transport 3 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_boolean_vector_savt <= transport Std.Standard.Now ; chk_st_boolean_vector <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb to highb-1) <= transport c_st_boolean_vector_2(lowb to highb-1) after 10 ns, c_st_boolean_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG2 : process ( s_st_severity_level_vector ) variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_severity_level_vector_select <= transport 2 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; st_severity_level_vector_select <= transport 3 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_severity_level_vector_savt <= transport Std.Standard.Now ; chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb to highb-1) <= transport c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, c_st_severity_level_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG3 : process ( s_st_string ) variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns, -- c_st_string_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_string_select <= transport 2 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; st_string_select <= transport 3 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_string_savt <= transport Std.Standard.Now ; chk_st_string <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; s_st_string_cnt <= transport s_st_string_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb-1 to highb-1) <= transport c_st_string_2(highb-1 to highb-1) after 10 ns, c_st_string_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG4 : process ( s_st_enum1_vector ) variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_vector_select <= transport 2 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; st_enum1_vector_select <= transport 3 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_enum1_vector_savt <= transport Std.Standard.Now ; chk_st_enum1_vector <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb-1 to highb-1) <= transport c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG5 : process ( s_st_integer_vector ) variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns, -- c_st_integer_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_integer_vector_select <= transport 2 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; st_integer_vector_select <= transport 3 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_integer_vector_savt <= transport Std.Standard.Now ; chk_st_integer_vector <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb to highb-1) <= transport c_st_integer_vector_2(lowb to highb-1) after 10 ns, c_st_integer_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG6 : process ( s_st_time_vector ) variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns, -- c_st_time_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_time_vector_select <= transport 2 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; st_time_vector_select <= transport 3 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_time_vector_savt <= transport Std.Standard.Now ; chk_st_time_vector <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb to highb-1) <= transport c_st_time_vector_2(lowb to highb-1) after 10 ns, c_st_time_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG7 : process ( s_st_real_vector ) variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real_vector_select <= transport 2 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; st_real_vector_select <= transport 3 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_real_vector_savt <= transport Std.Standard.Now ; chk_st_real_vector <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb-1 to highb-1) <= transport c_st_real_vector_2(highb-1 to highb-1) after 10 ns, c_st_real_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG8 : process ( s_st_rec1_vector ) variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb-1 to highb-1) <= transport c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG9 : process ( s_st_arr2_vector ) variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns, -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00349.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_vector_select <= transport 2 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; st_arr2_vector_select <= transport 3 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00349" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00349" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr2_vector_savt <= transport Std.Standard.Now ; chk_st_arr2_vector <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb to highb-1) <= transport c_st_arr2_vector_2(lowb to highb-1) after 10 ns, c_st_arr2_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ; -- end ARCH00349 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00349_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; -- end ENT00349_Test_Bench ; -- -- architecture ARCH00349_Test_Bench of ENT00349_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00349 ( ARCH00349 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector ) ; end block L1 ; end ARCH00349_Test_Bench ;
gpl-3.0
db37428af3616e75563b2ab1b910f6ae
0.532884
3.307368
false
true
false
false
grwlf/vsim
vhdl_ct/ct00391.vhd
1
69,677
-- NEED RESULT: ARCH00391.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P4: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P5: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P6: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P7: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P8: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391.P9: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00391: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P9: Inertial transactions completed entirely passed -- NEED RESULT: P8: Inertial transactions completed entirely passed -- NEED RESULT: P7: Inertial transactions completed entirely passed -- NEED RESULT: P6: Inertial transactions completed entirely passed -- NEED RESULT: P5: Inertial transactions completed entirely passed -- NEED RESULT: P4: Inertial transactions completed entirely passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00391 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.2 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00391(ARCH00391) -- ENT00391_Test_Bench(ARCH00391_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00391 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; -- end ENT00391 ; -- -- architecture ARCH00391 of ENT00391 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns, -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_boolean_vector_select <= transport 2 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; st_boolean_vector_select <= transport 3 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 4 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 5 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_boolean_vector_savt <= transport Std.Standard.Now ; chk_st_boolean_vector <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ; wait until (not s_st_boolean_vector(lowb to highb-1)'Quiet) and (s_st_boolean_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_boolean_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb to highb-1) <= c_st_boolean_vector_2(lowb to highb-1) after 10 ns, c_st_boolean_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3, -- c_st_boolean_vector_1(lowb to highb-1) after 100 ns when 4, -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 6 ; -- CHG2 : process variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_severity_level_vector_select <= transport 2 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; st_severity_level_vector_select <= transport 3 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 4 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 5 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_severity_level_vector_savt <= transport Std.Standard.Now ; chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt + 1 ; wait until (not s_st_severity_level_vector(lowb to highb-1)'Quiet) and (s_st_severity_level_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_severity_level_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb to highb-1) <= c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, c_st_severity_level_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3, -- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns when 4, -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 6 ; -- CHG3 : process variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns, -- c_st_string_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_string_select <= transport 2 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; st_string_select <= transport 3 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 4 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 5 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 6 ; -- Last transaction above is marked -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_string_savt <= transport Std.Standard.Now ; chk_st_string <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; s_st_string_cnt <= transport s_st_string_cnt + 1 ; wait until (not s_st_string(highb-1 to highb-1)'Quiet) and (s_st_string_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_st_string = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb-1 to highb-1) <= c_st_string_2(highb-1 to highb-1) after 10 ns, c_st_string_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_string_1(highb-1 to highb-1) after 5 ns when 3, -- c_st_string_1(highb-1 to highb-1) after 100 ns when 4, -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_string_1(highb-1 to highb-1) after 40 ns when 6 ; -- CHG4 : process variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P4" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_vector_select <= transport 2 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; st_enum1_vector_select <= transport 3 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 4 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 5 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_enum1_vector_savt <= transport Std.Standard.Now ; chk_st_enum1_vector <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ; wait until (not s_st_enum1_vector(highb-1 to highb-1)'Quiet) and (s_st_enum1_vector_savt /= Std.Standard.Now) ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions completed entirely", chk_st_enum1_vector = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb-1 to highb-1) <= c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3, -- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns when 4, -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 6 ; -- CHG5 : process variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns, -- c_st_integer_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P5" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_integer_vector_select <= transport 2 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; st_integer_vector_select <= transport 3 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 4 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 5 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_integer_vector_savt <= transport Std.Standard.Now ; chk_st_integer_vector <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ; wait until (not s_st_integer_vector(lowb to highb-1)'Quiet) and (s_st_integer_vector_savt /= Std.Standard.Now) ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions completed entirely", chk_st_integer_vector = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb to highb-1) <= c_st_integer_vector_2(lowb to highb-1) after 10 ns, c_st_integer_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3, -- c_st_integer_vector_1(lowb to highb-1) after 100 ns when 4, -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_integer_vector_1(lowb to highb-1) after 40 ns when 6 ; -- CHG6 : process variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns, -- c_st_time_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P6" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_time_vector_select <= transport 2 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; st_time_vector_select <= transport 3 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 4 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 5 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_time_vector_savt <= transport Std.Standard.Now ; chk_st_time_vector <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ; wait until (not s_st_time_vector(lowb to highb-1)'Quiet) and (s_st_time_vector_savt /= Std.Standard.Now) ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions completed entirely", chk_st_time_vector = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb to highb-1) <= c_st_time_vector_2(lowb to highb-1) after 10 ns, c_st_time_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_time_vector_1(lowb to highb-1) after 5 ns when 3, -- c_st_time_vector_1(lowb to highb-1) after 100 ns when 4, -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_time_vector_1(lowb to highb-1) after 40 ns when 6 ; -- CHG7 : process variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P7" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real_vector_select <= transport 2 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; st_real_vector_select <= transport 3 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 4 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 5 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_real_vector_savt <= transport Std.Standard.Now ; chk_st_real_vector <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ; wait until (not s_st_real_vector(highb-1 to highb-1)'Quiet) and (s_st_real_vector_savt /= Std.Standard.Now) ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions completed entirely", chk_st_real_vector = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb-1 to highb-1) <= c_st_real_vector_2(highb-1 to highb-1) after 10 ns, c_st_real_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3, -- c_st_real_vector_1(highb-1 to highb-1) after 100 ns when 4, -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 6 ; -- CHG8 : process variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P8" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 4 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 5 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; wait until (not s_st_rec1_vector(highb-1 to highb-1)'Quiet) and (s_st_rec1_vector_savt /= Std.Standard.Now) ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions completed entirely", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb-1 to highb-1) <= c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3, -- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns when 4, -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 6 ; -- CHG9 : process variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns, -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391.P9" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_vector_select <= transport 2 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; st_arr2_vector_select <= transport 3 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 4 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 5 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00391" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_vector_savt <= transport Std.Standard.Now ; chk_st_arr2_vector <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ; wait until (not s_st_arr2_vector(lowb to highb-1)'Quiet) and (s_st_arr2_vector_savt /= Std.Standard.Now) ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions completed entirely", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb to highb-1) <= c_st_arr2_vector_2(lowb to highb-1) after 10 ns, c_st_arr2_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3, -- c_st_arr2_vector_1(lowb to highb-1) after 100 ns when 4, -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 6 ; -- end ARCH00391 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00391_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; -- end ENT00391_Test_Bench ; -- -- architecture ARCH00391_Test_Bench of ENT00391_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00391 ( ARCH00391 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector ) ; end block L1 ; end ARCH00391_Test_Bench ;
gpl-3.0
3dfc3a62646e4f6e72ccca5f8ca10e78
0.527663
3.403028
false
false
false
false
wsoltys/AtomFpga
src/ROM/SDROM23ROM.vhd
1
152,362
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; --use UNISIM.Vcomponents.all; entity SDROM is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of SDROM is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"2C"; when x"001" => DATA <= x"01"; when x"002" => DATA <= x"B0"; when x"003" => DATA <= x"70"; when x"004" => DATA <= x"03"; when x"005" => DATA <= x"4C"; when x"006" => DATA <= x"B2"; when x"007" => DATA <= x"C2"; when x"008" => DATA <= x"98"; when x"009" => DATA <= x"48"; when x"00A" => DATA <= x"8A"; when x"00B" => DATA <= x"48"; when x"00C" => DATA <= x"A2"; when x"00D" => DATA <= x"00"; when x"00E" => DATA <= x"8E"; when x"00F" => DATA <= x"CA"; when x"010" => DATA <= x"03"; when x"011" => DATA <= x"A9"; when x"012" => DATA <= x"2B"; when x"013" => DATA <= x"8D"; when x"014" => DATA <= x"0B"; when x"015" => DATA <= x"80"; when x"016" => DATA <= x"BD"; when x"017" => DATA <= x"8A"; when x"018" => DATA <= x"EB"; when x"019" => DATA <= x"29"; when x"01A" => DATA <= x"BF"; when x"01B" => DATA <= x"9D"; when x"01C" => DATA <= x"0D"; when x"01D" => DATA <= x"80"; when x"01E" => DATA <= x"E8"; when x"01F" => DATA <= x"C9"; when x"020" => DATA <= x"20"; when x"021" => DATA <= x"D0"; when x"022" => DATA <= x"F3"; when x"023" => DATA <= x"20"; when x"024" => DATA <= x"D6"; when x"025" => DATA <= x"E7"; when x"026" => DATA <= x"2C"; when x"027" => DATA <= x"01"; when x"028" => DATA <= x"B0"; when x"029" => DATA <= x"30"; when x"02A" => DATA <= x"0A"; when x"02B" => DATA <= x"A9"; when x"02C" => DATA <= x"3C"; when x"02D" => DATA <= x"8D"; when x"02E" => DATA <= x"0A"; when x"02F" => DATA <= x"02"; when x"030" => DATA <= x"A9"; when x"031" => DATA <= x"E0"; when x"032" => DATA <= x"8D"; when x"033" => DATA <= x"0B"; when x"034" => DATA <= x"02"; when x"035" => DATA <= x"68"; when x"036" => DATA <= x"AA"; when x"037" => DATA <= x"68"; when x"038" => DATA <= x"A8"; when x"039" => DATA <= x"4C"; when x"03A" => DATA <= x"B2"; when x"03B" => DATA <= x"C2"; when x"03C" => DATA <= x"08"; when x"03D" => DATA <= x"D8"; when x"03E" => DATA <= x"86"; when x"03F" => DATA <= x"E4"; when x"040" => DATA <= x"84"; when x"041" => DATA <= x"E5"; when x"042" => DATA <= x"AE"; when x"043" => DATA <= x"CA"; when x"044" => DATA <= x"03"; when x"045" => DATA <= x"BD"; when x"046" => DATA <= x"66"; when x"047" => DATA <= x"E0"; when x"048" => DATA <= x"C9"; when x"049" => DATA <= x"0D"; when x"04A" => DATA <= x"F0"; when x"04B" => DATA <= x"0A"; when x"04C" => DATA <= x"E8"; when x"04D" => DATA <= x"8E"; when x"04E" => DATA <= x"CA"; when x"04F" => DATA <= x"03"; when x"050" => DATA <= x"A6"; when x"051" => DATA <= x"E4"; when x"052" => DATA <= x"A4"; when x"053" => DATA <= x"E5"; when x"054" => DATA <= x"28"; when x"055" => DATA <= x"60"; when x"056" => DATA <= x"A9"; when x"057" => DATA <= x"94"; when x"058" => DATA <= x"8D"; when x"059" => DATA <= x"0A"; when x"05A" => DATA <= x"02"; when x"05B" => DATA <= x"A9"; when x"05C" => DATA <= x"FE"; when x"05D" => DATA <= x"8D"; when x"05E" => DATA <= x"0B"; when x"05F" => DATA <= x"02"; when x"060" => DATA <= x"A9"; when x"061" => DATA <= x"0D"; when x"062" => DATA <= x"48"; when x"063" => DATA <= x"4C"; when x"064" => DATA <= x"5C"; when x"065" => DATA <= x"FE"; when x"066" => DATA <= x"2A"; when x"067" => DATA <= x"4D"; when x"068" => DATA <= x"45"; when x"069" => DATA <= x"4E"; when x"06A" => DATA <= x"55"; when x"06B" => DATA <= x"0D"; when x"06C" => DATA <= x"00"; when x"06D" => DATA <= x"6C"; when x"06E" => DATA <= x"52"; when x"06F" => DATA <= x"00"; when x"070" => DATA <= x"A2"; when x"071" => DATA <= x"FF"; when x"072" => DATA <= x"D8"; when x"073" => DATA <= x"A0"; when x"074" => DATA <= x"00"; when x"075" => DATA <= x"20"; when x"076" => DATA <= x"76"; when x"077" => DATA <= x"F8"; when x"078" => DATA <= x"88"; when x"079" => DATA <= x"C8"; when x"07A" => DATA <= x"E8"; when x"07B" => DATA <= x"BD"; when x"07C" => DATA <= x"CD"; when x"07D" => DATA <= x"E0"; when x"07E" => DATA <= x"30"; when x"07F" => DATA <= x"18"; when x"080" => DATA <= x"D9"; when x"081" => DATA <= x"00"; when x"082" => DATA <= x"01"; when x"083" => DATA <= x"F0"; when x"084" => DATA <= x"F4"; when x"085" => DATA <= x"CA"; when x"086" => DATA <= x"E8"; when x"087" => DATA <= x"BD"; when x"088" => DATA <= x"CD"; when x"089" => DATA <= x"E0"; when x"08A" => DATA <= x"10"; when x"08B" => DATA <= x"FA"; when x"08C" => DATA <= x"E8"; when x"08D" => DATA <= x"B9"; when x"08E" => DATA <= x"00"; when x"08F" => DATA <= x"01"; when x"090" => DATA <= x"C9"; when x"091" => DATA <= x"2E"; when x"092" => DATA <= x"D0"; when x"093" => DATA <= x"DF"; when x"094" => DATA <= x"C8"; when x"095" => DATA <= x"CA"; when x"096" => DATA <= x"B0"; when x"097" => DATA <= x"E3"; when x"098" => DATA <= x"84"; when x"099" => DATA <= x"9A"; when x"09A" => DATA <= x"A4"; when x"09B" => DATA <= x"03"; when x"09C" => DATA <= x"84"; when x"09D" => DATA <= x"D5"; when x"09E" => DATA <= x"A4"; when x"09F" => DATA <= x"05"; when x"0A0" => DATA <= x"84"; when x"0A1" => DATA <= x"D6"; when x"0A2" => DATA <= x"A4"; when x"0A3" => DATA <= x"06"; when x"0A4" => DATA <= x"84"; when x"0A5" => DATA <= x"D7"; when x"0A6" => DATA <= x"A0"; when x"0A7" => DATA <= x"00"; when x"0A8" => DATA <= x"84"; when x"0A9" => DATA <= x"05"; when x"0AA" => DATA <= x"A0"; when x"0AB" => DATA <= x"01"; when x"0AC" => DATA <= x"84"; when x"0AD" => DATA <= x"06"; when x"0AE" => DATA <= x"A4"; when x"0AF" => DATA <= x"9A"; when x"0B0" => DATA <= x"84"; when x"0B1" => DATA <= x"03"; when x"0B2" => DATA <= x"85"; when x"0B3" => DATA <= x"53"; when x"0B4" => DATA <= x"BD"; when x"0B5" => DATA <= x"CE"; when x"0B6" => DATA <= x"E0"; when x"0B7" => DATA <= x"85"; when x"0B8" => DATA <= x"52"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"6D"; when x"0BB" => DATA <= x"E0"; when x"0BC" => DATA <= x"A4"; when x"0BD" => DATA <= x"D6"; when x"0BE" => DATA <= x"84"; when x"0BF" => DATA <= x"05"; when x"0C0" => DATA <= x"A4"; when x"0C1" => DATA <= x"D7"; when x"0C2" => DATA <= x"84"; when x"0C3" => DATA <= x"06"; when x"0C4" => DATA <= x"A4"; when x"0C5" => DATA <= x"D5"; when x"0C6" => DATA <= x"84"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"A9"; when x"0C9" => DATA <= x"0D"; when x"0CA" => DATA <= x"91"; when x"0CB" => DATA <= x"05"; when x"0CC" => DATA <= x"60"; when x"0CD" => DATA <= x"43"; when x"0CE" => DATA <= x"41"; when x"0CF" => DATA <= x"54"; when x"0D0" => DATA <= x"E1"; when x"0D1" => DATA <= x"8A"; when x"0D2" => DATA <= x"44"; when x"0D3" => DATA <= x"45"; when x"0D4" => DATA <= x"4C"; when x"0D5" => DATA <= x"45"; when x"0D6" => DATA <= x"54"; when x"0D7" => DATA <= x"45"; when x"0D8" => DATA <= x"E2"; when x"0D9" => DATA <= x"B7"; when x"0DA" => DATA <= x"44"; when x"0DB" => DATA <= x"49"; when x"0DC" => DATA <= x"52"; when x"0DD" => DATA <= x"E2"; when x"0DE" => DATA <= x"DA"; when x"0DF" => DATA <= x"44"; when x"0E0" => DATA <= x"52"; when x"0E1" => DATA <= x"49"; when x"0E2" => DATA <= x"56"; when x"0E3" => DATA <= x"45"; when x"0E4" => DATA <= x"E2"; when x"0E5" => DATA <= x"E0"; when x"0E6" => DATA <= x"49"; when x"0E7" => DATA <= x"4E"; when x"0E8" => DATA <= x"46"; when x"0E9" => DATA <= x"4F"; when x"0EA" => DATA <= x"E2"; when x"0EB" => DATA <= x"F5"; when x"0EC" => DATA <= x"49"; when x"0ED" => DATA <= x"4E"; when x"0EE" => DATA <= x"46"; when x"0EF" => DATA <= x"41"; when x"0F0" => DATA <= x"4C"; when x"0F1" => DATA <= x"4C"; when x"0F2" => DATA <= x"E2"; when x"0F3" => DATA <= x"FB"; when x"0F4" => DATA <= x"4C"; when x"0F5" => DATA <= x"4F"; when x"0F6" => DATA <= x"41"; when x"0F7" => DATA <= x"44"; when x"0F8" => DATA <= x"E3"; when x"0F9" => DATA <= x"12"; when x"0FA" => DATA <= x"4C"; when x"0FB" => DATA <= x"4F"; when x"0FC" => DATA <= x"43"; when x"0FD" => DATA <= x"4B"; when x"0FE" => DATA <= x"E3"; when x"0FF" => DATA <= x"BD"; when x"100" => DATA <= x"4D"; when x"101" => DATA <= x"4F"; when x"102" => DATA <= x"4E"; when x"103" => DATA <= x"E3"; when x"104" => DATA <= x"C1"; when x"105" => DATA <= x"4E"; when x"106" => DATA <= x"4F"; when x"107" => DATA <= x"4D"; when x"108" => DATA <= x"4F"; when x"109" => DATA <= x"4E"; when x"10A" => DATA <= x"E3"; when x"10B" => DATA <= x"CB"; when x"10C" => DATA <= x"52"; when x"10D" => DATA <= x"55"; when x"10E" => DATA <= x"4E"; when x"10F" => DATA <= x"E3"; when x"110" => DATA <= x"D0"; when x"111" => DATA <= x"53"; when x"112" => DATA <= x"41"; when x"113" => DATA <= x"56"; when x"114" => DATA <= x"45"; when x"115" => DATA <= x"E3"; when x"116" => DATA <= x"DB"; when x"117" => DATA <= x"53"; when x"118" => DATA <= x"45"; when x"119" => DATA <= x"54"; when x"11A" => DATA <= x"E5"; when x"11B" => DATA <= x"79"; when x"11C" => DATA <= x"54"; when x"11D" => DATA <= x"49"; when x"11E" => DATA <= x"54"; when x"11F" => DATA <= x"4C"; when x"120" => DATA <= x"45"; when x"121" => DATA <= x"E5"; when x"122" => DATA <= x"87"; when x"123" => DATA <= x"55"; when x"124" => DATA <= x"4E"; when x"125" => DATA <= x"4C"; when x"126" => DATA <= x"4F"; when x"127" => DATA <= x"43"; when x"128" => DATA <= x"4B"; when x"129" => DATA <= x"E5"; when x"12A" => DATA <= x"F1"; when x"12B" => DATA <= x"55"; when x"12C" => DATA <= x"53"; when x"12D" => DATA <= x"45"; when x"12E" => DATA <= x"E6"; when x"12F" => DATA <= x"10"; when x"130" => DATA <= x"44"; when x"131" => DATA <= x"49"; when x"132" => DATA <= x"4E"; when x"133" => DATA <= x"E8"; when x"134" => DATA <= x"31"; when x"135" => DATA <= x"44"; when x"136" => DATA <= x"43"; when x"137" => DATA <= x"41"; when x"138" => DATA <= x"54"; when x"139" => DATA <= x"E8"; when x"13A" => DATA <= x"94"; when x"13B" => DATA <= x"44"; when x"13C" => DATA <= x"44"; when x"13D" => DATA <= x"49"; when x"13E" => DATA <= x"53"; when x"13F" => DATA <= x"4B"; when x"140" => DATA <= x"53"; when x"141" => DATA <= x"E9"; when x"142" => DATA <= x"3F"; when x"143" => DATA <= x"44"; when x"144" => DATA <= x"50"; when x"145" => DATA <= x"52"; when x"146" => DATA <= x"4F"; when x"147" => DATA <= x"54"; when x"148" => DATA <= x"E9"; when x"149" => DATA <= x"85"; when x"14A" => DATA <= x"44"; when x"14B" => DATA <= x"55"; when x"14C" => DATA <= x"4E"; when x"14D" => DATA <= x"50"; when x"14E" => DATA <= x"52"; when x"14F" => DATA <= x"4F"; when x"150" => DATA <= x"54"; when x"151" => DATA <= x"E9"; when x"152" => DATA <= x"9D"; when x"153" => DATA <= x"44"; when x"154" => DATA <= x"46"; when x"155" => DATA <= x"52"; when x"156" => DATA <= x"45"; when x"157" => DATA <= x"45"; when x"158" => DATA <= x"E9"; when x"159" => DATA <= x"B5"; when x"15A" => DATA <= x"44"; when x"15B" => DATA <= x"4B"; when x"15C" => DATA <= x"49"; when x"15D" => DATA <= x"4C"; when x"15E" => DATA <= x"4C"; when x"15F" => DATA <= x"EA"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"44"; when x"162" => DATA <= x"52"; when x"163" => DATA <= x"45"; when x"164" => DATA <= x"53"; when x"165" => DATA <= x"54"; when x"166" => DATA <= x"4F"; when x"167" => DATA <= x"52"; when x"168" => DATA <= x"45"; when x"169" => DATA <= x"EA"; when x"16A" => DATA <= x"61"; when x"16B" => DATA <= x"44"; when x"16C" => DATA <= x"4E"; when x"16D" => DATA <= x"45"; when x"16E" => DATA <= x"57"; when x"16F" => DATA <= x"EA"; when x"170" => DATA <= x"76"; when x"171" => DATA <= x"44"; when x"172" => DATA <= x"46"; when x"173" => DATA <= x"4F"; when x"174" => DATA <= x"52"; when x"175" => DATA <= x"4D"; when x"176" => DATA <= x"EA"; when x"177" => DATA <= x"EE"; when x"178" => DATA <= x"44"; when x"179" => DATA <= x"4F"; when x"17A" => DATA <= x"4E"; when x"17B" => DATA <= x"42"; when x"17C" => DATA <= x"4F"; when x"17D" => DATA <= x"4F"; when x"17E" => DATA <= x"54"; when x"17F" => DATA <= x"EB"; when x"180" => DATA <= x"64"; when x"181" => DATA <= x"44"; when x"182" => DATA <= x"48"; when x"183" => DATA <= x"45"; when x"184" => DATA <= x"4C"; when x"185" => DATA <= x"50"; when x"186" => DATA <= x"EB"; when x"187" => DATA <= x"81"; when x"188" => DATA <= x"E6"; when x"189" => DATA <= x"20"; when x"18A" => DATA <= x"20"; when x"18B" => DATA <= x"DA"; when x"18C" => DATA <= x"E2"; when x"18D" => DATA <= x"A2"; when x"18E" => DATA <= x"00"; when x"18F" => DATA <= x"86"; when x"190" => DATA <= x"B6"; when x"191" => DATA <= x"BD"; when x"192" => DATA <= x"00"; when x"193" => DATA <= x"20"; when x"194" => DATA <= x"E0"; when x"195" => DATA <= x"08"; when x"196" => DATA <= x"90"; when x"197" => DATA <= x"03"; when x"198" => DATA <= x"BD"; when x"199" => DATA <= x"F8"; when x"19A" => DATA <= x"20"; when x"19B" => DATA <= x"20"; when x"19C" => DATA <= x"F4"; when x"19D" => DATA <= x"FF"; when x"19E" => DATA <= x"E8"; when x"19F" => DATA <= x"E0"; when x"1A0" => DATA <= x"0D"; when x"1A1" => DATA <= x"D0"; when x"1A2" => DATA <= x"EE"; when x"1A3" => DATA <= x"20"; when x"1A4" => DATA <= x"D1"; when x"1A5" => DATA <= x"F7"; when x"1A6" => DATA <= x"20"; when x"1A7" => DATA <= x"44"; when x"1A8" => DATA <= x"52"; when x"1A9" => DATA <= x"3A"; when x"1AA" => DATA <= x"EA"; when x"1AB" => DATA <= x"A5"; when x"1AC" => DATA <= x"EE"; when x"1AD" => DATA <= x"20"; when x"1AE" => DATA <= x"0B"; when x"1AF" => DATA <= x"F8"; when x"1B0" => DATA <= x"20"; when x"1B1" => DATA <= x"D1"; when x"1B2" => DATA <= x"F7"; when x"1B3" => DATA <= x"20"; when x"1B4" => DATA <= x"51"; when x"1B5" => DATA <= x"3A"; when x"1B6" => DATA <= x"EA"; when x"1B7" => DATA <= x"A5"; when x"1B8" => DATA <= x"AC"; when x"1B9" => DATA <= x"20"; when x"1BA" => DATA <= x"F4"; when x"1BB" => DATA <= x"FF"; when x"1BC" => DATA <= x"20"; when x"1BD" => DATA <= x"D1"; when x"1BE" => DATA <= x"F7"; when x"1BF" => DATA <= x"20"; when x"1C0" => DATA <= x"44"; when x"1C1" => DATA <= x"53"; when x"1C2" => DATA <= x"4B"; when x"1C3" => DATA <= x"3A"; when x"1C4" => DATA <= x"EA"; when x"1C5" => DATA <= x"A5"; when x"1C6" => DATA <= x"EE"; when x"1C7" => DATA <= x"0A"; when x"1C8" => DATA <= x"A8"; when x"1C9" => DATA <= x"B6"; when x"1CA" => DATA <= x"F0"; when x"1CB" => DATA <= x"B9"; when x"1CC" => DATA <= x"F1"; when x"1CD" => DATA <= x"00"; when x"1CE" => DATA <= x"A8"; when x"1CF" => DATA <= x"20"; when x"1D0" => DATA <= x"88"; when x"1D1" => DATA <= x"ED"; when x"1D2" => DATA <= x"A0"; when x"1D3" => DATA <= x"00"; when x"1D4" => DATA <= x"20"; when x"1D5" => DATA <= x"ED"; when x"1D6" => DATA <= x"E1"; when x"1D7" => DATA <= x"90"; when x"1D8" => DATA <= x"4A"; when x"1D9" => DATA <= x"20"; when x"1DA" => DATA <= x"15"; when x"1DB" => DATA <= x"EE"; when x"1DC" => DATA <= x"B9"; when x"1DD" => DATA <= x"08"; when x"1DE" => DATA <= x"20"; when x"1DF" => DATA <= x"29"; when x"1E0" => DATA <= x"7F"; when x"1E1" => DATA <= x"99"; when x"1E2" => DATA <= x"08"; when x"1E3" => DATA <= x"20"; when x"1E4" => DATA <= x"98"; when x"1E5" => DATA <= x"D0"; when x"1E6" => DATA <= x"F2"; when x"1E7" => DATA <= x"4C"; when x"1E8" => DATA <= x"ED"; when x"1E9" => DATA <= x"FF"; when x"1EA" => DATA <= x"20"; when x"1EB" => DATA <= x"0C"; when x"1EC" => DATA <= x"EE"; when x"1ED" => DATA <= x"CC"; when x"1EE" => DATA <= x"05"; when x"1EF" => DATA <= x"21"; when x"1F0" => DATA <= x"B0"; when x"1F1" => DATA <= x"05"; when x"1F2" => DATA <= x"B9"; when x"1F3" => DATA <= x"08"; when x"1F4" => DATA <= x"20"; when x"1F5" => DATA <= x"30"; when x"1F6" => DATA <= x"F3"; when x"1F7" => DATA <= x"60"; when x"1F8" => DATA <= x"A4"; when x"1F9" => DATA <= x"B8"; when x"1FA" => DATA <= x"F0"; when x"1FB" => DATA <= x"05"; when x"1FC" => DATA <= x"20"; when x"1FD" => DATA <= x"ED"; when x"1FE" => DATA <= x"FF"; when x"1FF" => DATA <= x"A0"; when x"200" => DATA <= x"FF"; when x"201" => DATA <= x"C8"; when x"202" => DATA <= x"84"; when x"203" => DATA <= x"B8"; when x"204" => DATA <= x"20"; when x"205" => DATA <= x"03"; when x"206" => DATA <= x"EE"; when x"207" => DATA <= x"A9"; when x"208" => DATA <= x"23"; when x"209" => DATA <= x"A4"; when x"20A" => DATA <= x"B7"; when x"20B" => DATA <= x"BE"; when x"20C" => DATA <= x"0F"; when x"20D" => DATA <= x"20"; when x"20E" => DATA <= x"30"; when x"20F" => DATA <= x"02"; when x"210" => DATA <= x"A9"; when x"211" => DATA <= x"20"; when x"212" => DATA <= x"20"; when x"213" => DATA <= x"F4"; when x"214" => DATA <= x"FF"; when x"215" => DATA <= x"A2"; when x"216" => DATA <= x"00"; when x"217" => DATA <= x"B5"; when x"218" => DATA <= x"AE"; when x"219" => DATA <= x"20"; when x"21A" => DATA <= x"F4"; when x"21B" => DATA <= x"FF"; when x"21C" => DATA <= x"E8"; when x"21D" => DATA <= x"E0"; when x"21E" => DATA <= x"07"; when x"21F" => DATA <= x"D0"; when x"220" => DATA <= x"F6"; when x"221" => DATA <= x"F0"; when x"222" => DATA <= x"AF"; when x"223" => DATA <= x"84"; when x"224" => DATA <= x"B7"; when x"225" => DATA <= x"A2"; when x"226" => DATA <= x"00"; when x"227" => DATA <= x"B9"; when x"228" => DATA <= x"08"; when x"229" => DATA <= x"20"; when x"22A" => DATA <= x"29"; when x"22B" => DATA <= x"7F"; when x"22C" => DATA <= x"95"; when x"22D" => DATA <= x"AE"; when x"22E" => DATA <= x"C8"; when x"22F" => DATA <= x"E8"; when x"230" => DATA <= x"E0"; when x"231" => DATA <= x"08"; when x"232" => DATA <= x"D0"; when x"233" => DATA <= x"F3"; when x"234" => DATA <= x"20"; when x"235" => DATA <= x"ED"; when x"236" => DATA <= x"E1"; when x"237" => DATA <= x"B0"; when x"238" => DATA <= x"1D"; when x"239" => DATA <= x"A2"; when x"23A" => DATA <= x"06"; when x"23B" => DATA <= x"38"; when x"23C" => DATA <= x"B9"; when x"23D" => DATA <= x"0E"; when x"23E" => DATA <= x"20"; when x"23F" => DATA <= x"F5"; when x"240" => DATA <= x"AE"; when x"241" => DATA <= x"88"; when x"242" => DATA <= x"CA"; when x"243" => DATA <= x"10"; when x"244" => DATA <= x"F7"; when x"245" => DATA <= x"20"; when x"246" => DATA <= x"0D"; when x"247" => DATA <= x"EE"; when x"248" => DATA <= x"B9"; when x"249" => DATA <= x"0F"; when x"24A" => DATA <= x"20"; when x"24B" => DATA <= x"29"; when x"24C" => DATA <= x"7F"; when x"24D" => DATA <= x"E5"; when x"24E" => DATA <= x"B5"; when x"24F" => DATA <= x"90"; when x"250" => DATA <= x"D2"; when x"251" => DATA <= x"20"; when x"252" => DATA <= x"0C"; when x"253" => DATA <= x"EE"; when x"254" => DATA <= x"B0"; when x"255" => DATA <= x"DE"; when x"256" => DATA <= x"A4"; when x"257" => DATA <= x"B7"; when x"258" => DATA <= x"B9"; when x"259" => DATA <= x"08"; when x"25A" => DATA <= x"20"; when x"25B" => DATA <= x"09"; when x"25C" => DATA <= x"80"; when x"25D" => DATA <= x"99"; when x"25E" => DATA <= x"08"; when x"25F" => DATA <= x"20"; when x"260" => DATA <= x"A5"; when x"261" => DATA <= x"B5"; when x"262" => DATA <= x"C5"; when x"263" => DATA <= x"B6"; when x"264" => DATA <= x"F0"; when x"265" => DATA <= x"92"; when x"266" => DATA <= x"85"; when x"267" => DATA <= x"B6"; when x"268" => DATA <= x"20"; when x"269" => DATA <= x"ED"; when x"26A" => DATA <= x"FF"; when x"26B" => DATA <= x"A5"; when x"26C" => DATA <= x"B5"; when x"26D" => DATA <= x"20"; when x"26E" => DATA <= x"F4"; when x"26F" => DATA <= x"FF"; when x"270" => DATA <= x"A9"; when x"271" => DATA <= x"3A"; when x"272" => DATA <= x"20"; when x"273" => DATA <= x"F4"; when x"274" => DATA <= x"FF"; when x"275" => DATA <= x"A0"; when x"276" => DATA <= x"04"; when x"277" => DATA <= x"20"; when x"278" => DATA <= x"05"; when x"279" => DATA <= x"EE"; when x"27A" => DATA <= x"84"; when x"27B" => DATA <= x"B8"; when x"27C" => DATA <= x"F0"; when x"27D" => DATA <= x"89"; when x"27E" => DATA <= x"B9"; when x"27F" => DATA <= x"0E"; when x"280" => DATA <= x"21"; when x"281" => DATA <= x"20"; when x"282" => DATA <= x"1F"; when x"283" => DATA <= x"EE"; when x"284" => DATA <= x"85"; when x"285" => DATA <= x"A2"; when x"286" => DATA <= x"18"; when x"287" => DATA <= x"A9"; when x"288" => DATA <= x"FF"; when x"289" => DATA <= x"79"; when x"28A" => DATA <= x"0C"; when x"28B" => DATA <= x"21"; when x"28C" => DATA <= x"B9"; when x"28D" => DATA <= x"0F"; when x"28E" => DATA <= x"21"; when x"28F" => DATA <= x"79"; when x"290" => DATA <= x"0D"; when x"291" => DATA <= x"21"; when x"292" => DATA <= x"85"; when x"293" => DATA <= x"A3"; when x"294" => DATA <= x"B9"; when x"295" => DATA <= x"0E"; when x"296" => DATA <= x"21"; when x"297" => DATA <= x"29"; when x"298" => DATA <= x"0F"; when x"299" => DATA <= x"65"; when x"29A" => DATA <= x"A2"; when x"29B" => DATA <= x"85"; when x"29C" => DATA <= x"A2"; when x"29D" => DATA <= x"38"; when x"29E" => DATA <= x"B9"; when x"29F" => DATA <= x"07"; when x"2A0" => DATA <= x"21"; when x"2A1" => DATA <= x"E5"; when x"2A2" => DATA <= x"A3"; when x"2A3" => DATA <= x"48"; when x"2A4" => DATA <= x"B9"; when x"2A5" => DATA <= x"06"; when x"2A6" => DATA <= x"21"; when x"2A7" => DATA <= x"29"; when x"2A8" => DATA <= x"0F"; when x"2A9" => DATA <= x"E5"; when x"2AA" => DATA <= x"A2"; when x"2AB" => DATA <= x"AA"; when x"2AC" => DATA <= x"A9"; when x"2AD" => DATA <= x"00"; when x"2AE" => DATA <= x"C5"; when x"2AF" => DATA <= x"A0"; when x"2B0" => DATA <= x"68"; when x"2B1" => DATA <= x"E5"; when x"2B2" => DATA <= x"A1"; when x"2B3" => DATA <= x"8A"; when x"2B4" => DATA <= x"E9"; when x"2B5" => DATA <= x"00"; when x"2B6" => DATA <= x"60"; when x"2B7" => DATA <= x"20"; when x"2B8" => DATA <= x"E4"; when x"2B9" => DATA <= x"ED"; when x"2BA" => DATA <= x"B9"; when x"2BB" => DATA <= x"0F"; when x"2BC" => DATA <= x"20"; when x"2BD" => DATA <= x"30"; when x"2BE" => DATA <= x"11"; when x"2BF" => DATA <= x"20"; when x"2C0" => DATA <= x"FA"; when x"2C1" => DATA <= x"E6"; when x"2C2" => DATA <= x"20"; when x"2C3" => DATA <= x"63"; when x"2C4" => DATA <= x"E6"; when x"2C5" => DATA <= x"A4"; when x"2C6" => DATA <= x"9A"; when x"2C7" => DATA <= x"20"; when x"2C8" => DATA <= x"AD"; when x"2C9" => DATA <= x"E7"; when x"2CA" => DATA <= x"20"; when x"2CB" => DATA <= x"7B"; when x"2CC" => DATA <= x"EC"; when x"2CD" => DATA <= x"4C"; when x"2CE" => DATA <= x"56"; when x"2CF" => DATA <= x"E3"; when x"2D0" => DATA <= x"20"; when x"2D1" => DATA <= x"D1"; when x"2D2" => DATA <= x"F7"; when x"2D3" => DATA <= x"50"; when x"2D4" => DATA <= x"52"; when x"2D5" => DATA <= x"4F"; when x"2D6" => DATA <= x"54"; when x"2D7" => DATA <= x"3F"; when x"2D8" => DATA <= x"EA"; when x"2D9" => DATA <= x"00"; when x"2DA" => DATA <= x"20"; when x"2DB" => DATA <= x"E0"; when x"2DC" => DATA <= x"E2"; when x"2DD" => DATA <= x"4C"; when x"2DE" => DATA <= x"2D"; when x"2DF" => DATA <= x"EC"; when x"2E0" => DATA <= x"20"; when x"2E1" => DATA <= x"76"; when x"2E2" => DATA <= x"F8"; when x"2E3" => DATA <= x"C9"; when x"2E4" => DATA <= x"0D"; when x"2E5" => DATA <= x"F0"; when x"2E6" => DATA <= x"0D"; when x"2E7" => DATA <= x"20"; when x"2E8" => DATA <= x"3E"; when x"2E9" => DATA <= x"ED"; when x"2EA" => DATA <= x"45"; when x"2EB" => DATA <= x"EE"; when x"2EC" => DATA <= x"C9"; when x"2ED" => DATA <= x"80"; when x"2EE" => DATA <= x"F0"; when x"2EF" => DATA <= x"04"; when x"2F0" => DATA <= x"45"; when x"2F1" => DATA <= x"EE"; when x"2F2" => DATA <= x"85"; when x"2F3" => DATA <= x"EE"; when x"2F4" => DATA <= x"60"; when x"2F5" => DATA <= x"20"; when x"2F6" => DATA <= x"E4"; when x"2F7" => DATA <= x"ED"; when x"2F8" => DATA <= x"4C"; when x"2F9" => DATA <= x"FE"; when x"2FA" => DATA <= x"E6"; when x"2FB" => DATA <= x"20"; when x"2FC" => DATA <= x"2D"; when x"2FD" => DATA <= x"EC"; when x"2FE" => DATA <= x"A0"; when x"2FF" => DATA <= x"00"; when x"300" => DATA <= x"84"; when x"301" => DATA <= x"9A"; when x"302" => DATA <= x"20"; when x"303" => DATA <= x"FE"; when x"304" => DATA <= x"E6"; when x"305" => DATA <= x"A4"; when x"306" => DATA <= x"9A"; when x"307" => DATA <= x"20"; when x"308" => DATA <= x"0C"; when x"309" => DATA <= x"EE"; when x"30A" => DATA <= x"84"; when x"30B" => DATA <= x"9A"; when x"30C" => DATA <= x"CC"; when x"30D" => DATA <= x"05"; when x"30E" => DATA <= x"21"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F1"; when x"311" => DATA <= x"60"; when x"312" => DATA <= x"20"; when x"313" => DATA <= x"63"; when x"314" => DATA <= x"E7"; when x"315" => DATA <= x"A2"; when x"316" => DATA <= x"9C"; when x"317" => DATA <= x"20"; when x"318" => DATA <= x"93"; when x"319" => DATA <= x"F8"; when x"31A" => DATA <= x"F0"; when x"31B" => DATA <= x"04"; when x"31C" => DATA <= x"A9"; when x"31D" => DATA <= x"FF"; when x"31E" => DATA <= x"85"; when x"31F" => DATA <= x"9E"; when x"320" => DATA <= x"A2"; when x"321" => DATA <= x"9A"; when x"322" => DATA <= x"18"; when x"323" => DATA <= x"6C"; when x"324" => DATA <= x"0C"; when x"325" => DATA <= x"02"; when x"326" => DATA <= x"20"; when x"327" => DATA <= x"E7"; when x"328" => DATA <= x"ED"; when x"329" => DATA <= x"A2"; when x"32A" => DATA <= x"00"; when x"32B" => DATA <= x"A5"; when x"32C" => DATA <= x"9E"; when x"32D" => DATA <= x"10"; when x"32E" => DATA <= x"04"; when x"32F" => DATA <= x"A2"; when x"330" => DATA <= x"02"; when x"331" => DATA <= x"C8"; when x"332" => DATA <= x"C8"; when x"333" => DATA <= x"B9"; when x"334" => DATA <= x"08"; when x"335" => DATA <= x"21"; when x"336" => DATA <= x"95"; when x"337" => DATA <= x"9C"; when x"338" => DATA <= x"C8"; when x"339" => DATA <= x"E8"; when x"33A" => DATA <= x"E0"; when x"33B" => DATA <= x"08"; when x"33C" => DATA <= x"D0"; when x"33D" => DATA <= x"F5"; when x"33E" => DATA <= x"A5"; when x"33F" => DATA <= x"9C"; when x"340" => DATA <= x"85"; when x"341" => DATA <= x"F9"; when x"342" => DATA <= x"A5"; when x"343" => DATA <= x"9D"; when x"344" => DATA <= x"85"; when x"345" => DATA <= x"FA"; when x"346" => DATA <= x"A5"; when x"347" => DATA <= x"A0"; when x"348" => DATA <= x"85"; when x"349" => DATA <= x"FB"; when x"34A" => DATA <= x"A5"; when x"34B" => DATA <= x"A1"; when x"34C" => DATA <= x"85"; when x"34D" => DATA <= x"FC"; when x"34E" => DATA <= x"20"; when x"34F" => DATA <= x"5B"; when x"350" => DATA <= x"E3"; when x"351" => DATA <= x"A4"; when x"352" => DATA <= x"9A"; when x"353" => DATA <= x"20"; when x"354" => DATA <= x"FA"; when x"355" => DATA <= x"E6"; when x"356" => DATA <= x"A5"; when x"357" => DATA <= x"AD"; when x"358" => DATA <= x"85"; when x"359" => DATA <= x"AC"; when x"35A" => DATA <= x"60"; when x"35B" => DATA <= x"20"; when x"35C" => DATA <= x"8B"; when x"35D" => DATA <= x"EC"; when x"35E" => DATA <= x"24"; when x"35F" => DATA <= x"FD"; when x"360" => DATA <= x"30"; when x"361" => DATA <= x"03"; when x"362" => DATA <= x"4C"; when x"363" => DATA <= x"70"; when x"364" => DATA <= x"E3"; when x"365" => DATA <= x"20"; when x"366" => DATA <= x"9F"; when x"367" => DATA <= x"EE"; when x"368" => DATA <= x"20"; when x"369" => DATA <= x"B4"; when x"36A" => DATA <= x"E3"; when x"36B" => DATA <= x"A2"; when x"36C" => DATA <= x"01"; when x"36D" => DATA <= x"4C"; when x"36E" => DATA <= x"75"; when x"36F" => DATA <= x"E3"; when x"370" => DATA <= x"20"; when x"371" => DATA <= x"9F"; when x"372" => DATA <= x"EE"; when x"373" => DATA <= x"A2"; when x"374" => DATA <= x"02"; when x"375" => DATA <= x"A0"; when x"376" => DATA <= x"00"; when x"377" => DATA <= x"20"; when x"378" => DATA <= x"FB"; when x"379" => DATA <= x"EF"; when x"37A" => DATA <= x"91"; when x"37B" => DATA <= x"F9"; when x"37C" => DATA <= x"A5"; when x"37D" => DATA <= x"FB"; when x"37E" => DATA <= x"D0"; when x"37F" => DATA <= x"02"; when x"380" => DATA <= x"C6"; when x"381" => DATA <= x"FC"; when x"382" => DATA <= x"C6"; when x"383" => DATA <= x"FB"; when x"384" => DATA <= x"A5"; when x"385" => DATA <= x"FB"; when x"386" => DATA <= x"05"; when x"387" => DATA <= x"FC"; when x"388" => DATA <= x"F0"; when x"389" => DATA <= x"18"; when x"38A" => DATA <= x"C8"; when x"38B" => DATA <= x"D0"; when x"38C" => DATA <= x"EA"; when x"38D" => DATA <= x"E6"; when x"38E" => DATA <= x"FA"; when x"38F" => DATA <= x"CA"; when x"390" => DATA <= x"D0"; when x"391" => DATA <= x"E3"; when x"392" => DATA <= x"20"; when x"393" => DATA <= x"AE"; when x"394" => DATA <= x"EE"; when x"395" => DATA <= x"E6"; when x"396" => DATA <= x"84"; when x"397" => DATA <= x"D0"; when x"398" => DATA <= x"06"; when x"399" => DATA <= x"E6"; when x"39A" => DATA <= x"85"; when x"39B" => DATA <= x"D0"; when x"39C" => DATA <= x"02"; when x"39D" => DATA <= x"E6"; when x"39E" => DATA <= x"86"; when x"39F" => DATA <= x"4C"; when x"3A0" => DATA <= x"70"; when x"3A1" => DATA <= x"E3"; when x"3A2" => DATA <= x"C0"; when x"3A3" => DATA <= x"00"; when x"3A4" => DATA <= x"F0"; when x"3A5" => DATA <= x"04"; when x"3A6" => DATA <= x"20"; when x"3A7" => DATA <= x"B6"; when x"3A8" => DATA <= x"E3"; when x"3A9" => DATA <= x"CA"; when x"3AA" => DATA <= x"E0"; when x"3AB" => DATA <= x"00"; when x"3AC" => DATA <= x"F0"; when x"3AD" => DATA <= x"03"; when x"3AE" => DATA <= x"20"; when x"3AF" => DATA <= x"B4"; when x"3B0" => DATA <= x"E3"; when x"3B1" => DATA <= x"4C"; when x"3B2" => DATA <= x"AE"; when x"3B3" => DATA <= x"EE"; when x"3B4" => DATA <= x"A0"; when x"3B5" => DATA <= x"00"; when x"3B6" => DATA <= x"20"; when x"3B7" => DATA <= x"FB"; when x"3B8" => DATA <= x"EF"; when x"3B9" => DATA <= x"C8"; when x"3BA" => DATA <= x"D0"; when x"3BB" => DATA <= x"FA"; when x"3BC" => DATA <= x"60"; when x"3BD" => DATA <= x"38"; when x"3BE" => DATA <= x"4C"; when x"3BF" => DATA <= x"F2"; when x"3C0" => DATA <= x"E5"; when x"3C1" => DATA <= x"A2"; when x"3C2" => DATA <= x"00"; when x"3C3" => DATA <= x"20"; when x"3C4" => DATA <= x"F0"; when x"3C5" => DATA <= x"ED"; when x"3C6" => DATA <= x"86"; when x"3C7" => DATA <= x"EF"; when x"3C8" => DATA <= x"4C"; when x"3C9" => DATA <= x"56"; when x"3CA" => DATA <= x"E3"; when x"3CB" => DATA <= x"A2"; when x"3CC" => DATA <= x"FF"; when x"3CD" => DATA <= x"4C"; when x"3CE" => DATA <= x"C3"; when x"3CF" => DATA <= x"E3"; when x"3D0" => DATA <= x"20"; when x"3D1" => DATA <= x"12"; when x"3D2" => DATA <= x"E3"; when x"3D3" => DATA <= x"A4"; when x"3D4" => DATA <= x"03"; when x"3D5" => DATA <= x"20"; when x"3D6" => DATA <= x"51"; when x"3D7" => DATA <= x"E6"; when x"3D8" => DATA <= x"6C"; when x"3D9" => DATA <= x"9E"; when x"3DA" => DATA <= x"00"; when x"3DB" => DATA <= x"20"; when x"3DC" => DATA <= x"63"; when x"3DD" => DATA <= x"E7"; when x"3DE" => DATA <= x"A2"; when x"3DF" => DATA <= x"9C"; when x"3E0" => DATA <= x"20"; when x"3E1" => DATA <= x"65"; when x"3E2" => DATA <= x"FA"; when x"3E3" => DATA <= x"A2"; when x"3E4" => DATA <= x"A2"; when x"3E5" => DATA <= x"20"; when x"3E6" => DATA <= x"65"; when x"3E7" => DATA <= x"FA"; when x"3E8" => DATA <= x"A2"; when x"3E9" => DATA <= x"9E"; when x"3EA" => DATA <= x"20"; when x"3EB" => DATA <= x"93"; when x"3EC" => DATA <= x"F8"; when x"3ED" => DATA <= x"08"; when x"3EE" => DATA <= x"A5"; when x"3EF" => DATA <= x"9C"; when x"3F0" => DATA <= x"A6"; when x"3F1" => DATA <= x"9D"; when x"3F2" => DATA <= x"28"; when x"3F3" => DATA <= x"D0"; when x"3F4" => DATA <= x"04"; when x"3F5" => DATA <= x"85"; when x"3F6" => DATA <= x"9E"; when x"3F7" => DATA <= x"86"; when x"3F8" => DATA <= x"9F"; when x"3F9" => DATA <= x"85"; when x"3FA" => DATA <= x"A0"; when x"3FB" => DATA <= x"86"; when x"3FC" => DATA <= x"A1"; when x"3FD" => DATA <= x"84"; when x"3FE" => DATA <= x"03"; when x"3FF" => DATA <= x"20"; when x"400" => DATA <= x"76"; when x"401" => DATA <= x"FA"; when x"402" => DATA <= x"A2"; when x"403" => DATA <= x"9A"; when x"404" => DATA <= x"18"; when x"405" => DATA <= x"6C"; when x"406" => DATA <= x"0E"; when x"407" => DATA <= x"02"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"E6"; when x"40B" => DATA <= x"20"; when x"40C" => DATA <= x"2D"; when x"40D" => DATA <= x"EC"; when x"40E" => DATA <= x"20"; when x"40F" => DATA <= x"63"; when x"410" => DATA <= x"E6"; when x"411" => DATA <= x"20"; when x"412" => DATA <= x"CB"; when x"413" => DATA <= x"E6"; when x"414" => DATA <= x"90"; when x"415" => DATA <= x"03"; when x"416" => DATA <= x"20"; when x"417" => DATA <= x"AD"; when x"418" => DATA <= x"E7"; when x"419" => DATA <= x"A5"; when x"41A" => DATA <= x"A0"; when x"41B" => DATA <= x"48"; when x"41C" => DATA <= x"A5"; when x"41D" => DATA <= x"A1"; when x"41E" => DATA <= x"48"; when x"41F" => DATA <= x"38"; when x"420" => DATA <= x"A5"; when x"421" => DATA <= x"A2"; when x"422" => DATA <= x"E5"; when x"423" => DATA <= x"A0"; when x"424" => DATA <= x"85"; when x"425" => DATA <= x"A0"; when x"426" => DATA <= x"A5"; when x"427" => DATA <= x"A3"; when x"428" => DATA <= x"E5"; when x"429" => DATA <= x"A1"; when x"42A" => DATA <= x"85"; when x"42B" => DATA <= x"A1"; when x"42C" => DATA <= x"A9"; when x"42D" => DATA <= x"00"; when x"42E" => DATA <= x"85"; when x"42F" => DATA <= x"A2"; when x"430" => DATA <= x"A9"; when x"431" => DATA <= x"02"; when x"432" => DATA <= x"85"; when x"433" => DATA <= x"A3"; when x"434" => DATA <= x"AC"; when x"435" => DATA <= x"05"; when x"436" => DATA <= x"21"; when x"437" => DATA <= x"F0"; when x"438" => DATA <= x"44"; when x"439" => DATA <= x"C0"; when x"43A" => DATA <= x"F8"; when x"43B" => DATA <= x"90"; when x"43C" => DATA <= x"09"; when x"43D" => DATA <= x"20"; when x"43E" => DATA <= x"D1"; when x"43F" => DATA <= x"F7"; when x"440" => DATA <= x"46"; when x"441" => DATA <= x"55"; when x"442" => DATA <= x"4C"; when x"443" => DATA <= x"4C"; when x"444" => DATA <= x"EA"; when x"445" => DATA <= x"00"; when x"446" => DATA <= x"20"; when x"447" => DATA <= x"DF"; when x"448" => DATA <= x"E4"; when x"449" => DATA <= x"4C"; when x"44A" => DATA <= x"52"; when x"44B" => DATA <= x"E4"; when x"44C" => DATA <= x"20"; when x"44D" => DATA <= x"15"; when x"44E" => DATA <= x"EE"; when x"44F" => DATA <= x"20"; when x"450" => DATA <= x"C0"; when x"451" => DATA <= x"E4"; when x"452" => DATA <= x"98"; when x"453" => DATA <= x"F0"; when x"454" => DATA <= x"02"; when x"455" => DATA <= x"90"; when x"456" => DATA <= x"F5"; when x"457" => DATA <= x"B0"; when x"458" => DATA <= x"0C"; when x"459" => DATA <= x"20"; when x"45A" => DATA <= x"D1"; when x"45B" => DATA <= x"F7"; when x"45C" => DATA <= x"4E"; when x"45D" => DATA <= x"4F"; when x"45E" => DATA <= x"20"; when x"45F" => DATA <= x"52"; when x"460" => DATA <= x"4F"; when x"461" => DATA <= x"4F"; when x"462" => DATA <= x"4D"; when x"463" => DATA <= x"EA"; when x"464" => DATA <= x"00"; when x"465" => DATA <= x"84"; when x"466" => DATA <= x"EA"; when x"467" => DATA <= x"AC"; when x"468" => DATA <= x"05"; when x"469" => DATA <= x"21"; when x"46A" => DATA <= x"C4"; when x"46B" => DATA <= x"EA"; when x"46C" => DATA <= x"F0"; when x"46D" => DATA <= x"0F"; when x"46E" => DATA <= x"B9"; when x"46F" => DATA <= x"07"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"99"; when x"472" => DATA <= x"0F"; when x"473" => DATA <= x"20"; when x"474" => DATA <= x"B9"; when x"475" => DATA <= x"07"; when x"476" => DATA <= x"21"; when x"477" => DATA <= x"99"; when x"478" => DATA <= x"0F"; when x"479" => DATA <= x"21"; when x"47A" => DATA <= x"88"; when x"47B" => DATA <= x"B0"; when x"47C" => DATA <= x"ED"; when x"47D" => DATA <= x"A2"; when x"47E" => DATA <= x"00"; when x"47F" => DATA <= x"B5"; when x"480" => DATA <= x"A5"; when x"481" => DATA <= x"99"; when x"482" => DATA <= x"08"; when x"483" => DATA <= x"20"; when x"484" => DATA <= x"C8"; when x"485" => DATA <= x"E8"; when x"486" => DATA <= x"E0"; when x"487" => DATA <= x"08"; when x"488" => DATA <= x"D0"; when x"489" => DATA <= x"F5"; when x"48A" => DATA <= x"B5"; when x"48B" => DATA <= x"9B"; when x"48C" => DATA <= x"88"; when x"48D" => DATA <= x"99"; when x"48E" => DATA <= x"08"; when x"48F" => DATA <= x"21"; when x"490" => DATA <= x"CA"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"F7"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"FA"; when x"495" => DATA <= x"E6"; when x"496" => DATA <= x"68"; when x"497" => DATA <= x"85"; when x"498" => DATA <= x"9D"; when x"499" => DATA <= x"68"; when x"49A" => DATA <= x"85"; when x"49B" => DATA <= x"9C"; when x"49C" => DATA <= x"AC"; when x"49D" => DATA <= x"05"; when x"49E" => DATA <= x"21"; when x"49F" => DATA <= x"20"; when x"4A0" => DATA <= x"0C"; when x"4A1" => DATA <= x"EE"; when x"4A2" => DATA <= x"8C"; when x"4A3" => DATA <= x"05"; when x"4A4" => DATA <= x"21"; when x"4A5" => DATA <= x"20"; when x"4A6" => DATA <= x"7B"; when x"4A7" => DATA <= x"EC"; when x"4A8" => DATA <= x"A5"; when x"4A9" => DATA <= x"9C"; when x"4AA" => DATA <= x"85"; when x"4AB" => DATA <= x"F9"; when x"4AC" => DATA <= x"A5"; when x"4AD" => DATA <= x"9D"; when x"4AE" => DATA <= x"85"; when x"4AF" => DATA <= x"FA"; when x"4B0" => DATA <= x"A5"; when x"4B1" => DATA <= x"A1"; when x"4B2" => DATA <= x"85"; when x"4B3" => DATA <= x"FB"; when x"4B4" => DATA <= x"A5"; when x"4B5" => DATA <= x"A0"; when x"4B6" => DATA <= x"F0"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"E6"; when x"4B9" => DATA <= x"FB"; when x"4BA" => DATA <= x"20"; when x"4BB" => DATA <= x"F9"; when x"4BC" => DATA <= x"E4"; when x"4BD" => DATA <= x"4C"; when x"4BE" => DATA <= x"56"; when x"4BF" => DATA <= x"E3"; when x"4C0" => DATA <= x"B9"; when x"4C1" => DATA <= x"0E"; when x"4C2" => DATA <= x"21"; when x"4C3" => DATA <= x"20"; when x"4C4" => DATA <= x"1F"; when x"4C5" => DATA <= x"EE"; when x"4C6" => DATA <= x"85"; when x"4C7" => DATA <= x"A2"; when x"4C8" => DATA <= x"18"; when x"4C9" => DATA <= x"A9"; when x"4CA" => DATA <= x"FF"; when x"4CB" => DATA <= x"79"; when x"4CC" => DATA <= x"0C"; when x"4CD" => DATA <= x"21"; when x"4CE" => DATA <= x"B9"; when x"4CF" => DATA <= x"0F"; when x"4D0" => DATA <= x"21"; when x"4D1" => DATA <= x"79"; when x"4D2" => DATA <= x"0D"; when x"4D3" => DATA <= x"21"; when x"4D4" => DATA <= x"85"; when x"4D5" => DATA <= x"A3"; when x"4D6" => DATA <= x"B9"; when x"4D7" => DATA <= x"0E"; when x"4D8" => DATA <= x"21"; when x"4D9" => DATA <= x"29"; when x"4DA" => DATA <= x"0F"; when x"4DB" => DATA <= x"65"; when x"4DC" => DATA <= x"A2"; when x"4DD" => DATA <= x"85"; when x"4DE" => DATA <= x"A2"; when x"4DF" => DATA <= x"38"; when x"4E0" => DATA <= x"B9"; when x"4E1" => DATA <= x"07"; when x"4E2" => DATA <= x"21"; when x"4E3" => DATA <= x"E5"; when x"4E4" => DATA <= x"A3"; when x"4E5" => DATA <= x"48"; when x"4E6" => DATA <= x"B9"; when x"4E7" => DATA <= x"06"; when x"4E8" => DATA <= x"21"; when x"4E9" => DATA <= x"29"; when x"4EA" => DATA <= x"0F"; when x"4EB" => DATA <= x"E5"; when x"4EC" => DATA <= x"A2"; when x"4ED" => DATA <= x"AA"; when x"4EE" => DATA <= x"A9"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"C5"; when x"4F1" => DATA <= x"A0"; when x"4F2" => DATA <= x"68"; when x"4F3" => DATA <= x"E5"; when x"4F4" => DATA <= x"A1"; when x"4F5" => DATA <= x"8A"; when x"4F6" => DATA <= x"E9"; when x"4F7" => DATA <= x"00"; when x"4F8" => DATA <= x"60"; when x"4F9" => DATA <= x"20"; when x"4FA" => DATA <= x"8B"; when x"4FB" => DATA <= x"EC"; when x"4FC" => DATA <= x"24"; when x"4FD" => DATA <= x"FD"; when x"4FE" => DATA <= x"30"; when x"4FF" => DATA <= x"03"; when x"500" => DATA <= x"4C"; when x"501" => DATA <= x"16"; when x"502" => DATA <= x"E5"; when x"503" => DATA <= x"20"; when x"504" => DATA <= x"52"; when x"505" => DATA <= x"E5"; when x"506" => DATA <= x"C6"; when x"507" => DATA <= x"FA"; when x"508" => DATA <= x"20"; when x"509" => DATA <= x"B7"; when x"50A" => DATA <= x"EE"; when x"50B" => DATA <= x"20"; when x"50C" => DATA <= x"6E"; when x"50D" => DATA <= x"E5"; when x"50E" => DATA <= x"20"; when x"50F" => DATA <= x"65"; when x"510" => DATA <= x"E5"; when x"511" => DATA <= x"A2"; when x"512" => DATA <= x"01"; when x"513" => DATA <= x"4C"; when x"514" => DATA <= x"27"; when x"515" => DATA <= x"E5"; when x"516" => DATA <= x"A5"; when x"517" => DATA <= x"FB"; when x"518" => DATA <= x"C9"; when x"519" => DATA <= x"01"; when x"51A" => DATA <= x"D0"; when x"51B" => DATA <= x"06"; when x"51C" => DATA <= x"20"; when x"51D" => DATA <= x"52"; when x"51E" => DATA <= x"E5"; when x"51F" => DATA <= x"20"; when x"520" => DATA <= x"65"; when x"521" => DATA <= x"E5"; when x"522" => DATA <= x"20"; when x"523" => DATA <= x"B7"; when x"524" => DATA <= x"EE"; when x"525" => DATA <= x"A2"; when x"526" => DATA <= x"02"; when x"527" => DATA <= x"20"; when x"528" => DATA <= x"6E"; when x"529" => DATA <= x"E5"; when x"52A" => DATA <= x"E6"; when x"52B" => DATA <= x"FA"; when x"52C" => DATA <= x"C6"; when x"52D" => DATA <= x"FB"; when x"52E" => DATA <= x"F0"; when x"52F" => DATA <= x"13"; when x"530" => DATA <= x"CA"; when x"531" => DATA <= x"D0"; when x"532" => DATA <= x"F4"; when x"533" => DATA <= x"20"; when x"534" => DATA <= x"D7"; when x"535" => DATA <= x"EE"; when x"536" => DATA <= x"E6"; when x"537" => DATA <= x"84"; when x"538" => DATA <= x"D0"; when x"539" => DATA <= x"06"; when x"53A" => DATA <= x"E6"; when x"53B" => DATA <= x"85"; when x"53C" => DATA <= x"D0"; when x"53D" => DATA <= x"02"; when x"53E" => DATA <= x"E6"; when x"53F" => DATA <= x"86"; when x"540" => DATA <= x"4C"; when x"541" => DATA <= x"16"; when x"542" => DATA <= x"E5"; when x"543" => DATA <= x"E0"; when x"544" => DATA <= x"02"; when x"545" => DATA <= x"D0"; when x"546" => DATA <= x"08"; when x"547" => DATA <= x"20"; when x"548" => DATA <= x"EF"; when x"549" => DATA <= x"EB"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"FA"; when x"54C" => DATA <= x"20"; when x"54D" => DATA <= x"6E"; when x"54E" => DATA <= x"E5"; when x"54F" => DATA <= x"4C"; when x"550" => DATA <= x"D7"; when x"551" => DATA <= x"EE"; when x"552" => DATA <= x"8A"; when x"553" => DATA <= x"48"; when x"554" => DATA <= x"A5"; when x"555" => DATA <= x"F9"; when x"556" => DATA <= x"85"; when x"557" => DATA <= x"FE"; when x"558" => DATA <= x"A5"; when x"559" => DATA <= x"FA"; when x"55A" => DATA <= x"85"; when x"55B" => DATA <= x"FF"; when x"55C" => DATA <= x"20"; when x"55D" => DATA <= x"EF"; when x"55E" => DATA <= x"EB"; when x"55F" => DATA <= x"20"; when x"560" => DATA <= x"71"; when x"561" => DATA <= x"EE"; when x"562" => DATA <= x"68"; when x"563" => DATA <= x"AA"; when x"564" => DATA <= x"60"; when x"565" => DATA <= x"A5"; when x"566" => DATA <= x"FF"; when x"567" => DATA <= x"85"; when x"568" => DATA <= x"FA"; when x"569" => DATA <= x"A5"; when x"56A" => DATA <= x"FE"; when x"56B" => DATA <= x"85"; when x"56C" => DATA <= x"F9"; when x"56D" => DATA <= x"60"; when x"56E" => DATA <= x"A0"; when x"56F" => DATA <= x"00"; when x"570" => DATA <= x"B1"; when x"571" => DATA <= x"F9"; when x"572" => DATA <= x"20"; when x"573" => DATA <= x"FD"; when x"574" => DATA <= x"EF"; when x"575" => DATA <= x"C8"; when x"576" => DATA <= x"D0"; when x"577" => DATA <= x"F8"; when x"578" => DATA <= x"60"; when x"579" => DATA <= x"A4"; when x"57A" => DATA <= x"03"; when x"57B" => DATA <= x"C8"; when x"57C" => DATA <= x"20"; when x"57D" => DATA <= x"76"; when x"57E" => DATA <= x"FA"; when x"57F" => DATA <= x"B9"; when x"580" => DATA <= x"FF"; when x"581" => DATA <= x"00"; when x"582" => DATA <= x"85"; when x"583" => DATA <= x"AC"; when x"584" => DATA <= x"85"; when x"585" => DATA <= x"AD"; when x"586" => DATA <= x"60"; when x"587" => DATA <= x"20"; when x"588" => DATA <= x"63"; when x"589" => DATA <= x"E7"; when x"58A" => DATA <= x"20"; when x"58B" => DATA <= x"2D"; when x"58C" => DATA <= x"EC"; when x"58D" => DATA <= x"A2"; when x"58E" => DATA <= x"FF"; when x"58F" => DATA <= x"E8"; when x"590" => DATA <= x"BD"; when x"591" => DATA <= x"40"; when x"592" => DATA <= x"01"; when x"593" => DATA <= x"C9"; when x"594" => DATA <= x"0D"; when x"595" => DATA <= x"D0"; when x"596" => DATA <= x"F8"; when x"597" => DATA <= x"E0"; when x"598" => DATA <= x"0E"; when x"599" => DATA <= x"B0"; when x"59A" => DATA <= x"03"; when x"59B" => DATA <= x"4C"; when x"59C" => DATA <= x"A8"; when x"59D" => DATA <= x"E5"; when x"59E" => DATA <= x"20"; when x"59F" => DATA <= x"D1"; when x"5A0" => DATA <= x"F7"; when x"5A1" => DATA <= x"4E"; when x"5A2" => DATA <= x"41"; when x"5A3" => DATA <= x"4D"; when x"5A4" => DATA <= x"45"; when x"5A5" => DATA <= x"3F"; when x"5A6" => DATA <= x"EA"; when x"5A7" => DATA <= x"00"; when x"5A8" => DATA <= x"A5"; when x"5A9" => DATA <= x"EE"; when x"5AA" => DATA <= x"20"; when x"5AB" => DATA <= x"AA"; when x"5AC" => DATA <= x"ED"; when x"5AD" => DATA <= x"20"; when x"5AE" => DATA <= x"16"; when x"5AF" => DATA <= x"EC"; when x"5B0" => DATA <= x"20"; when x"5B1" => DATA <= x"63"; when x"5B2" => DATA <= x"E6"; when x"5B3" => DATA <= x"A0"; when x"5B4" => DATA <= x"00"; when x"5B5" => DATA <= x"B9"; when x"5B6" => DATA <= x"40"; when x"5B7" => DATA <= x"01"; when x"5B8" => DATA <= x"C9"; when x"5B9" => DATA <= x"0D"; when x"5BA" => DATA <= x"F0"; when x"5BB" => DATA <= x"13"; when x"5BC" => DATA <= x"91"; when x"5BD" => DATA <= x"87"; when x"5BE" => DATA <= x"C0"; when x"5BF" => DATA <= x"08"; when x"5C0" => DATA <= x"B0"; when x"5C1" => DATA <= x"06"; when x"5C2" => DATA <= x"99"; when x"5C3" => DATA <= x"00"; when x"5C4" => DATA <= x"20"; when x"5C5" => DATA <= x"4C"; when x"5C6" => DATA <= x"CB"; when x"5C7" => DATA <= x"E5"; when x"5C8" => DATA <= x"99"; when x"5C9" => DATA <= x"F8"; when x"5CA" => DATA <= x"20"; when x"5CB" => DATA <= x"C8"; when x"5CC" => DATA <= x"4C"; when x"5CD" => DATA <= x"B5"; when x"5CE" => DATA <= x"E5"; when x"5CF" => DATA <= x"C0"; when x"5D0" => DATA <= x"0D"; when x"5D1" => DATA <= x"F0"; when x"5D2" => DATA <= x"15"; when x"5D3" => DATA <= x"A9"; when x"5D4" => DATA <= x"20"; when x"5D5" => DATA <= x"91"; when x"5D6" => DATA <= x"87"; when x"5D7" => DATA <= x"C0"; when x"5D8" => DATA <= x"08"; when x"5D9" => DATA <= x"B0"; when x"5DA" => DATA <= x"06"; when x"5DB" => DATA <= x"99"; when x"5DC" => DATA <= x"00"; when x"5DD" => DATA <= x"20"; when x"5DE" => DATA <= x"4C"; when x"5DF" => DATA <= x"E4"; when x"5E0" => DATA <= x"E5"; when x"5E1" => DATA <= x"99"; when x"5E2" => DATA <= x"F8"; when x"5E3" => DATA <= x"20"; when x"5E4" => DATA <= x"C8"; when x"5E5" => DATA <= x"4C"; when x"5E6" => DATA <= x"CF"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"20"; when x"5E9" => DATA <= x"26"; when x"5EA" => DATA <= x"EC"; when x"5EB" => DATA <= x"20"; when x"5EC" => DATA <= x"7B"; when x"5ED" => DATA <= x"EC"; when x"5EE" => DATA <= x"4C"; when x"5EF" => DATA <= x"E0"; when x"5F0" => DATA <= x"EB"; when x"5F1" => DATA <= x"18"; when x"5F2" => DATA <= x"08"; when x"5F3" => DATA <= x"20"; when x"5F4" => DATA <= x"63"; when x"5F5" => DATA <= x"E7"; when x"5F6" => DATA <= x"20"; when x"5F7" => DATA <= x"91"; when x"5F8" => DATA <= x"E6"; when x"5F9" => DATA <= x"20"; when x"5FA" => DATA <= x"BC"; when x"5FB" => DATA <= x"E6"; when x"5FC" => DATA <= x"20"; when x"5FD" => DATA <= x"63"; when x"5FE" => DATA <= x"E6"; when x"5FF" => DATA <= x"A5"; when x"600" => DATA <= x"AC"; when x"601" => DATA <= x"2A"; when x"602" => DATA <= x"28"; when x"603" => DATA <= x"6A"; when x"604" => DATA <= x"99"; when x"605" => DATA <= x"0F"; when x"606" => DATA <= x"20"; when x"607" => DATA <= x"20"; when x"608" => DATA <= x"FA"; when x"609" => DATA <= x"E6"; when x"60A" => DATA <= x"20"; when x"60B" => DATA <= x"7B"; when x"60C" => DATA <= x"EC"; when x"60D" => DATA <= x"4C"; when x"60E" => DATA <= x"56"; when x"60F" => DATA <= x"E3"; when x"610" => DATA <= x"A5"; when x"611" => DATA <= x"AC"; when x"612" => DATA <= x"85"; when x"613" => DATA <= x"AD"; when x"614" => DATA <= x"A4"; when x"615" => DATA <= x"03"; when x"616" => DATA <= x"C8"; when x"617" => DATA <= x"20"; when x"618" => DATA <= x"76"; when x"619" => DATA <= x"FA"; when x"61A" => DATA <= x"B9"; when x"61B" => DATA <= x"FF"; when x"61C" => DATA <= x"00"; when x"61D" => DATA <= x"85"; when x"61E" => DATA <= x"AC"; when x"61F" => DATA <= x"60"; when x"620" => DATA <= x"20"; when x"621" => DATA <= x"63"; when x"622" => DATA <= x"E7"; when x"623" => DATA <= x"20"; when x"624" => DATA <= x"91"; when x"625" => DATA <= x"E6"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"51"; when x"628" => DATA <= x"E6"; when x"629" => DATA <= x"20"; when x"62A" => DATA <= x"CB"; when x"62B" => DATA <= x"E6"; when x"62C" => DATA <= x"B0"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"4C"; when x"62F" => DATA <= x"26"; when x"630" => DATA <= x"F9"; when x"631" => DATA <= x"A5"; when x"632" => DATA <= x"EE"; when x"633" => DATA <= x"85"; when x"634" => DATA <= x"C7"; when x"635" => DATA <= x"A5"; when x"636" => DATA <= x"AC"; when x"637" => DATA <= x"85"; when x"638" => DATA <= x"C8"; when x"639" => DATA <= x"A9"; when x"63A" => DATA <= x"20"; when x"63B" => DATA <= x"85"; when x"63C" => DATA <= x"AC"; when x"63D" => DATA <= x"A9"; when x"63E" => DATA <= x"00"; when x"63F" => DATA <= x"85"; when x"640" => DATA <= x"EE"; when x"641" => DATA <= x"85"; when x"642" => DATA <= x"9E"; when x"643" => DATA <= x"20"; when x"644" => DATA <= x"20"; when x"645" => DATA <= x"E3"; when x"646" => DATA <= x"A5"; when x"647" => DATA <= x"C7"; when x"648" => DATA <= x"85"; when x"649" => DATA <= x"EE"; when x"64A" => DATA <= x"A5"; when x"64B" => DATA <= x"C8"; when x"64C" => DATA <= x"85"; when x"64D" => DATA <= x"AC"; when x"64E" => DATA <= x"6C"; when x"64F" => DATA <= x"9E"; when x"650" => DATA <= x"00"; when x"651" => DATA <= x"20"; when x"652" => DATA <= x"76"; when x"653" => DATA <= x"F8"; when x"654" => DATA <= x"A2"; when x"655" => DATA <= x"00"; when x"656" => DATA <= x"B9"; when x"657" => DATA <= x"00"; when x"658" => DATA <= x"01"; when x"659" => DATA <= x"9D"; when x"65A" => DATA <= x"00"; when x"65B" => DATA <= x"01"; when x"65C" => DATA <= x"E8"; when x"65D" => DATA <= x"C8"; when x"65E" => DATA <= x"C9"; when x"65F" => DATA <= x"0D"; when x"660" => DATA <= x"D0"; when x"661" => DATA <= x"F4"; when x"662" => DATA <= x"60"; when x"663" => DATA <= x"A5"; when x"664" => DATA <= x"F8"; when x"665" => DATA <= x"4C"; when x"666" => DATA <= x"7E"; when x"667" => DATA <= x"E6"; when x"668" => DATA <= x"A0"; when x"669" => DATA <= x"0F"; when x"66A" => DATA <= x"B1"; when x"66B" => DATA <= x"87"; when x"66C" => DATA <= x"C9"; when x"66D" => DATA <= x"FF"; when x"66E" => DATA <= x"D0"; when x"66F" => DATA <= x"20"; when x"670" => DATA <= x"20"; when x"671" => DATA <= x"D1"; when x"672" => DATA <= x"F7"; when x"673" => DATA <= x"4E"; when x"674" => DATA <= x"4F"; when x"675" => DATA <= x"54"; when x"676" => DATA <= x"20"; when x"677" => DATA <= x"56"; when x"678" => DATA <= x"41"; when x"679" => DATA <= x"4C"; when x"67A" => DATA <= x"49"; when x"67B" => DATA <= x"44"; when x"67C" => DATA <= x"EA"; when x"67D" => DATA <= x"00"; when x"67E" => DATA <= x"C9"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"D0"; when x"681" => DATA <= x"0E"; when x"682" => DATA <= x"20"; when x"683" => DATA <= x"D1"; when x"684" => DATA <= x"F7"; when x"685" => DATA <= x"44"; when x"686" => DATA <= x"49"; when x"687" => DATA <= x"53"; when x"688" => DATA <= x"4B"; when x"689" => DATA <= x"20"; when x"68A" => DATA <= x"50"; when x"68B" => DATA <= x"52"; when x"68C" => DATA <= x"4F"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"EA"; when x"68F" => DATA <= x"00"; when x"690" => DATA <= x"60"; when x"691" => DATA <= x"A0"; when x"692" => DATA <= x"00"; when x"693" => DATA <= x"B5"; when x"694" => DATA <= x"00"; when x"695" => DATA <= x"99"; when x"696" => DATA <= x"9A"; when x"697" => DATA <= x"00"; when x"698" => DATA <= x"E8"; when x"699" => DATA <= x"C8"; when x"69A" => DATA <= x"C0"; when x"69B" => DATA <= x"0A"; when x"69C" => DATA <= x"90"; when x"69D" => DATA <= x"F5"; when x"69E" => DATA <= x"A9"; when x"69F" => DATA <= x"20"; when x"6A0" => DATA <= x"A0"; when x"6A1" => DATA <= x"06"; when x"6A2" => DATA <= x"99"; when x"6A3" => DATA <= x"A5"; when x"6A4" => DATA <= x"00"; when x"6A5" => DATA <= x"88"; when x"6A6" => DATA <= x"10"; when x"6A7" => DATA <= x"FA"; when x"6A8" => DATA <= x"C8"; when x"6A9" => DATA <= x"B1"; when x"6AA" => DATA <= x"9A"; when x"6AB" => DATA <= x"C9"; when x"6AC" => DATA <= x"0D"; when x"6AD" => DATA <= x"F0"; when x"6AE" => DATA <= x"09"; when x"6AF" => DATA <= x"C0"; when x"6B0" => DATA <= x"07"; when x"6B1" => DATA <= x"B0"; when x"6B2" => DATA <= x"06"; when x"6B3" => DATA <= x"99"; when x"6B4" => DATA <= x"A5"; when x"6B5" => DATA <= x"00"; when x"6B6" => DATA <= x"D0"; when x"6B7" => DATA <= x"F0"; when x"6B8" => DATA <= x"60"; when x"6B9" => DATA <= x"4C"; when x"6BA" => DATA <= x"9E"; when x"6BB" => DATA <= x"E5"; when x"6BC" => DATA <= x"20"; when x"6BD" => DATA <= x"CB"; when x"6BE" => DATA <= x"E6"; when x"6BF" => DATA <= x"B0"; when x"6C0" => DATA <= x"F7"; when x"6C1" => DATA <= x"20"; when x"6C2" => DATA <= x"D1"; when x"6C3" => DATA <= x"F7"; when x"6C4" => DATA <= x"46"; when x"6C5" => DATA <= x"49"; when x"6C6" => DATA <= x"4C"; when x"6C7" => DATA <= x"45"; when x"6C8" => DATA <= x"3F"; when x"6C9" => DATA <= x"EA"; when x"6CA" => DATA <= x"00"; when x"6CB" => DATA <= x"20"; when x"6CC" => DATA <= x"2D"; when x"6CD" => DATA <= x"EC"; when x"6CE" => DATA <= x"A0"; when x"6CF" => DATA <= x"F8"; when x"6D0" => DATA <= x"20"; when x"6D1" => DATA <= x"0C"; when x"6D2" => DATA <= x"EE"; when x"6D3" => DATA <= x"CC"; when x"6D4" => DATA <= x"05"; when x"6D5" => DATA <= x"21"; when x"6D6" => DATA <= x"B0"; when x"6D7" => DATA <= x"20"; when x"6D8" => DATA <= x"B9"; when x"6D9" => DATA <= x"0F"; when x"6DA" => DATA <= x"20"; when x"6DB" => DATA <= x"29"; when x"6DC" => DATA <= x"7F"; when x"6DD" => DATA <= x"C5"; when x"6DE" => DATA <= x"AC"; when x"6DF" => DATA <= x"D0"; when x"6E0" => DATA <= x"EF"; when x"6E1" => DATA <= x"20"; when x"6E2" => DATA <= x"0D"; when x"6E3" => DATA <= x"EE"; when x"6E4" => DATA <= x"A2"; when x"6E5" => DATA <= x"06"; when x"6E6" => DATA <= x"B9"; when x"6E7" => DATA <= x"07"; when x"6E8" => DATA <= x"20"; when x"6E9" => DATA <= x"D5"; when x"6EA" => DATA <= x"A5"; when x"6EB" => DATA <= x"D0"; when x"6EC" => DATA <= x"05"; when x"6ED" => DATA <= x"88"; when x"6EE" => DATA <= x"CA"; when x"6EF" => DATA <= x"10"; when x"6F0" => DATA <= x"F5"; when x"6F1" => DATA <= x"60"; when x"6F2" => DATA <= x"88"; when x"6F3" => DATA <= x"CA"; when x"6F4" => DATA <= x"10"; when x"6F5" => DATA <= x"FC"; when x"6F6" => DATA <= x"30"; when x"6F7" => DATA <= x"D8"; when x"6F8" => DATA <= x"18"; when x"6F9" => DATA <= x"60"; when x"6FA" => DATA <= x"A5"; when x"6FB" => DATA <= x"EF"; when x"6FC" => DATA <= x"D0"; when x"6FD" => DATA <= x"64"; when x"6FE" => DATA <= x"B9"; when x"6FF" => DATA <= x"0F"; when x"700" => DATA <= x"20"; when x"701" => DATA <= x"29"; when x"702" => DATA <= x"7F"; when x"703" => DATA <= x"20"; when x"704" => DATA <= x"F4"; when x"705" => DATA <= x"FF"; when x"706" => DATA <= x"20"; when x"707" => DATA <= x"FD"; when x"708" => DATA <= x"F7"; when x"709" => DATA <= x"BE"; when x"70A" => DATA <= x"0F"; when x"70B" => DATA <= x"20"; when x"70C" => DATA <= x"10"; when x"70D" => DATA <= x"02"; when x"70E" => DATA <= x"A9"; when x"70F" => DATA <= x"23"; when x"710" => DATA <= x"20"; when x"711" => DATA <= x"F4"; when x"712" => DATA <= x"FF"; when x"713" => DATA <= x"A2"; when x"714" => DATA <= x"07"; when x"715" => DATA <= x"B9"; when x"716" => DATA <= x"08"; when x"717" => DATA <= x"20"; when x"718" => DATA <= x"20"; when x"719" => DATA <= x"F4"; when x"71A" => DATA <= x"FF"; when x"71B" => DATA <= x"C8"; when x"71C" => DATA <= x"CA"; when x"71D" => DATA <= x"D0"; when x"71E" => DATA <= x"F6"; when x"71F" => DATA <= x"20"; when x"720" => DATA <= x"FD"; when x"721" => DATA <= x"F7"; when x"722" => DATA <= x"B9"; when x"723" => DATA <= x"02"; when x"724" => DATA <= x"21"; when x"725" => DATA <= x"20"; when x"726" => DATA <= x"02"; when x"727" => DATA <= x"F8"; when x"728" => DATA <= x"B9"; when x"729" => DATA <= x"01"; when x"72A" => DATA <= x"21"; when x"72B" => DATA <= x"20"; when x"72C" => DATA <= x"02"; when x"72D" => DATA <= x"F8"; when x"72E" => DATA <= x"C8"; when x"72F" => DATA <= x"E8"; when x"730" => DATA <= x"C8"; when x"731" => DATA <= x"E0"; when x"732" => DATA <= x"02"; when x"733" => DATA <= x"90"; when x"734" => DATA <= x"EA"; when x"735" => DATA <= x"20"; when x"736" => DATA <= x"FD"; when x"737" => DATA <= x"F7"; when x"738" => DATA <= x"20"; when x"739" => DATA <= x"FD"; when x"73A" => DATA <= x"F7"; when x"73B" => DATA <= x"B9"; when x"73C" => DATA <= x"03"; when x"73D" => DATA <= x"21"; when x"73E" => DATA <= x"20"; when x"73F" => DATA <= x"1F"; when x"740" => DATA <= x"EE"; when x"741" => DATA <= x"20"; when x"742" => DATA <= x"0B"; when x"743" => DATA <= x"F8"; when x"744" => DATA <= x"B9"; when x"745" => DATA <= x"02"; when x"746" => DATA <= x"21"; when x"747" => DATA <= x"20"; when x"748" => DATA <= x"02"; when x"749" => DATA <= x"F8"; when x"74A" => DATA <= x"B9"; when x"74B" => DATA <= x"01"; when x"74C" => DATA <= x"21"; when x"74D" => DATA <= x"20"; when x"74E" => DATA <= x"02"; when x"74F" => DATA <= x"F8"; when x"750" => DATA <= x"20"; when x"751" => DATA <= x"FD"; when x"752" => DATA <= x"F7"; when x"753" => DATA <= x"B9"; when x"754" => DATA <= x"03"; when x"755" => DATA <= x"21"; when x"756" => DATA <= x"20"; when x"757" => DATA <= x"0B"; when x"758" => DATA <= x"F8"; when x"759" => DATA <= x"B9"; when x"75A" => DATA <= x"04"; when x"75B" => DATA <= x"21"; when x"75C" => DATA <= x"20"; when x"75D" => DATA <= x"02"; when x"75E" => DATA <= x"F8"; when x"75F" => DATA <= x"20"; when x"760" => DATA <= x"ED"; when x"761" => DATA <= x"FF"; when x"762" => DATA <= x"60"; when x"763" => DATA <= x"A2"; when x"764" => DATA <= x"00"; when x"765" => DATA <= x"A4"; when x"766" => DATA <= x"9A"; when x"767" => DATA <= x"20"; when x"768" => DATA <= x"76"; when x"769" => DATA <= x"F8"; when x"76A" => DATA <= x"C9"; when x"76B" => DATA <= x"22"; when x"76C" => DATA <= x"F0"; when x"76D" => DATA <= x"20"; when x"76E" => DATA <= x"C9"; when x"76F" => DATA <= x"0D"; when x"770" => DATA <= x"F0"; when x"771" => DATA <= x"0C"; when x"772" => DATA <= x"9D"; when x"773" => DATA <= x"40"; when x"774" => DATA <= x"01"; when x"775" => DATA <= x"E8"; when x"776" => DATA <= x"C8"; when x"777" => DATA <= x"B9"; when x"778" => DATA <= x"00"; when x"779" => DATA <= x"01"; when x"77A" => DATA <= x"C9"; when x"77B" => DATA <= x"20"; when x"77C" => DATA <= x"D0"; when x"77D" => DATA <= x"F0"; when x"77E" => DATA <= x"A9"; when x"77F" => DATA <= x"0D"; when x"780" => DATA <= x"9D"; when x"781" => DATA <= x"40"; when x"782" => DATA <= x"01"; when x"783" => DATA <= x"A9"; when x"784" => DATA <= x"40"; when x"785" => DATA <= x"85"; when x"786" => DATA <= x"9A"; when x"787" => DATA <= x"A9"; when x"788" => DATA <= x"01"; when x"789" => DATA <= x"85"; when x"78A" => DATA <= x"9B"; when x"78B" => DATA <= x"A2"; when x"78C" => DATA <= x"9A"; when x"78D" => DATA <= x"60"; when x"78E" => DATA <= x"C8"; when x"78F" => DATA <= x"B9"; when x"790" => DATA <= x"00"; when x"791" => DATA <= x"01"; when x"792" => DATA <= x"C9"; when x"793" => DATA <= x"0D"; when x"794" => DATA <= x"F0"; when x"795" => DATA <= x"14"; when x"796" => DATA <= x"9D"; when x"797" => DATA <= x"40"; when x"798" => DATA <= x"01"; when x"799" => DATA <= x"E8"; when x"79A" => DATA <= x"C9"; when x"79B" => DATA <= x"22"; when x"79C" => DATA <= x"D0"; when x"79D" => DATA <= x"F0"; when x"79E" => DATA <= x"CA"; when x"79F" => DATA <= x"C8"; when x"7A0" => DATA <= x"B9"; when x"7A1" => DATA <= x"00"; when x"7A2" => DATA <= x"01"; when x"7A3" => DATA <= x"C9"; when x"7A4" => DATA <= x"22"; when x"7A5" => DATA <= x"D0"; when x"7A6" => DATA <= x"D7"; when x"7A7" => DATA <= x"E8"; when x"7A8" => DATA <= x"B0"; when x"7A9" => DATA <= x"E4"; when x"7AA" => DATA <= x"4C"; when x"7AB" => DATA <= x"9E"; when x"7AC" => DATA <= x"E5"; when x"7AD" => DATA <= x"B9"; when x"7AE" => DATA <= x"0F"; when x"7AF" => DATA <= x"20"; when x"7B0" => DATA <= x"30"; when x"7B1" => DATA <= x"19"; when x"7B2" => DATA <= x"B9"; when x"7B3" => DATA <= x"10"; when x"7B4" => DATA <= x"20"; when x"7B5" => DATA <= x"99"; when x"7B6" => DATA <= x"08"; when x"7B7" => DATA <= x"20"; when x"7B8" => DATA <= x"B9"; when x"7B9" => DATA <= x"10"; when x"7BA" => DATA <= x"21"; when x"7BB" => DATA <= x"99"; when x"7BC" => DATA <= x"08"; when x"7BD" => DATA <= x"21"; when x"7BE" => DATA <= x"C8"; when x"7BF" => DATA <= x"CC"; when x"7C0" => DATA <= x"05"; when x"7C1" => DATA <= x"21"; when x"7C2" => DATA <= x"90"; when x"7C3" => DATA <= x"EE"; when x"7C4" => DATA <= x"98"; when x"7C5" => DATA <= x"E9"; when x"7C6" => DATA <= x"08"; when x"7C7" => DATA <= x"8D"; when x"7C8" => DATA <= x"05"; when x"7C9" => DATA <= x"21"; when x"7CA" => DATA <= x"60"; when x"7CB" => DATA <= x"4C"; when x"7CC" => DATA <= x"D0"; when x"7CD" => DATA <= x"E2"; when x"7CE" => DATA <= x"53"; when x"7CF" => DATA <= x"44"; when x"7D0" => DATA <= x"44"; when x"7D1" => DATA <= x"4F"; when x"7D2" => DATA <= x"53"; when x"7D3" => DATA <= x"20"; when x"7D4" => DATA <= x"20"; when x"7D5" => DATA <= x"20"; when x"7D6" => DATA <= x"20"; when x"7D7" => DATA <= x"24"; when x"7D8" => DATA <= x"EE"; when x"7D9" => DATA <= x"20"; when x"7DA" => DATA <= x"01"; when x"7DB" => DATA <= x"EC"; when x"7DC" => DATA <= x"A0"; when x"7DD" => DATA <= x"07"; when x"7DE" => DATA <= x"B9"; when x"7DF" => DATA <= x"08"; when x"7E0" => DATA <= x"23"; when x"7E1" => DATA <= x"D9"; when x"7E2" => DATA <= x"CE"; when x"7E3" => DATA <= x"E7"; when x"7E4" => DATA <= x"F0"; when x"7E5" => DATA <= x"0F"; when x"7E6" => DATA <= x"20"; when x"7E7" => DATA <= x"D1"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"53"; when x"7EA" => DATA <= x"44"; when x"7EB" => DATA <= x"20"; when x"7EC" => DATA <= x"46"; when x"7ED" => DATA <= x"4F"; when x"7EE" => DATA <= x"52"; when x"7EF" => DATA <= x"4D"; when x"7F0" => DATA <= x"41"; when x"7F1" => DATA <= x"54"; when x"7F2" => DATA <= x"3F"; when x"7F3" => DATA <= x"EA"; when x"7F4" => DATA <= x"00"; when x"7F5" => DATA <= x"88"; when x"7F6" => DATA <= x"10"; when x"7F7" => DATA <= x"E6"; when x"7F8" => DATA <= x"A0"; when x"7F9" => DATA <= x"07"; when x"7FA" => DATA <= x"B9"; when x"7FB" => DATA <= x"00"; when x"7FC" => DATA <= x"23"; when x"7FD" => DATA <= x"99"; when x"7FE" => DATA <= x"F0"; when x"7FF" => DATA <= x"00"; when x"800" => DATA <= x"88"; when x"801" => DATA <= x"10"; when x"802" => DATA <= x"F7"; when x"803" => DATA <= x"A9"; when x"804" => DATA <= x"70"; when x"805" => DATA <= x"8D"; when x"806" => DATA <= x"06"; when x"807" => DATA <= x"02"; when x"808" => DATA <= x"A9"; when x"809" => DATA <= x"E0"; when x"80A" => DATA <= x"8D"; when x"80B" => DATA <= x"07"; when x"80C" => DATA <= x"02"; when x"80D" => DATA <= x"A2"; when x"80E" => DATA <= x"03"; when x"80F" => DATA <= x"BD"; when x"810" => DATA <= x"2D"; when x"811" => DATA <= x"E8"; when x"812" => DATA <= x"9D"; when x"813" => DATA <= x"0C"; when x"814" => DATA <= x"02"; when x"815" => DATA <= x"CA"; when x"816" => DATA <= x"10"; when x"817" => DATA <= x"F7"; when x"818" => DATA <= x"A9"; when x"819" => DATA <= x"20"; when x"81A" => DATA <= x"85"; when x"81B" => DATA <= x"AC"; when x"81C" => DATA <= x"85"; when x"81D" => DATA <= x"AD"; when x"81E" => DATA <= x"49"; when x"81F" => DATA <= x"20"; when x"820" => DATA <= x"85"; when x"821" => DATA <= x"EE"; when x"822" => DATA <= x"85"; when x"823" => DATA <= x"C0"; when x"824" => DATA <= x"85"; when x"825" => DATA <= x"B9"; when x"826" => DATA <= x"85"; when x"827" => DATA <= x"BA"; when x"828" => DATA <= x"A0"; when x"829" => DATA <= x"FF"; when x"82A" => DATA <= x"84"; when x"82B" => DATA <= x"EF"; when x"82C" => DATA <= x"60"; when x"82D" => DATA <= x"26"; when x"82E" => DATA <= x"E3"; when x"82F" => DATA <= x"08"; when x"830" => DATA <= x"E4"; when x"831" => DATA <= x"20"; when x"832" => DATA <= x"3E"; when x"833" => DATA <= x"ED"; when x"834" => DATA <= x"20"; when x"835" => DATA <= x"55"; when x"836" => DATA <= x"ED"; when x"837" => DATA <= x"20"; when x"838" => DATA <= x"F0"; when x"839" => DATA <= x"ED"; when x"83A" => DATA <= x"A2"; when x"83B" => DATA <= x"FF"; when x"83C" => DATA <= x"A5"; when x"83D" => DATA <= x"83"; when x"83E" => DATA <= x"C5"; when x"83F" => DATA <= x"F1"; when x"840" => DATA <= x"D0"; when x"841" => DATA <= x"0D"; when x"842" => DATA <= x"A5"; when x"843" => DATA <= x"82"; when x"844" => DATA <= x"C5"; when x"845" => DATA <= x"F0"; when x"846" => DATA <= x"D0"; when x"847" => DATA <= x"07"; when x"848" => DATA <= x"86"; when x"849" => DATA <= x"F0"; when x"84A" => DATA <= x"86"; when x"84B" => DATA <= x"F1"; when x"84C" => DATA <= x"4C"; when x"84D" => DATA <= x"85"; when x"84E" => DATA <= x"E8"; when x"84F" => DATA <= x"A5"; when x"850" => DATA <= x"83"; when x"851" => DATA <= x"C5"; when x"852" => DATA <= x"F3"; when x"853" => DATA <= x"D0"; when x"854" => DATA <= x"0D"; when x"855" => DATA <= x"A5"; when x"856" => DATA <= x"82"; when x"857" => DATA <= x"C5"; when x"858" => DATA <= x"F2"; when x"859" => DATA <= x"D0"; when x"85A" => DATA <= x"07"; when x"85B" => DATA <= x"86"; when x"85C" => DATA <= x"F2"; when x"85D" => DATA <= x"86"; when x"85E" => DATA <= x"F3"; when x"85F" => DATA <= x"4C"; when x"860" => DATA <= x"85"; when x"861" => DATA <= x"E8"; when x"862" => DATA <= x"A5"; when x"863" => DATA <= x"83"; when x"864" => DATA <= x"C5"; when x"865" => DATA <= x"F5"; when x"866" => DATA <= x"D0"; when x"867" => DATA <= x"0D"; when x"868" => DATA <= x"A5"; when x"869" => DATA <= x"82"; when x"86A" => DATA <= x"C5"; when x"86B" => DATA <= x"F4"; when x"86C" => DATA <= x"D0"; when x"86D" => DATA <= x"07"; when x"86E" => DATA <= x"86"; when x"86F" => DATA <= x"F4"; when x"870" => DATA <= x"86"; when x"871" => DATA <= x"F5"; when x"872" => DATA <= x"4C"; when x"873" => DATA <= x"85"; when x"874" => DATA <= x"E8"; when x"875" => DATA <= x"A5"; when x"876" => DATA <= x"83"; when x"877" => DATA <= x"C5"; when x"878" => DATA <= x"F7"; when x"879" => DATA <= x"D0"; when x"87A" => DATA <= x"0A"; when x"87B" => DATA <= x"A5"; when x"87C" => DATA <= x"82"; when x"87D" => DATA <= x"C5"; when x"87E" => DATA <= x"F6"; when x"87F" => DATA <= x"D0"; when x"880" => DATA <= x"04"; when x"881" => DATA <= x"86"; when x"882" => DATA <= x"F6"; when x"883" => DATA <= x"86"; when x"884" => DATA <= x"F7"; when x"885" => DATA <= x"A5"; when x"886" => DATA <= x"80"; when x"887" => DATA <= x"0A"; when x"888" => DATA <= x"AA"; when x"889" => DATA <= x"A5"; when x"88A" => DATA <= x"82"; when x"88B" => DATA <= x"95"; when x"88C" => DATA <= x"F0"; when x"88D" => DATA <= x"A5"; when x"88E" => DATA <= x"83"; when x"88F" => DATA <= x"95"; when x"890" => DATA <= x"F1"; when x"891" => DATA <= x"4C"; when x"892" => DATA <= x"E0"; when x"893" => DATA <= x"EB"; when x"894" => DATA <= x"20"; when x"895" => DATA <= x"55"; when x"896" => DATA <= x"ED"; when x"897" => DATA <= x"A5"; when x"898" => DATA <= x"82"; when x"899" => DATA <= x"85"; when x"89A" => DATA <= x"92"; when x"89B" => DATA <= x"A5"; when x"89C" => DATA <= x"83"; when x"89D" => DATA <= x"85"; when x"89E" => DATA <= x"93"; when x"89F" => DATA <= x"20"; when x"8A0" => DATA <= x"55"; when x"8A1" => DATA <= x"ED"; when x"8A2" => DATA <= x"A5"; when x"8A3" => DATA <= x"82"; when x"8A4" => DATA <= x"85"; when x"8A5" => DATA <= x"94"; when x"8A6" => DATA <= x"A5"; when x"8A7" => DATA <= x"83"; when x"8A8" => DATA <= x"85"; when x"8A9" => DATA <= x"95"; when x"8AA" => DATA <= x"20"; when x"8AB" => DATA <= x"76"; when x"8AC" => DATA <= x"F8"; when x"8AD" => DATA <= x"C9"; when x"8AE" => DATA <= x"0D"; when x"8AF" => DATA <= x"F0"; when x"8B0" => DATA <= x"19"; when x"8B1" => DATA <= x"A4"; when x"8B2" => DATA <= x"03"; when x"8B3" => DATA <= x"B1"; when x"8B4" => DATA <= x"05"; when x"8B5" => DATA <= x"C9"; when x"8B6" => DATA <= x"0D"; when x"8B7" => DATA <= x"F0"; when x"8B8" => DATA <= x"11"; when x"8B9" => DATA <= x"85"; when x"8BA" => DATA <= x"96"; when x"8BB" => DATA <= x"C8"; when x"8BC" => DATA <= x"B1"; when x"8BD" => DATA <= x"05"; when x"8BE" => DATA <= x"C9"; when x"8BF" => DATA <= x"0D"; when x"8C0" => DATA <= x"D0"; when x"8C1" => DATA <= x"71"; when x"8C2" => DATA <= x"84"; when x"8C3" => DATA <= x"03"; when x"8C4" => DATA <= x"20"; when x"8C5" => DATA <= x"31"; when x"8C6" => DATA <= x"C2"; when x"8C7" => DATA <= x"4C"; when x"8C8" => DATA <= x"CE"; when x"8C9" => DATA <= x"E8"; when x"8CA" => DATA <= x"A2"; when x"8CB" => DATA <= x"00"; when x"8CC" => DATA <= x"86"; when x"8CD" => DATA <= x"96"; when x"8CE" => DATA <= x"20"; when x"8CF" => DATA <= x"ED"; when x"8D0" => DATA <= x"FF"; when x"8D1" => DATA <= x"A9"; when x"8D2" => DATA <= x"00"; when x"8D3" => DATA <= x"85"; when x"8D4" => DATA <= x"90"; when x"8D5" => DATA <= x"85"; when x"8D6" => DATA <= x"91"; when x"8D7" => DATA <= x"A6"; when x"8D8" => DATA <= x"92"; when x"8D9" => DATA <= x"A4"; when x"8DA" => DATA <= x"93"; when x"8DB" => DATA <= x"20"; when x"8DC" => DATA <= x"0D"; when x"8DD" => DATA <= x"EC"; when x"8DE" => DATA <= x"A0"; when x"8DF" => DATA <= x"0F"; when x"8E0" => DATA <= x"B1"; when x"8E1" => DATA <= x"87"; when x"8E2" => DATA <= x"30"; when x"8E3" => DATA <= x"1C"; when x"8E4" => DATA <= x"A5"; when x"8E5" => DATA <= x"96"; when x"8E6" => DATA <= x"F0"; when x"8E7" => DATA <= x"08"; when x"8E8" => DATA <= x"A0"; when x"8E9" => DATA <= x"00"; when x"8EA" => DATA <= x"B1"; when x"8EB" => DATA <= x"87"; when x"8EC" => DATA <= x"C5"; when x"8ED" => DATA <= x"96"; when x"8EE" => DATA <= x"D0"; when x"8EF" => DATA <= x"10"; when x"8F0" => DATA <= x"A6"; when x"8F1" => DATA <= x"92"; when x"8F2" => DATA <= x"A4"; when x"8F3" => DATA <= x"93"; when x"8F4" => DATA <= x"20"; when x"8F5" => DATA <= x"B7"; when x"8F6" => DATA <= x"ED"; when x"8F7" => DATA <= x"20"; when x"8F8" => DATA <= x"ED"; when x"8F9" => DATA <= x"FF"; when x"8FA" => DATA <= x"E6"; when x"8FB" => DATA <= x"90"; when x"8FC" => DATA <= x"D0"; when x"8FD" => DATA <= x"02"; when x"8FE" => DATA <= x"E6"; when x"8FF" => DATA <= x"91"; when x"900" => DATA <= x"E6"; when x"901" => DATA <= x"92"; when x"902" => DATA <= x"D0"; when x"903" => DATA <= x"02"; when x"904" => DATA <= x"E6"; when x"905" => DATA <= x"93"; when x"906" => DATA <= x"A5"; when x"907" => DATA <= x"93"; when x"908" => DATA <= x"C5"; when x"909" => DATA <= x"95"; when x"90A" => DATA <= x"90"; when x"90B" => DATA <= x"CB"; when x"90C" => DATA <= x"D0"; when x"90D" => DATA <= x"08"; when x"90E" => DATA <= x"A5"; when x"90F" => DATA <= x"92"; when x"910" => DATA <= x"C5"; when x"911" => DATA <= x"94"; when x"912" => DATA <= x"90"; when x"913" => DATA <= x"C3"; when x"914" => DATA <= x"F0"; when x"915" => DATA <= x"C1"; when x"916" => DATA <= x"20"; when x"917" => DATA <= x"ED"; when x"918" => DATA <= x"FF"; when x"919" => DATA <= x"20"; when x"91A" => DATA <= x"D1"; when x"91B" => DATA <= x"F7"; when x"91C" => DATA <= x"44"; when x"91D" => DATA <= x"49"; when x"91E" => DATA <= x"53"; when x"91F" => DATA <= x"4B"; when x"920" => DATA <= x"53"; when x"921" => DATA <= x"20"; when x"922" => DATA <= x"46"; when x"923" => DATA <= x"4F"; when x"924" => DATA <= x"55"; when x"925" => DATA <= x"4E"; when x"926" => DATA <= x"44"; when x"927" => DATA <= x"3A"; when x"928" => DATA <= x"EA"; when x"929" => DATA <= x"A6"; when x"92A" => DATA <= x"90"; when x"92B" => DATA <= x"A4"; when x"92C" => DATA <= x"91"; when x"92D" => DATA <= x"20"; when x"92E" => DATA <= x"88"; when x"92F" => DATA <= x"ED"; when x"930" => DATA <= x"4C"; when x"931" => DATA <= x"ED"; when x"932" => DATA <= x"FF"; when x"933" => DATA <= x"20"; when x"934" => DATA <= x"D1"; when x"935" => DATA <= x"F7"; when x"936" => DATA <= x"46"; when x"937" => DATA <= x"49"; when x"938" => DATA <= x"4C"; when x"939" => DATA <= x"54"; when x"93A" => DATA <= x"45"; when x"93B" => DATA <= x"52"; when x"93C" => DATA <= x"3F"; when x"93D" => DATA <= x"EA"; when x"93E" => DATA <= x"00"; when x"93F" => DATA <= x"20"; when x"940" => DATA <= x"F0"; when x"941" => DATA <= x"ED"; when x"942" => DATA <= x"A2"; when x"943" => DATA <= x"00"; when x"944" => DATA <= x"86"; when x"945" => DATA <= x"80"; when x"946" => DATA <= x"A5"; when x"947" => DATA <= x"80"; when x"948" => DATA <= x"48"; when x"949" => DATA <= x"20"; when x"94A" => DATA <= x"0B"; when x"94B" => DATA <= x"F8"; when x"94C" => DATA <= x"A9"; when x"94D" => DATA <= x"3A"; when x"94E" => DATA <= x"20"; when x"94F" => DATA <= x"F4"; when x"950" => DATA <= x"FF"; when x"951" => DATA <= x"68"; when x"952" => DATA <= x"20"; when x"953" => DATA <= x"AA"; when x"954" => DATA <= x"ED"; when x"955" => DATA <= x"30"; when x"956" => DATA <= x"18"; when x"957" => DATA <= x"20"; when x"958" => DATA <= x"16"; when x"959" => DATA <= x"EC"; when x"95A" => DATA <= x"A0"; when x"95B" => DATA <= x"0F"; when x"95C" => DATA <= x"B1"; when x"95D" => DATA <= x"87"; when x"95E" => DATA <= x"C9"; when x"95F" => DATA <= x"FF"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"0D"; when x"962" => DATA <= x"A6"; when x"963" => DATA <= x"82"; when x"964" => DATA <= x"A4"; when x"965" => DATA <= x"83"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"B7"; when x"968" => DATA <= x"ED"; when x"969" => DATA <= x"20"; when x"96A" => DATA <= x"ED"; when x"96B" => DATA <= x"FF"; when x"96C" => DATA <= x"4C"; when x"96D" => DATA <= x"7A"; when x"96E" => DATA <= x"E9"; when x"96F" => DATA <= x"20"; when x"970" => DATA <= x"D1"; when x"971" => DATA <= x"F7"; when x"972" => DATA <= x"20"; when x"973" => DATA <= x"20"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"2D"; when x"976" => DATA <= x"EA"; when x"977" => DATA <= x"20"; when x"978" => DATA <= x"ED"; when x"979" => DATA <= x"FF"; when x"97A" => DATA <= x"E6"; when x"97B" => DATA <= x"80"; when x"97C" => DATA <= x"A5"; when x"97D" => DATA <= x"80"; when x"97E" => DATA <= x"C9"; when x"97F" => DATA <= x"04"; when x"980" => DATA <= x"D0"; when x"981" => DATA <= x"C4"; when x"982" => DATA <= x"4C"; when x"983" => DATA <= x"ED"; when x"984" => DATA <= x"FF"; when x"985" => DATA <= x"20"; when x"986" => DATA <= x"55"; when x"987" => DATA <= x"ED"; when x"988" => DATA <= x"20"; when x"989" => DATA <= x"F0"; when x"98A" => DATA <= x"ED"; when x"98B" => DATA <= x"20"; when x"98C" => DATA <= x"16"; when x"98D" => DATA <= x"EC"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"68"; when x"990" => DATA <= x"E6"; when x"991" => DATA <= x"A0"; when x"992" => DATA <= x"0F"; when x"993" => DATA <= x"A9"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"91"; when x"996" => DATA <= x"87"; when x"997" => DATA <= x"20"; when x"998" => DATA <= x"26"; when x"999" => DATA <= x"EC"; when x"99A" => DATA <= x"4C"; when x"99B" => DATA <= x"E0"; when x"99C" => DATA <= x"EB"; when x"99D" => DATA <= x"20"; when x"99E" => DATA <= x"55"; when x"99F" => DATA <= x"ED"; when x"9A0" => DATA <= x"20"; when x"9A1" => DATA <= x"F0"; when x"9A2" => DATA <= x"ED"; when x"9A3" => DATA <= x"20"; when x"9A4" => DATA <= x"16"; when x"9A5" => DATA <= x"EC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"68"; when x"9A8" => DATA <= x"E6"; when x"9A9" => DATA <= x"A0"; when x"9AA" => DATA <= x"0F"; when x"9AB" => DATA <= x"A9"; when x"9AC" => DATA <= x"0F"; when x"9AD" => DATA <= x"91"; when x"9AE" => DATA <= x"87"; when x"9AF" => DATA <= x"20"; when x"9B0" => DATA <= x"26"; when x"9B1" => DATA <= x"EC"; when x"9B2" => DATA <= x"4C"; when x"9B3" => DATA <= x"E0"; when x"9B4" => DATA <= x"EB"; when x"9B5" => DATA <= x"20"; when x"9B6" => DATA <= x"F0"; when x"9B7" => DATA <= x"ED"; when x"9B8" => DATA <= x"A9"; when x"9B9" => DATA <= x"00"; when x"9BA" => DATA <= x"85"; when x"9BB" => DATA <= x"90"; when x"9BC" => DATA <= x"85"; when x"9BD" => DATA <= x"91"; when x"9BE" => DATA <= x"85"; when x"9BF" => DATA <= x"92"; when x"9C0" => DATA <= x"85"; when x"9C1" => DATA <= x"93"; when x"9C2" => DATA <= x"85"; when x"9C3" => DATA <= x"94"; when x"9C4" => DATA <= x"85"; when x"9C5" => DATA <= x"95"; when x"9C6" => DATA <= x"A6"; when x"9C7" => DATA <= x"94"; when x"9C8" => DATA <= x"A4"; when x"9C9" => DATA <= x"95"; when x"9CA" => DATA <= x"20"; when x"9CB" => DATA <= x"0D"; when x"9CC" => DATA <= x"EC"; when x"9CD" => DATA <= x"A0"; when x"9CE" => DATA <= x"0F"; when x"9CF" => DATA <= x"B1"; when x"9D0" => DATA <= x"87"; when x"9D1" => DATA <= x"C9"; when x"9D2" => DATA <= x"FF"; when x"9D3" => DATA <= x"F0"; when x"9D4" => DATA <= x"10"; when x"9D5" => DATA <= x"E6"; when x"9D6" => DATA <= x"90"; when x"9D7" => DATA <= x"D0"; when x"9D8" => DATA <= x"02"; when x"9D9" => DATA <= x"E6"; when x"9DA" => DATA <= x"91"; when x"9DB" => DATA <= x"29"; when x"9DC" => DATA <= x"F0"; when x"9DD" => DATA <= x"F0"; when x"9DE" => DATA <= x"06"; when x"9DF" => DATA <= x"E6"; when x"9E0" => DATA <= x"92"; when x"9E1" => DATA <= x"D0"; when x"9E2" => DATA <= x"02"; when x"9E3" => DATA <= x"E6"; when x"9E4" => DATA <= x"93"; when x"9E5" => DATA <= x"E6"; when x"9E6" => DATA <= x"94"; when x"9E7" => DATA <= x"D0"; when x"9E8" => DATA <= x"02"; when x"9E9" => DATA <= x"E6"; when x"9EA" => DATA <= x"95"; when x"9EB" => DATA <= x"A5"; when x"9EC" => DATA <= x"95"; when x"9ED" => DATA <= x"C9"; when x"9EE" => DATA <= x"03"; when x"9EF" => DATA <= x"90"; when x"9F0" => DATA <= x"D5"; when x"9F1" => DATA <= x"D0"; when x"9F2" => DATA <= x"08"; when x"9F3" => DATA <= x"A5"; when x"9F4" => DATA <= x"94"; when x"9F5" => DATA <= x"C9"; when x"9F6" => DATA <= x"FE"; when x"9F7" => DATA <= x"90"; when x"9F8" => DATA <= x"CD"; when x"9F9" => DATA <= x"F0"; when x"9FA" => DATA <= x"CB"; when x"9FB" => DATA <= x"A6"; when x"9FC" => DATA <= x"92"; when x"9FD" => DATA <= x"A4"; when x"9FE" => DATA <= x"93"; when x"9FF" => DATA <= x"20"; when x"A00" => DATA <= x"88"; when x"A01" => DATA <= x"ED"; when x"A02" => DATA <= x"20"; when x"A03" => DATA <= x"D1"; when x"A04" => DATA <= x"F7"; when x"A05" => DATA <= x"20"; when x"A06" => DATA <= x"4F"; when x"A07" => DATA <= x"46"; when x"A08" => DATA <= x"20"; when x"A09" => DATA <= x"EA"; when x"A0A" => DATA <= x"A6"; when x"A0B" => DATA <= x"90"; when x"A0C" => DATA <= x"A4"; when x"A0D" => DATA <= x"91"; when x"A0E" => DATA <= x"20"; when x"A0F" => DATA <= x"88"; when x"A10" => DATA <= x"ED"; when x"A11" => DATA <= x"20"; when x"A12" => DATA <= x"D1"; when x"A13" => DATA <= x"F7"; when x"A14" => DATA <= x"20"; when x"A15" => DATA <= x"44"; when x"A16" => DATA <= x"49"; when x"A17" => DATA <= x"53"; when x"A18" => DATA <= x"4B"; when x"A19" => DATA <= x"53"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"46"; when x"A1C" => DATA <= x"52"; when x"A1D" => DATA <= x"45"; when x"A1E" => DATA <= x"45"; when x"A1F" => DATA <= x"EA"; when x"A20" => DATA <= x"4C"; when x"A21" => DATA <= x"ED"; when x"A22" => DATA <= x"FF"; when x"A23" => DATA <= x"20"; when x"A24" => DATA <= x"55"; when x"A25" => DATA <= x"ED"; when x"A26" => DATA <= x"20"; when x"A27" => DATA <= x"F0"; when x"A28" => DATA <= x"ED"; when x"A29" => DATA <= x"20"; when x"A2A" => DATA <= x"16"; when x"A2B" => DATA <= x"EC"; when x"A2C" => DATA <= x"20"; when x"A2D" => DATA <= x"68"; when x"A2E" => DATA <= x"E6"; when x"A2F" => DATA <= x"20"; when x"A30" => DATA <= x"7E"; when x"A31" => DATA <= x"E6"; when x"A32" => DATA <= x"20"; when x"A33" => DATA <= x"D1"; when x"A34" => DATA <= x"F7"; when x"A35" => DATA <= x"4B"; when x"A36" => DATA <= x"49"; when x"A37" => DATA <= x"4C"; when x"A38" => DATA <= x"4C"; when x"A39" => DATA <= x"20"; when x"A3A" => DATA <= x"44"; when x"A3B" => DATA <= x"49"; when x"A3C" => DATA <= x"53"; when x"A3D" => DATA <= x"4B"; when x"A3E" => DATA <= x"3A"; when x"A3F" => DATA <= x"EA"; when x"A40" => DATA <= x"20"; when x"A41" => DATA <= x"A3"; when x"A42" => DATA <= x"ED"; when x"A43" => DATA <= x"20"; when x"A44" => DATA <= x"F5"; when x"A45" => DATA <= x"ED"; when x"A46" => DATA <= x"48"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"F4"; when x"A49" => DATA <= x"FF"; when x"A4A" => DATA <= x"68"; when x"A4B" => DATA <= x"C9"; when x"A4C" => DATA <= x"59"; when x"A4D" => DATA <= x"F0"; when x"A4E" => DATA <= x"03"; when x"A4F" => DATA <= x"4C"; when x"A50" => DATA <= x"ED"; when x"A51" => DATA <= x"FF"; when x"A52" => DATA <= x"20"; when x"A53" => DATA <= x"ED"; when x"A54" => DATA <= x"FF"; when x"A55" => DATA <= x"A0"; when x"A56" => DATA <= x"0F"; when x"A57" => DATA <= x"A9"; when x"A58" => DATA <= x"F0"; when x"A59" => DATA <= x"91"; when x"A5A" => DATA <= x"87"; when x"A5B" => DATA <= x"20"; when x"A5C" => DATA <= x"26"; when x"A5D" => DATA <= x"EC"; when x"A5E" => DATA <= x"4C"; when x"A5F" => DATA <= x"E0"; when x"A60" => DATA <= x"EB"; when x"A61" => DATA <= x"20"; when x"A62" => DATA <= x"55"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"20"; when x"A65" => DATA <= x"F0"; when x"A66" => DATA <= x"ED"; when x"A67" => DATA <= x"20"; when x"A68" => DATA <= x"16"; when x"A69" => DATA <= x"EC"; when x"A6A" => DATA <= x"A0"; when x"A6B" => DATA <= x"0F"; when x"A6C" => DATA <= x"A9"; when x"A6D" => DATA <= x"0F"; when x"A6E" => DATA <= x"91"; when x"A6F" => DATA <= x"87"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"26"; when x"A72" => DATA <= x"EC"; when x"A73" => DATA <= x"4C"; when x"A74" => DATA <= x"E0"; when x"A75" => DATA <= x"EB"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"E0"; when x"A78" => DATA <= x"E2"; when x"A79" => DATA <= x"20"; when x"A7A" => DATA <= x"F0"; when x"A7B" => DATA <= x"ED"; when x"A7C" => DATA <= x"A9"; when x"A7D" => DATA <= x"00"; when x"A7E" => DATA <= x"85"; when x"A7F" => DATA <= x"90"; when x"A80" => DATA <= x"85"; when x"A81" => DATA <= x"91"; when x"A82" => DATA <= x"A6"; when x"A83" => DATA <= x"90"; when x"A84" => DATA <= x"A4"; when x"A85" => DATA <= x"91"; when x"A86" => DATA <= x"20"; when x"A87" => DATA <= x"0D"; when x"A88" => DATA <= x"EC"; when x"A89" => DATA <= x"A0"; when x"A8A" => DATA <= x"0F"; when x"A8B" => DATA <= x"B1"; when x"A8C" => DATA <= x"87"; when x"A8D" => DATA <= x"C9"; when x"A8E" => DATA <= x"F0"; when x"A8F" => DATA <= x"F0"; when x"A90" => DATA <= x"2A"; when x"A91" => DATA <= x"E6"; when x"A92" => DATA <= x"90"; when x"A93" => DATA <= x"D0"; when x"A94" => DATA <= x"02"; when x"A95" => DATA <= x"E6"; when x"A96" => DATA <= x"91"; when x"A97" => DATA <= x"A5"; when x"A98" => DATA <= x"91"; when x"A99" => DATA <= x"C9"; when x"A9A" => DATA <= x"03"; when x"A9B" => DATA <= x"90"; when x"A9C" => DATA <= x"E5"; when x"A9D" => DATA <= x"D0"; when x"A9E" => DATA <= x"08"; when x"A9F" => DATA <= x"A5"; when x"AA0" => DATA <= x"90"; when x"AA1" => DATA <= x"C9"; when x"AA2" => DATA <= x"FE"; when x"AA3" => DATA <= x"90"; when x"AA4" => DATA <= x"DD"; when x"AA5" => DATA <= x"F0"; when x"AA6" => DATA <= x"DB"; when x"AA7" => DATA <= x"20"; when x"AA8" => DATA <= x"D1"; when x"AA9" => DATA <= x"F7"; when x"AAA" => DATA <= x"4E"; when x"AAB" => DATA <= x"4F"; when x"AAC" => DATA <= x"20"; when x"AAD" => DATA <= x"44"; when x"AAE" => DATA <= x"49"; when x"AAF" => DATA <= x"53"; when x"AB0" => DATA <= x"4B"; when x"AB1" => DATA <= x"20"; when x"AB2" => DATA <= x"46"; when x"AB3" => DATA <= x"4F"; when x"AB4" => DATA <= x"55"; when x"AB5" => DATA <= x"4E"; when x"AB6" => DATA <= x"44"; when x"AB7" => DATA <= x"EA"; when x"AB8" => DATA <= x"4C"; when x"AB9" => DATA <= x"EB"; when x"ABA" => DATA <= x"EA"; when x"ABB" => DATA <= x"A5"; when x"ABC" => DATA <= x"90"; when x"ABD" => DATA <= x"85"; when x"ABE" => DATA <= x"82"; when x"ABF" => DATA <= x"A5"; when x"AC0" => DATA <= x"91"; when x"AC1" => DATA <= x"85"; when x"AC2" => DATA <= x"83"; when x"AC3" => DATA <= x"A5"; when x"AC4" => DATA <= x"EE"; when x"AC5" => DATA <= x"85"; when x"AC6" => DATA <= x"80"; when x"AC7" => DATA <= x"A9"; when x"AC8" => DATA <= x"00"; when x"AC9" => DATA <= x"20"; when x"ACA" => DATA <= x"3A"; when x"ACB" => DATA <= x"E8"; when x"ACC" => DATA <= x"20"; when x"ACD" => DATA <= x"D1"; when x"ACE" => DATA <= x"F7"; when x"ACF" => DATA <= x"44"; when x"AD0" => DATA <= x"49"; when x"AD1" => DATA <= x"53"; when x"AD2" => DATA <= x"4B"; when x"AD3" => DATA <= x"20"; when x"AD4" => DATA <= x"EA"; when x"AD5" => DATA <= x"20"; when x"AD6" => DATA <= x"A3"; when x"AD7" => DATA <= x"ED"; when x"AD8" => DATA <= x"20"; when x"AD9" => DATA <= x"D1"; when x"ADA" => DATA <= x"F7"; when x"ADB" => DATA <= x"20"; when x"ADC" => DATA <= x"49"; when x"ADD" => DATA <= x"4E"; when x"ADE" => DATA <= x"20"; when x"ADF" => DATA <= x"44"; when x"AE0" => DATA <= x"52"; when x"AE1" => DATA <= x"49"; when x"AE2" => DATA <= x"56"; when x"AE3" => DATA <= x"45"; when x"AE4" => DATA <= x"20"; when x"AE5" => DATA <= x"EA"; when x"AE6" => DATA <= x"A5"; when x"AE7" => DATA <= x"EE"; when x"AE8" => DATA <= x"20"; when x"AE9" => DATA <= x"0B"; when x"AEA" => DATA <= x"F8"; when x"AEB" => DATA <= x"4C"; when x"AEC" => DATA <= x"ED"; when x"AED" => DATA <= x"FF"; when x"AEE" => DATA <= x"20"; when x"AEF" => DATA <= x"55"; when x"AF0" => DATA <= x"ED"; when x"AF1" => DATA <= x"20"; when x"AF2" => DATA <= x"F0"; when x"AF3" => DATA <= x"ED"; when x"AF4" => DATA <= x"20"; when x"AF5" => DATA <= x"16"; when x"AF6" => DATA <= x"EC"; when x"AF7" => DATA <= x"20"; when x"AF8" => DATA <= x"68"; when x"AF9" => DATA <= x"E6"; when x"AFA" => DATA <= x"20"; when x"AFB" => DATA <= x"7E"; when x"AFC" => DATA <= x"E6"; when x"AFD" => DATA <= x"20"; when x"AFE" => DATA <= x"D1"; when x"AFF" => DATA <= x"F7"; when x"B00" => DATA <= x"46"; when x"B01" => DATA <= x"4F"; when x"B02" => DATA <= x"52"; when x"B03" => DATA <= x"4D"; when x"B04" => DATA <= x"41"; when x"B05" => DATA <= x"54"; when x"B06" => DATA <= x"20"; when x"B07" => DATA <= x"44"; when x"B08" => DATA <= x"49"; when x"B09" => DATA <= x"53"; when x"B0A" => DATA <= x"4B"; when x"B0B" => DATA <= x"3A"; when x"B0C" => DATA <= x"EA"; when x"B0D" => DATA <= x"20"; when x"B0E" => DATA <= x"A3"; when x"B0F" => DATA <= x"ED"; when x"B10" => DATA <= x"20"; when x"B11" => DATA <= x"F5"; when x"B12" => DATA <= x"ED"; when x"B13" => DATA <= x"48"; when x"B14" => DATA <= x"20"; when x"B15" => DATA <= x"F4"; when x"B16" => DATA <= x"FF"; when x"B17" => DATA <= x"68"; when x"B18" => DATA <= x"C9"; when x"B19" => DATA <= x"59"; when x"B1A" => DATA <= x"F0"; when x"B1B" => DATA <= x"03"; when x"B1C" => DATA <= x"4C"; when x"B1D" => DATA <= x"ED"; when x"B1E" => DATA <= x"FF"; when x"B1F" => DATA <= x"20"; when x"B20" => DATA <= x"67"; when x"B21" => DATA <= x"EA"; when x"B22" => DATA <= x"20"; when x"B23" => DATA <= x"ED"; when x"B24" => DATA <= x"FF"; when x"B25" => DATA <= x"A9"; when x"B26" => DATA <= x"20"; when x"B27" => DATA <= x"A2"; when x"B28" => DATA <= x"00"; when x"B29" => DATA <= x"9D"; when x"B2A" => DATA <= x"00"; when x"B2B" => DATA <= x"20"; when x"B2C" => DATA <= x"9D"; when x"B2D" => DATA <= x"00"; when x"B2E" => DATA <= x"21"; when x"B2F" => DATA <= x"E8"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"F7"; when x"B32" => DATA <= x"A9"; when x"B33" => DATA <= x"00"; when x"B34" => DATA <= x"8D"; when x"B35" => DATA <= x"05"; when x"B36" => DATA <= x"21"; when x"B37" => DATA <= x"A9"; when x"B38" => DATA <= x"01"; when x"B39" => DATA <= x"8D"; when x"B3A" => DATA <= x"06"; when x"B3B" => DATA <= x"21"; when x"B3C" => DATA <= x"A9"; when x"B3D" => DATA <= x"90"; when x"B3E" => DATA <= x"8D"; when x"B3F" => DATA <= x"07"; when x"B40" => DATA <= x"21"; when x"B41" => DATA <= x"20"; when x"B42" => DATA <= x"7B"; when x"B43" => DATA <= x"EC"; when x"B44" => DATA <= x"A0"; when x"B45" => DATA <= x"00"; when x"B46" => DATA <= x"A2"; when x"B47" => DATA <= x"00"; when x"B48" => DATA <= x"BD"; when x"B49" => DATA <= x"00"; when x"B4A" => DATA <= x"20"; when x"B4B" => DATA <= x"91"; when x"B4C" => DATA <= x"87"; when x"B4D" => DATA <= x"C8"; when x"B4E" => DATA <= x"E8"; when x"B4F" => DATA <= x"E0"; when x"B50" => DATA <= x"08"; when x"B51" => DATA <= x"D0"; when x"B52" => DATA <= x"F5"; when x"B53" => DATA <= x"BD"; when x"B54" => DATA <= x"F8"; when x"B55" => DATA <= x"20"; when x"B56" => DATA <= x"91"; when x"B57" => DATA <= x"87"; when x"B58" => DATA <= x"C8"; when x"B59" => DATA <= x"E8"; when x"B5A" => DATA <= x"E0"; when x"B5B" => DATA <= x"0D"; when x"B5C" => DATA <= x"D0"; when x"B5D" => DATA <= x"F5"; when x"B5E" => DATA <= x"20"; when x"B5F" => DATA <= x"26"; when x"B60" => DATA <= x"EC"; when x"B61" => DATA <= x"4C"; when x"B62" => DATA <= x"E0"; when x"B63" => DATA <= x"EB"; when x"B64" => DATA <= x"20"; when x"B65" => DATA <= x"3E"; when x"B66" => DATA <= x"ED"; when x"B67" => DATA <= x"20"; when x"B68" => DATA <= x"55"; when x"B69" => DATA <= x"ED"; when x"B6A" => DATA <= x"20"; when x"B6B" => DATA <= x"F0"; when x"B6C" => DATA <= x"ED"; when x"B6D" => DATA <= x"20"; when x"B6E" => DATA <= x"01"; when x"B6F" => DATA <= x"EC"; when x"B70" => DATA <= x"A5"; when x"B71" => DATA <= x"80"; when x"B72" => DATA <= x"0A"; when x"B73" => DATA <= x"A8"; when x"B74" => DATA <= x"A5"; when x"B75" => DATA <= x"82"; when x"B76" => DATA <= x"99"; when x"B77" => DATA <= x"00"; when x"B78" => DATA <= x"23"; when x"B79" => DATA <= x"A5"; when x"B7A" => DATA <= x"83"; when x"B7B" => DATA <= x"99"; when x"B7C" => DATA <= x"01"; when x"B7D" => DATA <= x"23"; when x"B7E" => DATA <= x"4C"; when x"B7F" => DATA <= x"07"; when x"B80" => DATA <= x"EC"; when x"B81" => DATA <= x"20"; when x"B82" => DATA <= x"F0"; when x"B83" => DATA <= x"ED"; when x"B84" => DATA <= x"20"; when x"B85" => DATA <= x"ED"; when x"B86" => DATA <= x"FF"; when x"B87" => DATA <= x"20"; when x"B88" => DATA <= x"D1"; when x"B89" => DATA <= x"F7"; when x"B8A" => DATA <= x"53"; when x"B8B" => DATA <= x"44"; when x"B8C" => DATA <= x"44"; when x"B8D" => DATA <= x"4F"; when x"B8E" => DATA <= x"53"; when x"B8F" => DATA <= x"20"; when x"B90" => DATA <= x"56"; when x"B91" => DATA <= x"32"; when x"B92" => DATA <= x"2E"; when x"B93" => DATA <= x"33"; when x"B94" => DATA <= x"45"; when x"B95" => DATA <= x"EA"; when x"B96" => DATA <= x"20"; when x"B97" => DATA <= x"ED"; when x"B98" => DATA <= x"FF"; when x"B99" => DATA <= x"20"; when x"B9A" => DATA <= x"ED"; when x"B9B" => DATA <= x"FF"; when x"B9C" => DATA <= x"A0"; when x"B9D" => DATA <= x"00"; when x"B9E" => DATA <= x"A2"; when x"B9F" => DATA <= x"0F"; when x"BA0" => DATA <= x"B9"; when x"BA1" => DATA <= x"30"; when x"BA2" => DATA <= x"E1"; when x"BA3" => DATA <= x"30"; when x"BA4" => DATA <= x"08"; when x"BA5" => DATA <= x"20"; when x"BA6" => DATA <= x"F4"; when x"BA7" => DATA <= x"FF"; when x"BA8" => DATA <= x"C8"; when x"BA9" => DATA <= x"CA"; when x"BAA" => DATA <= x"4C"; when x"BAB" => DATA <= x"A0"; when x"BAC" => DATA <= x"EB"; when x"BAD" => DATA <= x"E0"; when x"BAE" => DATA <= x"04"; when x"BAF" => DATA <= x"F0"; when x"BB0" => DATA <= x"08"; when x"BB1" => DATA <= x"A9"; when x"BB2" => DATA <= x"20"; when x"BB3" => DATA <= x"20"; when x"BB4" => DATA <= x"F4"; when x"BB5" => DATA <= x"FF"; when x"BB6" => DATA <= x"CA"; when x"BB7" => DATA <= x"D0"; when x"BB8" => DATA <= x"F4"; when x"BB9" => DATA <= x"B9"; when x"BBA" => DATA <= x"30"; when x"BBB" => DATA <= x"E1"; when x"BBC" => DATA <= x"20"; when x"BBD" => DATA <= x"02"; when x"BBE" => DATA <= x"F8"; when x"BBF" => DATA <= x"B9"; when x"BC0" => DATA <= x"31"; when x"BC1" => DATA <= x"E1"; when x"BC2" => DATA <= x"20"; when x"BC3" => DATA <= x"02"; when x"BC4" => DATA <= x"F8"; when x"BC5" => DATA <= x"A9"; when x"BC6" => DATA <= x"20"; when x"BC7" => DATA <= x"20"; when x"BC8" => DATA <= x"F4"; when x"BC9" => DATA <= x"FF"; when x"BCA" => DATA <= x"C8"; when x"BCB" => DATA <= x"C8"; when x"BCC" => DATA <= x"B9"; when x"BCD" => DATA <= x"30"; when x"BCE" => DATA <= x"E1"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"E6"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"07"; when x"BD3" => DATA <= x"B9"; when x"BD4" => DATA <= x"31"; when x"BD5" => DATA <= x"E1"; when x"BD6" => DATA <= x"C9"; when x"BD7" => DATA <= x"20"; when x"BD8" => DATA <= x"F0"; when x"BD9" => DATA <= x"03"; when x"BDA" => DATA <= x"4C"; when x"BDB" => DATA <= x"9E"; when x"BDC" => DATA <= x"EB"; when x"BDD" => DATA <= x"4C"; when x"BDE" => DATA <= x"ED"; when x"BDF" => DATA <= x"FF"; when x"BE0" => DATA <= x"A5"; when x"BE1" => DATA <= x"EE"; when x"BE2" => DATA <= x"29"; when x"BE3" => DATA <= x"03"; when x"BE4" => DATA <= x"85"; when x"BE5" => DATA <= x"EE"; when x"BE6" => DATA <= x"60"; when x"BE7" => DATA <= x"A9"; when x"BE8" => DATA <= x"00"; when x"BE9" => DATA <= x"85"; when x"BEA" => DATA <= x"84"; when x"BEB" => DATA <= x"85"; when x"BEC" => DATA <= x"85"; when x"BED" => DATA <= x"85"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"A9"; when x"BF0" => DATA <= x"00"; when x"BF1" => DATA <= x"85"; when x"BF2" => DATA <= x"F9"; when x"BF3" => DATA <= x"A9"; when x"BF4" => DATA <= x"23"; when x"BF5" => DATA <= x"85"; when x"BF6" => DATA <= x"FA"; when x"BF7" => DATA <= x"60"; when x"BF8" => DATA <= x"A9"; when x"BF9" => DATA <= x"00"; when x"BFA" => DATA <= x"85"; when x"BFB" => DATA <= x"F9"; when x"BFC" => DATA <= x"A9"; when x"BFD" => DATA <= x"20"; when x"BFE" => DATA <= x"85"; when x"BFF" => DATA <= x"FA"; when x"C00" => DATA <= x"60"; when x"C01" => DATA <= x"20"; when x"C02" => DATA <= x"E7"; when x"C03" => DATA <= x"EB"; when x"C04" => DATA <= x"4C"; when x"C05" => DATA <= x"71"; when x"C06" => DATA <= x"EE"; when x"C07" => DATA <= x"20"; when x"C08" => DATA <= x"E7"; when x"C09" => DATA <= x"EB"; when x"C0A" => DATA <= x"4C"; when x"C0B" => DATA <= x"88"; when x"C0C" => DATA <= x"EE"; when x"C0D" => DATA <= x"20"; when x"C0E" => DATA <= x"B4"; when x"C0F" => DATA <= x"EC"; when x"C10" => DATA <= x"20"; when x"C11" => DATA <= x"EF"; when x"C12" => DATA <= x"EB"; when x"C13" => DATA <= x"4C"; when x"C14" => DATA <= x"71"; when x"C15" => DATA <= x"EE"; when x"C16" => DATA <= x"A6"; when x"C17" => DATA <= x"82"; when x"C18" => DATA <= x"A4"; when x"C19" => DATA <= x"83"; when x"C1A" => DATA <= x"4C"; when x"C1B" => DATA <= x"0D"; when x"C1C" => DATA <= x"EC"; when x"C1D" => DATA <= x"20"; when x"C1E" => DATA <= x"B4"; when x"C1F" => DATA <= x"EC"; when x"C20" => DATA <= x"20"; when x"C21" => DATA <= x"EF"; when x"C22" => DATA <= x"EB"; when x"C23" => DATA <= x"4C"; when x"C24" => DATA <= x"88"; when x"C25" => DATA <= x"EE"; when x"C26" => DATA <= x"A6"; when x"C27" => DATA <= x"82"; when x"C28" => DATA <= x"A4"; when x"C29" => DATA <= x"83"; when x"C2A" => DATA <= x"4C"; when x"C2B" => DATA <= x"1D"; when x"C2C" => DATA <= x"EC"; when x"C2D" => DATA <= x"A5"; when x"C2E" => DATA <= x"EE"; when x"C2F" => DATA <= x"29"; when x"C30" => DATA <= x"80"; when x"C31" => DATA <= x"F0"; when x"C32" => DATA <= x"03"; when x"C33" => DATA <= x"4C"; when x"C34" => DATA <= x"78"; when x"C35" => DATA <= x"EC"; when x"C36" => DATA <= x"A5"; when x"C37" => DATA <= x"EE"; when x"C38" => DATA <= x"20"; when x"C39" => DATA <= x"AA"; when x"C3A" => DATA <= x"ED"; when x"C3B" => DATA <= x"10"; when x"C3C" => DATA <= x"0C"; when x"C3D" => DATA <= x"20"; when x"C3E" => DATA <= x"D1"; when x"C3F" => DATA <= x"F7"; when x"C40" => DATA <= x"4E"; when x"C41" => DATA <= x"4F"; when x"C42" => DATA <= x"20"; when x"C43" => DATA <= x"44"; when x"C44" => DATA <= x"49"; when x"C45" => DATA <= x"53"; when x"C46" => DATA <= x"4B"; when x"C47" => DATA <= x"EA"; when x"C48" => DATA <= x"00"; when x"C49" => DATA <= x"20"; when x"C4A" => DATA <= x"16"; when x"C4B" => DATA <= x"EC"; when x"C4C" => DATA <= x"A0"; when x"C4D" => DATA <= x"0F"; when x"C4E" => DATA <= x"B1"; when x"C4F" => DATA <= x"87"; when x"C50" => DATA <= x"85"; when x"C51" => DATA <= x"F8"; when x"C52" => DATA <= x"C9"; when x"C53" => DATA <= x"F0"; when x"C54" => DATA <= x"D0"; when x"C55" => DATA <= x"10"; when x"C56" => DATA <= x"20"; when x"C57" => DATA <= x"D1"; when x"C58" => DATA <= x"F7"; when x"C59" => DATA <= x"55"; when x"C5A" => DATA <= x"4E"; when x"C5B" => DATA <= x"46"; when x"C5C" => DATA <= x"4F"; when x"C5D" => DATA <= x"52"; when x"C5E" => DATA <= x"4D"; when x"C5F" => DATA <= x"41"; when x"C60" => DATA <= x"54"; when x"C61" => DATA <= x"54"; when x"C62" => DATA <= x"45"; when x"C63" => DATA <= x"44"; when x"C64" => DATA <= x"EA"; when x"C65" => DATA <= x"00"; when x"C66" => DATA <= x"20"; when x"C67" => DATA <= x"6C"; when x"C68" => DATA <= x"E6"; when x"C69" => DATA <= x"20"; when x"C6A" => DATA <= x"E3"; when x"C6B" => DATA <= x"EC"; when x"C6C" => DATA <= x"20"; when x"C6D" => DATA <= x"F8"; when x"C6E" => DATA <= x"EB"; when x"C6F" => DATA <= x"20"; when x"C70" => DATA <= x"71"; when x"C71" => DATA <= x"EE"; when x"C72" => DATA <= x"A5"; when x"C73" => DATA <= x"EE"; when x"C74" => DATA <= x"09"; when x"C75" => DATA <= x"80"; when x"C76" => DATA <= x"85"; when x"C77" => DATA <= x"EE"; when x"C78" => DATA <= x"A5"; when x"C79" => DATA <= x"F8"; when x"C7A" => DATA <= x"60"; when x"C7B" => DATA <= x"20"; when x"C7C" => DATA <= x"E3"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"20"; when x"C7F" => DATA <= x"F8"; when x"C80" => DATA <= x"EB"; when x"C81" => DATA <= x"20"; when x"C82" => DATA <= x"88"; when x"C83" => DATA <= x"EE"; when x"C84" => DATA <= x"A5"; when x"C85" => DATA <= x"EE"; when x"C86" => DATA <= x"09"; when x"C87" => DATA <= x"80"; when x"C88" => DATA <= x"85"; when x"C89" => DATA <= x"EE"; when x"C8A" => DATA <= x"60"; when x"C8B" => DATA <= x"A5"; when x"C8C" => DATA <= x"EE"; when x"C8D" => DATA <= x"20"; when x"C8E" => DATA <= x"AA"; when x"C8F" => DATA <= x"ED"; when x"C90" => DATA <= x"20"; when x"C91" => DATA <= x"E3"; when x"C92" => DATA <= x"EC"; when x"C93" => DATA <= x"A5"; when x"C94" => DATA <= x"A3"; when x"C95" => DATA <= x"4A"; when x"C96" => DATA <= x"66"; when x"C97" => DATA <= x"FD"; when x"C98" => DATA <= x"18"; when x"C99" => DATA <= x"65"; when x"C9A" => DATA <= x"84"; when x"C9B" => DATA <= x"85"; when x"C9C" => DATA <= x"84"; when x"C9D" => DATA <= x"A5"; when x"C9E" => DATA <= x"A2"; when x"C9F" => DATA <= x"29"; when x"CA0" => DATA <= x"0F"; when x"CA1" => DATA <= x"F0"; when x"CA2" => DATA <= x"04"; when x"CA3" => DATA <= x"69"; when x"CA4" => DATA <= x"80"; when x"CA5" => DATA <= x"85"; when x"CA6" => DATA <= x"84"; when x"CA7" => DATA <= x"A5"; when x"CA8" => DATA <= x"85"; when x"CA9" => DATA <= x"69"; when x"CAA" => DATA <= x"00"; when x"CAB" => DATA <= x"85"; when x"CAC" => DATA <= x"85"; when x"CAD" => DATA <= x"A5"; when x"CAE" => DATA <= x"86"; when x"CAF" => DATA <= x"69"; when x"CB0" => DATA <= x"00"; when x"CB1" => DATA <= x"85"; when x"CB2" => DATA <= x"86"; when x"CB3" => DATA <= x"60"; when x"CB4" => DATA <= x"E8"; when x"CB5" => DATA <= x"86"; when x"CB6" => DATA <= x"84"; when x"CB7" => DATA <= x"D0"; when x"CB8" => DATA <= x"01"; when x"CB9" => DATA <= x"C8"; when x"CBA" => DATA <= x"84"; when x"CBB" => DATA <= x"85"; when x"CBC" => DATA <= x"A9"; when x"CBD" => DATA <= x"00"; when x"CBE" => DATA <= x"85"; when x"CBF" => DATA <= x"86"; when x"CC0" => DATA <= x"85"; when x"CC1" => DATA <= x"87"; when x"CC2" => DATA <= x"85"; when x"CC3" => DATA <= x"88"; when x"CC4" => DATA <= x"A2"; when x"CC5" => DATA <= x"04"; when x"CC6" => DATA <= x"46"; when x"CC7" => DATA <= x"85"; when x"CC8" => DATA <= x"66"; when x"CC9" => DATA <= x"84"; when x"CCA" => DATA <= x"66"; when x"CCB" => DATA <= x"87"; when x"CCC" => DATA <= x"CA"; when x"CCD" => DATA <= x"D0"; when x"CCE" => DATA <= x"F7"; when x"CCF" => DATA <= x"46"; when x"CD0" => DATA <= x"85"; when x"CD1" => DATA <= x"66"; when x"CD2" => DATA <= x"84"; when x"CD3" => DATA <= x"26"; when x"CD4" => DATA <= x"88"; when x"CD5" => DATA <= x"18"; when x"CD6" => DATA <= x"A5"; when x"CD7" => DATA <= x"87"; when x"CD8" => DATA <= x"69"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"85"; when x"CDB" => DATA <= x"87"; when x"CDC" => DATA <= x"A5"; when x"CDD" => DATA <= x"88"; when x"CDE" => DATA <= x"69"; when x"CDF" => DATA <= x"23"; when x"CE0" => DATA <= x"85"; when x"CE1" => DATA <= x"88"; when x"CE2" => DATA <= x"60"; when x"CE3" => DATA <= x"A9"; when x"CE4" => DATA <= x"00"; when x"CE5" => DATA <= x"85"; when x"CE6" => DATA <= x"84"; when x"CE7" => DATA <= x"85"; when x"CE8" => DATA <= x"85"; when x"CE9" => DATA <= x"85"; when x"CEA" => DATA <= x"86"; when x"CEB" => DATA <= x"85"; when x"CEC" => DATA <= x"8B"; when x"CED" => DATA <= x"A5"; when x"CEE" => DATA <= x"83"; when x"CEF" => DATA <= x"85"; when x"CF0" => DATA <= x"8A"; when x"CF1" => DATA <= x"A5"; when x"CF2" => DATA <= x"82"; when x"CF3" => DATA <= x"85"; when x"CF4" => DATA <= x"89"; when x"CF5" => DATA <= x"20"; when x"CF6" => DATA <= x"1A"; when x"CF7" => DATA <= x"ED"; when x"CF8" => DATA <= x"20"; when x"CF9" => DATA <= x"2A"; when x"CFA" => DATA <= x"ED"; when x"CFB" => DATA <= x"20"; when x"CFC" => DATA <= x"1A"; when x"CFD" => DATA <= x"ED"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"2A"; when x"D00" => DATA <= x"ED"; when x"D01" => DATA <= x"20"; when x"D02" => DATA <= x"23"; when x"D03" => DATA <= x"ED"; when x"D04" => DATA <= x"20"; when x"D05" => DATA <= x"2A"; when x"D06" => DATA <= x"ED"; when x"D07" => DATA <= x"18"; when x"D08" => DATA <= x"A9"; when x"D09" => DATA <= x"20"; when x"D0A" => DATA <= x"65"; when x"D0B" => DATA <= x"84"; when x"D0C" => DATA <= x"85"; when x"D0D" => DATA <= x"84"; when x"D0E" => DATA <= x"A9"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"65"; when x"D11" => DATA <= x"85"; when x"D12" => DATA <= x"85"; when x"D13" => DATA <= x"85"; when x"D14" => DATA <= x"A9"; when x"D15" => DATA <= x"00"; when x"D16" => DATA <= x"65"; when x"D17" => DATA <= x"86"; when x"D18" => DATA <= x"85"; when x"D19" => DATA <= x"86"; when x"D1A" => DATA <= x"A2"; when x"D1B" => DATA <= x"03"; when x"D1C" => DATA <= x"20"; when x"D1D" => DATA <= x"23"; when x"D1E" => DATA <= x"ED"; when x"D1F" => DATA <= x"CA"; when x"D20" => DATA <= x"D0"; when x"D21" => DATA <= x"FA"; when x"D22" => DATA <= x"60"; when x"D23" => DATA <= x"06"; when x"D24" => DATA <= x"89"; when x"D25" => DATA <= x"26"; when x"D26" => DATA <= x"8A"; when x"D27" => DATA <= x"26"; when x"D28" => DATA <= x"8B"; when x"D29" => DATA <= x"60"; when x"D2A" => DATA <= x"18"; when x"D2B" => DATA <= x"A5"; when x"D2C" => DATA <= x"89"; when x"D2D" => DATA <= x"65"; when x"D2E" => DATA <= x"84"; when x"D2F" => DATA <= x"85"; when x"D30" => DATA <= x"84"; when x"D31" => DATA <= x"A5"; when x"D32" => DATA <= x"8A"; when x"D33" => DATA <= x"65"; when x"D34" => DATA <= x"85"; when x"D35" => DATA <= x"85"; when x"D36" => DATA <= x"85"; when x"D37" => DATA <= x"A5"; when x"D38" => DATA <= x"8B"; when x"D39" => DATA <= x"65"; when x"D3A" => DATA <= x"86"; when x"D3B" => DATA <= x"85"; when x"D3C" => DATA <= x"86"; when x"D3D" => DATA <= x"60"; when x"D3E" => DATA <= x"20"; when x"D3F" => DATA <= x"77"; when x"D40" => DATA <= x"ED"; when x"D41" => DATA <= x"85"; when x"D42" => DATA <= x"80"; when x"D43" => DATA <= x"C9"; when x"D44" => DATA <= x"04"; when x"D45" => DATA <= x"B0"; when x"D46" => DATA <= x"03"; when x"D47" => DATA <= x"A5"; when x"D48" => DATA <= x"80"; when x"D49" => DATA <= x"60"; when x"D4A" => DATA <= x"20"; when x"D4B" => DATA <= x"D1"; when x"D4C" => DATA <= x"F7"; when x"D4D" => DATA <= x"44"; when x"D4E" => DATA <= x"52"; when x"D4F" => DATA <= x"49"; when x"D50" => DATA <= x"56"; when x"D51" => DATA <= x"45"; when x"D52" => DATA <= x"3F"; when x"D53" => DATA <= x"EA"; when x"D54" => DATA <= x"00"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"77"; when x"D57" => DATA <= x"ED"; when x"D58" => DATA <= x"85"; when x"D59" => DATA <= x"82"; when x"D5A" => DATA <= x"86"; when x"D5B" => DATA <= x"83"; when x"D5C" => DATA <= x"A5"; when x"D5D" => DATA <= x"83"; when x"D5E" => DATA <= x"C9"; when x"D5F" => DATA <= x"03"; when x"D60" => DATA <= x"90"; when x"D61" => DATA <= x"0A"; when x"D62" => DATA <= x"D0"; when x"D63" => DATA <= x"09"; when x"D64" => DATA <= x"A5"; when x"D65" => DATA <= x"82"; when x"D66" => DATA <= x"C9"; when x"D67" => DATA <= x"FE"; when x"D68" => DATA <= x"90"; when x"D69" => DATA <= x"02"; when x"D6A" => DATA <= x"D0"; when x"D6B" => DATA <= x"01"; when x"D6C" => DATA <= x"60"; when x"D6D" => DATA <= x"20"; when x"D6E" => DATA <= x"D1"; when x"D6F" => DATA <= x"F7"; when x"D70" => DATA <= x"44"; when x"D71" => DATA <= x"49"; when x"D72" => DATA <= x"53"; when x"D73" => DATA <= x"4B"; when x"D74" => DATA <= x"3F"; when x"D75" => DATA <= x"EA"; when x"D76" => DATA <= x"00"; when x"D77" => DATA <= x"20"; when x"D78" => DATA <= x"BC"; when x"D79" => DATA <= x"C8"; when x"D7A" => DATA <= x"20"; when x"D7B" => DATA <= x"31"; when x"D7C" => DATA <= x"C2"; when x"D7D" => DATA <= x"A0"; when x"D7E" => DATA <= x"00"; when x"D7F" => DATA <= x"84"; when x"D80" => DATA <= x"04"; when x"D81" => DATA <= x"A5"; when x"D82" => DATA <= x"16"; when x"D83" => DATA <= x"A6"; when x"D84" => DATA <= x"25"; when x"D85" => DATA <= x"A4"; when x"D86" => DATA <= x"34"; when x"D87" => DATA <= x"60"; when x"D88" => DATA <= x"AD"; when x"D89" => DATA <= x"21"; when x"D8A" => DATA <= x"03"; when x"D8B" => DATA <= x"48"; when x"D8C" => DATA <= x"A9"; when x"D8D" => DATA <= x"05"; when x"D8E" => DATA <= x"8D"; when x"D8F" => DATA <= x"21"; when x"D90" => DATA <= x"03"; when x"D91" => DATA <= x"86"; when x"D92" => DATA <= x"16"; when x"D93" => DATA <= x"84"; when x"D94" => DATA <= x"25"; when x"D95" => DATA <= x"A9"; when x"D96" => DATA <= x"00"; when x"D97" => DATA <= x"85"; when x"D98" => DATA <= x"34"; when x"D99" => DATA <= x"85"; when x"D9A" => DATA <= x"43"; when x"D9B" => DATA <= x"20"; when x"D9C" => DATA <= x"89"; when x"D9D" => DATA <= x"C5"; when x"D9E" => DATA <= x"68"; when x"D9F" => DATA <= x"8D"; when x"DA0" => DATA <= x"21"; when x"DA1" => DATA <= x"03"; when x"DA2" => DATA <= x"60"; when x"DA3" => DATA <= x"A6"; when x"DA4" => DATA <= x"82"; when x"DA5" => DATA <= x"A4"; when x"DA6" => DATA <= x"83"; when x"DA7" => DATA <= x"4C"; when x"DA8" => DATA <= x"88"; when x"DA9" => DATA <= x"ED"; when x"DAA" => DATA <= x"0A"; when x"DAB" => DATA <= x"A8"; when x"DAC" => DATA <= x"B9"; when x"DAD" => DATA <= x"F0"; when x"DAE" => DATA <= x"00"; when x"DAF" => DATA <= x"85"; when x"DB0" => DATA <= x"82"; when x"DB1" => DATA <= x"B9"; when x"DB2" => DATA <= x"F1"; when x"DB3" => DATA <= x"00"; when x"DB4" => DATA <= x"85"; when x"DB5" => DATA <= x"83"; when x"DB6" => DATA <= x"60"; when x"DB7" => DATA <= x"20"; when x"DB8" => DATA <= x"88"; when x"DB9" => DATA <= x"ED"; when x"DBA" => DATA <= x"A9"; when x"DBB" => DATA <= x"20"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"F4"; when x"DBE" => DATA <= x"FF"; when x"DBF" => DATA <= x"A0"; when x"DC0" => DATA <= x"00"; when x"DC1" => DATA <= x"B1"; when x"DC2" => DATA <= x"87"; when x"DC3" => DATA <= x"C9"; when x"DC4" => DATA <= x"20"; when x"DC5" => DATA <= x"10"; when x"DC6" => DATA <= x"02"; when x"DC7" => DATA <= x"A9"; when x"DC8" => DATA <= x"20"; when x"DC9" => DATA <= x"20"; when x"DCA" => DATA <= x"F4"; when x"DCB" => DATA <= x"FF"; when x"DCC" => DATA <= x"C8"; when x"DCD" => DATA <= x"C0"; when x"DCE" => DATA <= x"0D"; when x"DCF" => DATA <= x"D0"; when x"DD0" => DATA <= x"F0"; when x"DD1" => DATA <= x"A9"; when x"DD2" => DATA <= x"20"; when x"DD3" => DATA <= x"20"; when x"DD4" => DATA <= x"F4"; when x"DD5" => DATA <= x"FF"; when x"DD6" => DATA <= x"A0"; when x"DD7" => DATA <= x"0F"; when x"DD8" => DATA <= x"B1"; when x"DD9" => DATA <= x"87"; when x"DDA" => DATA <= x"29"; when x"DDB" => DATA <= x"0F"; when x"DDC" => DATA <= x"D0"; when x"DDD" => DATA <= x"05"; when x"DDE" => DATA <= x"A9"; when x"DDF" => DATA <= x"50"; when x"DE0" => DATA <= x"20"; when x"DE1" => DATA <= x"F4"; when x"DE2" => DATA <= x"FF"; when x"DE3" => DATA <= x"60"; when x"DE4" => DATA <= x"20"; when x"DE5" => DATA <= x"63"; when x"DE6" => DATA <= x"E7"; when x"DE7" => DATA <= x"20"; when x"DE8" => DATA <= x"91"; when x"DE9" => DATA <= x"E6"; when x"DEA" => DATA <= x"20"; when x"DEB" => DATA <= x"BC"; when x"DEC" => DATA <= x"E6"; when x"DED" => DATA <= x"84"; when x"DEE" => DATA <= x"9A"; when x"DEF" => DATA <= x"60"; when x"DF0" => DATA <= x"A4"; when x"DF1" => DATA <= x"03"; when x"DF2" => DATA <= x"4C"; when x"DF3" => DATA <= x"76"; when x"DF4" => DATA <= x"FA"; when x"DF5" => DATA <= x"20"; when x"DF6" => DATA <= x"D1"; when x"DF7" => DATA <= x"F7"; when x"DF8" => DATA <= x"20"; when x"DF9" => DATA <= x"3A"; when x"DFA" => DATA <= x"28"; when x"DFB" => DATA <= x"59"; when x"DFC" => DATA <= x"2F"; when x"DFD" => DATA <= x"4E"; when x"DFE" => DATA <= x"29"; when x"DFF" => DATA <= x"EA"; when x"E00" => DATA <= x"4C"; when x"E01" => DATA <= x"94"; when x"E02" => DATA <= x"FE"; when x"E03" => DATA <= x"A0"; when x"E04" => DATA <= x"06"; when x"E05" => DATA <= x"20"; when x"E06" => DATA <= x"FD"; when x"E07" => DATA <= x"F7"; when x"E08" => DATA <= x"88"; when x"E09" => DATA <= x"D0"; when x"E0A" => DATA <= x"FA"; when x"E0B" => DATA <= x"60"; when x"E0C" => DATA <= x"C8"; when x"E0D" => DATA <= x"C8"; when x"E0E" => DATA <= x"C8"; when x"E0F" => DATA <= x"C8"; when x"E10" => DATA <= x"C8"; when x"E11" => DATA <= x"C8"; when x"E12" => DATA <= x"C8"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"60"; when x"E15" => DATA <= x"88"; when x"E16" => DATA <= x"88"; when x"E17" => DATA <= x"88"; when x"E18" => DATA <= x"88"; when x"E19" => DATA <= x"88"; when x"E1A" => DATA <= x"88"; when x"E1B" => DATA <= x"88"; when x"E1C" => DATA <= x"88"; when x"E1D" => DATA <= x"60"; when x"E1E" => DATA <= x"4A"; when x"E1F" => DATA <= x"4A"; when x"E20" => DATA <= x"4A"; when x"E21" => DATA <= x"4A"; when x"E22" => DATA <= x"4A"; when x"E23" => DATA <= x"60"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"EB"; when x"E26" => DATA <= x"8D"; when x"E27" => DATA <= x"3E"; when x"E28" => DATA <= x"02"; when x"E29" => DATA <= x"A9"; when x"E2A" => DATA <= x"EE"; when x"E2B" => DATA <= x"8D"; when x"E2C" => DATA <= x"3F"; when x"E2D" => DATA <= x"02"; when x"E2E" => DATA <= x"A9"; when x"E2F" => DATA <= x"80"; when x"E30" => DATA <= x"8D"; when x"E31" => DATA <= x"2B"; when x"E32" => DATA <= x"02"; when x"E33" => DATA <= x"20"; when x"E34" => DATA <= x"21"; when x"E35" => DATA <= x"EF"; when x"E36" => DATA <= x"B0"; when x"E37" => DATA <= x"29"; when x"E38" => DATA <= x"A9"; when x"E39" => DATA <= x"F8"; when x"E3A" => DATA <= x"8D"; when x"E3B" => DATA <= x"3E"; when x"E3C" => DATA <= x"02"; when x"E3D" => DATA <= x"A9"; when x"E3E" => DATA <= x"EE"; when x"E3F" => DATA <= x"8D"; when x"E40" => DATA <= x"3F"; when x"E41" => DATA <= x"02"; when x"E42" => DATA <= x"A9"; when x"E43" => DATA <= x"40"; when x"E44" => DATA <= x"8D"; when x"E45" => DATA <= x"2B"; when x"E46" => DATA <= x"02"; when x"E47" => DATA <= x"20"; when x"E48" => DATA <= x"54"; when x"E49" => DATA <= x"EF"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"21"; when x"E4C" => DATA <= x"EF"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"12"; when x"E4F" => DATA <= x"A9"; when x"E50" => DATA <= x"62"; when x"E51" => DATA <= x"8D"; when x"E52" => DATA <= x"3E"; when x"E53" => DATA <= x"02"; when x"E54" => DATA <= x"A9"; when x"E55" => DATA <= x"EE"; when x"E56" => DATA <= x"8D"; when x"E57" => DATA <= x"3F"; when x"E58" => DATA <= x"02"; when x"E59" => DATA <= x"A9"; when x"E5A" => DATA <= x"00"; when x"E5B" => DATA <= x"8D"; when x"E5C" => DATA <= x"2B"; when x"E5D" => DATA <= x"02"; when x"E5E" => DATA <= x"4C"; when x"E5F" => DATA <= x"62"; when x"E60" => DATA <= x"EE"; when x"E61" => DATA <= x"60"; when x"E62" => DATA <= x"20"; when x"E63" => DATA <= x"D1"; when x"E64" => DATA <= x"F7"; when x"E65" => DATA <= x"49"; when x"E66" => DATA <= x"4E"; when x"E67" => DATA <= x"54"; when x"E68" => DATA <= x"45"; when x"E69" => DATA <= x"52"; when x"E6A" => DATA <= x"46"; when x"E6B" => DATA <= x"41"; when x"E6C" => DATA <= x"43"; when x"E6D" => DATA <= x"45"; when x"E6E" => DATA <= x"3F"; when x"E6F" => DATA <= x"EA"; when x"E70" => DATA <= x"00"; when x"E71" => DATA <= x"20"; when x"E72" => DATA <= x"9F"; when x"E73" => DATA <= x"EE"; when x"E74" => DATA <= x"A2"; when x"E75" => DATA <= x"02"; when x"E76" => DATA <= x"A0"; when x"E77" => DATA <= x"00"; when x"E78" => DATA <= x"20"; when x"E79" => DATA <= x"FB"; when x"E7A" => DATA <= x"EF"; when x"E7B" => DATA <= x"91"; when x"E7C" => DATA <= x"F9"; when x"E7D" => DATA <= x"C8"; when x"E7E" => DATA <= x"D0"; when x"E7F" => DATA <= x"F8"; when x"E80" => DATA <= x"E6"; when x"E81" => DATA <= x"FA"; when x"E82" => DATA <= x"CA"; when x"E83" => DATA <= x"D0"; when x"E84" => DATA <= x"F3"; when x"E85" => DATA <= x"4C"; when x"E86" => DATA <= x"AE"; when x"E87" => DATA <= x"EE"; when x"E88" => DATA <= x"20"; when x"E89" => DATA <= x"B7"; when x"E8A" => DATA <= x"EE"; when x"E8B" => DATA <= x"A2"; when x"E8C" => DATA <= x"02"; when x"E8D" => DATA <= x"A0"; when x"E8E" => DATA <= x"00"; when x"E8F" => DATA <= x"B1"; when x"E90" => DATA <= x"F9"; when x"E91" => DATA <= x"20"; when x"E92" => DATA <= x"FD"; when x"E93" => DATA <= x"EF"; when x"E94" => DATA <= x"C8"; when x"E95" => DATA <= x"D0"; when x"E96" => DATA <= x"F8"; when x"E97" => DATA <= x"E6"; when x"E98" => DATA <= x"FA"; when x"E99" => DATA <= x"CA"; when x"E9A" => DATA <= x"D0"; when x"E9B" => DATA <= x"F3"; when x"E9C" => DATA <= x"4C"; when x"E9D" => DATA <= x"D7"; when x"E9E" => DATA <= x"EE"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"E5"; when x"EA1" => DATA <= x"EF"; when x"EA2" => DATA <= x"A9"; when x"EA3" => DATA <= x"51"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"6E"; when x"EA6" => DATA <= x"EF"; when x"EA7" => DATA <= x"D0"; when x"EA8" => DATA <= x"20"; when x"EA9" => DATA <= x"A9"; when x"EAA" => DATA <= x"FE"; when x"EAB" => DATA <= x"4C"; when x"EAC" => DATA <= x"BF"; when x"EAD" => DATA <= x"EF"; when x"EAE" => DATA <= x"20"; when x"EAF" => DATA <= x"FB"; when x"EB0" => DATA <= x"EF"; when x"EB1" => DATA <= x"20"; when x"EB2" => DATA <= x"FB"; when x"EB3" => DATA <= x"EF"; when x"EB4" => DATA <= x"4C"; when x"EB5" => DATA <= x"AF"; when x"EB6" => DATA <= x"EF"; when x"EB7" => DATA <= x"20"; when x"EB8" => DATA <= x"E5"; when x"EB9" => DATA <= x"EF"; when x"EBA" => DATA <= x"A9"; when x"EBB" => DATA <= x"58"; when x"EBC" => DATA <= x"20"; when x"EBD" => DATA <= x"6E"; when x"EBE" => DATA <= x"EF"; when x"EBF" => DATA <= x"F0"; when x"EC0" => DATA <= x"03"; when x"EC1" => DATA <= x"4C"; when x"EC2" => DATA <= x"C9"; when x"EC3" => DATA <= x"EE"; when x"EC4" => DATA <= x"A9"; when x"EC5" => DATA <= x"FE"; when x"EC6" => DATA <= x"4C"; when x"EC7" => DATA <= x"FD"; when x"EC8" => DATA <= x"EF"; when x"EC9" => DATA <= x"20"; when x"ECA" => DATA <= x"D1"; when x"ECB" => DATA <= x"F7"; when x"ECC" => DATA <= x"4E"; when x"ECD" => DATA <= x"4F"; when x"ECE" => DATA <= x"54"; when x"ECF" => DATA <= x"20"; when x"ED0" => DATA <= x"52"; when x"ED1" => DATA <= x"45"; when x"ED2" => DATA <= x"41"; when x"ED3" => DATA <= x"44"; when x"ED4" => DATA <= x"59"; when x"ED5" => DATA <= x"EA"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"20"; when x"ED8" => DATA <= x"FB"; when x"ED9" => DATA <= x"EF"; when x"EDA" => DATA <= x"20"; when x"EDB" => DATA <= x"FB"; when x"EDC" => DATA <= x"EF"; when x"EDD" => DATA <= x"20"; when x"EDE" => DATA <= x"FB"; when x"EDF" => DATA <= x"EF"; when x"EE0" => DATA <= x"A9"; when x"EE1" => DATA <= x"FF"; when x"EE2" => DATA <= x"20"; when x"EE3" => DATA <= x"BF"; when x"EE4" => DATA <= x"EF"; when x"EE5" => DATA <= x"20"; when x"EE6" => DATA <= x"FB"; when x"EE7" => DATA <= x"EF"; when x"EE8" => DATA <= x"4C"; when x"EE9" => DATA <= x"AF"; when x"EEA" => DATA <= x"EF"; when x"EEB" => DATA <= x"8D"; when x"EEC" => DATA <= x"00"; when x"EED" => DATA <= x"B4"; when x"EEE" => DATA <= x"EA"; when x"EEF" => DATA <= x"EA"; when x"EF0" => DATA <= x"EA"; when x"EF1" => DATA <= x"EA"; when x"EF2" => DATA <= x"EA"; when x"EF3" => DATA <= x"EA"; when x"EF4" => DATA <= x"AD"; when x"EF5" => DATA <= x"00"; when x"EF6" => DATA <= x"B4"; when x"EF7" => DATA <= x"60"; when x"EF8" => DATA <= x"8E"; when x"EF9" => DATA <= x"D4"; when x"EFA" => DATA <= x"03"; when x"EFB" => DATA <= x"8C"; when x"EFC" => DATA <= x"D5"; when x"EFD" => DATA <= x"03"; when x"EFE" => DATA <= x"A0"; when x"EFF" => DATA <= x"08"; when x"F00" => DATA <= x"48"; when x"F01" => DATA <= x"29"; when x"F02" => DATA <= x"80"; when x"F03" => DATA <= x"8D"; when x"F04" => DATA <= x"00"; when x"F05" => DATA <= x"B8"; when x"F06" => DATA <= x"09"; when x"F07" => DATA <= x"40"; when x"F08" => DATA <= x"8D"; when x"F09" => DATA <= x"00"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"AE"; when x"F0C" => DATA <= x"00"; when x"F0D" => DATA <= x"B8"; when x"F0E" => DATA <= x"49"; when x"F0F" => DATA <= x"40"; when x"F10" => DATA <= x"8D"; when x"F11" => DATA <= x"00"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"8A"; when x"F14" => DATA <= x"6A"; when x"F15" => DATA <= x"68"; when x"F16" => DATA <= x"2A"; when x"F17" => DATA <= x"88"; when x"F18" => DATA <= x"D0"; when x"F19" => DATA <= x"E6"; when x"F1A" => DATA <= x"AC"; when x"F1B" => DATA <= x"D5"; when x"F1C" => DATA <= x"03"; when x"F1D" => DATA <= x"AE"; when x"F1E" => DATA <= x"D4"; when x"F1F" => DATA <= x"03"; when x"F20" => DATA <= x"60"; when x"F21" => DATA <= x"A2"; when x"F22" => DATA <= x"01"; when x"F23" => DATA <= x"86"; when x"F24" => DATA <= x"04"; when x"F25" => DATA <= x"A9"; when x"F26" => DATA <= x"00"; when x"F27" => DATA <= x"95"; when x"F28" => DATA <= x"16"; when x"F29" => DATA <= x"95"; when x"F2A" => DATA <= x"25"; when x"F2B" => DATA <= x"95"; when x"F2C" => DATA <= x"34"; when x"F2D" => DATA <= x"95"; when x"F2E" => DATA <= x"43"; when x"F2F" => DATA <= x"A9"; when x"F30" => DATA <= x"40"; when x"F31" => DATA <= x"20"; when x"F32" => DATA <= x"6E"; when x"F33" => DATA <= x"EF"; when x"F34" => DATA <= x"C9"; when x"F35" => DATA <= x"01"; when x"F36" => DATA <= x"D0"; when x"F37" => DATA <= x"18"; when x"F38" => DATA <= x"A9"; when x"F39" => DATA <= x"69"; when x"F3A" => DATA <= x"20"; when x"F3B" => DATA <= x"6E"; when x"F3C" => DATA <= x"EF"; when x"F3D" => DATA <= x"F0"; when x"F3E" => DATA <= x"13"; when x"F3F" => DATA <= x"A9"; when x"F40" => DATA <= x"00"; when x"F41" => DATA <= x"8D"; when x"F42" => DATA <= x"D1"; when x"F43" => DATA <= x"03"; when x"F44" => DATA <= x"A9"; when x"F45" => DATA <= x"41"; when x"F46" => DATA <= x"20"; when x"F47" => DATA <= x"6E"; when x"F48" => DATA <= x"EF"; when x"F49" => DATA <= x"F0"; when x"F4A" => DATA <= x"07"; when x"F4B" => DATA <= x"CE"; when x"F4C" => DATA <= x"D1"; when x"F4D" => DATA <= x"03"; when x"F4E" => DATA <= x"D0"; when x"F4F" => DATA <= x"F4"; when x"F50" => DATA <= x"18"; when x"F51" => DATA <= x"60"; when x"F52" => DATA <= x"38"; when x"F53" => DATA <= x"60"; when x"F54" => DATA <= x"A9"; when x"F55" => DATA <= x"E0"; when x"F56" => DATA <= x"8D"; when x"F57" => DATA <= x"00"; when x"F58" => DATA <= x"B8"; when x"F59" => DATA <= x"A9"; when x"F5A" => DATA <= x"FE"; when x"F5B" => DATA <= x"8D"; when x"F5C" => DATA <= x"02"; when x"F5D" => DATA <= x"B8"; when x"F5E" => DATA <= x"A9"; when x"F5F" => DATA <= x"E0"; when x"F60" => DATA <= x"A2"; when x"F61" => DATA <= x"A0"; when x"F62" => DATA <= x"A0"; when x"F63" => DATA <= x"58"; when x"F64" => DATA <= x"8D"; when x"F65" => DATA <= x"00"; when x"F66" => DATA <= x"B8"; when x"F67" => DATA <= x"8E"; when x"F68" => DATA <= x"00"; when x"F69" => DATA <= x"B8"; when x"F6A" => DATA <= x"88"; when x"F6B" => DATA <= x"D0"; when x"F6C" => DATA <= x"F7"; when x"F6D" => DATA <= x"60"; when x"F6E" => DATA <= x"48"; when x"F6F" => DATA <= x"AD"; when x"F70" => DATA <= x"2B"; when x"F71" => DATA <= x"02"; when x"F72" => DATA <= x"F0"; when x"F73" => DATA <= x"34"; when x"F74" => DATA <= x"20"; when x"F75" => DATA <= x"AB"; when x"F76" => DATA <= x"EF"; when x"F77" => DATA <= x"20"; when x"F78" => DATA <= x"FB"; when x"F79" => DATA <= x"EF"; when x"F7A" => DATA <= x"68"; when x"F7B" => DATA <= x"20"; when x"F7C" => DATA <= x"FD"; when x"F7D" => DATA <= x"EF"; when x"F7E" => DATA <= x"A6"; when x"F7F" => DATA <= x"04"; when x"F80" => DATA <= x"B5"; when x"F81" => DATA <= x"43"; when x"F82" => DATA <= x"20"; when x"F83" => DATA <= x"FD"; when x"F84" => DATA <= x"EF"; when x"F85" => DATA <= x"B5"; when x"F86" => DATA <= x"34"; when x"F87" => DATA <= x"20"; when x"F88" => DATA <= x"FD"; when x"F89" => DATA <= x"EF"; when x"F8A" => DATA <= x"B5"; when x"F8B" => DATA <= x"25"; when x"F8C" => DATA <= x"20"; when x"F8D" => DATA <= x"FD"; when x"F8E" => DATA <= x"EF"; when x"F8F" => DATA <= x"B5"; when x"F90" => DATA <= x"16"; when x"F91" => DATA <= x"20"; when x"F92" => DATA <= x"FD"; when x"F93" => DATA <= x"EF"; when x"F94" => DATA <= x"A9"; when x"F95" => DATA <= x"95"; when x"F96" => DATA <= x"20"; when x"F97" => DATA <= x"FD"; when x"F98" => DATA <= x"EF"; when x"F99" => DATA <= x"A0"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"88"; when x"F9C" => DATA <= x"F0"; when x"F9D" => DATA <= x"07"; when x"F9E" => DATA <= x"20"; when x"F9F" => DATA <= x"FB"; when x"FA0" => DATA <= x"EF"; when x"FA1" => DATA <= x"29"; when x"FA2" => DATA <= x"FF"; when x"FA3" => DATA <= x"30"; when x"FA4" => DATA <= x"F6"; when x"FA5" => DATA <= x"C9"; when x"FA6" => DATA <= x"00"; when x"FA7" => DATA <= x"60"; when x"FA8" => DATA <= x"4C"; when x"FA9" => DATA <= x"62"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"A9"; when x"FAC" => DATA <= x"80"; when x"FAD" => DATA <= x"D0"; when x"FAE" => DATA <= x"02"; when x"FAF" => DATA <= x"A9"; when x"FB0" => DATA <= x"A0"; when x"FB1" => DATA <= x"2C"; when x"FB2" => DATA <= x"2B"; when x"FB3" => DATA <= x"02"; when x"FB4" => DATA <= x"30"; when x"FB5" => DATA <= x"08"; when x"FB6" => DATA <= x"8D"; when x"FB7" => DATA <= x"00"; when x"FB8" => DATA <= x"B8"; when x"FB9" => DATA <= x"A2"; when x"FBA" => DATA <= x"00"; when x"FBB" => DATA <= x"CA"; when x"FBC" => DATA <= x"D0"; when x"FBD" => DATA <= x"FD"; when x"FBE" => DATA <= x"60"; when x"FBF" => DATA <= x"A0"; when x"FC0" => DATA <= x"00"; when x"FC1" => DATA <= x"8D"; when x"FC2" => DATA <= x"D1"; when x"FC3" => DATA <= x"03"; when x"FC4" => DATA <= x"88"; when x"FC5" => DATA <= x"F0"; when x"FC6" => DATA <= x"09"; when x"FC7" => DATA <= x"20"; when x"FC8" => DATA <= x"FB"; when x"FC9" => DATA <= x"EF"; when x"FCA" => DATA <= x"CD"; when x"FCB" => DATA <= x"D1"; when x"FCC" => DATA <= x"03"; when x"FCD" => DATA <= x"D0"; when x"FCE" => DATA <= x"F5"; when x"FCF" => DATA <= x"60"; when x"FD0" => DATA <= x"20"; when x"FD1" => DATA <= x"D1"; when x"FD2" => DATA <= x"F7"; when x"FD3" => DATA <= x"20"; when x"FD4" => DATA <= x"20"; when x"FD5" => DATA <= x"52"; when x"FD6" => DATA <= x"45"; when x"FD7" => DATA <= x"53"; when x"FD8" => DATA <= x"50"; when x"FD9" => DATA <= x"4F"; when x"FDA" => DATA <= x"4E"; when x"FDB" => DATA <= x"53"; when x"FDC" => DATA <= x"45"; when x"FDD" => DATA <= x"20"; when x"FDE" => DATA <= x"45"; when x"FDF" => DATA <= x"52"; when x"FE0" => DATA <= x"52"; when x"FE1" => DATA <= x"4F"; when x"FE2" => DATA <= x"52"; when x"FE3" => DATA <= x"EA"; when x"FE4" => DATA <= x"00"; when x"FE5" => DATA <= x"A6"; when x"FE6" => DATA <= x"04"; when x"FE7" => DATA <= x"A5"; when x"FE8" => DATA <= x"84"; when x"FE9" => DATA <= x"0A"; when x"FEA" => DATA <= x"95"; when x"FEB" => DATA <= x"25"; when x"FEC" => DATA <= x"A5"; when x"FED" => DATA <= x"85"; when x"FEE" => DATA <= x"2A"; when x"FEF" => DATA <= x"95"; when x"FF0" => DATA <= x"34"; when x"FF1" => DATA <= x"A5"; when x"FF2" => DATA <= x"86"; when x"FF3" => DATA <= x"2A"; when x"FF4" => DATA <= x"95"; when x"FF5" => DATA <= x"43"; when x"FF6" => DATA <= x"A9"; when x"FF7" => DATA <= x"00"; when x"FF8" => DATA <= x"95"; when x"FF9" => DATA <= x"16"; when x"FFA" => DATA <= x"60"; when x"FFB" => DATA <= x"A9"; when x"FFC" => DATA <= x"FF"; when x"FFD" => DATA <= x"6C"; when x"FFE" => DATA <= x"3E"; when x"FFF" => DATA <= x"02"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
a014c5c363c4995178a40beff7e541d1
0.406427
2.58022
false
false
false
false
grwlf/vsim
vhdl_ct/ct00288.vhd
1
8,674
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00288 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.1 (1) -- 7.2.1 (9) -- 7.2.1 (10) -- 7.2.1 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00288(ARCH00288) -- ENT00288_Test_Bench(ARCH00288_Test_Bench) -- -- REVISION HISTORY: -- -- 21-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00288 is generic ( bit1, bit2 : bit ; bool1, bool2 : boolean ) ; port ( locally_static_correct_1, locally_static_correct_2 : out boolean := false ; dynamic_correct_1, dynamic_correct_2 : out boolean := false ) ; end ENT00288 ; architecture ARCH00288 of ENT00288 is signal sbit1, sbit2 : bit := '0' ; signal sboolean1, sboolean2 : boolean := false ; constant answer : boolean := true ; begin sbit2 <= '1' ; sboolean2 <= true ; -- bit g1: if (((bit1 and bit1) = '0') and ((bit1 and bit2) = '0') and ((bit2 and bit1) = '0') and ((bit2 and bit2) = '1') and ((bit1 or bit1) = '0') and ((bit1 or bit2) = '1') and ((bit2 or bit1) = '1') and ((bit2 or bit2) = '1') and ((bit1 nand bit1) = '1') and ((bit1 nand bit2) = '1') and ((bit2 nand bit1) = '1') and ((bit2 nand bit2) = '0') and ((bit1 nor bit1) = '1') and ((bit1 nor bit2) = '0') and ((bit2 nor bit1) = '0') and ((bit2 nor bit2) = '0') and ((bit1 xor bit1) = '0') and ((bit1 xor bit2) = '1') and ((bit2 xor bit1) = '1') and ((bit2 xor bit2) = '0') and ((not bit1) = '1') and ((not bit2) = '0') ) generate process ( sbit2 ) variable bool : boolean ; begin if sbit2 = '1' then bool := true ; case bool is when ( answer = ( ((c_bit_1 and c_bit_1) = '0') and ((c_bit_1 and c_bit_2) = '0') and ((c_bit_2 and c_bit_1) = '0') and ((c_bit_2 and c_bit_2) = '1') and ((c_bit_1 or c_bit_1) = '0') and ((c_bit_1 or c_bit_2) = '1') and ((c_bit_2 or c_bit_1) = '1') and ((c_bit_2 or c_bit_2) = '1') and ((c_bit_1 nand c_bit_1) = '1') and ((c_bit_1 nand c_bit_2) = '1') and ((c_bit_2 nand c_bit_1) = '1') and ((c_bit_2 nand c_bit_2) = '0') and ((c_bit_1 nor c_bit_1) = '1') and ((c_bit_1 nor c_bit_2) = '0') and ((c_bit_2 nor c_bit_1) = '0') and ((c_bit_2 nor c_bit_2) = '0') and ((c_bit_1 xor c_bit_1) = '0') and ((c_bit_1 xor c_bit_2) = '1') and ((c_bit_2 xor c_bit_1) = '1') and ((c_bit_2 xor c_bit_2) = '0') and ((not c_bit_1) = '1') and ((not c_bit_2) = '0') ) ) => locally_static_correct_1 <= true ; when others => locally_static_correct_1 <= false ; end case ; dynamic_correct_1 <= ((sbit1 and sbit1) = '0') and ((sbit1 and sbit2) = '0') and ((sbit2 and sbit1) = '0') and ((sbit2 and sbit2) = '1') and ((sbit1 or sbit1) = '0') and ((sbit1 or sbit2) = '1') and ((sbit2 or sbit1) = '1') and ((sbit2 or sbit2) = '1') and ((sbit1 nand sbit1) = '1') and ((sbit1 nand sbit2) = '1') and ((sbit2 nand sbit1) = '1') and ((sbit2 nand sbit2) = '0') and ((sbit1 nor sbit1) = '1') and ((sbit1 nor sbit2) = '0') and ((sbit2 nor sbit1) = '0') and ((sbit2 nor sbit2) = '0') and ((sbit1 xor sbit1) = '0') and ((sbit1 xor sbit2) = '1') and ((sbit2 xor sbit1) = '1') and ((sbit2 xor sbit2) = '0') and ((not sbit1) = '1') and ((not sbit2) = '0') ; end if ; end process ; end generate ; -- boolean g2: if (((bool1 and bool1) = false) and ((bool1 and bool2) = false) and ((bool2 and bool1) = false) and ((bool2 and bool2) = true) and ((bool1 or bool1) = false) and ((bool1 or bool2) = true) and ((bool2 or bool1) = true) and ((bool2 or bool2) = true) and ((bool1 nand bool1) = true) and ((bool1 nand bool2) = true) and ((bool2 nand bool1) = true) and ((bool2 nand bool2) = false) and ((bool1 nor bool1) = true) and ((bool1 nor bool2) = false) and ((bool2 nor bool1) = false) and ((bool2 nor bool2) = false) and ((bool1 xor bool1) = false) and ((bool1 xor bool2) = true) and ((bool2 xor bool1) = true) and ((bool2 xor bool2) = false) and ((not bool1) = true) and ((not bool2) = false) ) generate process ( sboolean2 ) variable bool : boolean ; begin if sboolean2 then bool := true ; case bool is when ( answer = ( ((c_boolean_1 and c_boolean_1) = false) and ((c_boolean_1 and c_boolean_2) = false) and ((c_boolean_2 and c_boolean_1) = false) and ((c_boolean_2 and c_boolean_2) = true) and ((c_boolean_1 or c_boolean_1) = false) and ((c_boolean_1 or c_boolean_2) = true) and ((c_boolean_2 or c_boolean_1) = true) and ((c_boolean_2 or c_boolean_2) = true) and ((c_boolean_1 nand c_boolean_1) = true) and ((c_boolean_1 nand c_boolean_2) = true) and ((c_boolean_2 nand c_boolean_1) = true) and ((c_boolean_2 nand c_boolean_2) = false) and ((c_boolean_1 nor c_boolean_1) = true) and ((c_boolean_1 nor c_boolean_2) = false) and ((c_boolean_2 nor c_boolean_1) = false) and ((c_boolean_2 nor c_boolean_2) = false) and ((c_boolean_1 xor c_boolean_1) = false) and ((c_boolean_1 xor c_boolean_2) = true) and ((c_boolean_2 xor c_boolean_1) = true) and ((c_boolean_2 xor c_boolean_2) = false) and ((not c_boolean_1) = true) and ((not c_boolean_2) = false) ) ) => locally_static_correct_2 <= true ; when others => locally_static_correct_2 <= false ; end case ; dynamic_correct_2 <= ((sboolean1 and sboolean1) = false) and ((sboolean1 and sboolean2) = false) and ((sboolean2 and sboolean1) = false) and ((sboolean2 and sboolean2) = true) and ((sboolean1 or sboolean1) = false) and ((sboolean1 or sboolean2) = true) and ((sboolean2 or sboolean1) = true) and ((sboolean2 or sboolean2) = true) and ((sboolean1 nand sboolean1) = true) and ((sboolean1 nand sboolean2) = true) and ((sboolean2 nand sboolean1) = true) and ((sboolean2 nand sboolean2) = false) and ((sboolean1 nor sboolean1) = true) and ((sboolean1 nor sboolean2) = false) and ((sboolean2 nor sboolean1) = false) and ((sboolean2 nor sboolean2) = false) and ((sboolean1 xor sboolean1) = false) and ((sboolean1 xor sboolean2) = true) and ((sboolean2 xor sboolean1) = true) and ((sboolean2 xor sboolean2) = false) and ((not sboolean1) = true) and ((not sboolean2) = false) ; end if ; end process ; end generate ; end ARCH00288 ; use WORK.STANDARD_TYPES.all ; entity ENT00288_Test_Bench is end ENT00288_Test_Bench ; architecture ARCH00288_Test_Bench of ENT00288_Test_Bench is begin L1: block signal locally_static_correct_1, dynamic_correct_1 : boolean := false ; signal locally_static_correct_2, dynamic_correct_2 : boolean := false ; component UUT end component ; for CIS1 : UUT use entity WORK.ENT00288 ( ARCH00288 ) generic map ( c_bit_1, c_bit_2, c_boolean_1, c_boolean_2 ) port map ( locally_static_correct_1, locally_static_correct_2 , dynamic_correct_1 , dynamic_correct_2 ) ; begin CIS1 : UUT ; process ( locally_static_correct_1, locally_static_correct_2, dynamic_correct_1, dynamic_correct_2 ) begin if locally_static_correct_1 and dynamic_correct_1 then test_report ( "ARCH00288" , "Logical operators are correctly predefined" & " for boolean types" , true ) ; end if ; if locally_static_correct_2 and dynamic_correct_2 then test_report ( "ARCH00288" , "Logical operators are correctly predefined" & " for bit types" , true ) ; end if ; end process ; end block L1 ; end ARCH00288_Test_Bench ;
gpl-3.0
1177fb7b2bdd20059c5301a4e7f0d329
0.516717
3.095646
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/vhdl/sample_iterator_get_offset.vhd
1
15,189
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_req_din : OUT STD_LOGIC; indices_req_full_n : IN STD_LOGIC; indices_req_write : OUT STD_LOGIC; indices_rsp_empty_n : IN STD_LOGIC; indices_rsp_read : OUT STD_LOGIC; indices_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_datain : IN STD_LOGIC_VECTOR (55 downto 0); indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0); indices_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000"; constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111"; constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal i_sample_read_reg_127 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_9_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_9_reg_138 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_9_reg_138_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_load_new_reg_143 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_112_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_112_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_112_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_2_cast_fu_118_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_112_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_112_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_112_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 generic map ( ID => 0, NUM_STAGE => 2, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_112_p0, din1 => grp_fu_112_p1, ce => grp_fu_112_ce, dout => grp_fu_112_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 <= i_sample_read_reg_127; ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_127_pp0_it1; ap_reg_ppstg_tmp_9_reg_138_pp0_it3 <= tmp_9_reg_138; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_127 <= i_sample; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_load_new_reg_143 <= indices_datain(55 downto 48); tmp_9_reg_138 <= tmp_9_fu_92_p1; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it4, indices_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= std_logic_vector(unsigned(tmp_2_cast_fu_118_p1) + unsigned(ap_reg_ppstg_tmp_9_reg_138_pp0_it3)); -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_112_ce assign process. -- grp_fu_112_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_112_ce <= ap_const_logic_1; else grp_fu_112_ce <= ap_const_logic_0; end if; end process; grp_fu_112_p0 <= grp_fu_112_p00(16 - 1 downto 0); grp_fu_112_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_127_pp0_it2),24)); grp_fu_112_p1 <= grp_fu_112_p10(8 - 1 downto 0); grp_fu_112_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_143),24)); indices_address <= tmp_fu_81_p1(32 - 1 downto 0); indices_dataout <= ap_const_lv56_0; indices_req_din <= ap_const_logic_0; -- indices_req_write assign process. -- indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_req_write <= ap_const_logic_1; else indices_req_write <= ap_const_logic_0; end if; end process; -- indices_rsp_read assign process. -- indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_rsp_read <= ap_const_logic_1; else indices_rsp_read <= ap_const_logic_0; end if; end process; indices_size <= ap_const_lv32_1; tmp_2_cast_fu_118_p1 <= std_logic_vector(resize(unsigned(grp_fu_112_p2),32)); tmp_9_fu_92_p1 <= indices_datain(32 - 1 downto 0); tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64)); end behav;
lgpl-3.0
b9988ac6a73e0f39d9d2ae408632654b
0.593917
2.772727
false
false
false
false
grwlf/vsim
vhdl/standard1.vhd
1
2,976
-- VHDL 1992 standard types with some exceptions entity main is end entity main; architecture amain of main is type boolean is ( false , true ); type bit is ('0', '1'); type character is ( nul, soh, stx, etx, eot, enq, ack, bel, bs, ht, lf, vt, ff, cr, so, si, dle, dc1, dc2, dc3, dc4, nak, syn, etb, can, em, sub, esc, fsp, gsp, rsp, usp, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', del, c128, c129, c130, c131, c132, c133, c134, c135, c136, c137, c138, c139, c140, c141, c142, c143, c144, c145, c146, c147, c148, c149, c150, c151, c152, c153, c154, c155, c156, c157, c158, c159 -- the character code for 160 is there (NBSP), -- but prints as no char -- 'а', 'б', 'в', 'г', 'д', 'е', 'ж', 'з', -- 'и', 'й', 'к', 'л', 'м', 'н', 'о', 'п', -- '░', '▒', '▓', '│', '┤', '╡', '╢', '╖', -- '╕', '╣', '║', '╗', '╝', '╜', '╛', '┐', -- '└', '┴', '┬', '├', '─', '┼', '╞', '╟', -- '╚', '╔', '╩', '╦', '╠', '═', '╬', '╧', -- '╨', '╤', '╥', '╙', '╘', '╒', '╓', '╫', -- '╪', '┘', '┌', '█', '▄', '▌', '▐', '▀', -- 'р', 'с', 'т', 'у', 'ф', 'х', 'ц', 'ч', -- 'ш', 'щ', 'ъ', 'ы', 'ь', 'э', 'ю', 'я', -- 'Ё', 'ё', 'Є', 'є', 'Ї', 'ї', 'Ў', 'ў', -- '°', '∙', '·', '√', '№', '¤', '■', ' ' ); type severity_level is (note, warning, error, failure); type integer is range -2147483647 to 2147483647; -- type real is range -1.0E308 to 1.0E308; -- type time is range -2147483647 to 2147483647 -- units -- fs; -- ps = 1000 fs; -- ns = 1000 ps; -- us = 1000 ns; -- ms = 1000 us; -- sec = 1000 ms; -- min = 60 sec; -- hr = 60 min; -- end units; -- subtype delay_length is time range 0 fs to time'high; -- impure function now return delay_length; subtype natural is integer range 0 to integer'high; subtype positive is integer range 1 to integer'high; type string is array (positive range <>) of character; type bit_vector is array (natural range <>) of bit; type file_open_kind is ( read_mode, write_mode, append_mode); type file_open_status is ( open_ok, status_error, name_error, mode_error); -- attribute foreign : string; begin pmain : process begin assert false report "end of simulation" severity failure; end process; end;
gpl-3.0
62add8ea8a67fb0b60a14cb596fe491d
0.413366
2.20765
false
false
false
false
EpicFailv2/open-source-repo
Embedded Systems/maxFreqSig.vhd
1
2,368
library ieee; use ieee.std_logic_1164.all; entity IESigGen is Port ( CLOCK_50 : IN STD_LOGIC; SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0); HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); HEX1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); HEX2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); HEX3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); LEDG : OUT STD_LOGIC_VECTOR(9 downto 0); GPIO_0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); end IESigGen; architecture Whatever of IESigGen is constant timer_max : INTEGER := 50000000; signal timer_count : INTEGER := 0; signal timer_owerflow: STD_LOGIC; signal led_state : STD_LOGIC := '0'; signal counter : INTEGER := 0; begin -- WITH counter mod 10 SELECT HEX0 <= -- "11000000" WHEN 0, -- "11111001" WHEN 1, -- "10100100" WHEN 2, -- "10110000" WHEN 3, -- "10011001" WHEN 4, -- "10010010" WHEN 5, -- "10000010" WHEN 6, -- "11111000" WHEN 7, -- "10000000" WHEN 8, -- "10010000" WHEN 9, -- "01111111" WHEN OTHERS; -- -- WITH (counter / 10) mod 10 SELECT HEX1 <= -- "11000000" WHEN 0, -- "11111001" WHEN 1, -- "10100100" WHEN 2, -- "10110000" WHEN 3, -- "10011001" WHEN 4, -- "10010010" WHEN 5, -- "10000010" WHEN 6, -- "11111000" WHEN 7, -- "10000000" WHEN 8, -- "10010000" WHEN 9, -- "01111111" WHEN OTHERS; -- -- WITH (counter / 100) mod 10 SELECT HEX2 <= -- "11000000" WHEN 0, -- "11111001" WHEN 1, -- "10100100" WHEN 2, -- "10110000" WHEN 3, -- "10011001" WHEN 4, -- "10010010" WHEN 5, -- "10000010" WHEN 6, -- "11111000" WHEN 7, -- "10000000" WHEN 8, -- "10010000" WHEN 9, -- "01111111" WHEN OTHERS; -- -- WITH (counter / 1000) mod 10 SELECT HEX3 <= -- "11000000" WHEN 0, -- "11111001" WHEN 1, -- "10100100" WHEN 2, -- "10110000" WHEN 3, -- "10011001" WHEN 4, -- "10010010" WHEN 5, -- "10000010" WHEN 6, -- "11111000" WHEN 7, -- "10000000" WHEN 8, -- "10010000" WHEN 9, -- "01111111" WHEN OTHERS; WITH timer_count MOD 2 SELECT GPIO_0 <= "001" WHEN 0, "000" WHEN OTHERS; process(CLOCK_50) begin if rising_edge(CLOCK_50) then timer_count <= timer_count + 1; if (timer_count = TIMER_MAX) then timer_owerflow <= '1'; led_state <= not led_state; counter <= counter + 1; timer_count <= 0; else timer_owerflow <= '0'; end if; end if; end process; LEDG(0) <= led_state; LEDG(1) <= KEY(1); end Whatever;
mit
75a6388b518ee0e70398d9bca5a08b56
0.609797
2.557235
false
false
false
false
jairov4/accel-oil
solution_kintex7/syn/vhdl/nfa_accept_samples_generic_hw.vhd
1
82,370
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_req_din : OUT STD_LOGIC; sample_buffer_req_full_n : IN STD_LOGIC; sample_buffer_req_write : OUT STD_LOGIC; sample_buffer_rsp_empty_n : IN STD_LOGIC; sample_buffer_rsp_read : OUT STD_LOGIC; sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_size : IN STD_LOGIC_VECTOR (15 downto 0); begin_index : IN STD_LOGIC_VECTOR (15 downto 0); begin_sample : IN STD_LOGIC_VECTOR (15 downto 0); end_index : IN STD_LOGIC_VECTOR (15 downto 0); end_sample : IN STD_LOGIC_VECTOR (15 downto 0); stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0); accept : IN STD_LOGIC_VECTOR (0 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_accept_samples_generic_hw is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg676-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.350000,HLS_SYN_LAT=92262011,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_314 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_reg_319 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_reg_324 : STD_LOGIC_VECTOR (0 downto 0); signal c_load_reg_328 : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0); signal offset_reg_334 : STD_LOGIC_VECTOR (31 downto 0); signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_339 : STD_LOGIC_VECTOR (0 downto 0); signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC; signal grp_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0); signal c_1_reg_343 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0); signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0); signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0); signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0'; signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_250_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_250_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_250_ce : STD_LOGIC; component nfa_accept_sample IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); empty : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component sample_iterator_get_offset IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sample_iterator_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_nfa_accept_sample_fu_176 : component nfa_accept_sample port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_accept_sample_fu_176_ap_start, ap_done => grp_nfa_accept_sample_fu_176_ap_done, ap_idle => grp_nfa_accept_sample_fu_176_ap_idle, ap_ready => grp_nfa_accept_sample_fu_176_ap_ready, nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size, nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size, nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din, nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n, nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write, nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n, nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read, nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address, nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain, nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout, nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size, nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols, sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din, sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n, sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write, sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n, sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read, sample_address => grp_nfa_accept_sample_fu_176_sample_address, sample_datain => grp_nfa_accept_sample_fu_176_sample_datain, sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout, sample_size => grp_nfa_accept_sample_fu_176_sample_size, empty => grp_nfa_accept_sample_fu_176_empty, length_r => grp_nfa_accept_sample_fu_176_length_r, ap_return => grp_nfa_accept_sample_fu_176_ap_return); grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_get_offset_fu_192_ap_start, ap_done => grp_sample_iterator_get_offset_fu_192_ap_done, ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle, ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready, indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address, indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size, indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address, indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size, ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce, i_index => grp_sample_iterator_get_offset_fu_192_i_index, i_sample => grp_sample_iterator_get_offset_fu_192_i_sample, indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address, indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size, sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size, sample_length => grp_sample_iterator_get_offset_fu_192_sample_length, ap_return => grp_sample_iterator_get_offset_fu_192_ap_return); grp_sample_iterator_next_fu_209 : component sample_iterator_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_next_fu_209_ap_start, ap_done => grp_sample_iterator_next_fu_209_ap_done, ap_idle => grp_sample_iterator_next_fu_209_ap_idle, ap_ready => grp_sample_iterator_next_fu_209_ap_ready, indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address, indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout, indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size, ap_ce => grp_sample_iterator_next_fu_209_ap_ce, indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address, indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout, indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size, indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address, indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout, indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size, i_index => grp_sample_iterator_next_fu_209_i_index, i_sample => grp_sample_iterator_next_fu_209_i_sample, ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0, ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 38, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_250_p0, din1 => grp_fu_250_p1, ce => grp_fu_250_ce, dout => grp_fu_250_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. -- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0; else if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. -- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. -- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st26_fsm_25 = ap_NS_fsm) and ((ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm)))) then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- c_fu_92 assign process. -- c_fu_92_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st26_fsm_25 = ap_CS_fsm) and (or_cond_reg_339 = ap_const_lv1_0))) then c_fu_92 <= c_1_reg_343; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then c_fu_92 <= ap_const_lv32_0; end if; end if; end process; -- i_index_reg_144 assign process. -- i_index_reg_144_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_index_reg_144 <= begin_index; end if; end if; end process; -- i_sample_reg_154 assign process. -- i_sample_reg_154_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_sample_reg_154 <= begin_sample; end if; end if; end process; -- p_0_reg_164 assign process. -- p_0_reg_164_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then p_0_reg_164 <= ap_const_lv32_1; elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_324 = ap_const_lv1_0)))) then p_0_reg_164 <= c_fu_92; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st25_fsm_24 = ap_CS_fsm)) then c_1_reg_343 <= grp_fu_250_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then c_load_reg_328 <= c_fu_92; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then offset_reg_334 <= grp_sample_iterator_get_offset_fu_192_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then or_cond_reg_339 <= or_cond_fu_245_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then tmp_i_10_reg_319 <= tmp_i_10_fu_233_p2; tmp_i_reg_314 <= tmp_i_fu_228_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then tmp_i_11_reg_324 <= tmp_i_11_fu_238_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_324 , or_cond_fu_245_p2 , grp_nfa_accept_sample_fu_176_ap_done) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => if (not((tmp_i_11_reg_324 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st34_fsm_33; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => if ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st34_fsm_33; elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and (stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st19_fsm_18; elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and not((or_cond_fu_245_p2 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st26_fsm_25; else ap_NS_fsm <= ap_ST_st18_fsm_17; end if; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st2_fsm_1; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= p_0_reg_164; -- grp_fu_250_ce assign process. -- grp_fu_250_ce_assign_proc : process(ap_CS_fsm, stop_on_first_read_read_fu_102_p2, or_cond_fu_245_p2, grp_nfa_accept_sample_fu_176_ap_done) begin if (((ap_ST_st25_fsm_24 = ap_CS_fsm) or ((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)) and (stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0)) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm))) then grp_fu_250_ce <= ap_const_logic_1; else grp_fu_250_ce <= ap_const_logic_0; end if; end process; grp_fu_250_p0 <= c_load_reg_328; grp_fu_250_p1 <= ap_const_lv32_1; grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg; grp_nfa_accept_sample_fu_176_empty <= offset_reg_334; grp_nfa_accept_sample_fu_176_length_r <= sample_length; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols; grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain; grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n; grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1; grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg; grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144; grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154; grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length; grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length; grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1; grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg; grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144; grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154; grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; -- indices_begin_address assign process. -- indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address; else indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_dataout assign process. -- indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout; else indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_req_din assign process. -- indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din; else indices_begin_req_din <= 'X'; end if; end process; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write; else indices_begin_req_write <= 'X'; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read; else indices_begin_rsp_read <= 'X'; end if; end process; -- indices_begin_size assign process. -- indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size; else indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_address assign process. -- indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address; else indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_dataout assign process. -- indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout; else indices_samples_dataout <= "XXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_req_din assign process. -- indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din; else indices_samples_req_din <= 'X'; end if; end process; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write; else indices_samples_req_write <= 'X'; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read; else indices_samples_rsp_read <= 'X'; end if; end process; -- indices_samples_size assign process. -- indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size; else indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_address assign process. -- indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address; else indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_dataout assign process. -- indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout; else indices_stride_dataout <= "XXXXXXXX"; end if; end process; -- indices_stride_req_din assign process. -- indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din; else indices_stride_req_din <= 'X'; end if; end process; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write; else indices_stride_req_write <= 'X'; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read; else indices_stride_rsp_read <= 'X'; end if; end process; -- indices_stride_size assign process. -- indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_324, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size) begin if (((ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size; elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_324 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size; else indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size; nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address; nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout; nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din; nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write; nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read; nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size; nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size; or_cond_fu_245_p2 <= (grp_nfa_accept_sample_fu_176_ap_return xor accept); sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address; sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout; sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din; sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write; sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read; sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size; stop_on_first_read_read_fu_102_p2 <= stop_on_first; tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0"; tmp_i_11_fu_238_p2 <= (tmp_i_reg_314 and tmp_i_10_reg_319); tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0"; end behav;
lgpl-3.0
5992539eaaf3f4ce538a644c86f3cefb
0.645478
2.689808
false
false
false
false
grwlf/vsim
vhdl_ct/ct00668.vhd
1
7,560
-- NEED RESULT: ARCH00668: Variable default initial values - static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00668 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (1) -- 4.3.1.3 (2) -- 4.3.1.3 (3) -- 4.3.1.3 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00668) -- ENT00668_Test_Bench(ARCH00668_Test_Bench) -- -- REVISION HISTORY: -- -- 31-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; -- architecture ARCH00668 of E00000 is begin process variable correct : boolean := true ; variable va_boolean_1 : boolean ; variable va_boolean_2 : boolean := d_boolean ; variable va_bit_1 : bit ; variable va_bit_2 : bit := d_bit ; variable va_severity_level_1 : severity_level ; variable va_severity_level_2 : severity_level := d_severity_level ; variable va_character_1 : character ; variable va_character_2 : character := d_character ; variable va_t_enum1_1 : t_enum1 ; variable va_t_enum1_2 : t_enum1 := d_t_enum1 ; variable va_st_enum1_1 : st_enum1 ; variable va_st_enum1_2 : st_enum1 := d_st_enum1 ; variable va_integer_1 : integer ; variable va_integer_2 : integer := d_integer ; variable va_t_int1_1 : t_int1 ; variable va_t_int1_2 : t_int1 := d_t_int1 ; variable va_st_int1_1 : st_int1 ; variable va_st_int1_2 : st_int1 := d_st_int1 ; variable va_time_1 : time ; variable va_time_2 : time := d_time ; variable va_t_phys1_1 : t_phys1 ; variable va_t_phys1_2 : t_phys1 := d_t_phys1 ; variable va_st_phys1_1 : st_phys1 ; variable va_st_phys1_2 : st_phys1 := d_st_phys1 ; variable va_real_1 : real ; variable va_real_2 : real := d_real ; variable va_t_real1_1 : t_real1 ; variable va_t_real1_2 : t_real1 := d_t_real1 ; variable va_st_real1_1 : st_real1 ; variable va_st_real1_2 : st_real1 := d_st_real1 ; variable va_st_bit_vector_1 : st_bit_vector ; variable va_st_bit_vector_2 : st_bit_vector := d_st_bit_vector ; variable va_st_string_1 : st_string ; variable va_st_string_2 : st_string := d_st_string ; variable va_t_rec1_1 : t_rec1 ; variable va_t_rec1_2 : t_rec1 := d_t_rec1 ; variable va_st_rec1_1 : st_rec1 ; variable va_st_rec1_2 : st_rec1 := d_st_rec1 ; variable va_t_rec2_1 : t_rec2 ; variable va_t_rec2_2 : t_rec2 := d_t_rec2 ; variable va_st_rec2_1 : st_rec2 ; variable va_st_rec2_2 : st_rec2 := d_st_rec2 ; variable va_t_rec3_1 : t_rec3 ; variable va_t_rec3_2 : t_rec3 := d_t_rec3 ; variable va_st_rec3_1 : st_rec3 ; variable va_st_rec3_2 : st_rec3 := d_st_rec3 ; variable va_st_arr1_1 : st_arr1 ; variable va_st_arr1_2 : st_arr1 := d_st_arr1 ; variable va_st_arr2_1 : st_arr2 ; variable va_st_arr2_2 : st_arr2 := d_st_arr2 ; variable va_st_arr3_1 : st_arr3 ; variable va_st_arr3_2 : st_arr3 := d_st_arr3 ; begin correct := correct and va_boolean_1 = va_boolean_2 and va_boolean_2 = d_boolean ; correct := correct and va_bit_1 = va_bit_2 and va_bit_2 = d_bit ; correct := correct and va_severity_level_1 = va_severity_level_2 and va_severity_level_2 = d_severity_level ; correct := correct and va_character_1 = va_character_2 and va_character_2 = d_character ; correct := correct and va_t_enum1_1 = va_t_enum1_2 and va_t_enum1_2 = d_t_enum1 ; correct := correct and va_st_enum1_1 = va_st_enum1_2 and va_st_enum1_2 = d_st_enum1 ; correct := correct and va_integer_1 = va_integer_2 and va_integer_2 = d_integer ; correct := correct and va_t_int1_1 = va_t_int1_2 and va_t_int1_2 = d_t_int1 ; correct := correct and va_st_int1_1 = va_st_int1_2 and va_st_int1_2 = d_st_int1 ; correct := correct and va_time_1 = va_time_2 and va_time_2 = d_time ; correct := correct and va_t_phys1_1 = va_t_phys1_2 and va_t_phys1_2 = d_t_phys1 ; correct := correct and va_st_phys1_1 = va_st_phys1_2 and va_st_phys1_2 = d_st_phys1 ; correct := correct and va_real_1 = va_real_2 and va_real_2 = d_real ; correct := correct and va_t_real1_1 = va_t_real1_2 and va_t_real1_2 = d_t_real1 ; correct := correct and va_st_real1_1 = va_st_real1_2 and va_st_real1_2 = d_st_real1 ; correct := correct and va_st_bit_vector_1 = va_st_bit_vector_2 and va_st_bit_vector_2 = d_st_bit_vector ; correct := correct and va_st_string_1 = va_st_string_2 and va_st_string_2 = d_st_string ; correct := correct and va_t_rec1_1 = va_t_rec1_2 and va_t_rec1_2 = d_t_rec1 ; correct := correct and va_st_rec1_1 = va_st_rec1_2 and va_st_rec1_2 = d_st_rec1 ; correct := correct and va_t_rec2_1 = va_t_rec2_2 and va_t_rec2_2 = d_t_rec2 ; correct := correct and va_st_rec2_1 = va_st_rec2_2 and va_st_rec2_2 = d_st_rec2 ; correct := correct and va_t_rec3_1 = va_t_rec3_2 and va_t_rec3_2 = d_t_rec3 ; correct := correct and va_st_rec3_1 = va_st_rec3_2 and va_st_rec3_2 = d_st_rec3 ; correct := correct and va_st_arr1_1 = va_st_arr1_2 and va_st_arr1_2 = d_st_arr1 ; correct := correct and va_st_arr2_1 = va_st_arr2_2 and va_st_arr2_2 = d_st_arr2 ; correct := correct and va_st_arr3_1 = va_st_arr3_2 and va_st_arr3_2 = d_st_arr3 ; test_report ( "ARCH00668" , "Variable default initial values - static subtypes" , correct) ; wait ; end process ; end ARCH00668 ; -- entity ENT00668_Test_Bench is end ENT00668_Test_Bench ; -- architecture ARCH00668_Test_Bench of ENT00668_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00668 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00668_Test_Bench ;
gpl-3.0
bf794fe9c61736ab5cde704ae748cafc
0.477249
3.184499
false
false
false
false
progranism/Open-Source-FPGA-Bitcoin-Miner
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/async_fifo.vhd
9
33,173
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block eRdqbYtYD+emJKWvdk5CjII05peDuBgi437PzUiA9Dfanoo97pQ/49On6720vtzB/5nOi+7NAv2R irBUJoVU7A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Xh5FhMQ2FmtdG7dozNBaHOQRNATVfMplGP8gI07mJb8iHxdOGNZfRYqtDXWuze0fBGtjGRlC7GxA s8oEeNc43Vz6HreBV7cTx3dfc2eHfIyR3GrrxbPPrnxLrWkmZKarXAyWnx6G/R1bRbesVmKii8Q9 5//fBqx/GHLoCsVxnP4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block wmO7bvGefMsMoSLtXgE7DX18XW18KKV82eC8a6a8qIYOKNkumB4Y0iKaYjVxIIuoc0SK8X/6UBge wy3Y9nIlQvKE/s0BqfM/XQGe3hDGY0H0z24sy8n07g2L2jBNAIRqQGhQP+uzVfU4oJID6w4wRoVb bB5KLjV/r5X7WKKek8c3gxHrTd+SA9xtU0G+KqDaZxVZksoVBlkyuSdQsnSrYn8pQMhGFcX6+eJY R9KS45DbzW8tDupqyigYKzsvSr4WVzNJIVJF7vDjE/cDD9cv++iVVzZ1NDeszgjBjWHpiG3sTK29 nG6bx1JFnRjywZLti6puEInRpv7ls+G3oFmOkg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block aCcru7jE6BS5dTc+KEO9f8gQlScRDhLF86pCIcASRMjqzz7GHJZhjS6XGG1Dphc2y6jMHvhsUeZP zUffYqci6+8TPwGC82dswoHz+n4bwXaWqSjmsw6oOe574EVFl547wKVjx+jlAeBFEP+pdq8M45J9 LUzZEynfeTkNPrkhP8A= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Fr8GJXUBEYtEBjF8cn/9l+0FoZZT/djLR9QiIiAnL5SsQ2BUDjkBceTKUCLrASa09Uyv0GoGYf9M 2jmCzvRke1/uwOo3dVPjFcfCJmrW+7Qe52XHPS2any2QxI/kArYrRb6G3HkROSSW01xgXI9WsIRM 9EUc8CbUix1N2n/Xf/pPXJS1w8TW+58+6gvzrcBqQnBs/IcNXXiYJQRBTdNrFlk4o3CWZGdlvH8K ZBSSfqf3QFxod+g/mPD7P6DOoHeDIY4PJ+DtQS4rJGkgkWpiL2DA65PSUe5VSjEdMpY2W1AlWhhH xqTHrX5FvwenScavtWwySZtiZPq56XOm4iP4JA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22816) `protect data_block 3I75aSxZJUp0L2UIY92Z4OcofdmM758hnlnQEa0P4LagJ0jdsqD/k2U9Ry3FgRL+72mI0r471n0a GOZ0X0ABisYh4NM9O9jrYX6RP/vM9cKUgKKvsHlD7VmMH7pLb6Q8GtDJTJXVWS5kmBvNRheA5SSo 0SP/mwE0F/SV21KM1vfkQCMPsH/H09kZgdrDV7o76uQdJKoh2NeVomXCR1uoFQ/oflpsOanxZKKe /TM+9T9kpOKujMydXcRV0eCN8pEVdJRl2mpfFDP1SS4SPsu5+WuKwzpmpEzYsB3rKEumt8xeWhmz +iptCg6vKyv2o5VXqyusjjCqrApujWp7aQ1AK+uaEsdEVlXfFsxNkhWNIZS2tL/DBUMueWF8quLH 1HobJLXCOYu/dSkWs6HKJu4sJyD2+TL6eArro2ZwgFKa9NLQHoAWhPi3iRvUzBpH43zUpJW4lJ3E eRFZFkaFC+MffpYOE0Ul17qNJu90bQmGTmWv4RmHpUJ7Vll0CmRkUNDkQdRoVaLqXI/4F1OIqgk1 Uq+4or1g0LzDt8BAGdqayZ3Lruj5+IlOi7n4h8/6Zb+JT9IOfqW55eE06eHcSVhcVe3YmaQoHW7n Z/yD4ngbxnYH5c3AMy8nuOMkBcZKacljtbo4X2IO/ZzDy+G8r391KKZXVRRrjxvKnewKIn515iTo HyMwxOqeij7TJQJLOjSenX/0SFNv5j9uSPdBiCyKBY5G6Om3lBfbgETdSDoa2/Gn4ZiTfNXXEqq7 a+rtMruwM7UC7UycsUgvwF3w4/cGe0UHH9cSrhjt8W9z9xufUtVoppXfRJHVyeEEwR0eopt2SbiV 4X82yoLPMhHNVp2KV720SJjn2bymykCySGiWNEg8G5SVq0VrhpOPFTRm6VRFLuG0s6TAzu3Q9EbI 3WCZtCtdLZv4F5TgW5zi3LVEDmbdtGOj4Alm485P7Wo5FcTuKrnnb5VaR6oBq/61+nsPmlcEeCPn sRHMOdvmIhX+4egu0cj3hqmFXY6t2jDMya2pHhwfqisUqQ8617eOoxj4sugI10U5G3LAs4kwqqrS POF/xBQHAegqQIdC/NdTvhu4HgNwBa0xWrlVhwjXdOl3pt2pMVU8oHH9aQy19oupV/vnDHYlxsG/ PhoHIOh0abgtbP9uH8Jm6GmSWXa5wN81Fk90ga3iJ20DfCLekukWsP0vM0ZmSvAeHP1gNJiI3V08 OXyjfE6whsFR03IuVxA9yf1Y/Omxc8oPJT2HcQJQDl0e3JQ0eqMisrFYfUkMF2OlCIyylRPFbLdn Uah6PHMFmUohpZfZhPPVdbfClGs4lV9KR6XYG+JyD/agnfsXYxFDpoKFr+4JuWwrVtsH1Bj1oygE 4RN4obIjDVl7V8kS68+ajGq6yVzrfYrNdFrg+FOdPOaawSHbfgklWxT8bbh3H6HHDpWDZ7VpkI+/ V7IQ12uFGwJ9LCmquQ2qHC2TDwDRoBgIwdlXHftlhnXqdMPI0ay63Pz1vwyyLyTWA/clhygOgP4L 9vLCH4nCvg4IXR7bguAaY0g8hEhW5D5Znqgkscvnd8eMRFNrfJtrcvc7dp4UCwPdRQNiuxhh5NYw r0E9iUIYhJ2XfTfkuUtcxUFV7mGwitGhGiv+sKq/qdcy1JbhgAi36ZqLuQdkXwRC47uKG/7LKX6W BpwZExzuD1jT2qkTBY+h59BA8aFV2k5TA3t86dA8mkmg7yluQxB93KXUUOA3G1LaK2WIwag/9XEX jJGfiUDMhUlKUbryjJrGNxEcsmwNBKF276VLKWhTaJJNga8zbDfbZy75u2GkF2VLZ9q98v+/fGz1 FOzjpCn+udDJ/RWX37ue+uHK426B+VAibLlwl0pOiRC7l7EUanuzVp7NuLGTtYW1wNn5ys2DqpCL MEkMbm0NnpQr5mEkrV5ZQe6QY2I0qz+u4wFYNaHYIILQii7ab1PL+pCNuR37qcxN+PNhsIquk5DI 2dufrTMly5ZRTRdZDjcYVFFwE4WMeMA7V0kELI2qhaPk+3gcXsFoPprezHQRCZImNGFIvdz6+ytw samAoPtBdbQhcFnx3zDRG/dN4nFO8CuTKwql67cvb7JEGoTKwBiE/E96hu3uODrezmec/Lstfx5G ljXHELwygzO+iqGoy8qOGIDS8WbbcZi2BT2bXEpIQV2TO9cLWjRqV8xvecSEP83E1zPtfSpzDjG+ hFWk+3lTdrGPbexl66d1DW8zL67e/hiWtw7nQJhygHl6cqYzo/yXqrwGlCY0ePDm1NkwP70nUypP jNzHK9D6R+0TgO7sodYm7y1rPKLZ40FCncc5G5sHTFFk/n6t0qWOIHprNnvV9m8Os6xull7mF2Gm 8+7qg9YOPxtIFS5qGuoXWQmhX8YCoLVu1mC8dGcYfFrUJQFoKrC9o7K3y7GNDpBxA3Q1Skhcj1Hr R06jKGIo4dXAXJi+wN39tvgqwIzZP4TWqBmxruga8GWopmOist2rmFa0hnK8ks7v1Fv11RlCyO7X /ASgyYMJOTYPsxtw4PD839B9lUPayy8ltADSwReIF7m98JYC8LnufEBKYjyNYqObo3Voe/dhz+Uh 2Co486ahQ9+M1L70SGeQd0omc+EKpdEbqyo9FUFCSsAh8P0ryWIJ06XwnSt84rYdOe/RUdGDV4p7 79WLopc4JsruJ4HRWjVoqbjdtF0OyQ9L/eBcuC4oER2rluPICjBdCI9iZltC4yKW/dSwn+ixBul2 JwuqGU7fWW4fyNVayAehVgEOvekkccICOn6PXqv7GtaeDuBLOARNMpSuZeGKSElfQ+4PdsGYhool dwkW/hDdiRwjA1FAgLVZIEJ7UCsiOuYHWIoQkNnugKxqWLkcFLMb7gVOa80/His+kORVoXu1/gyW goJ4iwmb+b3gBpYMw9dyRDTRRQsjJ69zF93jGNqfC18Fmqyd3UEHfezYF3pj51RRvtqOBSnZnN/P ID/4OvCw6lU+blIHz2Jc5Z6PPiKO6oXphpjFpNKsOR/PY4pt5kH0NM1ynkkvD8jaoLQoTb0PWLKK VDfNxkRpnY6M7KWL0w2GN2s9+Cm08tGJoHh8z9BH4JqT8Xmoq9JLz0YnWPitT0OcA0NJw3ATYBfT yOKTpI7+HbxzI/eKugsGiws+7bgawNVFHnA0XNUGkOSLhcsyFttzKx0/lKTOHrSVOxal+kzc+8x5 gqzlZ0hmxK3e25mUAzj20OsR1PVOlKws7F4hP4qL6VQnERSjVodyocnR9caaHWqB6oq1YoWQFtxR FuW4lk7AJclslKfTHS4j/DLZZfKIefxaepfssjR8Yx3UbFxjPI1gkdF9bdzCtri7RMXZP7I8icGR LzeEVu+civGZ34M+i827FfmG5HUVK5CC0h0LxH97WoTjhBgU5xFCY/XVG7rY2VdVHxlm6obiwvK9 uNCd2c0qFAArrXf2JqbAeIwEtxEZYSfW83Ug7SuylOCmpZDPjGB9LPfMm6mTfOuZodhdIGiDKdVi KBvmWvW/ChItwED4rBs39C5o2hK2AqwinDXDUqz65TyFe2r2CWu3543TMsVFFcZMYoM5OPaQ/FTW QoR/tk4mPEJi9hxW/GZMGiIsPArEpNU/O87OToqdGg/MelVlU9jGyKNlal1qJKjbY6ETMdKaGZqT uumwKZQKi+emjOi5GEfS8Dlcyajj6/HuidsqLqfW2lXPp+Nx9nVp1X4Knu1mJBkQ5Od1BB+9Au9T IWxichR5Dh/I+wr9CsgyrZnsOQ3td2vjZyGe189GEhc88GwtKdJ0vgfsvftWR054qGgsvwPN1UMW eyJnyp7FYe+oLfF4HzkqMlVn35NafxUVBNZfiUHT/dZcQBSeClw7LbGzk870e2izRwFTs1p/Hxvh 5a1a99ux4o7TKQkXJKIp2UyhkDq4UUVRTQv6Ecmw+h/bRdu6BTZDCL7p520DV5mc9dlm4gr/fqH2 5ce0cxu0q14PBTlblJfrC+XqjzC4NAi8RJ/PPlDnwqRxz1NdD9rWhqccDh1y/mFjuws9F4p7fcsM chWf95GFjUrTUwEaGXYtItZL/HKLRZbAE6OeqSCXUaI2h0TqI/+kxoJC3w0wQAm1VgcKah63XZcP lwz6pjkSwul3ITT+vixdpMwfgxMcusgQiGdknsiZTdLA/NZJaFU/2TW7kTRHb6yFkp73dbf48T66 5BIlbIZ9rAF/b2GSfeS+qm8lFZTMuy6rCzZ4a+rsXWE39tiGapW/SQriPyei5wG7yDbzdVHtN3qB op4faIAGTcHM6iN4evHSCAInBPKjOdG8ualAFNIORyHc0Su0LUBjzLby5ciDFwdGypSMyoR0nl7j V9f+shGcy5mS1QEEeE3afBKCAEw/hRBfbSuXQyL08tbG9UoUuLxC/N3AlHbXT0pcVIKDqs3HrPpX w7IQoKLq36hISXzHSa2HtcNXy4Jd+Z+ROHGdgTzuZN2qYzLpaEdoI4WPzIG6b3soBLOchnniIzs1 1qdMyPyUFxx1sLoZ6NfA5VpsAHkJLTUjQWUKODGHrh0+52EdGlqdnbgai32QAYC6BWtcdCJ55BTZ 35+JgyNnouwTzNHxEZYr+6q2x5wmAiDOvkgaDTgFAcOY1zG6SjmoTaT0M5aTGHTMSp9Y3w3j6h6X auUSTJw/23rBiaq8GC0PR9juBaYdJg1C2FeWCBpzVC90ejw4pAI3RVaj1INGoO6Y4Le6zCnC9POV YawiwJ1aswjbMyvtzcp8Jd2JbGSpeg0O/RFbKWwHzAi1fZWaYxiEjwq8AP3rN6s9NcBIhD05vqBH eaPR9GNPo80mWB1gMpejpLNzoLyVEldCK8TCmPj3yteRfwr9Dy0ihK0gA+2TsH3p42Kl0RtrwHyw sKQvIWwQplhmOTe0ouC65vbE+ISI8ToknBabqFrAVt7BfTRmMzcDSs61a64YvWOOy4p3AUsQ774r 5SKNlIoOvsoa8f5wW/9dQnbxocPiBfP0PvBZnVAh31o3L4QshkQChkJIolVwUXA2LcwCV7PO5V91 Ivv5B+sgFF/JraEodTEtrtvwvcdYd5Eh7GUHkna86rH5QIDBeY+b0KPUAUilI9Eb/R/xDxLbY2ce c17iQacQhRAFpOq+UzY63YEy11fitO4xzhIoqSL6JWWOuVflcvZCfofMLvNLF3vST3lcybORaHM6 oLMB1xcaaGAjZjNFpSbO6uT19KdHVb0kmq9oeXG3nM4DAvl0scHYrcpMexrabgCcXo3sZf/qc4cu J0Zx8ZdiR5KVMM7iW+78S9b8YfIiv81bUXKO7CHEP4iR1yyGYBAXizW/forGU0KLOH1Yjto40CEf rRCnktxCUaQ923BXr8H+AGp2rLGUrwO7AuZBoWeQeqci8xvAnYx8rYVOrQZZrLhY13USbXV2PbPW vgIJNvqRfX8h41a27YMP3WDwldVoTVG5s8svR1EG6B8TODnWLYKhMwYLb0E2ek7v5sa1etdIZYwJ 0dRuwsg7L7krGITDHxYQlfPGC10iK2jwicScTnSmhEdt3DDkGnQa8OWjppp2aOcQaeDzfHo/8H2D ooU0UoB4D7HOXIzvgvramvqonh/sucAQUPtiqPhfBjzs8nydRZogltv3vmmzv+x7fcc+Hp10X27l umo5B0/Ka6jxJ2Se0UPBcYNKxj9MZ7Ii1CLCN+biNZ07PwETJi+y3ZBQfSRLNviSXwYrNba4Dx1O qDz6L7y0dtPsAwRROglitrqyzoZqeJCP3Rr9yIhaWnplgIxSLu1Cgsqi/cNfOsZndhE60WzNGjFi c6ze4SvsxTUnCUEp4z8+9nY9wPUddXECPtFj4nBqQUvDzgs3toTQn3tQ5+HnHZDYDo3FvwoH0nR8 yOnT+wYcz460B2pyHW1VVseW3bMExuYu59uMjgmbt7kt3n84XG9PqfIu4s7lit3wCHtsc8XVCKec CAfhBIAW2+hGpi/Ruj4O1boHji1yNRF486vzHIUdAG85tcbJhb4VaeQp6uGfYVgnr7NJO7tB0xac y9UJeW3juTtltoeWXq+bXmQ2QcUeMWecJRGEbNo8OcUoXXSB5VfqsgfIj7/CiMSRZ3rex/T7W0rJ rG8053wanb/usgWGop/lGSmW+Gm/LWeafxvCtrOaJhG8JWnWiiJgqqQmFTgWY+UnXfwv89RRHwdF n8NxVNVLzwCyWivzfn5/BirQm0nESZZhi4lTC6hNlQmFt4xIWiEQnedXOX9GWq54EB7votWOA8X3 0bgEsHbyczFOvcEIrfQXOu6GT6nIWZG3AYz8oN32um5yqDD0yYOVHUnpZeAVCxGfntWO9qcab4TW dL6pneZe0HGqSlZM+wM2Pf4np5GKTcz4A/V7gpK0jmdVLLXvXHXe3FZIOBOt7IzfUlBPTN0CqSTX C3DK/HlwhoOai+bHQXI/VcBdLl28zGu2oBUSlV8V45pZNUx6sugga83fWlDlr83HEISCt7yahdhB y67sc1VDOVF7bFRP9/GyzUVJjD3ymP0PckVaPx++wg/nAGMWfTq1CCH8JwI4ysUKhVxqyaNHSqsw kJeO530i+JK4fic8rZt6XjsgdbRJHWJCNhU5wnDZZbzAAdVWXYX6pSISmSwMMhlyYdcwKAKot2zI zuKWJXoEEBcQEA3SvTiW67gtz7hiFwPX+7fHcU9LoKp5Vmq05y35qRCSwjM/iRPMen9+i4sUMrhm RLcLzB66Me2Zb1rppouFfOBQrY1QwMI9fvyNHtM7b84Jd6WRCCig877OHw6GS142bD+VoFwis44z 8PGut0/vaRH+Xb65uQzcUTRQE8Us/sh7Q3eAL9G9K09zfa/39gB6/V3qACwqiHAvYd4jF5ouHVMP GMOqcDpixCQ3Lk/JGk8mEI2PmAHF7zDyDBYDoIuzLBOwx2LBS1ALcjlWCEfgBHapdvRW0OCoz0+P X9LAZvKdPe3NQwr5ASuknsj25KgRaCvCdJhKEmXKS5OL9e6RKg2WkyWJvgphwyFAuFffgXzxWza0 0Iq6e6iFXMzYSBEryHhnJWTnGTZ8N2JJkCxGmoVd2+yrKjd1IWZHPxHAKW6Gw5vCpErO9gpK+gqs 4D6yF9d8hldrjQc1Fuvn80FOJPefrfCl38HoEOsXrxZEXuAnth52USi9idvBVhYi3QyThmrJEdM7 kJRXVHe+toW6eqb/eafQwUJS3K5MrE+uGfpP2OlwY3EY7tHoHlxSNqIX5x7K8G4g9YUBeBDJYI/P CNMg5FnZfCDJFYJlqlnso8qhxCUMXXxNxubtdPyibvkiDe7v5z7cqhaoxO8+zCbbOZQ3HyRUUqwy VwTB0/XERIiuI1gjMGcW8BA38qAZn1xJ48XmEjGe1UbT2WzWSazTnf093DdTJppRe3LL+uzTTN3e ToTOMs4jMDnVmVQCRv7IPeQDoMTqlRMIpnKDGsbz+FHpjeyjgj+s8r3lg2v9p0PtLz8KigeK5fsZ sMvlmagYn0EeSnPuQybcvhgUUfSI2z61rGE9iv4WIw1odMdhBfRUntj0LxfBt6rUZLFrE0o+rpSE fX1hco/Z4FkRVQT2dVlYeN9EsUgCitY2BQzVNyZkGpiyLsiAmf+BFnqE9lyor1BrOxRreglpH6I7 uTTtnZVAthGUv4I9CH/gdjomU8JC8YpQWV4d9tx33A8jovesOXv0Hku0my0BIFxfp2NTRSbPs3/H 5ss384wtlB0XsBK7oGAy/6NAjo0KEmNxlmoif7v/UnXj1YnYTiikQtVaD8nqKr5r36sFZBodp7uU L8ENWuGCjb5rf/OSke8oJ/LjaIh/0WhMpPW7q1+WZhtqm3PtSOr2xvyNuSxxkgh5zAaBpdpTTbyE iq199L3gAO7a3loPIGMAlHXn3hyUfrEGAqxwY0GmA5U/BT4v52iBy6JPO1GmJo/v53lJWpzXhp2A US8vpG7HtFyr/foVXQwssXFl6+LlWQEDTFslB8DS4HQIKe7kEFErAVsWxF4ILnyt7PMJkcsv3TeH 3Zwf4fxcEop//hwDvQi8OH7JGygaTg4qXk2ViGlHAUV5Db+t+vfU26eLKHOxfAKopszWqigtwFyW 3aUBmLk49Dql6z5Vru56mNPm9H6xqIIvyJWha8IGD0GN+XMhKMaGveKhCF73aoNMNlL42LoWwUEp eO8ozB4Y1V9uwt0P9mMoFtcnu6qQW1yXDmZahywzvAr/fB32QyGSl7pdIIx0l3FAsrc6j43AREzM UYa99OdoegSJM65R3Dz6/cZ/ujfR9KqKfV1U69kEFFhuyfXhF4b5C4HJ6g0dDLcIgiVDaXhtpn1P cTMAVIjbFoYF0ii8+Y9OSIy7O2u2M+ZggugROeuFP9PFi5A6/dbJEQKXiO8IjVDWZjWePye/D7F8 qpx54Z+Aw6yNC4ywGYeUV/J2kwWy/lYWaWOFfeg4FZj/BV6PRTb8JpR7H/dAfhg9EmZBuo1gKJUc rTAHWMCwrwhlaf4BmkyyFrvTEWtUM/gCIYJjxAnXhwASOUbTYRJGKuNmi/twSfJIUwzoMC8Nxhws D3X45MUGfkbcygOH2VVKonaMWAMtY2xri9iLaCoPeqhvL4QlSGoaxZnxqb1LaaFMMy7rn90uibhA +IeSbl5vMqE3UmpR+davhwVqx3WVwbHvxHlHKvU3nD8xZ6lab8bbFXLgm/ZA8WpCwxdri27UVwzo meX+PIi3NQuVQExUBRHuTiLB/4pZbZn5f1sxL+ZjIIFVRNyZrLPWBnQryH3SG+ADspoEILRpsxi7 rLZP9hA3WqevpXfPWyxIqhgeHLYZiFI/5ThW6N/A7RKvHf05I9mtp77deXlPOuvGZze817uVFw46 PIh4cnEk3pmZCZzpTYXfAcfGNN4PlGflMBd4gV1sHLnyAzfr7x+t7DkWrzE3+g+wuuT4sjimJ71b 336SScwTGWxetSQFF37QPTS1dlN42r/7M8kyRIHgOfJGb68xs4TwAn2na9yMnXz7AOZLDnt8P4/t PbceeLPY92cwWhJMnMMr+63hIxvryKMIz/9BT6dXyesci7NhifUYs7bzWGORwcaz1Fv3ymBHOUIu RUtJ9TjCprylGfwtJUU6nOkxa+wsqFCGRqHdORGWGBY9TNt99W4a+KS2vVUAuoos7GsjVo7dD03A RG00B7yaWw2LDddvCq9pptQb7/fRHuUp+5QR3lqtJWqC7KtZwv+TMupBiK7KKrWlTbbY17xjvyqM LD9r72cmYCEN9V/kvvp6pqciiwwfmKyCHAcpEkR/9CULjEHndh9Gvt4bZJdX+nk+QBt/nN8Ylbpj A27CQdPgd0bLEUIVKn6RKD9j59a5+aXHfIaiEMtrELqbAu9Z6LczzN9B1kSQLbj6xE17yrn4TFtw ciDbnn71a6PzNkugg/s9BA8jty/oLS/uHlPX+W1ewI+0l3eeA2dHZhYko1elh8BkDfrC6i1wPo7e CqJcVM31BR7h5RVE8RrwjJIzfaTSOlwDvSf9clI+9nmb6Ksy5VQeHqcfjBMQ6idmO4R9UqRzTyG2 L5AOxz/ezK+8dn5icwb1Qcs9v+lFZL/WyT+2ltIaCkbM2FAAKOFXL8F9c+UGvrzld86mi+zKm2Xc HGlEp2QdPBpcoBJIpmDO5HEFee/Zd9s587fF7KvqPnZAT5loWq7bfDlcOeGs4KAdV3Wt0JMgY5cm tExOPdaDBJlLm6M2D6p26R26AA5/WaHWUQtfenIICCoVCkHBcIfjwcNcJqg68+xwss6Zf4mQKOJF viI0ZWEHoltCThncFwKM3Hstl0Bcbq+IIe/wOnqOg6BWBnYBb8T/cv475dolTj9fkkk8tMUhRYQE zscsc9TdXNT/q+sL7xQat38fav4yK++/Jj8ko5/+VKguDg9i1PWiqghCekELjC4aM2BAssrGGY3o DJm+DYhkk43FBJbx/ZQrr0uaaBEv7Zm+OTtj/uoc9vFZ4LnE+f6CwZVCQsSemfhUslaA7xvJiOOf gNpu51YruKCIF7sauIC/WYwC0esDNefpSTbJLTx8tEBhnMxv4WLt03iuA46MOljFd6E15s1BHKxc dtsMcAA4YXiiRO1K6kEMFGkmNZcWUTpsaHgNH20qtucZXw3EvXO0qGYwuhsZ9/JY0cQbFBWSCjin P3Xk8AVYMT5RZoInaLTgp7/nok4TRsw7RTCl1zuHPKHw/bynDAGUfKn2zI8PYY/Fmv5+CREMks47 hEYJOSilruEfv+qSuaqHXLwJyedJMZJ/FSpH8P4P0Cl+ZfDRhISRY6ZWEF0AMfxMxIuSCfgn9E3s HOGaI23XrkP/iTfdypXZ9OsFzDGbbU7APVwrMk4XAbgFJHkZf1yiYMvzWhuKzDnZMQ4DRi92FofZ 135PT079oOnezoqHitZgpyX+dWY6toBFhVq9n23QGVSnPfYZFuaPdvDfKiwmJD/2AhI5251ooVgn 7cEdoQloNqutQF9p2U8ec/S1MIEIsrQLXhohTnNr2VLrdkKnPDyzZVHtpZn4VqmTRhVJSqPAaW8o s82cwHdCwJ7yNhsW5HZ2e6DY3G4IU1Xw1IgdJGVl4KQGypsfPN37Nc9PPzQxRrIcj8S96/pL5nHI QMvRsN9OXueTc77NIZX2M+Mdb9Z6GAbffD816RLSBaGVZF6I0Pcj1pBef3MEJz6hboN8D0IJtb2x T2vSJQmEcwrAGT/CPoCkgm+hj86ETiZfHSjmkbNKXQ1i30cJClGlsloEmipzVThkTnXd+ZBXxdxC K1Vl5tQBSeBED2e7KmVyPxGe6qMi9ARlL5KaGlEm7sEvG8MEoPnhDdoTDtdkiOcSRFniIVEPUVVS 9i4eXEvmav6wC6W/AcyovedMv9vDxrmpJl/tpeyIuZ4BhrfAvnnL7m3m8u+xhNR0vVYXqaiGBD1z pLNLnFQe1x/IE/UA5Kljt6cTmM968/j+zbY1aUtEedEstqzuFnkdUHxW231Om3v/3CR5qg12ulsJ syKDEAkj8ezWTKW+WPbyfom+cAVXrBy1t34RArJStPOHZcVoSpmDY7bsTguGIxA64I+p6cqhle6+ rjJCqkWeMnC3j942pObvlkupbrjVZ4PmBmNitReeqfVZx4mQKyLVb4YpYf9N6kgtcG/fYWGHHF0l lJLZ07w+dSbiUSj2EcRaeCOzx70DP/g91crbf7POmLLqJqabpw88Zs+uTlsoy4RQ6SMgwZwo5yan fiA06WvjlwkY1t/gTmUHDcMFY1P7n7/tkLeR2RojWZ48gL+OCtzqxU4EASTCV2eSvUDwJZwBn5YA iXJd4u9EPL4MmHSJFoPRjUOE9Xux65Y1Xd1L0GBGR7DvXuDqkONfqnZN9U9UvB+wqkXA3sKGsFtD wtFgUH/xJSZvnONpdvCGHy6+c/ODcFJdLuWHWDJSJmMz2aj1G4kHpWM77l04CZa75pGGXotkpAfS QoUJAskVzr4DlXADyqgd3NK2motQ365Yee1ceUYF1ifxzIvt9hjQn6ZXplOYAs48tN0x6B1W4HL9 /ATBqaWQlvZWRjSoO7tPyoK2f168gtpYH2wUd/l2L6qiJGRRq7PFTNsE423mBfzV15M5DlEDK8B0 1g8ZpeEEPv6GFGu3iMBchHSG5snwfezdel6dVa+QZ57lxTeUF+HVjNXrPIcOid1LfToMvZMxaZBy oyU4N9eRsdZ9uW43y+I1LKLwvzNkdMFjexoS3B8sRdoUQlZShZAJSldp2tjwuPgepw1AClUSKlY6 5JaLnlf4nlhAxKOZG9GWFVBawuq7/w7RCDXVNGCrZXa8dNoQtNdscw0/EV1c+eYVunhBUfzUo70w xPPK0uaF/IT7T711BjwiZS/RXEm1X9O1Fn6ZwUjP4sTyP0WZa/jkJ2Z3j5UAx4NXAsG8O9D73haN h7uSZdrqLHqu5RE1go+kk8e84aBtVPNjl9zmQyMMcQUMxaFDmJNi89NQDqAE1mdtPgKxUGgLRf6t wkiLFWATPkv3fPPMsmse2LaUzvEox26GCNRYd4Z/1bx3ds9RYHGoBv7LYL4y/yX+6a4vHySQwQMl eh5NsQOLb3nvc1uVluIUUO6XyRLgKQrfnAaXeUJ9sfqrbG+7qJGthFGvvKDSTc8mt+nVBYi8BB8V p1huIHDoQB97mZp6pJnaTUZrjkHhAfsWrwnD36rnMJs/c1xQIRYUyiZ1dt6mbNgVb+e64WMrtxt5 2qX2r4DlWIwzCeGCmejm4splCXSOYCw2nexFdFXma6XCBlEH4Cmw61/gpd6KDsbbQFd80pzPwl7/ nz9Sj9BiU1YDzOCMwWcrBQ4osFy6YWe7RPxY6EyFnQ7xQ9lH7Q6IpYDgWM5IGsyuugO9xwGlViww puuSZztSabPb8uJcTgnG9RcKhfd4zJuFpKzJvKW5wlNOok3AN5zk2ImgdjiETDWGm5Ap/OhRJEPz +6uSmXBYTTXsmc3tn1tFOoGXTOYPESGVWh2Ey4jO/98likfm2YNbjTLstRmLqBwjFtfFFPV+FUap E/Zz6iNn2yVCKpX+sbyAO0fGmr22teteyilMZH2feGum1DwLOdzMQ8P/L19HrVObLASNTjZK5L6y Eb3HmX2fpYoK+OK6QYQy6rp5DPp4CqJo1NxeOCrhsLN51kifk/m2O1GbAQvfq8T/AwiEh0yLKfC4 vH5szDxo0DP5+xtZGIAcqMm+CAcCYUHPzg5DCLD3vM2pca3O2LeWwQ9LNecAS1dksX7s0hby5A/7 Lj/ZSGdSPB8JHFLrgUHZQYTkMEkI3WGyis5GN/tBdpxD5j2afZLxlB+8Tkav1LYJE2Rs9BeGZlyx aJowo/zgWPZcHJz9mbdA6EC8irg3FU8K0P57zZn6NEuZUlkX7yEdO4I1MxkaM/neKZQH7MUb9Ebb DmXMzxWWk45cZk8DXi3JVTjOY6U4ZQ6pSj2txTwKFbniyKgLF61MLbIbWLDRV6GwpucQ/El3DnGA PERlIMhGK+siEUZIfgkLINmdYm1SY98aqux4Js5m1qBNOdHxOaYajjByCKTnzF48j4dsiSt+HxXc YfkGwAdkIWdke7nVxpYEu5j0Pu3s7Sie5cPZuGRKKCekbgC9KGshSa1qVX847e0A+6rTF9XmDQ8L sw3eebWbwEhrucXrJ+SLXoCgCBmNl4g8BwR6Q1/QEHWnNTeLZBBloOKa18FsJiRpK9KJxaUGFHMU vuu6VARTQ4YsJkhW1oLD3mXsvTxgjSHzMF3khZBHY0+8D9gNDxiwWPWA+v1yeEk2TeCPe5+6QQXh fC5H/xIekrPcfxjJrqbJ3Q1oLScCnBsIvWj7SiRGaMme2Y0srcQZNQO3ae7pRIJfEnuw3LuZFcJO X7oQCeKPB5jFTmdZhqeflApRqpSBBtbzS6pmr7TlkSXHOasGw1xkBjDZrtvL3BSoWk/i8PGIClZJ y4Kum/2px/5UlCHp7GSLd5O42sfYKwZiLw4JYYf1G81A/AF7wayLte/fmCYqTDOdBq7sWytM5a8S ZE7n22+iDRPEw/e2YD730QS2F9R2XNHSyL9gyvXZFNxuwTilyrauieOX9mvs+St5nAHxSo1NzHZz EdBbe+TfevinQ4MHIbUmOV6grAk4ZmMcVy6A2BGGcg2FWDW6mFKkEz7IP6n5iUM7SIX79xFeEjQX jaUffSwwg+O6OzwSWBF2FnCX4JF2zuyhoya1X5c4hV+xce4xN19ZXEJzbRaoa2wdVHIWjBgKT17x L0MLrZrFnQVsnPtmcSI3nGpswGl2UQ3wRgCYA8EFhEhw2x741stroCzua7/ET32iBSZ+dsFrfCyb E1cCz4obJQtPMlUD4ydmUmCWCTTMQqG5d3dbX8jxtg0qFK/Lenyoev3Kiia2Syv/Xj8kMqudmlV5 6ff6Ssc0fU0yG5QUWONStwyL8/vSxXKOJry7VvuUoc/KpHz6uRvLIFo/ewRHqQvmW3JQuNUCgVap JDAMUDXtdLRa/VJfgnhH8gnfriioIQqzgvWhiA0VuPXDzZlNs7+eF3xg0Q3R2rRpZ286hoyM7B02 Psq1pn+geMgdTu/qSalxxxUdyLEIHhhwnhVFLkd/iE7uj2nV4glQBhf6VHJUsks1ZbdyuKf1xu6U +f/ydCBzVti91PMgZevrkZCaEM/MB9XcyaKk6noDxBoeCmQdbWcyjVHFLFWKUw90VRpS4RT7XGiy jXV3r/QNhptRCsdILEeBjkjilb3/lYaipGYz+ApbKyjAq+6i/qm62VNCsPL/01t5EQ4wp7k7yAIj qzy+bZYihGNQTm3iE6NC4fyotq4i+rocnOcIVz2O0isDG3yfui5YbpVaWD0oCOfiSLBDIPiVrM81 gzMoa+qL3v/Zp113jYjNGKCxDJyx+JhpVfOwl8PpiE/KJ4YhGMF7cahnhAhtS0tjeOW+E1zftgfx OaFcgc8Amv3VQV4USBvj5cTVpxmp7OG6iczThvNvsLzVhIWxYiZbX6tecjs+4p9e5dUUkb2gMbj0 I1MZYop5A9SbQZRd7DH/0V2LNiJTaop9VVlR/J/ba6h31sI9/bX5j7xf2bmBzS2O6aS0L0+YrlXQ ePKkjVAvs5CCSJNRUBIXcMLMeOxuoJZSMDkQspWSKMQLgjbpKBiBofT4PNfiPO+GvQeMp56iLirz YVqxzzaPPsHzH9w2a5dyl4KWcYgviA5SdxTQbOMH1Zyqn+aS3fNisWPqoyirFH2Fr3y8KQ0LjFV5 oNI6RWD+mr1S6IARkRUMx7FtMP5+uxhAK8YQXBnKxoPyIyvmdt28Kid0Uudl90d+Mv6bkC8pY0Y6 9DHkDzPiUxtSp9L3CHTIZvMxVy73pobTA4xTnapjsA04w4/Jh9pP/1v0uRO2FuySmFvalMBomcvT xPf4HCe8sVnU7CTx8sGI5jm05XoelLILHfHIgTjO+/kqTOhhcT4pyPk7eUG6jVlyW07l6xDDYe70 1IdCm+lpgWNGEeFUDXP4lQdyFzGWynHJaXgWoiqUrt4vB1rjslLymTKwI5PZhVV5wK0fukmlBhqA yQKDv+EroEn9/9UpgF+UGVNbb/lHmNdwt67eL1J7avs4pwg7iSQWrRjW/K0MNYLkXvKvDw33opoF DVyANYfwqD8fUBSmonFbEjEhtcnCP7KSaF9JFEpiaexjcstHvPsHsYpLR9694K+9emnmp7vftr3S 0wndFFfg54jJlbZermiyvhAB6fxCPBJ/fw/EthD1YTAH0aoex4yPkPZp/I8EQf+386F6nigge/+O j5E0MqpLJS7018zX8B+br7nSE92LebcgUelQ+yRngkNTYrj5kYYGepsclMlSDG81enuraGdSLJUQ /acCNE7iyGdwOW7P4hRMzylYA5VspRJYyHY5rFkSbJgDKCB38JDqgJbL+Ezw9TGdkPsdNeFhq8DU laSAual+4v225vOZOhV47pqqB/n9pLq2DDKsr4gU/DtyFB2v6z44xU4g0ekR4RQb1LbcOJQ//Aj9 F0MlGuH11YXvqxqFq4tydniYq+/Gz2T+X5ZM+Qeup4Cco3SMUCaDOJpaqw0ezjeC3kWlqH6fXmv3 l7zpL1ut0X4LXOcEyl2UZCdQGhOv3hKLaAoHlcGGSRZd9CUNyVD2Ex2YdJuku0+uBLVp5HUtvZDY ZXZYnuRIaXeJjblDjboNLnwvhj3hS530KWr1HLy+9/T8DlY3VtlWrwPyXCtBU2rhdVMWsIIbxR+s HrZ860XS5h35j0EqjQAtNMb+IruU9fw6kWUaYitgF5F8AM9qZrvWd/NKeIKwRipGak0Lgxaeew1l ZpxLPL3jkgMLR5N5ls9uAVY3dfdO/o3hnybWr1uBvOOKlQRolpuNhx/OQ5Wgkg2vxbHKFvEsYd6p RwcL1uMP3q+wgTWSTZ2lnDu0vFWfu2t689IASXLZqAaBImn/FRkWyEZG99ojB50kIz7iV7vxpMVC z3Vkc2TCM2Iz7ACF18rkCd0+Aodp7ELM2NF6M4V89Jni16orow8Y0QdFhsQgG/gk4pTs0oMY9o+4 e98dQjF2BrcoNfKssMPb4zuFqLDnFFeQGPJCaYuRgGXTf3PfdfmRejXf7+qpwr4pShNCs7VFXldF 9M2LQEapQYjCwF9dYe4z3If2RMRc1G5CLlDeezWVlCjGBED7imnMH6MbWHUvakCXpC0DCsW9ovr9 cJjV2Qkb06sUWXQSf4QsnzRvZpc/vgIC4JbeuVau5jvcqQRfKzuoAnF0Y7yWU+SiHGbkGkEQRsZb /5hdw+eIQz/EJ2qG2HNjQlXmm2s/JqyBBTrsX4ANJQDQbXc/WpfoCD/3mpjtZqmbQlXU1Dp4WAGr DZSJSmQpPgdzL+b23v9eB5qSTRhWBBQaKb0mGP+IkR3sMmW+7gST4Q5zm0jGN985vD7ydNQWVHPY XqNhqzdljJBuvqqI+7UrDxnDZdVVi9nmFuloD3yU090pRDi5F6shRfsO7A8jmT2r27LFoCvgioFx 86tqFT5Mcktf8hxptJRXLLwn39j+8uEHltCtdchcNkNFdZFdRkT1O9oOht0kzReRFRMSBm6XzmsY UbrwNl2E5VUkpjMJIeix13k7wMhPN+ABElcq1uFAwS6soX63U+WOABJ/hltpf4kLpN9V+8a6v6F/ bw/Gz5wIeeg6ghyc3XRt1zjw1lAEoo+mZT9FZGHMpl0sPEtFEiZUdy4bOIgVH+L/hOdGfm3GP49D JKOdTnky3nGHhticbG+sDZ5AScyfAKgOnKGCq6OGi9pZSLHT548a4F9ak7SNHUbG3CeLHBSD8Jyv 6ixtlT5tRyoCdu3xUXY+OzmF5IVipUwnwuTEbVx3WbDWgFQXTzHw6l54YcMm0VlVPGrS/pfCHuOe JDqGYjkapf96P9tbAC/aoORN4nuoCIH1dbjxQUiYWURwZicNUO6Hxb3QNXFveeDl463Rv1+4sFEY uY06LwKG5vMklEjR/DGEQGe8ZOtUEIp9pK3MHas7Sk9XL0bN9prewO7/n34XgWnGSPvqjwHIxl1H Ht9fcS7waK967waIXTpGdL6PO6nvuHsDOdq5mA6ViAXvPFDO3How+o+D2C/ffzzCJ5f+ekyS1r2J WE1wB1WOoXOT0MNXopo/J5fgRInd4kiYAaAwAoCZ2I9CEL6Nn4A1ZUZZLw3PT1Z0Quon+KEvBu7N rzFglt0mXFvcYpiOfNPih/aiEQXCYjVjiVdcOe3lVT28JcWdv0mXp9IgDu2GR8bU+nB8ePAZz0Yg +uEbwVh/XYfP9WqQ7iEQT9O4GehKM4P8bJKIUTmkPfSImoD28q4fZqJo0YW7Ha0bWudfoh5wKW/+ mXoPeo91C+9yHhvf4fmzmeumT1RUOTP3lBCI6rQcp78XMdNl8rqab7obCz3cZXtlBBPEZfIJxowz xnGqC5U49SNAFONxP/epzMybUddBld0Y621X4kvGfwJYZXFuE7vN+HM6YhBcVARSYkXVlZ0F4o7s X++/8kuXo6fUDims6/VBGoNtlXG8LK8I9QXiHE4MHT8ObLI4fYk1AZcEHCw07u0dkyXF8MKBmU2L J9TUCZxu0Ent8B+RgdhW1dYlzcbwd5ncE0xH1yHhzbdPQTfT9yv2w2aDMy1cPRW0lvuE+hQUAW+g IG9CNNgWihpaEUxkhu2jGvkDvqJgK5akl63SQh0i+ZSRmBtR5Ay1Pu4ikpnMmRsUTR/DK42DMZTx FVYWrOiobnk58mpvJa7i3xb/2UUaHlCyBgIfE8np/+kAf6idfoorv1nSwXcTIo1KAlSy2gireofR CgobEwUeUiH8IXO51iNgOF8BuCzmFYThZ0vsdivcGdUhq6pKcmMbWENR2gz2Z400RwxXF3WvzdDk Qxcsd+wUCtjQ02wx/Yr9X2BXDnB4Th97ugfm7jVch8DAKr+0qBMrIPq2h7VH3OdJU6QxMtnyfOun ZXTWKuqmhyZA+DyWb1HHda6rHVHk+u27tOab6ZrfgLw17IO0pWKJQWl9lpCMaMBzWxua18gygx/W MAU45O89QHyLQ2HCRTWafslzzyGrRTrlp6m+Mm3cEjnGN/LMlI6MMvyoqpz8P3JV6xzdl6mbqUW2 Ed7l2bLggV11/sv/oYc65SzwNLZwB8mCnczgMFEy5u/RueDWS0rUa9arhG2bCM38IkNFFPLszQT7 QzL0Mz3qGTONjD/vwM2iTMEjPDcMcRxQQi/gfWw/+nXrr2YafhHTFH9GID+99i9BSoEDNWVBMsuO J5kxVrChhNKlvq9QKM6Q1lf9Vqw1hqlF8E8xygFsdxX7GgHDB//OuwY/wstcvPHssiApI52jr4al pmybVyHFhZ1Ygod10oQOj4exEwNN11W5mmR6GXsw7NwlPFDtTZ8md3fKTl4X9DKiWmWZ+dh9t2nI BMQZLfdgwIzc64WFXNx+QaqYxOHgpt2SaEzJ9xQCYq722/mja4IxtiFDc5jHilZtoqgdsS5GtvyP p7u5gm6rsZaclAPs7jnMrjrXc4BiwoCoJHLTGHmhOYr2OZlb/GrgF4sP9qLMeG/Ze/rh+4ncooxm qVtvoMSJfaNrEiI5GGq5filVfos8BlNvYy3jpz+ZXj3klBeyei71l0mbWp9h47nyVGp74JPnATg2 ejsW7lyt8ldzoJ0uAlMpqjDODxjMmsxf/BsOJagTH80ZDZJNWanJ29yu/nW+TYesMkRcOSYJzb3N U6JzsT36XtL46QHrTbcSZYJd8lqX3fbGbPBFLZtVzzm4FAr31nwhqcBAq0NpV+kwTTegPic3Yfbg 0bqpU8D5vlzpkvTWLf0PpcawM6T2V4hqu9Suq4DlVlErf782sJbePXtrpLmCkhT9n6Y+5X2E82sP bov47RbamxSIdIeJvEV08HcRC80KTwgI/EOZFth/hoY9EGvSSTX4A5romAvwzBIj0CnaW/pHbDQY 0Hd7UwnWElK0sXZdHr+AtSPw/8tUjJ1cTsoWE/LIeU8BXYMV8pIHIUPwv/Ahawy/6rXz0JbhHwdn d6L7kXkwM96hvFbTGS2P69c4Hl0fcVlOF011Oj0BqhSCkNPCPa0RLo1EANZ8FYx+TC7l1x+1TbRR S+avr3rRWSE2RYomDAE1fh3cKZa/d4+zm+IFKT0Jrl74gPM1ddyW9cX0xE5HCPDVSExrBACJ4CCq DuDrBfgwLjJEA3Fa68K/0Vzw7mf05Fo8Sm21/06bkXJRwvRA6y4S6hh5cYjm6B13Ghct1ic4THp1 Gun7aRJMn0UWAeFHMSlQuIiYPueO6K5YnRR2HyY+CQJl9Qssthy76TXLwNmTU9GV47YNH0dAtM1r 7VIAtbxZrS3iOyzEJsM4R4ZUtcT/f822UtyZgKk8na/q6cijIBuXE3JQbj07e2WI7fMHH8vo76n8 fx/WzG4Oys77okTmsxTiBMTXxWv8+MWTYDwBwvQe/dLhoXwr8oZIWYIvzuP7ZeBn2XxknQpJJWps O48zc9Tbj06YFGy/0BeJBHn8YFJ9Q0d2VCPWDBBsS8NAdXu3D662rekDgXPTO26kBYQR36uEueLQ Wqw8+qcP0Gow4YA47t5nDolId4z8Ye9IPqANwaP7mCn2Ic1oJPPIHUfuLI+9OmR9evsM2mMLAke4 Ng66vRG441KeT4x9Ap/WJ/runeHFmyLnZ5bGLdwgWSQt+imPdtyTdAvAZxJxDupiNVXiyEYO/kPi DvPPUTExfJQ2F8jdP25ZQvV52mLsoo9+4iPwDboElO/cMfFxfI6OLEU3i6JoH+x+ela0Gi+O20I4 3g+PsXEuY79nHrIQ4gxAxeDbWGGcsz3vR6alFDVZD9crqiPXfBg020JJIN9IZRhpI6dSJO1QsWPu ORO4Zxqz8WNi2uEdtCw9amsTUTRzm2vTrWe3/x82qtCYqAatjltKh1edlb6rW4LJchjvwTGBrwGD md6Er1K0pwEcbqlXEQPT36jYollIJYaGf7rPFZwOssWaYR0IQ/d+ruFKlIUESxGUuyfr+6HX2h2y 09LUKEAQpG7UNGW9SnignTQMYlvgXBHe6CfMeAmzH3/3eCm8CwnzGayu8kWQKPRLRM0yatb8GN61 yDmL7qzFA2bGlbIA+nEomIPHmEbmJ8WrNqzDMdUrxi7t17MH3GlDs81TKqB1XGl4W6+FfyZPzpxl yzE6tbass2cPOijXxxVKJV1eYkUJX5/xm3T8X7aDLfWBQcZo07fwiwU8zH6/kGdyiv4fCLNgMEJN LOEQeHx22mzFSPqPb+o+r25A5IArIiEpQZrEnmXhkat+jSDPNGw7wSLMRYeXUybFeRx2KfYvgGU/ S6L07mqVVucbfvV2IMOzigzHRPbLVemCCns9bjY6zrUOM3lZI0E06+8U02b0yPfT1J+CzF7diulA dF+sf06rJsO5cETEs0InEJEasetfjiihN91+5CnNkilRc0THdxndj1NANagm36/rY3oDI2rQ5o4W gaAOw6J6tWTOEfnwbCjjTdTGugUVAgKKKYo/gx7CUrT62OlpRUGNaEYtKLs6tkJRPWKTzDKrUetb b+rs+WR2ZhXtyfEDG+ocgfmrs3RtdFipZdbTrOk090NSNV3Szj0XmpplF8P/O3CQFLXfO5aV7+N2 ROS4Bq32xsH9yUTilfcf91JI/JhYEGRTlsxZHzKrb3l17mt5cIOcQzlOHfXKN8jbJyXB/xVm7CHZ Gg7J3CO/7yZI6jpCXKh5zJl6UZjHfyEQR8V/9p+SuhDBSpvKmL0pQiZ/rIwFbuQfmfli3kzjilJU sWGgRsNbSLd/yzhog75Lk42uye6C4Pul+EQAjVXT3mUwNoJ02+c19364LbJ/vCdKcuJNFDkVRSwd 2uefOv8HUehtwTNWcCypho/o9vMhCIuFtegn3Gqg2LiGYKnGljMVnMDKAZwNil9y0JXixZ8lfcia 5aLaR73U1hOYwdvyuL5rbME5bYSCzpxQ2XoI0hspI26tXmoT/rS2ahcAkqfzUniGrSosMAF7bd0j 4nnWgFijG9fJ7IR/zeAwMZ5AEr05oWjwVT0+GujZqPl3kd/Kxj93H8FlVH3HItStuimyeBnZPctv IlmsrndS10P8LYRT4dqEy9iqfEJR+QHTJFxz5vgzLqAdXrruV8AZpeJkP2GHjEDTHh5misAZybtd uSypLXLQDYuU/P+FOnPMpqmzPvKKfMr0rvJBHKrvfNlKcR9KkDchs/cvxme5ob3NxuK1X1hykLaJ r7iyMOgeXYI0yiTigZn7DK/gcKPvoOM61zYyAwvlflUFfE12F3mXmciTwbaz4fvPWd9f50J1DnnT uxndVbyhcxHaf6ZgEgo9iDvYuF6gUdVRbONplfrOgR6SRl/phwEzWnTkusHRmVmb33P9pbyWx7Sk 55nTJPYhqMUPgYWngP6HewUzEObOf7HHAAhOeASoVnrK/kGG/p+gotUEgNfLn9lZ3OQvRkGuUIBs DISLzHmYMosiOhSDAIvhdm1dZSeZvMYlSE57ysG6EMs3lVjBbWdYTRei8bUuPwTzt5Ex/e0RepEH QsoH0XgswzusqZD8rUqJXhgNzLLq5uJ66wy8psyq5pcgmSkb34zSNIl6bmWzFgk3GqPv/LybzakS msxIh3eqa17kGp5xE2jlU5HB2JlSFAkm6bu8M8Fu/JYy4W2YLYpAdzW1p6AaGZziaKJZAv6A2xJu NqiOTMuNYKm2xLu3T/njuvZzZZrf00DjDC9/X5Itb+bYE/NTpHtORj9umsqqmmx6RIPUFJcM/5xV cQBjZcDaQJ8+vqj60deLCUZfvdnHGfqOqhEQgCbW05gZckgpGk2v/uQivjuX59rubCmMm3rKy69j CXHGMcadY5JLua5Jo8/f2pErGCHutat/PcUF4n6i36siqnBcVnADkw0tiPu8kTjkfFE4kPIOXn+W SuxZwMHL/ZekLJj/YWEUyI7RCTuY6imykdB3Jf3TQPEgjLrK8u6sG0DPhfqVjWDvyiwPk46rpX5J 2wC90N7nHk0hi2wxhQkW7VZeH2q1rRQQ3dcQhV+vTA9jgP/VL6A8s+hs0A9sb/TAK5YtGYh/Uyw7 cv+dGm6fJoLx30XK3ZWpnDnuyLA28vOVuwAD65gbp+572MdLEtxEjdVIhFCJLjh1ICkrEn67OoDS cSeXSCSOFZhPJEoT7vRomw+siEhz0vWmBP9nxcC4Jv5Ge4u7jvUv4hU7on3OhEWaUojEapZS6zOY yUMkfWCLvl9P7W/OS6mmOUsVJL9R5Ef5t5+NReok14F8aQV0XjwpUVhNAWcaz9n4p8IkljyrlNnw CP5Buvlvg3OPzqYHkD9h/W20Y4GO1icOAFFFUVjp6q2hTht2GjsV6tdeBY0rH7mt5dPGyR43h6uJ sLMVfQ4DN+zRfypZqqtpnoEE+BVegd3rJ3SOMsYOAmn5ruIAV4gSbomVCrwMHAgaJSktgxJwNtzJ CExB7ahuupofnDuWlKcWdkm/51CWGephMCq3NLXAF5665lYnDCH0euEpo2L2EtzOYceiPspaGaU/ OdKWNP99OmjGZE0msH/j5k3lZpHqmLMpIf6QTBLJ+MSRol8bkfOFJw2/ecz4sZcQHPXtsZW34qAp Ogkzx9V4YiDvO/YMmIGwT0CPoKSDM6DvIiGwpU1xDDocH1uNvfa7xLkaHzdZE8RjBOVRY0252Bo6 PCccxMC1dJdRKkcsh7gDD7OsikKKbTUDvLQ5vPIrWYossjWE725GWnOEc8p8F3szhZeSs7iWM3TB FyzZ//Ad3peljyf+8C5PazA/6bp66SJQYlaHrm/uPzKuzRD6XXmrpPeF3FuZMjwuWzeng55I24AN dJ8cm28AXEwwWeKbLFwekg2q0DHRVybUAnbyZLASXPwMB/n59o9qOwB6rlzlBBxm4g0mzn2HisEn dcs1OaYpjKcQzNHOfufJJIXYW0JzE74zTQgP802scyVxggUquO2NYFkQjDIeoJfzNfwjX0qS+x2I 68uoGCRLoO82jzAatVyMgcQkU+MPcdKu1Kwqj/i/7e99p8S26Vn/UOzGnXRQkzm1U/QUuEr1pgeW J+8htVYdNuI0PFwd/xoUO4TJ+v2nYsNNcOjo2VI7PCFtnM78D0IWOK3TBctjwOhw0Lqz/kZf11Gg fRTD5vFKibHf7nAhelQVUhl/aV6N/0oBTUJiO/dE2DXI/l75FrVXUVg6kWjNqoSK0Z//BOXz5lmf H8EZwp+pbKf2vEVijgGkLWzE20XKoiI11ROKB05j+fycpr77BiqNwciTINfKXQTnd4iEv0AOBaGo 2dT/LNclelCyLObXNI2G8GmOOOrUqke3vUgjlf5NCvv8ro/eCNdGitoaudK/ybz6HppTSxbOizOw drOgjsPFevBPfRCamiIckSiUAbk07Y6HzQBDRNJhn9XFFb6JpN9wsWzWrqcJ7lXQRuXgeRZwpqnx eETW7cwhVY74QkivhuuHgCAc6jIDvczxzPpTr054/mwrzL8GK2IDIrWereOATFpPtlbTMHhDoO0R UPhMuyRvKhJ/WBDX3TAhTSgHmbbMJT9YuuWC2WNWXgUfmeV0pC2yUvC2qySM3MSvJxDleD+aRsXK L75UdiI5UyYJ+cl2iEht/yNb4uw0PI+XiKJHhdaiC+1eFdjuLPfoLO4uWjer2lSDd6DkfPmt7+Rb WHhXNgQjJ+1dgLWokZ4LmjJQSD7HifpnQIrHRmA/n86nfIOOOsXTv+cczlvk4zH0fScP7y3rLh35 rtxLj9puOSgjQstEJviz17J3spwZ3x7y5PahUuO62UzU5BxHt8vfM88/ojAi6h2WJTFaQIVcw62X AKd51nJIe/y8PhbvhzlOvEsXVHFsANHfgzzIQPghBvw7dFQ/eb1bWU6zcFqJS42rJaC37jIicAjU 07gOQAD6hCwTJHqa+aahnQlA8Yyq5kbJevyyJJcZww3PIaG0pwy91ZCXmvctG0IJrdx0P1J3yNre PVfLqf7AxnpFQERLbgYPwYQTpKYWA7Fq+GxnEdUQ+Fn7e9Ys7pIgg5k02ngdEXtcYTBprkApXi+j p2C29XEZB+3MlpRdtoZMTuCrxgw5BgASGp8i6+j6ypyufb66kpWNxjClX7tcjmDXP1b8SRoG6cAt TbdmlH/VS92cCoYjgCy5LEM5tGhKdFyMNIHHP4NQTxUvMgSImNfxpiOGZ/EiXRyTk5OTgv9wgurD 6rQ7EYHnWW2/Rb01ZZan9UYZ0g5wH3oe+Gp1ofeq4aL7M9fwjB3a3ItfD7kTzF/oAWnjAPo88R8a +HDFco3oDFGr4CpaF55rQhFaZI2eXoOJ7GZLRvQXZnBaCImDxNyfomQqq9yoeg40Asm+K9GznL6f AZbJJ9cSmBalh2YlnCqO9R/xB6y2N1aZ2o3xs9yir2B7H6NPJVjMSKwHI6EQ3HzYxvGxLTxVSggG XNJGjfLX+CpdAGilZ1cDl6YaJiNj9Xl1r/Zr8GYdXHO0sricTdQLPNx9mzK3oOOtQNXq7XDRFjyu o+T0vpnNzaGIcf4OPgS9XnfNuI2mjBPgM2I//gwrBbrMwH0NAujq3qMw9j/LEbHR/Si1G1f0HgLr XYZqe6wS96G9LIG+8GH6W4lXAz9cHYUXT+HQw7hXaMD7OTGZKcs5FZbI+XjVsPjW503zDaVTiN1F nsYmIx4SjvLOIqvg07xdE3P/w/F2/dAZKaZHfjwenhmtz6bkKDNeW32actlu/s9inZoAXTZWzdLM k2o8IMPf/wKRDAeqeH6USD/QaDeMlpoZ1ilZfkwmTXmRbw2M4Qo/9DQ3jgYw9FmZw7CpzXG3NFuP NoINFQvb7x8s9CaDEtmE9hwQlGdvGwuEOSkGN+iE37/zWsizaoxEonFei/lCJYbM9XptxpM2MGhr kUT2vpIyJU7C/TGw0OKPRdQljOQ2M4aOTxAhOXzqSMaksMIi16dc6MParuRrNoNQbkSwLySwJVQ0 LstRgR7luDdtVEHQpzy2BECXpYct80s6sRnJJQXtYHy1PgvkjreG2VxNT7xYeBjpuvabTufvp+Yo 2J6wMWND+88lro+h2f+kKOzk8XpA0bNLyxJMdZ4VzUlIniGfKzDYwMzPcgaf61RpODoLjFkjSDeo OJm0QYpGJgnibIP0+Mo2962Z/yQatP5sdoku9jKNie5A1IKbyjIzH5FrUnMYqxJOYLcj7Rmbs513 jCzDxM4+l/Y5/IbYXqPKEaMV3r3moIHlJHJc5lg9jkw/GHYw4+JruQTsFf1th9zQcGXM1ckpuc8A pWQ5fkzJUX4GoXqWQTqe9nsbvZ+YbrlVMXqZe+N9b2yBZGxc4b6n/4VYOVM74MYt7l/zp6Rcsq86 R/Yjjp1CjqvDZhB3q+0XnO/1zTjGgCEqrSA+hIXGCu3nhFuvTCs3rR33TCHEJsd8Nij64lqgeIp3 4kfjFfXquXt8WkF6KCb8HNdSORYZ4ZJ+cYfkFt4GPpn1yv4uTIRXGm7Ol4Mpw/yZrqJw8hPtHDex pjWq8C0gTaumFY+73q0oveT7dNMueljAI/9GAKg93cVumP4VkGk9ST3ik4L2kNhIPInxuV5sJ68G 68UvdBw0atjc4qeRTf3Ui82FsM5khX7tVrABHN90CZfLL21S7Xmnw5ppYq7HTo3wr4Pd2G82hgPx 0t+tld9qf2VefaSOXcO73z7s6pnzk8dRZzNd/FgnY6pfu2nnyxiFdRHbVsEdetmvgngaomS4ah7y Q/aQKlBSgq2E9VaLgAnBqp1meF0QdFy2VcGPtAXlykDLecdv82NJGWFuHx2V0bhe9BSqa9D+UDtQ jOl998CoUMlIS2DPoe9VHRE32m4uSaSGh4c9lI5bPHLSejlj9KcYy/b8BZtxXFSXplcxFf4jvfQ2 4Cmip/hfj96edofVPj0v837bsh/57j+y73Ty/wDgHqJXa4oiORMdkaW/NnxZiLX5DmzklIUBuUhs QQB06svCn9uoHoe6reBGCP1jG+vnsUwwSTwHOfozzZrAhNMdJh9y6a/hVH9ZKR6ZZ/ajjgw5KAHm LlPYFiJh0SAXL/yRFVTNpmn/Y8Tj2UXuGOzTRPKBJo8VrQbOcEnOJ1lDkzpw1PUwB3P9TBcYbZoJ lEQ2XfGKCwfxDBhs4uKY5YTOsdBARVA1cdv6qA4EiuJfTg0AM5rfhDr+d743jFQM+un4Hkn/pvYy DB8rtAYm2cuFeLXNbkD6gM68EOqRfffyYj5x9w2FEQbjzCZ4A09iyzadUNd87D4/3LDIwi0SUlST iOoKk9HeIOiCEA33M3zi0sD/g/uZSb/ZdSlBX9F8JmyXSwAvodQQ3nFs1zmD7fc2xLmTFgj3aAws 4SmrfukyrHyboM8LbfNDkp0zsAPh7Nh+axL7tnAZogNVRDXzPjWY2qIECR2eC5km6fTB7s8/9YrQ QuPvWob5fJ7w42RiFLyj/+KjPwC5DO4Ag1k53F2JNhAZrEC63QbKiHnVR/t6F9N7yC+qjNvLwxB/ 1KHXUW547u29vDou1Ac1MEqDWdC/yAYlf6SL1fNTuo0fY7v9iuMV9d4xPEWHP0q1hLHOhiaY6zZl RN/JPZEVGuE6tU4ZqA+GNzG1+z/y/Ruvtz8QE7YptYZq3JoSJfaK23QwYkSXF/D6VyID/I2eZkrM n+4FMgbXtlTRCukIXrIstF4biV5tGmEiFFcR+D393+K5oZxQRyt1nsRdb1av9s4MeHzIIpp23uKZ gHiG0Xsy9dUIPxvybv530FTDKkzMJOE+hAOM+u1bzbRdBM9Tb2KLmBsb0ZRtSN+80wA/+qYJqG3S mZVJdyl0fkbDAbtvlmk7U4wGntNafgvyNTSrovo2EaA3Pd3iGitx/PS115jFXOdhfJPiHbbm7plb 6xLDp3owybZtIVNfYnZNVZb8xmXsqnUmMe4v4LLLH/ZE1Zee4zZtnK6f7HKif3LjPb8bfeEw5Jwj aOHjwj6/U7tvCelf8KcGv5GoieijVaP8ELU27ZiFPeyVNtxWWvxOnD1krrXOEMjDV3jx9cLLgEXq Z+J6G5PXkAR16UTcUoMXX84bJRhpSmY5G16uItNYavYsctSSbTqaxYsS7WiGNzLoX38lJaGKlTCh kxkMSt6o/5Mdd95F64mvcGtRMPUiNVW3aYwh13LibTI1oKYWCCSe0eL506+VWnRq+dvbOe3i3Tpi Hcb3P8u5YG166RIJmWz6z34b1AeoqjULKbpwaXcr71vmy1vOTITdLFYlFjPKAUu3OrT4RszG2Ba3 HTBUdX2H50cEXt7U+c+yvYI74QH7X02OthSt9baypqTgV2aU5x7t5tOnZwRiuutyOIpLZoBo1Ryh U/KHsJfMsh7jclVYpdQlwrYmEA3AaI6GpredjNJo/UK2+eTXaUz6p+V0kl5F7GnV3EXIXXNTfzqv OgigjYgXfNVmcauJZxIW2Ikc0CD3Dewo2svpbunfqdSRjPk/8jWMh8PCkg2GqyrPghn9mURtIBV5 YKAUBxso/qbsDFT/jsK3t16w3saGrSyJru+E+SL+NFdzumzp1JEpyf9eFQhqlUMYEYK789jBFqJD PLpTHThZclRuE51drJEQ56FhYboTs8td0ErsJlFlWJQ/tIEMeslDUjB+kNmJZNKZ78/Ci0dPgGpa aZWcbQdgiKLEiTw2G7wKp6+ugu6t7mrrOTGbkGGoqs7jlKQF4brCgNK2lvIEjT5VW6DxmQLaBB51 iUt7CcyUKY9NUmQROMkAEXWz7ZN9ZcpdlHzi+NUAf1vgbK3no/JHRmCHx6NiYORGc1QWT1udGTt7 Y/Lh7mGFHgA6RkdH034uQJdBmoEBJ6vd/5VXJwA7RmaOiEIg0a3UPoF+EdkK7a0ZkG50f2XDgPA5 3HECUWjh+2ByXmdCChirhzHqIplqlOoPgWjo6xvnT2reMCZQ4MPRtYhYzuqu4TTabpemmYzINTSN cNcHr7YW1gVJnpaVAb7ZdEX/cxCcfopl1AHNbVi5n69Y1xCnfUEeHjvACn3frfZ6p3LTyheFH05X nOZJx1NQEziDVZOtMz0v+q2sGMLAWoUtxM5PS0ei9BxnPdgbF5unaHCCT/gREuTbpq/dMQyO3bgf gWiDTWvf928fHNW/1gLzbKmMjWg1Qtti/K8tChGrzkKzZxiXMpGm1LzVmXe84o5cK/Da9TtJnzIj 5DANYZcd84Dyysd7PWghZrBKtKTHHuNZYxfLvwuHHiMG49ZxKQl0aLcqd2nrDK5QKApMbV7gMbgX 7GqRazVudgkjOYdjp+gZdVFIEMoo+TTMLNmNgAIp0PHVUyAvoaw9EP4mIzoAmJJrYH8iUtyDXOHe JzezDbZKpPxwrnSAV9+Dx7Qr8YnYCUsm0hccDk43smWz74DCAK6nwiPl+ehGeW5E56TqvXYXIKBQ U5giLRNr9WtQPrpMlXYBFLQVZVgpI0MOGPhHYRQ+f693NiY9rG7LMaSxavF0Li4DMgYgOvHuVT/6 ODgZbyMAWju6NBfZgfeuMVgEWB4n963lpsGwUp1cE+zHY96fxdYWgfLRMa0rO4IRjYzt12j2tKK8 gMAkZpwYKqo7Bn9Tyu3KI84UH4Ozt/Go6FXQTzchvTt2vk+2b44Vk9XabCUOsHzokDyVsRjqn7gI 4cyLJQYtFGlHoa5KOBuGSef/NoVUYVWTMcAR5IkXaF0tLtyL7ixOv3sudnCToTNuz/UO0sYNSsCL 76N4bHnOqpPsO7nQeDcmWgd8tWbsf88JQFmy7QTtgxfPBPOlUs86EyQ4AEANfJyhnJ+row0XbcZ+ d0VPK7corZKgGQxVHnhEE+gp4kj4SzdkDrAm0rO0gVkpU22Yw/NEHC4VQRdep/Tkg8XJyM41ZZ5m t8MAQa+nW5tp4UaZpbsWz3OopWwgUij6C/5bj8u5v9UyNq8t6HwyZR3B5tyVB3GOBB8GlWwqjAMd gsjGNbmuWo6Tse2UW7UMIKFXzCA5m5wcZ8cpqSjjaEEb285hqMLxkmDc1PzYvz1AXDeDyN11rgzv JuV4twbcB8opiG/yZGBD1b0ZUUOm9FO/c22bGKZuPW+gQWaRMS49WGSp6HNa3SZk7so0YExgyamZ FDvPHlQfJoLveFHNN1EhNxmuBo2YEvJw3G+NQLMrp59SLqgewTFCmP5qtsl63Vfyh7Sil12zkfn0 dJzjQnKqoYpit/StPj2xM64NtrUITY7aqcS7x7iZxjBeEVM1bxADXPeCR/5EZXlMjZcb+xnjZe14 vEot02gij3pQY36e35S3e8TVKw6B+wpx5g4KOjYixUyJTyGxLp2m0pF6gHpd3qrvKc133crNQN/X 9ITSINydTEjIo6V8Olabrlne4/4eRK6fNUTwCul13rkZdx2vzZQIy7mdpUIsvBR5ifj6+aFMKgM0 kCqLjQtJBXm5ZOHAv48rjGDXAEX8zz7xK9roe/Xg4HZJa46UwnjFxY4PGYLGPLQaCv3NfdbdIs5L aa5JePu2IwY2olwFBn8JW/39SCxoFsBMnkIKyIw+bJlp3qdk2SoAHSIuoupIP2UXZmt5qHQyMioD CGQcPcg4tI3UpJ10ON5OqQqBwIeXKxh7XD40BUoh6xBpW2ZzFZg/zFEEGt2G2Ml6mn2qhL1MyVXu zwKUrYzVbyvdgbCdjOk/L0iCSWU0F3MV30tpCDWBsVhpaqDb9N30vWCIYvn7D8kjZ7SdCwr90wQA ak7JT+oNnTggvbpjuczicmmxO9RQ4bb7/BkISSWlz7VIHt1WQiSHMTnJfbnLaxtQYkvrsIIk8NmW Gw4tpINwKQY/sTAVP+/P7AbIqkSBDhiL72dGLfnoCO1pHB9QIaukf2Y4v3xRH1Jyt4PkxVIzqn/4 X6oHtYliJJLtTe1OeBQQIw0DNtwsT5M4Mu+9z3vger3RnXRXtZc5V3g5S0R9TFIw7BIgLijz60e6 mHU1s3gPzbvbIIGxkiN4xNlZg9/Cgd5RwcRwKE65w9DrXIk4ATyEz72JF5TnYctg4qhbVuolJxZ+ 8ZZrqsl/8kxo3Y1eCxo1N15kZzKtFExAQlr3xH2NxU8vNVZD/X9tUrU7ugXfXgH4BDu/o6fxZmAA b3vf+Ie8FYsPscjiRN3DYEJcyfEJ/dVyLvKBFrZ0bZNNGrutpyo0hK48bdX4WOaFNq7PeETCDnFX B9CbXdw/ZrE6W0lGKkni2OiuX87/ftsw4/46zkJuwAwyG4rYKM5ucrM6pfs2pH0tSXYlmTDvncyt LTzKIvWQeGz0RMWJnKto+kHSMH2tK1YV+dKvjBKUUFyDaDmNEhV6dG5Ib9slac0ocvZ2U1S0xHRw 5lROKdslRFbONAmrQzBgZkoUdar6NEmgcmKvysMqgj7Acwayn2zmswZJmp6NZuZlAZOXXFuXwqP8 TCzy2jUWYUOwDKtFoO0HtCBPR03ChnlmLu88ltc9cf8ioHSs+K8OJ8MttkwyLbY4GLgZvAg0C2Iv 8j70YKiY7gTfr9xJ/kumMXh9f5739yF0JeSKWSBJo6Fjgpnw0wXQqLlSiQlsjqLEEbtmGvGHMk2F fnHOsGFt8Ek0TY8+TIadIA== `protect end_protected
gpl-3.0
ecb123c4c993978be3b2e183c8fb809a
0.947216
1.836923
false
false
false
false
TWW12/lzw
final_project_sim/lzw/lzw.cache/ip/5e089f381688f2a0/bram_1024_1_sim_netlist.vhdl
1
52,972
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:15:12 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_1_sim_netlist.vhdl -- Design : bram_1024_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000001E0000001A00000016000000120000000E0000000A0000000600000002", INIT_01 => X"0000011E0000011A00000116000001120000010E0000010A0000010600000102", INIT_02 => X"0000021E0000021A00000216000002120000020E0000020A0000020600000202", INIT_03 => X"0000031E0000031A00000316000003120000030E0000030A0000030600000302", INIT_04 => X"0000041E0000041A00000416000004120000040E0000040A0000040600000402", INIT_05 => X"0000051E0000051A00000516000005120000050E0000050A0000050600000502", INIT_06 => X"0000061E0000061A00000616000006120000060E0000060A0000060600000602", INIT_07 => X"0000071E0000071A00000716000007120000070E0000070A0000070600000702", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 36, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 5) => addra(9 downto 0), ADDRARDADDR(4 downto 0) => B"11111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 29) => B"000", DIADI(28 downto 24) => dina(19 downto 15), DIADI(23 downto 21) => B"000", DIADI(20 downto 16) => dina(14 downto 10), DIADI(15 downto 13) => B"000", DIADI(12 downto 8) => dina(9 downto 5), DIADI(7 downto 5) => B"000", DIADI(4 downto 0) => dina(4 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\, DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\, DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\, DOADO(28 downto 24) => douta(19 downto 15), DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\, DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\, DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\, DOADO(20 downto 16) => douta(14 downto 10), DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\, DOADO(12 downto 8) => douta(9 downto 5), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\, DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\, DOADO(4 downto 0) => douta(4 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\, DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\, DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is begin \valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_1024_1,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_1024_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 port map ( addra(9 downto 0) => addra(9 downto 0), addrb(9 downto 0) => B"0000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
4c488937f870e0b5bc87381e7dfc8737
0.70643
3.442646
false
false
false
false
progranism/Open-Source-FPGA-Bitcoin-Miner
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth_low_latency.vhd
9
37,992
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MZXEstTSOPKn8d5gf+3b10LFSw1L9kvafhezpuljrAF/7ghdUav62CewvwgRX4SemyQaR291yKZu bGSff5WMXg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block kLYSw7WMBCamT+m4atNFnoIZxka3g3JtON0cEggFoebXF71E9cyWqze2b5I3JNud2dq0mGJH86Cd tM81uqf2Xg9WhxjI6FuBts9Vex6Dv6Nj04kCYSbuxNDshz7+gd5ia/7qUkXzcA4guNI5WUF1UBV6 vDQhVHruydJ1Ww/FftE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block lMrOCGyxZ/Fxxm6s9SRkkqLKs/uI+at6ayAxg/a9ANgJfEz/Zb4jsgW4Xt69KeT3jWnYXdV6GL0O jm2lG3IkYft69rEThC+KNJd6SQCFL1T3ZYzv/OA0eNyOCL0xoNpv5H8+4CBzH8WTy+/ggroV26dR hQoPf+zy21Zc8/t3QBPXnKLuBdUSREEg+EuSQd0FBzePur8B0T6IZAmI6EvX+dL0R/TZucTJyiX2 BTX6CcjyTSEuH7bbLRjv9rLpnNMdGbH6kj2fBldtAH9Gk9q7MchvRLlwmD+ZzXbSr+2L+Ep90L91 mZShWV7rMZzb3Dhq/4hW/q78PrJ+r6ohca3tjQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WAKJ9pPjicuiVZ/fl+UB5nOkuvOQJAs9LrqbFlgs8XDnUZpCaLb9BpTjQQ7lcfETin0krqrmPbEL Wuu6HfE8W0t30hwzR9t4xMkSGvKZ8OHZfnNuw3XYNLdqIpYQMH5RkOkP7LxnZa+4iClFwjRZiY5q qYSdY8Ga52Wi5cC2Hbo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block QjKrVi7WlHib6bKGT0OGTYs84rdmdleh6oyJXreK+5fkpjerLYbeEOPTjafziaS2WrFtudblMdrM E/LNohWFMg6HI5Be26qj8xWEs0q0AC8WTaKp6gJqvbS6/F7+AKuVdcIPelTrXKZOdyuOFLF64ju3 ybXKkvB/gCzTX5yFRChHQ+LRxfg2IkNNBF5JGaz+YyvIs2ar2kXSbUjGTl0tOC3QQ0oOO/oHlU7y bZvJ/NYdMJGcDDpZOufURSkyS0wkF3aAOdsXQRalncGVFQfbyohwEc4ZKnhd4xUEvAdlWzeSxdvO 1KZnNrgRbhhqLJkrU6oEQC+8G6eTCrAD3PT+hw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26384) `protect data_block T5hEEpYZDyI6IFna9r87axT1ja05gx9M51V3cKofAcPT3uPoqwWN9CdcaQ2czOfPxeq+BwxpiZmk 5ouxPXHBQi1Ey8mKyAPBofva6jhS6BEN7y8ZjdjeMWhcHepRGx5Z8s/XKWl+D6mtihVlJ7U0D+5S g/s6UKhwUHFsJTM45xxzVXqVWq9pOsioMGIlv7jk4HCnZjiPHFdhSbI+jbgKRnfbJHaiP8ega6VB A9DBqqZmM3rkg0V3MC0j6bJ4lyA/NCna8zJibq7G+p9HZ+7/nO/HvZNJp3h3L8u5JdSWbhOKwXiJ UjoiS5BhuPxd7kv859ById04Ss18OJp5Nd+Q/BOV0USYrelqdZ2XMZoMzhRTVJDdEhDPovAr2D7f zYYUEhvx/z5e1GqnTTL4bhD7xRYamBOyhCRFs35KwoemFk2UvrzJBqSWc4ceI5DQaozOXcDd/41u cqRN7WcB3Nt6hpfyGS9/2vjd+rZLP5xUp7muWZx8ITdmar5rQDwL/nfVCAD1VPvnO3LRVDchbTsc TASUTRzkMqPHNyU+LLk+cAvkrqK7o4W0enGAjncaoOkg2Q3qcy/E9slq7cEnQ88iXem7MTbi2WfN y0Vsfs4A6Mec/kxKQfPQgD733dyTE+EsKtpNc/ZlZT6uR5vPWlc4Ysbnd+DaZbHPhmaWWFzCyNLo 8vOMMdtKOEam7sp8E/HjQjQZXhl6AKmG2gZscHP7EuAHu1G3HxszgkGRqljaAlXvDF0oyyINW9BX gG7mg3KtacZgaQHuXQp974lkdaD5QeeZpYxBqteY9YlBX9wSoAXTSgBbb+2suwIX/vleCcMXTrXs ZYPde8h8uwlKjdCfW0ApAWU2Wc9rVDQdjbtbIBULqiGcqnLkhD47Ik513wH1Oaxez9Vz2yCYFCHj g5JCu0Qc0fVax+h1F81XpTXoZxsL2rJM/hnAsI7LYzeCDmaAK5iG7DdHEISYd/6FVksuY+ZU6qKu 9TtG3+pbC3BfZvsutgEDDBjaiseiTwFZ6MxgoJtNPKef1n8ocSvOpZsS2JPsI6JduIPnmf0h1N9w 9EiRAQlwh1ME2uwavEM1T/G+1ZDTOKfiw/IgjSt6hMZQD1y0ndwJopGjGQIL1adpcTGRD6bnPmpI XCsp9B5BL7gVeJ3VweYirBxI339wmAW87arvKFYuDbPoMZ1bYjzi701sy5Knh/eyFmG0qi1YkPxB sNYCjFgT1Dw0U7Y70siSm5UjZN7Sq6gS8+u9lM5meS7r9yIm/0xp5EwFktG7E7KTistYgS4XbDyE 6k3+TwthfHq/bUaHZxwz+ViWzcxNtyfGZ17YstLpJcjMi3pwi907NMtP3/n3R+oxRrBcF+VBzkbi GCR9KhdfWcHsIyNrCEzS1dK6tA5pUmPnehZD6fYKgd7ZuBEh2oYsWStMJl/y3A7fq8wRPEEy4f6C fY5EFhhCfsOH3MboTDCeb3gONwjq/xJQzpRgBw2QZ66MGiHW2SP9GWcmrc7VAHkH/7yAZHPCEHEH TtAO/8GHbfmbN2FTM9zJN2NG8UNwknfki/ArWh8TZ6rS4hXWLPkoHO/WzwaPZSzBWCJd+4sr+4PQ Tpj0I/JhYtPQY/hR3IolPXCCTH3TNta/LQJ6QPROeNdeiU8WBkZ/kqa4FU1ovK11H4lhtKRVLjlV SdlMZuYZameh9hqvLb1HDRBHWufGgq2q4R/CWLIVxXjhr/fSSwCrxuwQHSVdvHkwK6WZR+QkPL5p He+1RInYYXprQnF5lDGwom4K2qOWAXqJ4m18pEvGgF73Hte2R1dY6C8lhMtNsrLK3XMv9WJomptQ OYkOcVz2NiGEpZwLuofg7aCMDtBDnYyBjMh0st+00KjGKy8bR9SvTBElyn472MxM/Dv1s4CFZpwp unay1ixJt0HNNMlktvtz4/BY8hr7L5wD1Dp8HUSBvFsFchM+/0d1ogoNffdlDkfKYTHKJiXy24BP aP2UxlrjGpCbxBbwGdp9nang/Wzgg9UMnWH2c/hBAH5D+lNYO8P6R6EAJwsZsaUu9CI7PVe4HHJM rXvTdgi26gjn1kueXwCweltZAlIqRWuuPgOVKm1tyKDS9qYLIosgrCptaWbx057DrW93TbHa5vfu dcPC/7883B+SYy/VO77EpVEiElpNTPLwyPFxFNMx8cqMuJtPS1iDBxYDNSGmP5bXO/rC9DsCUzST BaEks/moElYWK0tFNYiGmv/s3/rLc8FfEe6vPnKhBahOHwkkJTqjS1XsiFPSPPRpxsrRc7m3A8zW km8H9Hw9rxismtu05K8dl+ZfEoe8N/bI9pNjd/FJlXnTIm0x7n4anMKTd7fFYe2EN4DlsLOtnzbE bc/S7dLmq84E8Umej8bBXTim1fCKQ/CmofscKeg6nmR6D9VGDFILzyzuYpcgl/Nd2NFmxXs1c2my FgOlkgOj0mOeRNDhQ7WsSGFmC+EV2TwLY3Yl3UOd68AkM1oCiUoEdkqGvokcLrODqGcHz5KVMX8Z YcRkBHKdRLKUKINPpWd6ux8lFsbSzIVpw+5JGa1UBoUPvye+9242T1SVd+UHgskmL670+KARvLIu 4d0WP0waZaezscgGa+Nl8BYg6lz7sb6jGJC9T/DPck8pdUqesi7Iw3iLfsCMN2ve+e+tKQfB/KqY +ZjvwC1WqozGAdq6hvAhFrMDr2YQztDQZBBG/4DDNTCuNHtELBqLIUbyP5b4ciEBSQfa/cuSbDeq ByY8cCxb4iH2poCBeSN0+f0/112jeUn+EZLnSqwkaUz4Hs/dqtFjcgR3kRHMYpkszvP9mRPm0Pnt WhUS1Qf+JXVqS6hX9oWD5weumsalaYiiKSoVMEwAZWVHIyf5SSlANdBGe9QCozlauOmWElsqObcC xYSsSj+HlMrGNehmm0GxdJeCSWsXjNFvuquw/6eNbf9o/lzitr7j0aAMrA7S6JPVMqD2hT2l453w R+d2YMOkwDxLliizqI8fR+WxN7LK49baR7t77hgBcYaq+VOOI02qj/xfvPQy49R+IGJ6fNolI7HT cXFSCpfqP30mnJZIw5dUCWDsR0Sa22pAUTbHGHu1BvfDNtoS+CmGxQazivicMUjfihxFujx08lIZ bMTwkppsBdxJ4a88/jY/o/2lezlLESOWOZ7H9/+9y0hTs3JUhXuEpmd8GrM7y4uCMEFyZNzOHkHi E+tG2dHWY+nMsV0qep6mxbhKTqsufSg5F7cTebDe/r7ZacSD+QXHbI//LOZhf4N4BxwBvbRRaeOJ ewxeulT8DH4OU2qLPfUe9U5tSIFFtRCWIwuLI8SsXz3K+32tofkyWKZh3UndsClklFfxGqu4EFMh SSZew+ZpJTSPmRVVlI52sXe1rpZAF1uuddWv7Vc1TOAMkZzz9IZV9jjGOlKZBH3gO5onUy6NzWn/ 1W1jU6pDUO51/dn7/MQ6+aCWI+LZNxcwb7rYTGX7bkEuPdRDpUDuVe+Uzl8XQYZBLsTRVVx0qzhP HRNMqRwRv6QQNCCawvyj9abE5vv73yBNaT48UzmPLOU/52z5wbLQbQ5d1yCtxkC+OzuSezq+H+Sx hcDAW3lbKUPWKn8Mz2qkOBX/u8VRVBzEVa/2heqK/aFB1DvM8b9rIfkHBRSetLDzQi7Cmh6+e27x 4lNCJLFShTI+7Gc852xQRp5v/WKJ1+ZPKWPUsUVjpcB0pFKYZeKXqgcIqdjLBCCjlH0PaAoK0Pio qV+rzcwmSwRzNEF4isVx0+zWxu1mJM8fYwl/J+FkVqQxaRfYsDFdrBMsdjhzKOiuk7faYXdPEUb5 neE+0en5dOyDSwj455qkqc9ni+Q6LZFALTceR6F/plw57riH54VmkOSovj0ZSUcczKqWbRsjxqpO b+0WAbI9W77q7uFA9F4X8D39MOxHoWYkgEIzlnbohFc3QpD1Rb4AigtnPbIQta/5voZhnAy3ctfM +M7qSczGLY0I/3hW2jUKt+iWzYqauYNXgQ/lss96TvYQz3CIAFqOhi0L950Gkmp/zYZg7hbR34yJ EIZF/o3soFLte7NMwW2cfJx+EK5agx+N/LIL8IzWTY4vi+7w2bgdMpUcl3ioQEa4OijO34j/IlwK hYhsrOF3oWPGVuLtwk6lf2inUubTrfTIOgtzA6gAJDSQpoX3VlEKOuC8iyeW3kRDPVeIJrhuo7um CfK9F8tYdJZ8Tr+qYppzfyW6VDb7QPSaZViRjz9dhU/yALfTB5RVs35jnCyUDIVXsnCCUQgOFmBi vRq5M/5WQsMwVRn+XqcUG0/7znTcT7ERtrZ0CeZor5wCoBn1yn2+VFjOJlyxbs7n1hqirBQg/Qyv k/xBGyJasYJ9FllH1498v8wcXHLptn3oppa4jXKT0Uc7XkarG8Q8nTu2t9vrHZENha1lk+Gwg7hv yRzvsfJF9gcdwKp6aFqoaZqh3YFFTep6rFSLzm6MyddT3MjaPtJdmQ8rOPR46mEDnrKBl8hzmebJ ufXxiScvKN+npusLE29PqGBUpGoY3LQe3ZTIC8WvWGa5KI3h4GBiVC+E+pJlnDxLpV5RFvTRQlki Vn6n6oRt4BKwPOFR+DMuJ1HTNMN5ZLx0aUn6HLTkXYTycj17qBi+1Z2w2W7MeLx7QcuAz367h/GF Xe3C6yGCC72KJi6xy4411yXl7qU2nI/f2WFtkwXguCtLrJlrCEKkj7hYrGkl/UniBJSSqpMZHKwM r3A7K5tJRH0h6wZ7cpY9jgZYwAtW6GqI+totO+1xi0kWPnc1OZuJMTTOsSD3Sy7EguYlM5PJsSHX OKS4vr5aXwTOFNByMWCI4uEKuUhn51kQjP9h5GQVJ2YNN5zUVFkup5ixW+KvMufhsyvfuuYLG20H uTkMdX/upXmzFDxxQPO0JIDKIzDHXC4Go5ZCvbU3RqLHFSBo3vVwHpFlfIaFDELpZFz25WSk1quj TZDHqJvTBIs93D1c6+p+ROD2DDYRp/ijLsCyVcx+4VNVoh+HnlS8DdQCsac5ZXG9WzKa4RTKWagr SZnZNiA5rkSDri2maWv3iWapcZRB7tQ4AHy3XTZzxV4KfPET5UItLXM8GNCTEwyEPX+Y6r5pH5Rx IZdIvgJ4UB7lZfCqkq973SIPOARRcN45IZw/sEakS8oiXSZGqwO0nAUBsuPC3kafLf9z6vpPh79D rrJ1atqFWHLGMwk1zYzhsHwyR9KHr7D975dsrr9IFzu41MhcPGxWr+ejUBSG9nv3ayzaZNgIo6um iZofhPYF4NgJdgqmR0XBob9TrLKhDCL7Xao476A3izeW/7NR3yKT0Ky6Rdtq2/kJCqx5Bv1ZLZ8P rVzrNmGJZ8lhZOQ8UvEGgvzT8WLLzqOq6zSUkFMiCbRgY9GtgOH5mq4mGpTAPUa98Gi66HtkV52Y p0lKs+BYbRBEpK9uPvvdIGL0HrRFpVYGUahqovOfvfxk3DCmJM90hnVd8YW9/ab6ZfffTlkyIHMt CfVK1ZO92uN2lADN4MzDxdh7bGkiIvuQb+KCusu5q5M2YU8qnvUzvx/UW898hKgUJIpzKnI6P6yK TFEXYQRSU9n4nX5pL/tWxhrKAwxqglfLCMbuj1+JT41FiKXkiaLnN9mBoXwAb2cAeEYhaM0C6f2/ FxqZagopTAC7M5XRhi2jh8URFsSpICLmwhWPGdlEDMzA+42e/h/GnXNXix1zqgUFLPWH6Lx9gjlM 8rJm4tQvCFJWsT4Mvp3ytkxxWq7sL3JzcavWC4Zd5cCtDnnhHaTmjIObACZwupWxbbruKpkq92xZ bHR+wzhHYO07aG869hCKxlxlVGxr7fdcbU8KlD9WS+ojFU2o7bSeDSSlYuLjURJdzDkwLQEMHkAC NxM8vr5NOKA65onfAQFqbJ+5xpZuW7srQahIHUujzluIf9WUKRV5Flq+Yrx3coXuGivsUFxw374E crcAXUp55gWs26NAk21gjCi0Rz6zVgDloAAgv5zKcmP34QwcMUL44m36DfYCPx1N0E+fhhPuKiLY NpKQDFS94XuOanieJiktbqPCWAhd7T23lHtZ1ZWad2JsKmEkniCUXS0gPWOzXZA1LYtZechjj8sd 3hidnQVfr8sjTbrU5XTtzrbB9+EmPu2AJk3An0t/YnH22l83qq7LvrMtB7nz/aWbyo57NJ8vhQqJ 5rkXf5lfs9DEBuK+fRBwJ0uXXNxBzwgNY4KEHp0NqENhrWCV3suDZojJr2IfsoX+kHiYuc4pkSqu w2s9EArUY4y9rrItgi6qNWP8BPWt3ssqJyhkHyGclybRN4fVVkTEObDoWx/DKjCvjXSqzXELIRv+ 5OR2DO2OGG50YJwh9NydXLH1G01d/wNJIB4IQ0iON/RAQ3g7RHrzPZY0uSdPBGkKmlbt2/MPJG9F II3ZgSrurKW/SswqRzYZTgvb7DrwFc5gGflD3Yzc0qHROdpzx5pW+CISud5ytWV/59Rv7eAp9QD2 KCNGP1VBcoUHhFlczEKvdAtm9vtK6ulS4kdBFPRISCK1sSXj0BJzE4TS5+1luqMz/B6xdMHZ01zB t6rO51hMyYRRvalJKWcTWsSPB+l5NutnV3TLGyMu3maztgrWdl5aXX0pYwQO5LSxg6oHXEovLRmL QUHXd6I0mK5hfFTvRgJklGID24UAdphp8R4fzRgBm8fEwBezAXVgNsRHoF5eiOF+PnNXScT5DBdg Wm7J72IJ8iP+PVte944b4Q4MoizieN8eh/Yn9PJHdMGMPuNI3V+W9N2lCRNpIqWGrQheWZmlTrQc mywcVfdm4KBLrfP6cCmi3HBs6VbuWAVNfvuG2dFCZZ+fycqPoBF+ZtSDYNryDM5rPYzz5ELdQaBV 0EC6f55/e3yrRlQOzgqkVXvfKldfU7lqVx8h7U2TTz2yzBhJrjq5X4DyiZiriXZMI5qYekCdMdYM bieZjz3Pl4tZzv6JcjNYxOBBc5R6oM7NHOPGauRwjhrLlErIX+w2fwDd8DSlZTrN+hNteyh75CzG HmC0mQTJ+AX42x2tdlgMP6OTKuVqS7pZ/2MkwcfzZVlZX3QzSivj4h4/4gradEdv5F6/3OyNp/yQ /rlIyJu7a0baA+r9xE7tlmtilhjli1JRZ0XSaaO1e4XIyqz6Je/bPNSAhZHD9hLLixXHept6ETzW VJ6x9cvUGbXaHNSzLcG6mp0PUIvsxrWbkjdpdSyo5GKCjEu898r5PcdkCxYLzd0HV/e+300bDSZi Koev9Hc+6M3HBk6RTpRnTnH/uwOJ0OEPybUN0nyq6/LrTnJ8VXSFa4IlnB0r5kWSem8yX3UDWhF/ 3PIqbn5R5gUd2Hgs2uYswAFe39bQnIOzo2I2MT9zw7y1tOZIpIglMHbf+5jSqVus0QrVLG9Oo4u1 f8Z7pwb7G0C3ckQ2KTFIxGxsXZS4b68PcHwAROmRpMPH9lPjAibGyg70NKM43JgsMVOGWVh5HUvR 9q69KnBvr3QtsquuVIVEHLGE0C0vYVd4zkMaUBM2cjzuS5KMhoB1mHwi8HgGW/bC1fDkyNzV7ICw eloYojix56CDhjySo4GfmmioIOVOsb75KWFLBBE7Bz0nLwfq0LCKJ4rpaB77nGhAbeJU+oB+9ZGv +tcvfDTr9S/C1EtYBZdbYX4y57E/t4Fk8DbljUURFipZekTd8RCFk/JpQX/q8jYG/wvHEw7wTAY3 oVRX8BOkfwXjM+XjJf6txOctUdU6nQuOB/1Vz1tpyymgO7KMvOncg8IKvJHPjUR9ONcVpOU7LTdQ Qt9kgRJYXRg6WmaNOuHmVMTulFwGXF1uMacyJP5Q+rLcIRFMz4r4toi+r16QCbcMeJBUluKpHqRK pBdVKoD7XQOZ6sO7DpG7yVM5Zq+qlrGxvyX0tGxccDJlpDlhnfkAHVhKILoI+gWtXA9RKOzgoAPB AUjzkEHds00ndtS7Q5TykhpDH9e5PRfob01rqIaZBY7KJhtCPkjaB8noFChD8RGzzzg+b+tSmrAC vFs//poeE19G4X+M1RYwgFwoINiN1BJTVoxteEMwyz4hVOG5W22m9eASrXD7fR9kz5Dyq2SNNhql JJdVh7EHptUnSIRO+D4Ob3MDlQ+hnyOHW3RBjh5v9RP202oCkAjmLb4fCbQNez2NOuica/ggDZOd oBZi8D/zd3U8z7qdzcRhKjhiDIdbivmZ7DnhWM3WxM6p243RNKi1alKVgCtViKgJS8vOyPRfplLF OK8MznZFVVbAlxn26tM60HPX8l+PEtV4X3fwmIvgan6ehaw2edUQjIDHR97FWTg/rVMjoPPaiiw2 9HVBDcYLYev5jtYP4qEpGKXlftdJ/OFofXPkCnCciB44IjU8QCyl4CPuHJwPMNkeV0uBtlk5uQSx LmUH6fMSkPpd75HxWcWl325Mhzqg17AOieDtT/aQgNEiykrWcdfI3XaWp0RBNpm0TBBwZ6HrlPvR Ql0YK4j4uQMLr00sew1NazPKtBrMg5L6dSfF6n/6Q9Vw8aFd1f3PWCZqbkzi7UbEmCDOMsmJ/z37 K647eXx3mRLT0pwOlSXIRKb0Kkkmd239RmH1D+vjqRvTfxwuBVTbxRR1m93Xj+W0D6j0ocCBvC0C nbSraJf5sc61JRnmgJWhuZY5U3enpMfWaPJOrxu/LsyacqzZP2D3TKX3lZmgyHx+1s//7j3zNi04 5vsXtrpzUlCKj7FA3Bx6IPV4LpCUBeJndlr+8hns04Aw48RX0MMq7h0bF9UdujdARg8bpzjneXEu 26ZdH5pt80iLfj0LABQb/24w6rt5vt71E6Y2vIuRY+y3rY2spKGd7t3J8DAwwoZ4ElYE2dmAYGzM J09IeTegMXrOea0pqtL+aDz8TA3MR9LXtm4RmpS21JX7obQc6LmKvHqvONDV+ybMTlHM2mIS5Oce ZWDlsWeI6asmlZNVHPexGZwkOajx3vfHbS2Sjgt6lr2nIEyw3yrq24rK+FD4eTAfUAHc94DRlBcH qceIZufk3EJZ2kVk4IvIsB6Fd5QCZLJmuPIMUSX9y7gShfcUIrZKAxjKN6qZCpCukZA08GMfKLj0 SZ40WyUqZVrzPAGRCtHJI93DLUkFXVsPuRfBWuGmV505Wgd6IXIPJWVF7XYMUd1yEiekUvxo9Fxl uLmb7KUodKVkY5fAAiihlbbjSm5IUhTmD7HfaITfBt6Zdl9EMLq0WsurAiVwUdnGouT6nEd9LZNF schYDU6odbl08iseWjoZcF1GyB9UfTnqzhlt4/0IEHqFz1vEiABj67al7WRV8sbovp0HXSei3+7s KOGv+9CP4Hi01vs5Wrqg+hKp56Bv4BZhnjo1DiRmJLVznKiqM8U+mzDzkJmWtHR9VmAjGrHR6Fb0 hV9tVk7dwzQTc6tWn6I3UPY629fKrtHXqiUEt0OZdDqvmvr3vggQkMPUcGzm/5wyCQOmIHdggM8B RRShm5I9wbxNW6AMLSWUBp7BLpWEoteNLFl3DRa/5avCoVoM//DVVuNRwCluW9NLooM/hifOw9vd DllA0wX5AKwN3jTfduI3bfkjA9uMPosItPdh7TyFtpAP4rC2JSjl7yWIEviIMn/yWYNeqUQHqv67 uCeesBqNMJwOopoNSYYnwlHNSLlaI+9tF5QFu85RzAq4taf1Dqfpz0jjcOhGEc3hp+PkkTef7E3r JhfHgEQt9Pb+uchraQ6EeEl0JWpAEoJV5cbJEaGURZCql9UMnBZRK6ZoNVi9xhdK9rFmvq6Avu2a TPpciy0wT0ylaaoVvc7HxLSV0vNNodyL87Z9FQQhJ9X+4f43KQa5ewz7nxFMigjLI9sQiUtNpadl 7sL/f4jR0EY/OWY0yKrsioz4PgTIhaESSfEd6l3ZYtNVyHPD4FoVnR3Cs3g87/ployhbhwFZl80o NL13RwBgI7sqwUrBEsHe4r0dlMh0L+WUmGGwPWjlbG6MGefNwFIZ00SAWk7/k0IytFtvjLsTIcho 5QqLSKgHXBqn2D2DpCbtl5+cmGpW+4dNgJF8kfhx4pfAj8XHIaCMPDvkPd/TWwFhgHMZ+lHtB3l6 f2EZKwZA3wPAsuUoXNVfl6wRHqSi6eOwx87R5F5aAOGnzP5By3MsG5WKILG+Z8JKRnA223m6WhYR PuzErCRgzGSGwD6U9XTh9jC/BjYO7EgnlG7Ph6AabY4Rhw1zpz2PmRVZuQAy+qAbB9OydBlwRMn7 JoXmsObXfT9DVEo4QETvMooYswVGTwpE1ihV4hMWplKxP8Leud7DOf9kO1fRubIjWP9fCCuRpK0o pEw4HjC2yLi90tdBQg5G0I8WRmMo5KTYT1rMbcmTCucqiKu+lHOwnB24Ig7CvQ5IP2Fxa4vHP3of 0RcBusgEWi1l3fHD2Hu+OTSuZ/p9JfSevecJBhIrSXDvIl5588H1B9m8R+rfhyLtclaR/PZRzocl jqih3OfLWj0JpKiqmpZb+wHCVp4WizZTSlrvMQ3Z37qEJI+L+YxK/Vm+R52dBDjk1WDnOLGzYz7j X2L6sYH0V7aF+fQaFVUn14H1ZCyXbqKsEZ9iPpnlBGxZctcwZh7C1fBPQUTsqFlWxUbKGPiqVRKS fRzFwc4kIO+ynGmBsPtW18RBv1CBAPzBCHKx1Dq+g7l6SAUxQOUyNrFLPIYOQQv7bs0EZ+AlppZM WqEoJS6/0mQXSSMihrRbetkEK7mRj5SWBbLZrt6ZVlkXCjK6wO2WR3Lhp7HUn7HT388lcNZz3FfI EO8caeZOcFsy8ERe/MuiHV1e5u9lEtx0ENKXPQOt2bnh57nfRh2MsBpSFcCCgUpuwTm5HMv4InpV 0RowQPICQNnQK9rIxCa5DUYIRghWdoCsPzMStZFKFLpE9RsiEB6A9/ppqEGyL/pER4Lf53bslKke mtFG04aUGWKSxYKe+QqrW2UV4f10N2EcfOY0l6PZJKaTLe9fMMxhVwwsWyS4OqWE8Qs37CnvapU2 7UF/9/TgyCdRiOY1GpCkkBsSFQNRObDTXjBkXHop2HLdDigRlhX8Ef92k4EtxfgrdNKVFh0ZIWxJ hdvrGaOe7ZuWCnhChMzoot36+hZHS2+RUnqH3NgiHkHVIG3qOjyHnZhdrClcNK+Fnz7SLyNsKvAc wFz2k4gCy0n02nH2UJkmtB3C4mSMfb4Edyq/bqWR52UF84CxwZu+EFVS1PqIg7sFLlN58NLF4zp4 ofkR0VGYgChQK+/K47vDsnEfXUBmR+8Gt8B2uy4g6pkeRMyEWrhchNnw6e4ONa5KKzZXQR3hBp/p HPwrvAz/f1bJGEG6Msm31OLJsKfN9Byz716dW54lo3Nft5XjvcZCb5jeevN+1Kdbj1pjBbRmyWNQ xPk1f/NPkF8cnhIqnNUCcKjVypcS2LmPtf7HMJY9JhYhtqyoQtQrGbbpS5GDgD3D57QflmklfFzY wwlE3JRmVgcAFDM0yu09L9JsUSYhwf7CYhgRwu/YZc4LjcqMn8/lHi450An4SD9JN1oau5w5XhpO E3QM+nKqgzGOS98xtD/DkWhYPAsHiOCN4VdRcn0mMz1u1Gm9F9Lam3YjgGo9XVmiCfva1nmVtEqb JaXWBCTfYDcwM5FKUSaRca9TVPUVwxoliPIYIrbotD7fpxvuSKDZJKWEp7eNZSxKw2UtpnAhMt3l JYoQZxcM8Dh3t8m6WdR3hBKnsUiqucMj1tpv7t9rvygUSgLmyURnmrKUUdF7ty+FAHYQyqhbuvnB 7HEwhqV4r0gwjUx3S+/8BjwfMs79p+xVdzTso1+tlLEa2tqnYfr62/oy5K0LuMxUSei800cpVcNY znUr+pF8L20Zjm5tP3hBGECjRpTpFkKq8mYga5s82g+9jLv2JLeQmfYr9jaKeRjk5K44gBcdarOg MfPXwSrpY5soGcG/Ga5zDvwuddL8OKDfTn9Da+vd7KTb/IUzHdqn+cHiqKWKmZhOwEhLdl1uTogf LjXmwYmk7Z2XK4wsPhU++sM0FVOPDwuBVA1hElzM0yRoySTMdjHch7d323c4ei9U3woNAYu2BP+2 fr+Tyt3wPAZDtK3lLHEimoHWolqKKBC9LlpTxB+KyVpAcXDWdYt3PqytURhqwP5LQ+EjyHlEC90A AVL0e3Z0MKR8r8etc67/C2ozvUmRVFfGGI9rn6hWufoxM9sar875aJ8Mcx/VnvOEG94KHPyer0Rq L1gOJ7N+rapghyf9e0Bd6AQF5WJDRk8in54GrzRK8UiSuq2nnekXiUI1ElkyiZ87HStilpcS3ojc hs9c89afygZfgqHhjDw25WDCfb8NFTptdghkFggJyY2TWcPcYJIZAtB0VnZhyKlCAcArFkdDUqGM 2vsENM3pLkbuj/GmwyZENi1j5ghTVbtyzs6z9vas9jZeo8iy/53CHkl2V5OgcLNdpQkgLL/rqeQG P0fbsXrKrHQ93ts3gNcZjZ/4QXD5uT4eN3NnFt8ldwf3Lj/+0VTdKBzZoHSu6ynLafk0v6pt1Bwg VTqhenxFn6DLTAschVFc6o7S29+2nJtFl5IC7mVpj807KRHOd41JjIBYsKwTRr7uvCyZv7djP8f2 q2spGus2ABn+mnE5itjI6ifLg0sYmNo7rXk+0tNZkDfdFA9g05Np5i8cuN8OVcKsyF1ephFCLRc8 RVIkNGZGgVKBuz41PUU8r4q4cpJo9ys8fqY/r9XrBMrbw3m7dd9JpZzvNJwyynGK4yvmXgrgG4zn 1pcWhbkogXdzwQ+GlsEh1DfD/vdYox84u7ngP79zferlPqpvjtEreadudXdoU9xcAG9mZfDEO+sL iJtCgADnO07llzBq9ec/Ieq+TU65OzsLMwaydNpFO+drBirZtlW4S4MVO/WPBb0UtQlihS5TTGEw 1USTSlLge1HPRy6BwVA5Bw5JOgs2/LeKBuedsJ5SswSWwoYvX1vPQzwg2e/dzANivaxYlhXquoPc y28n33pmmPpMqh3bHIXSc0R5441oO+yWiWKl8/r6kkHsTwhuAobbe8fklVBQDVbHUdTrF/I848gB ZaK8M+RqROJ/MY26nwOZh0fLtUP/QZjJ2qC8q3ukVTtHwFVqvKrFuUg6yiMF3yzm+qG9R3WWp7cj 4XeB5kivHz3camUk1U6vG8vsq0/hHQR//CrcWnRS+5tHoCzOkK1ztbnW30fW1Gg61GaFOO3pCI3H dJiL1PewqVQx4tBz5RtekEzHHdbHFAHLNFb9GGep6yaNmEVdJtNRcguWXemWFVh/A0RcJT4k3mLi 5rw8av4iuWrT7Yb45Wyd4Z3YmZpulxXqihvTJhKvXzBJADIaTgHJ9erwj4gaexePj0d1dcDFaJkM 5vjK42SFqkCxsOZKrCyfATpqIfieTVZk3rfLYZlLXNYcyTWNkBDy11Bx6od0q8raieKMk3vJ9koJ yL6aosGNsRrNOuHYbDA8pB/+cJDSrIdo8jbbWongGUvjkDur7NA3igM7CjXxqUAJeqt0AjAQg8jx FvKXMT+bSKwPmvnWjGRN5JbC6ppABvUd1Uj1ldcoT7R1GH7UtFnVx8Jf73zkNd66A7iwgUfcgnzq V2tTYGZZi+bnnKkjzVTqjd3vgy6a3qwUZv7UtTTyFiW1JpBU1eOHySDN6/V4HzRsY4l7ZSCUrIz5 idOxSc7ykEP6waId10bsR3hkwvIK1HjXbhoIU/OWAALMDKwnKCQsYfYywFXsk1qjM6+ltP6SJk8C QtpS7pIV9bPN2Jhy1TLLMrtrCHRg/jSF1C64OcbTY3F+U3O70ogGV9CvRBuBTPKqcO/KPrEmsCsU fWqDGH6rRrt2f8Q75lvEQ7GauK6vmOpI1wb/mlnsxnV+JyBlkSHiBxxe7NIOFVsrWYpcfs0rTu8J TRXO3ZBmoSQKCF/K3wu+JSaHFGwWra1PaRjT5F6KWwWG3rUsVp2segJRyv+HJnlinhq+1LXTlgVT rDps1xfSLbDMDo1/NgWsrYfhg2BEGh2KIwHx5SlUfYPeCUcDWgmruhZr6+6yazhJUvvYE1NlL0M0 Q0ILOji1bJTufyfXrmaFJRYGbWzRVh2OtFWVdckEikVXiG2vRzPc2GucKdOeHqFct7xVym1Yq6+3 lLd3RGhkEjo0Cs7sVDuMSmuBDrsN+k+UMYr9dpsNUbSNK6xZodG5D7U80XxxbatJx5hIKbQ2aJOO 9ASCR5D6rWz/ZekbQhxabupOm3CE20F+TCLsq5xBFEzjoAaK8eIgxQnT0a4Q5ZSBjgc5PFkXGM2F qMU6uhpC3NL0NfqqJK5fx6PiU4u1lkVtYvvTJePUo0cXKWVfyKQ6vR2HGmahcWcrtffsU+2Centi n3y8KpnSxkQGDcmw0tmvDACEuq+AvHb770A0svLkRJikMlGgpC/j04pffRZZXhCzoJuW4PF0JLIY u/uaKgRpmqUtdaq5Kn0XpYPgJVyaBbysZop1aidoHdCpq3Tu6PmbT6s/fpzckg0hJ4G5e27yDLNk seXHh8AubvOJYMZLmKa/0bamQYirpBP+UWwRo4xtboqteXeopbjRSULzSk/e3kNAj03gwRwq3hkS NmL6RamtowRq6u9zZYCrP/9fSkPr7MfB2mvxp47M0+UUWGSDMUTht09uzLiTkrgHsJ7UCW4AKlc4 r9fsstPCaMFNBsarh90zX0h5RgxDeYvazAvh+tdVNRYQKIOFvUR8seIxmuH2QtS4VhPOyI9qPT29 LOqbs67ifI8BW31TRz2cVyJ2gLxk45rtKVUiwjVBAZPY1RIxo/vobWfgZckMWJc5Afe5fFfcwKGn iXunXPOfHUDOcwCu1VLHn1tRUfLPMwDK1dWvkvDyCJTckqAMFvN5Bmltns1HgQjNUkifF35Ak5TM 14YMBCemGmOCL7JR3yvkgC4H7tQVJJl/cxKqoywfhzkf/50q1sAEeK+Pekkfmn8BqnYAk9ZrKMW7 p+h2vRNiaHmtU+lJnkX8QmpJbKG8GYaYvRCOuk8DrTwmTo8FYWo0G49hPYQzZvJaF653wWpXLyAw TJgw+NhibPgBSh0zuPYtbHPWWLQC6pSkOpnDGGDgId7b7BDTgnOIiEvkahyE9aUr3yM0mh7NLreT kUhudTzgn01Dcm+488aVNslTNMwaWqcaa3qygc0caRcUEb7qZu9/pkKLGFRoJYDSmYZDk5ZW1MrD P5ZuHNiUflA5q3AGmfdmJpufYsqID+doqj9xH8QPEL2gFG89iSVEJL9onCye1HJ/mOFUXYCvD54e l7SJ3OVLm+hwnRrM1rymVwRXMgwOsimqtf6IqJjMRYvUFBfjoKhT8c9SUevrfJC5IyomGi8Pyk/z f5QfwENYTXv9TbEH+B8NgTMdfpZ0lP1NxMRYKipysoLlKYUEIhyilz1R7jsQX63p1pXxguI2Pkfs 248uPc3iQs+FKSxXF8nKykJLFPbVsuM+DLv76/Lnjtn2eckrMWPY3UvNLif+EMzQtNu1GPRYikZH gpDt6vEHnPIYZ08ZHQ25CQL5H2Q1DAltWJOaT0UDBqVHgl6okm9cakqD/3Xr24+5op5sl3QzwtSy i0msayZca+e2IdAa4lqmNTjEVcv6V1NMWzliQkYyv/lFJDL+vNbpDIMtDUZVYV04Hb9494npPfbn AYjTAe/EtR84Kr+8vfaFb0kmzKVgOkWFGx8SF8sIs/iNMdLvy2pLN++N7QOOrq50kXffPqvtTp6Y BLj5yBuVesiZlhuR1lj9Reog+gWvBe/djqPosSlBiMykdQxGPdNLlR7PCJipHAP/+su3c4EWFg6a qfD7DQ1k+JocuFvnHuju9zZkywmWX+EXFY/sFRfagn1b0dfNltsvkXHXK4xfjTzsDw6mPTPoliv1 Me06VGB+psOHTSxWuMLAZZ3KllrlBlTvg8yoxV2y/yg95HFLIKzoFcCEint6mCZnOHZ4zazpV8il QZSDY6n1Gpdb1S7zlef4/NksX1GLk3bRjbqrZLcZOcCa07coUdpjUcM+AotSENPJromzJA/a68rU DPu+9zCbm4JRmLui0Yj9t3b0ahQOHZRKuPvBoswZ5d+aW73J7ZVi6lOX1rn0Hesrknk7WNZZW3mG X+XZavCcCHC54pT5pALkbjhteoWif2on/eqmP8qnLtivmNDlAhLqIqUTrZGf84OUx8iNEWQSOXhJ RDOVKn9EnJ+LlhZpl2j5bBCxVY84SzAKTY9XkZa3zABDbH4O5aQIR4QlQJveUSYSlcxMc3nTGlA5 Kcx9f91hPJwGci1gBNReojgXPV9JlRo3xE5T1c5vFgvUk4YEyhflCGZG974NqgwLzAPtCEr6fZ23 yI89ukbp/s8S51HNpTg1wATrslC2hwdMAEsfV206PYiqZ0zjY3Ur1FFx/HbGTfVF95w8yT3gyAEO tsnwLSbXbRVa5twKvghfuBkn3EZyxDU/oxPZ4V5ceOlPMYmJEKeFKYg6w7L5TyOP3sXW0/hcH6F9 6+blhYmD+IAv90sOjRLerDxM9qewjCXX8yZa/oURHlvk6Fc1R44sHqdfAG0uHUbp8K1C3Iokgn1l pKuedKD45w9pZQbfj2B1ZPr94XThATRMh3hNtLSS2v4nioiCC0xoctQn2ZOcOvZue5KzFqFY66Uq DF4PaxyIq7aO2717K7kDmlekxVmpZBhg3cdoG9Osg936Ixf/5J3zr2L2/lZAzsRHpXRfqMaQfETr dqeZrrhtLu3G7Rs6Mj81ri+C5bqV/w9KSVC/Q0+81E7ypMqZT4i9Ddx00yGn98/lZwX5ztoLRTAm 17kH/prMr+Gvbd3y2aIDqu2viDEieKpNzpUqJDQasMdkQZ53uYKWASwUXWz3taox6JzW151Fz+FE rV5MSx6gTszaFe3mC9ce9lrcUGsN+9MT6wk4yzSZvOILE8/DCjQ+SGCiBVzUqeM1qQ3ZEgh3Mlhk qbZt9HZeWvrEw1hBW6vcWffx8eFZ4NZw7360DrtYAsR9Dl65/RJvPvlV3ct44tam1qAnGeDcNMAy 7xyDdsL8zFoOMizBSdGE/W23XfgVdURZzAeuIWQn08aq0l7mPpReblGLbJPi2fjBhzU15EFVtAxo VIjcnaCYJl1lvLoGZ8S3g/V15Igh6wUYnzdFEwdlz8FgINYsX0pIFhI7dL/Fbyq0/86OoJpXWx+I wU927ZmoAKv+RrWwvkLljZlLBLNxYufDnbhQVGy1AnWrrQl6UG+QDcKvP6Ci1VQPJmGJzuJIWARu FVd3aViRa/IR44hhfjiRhpGJm13o/17kVmDuNDvl0ru6zkLs46nA16M3oWbELN3p9i8T6ZxtMWK7 hcbY8mw0S3LqJB/EfV24v8Z5pbSM65KcYpEdvpYtXoDCYq8qC0WHP4S9q/GUw/+gZoI3xPFBy9s2 1vjtdXajD5d7Nxkk75sYe6Vc9QFqOhKQpAg4F0uLVvd8tlq4K51huKyiE0C4PsQyvyn8hJGuB9KR FQFes9R8zzeoIxy0BzdBaMd3eBLnKIkVZ3LgLPNis99vwQ5oOTdNSRWUoMNfxEohVII/PSlUzCMz JYeTEonWMqqVG3L5Ynx3UTSkXrUkLYlaXbPFSdYxF5FC/tgimAaMin/l+iTUJhmK/bn580QmpCu7 KAHUazrjh8QoszK+WjOkzJjxe96zxaA3ZpRQJUuv4YDKTymifX+D76ueNPPCBZi8u5LPgDymG1j5 Zv/gTOD3FdNuI5JIUZ4fQp2zcJuviKkAm+DcbLFVaxCV2njsubuZT8uyxU7mbFFvfhWMmawEF7Ua Tizh9zTDAhM+J1/WqhzmfeTUvK9FOiawIs3EwSsdA7nOfFiR1cgtoLuqJe1pBLKM+rFD+GbvBoGg MJmVeXXwJTZ4g81W6f+Oesu1ahkwdF6p+YVYBT1fBqOLIV/FJlaMNnrycUG3G4khA3FJcDDTMVPt a9anYcOSEQrRJDBSwSRvvKevaXUW7dYXTB8wvpLmYbvdezQ8iDtBYSYnSVXAQOhxEv1OCMsXDvmm YmYnpD8S5hWbWubbqedYfp43bjZN2NgqljwgGBlnE/oZ6PBk1I5rt7k5FoXkXXVkesXv/cgEsxcT x+3Rc91HrO417qc70s58lpaZM38XkhPvxHQbvFdYX+LW+fH6NarAfzPUADFd/nm7KLyLv1M9YmeR Dh+1tieQKRr0s+ltLyalvWrweqgPVrvxdXTCbhVbRnawcVb8WoZFZawG/BpuEL5+4Igi7X3/jUpT lsUHlPTN3PvEi890KUF47+5zLQnrH2mND9erZZT7xjtzO2WG70LgC9gSwEdlSZx50/JHsolGmSw0 x5Gzw2uxOYH+Sdqm97luLHruSLp/NvnkV2gu2Zn86Ot3ufx4PBqfbtx4Qn6MFLJuU4FdeyHeBUa8 LYGf2TS44nCqY/ReQz8K09IXeMYsIBdiEXymb/cdxtD71IKdK7hTaApOkYpLndq+33J2HbPBNi9n nSiM7jQ3+QRlkOiFSGo9IBYxWK0wm45YrYcifP1surj2Aqi7+j3pjfXMSRSr0EQPauE737LTtQNA 4L2ZVxBM4g4MhDaL8iuzuj+0F+5M5VcZBWWGEdSwZbK+Kvp/JFjMymBsXG3oBePQkbGgpfl4bFWC 0JiLh5ZXcVdXDChVPvPk4DTFaw36i3vTMqIzlMno7q6HHiCS0vgjm9qmbDluGj/Wiq0pKLo9FhXe sjh813QaCRYD387RFzLw5gErKU37x+JdzVmzpeJfA4FI55aj+QzPh2t+RO0ywhYjbuEc6nRDPK7S rI1mCuQhT6flIgnvmtHqOBWL2nWYjM+9N0hL0LYjQkHuewZDP9olo3hcH9rlz3NYYJI05I7R2yH4 yqZ5Ewrxy6wyaeTpE+zGduEia324bPOJ9ccYBmK+W29I/enAATm6XGwgXxRcLRroCBBk5dYyfv5N SHCTuZhaDtSDptgt8aprDCDYiNuvu3kZ/hkPxCEmCbMHKs4DogLmUJy1U9F8UiWydzL1IPqGaIr3 bg6RY/trbVIcpwpsZZ7awV8OQ/oAC4o4rldRikQxYVuQfaBepbkGzhP+MrVA0JvFbiVacfsITnXj 4dV0rPf+6OegXExeHBkSIvU2ZF48tc5RXlB4ceAY1jrXu+Mj+op8hMyqdCte/G6aGku60FhlJFIF pDc4gPQZouUbNjwomzqLFLxDTYpKKE0TJodRF6ooWRfrxvlDwMOmFyOpi5ggL3q/nLUkvok2P5ch B+oi4nZ6GwzRZh18pyZEOHPIJKVDly/urJ16vQw/df5XxgazvGQyhC4pX6HqqUnCs3mBWAJ5IPwn xaesLhU326DvQgc+CBbvEWB3nWSNL7ecCyFHIDwQ2kHHNFk2lXuL3KD5cEAfa4vVZfzhL7A7xqR1 ci3J6Uc/rgpByJ4MTNVbqSzYANSjEJSF/vsLBvHsHERnWnSAKBb+W9daasxJwu33NgSCUMG+/x8X ekNtaKhcyq7grwQ9EgUHzMK1k40pZ36PaYSPk1S/nvvcgevoiMoOypCmM6AXpwRqD/jxylIzYKhu zzGQi0IGzyRxGlIl6uWS8MBM+ANAv8l/410wuVUaQz0l7XCr0JzqCTblo3/rwbVdVjnYPx4BFV66 OOXu3Oxo49ZgJsnazLziWazhrLHLPW+CSHuDDVpOjsm4wCePWf6DoWhetMADD6zzfZd1aUhB4dGB XmP7Eu0OuTM9nRGz89QewWrcd7/Vp+KmQAht9H6/NOue8hkwIiI7YPDp/TcmOzMwWQMi/iEKB/Fh mWAXaG/ZCJu+Djmb2L5DgTQakh7mOF/YstameEAItMHaqUqMY2f8K+T38NBytd5xw8Z2eE1414Q5 LVHgtn7xup8zX9C9lJ1gbAuuT/eokSeTJlqFIE3A92zOwg5U+6IwBcHDM/9ipmzZBeOxM2y6t2uj /nFMK4nYpABpm0wga/S0NaeZ7j9i56vC5aHuAosLa7gvAJx04dw1jTHO6VMXSQkwlmyZvZU06z7X jwipX6q/1nUcUw/ZQCD82dzOkGVSSIgWl4bzFMjHCBMlMNDR1UWV7x+m6GJZ84dMBdTf6n3o6OC3 NXhGI+5JDBljjHUhulas5sR2bZduJcPSjJ+tsVMRSA10nZQutstuwMIMMZiFPzWSgF4z8ifijhY/ JLFYThaukeWbTJ+3DsSG4WVEydXuZhrICYDWXa3tPPT3PJPaJuLIv+wddJ/5O6wjAbIeYqz6/HVC IPaHdx32EksOx4oJfS4QoP8ySTNTjPEuuRR5cCsoKzk2VYB73g7Q54XZqaqmOASCOgpc3YSb5pGY CNBQLKhk10n56xMpNv8npWT5Kh/fNC54ne0G77KpuFZ/KfINkXzCqzkE4l14Ev3u9E7TF3W0iMvP ykzVguUafZxsbjHhr3zRRWNCKgY40a0NPC4gtmogzQ8yKy3crcDKrTxJ1JAwdNNGcvu3TBvOL+uP KA99burzNhLQj+SZwNxkCJ8/iPj6GiDeXkpO4aZKK0MKeoE3GpeqqjwmpUSufNzJuEPCpJrJ+jWU DPYXLrrGvgzYKFkZI6TCVJXosoCdFzwApvG0UeStV1kFHd1uLKjp37UPy5ypRbT/AKjIl/biWSF7 lERWPX4QHIOU957qiHxJANa76yflcUubH8K5YqCe2m/t50zxwx6FYRKlXUS45y2apcKfFje5osi3 J7GMyyesQsar6ch4I5HzjaliXPylIQPKWGI+cY23dnmERXMyWdj0mBljtIyclGfaz/S5EeuEI29X aOD3IF4KOCOUSuXK7PcxGj80d6qc2tKdyzUbDCFElLpk/IqPCMcPAGIaJr7iYmXgjMJFeRK+WQ8C ERNnQ7V3qJNhmpz+YpQxTJQ0+G63Q+ZK8cv1R1eexLLzOAPzDY1y2x9kHrTSyKYcRsii+3pulxVG K9v+CKeH9gyBC7aJVAe9awdHUfCxDvSXgTyTC2RqIxRtohWlMZ364LJpfyZ6rYghxcnUdVFZD/F/ +SDD9REKBl4TjewngY+/2iKIUECZk/iau4Ezv1jGRFBNiWB04PZ5OglHb6z6wFdtjV224WLyAO/U P5eEiw+stZcpJtypz7ZAYNkCJRc4Rvj+t7QQBSM+ybz/gSNGuzjnNXhz2agjfv8LTz313tszoH7i zte4xuhRkYmeUxtAuf1r549y4lXkbQ2QjoghnZP14Uy8Gqhq65bb2Q3SAFwvFejaPxtU6h008LyU TaHxRpU8hIqqEvHxUoCp+ScdTe0nxuDAuxTj245YKyrGS1em/pSb6WJ+1IhETQQ9GJ6vhHEq3XjD I2Ziy88++ZwS5ykg8T+yVwQsS2mjwn+tZvoqACk7GqZEh4TTJ3/H4uz+nT5RxTygcfThdFehm0zR ZWXfcyvqZ3tUHJmync9zU+AFglVZrEiyChBhL0Pi8ofGaygDIs6q3DHToR1aMbKEhVBBaFiD/dEI MwoCcG46YTjLVGkKw6f7htYD08a2mH0DTokhcl9tSV1uAfSYryzaWoMpQjV5rRe+BkBMm6d6ZlhJ poSyUG1408RM3kjSpAWaKX8TgCYZX+t+8QCNdv540I9qB2cXi22YW2hzgUZNmbrwS3xhzA4TKK6N 8aOWDxktEOD2fGnM1GDR3E8FpBn++bYMZ+GUhI+8jsaZFBMVXET4MbWfdrKnsYnGEEGljbq+ci+K hI6DH16gyBzmKBZcFa1U+ElYDE12WaaFR+yacQhTIYmVdxS1FQzZ/ljE492yXLanWlNig3t0Exef MK6MR1rHi4fKI+xq7hpkCIoRKHb4/vtgTIGf/lub1RadyOIAUqodr557W7ojBMBavGEe6B0m5hmy dnSPZ6WduSLIZMwhN3tAZFh11PZsNdGFaJjaIXq5FoTpks/vVmLRj9CkeIvP3s5726mDSk8XILBf JJvWUxShODByUr7WfGgaKOX4kqbM1fKR4nTNlm56xEHSSewtAzDz1ztiQwleOhcJdnJWqB9+o46b YRr8b8rNjkahCY8dRt77s15SMoqzUVy5ijUa0FobdnS+K/1cEZ42iR6Ssy9Nen937JesZV00Sp8R DKXIu37A4ZFJ9mSj05k1RogV9/clGr4K74ohkR9IvhuxQPWL6/x0Si1O288kpn7J7m8CRTlUtcWP rZJYFcCllqK9wiqmkzzSbgsUGcvBbaSUOPY8++y2dT7yzlgVQ9DGBlHCjCLBpS83Brb6cU45kqVs tvlJbFwOxHV1I/z2BqnuUiVVPiztu/oJmFuO6gYHwIFGturI30q9N8OSAJbDcETzwxvW8VwMcfBo 12tKzv7jGr71lYo9ea4rYSUnAcDbTjKRaBDdl6cBytYWRrTG4wyipd8IHVLq27M9WUHSJMI2MX1S xhvKhXcDCe+hChHoODHYVe8oSqlBn+qgaW2GIacZ7wORhPq6FMGWyLqQZqL7/NiNpf7kELDFZKAE 4vZGHqIcXWSuaJTX2UG9mtX0LwN+tkQNbTqN1d7RVFly+NE10vMOJ+NjUTAwuFp9VQkaYsdlm7TW vlHa2r16MrB0QEbFEAniGFwlpvbfnutjxmLmkY8fVI9jxIVyTR96l3p0xfHmBMidV1ozJzC8OD7H mbwv7fL3AB+99u9xIsRVRSu13hoemG/VLQCIwn+n+Pw+3rhHf4hDxd+xn8yGJ0RuCh66dXwxlTuy pU4EGKWopUFsRSAi6gIokwlGc7VuVY58y3f21qXJebabwtE1XcGRj4nV8YunEs147kC68ecayQ3I VT9Rnns4KfX17uHkfKZwq2Yvu4Y9pN3LB1aaY2Wkbts/O7/2g+XdvN/bIFf77M0uPd0oUF/VY+BS oqpYCMiT7sJPMsvSbXqzH0ct6azFnOu7kE7KiWBIuHAvVMEI1oipzrS3Xs4727zB4llAGxoruUpu STs6S2XQ3OaOjgRYHRTdIvTUo2yTmzdd9cR9dV36/Y3Aay+EJY2bpVg+4QyHP9TgrFN2La4txPlZ Ks/bV2Da5gkest9VXdISS491M1MfyPgZqDdiyb4p3fgE1KANF+Xp+8ikH3SIvXJnf6RjG+o5rdJW BU84hx2oHvH7NzMdRMN+tnXgwyYGKh0eXPYTm80khgQ6Ybx/1IQt+TvAT4CcB08oP4GdeNpoOGwM dnCueXh4ZckTXBIHZ/Rs6vFoshwpgOuCIuFneeygm3UNAT7frTjOhfUarm1ZI0H6m8O0nOtql6Sd oRPWz5OZrVT/7CxGklab5b/VnaksmoTESseHm5eIoEAxeJ+hu2LuYIp6R/DdsGllxCoj5Lv9b+Az UL7PvIeI9hQpKCulJ6ROJnVyWqJ6tjaPJkOK5nunxJAiL5zXkhehs3hPWXO2uZFmxuLDIQxVRod6 YZkZ6bCCxzu4yng6uZCpNiOvqVQilUVngRHpEoCUvo3yNqaWXjfVQmfSvk85qoUJjv+BCmBIDNaF BjpVte0mSe8NbHM3XZC1u8ZeIVOEpT5wMVmKlMvACJVk4UWu0lXIR03O5yKvFV4V+4mMIxNnUdH/ z+r7YyOxh+g0cNV16gH6PjOxwZ+1v/a6xiKvGbLYO63GNTyi3596mUgVBn1PlW5O8DawuJwLON6y M+f9qpXVB2UtWJ/yVHk0ukRku8siJk8FRMBemZdx8fxwrmSzDaPqyKO2pc7zmaf38iYqw2OxcQLb hUPG2LeNjnwsZkjs6XDPZqD7d0QMzppbtalIURwkOy15P4LgMwWVFAwv9SDwaqyOOY0+CgiB025+ DmjpeBZg4yNKMKamA62TEEqHOrNyJ3uY2AyrQ30cg3k8p0U6D5cgRa6smM+nNzXOA5ysMe+I1IVN vOd8Qfhu/6kWUMFvVb094cMqYzNiFLQ2H6jTBU3SPgaGsPpJtYvQ9JmC9kieBdOSEzz6WMsbaN4P 0algjFyK+JbNkT94orlQIeLtS7mJGIHqH+7VVsgslufIQfBCyv7IMHgIIXbza/MriJnwlcKeitp8 2HQperO9zI+DJLQ7wHo2LQY2xezG8xNFnlzlJUTJtD3RaC/QolZL5Lvcw0NLj1O7DYhbFAkOLCim ZThi2nemjmSuo2p44fqGepVDKHY7e0fGRn9A3/kVtckczZ93SHnbO3e7Ecj2xpRETVt6uBWeKRPe aP4sf4mlhXXP+bellFAPga0LK5Y4cVT+irC1elYLMao8b00YeWWjLxzK/ctLnPToDheDF6YoLYtS xQDrIgQtDBV1Yx5SZtE6rYaH+SzzCIX3qssWgiuz36kDHDWdoaaial/FX91YWbNYnVePA2y2QoXJ tKKFeUqlbqM8ZqR5TDKR9Qx0RCekwJ3cPDqiwTFFd20YOLIhwC8ZZiKkv/tM1RDckmGVcVoFELzs jqcvBHo+iKP0m55/hBL8BPuglglXmfHmeCJ16a1/fBWw6a1IWYMQ5yqVB3PDIlfTagEjJWrHKIpS oNejsKPYvIPxzdff0rnSpDg5ClX2Jhc+U2KNerCFq++PQ/lq/jGK3U2EyXGeawFz3JheMPpokATq nCjz8KRrfUxWesBYwONBoeaWRq0rWjUH7ChphY7wRjKEB4e7iCOJFaOLa43SMUfjFLyBXxfTWJ60 78HzBJtuq6/Nwax9oBvBIRTpXfH5SCoAuY+0BpXIF/j22/IjvU3dLZZsFf5fUvXrkgFTGlDRutD4 WB3uyrmIZs/jsleNte/EmCer/mY5fnn8S4BNF4Dxk7U2cmQmnowC/fvGsMoAr8WOaHHlwC+XexWe z9oCXH41M3xkDi+351YKmvL1qP4L5Vy9eNEcDvhtZJUtHqlsVV651n54vqqlLxvXLST6k7NOrM2B 9lS2SePPbLttlduwLRhq/ZmqFZLC13jyEZ+Bj6fWDIKsJ20CLcgQ6dO40nft0w1LFRQ1K4ibZSxz G7U4V+qCp4LNgZRgzzhoQME0unDwL8xY+5/IoaNa92UxiXqv2Jh7UzUOOhT8o2KPi8m3T+Jc8fLa bshryxSH3/QFKcGE9O6gkEtV5wCtAMaRk2/WDGP8prsnSU1E7d9NDQpwK5UFYMaXVPd5iHLY4oTN FvlJeql/kiWWkl/v6r+QHcD+tNGWtDC7Hqfg66sTq/4nbmve1nxzpYtbxu6lbNDFngIXoj4e2tof 3yL3XbRGL6EJSg+qN0mgTemFBsSf3N8iBqP4+EYidegfvdnRS+HCdThE3ZQYfUwJO0DhJZ4lZH9z xH5CDsMXI2rETgHibDwZe33ANfsWG72TtWide97qUIE9ny8fwI620R0ub3vXwzAuWk7TklIOjy1O jK44i9LTzIKh9HFM7AEMp0aGGPk2ZWo/3ptLVMVeWZkiDg8B3wTzup9e+spwdE+uLErr2bTbEQHd iRcm2cHfQYBP6dBIt7bEUzhXJK6GsGmyc93GtG9LrV4vh4yB0MP6RfAYgdKIWeCWjArivWLY0YD8 AJdwAj/N6Ht6vQMEYTeZIi3OeC3k08bEGpbUiyh0nNpQejUHWQhBUH2rLlyw7IORPCaP/XD6fzP5 UWEk2l5MqmxVXpHAECPkItcFkewZsrXSLGAdzFOJFtD6BHpn5xX5ugYR3jkkd8dHwBNqXW+7f7qB NMahX/+weoU80ADXdeSVj26DeMHO2wYwg5qPI/K1oKG3Vbxj3f/BLkWAx65Rnaw75Hh5Zm+C+dE9 JQB0UqZjq2RmUXY8xLuTWh+UHhDT/2+Y+BkNobW1T4UneJYElWIDbZaCerG26EIcRsFOVGKqAPMM GaeFpPNF2Csx6/OtlBD9FfBBkhr8s7lJF8X1Vk0C9RkLd92VovA5UAmESQcYID91SEja7j2aVZFq c4WlIjVnYUb0d3+137bU6u30+P2mRnwr4BpiY4xzILXi5KVLSdgJT57NWbMME0eAsEuZiBFj7fxg C4y2h87sfzm0/c8El3n6rB9e9Kk/028etHd8ptfWHyJwJARyqOzVF9iGfXaZDxv2UWi9MlrnnSBg f+RGYmZT/buwfUxh+GjV6I1qf5f/zAQVgmafAfulWMzCNwLqGJKOGV5Q8ThGQX5gFEyJCDqe4C61 ZtUmvfxAwLKjtGUB2LXa8Qp960IOmESy/SsbjhLllJ9DonD0CBk+dI5NGj+e7kfmZF+BqmIHYk3V PzgWEXRziqTq/829ScVbnx4NU48t4CcZ/wetojbJqVr0Gqw+pwmkePyfX4hWv9xSFLVdTvXSs4H8 /NjLxtg94xx1B7rC6kgHV/j0fO1w9aB14fYxFRVafFZ4WNSBOrm3YCEtFu93LPqhMdvWSaYofUw7 tBPNXYJRe4OEb6l/7pSrzkbZDo8Fcq0IIzrLCCi/3QxfIc3mwymhBt8UKaF4/mVhpur9vJ67aJbn dCuHTqOc1wYl6/gbEjbfj1E4BZTbWMwRH7AmCsoB1aSrFa6X3h1/M4FW/i33zPNAGHI+c6FVXQ38 qu//ClYB9r1APoTBh/yeyXVAu+3erp6mGJ7rHmeFVl9AflrpEXeerati+VExmlx8PQ3Wj3qNLJ1X t1gqh68ByQ18KFU37ZoOTsRaA4FFetlgv2lFl9s0OZ7+88U7pM5bXFi1bLtpLoohxkOfMbswztkm 5qKvLAvXe9Z1ev3wwKnGrBN0ruFW3jZgM+ijMmT+2sgOXFHK6++LK5STcGZxWtx7aNuYFhi+rGpo Og2Wd9MQaM64nAlVYl+6hCzwp2mTEjAtpcnUCrKm/AuK04XtNP3PxlmliiQkpsawOLt0lzwxOrDc 0a3rEcmavUw+Pcku+0xZ1l2p482J5CJxhR7ZH2d8Dv8mfqo5LQSlsGhv2+Ul/JIPVe/6NOECfNJG 7kZuTacGenS5PyI4Z6jDicCHC8KanL6Q/4cQrO8/WPT4nyc07H3xyps+kiKfZ5t5UjQgwhDJF72m viJ3ChStoedZ5m/tiRtQ47MZNNeveOG0+vBibAwQOu1JCyOYOykXKSgH5VeDlIhTOWFaHhVoWlXQ fE5SIAZaGsU9fxpVWSa6SH9g5mflivuPL6NrZ2J9OfSHHqI19ZG75k1jiYf+YTOW6HfrjQiCX+jh bAdXFSwiCwD0ZnAijvPqmG1OyNE8sPRrfahFlz1zTT/256Sz9Kcu2+4+AJ3HuX9jNXptJn6oA/vy z1ntcysL4pj9SvWoWijn3eBpcV+B2ZCCOTb/E60Lnd5ENkCD39EJ0WOMoOcTLkdhulS5KrXgB+Ci u7eaocNonZCCbg6i1cvCglsD5nftWgkztFYAeKiJxJVdkrmh/aGWefz0SzXOyj4BYedb43VlZOOI QzZvfNmkLsqC3rIK89xv1qpy7jQ/UJVXskADUZotDq4YMKZBZegsnYeteJOOHzgNydZ0B8LB5ybl zri4+f3+B4Li6y7Yzxb2/BfowKIbdik5AkguufMhnHQaz7hbL8A4cVcjMlhtm0p8oo+nmI9AVzsX RC/J2VtU15U+xWwt8lU3cHPt+NgakwbHdKk1NRzh1MKLQA8G0L4cvxHUL60SMasf4Ordx+cg39+E igMTcPPaLXrPfN8iCascY9i0w5vFrpS/K/+W4D28gWA41WTLHLUHxLqb23P/8xpw69B1/bmL/raq YCEIfFwCFMjCEbTih8bpw+7qOQvsF3AQyt9+Fbr+SHr/tp1cKm/KUslqyDNhVxT7CvlhgBuuDbMl vrfFspieZ0LAqC4Cc2l8SL5iSfR47GLg9NuadAgW4UJl58vp+ghDjw4hj0XOECT53nWSo4+HEu/h gqAUS9OIr+JSQbwqrOZGV2c2SqYMSYsE55VNFBSAaqGHNuzfsWQfAWW0kWbQnROk42J28B8RZiT7 C4/UP7KI0r/YPBScyJ3/zMOuutAkNKJBIf7xHXBF5Nb4Gec94N41CWq1nvvrCKF8olIlT9H9Df9W mRr32724HMk85NcDMnVymg++DFgwljfGKbVpju0mAhiwT0qsTlOS4WK9kKCfEnBPw/6qRSmx2S3y rpiy1xU4m5f7kDk2klOaLQyV8IfPW0RDGHOJ1am8MhZ3CsBOOFg02yGkNSQEV0PF9WRwfvnMmyTY Jd6bzk/5MCt0LKEZZfqCpo0R5E/vPjHp9sAWT1gaBsuVoDVv26XzzTpvAX3XzkVSil0Pet89SzbS ZgnKwoa/8wOkeNZBRW+HDaV3ccF+4k15T9ITWZKOPMq3oUKlSS/JUGwefaz3nJ3J6PnCDdtrKqE7 8zzVDVyfiJA5OnM1AafFkeUSYhwGlcrSl83wHPFoGydchPIdxuyJC/PQ50MdqbwblwN5KK+Cq6FS Zcvcl8Su/eZmctuw5uCIGCOMRx3LayvRnPWW8mRLABmWMQ2RBAURUDOB5QxAsScqfJXeY3fg6m+9 9WvLf8n49f8uOAAwBaY6f99YQu+mLZCFXAfMxVLq5+LNi5DTZsDrWqJNDIymns3jYhgyBiaz/JnR E+A4T4pPfEfMMdHhdVwE+CFa2qImRWgcFph5edUFTbrXXCqe9cs0venmLfMwj6DFdKgsV5jxuLV2 9clCbshg+Qg6ikxmIc9Ix1mhEjlsMcbJGF0V9D+pG795qEZhYC4HgsKX6VKYHWmTCUCP4JpSRy6p iLNxCi85ORUOCItKNdpA3ozSJamAFQjP4ztzpeXkS/HbgzPJXZOdrRTF/SaYLMGMxWk3nvtFTNY6 Rz6FeW3WUqiqENRhns5tuVfE5ZqTmCC8v42uCJX45XVrdE0np5ezyhlE9gGA5OVt3rQAjDiZRehY 3+bzXCmStfN8MuvCjdMyAdSAkOusYmaym+1DSbRrWhFEI5L5tcrdgNUiLk7hgYDouoTb0IUj8ohj gWLXfspQH3Pw2dZC4UTTrIiTGqBNweGrijxh9dxdFjcRnbx/OwMoTVf+lRa1BN6pARd80kvecXtm VfgISLx1+ucyq4SplDZwWSviSfvIVMPqUBN2giXWp1y+6zJLn93llM6voE+2uCI/6uSC0EFDu6hv IoM313iIw0Su0DkOjj7u8zp7ulQeTt3NWIzp3N9NC31WFFE14vR1qNeS/ZAyajRTvWwpyGc/Kr+E TL/S/Z3PsshvJg/510duoojvZePFuli1aBVjbML8Z6k9ViVvUo/8nAJEs+LvxS1Tz5ZnoWCvVRsY t7j2SsLRBrGeqnlVmFshvb4OHTBd2vTTxsqkJz61CeGFOuIFPhtN+YEpPX1nh99Wlz6En+6IlJoi P0F9GHMoxIwNnUTGG+iVtf3D0+R6jgPSsJn7uZ+yt7HJROn7xvQWxeraJ8IyCPnA8HioadN9v9mA qqtzYX1q5AoIrgkHIJJ5/kJOnvTDmPaMpKqg6R0B+er58sBsbALYe9ddAreZ3H7ZyFkNRI1qrR0P fegvV5gC9/dadwEwZR7EpYYcMSfgL+wdOAi7mXaKpfN2BoF3ibT3U2vwBWahgyBz1izImojgTR3M 4eqenu7cVOkp4zqgC2JXKYsbpcwtvf55vVZTxK0+L1iLGmg+MNY9P2R2ICjuOYeVC2tv7BUG+LVe //mawzKl/qhWU6o1K7USVZqweHqY7Hkmn3GjrAAnAIIGSuQlcA5k14TksyrwiUyAiPpTXofH4Wf+ zWtxdA5tlm/afPQQsCCbnxempdhzaxPwkTdTfnWSP93sJmS6fWhnM91Iet1m2IXA+M6e71gBtnJv Lx8t9hgJzcCq7897TNF5fJDNDAieXAAr3gktRW/tyvLNXG9Qh+dTM6DPWw+/PSiS28QzBeNwxdxw gi/TDoHI91FM0hejpZ/B15/tHxbZLKkm60tswgrvbLUz6w0///wvFEz7/qBu0Zl9gc/sJblmigdD eYmjvkt3QgaLv7+oCd9HvW6LvHRok3eqCFE45mTNhPXBkzwfp2V247S2nKWF9NSXxkGB2IQ0Kx9P tMTIQUGvSjey5kyYEnpdVutzc3NPl8K2h0BAt9kh5YlRpKteNuo96KLnj66SOTptLJX+szxoLw+m +w2Ad8a/D7hw66/XiMBxbFXuHg/pIbeXjFnx/a9tUlg8RbRZlbCNSrfZYH6bUIFZv6V8SbRlO1Ki Zsrpz5ggVo6Jqp1DldBdywwUN0LMKYMeWRyJTofClEZTy/g2OuMvfa+0kP6kjfboNXPFWAKFK8eg 5WwWjsEvN++GM0G537sYvfek1LRwUk91P/vfxcVCU4J0e8oZejhnRXshlsMnfj8Y34rsJqll/7Hf tEPrqz/YIAb8n61z9N9tngsiVbaocCemgkMwQSHCM6CmEUPCwCnSHwaRgYYNhSIhcbcdhLtAavw0 DmIv/kgCokP3RzcXt1SmE7VOPyAXhbZbxGK3Z6gOOhwcaX9zSzPoWkf4fQkz5kO8e972dMxwYgZz oNUQGgPn3FLWFHMkAxNj+UcZhTKHv75CMYVNACQ2ZNNCMOKZaNnu8yKU7gkell08woYcTaxZNv6Y /Fyyi9KTqvJBZYkeu4rheEyBfB4oHeOLzsabTS4sfMuWIyhtj1L7TJQcneiYVphhR+h8EGv7sBBi oc7YCz+ehrQ310PuhcmNdEedZ0juNBQrgmGjx8z+T1OHyfe4k7bdrTwj9r1xQbM2X7UYh/kygy9p L+fTmSdHaUHY4r25WU7Dk46msT/n9mVBNttItZcHwLCVx/SCS1qWQljZZSHIZXBxS80K/Jyljo5n EA0ksnp/OnGPfeGrEJ0lkcPG+6ngGBnX/IFKX438Sp6l05G5i8TmGkUlh0o/IcMLMCjWfQUO+0Ma kYhKZekcnhBF4jNXKmWzkAvYRzsuKdOW4GKdy9HOB3onmv9l2vJvEewtcAl4D31h90am9txblGvl SUad+Zan1JNjC7+rhjtzegEeH+Pe5cDkt7JbgHphhj8WtYTOGnJmqQP6iFSsSgW8UjpAMBddbjQV eAoqZTbqpKkOYfEZXSiv1HGC+KGPQIJ4dckZdplWfEVGbv6qPRDHSVO6Isn/AFrFh2qlA1KtGYPw kZspglEfkj7DMvnyaEEvLJFmn+vVAo4IIhwzeebePFSJwuW0UC4SwfXW+mIFeIsXtxUojtciYmRi egnof4UzZTOPjIUWQr087WtiVpHezLAvSpIjBuaypgY1Y1vKTvvxcAIlJkbfP+LoKzFmlsb9ER9x YEh94CdQmfNGjNNpqgAz2gcCumRrtiKpzEU+90ZstCBc/llS9h9JiqlK8ogOX7tC4Aby4RZOQu15 8gpmsY+fRMaY1A7wyG6abHg+zfQnRRbBZAyU0xcThM/HZ2DF2CRTs0bDc23gn4Wd4vckx0TSm5ws 1FnV5Oj11WnkRcX4Sbula0fLSrGbNBhr+GHvJNHOHfgiY+82OG0Lzzy3r6AV0JIlmiev2dO6W4jb /C07NuBTp5BuEhlPZDOaAAsGISUQzc34woF9AimrGhtRuZDvLTuN41YJZP5Hosky9QM9IvIHy3JI MUSke8oozYN1iU2K/JfohI70QTsq5ngiGnpoE6nkPQrfiWzn4JWbmTpkZ5WzaUFr6ICe2n4KWIik BvlVO8bcAmNINw5AaXr7UTEmlkVNc6zXTK8+IsOq2fNRP7ZgMKzSTyq0VYeWDyZblOegGsOypAlt gRfJ+lS3RIUFqDKiUvV2b/x3KsxRjl2Rpz+7rKZ8Sw8D3FIlO1nrmTJsecAfTg0DE+LjdKzt/pNi ukreYSGYYCIVLCUWpvgblXpPCYA5dChUtQxXBz+lGLjoWnMvxJS7t+cVbDnYn33W6inDDtdLr+zi MY/+1QNQpAcWbTkUA7k3n+7flncsDlm/wySDzxhlDpmf+j3XC6U3eG4e8GYBFKfb1ysRQHnrmV9t zUyYcm8ZT7ynk1mc5rErcKqxD4DxlswdN1aUGH6nk8DyYaLEq1FwB+mMaCq9CNSew27VvVYsbaxs n0F/ofnjW3w3G6M/ev4lUlGVUpo6eJSbFni4g2wacjxd8SGrtAeSXPzcxbcj4T4fvnbHBhQZ4UF7 nKa75DzZS1921JBkXjedGGcQrPkFe/7IjcmPE3A14jbbVD6cl8iZh4KPnwcOGMMnx5YZpdwQAdzR IlA1J07zQ8LI8HBDblntxNJPMcDtYVxmrIlGJBc8+SnhbWqKajV/qYaUFifutuyWDwYaVAyljr9n vLnSOKXnHwyqMpUStahG7EzybVxzqIxNAQ2Px7lQXKTbA5nEfWG33LV65TBCryqj/EIRDFZbelVg bmUpdF/aIiQGmjFsPEO6bHVI7iL7CCxdBLuphQsYbsko6AkGRMs+vU9/IyiAtpD4+ONQPRUnlXOx 2adv0FFmnmeXTaE9PP3ivqguiP9vMO9F6azv9t7BvnreNkTAKGFolgGqhKDs+JpsVCil74EkeAIn VlhkEzBYZI1zWu+jSBxeSF66cDsDSqKwsrRaTMmOf7qfGwggxRILoNBY66InrVEZ6KZAD9siStiv g4d8NQU9DVAUQgC143MrVD4DJ6Cd+HJczUl8zOhUQdFi852ezZwjAHvdJF5TyNA4aShVfSgUCMYf iv5XyH137L0kuMdwijJExWXWG48SrAOnjjf8uoI2DapqBJTCcvlZFyoKQyvREbcONKhQqSYWXBN5 5bI+O3hgOouF8Xd7xV+pvnedIkkwLta5wvYjU0463ZnMRUiiNKaylcre1RwJlk1nwOfprG1vIAUf 94yL4YUWoBcfMbzCrx5yJD5J7r4u0uqgd660K58kOoFQyOoirpWY2x+nPFE2gcJrDTfLbpsOowgN W1x1m4UL2cNWyrhCaKqIzFPloc3RBs3vfCHHufJNDwV0vO2aZrkziA4x/Eb/6jYTQo6IaXKIimpZ LKhaaixxOshkRs7CoubWLo3ffhL1CWYPFA7GtKfRg7m0+uTJFuLA6NXOl5vYhEXkwJMH0Dff58ac Beu8iquKvK/lWvoNT/sZAzWDACKOnuIt831xpBki3puiStsrq9iP6Ow28AZbzNC5bOvWzR/1QtwI c1meafqX4A77UVV7SkmKGw6hzAgSxPdapcwgsvHIuY6yPhSiP8QzROAaZ5+VAOfUExDhfC5Fssms NVXtMg6ZplIOqjyiNzgdg6OkzP4k25tl9IzSuxl6FabA4STD21vDKDLymzuq0RK6kk/6C2tTa8C7 qlW+CTvPqkS/RsOOcdaoT7OzD2oZD8TmB8csZqKF/+8z3LaJvOR12wSd8URdAiQ95EXw6GzEhezK lFrTMgM8XpPSrQ+XpYdjcje9eLuIXEMzs2gccl+i6nO9wk2rpxabAKlqpHWtgAd6RpzhRzBFuujt ywPD1o08EpWtQK8bPLiN/TLP+9Cv9/o4uWE5PZDKpDXZKUXDe+5dLbZkmCJss/IN9fv/D5dRqMhj 7hWir6Ez/W47JTn+w9D0WnD4MUb217ZOnMUYLh8qOgqMXCsRF9L8SRCgsA5ZxuaG7E5O4+Bczlek +8hXP4IzRSrcHK7p1gvQySqwFrprSTUBlzZRkJXCBM2JUXlIO3S6IriRnbgZTDqJlzmX3hPykug3 oJOAhwmtNSS+vCVC4/09hKxcMjTsfs2/Sjlm1erFAPjV72A8BjpEIQvNV1+XeIZrc1/0MHr8pXTH lsUfD7tsBdG9zHsRi7onaGviXo5YNIsQiJfnLNVEoe6DeEw7YwVPS60pifgaqPfTwWOPGhErlyIc UrUpvW9Vq0Sc3Bsl9FEkkigD/sfPXT/iMD2ofM5Nja47sonJk1zsv0O/pypGdrwxl9zQOIEEB8E6 NaUqGMWz/awf76yN/Yv2dBEb1ezbKRQ25f9r0e6d+DhoXqRjCD0dUSYXHLdKl2vQQxDs0bAbWppx nQjXQyAH94evYKnaiuOwhloFPJrgD4lqK9IyFV4CW5ezzvnB4EGRXVSsEQm02NueR9b0s8glpYR0 2aqAzlqhjWR9etiElGNwRh6ptlFfD6z4QfBd0xxw7EAvQk7V0ZhaSks2DtpUT3HZGyiMNSh7grmL lqomAGWqn9XNzqD8uj8H05Q8wjz42yMZlWM/lkjKC7csQNgip1bFhrTqOjclg8i9VVJIbA6dLGG4 m4qbKfgOVJrAmwhZvHM1yUbM4q5SZoBiNU71G6wCyVApGqV9hh2Q0OvkWQynr2IITl8K/J2z4+ZX z4CXSmmx6P2lihEr7hAgYg1PRxJFt8MgKfDjvSS09OqAvOL5iVVIq9bRp+0l4FDLN2plf6fgizTT hKGl+YQWNaC5GKNtIgV2J2GY3BegqlVrviWTTfbsrySw+1/96Y8qAfpWvaIUvuGUE0LCXputvM2B 0wa2+0hBVzapn0wYyozcUWLeUuAHNcaUjcDFGjWogoU97kSx3CHtDmkKiIh77B6TvbMY1c3n2eZ8 hFJ+wgyyNNGOV2UNRcJHky3dqWpQs29GrLRa85lpfJOjJghxKx/vc+W4cxYfzUp4OSpYbUjgdiPz KrY7oqG4K1YPtM7PbdcvMYzZU3NgElBnZSqEQsjg30f1COee2kborzNRMTAzOmqIAA7n//4dxGnX 61L72/8Tq/MVj7eF8F0Hpban6uT9Sga3rmHU6zoxuTUwzMPKTnw9JABcGEGEBXE3OFvhCWow4wI0 00oBEosPs/0E6RA0JFBcATAs8Q/hVQ2AfDYIGQ16L5NIlihdukzSWTmeXnpWs4uC7qSUdtm18e+b 06IpO8j86lCTWYRnc0a/U5B+ofJPfRJ+zgyLbD+zhW38627y9VyS25UwmTmkyMaAJS7gMRj4VBD5 Xiugzohu03CN87trO24SYjjPmw2M4lpes217jzNup7Qkh/eykItLy7jrTkmo2iAMmniKsEM+0ORG DUaCtsy4q46Qfa1o5aP/VCWr0k+Tru5GSnv7g6rWGrKJuXpiOlO5fxfNsiYd/9/QTIgr/0yjonfe HapWGPIjmbY2Snm1mW0wZkk66ANGRsgc+YTUQaNt7k5YEGP78uWkwIzq8aicj4ZNxqtgGdZUMHPH JWF7Vrv5xHkF2Bw99qQv6AB6/D3HjwK7jCdXck3rlt99Wb8Qqn16aFeXisg+uPxIEdcH57vRKjK/ lQW6oaHFS9IrVc65VOCW3HsDQIUkMJO7UXeyeG+4iGdUFyBkWX9d9oxeMrEgejWgCarF6o9Eiko0 CLFncP4+oyPZM6NvYSPfjlLIVIR2kp+24fTK+htBSnv9B5qJDrS5n0Xh6SQUHuAsNIyWFAQ/frCA 5UFBoXCtEH0y8OYLokKmbEcVF4YtqYa0YxClNcAZR2mIOjGa0ydQ7aRmCj9lmFGGQDX4dX1NK4km jes6MKcgYaJsHJiAwZKgpL3T31ASKR8jmDYQg/iB1vRmZ13JtKnZEoAyIqoCGNm8Bkic8OD1BuWT +o2JXMFIkkhPAsSWN2MIs6FfZE7a1sCqKtWxWuemGEGX0xoiplZgEH7mhxKUrZDa NV4= `protect end_protected
gpl-3.0
7e9d291627a2138051efebba3b35b393
0.947778
1.831999
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/bitset_next/_primary.vhd
1
2,758
library verilog; use verilog.vl_types.all; entity bitset_next is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_pp0_stg0_fsm_0: vl_logic := Hi0; ap_const_lv1_0 : vl_logic := Hi0; ap_const_lv32_0 : integer := 0; ap_const_lv1_1 : vl_logic := Hi1; ap_const_lv2_1 : vl_logic_vector(0 to 1) := (Hi0, Hi1); ap_const_lv2_2 : vl_logic_vector(0 to 1) := (Hi1, Hi0); ap_const_lv32_FFFFFFFF: vl_logic_vector(31 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); ap_const_lv2_0 : vl_logic_vector(0 to 1) := (Hi0, Hi0); ap_const_lv32_1 : integer := 1; ap_const_lv8_1 : vl_logic_vector(0 to 7) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; ap_ce : in vl_logic; p_read : in vl_logic_vector(31 downto 0); r_bit : in vl_logic_vector(7 downto 0); r_bucket_index : in vl_logic_vector(7 downto 0); r_bucket : in vl_logic_vector(31 downto 0); ap_return_0 : out vl_logic_vector(7 downto 0); ap_return_1 : out vl_logic_vector(7 downto 0); ap_return_2 : out vl_logic_vector(31 downto 0); ap_return_3 : out vl_logic_vector(0 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv1_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv1_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv2_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv2_2 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_FFFFFFFF : constant is 1; attribute mti_svvh_generic_type of ap_const_lv2_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv8_1 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end bitset_next;
lgpl-3.0
406bad7cabccc7d6eb2f5f1f78309610
0.582669
2.85212
false
false
false
false
wsoltys/AtomFpga
src/AtomGodilVideo/src/MC6847/CharRam.vhd
1
16,743
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CharRam is port ( clka : in std_logic; wea : in std_logic; addra : in std_logic_vector(10 downto 0); dina : in std_logic_vector(7 downto 0); douta : out std_logic_vector(7 downto 0); clkb : in std_logic; web : in std_logic; addrb : in std_logic_vector(10 downto 0); dinb : in std_logic_vector(7 downto 0); doutb : out std_logic_vector(7 downto 0) ); end CharRam; architecture BEHAVIORAL of CharRam is -- Shared memory type ram_type is array (0 to 2047) of std_logic_vector (7 downto 0); shared variable RAM : ram_type := ( x"00", x"00", x"38", x"44", x"04", x"34", x"4c", x"4c", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"28", x"44", x"44", x"7c", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"24", x"24", x"38", x"24", x"24", x"78", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"40", x"40", x"40", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"24", x"24", x"24", x"24", x"24", x"78", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"40", x"40", x"70", x"40", x"40", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"40", x"40", x"70", x"40", x"40", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"40", x"40", x"4c", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"7c", x"44", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"10", x"10", x"10", x"10", x"10", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"04", x"04", x"04", x"04", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"48", x"50", x"60", x"50", x"48", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"40", x"40", x"40", x"40", x"40", x"40", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"6c", x"54", x"54", x"44", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"64", x"54", x"4c", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"44", x"44", x"44", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"44", x"44", x"78", x"40", x"40", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"44", x"44", x"54", x"48", x"34", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"44", x"44", x"78", x"50", x"48", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"40", x"38", x"04", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"10", x"10", x"10", x"10", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"44", x"44", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"28", x"28", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"44", x"54", x"6c", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"28", x"10", x"28", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"28", x"10", x"10", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"04", x"08", x"10", x"20", x"40", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"20", x"20", x"20", x"20", x"20", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"40", x"20", x"10", x"08", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"08", x"08", x"08", x"08", x"08", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"38", x"54", x"10", x"10", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"20", x"7c", x"20", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"10", x"10", x"10", x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"28", x"28", x"28", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"28", x"28", x"7c", x"28", x"7c", x"28", x"28", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"3c", x"50", x"38", x"14", x"78", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"60", x"64", x"08", x"10", x"20", x"4c", x"0c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"50", x"50", x"20", x"54", x"48", x"34", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"10", x"20", x"20", x"20", x"10", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"08", x"08", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"54", x"38", x"38", x"54", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"7c", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"20", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"08", x"10", x"20", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"4c", x"54", x"64", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"30", x"10", x"10", x"10", x"10", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"04", x"38", x"40", x"40", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"04", x"08", x"04", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"18", x"28", x"48", x"7c", x"08", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"40", x"78", x"04", x"04", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"40", x"40", x"78", x"44", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"04", x"08", x"10", x"20", x"40", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"44", x"38", x"44", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"44", x"3c", x"04", x"04", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"00", x"10", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"10", x"20", x"40", x"20", x"10", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"00", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"04", x"08", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"04", x"08", x"10", x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"28", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"04", x"3c", x"44", x"3c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"40", x"40", x"58", x"64", x"44", x"64", x"58", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"40", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"04", x"34", x"4c", x"44", x"4c", x"34", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"7c", x"40", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"14", x"10", x"38", x"10", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"34", x"4c", x"44", x"4c", x"34", x"04", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"40", x"40", x"58", x"64", x"44", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"30", x"10", x"10", x"10", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"00", x"04", x"04", x"04", x"04", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"40", x"40", x"48", x"50", x"60", x"50", x"48", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"30", x"10", x"10", x"10", x"10", x"10", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"54", x"54", x"54", x"54", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"58", x"64", x"44", x"44", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"38", x"44", x"44", x"44", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"78", x"44", x"44", x"44", x"78", x"40", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3c", x"44", x"44", x"44", x"3c", x"04", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"58", x"64", x"40", x"40", x"40", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3c", x"40", x"38", x"04", x"78", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"20", x"70", x"20", x"20", x"24", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"4c", x"34", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"28", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"54", x"54", x"28", x"28", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"28", x"10", x"28", x"44", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"44", x"44", x"44", x"3c", x"04", x"38", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"08", x"10", x"20", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"10", x"10", x"20", x"10", x"10", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"10", x"00", x"10", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"10", x"10", x"08", x"10", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"54", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"08", x"08", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"1c", x"20", x"20", x"20", x"1c", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"0c", x"12", x"10", x"38", x"10", x"10", x"3e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"22", x"1c", x"14", x"1c", x"22", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"22", x"14", x"08", x"3e", x"08", x"3e", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"08", x"08", x"00", x"08", x"08", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1c", x"20", x"1c", x"22", x"1c", x"02", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"14", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"41", x"5d", x"51", x"51", x"5d", x"41", x"3e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1c", x"02", x"1e", x"22", x"1e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"0a", x"14", x"28", x"14", x"0a", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"02", x"02", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"41", x"5d", x"55", x"59", x"55", x"41", x"3e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"7e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"28", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"08", x"3e", x"08", x"08", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"04", x"08", x"10", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"04", x"18", x"04", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"12", x"12", x"12", x"12", x"1c", x"10", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1a", x"2a", x"2a", x"1a", x"0a", x"0a", x"0a", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"18", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"18", x"08", x"08", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"28", x"14", x"0a", x"14", x"28", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"20", x"20", x"22", x"06", x"0e", x"02", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"20", x"20", x"20", x"2e", x"02", x"04", x"0e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"70", x"10", x"70", x"12", x"76", x"0e", x"02", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"10", x"12", x"0c", x"00", x"00", x"00", x"00", x"00", x"00" ); --attribute RAM_STYLE : string; --attribute RAM_STYLE of RAM: signal is "BLOCK"; begin process (clka) begin if rising_edge(clka) then if (wea = '1') then RAM(conv_integer(addra(10 downto 0))) := dina; end if; douta <= RAM(conv_integer(addra(10 downto 0))); end if; end process; process (clkb) begin if rising_edge(clkb) then if (web = '1') then RAM(conv_integer(addrb(10 downto 0))) := dinb; end if; doutb <= RAM(conv_integer(addrb(10 downto 0))); end if; end process; end BEHAVIORAL;
apache-2.0
00e65f0d0c9d6abfe95bac13bee990d0
0.413188
1.901965
false
false
false
false
grwlf/vsim
vhdl_bugs/assign2.vhd
1
44,363
entity ENT00001_Test_Bench is end entity ENT00001_Test_Bench; architecture arch of ENT00001_Test_Bench is signal clk : integer := 0; constant CYCLES : integer := 1000; begin main: process(clk) --{{{ variable a0001 : integer; variable a0002 : integer; variable a0003 : integer; variable a0004 : integer; variable a0005 : integer; variable a0006 : integer; variable a0007 : integer; variable a0008 : integer; variable a0009 : integer; variable a0010 : integer; variable a0011 : integer; variable a0012 : integer; variable a0013 : integer; variable a0014 : integer; variable a0015 : integer; variable a0016 : integer; variable a0017 : integer; variable a0018 : integer; variable a0019 : integer; variable a0020 : integer; variable a0021 : integer; variable a0022 : integer; variable a0023 : integer; variable a0024 : integer; variable a0025 : integer; variable a0026 : integer; variable a0027 : integer; variable a0028 : integer; variable a0029 : integer; variable a0030 : integer; variable a0031 : integer; variable a0032 : integer; variable a0033 : integer; variable a0034 : integer; variable a0035 : integer; variable a0036 : integer; variable a0037 : integer; variable a0038 : integer; variable a0039 : integer; variable a0040 : integer; variable a0041 : integer; variable a0042 : integer; variable a0043 : integer; variable a0044 : integer; variable a0045 : integer; variable a0046 : integer; variable a0047 : integer; variable a0048 : integer; variable a0049 : integer; variable a0050 : integer; variable a0051 : integer; variable a0052 : integer; variable a0053 : integer; variable a0054 : integer; variable a0055 : integer; variable a0056 : integer; variable a0057 : integer; variable a0058 : integer; variable a0059 : integer; variable a0060 : integer; variable a0061 : integer; variable a0062 : integer; variable a0063 : integer; variable a0064 : integer; variable a0065 : integer; variable a0066 : integer; variable a0067 : integer; variable a0068 : integer; variable a0069 : integer; variable a0070 : integer; variable a0071 : integer; variable a0072 : integer; variable a0073 : integer; variable a0074 : integer; variable a0075 : integer; variable a0076 : integer; variable a0077 : integer; variable a0078 : integer; variable a0079 : integer; variable a0080 : integer; variable a0081 : integer; variable a0082 : integer; variable a0083 : integer; variable a0084 : integer; variable a0085 : integer; variable a0086 : integer; variable a0087 : integer; variable a0088 : integer; variable a0089 : integer; variable a0090 : integer; variable a0091 : integer; variable a0092 : integer; variable a0093 : integer; variable a0094 : integer; variable a0095 : integer; variable a0096 : integer; variable a0097 : integer; variable a0098 : integer; variable a0099 : integer; variable a0100 : integer; variable a0101 : integer; variable a0102 : integer; variable a0103 : integer; variable a0104 : integer; variable a0105 : integer; variable a0106 : integer; variable a0107 : integer; variable a0108 : integer; variable a0109 : integer; variable a0110 : integer; variable a0111 : integer; variable a0112 : integer; variable a0113 : integer; variable a0114 : integer; variable a0115 : integer; variable a0116 : integer; variable a0117 : integer; variable a0118 : integer; variable a0119 : integer; variable a0120 : integer; variable a0121 : integer; variable a0122 : integer; variable a0123 : integer; variable a0124 : integer; variable a0125 : integer; variable a0126 : integer; variable a0127 : integer; variable a0128 : integer; variable a0129 : integer; variable a0130 : integer; variable a0131 : integer; variable a0132 : integer; variable a0133 : integer; variable a0134 : integer; variable a0135 : integer; variable a0136 : integer; variable a0137 : integer; variable a0138 : integer; variable a0139 : integer; variable a0140 : integer; variable a0141 : integer; variable a0142 : integer; variable a0143 : integer; variable a0144 : integer; variable a0145 : integer; variable a0146 : integer; variable a0147 : integer; variable a0148 : integer; variable a0149 : integer; variable a0150 : integer; variable a0151 : integer; variable a0152 : integer; variable a0153 : integer; variable a0154 : integer; variable a0155 : integer; variable a0156 : integer; variable a0157 : integer; variable a0158 : integer; variable a0159 : integer; variable a0160 : integer; variable a0161 : integer; variable a0162 : integer; variable a0163 : integer; variable a0164 : integer; variable a0165 : integer; variable a0166 : integer; variable a0167 : integer; variable a0168 : integer; variable a0169 : integer; variable a0170 : integer; variable a0171 : integer; variable a0172 : integer; variable a0173 : integer; variable a0174 : integer; variable a0175 : integer; variable a0176 : integer; variable a0177 : integer; variable a0178 : integer; variable a0179 : integer; variable a0180 : integer; variable a0181 : integer; variable a0182 : integer; variable a0183 : integer; variable a0184 : integer; variable a0185 : integer; variable a0186 : integer; variable a0187 : integer; variable a0188 : integer; variable a0189 : integer; variable a0190 : integer; variable a0191 : integer; variable a0192 : integer; variable a0193 : integer; variable a0194 : integer; variable a0195 : integer; variable a0196 : integer; variable a0197 : integer; variable a0198 : integer; variable a0199 : integer; variable a0200 : integer; variable a0201 : integer; variable a0202 : integer; variable a0203 : integer; variable a0204 : integer; variable a0205 : integer; variable a0206 : integer; variable a0207 : integer; variable a0208 : integer; variable a0209 : integer; variable a0210 : integer; variable a0211 : integer; variable a0212 : integer; variable a0213 : integer; variable a0214 : integer; variable a0215 : integer; variable a0216 : integer; variable a0217 : integer; variable a0218 : integer; variable a0219 : integer; variable a0220 : integer; variable a0221 : integer; variable a0222 : integer; variable a0223 : integer; variable a0224 : integer; variable a0225 : integer; variable a0226 : integer; variable a0227 : integer; variable a0228 : integer; variable a0229 : integer; variable a0230 : integer; variable a0231 : integer; variable a0232 : integer; variable a0233 : integer; variable a0234 : integer; variable a0235 : integer; variable a0236 : integer; variable a0237 : integer; variable a0238 : integer; variable a0239 : integer; variable a0240 : integer; variable a0241 : integer; variable a0242 : integer; variable a0243 : integer; variable a0244 : integer; variable a0245 : integer; variable a0246 : integer; variable a0247 : integer; variable a0248 : integer; variable a0249 : integer; variable a0250 : integer; variable a0251 : integer; variable a0252 : integer; variable a0253 : integer; variable a0254 : integer; variable a0255 : integer; variable a0256 : integer; variable a0257 : integer; variable a0258 : integer; variable a0259 : integer; variable a0260 : integer; variable a0261 : integer; variable a0262 : integer; variable a0263 : integer; variable a0264 : integer; variable a0265 : integer; variable a0266 : integer; variable a0267 : integer; variable a0268 : integer; variable a0269 : integer; variable a0270 : integer; variable a0271 : integer; variable a0272 : integer; variable a0273 : integer; variable a0274 : integer; variable a0275 : integer; variable a0276 : integer; variable a0277 : integer; variable a0278 : integer; variable a0279 : integer; variable a0280 : integer; variable a0281 : integer; variable a0282 : integer; variable a0283 : integer; variable a0284 : integer; variable a0285 : integer; variable a0286 : integer; variable a0287 : integer; variable a0288 : integer; variable a0289 : integer; variable a0290 : integer; variable a0291 : integer; variable a0292 : integer; variable a0293 : integer; variable a0294 : integer; variable a0295 : integer; variable a0296 : integer; variable a0297 : integer; variable a0298 : integer; variable a0299 : integer; variable a0300 : integer; variable a0301 : integer; variable a0302 : integer; variable a0303 : integer; variable a0304 : integer; variable a0305 : integer; variable a0306 : integer; variable a0307 : integer; variable a0308 : integer; variable a0309 : integer; variable a0310 : integer; variable a0311 : integer; variable a0312 : integer; variable a0313 : integer; variable a0314 : integer; variable a0315 : integer; variable a0316 : integer; variable a0317 : integer; variable a0318 : integer; variable a0319 : integer; variable a0320 : integer; variable a0321 : integer; variable a0322 : integer; variable a0323 : integer; variable a0324 : integer; variable a0325 : integer; variable a0326 : integer; variable a0327 : integer; variable a0328 : integer; variable a0329 : integer; variable a0330 : integer; variable a0331 : integer; variable a0332 : integer; variable a0333 : integer; variable a0334 : integer; variable a0335 : integer; variable a0336 : integer; variable a0337 : integer; variable a0338 : integer; variable a0339 : integer; variable a0340 : integer; variable a0341 : integer; variable a0342 : integer; variable a0343 : integer; variable a0344 : integer; variable a0345 : integer; variable a0346 : integer; variable a0347 : integer; variable a0348 : integer; variable a0349 : integer; variable a0350 : integer; variable a0351 : integer; variable a0352 : integer; variable a0353 : integer; variable a0354 : integer; variable a0355 : integer; variable a0356 : integer; variable a0357 : integer; variable a0358 : integer; variable a0359 : integer; variable a0360 : integer; variable a0361 : integer; variable a0362 : integer; variable a0363 : integer; variable a0364 : integer; variable a0365 : integer; variable a0366 : integer; variable a0367 : integer; variable a0368 : integer; variable a0369 : integer; variable a0370 : integer; variable a0371 : integer; variable a0372 : integer; variable a0373 : integer; variable a0374 : integer; variable a0375 : integer; variable a0376 : integer; variable a0377 : integer; variable a0378 : integer; variable a0379 : integer; variable a0380 : integer; variable a0381 : integer; variable a0382 : integer; variable a0383 : integer; variable a0384 : integer; variable a0385 : integer; variable a0386 : integer; variable a0387 : integer; variable a0388 : integer; variable a0389 : integer; variable a0390 : integer; variable a0391 : integer; variable a0392 : integer; variable a0393 : integer; variable a0394 : integer; variable a0395 : integer; variable a0396 : integer; variable a0397 : integer; variable a0398 : integer; variable a0399 : integer; variable a0400 : integer; variable a0401 : integer; variable a0402 : integer; variable a0403 : integer; variable a0404 : integer; variable a0405 : integer; variable a0406 : integer; variable a0407 : integer; variable a0408 : integer; variable a0409 : integer; variable a0410 : integer; variable a0411 : integer; variable a0412 : integer; variable a0413 : integer; variable a0414 : integer; variable a0415 : integer; variable a0416 : integer; variable a0417 : integer; variable a0418 : integer; variable a0419 : integer; variable a0420 : integer; variable a0421 : integer; variable a0422 : integer; variable a0423 : integer; variable a0424 : integer; variable a0425 : integer; variable a0426 : integer; variable a0427 : integer; variable a0428 : integer; variable a0429 : integer; variable a0430 : integer; variable a0431 : integer; variable a0432 : integer; variable a0433 : integer; variable a0434 : integer; variable a0435 : integer; variable a0436 : integer; variable a0437 : integer; variable a0438 : integer; variable a0439 : integer; variable a0440 : integer; variable a0441 : integer; variable a0442 : integer; variable a0443 : integer; variable a0444 : integer; variable a0445 : integer; variable a0446 : integer; variable a0447 : integer; variable a0448 : integer; variable a0449 : integer; variable a0450 : integer; variable a0451 : integer; variable a0452 : integer; variable a0453 : integer; variable a0454 : integer; variable a0455 : integer; variable a0456 : integer; variable a0457 : integer; variable a0458 : integer; variable a0459 : integer; variable a0460 : integer; variable a0461 : integer; variable a0462 : integer; variable a0463 : integer; variable a0464 : integer; variable a0465 : integer; variable a0466 : integer; variable a0467 : integer; variable a0468 : integer; variable a0469 : integer; variable a0470 : integer; variable a0471 : integer; variable a0472 : integer; variable a0473 : integer; variable a0474 : integer; variable a0475 : integer; variable a0476 : integer; variable a0477 : integer; variable a0478 : integer; variable a0479 : integer; variable a0480 : integer; variable a0481 : integer; variable a0482 : integer; variable a0483 : integer; variable a0484 : integer; variable a0485 : integer; variable a0486 : integer; variable a0487 : integer; variable a0488 : integer; variable a0489 : integer; variable a0490 : integer; variable a0491 : integer; variable a0492 : integer; variable a0493 : integer; variable a0494 : integer; variable a0495 : integer; variable a0496 : integer; variable a0497 : integer; variable a0498 : integer; variable a0499 : integer; variable a0500 : integer; variable a0501 : integer; variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0001 := 1; a0002 := 2; a0003 := 3; a0004 := 4; a0005 := 5; a0006 := 6; a0007 := 7; a0008 := 8; a0009 := 9; a0010 := 10; a0011 := 11; a0012 := 12; a0013 := 13; a0014 := 14; a0015 := 15; a0016 := 16; a0017 := 17; a0018 := 18; a0019 := 19; a0020 := 20; a0021 := 21; a0022 := 22; a0023 := 23; a0024 := 24; a0025 := 25; a0026 := 26; a0027 := 27; a0028 := 28; a0029 := 29; a0030 := 30; a0031 := 31; a0032 := 32; a0033 := 33; a0034 := 34; a0035 := 35; a0036 := 36; a0037 := 37; a0038 := 38; a0039 := 39; a0040 := 40; a0041 := 41; a0042 := 42; a0043 := 43; a0044 := 44; a0045 := 45; a0046 := 46; a0047 := 47; a0048 := 48; a0049 := 49; a0050 := 50; a0051 := 51; a0052 := 52; a0053 := 53; a0054 := 54; a0055 := 55; a0056 := 56; a0057 := 57; a0058 := 58; a0059 := 59; a0060 := 60; a0061 := 61; a0062 := 62; a0063 := 63; a0064 := 64; a0065 := 65; a0066 := 66; a0067 := 67; a0068 := 68; a0069 := 69; a0070 := 70; a0071 := 71; a0072 := 72; a0073 := 73; a0074 := 74; a0075 := 75; a0076 := 76; a0077 := 77; a0078 := 78; a0079 := 79; a0080 := 80; a0081 := 81; a0082 := 82; a0083 := 83; a0084 := 84; a0085 := 85; a0086 := 86; a0087 := 87; a0088 := 88; a0089 := 89; a0090 := 90; a0091 := 91; a0092 := 92; a0093 := 93; a0094 := 94; a0095 := 95; a0096 := 96; a0097 := 97; a0098 := 98; a0099 := 99; a0100 := 100; a0101 := 101; a0102 := 102; a0103 := 103; a0104 := 104; a0105 := 105; a0106 := 106; a0107 := 107; a0108 := 108; a0109 := 109; a0110 := 110; a0111 := 111; a0112 := 112; a0113 := 113; a0114 := 114; a0115 := 115; a0116 := 116; a0117 := 117; a0118 := 118; a0119 := 119; a0120 := 120; a0121 := 121; a0122 := 122; a0123 := 123; a0124 := 124; a0125 := 125; a0126 := 126; a0127 := 127; a0128 := 128; a0129 := 129; a0130 := 130; a0131 := 131; a0132 := 132; a0133 := 133; a0134 := 134; a0135 := 135; a0136 := 136; a0137 := 137; a0138 := 138; a0139 := 139; a0140 := 140; a0141 := 141; a0142 := 142; a0143 := 143; a0144 := 144; a0145 := 145; a0146 := 146; a0147 := 147; a0148 := 148; a0149 := 149; a0150 := 150; a0151 := 151; a0152 := 152; a0153 := 153; a0154 := 154; a0155 := 155; a0156 := 156; a0157 := 157; a0158 := 158; a0159 := 159; a0160 := 160; a0161 := 161; a0162 := 162; a0163 := 163; a0164 := 164; a0165 := 165; a0166 := 166; a0167 := 167; a0168 := 168; a0169 := 169; a0170 := 170; a0171 := 171; a0172 := 172; a0173 := 173; a0174 := 174; a0175 := 175; a0176 := 176; a0177 := 177; a0178 := 178; a0179 := 179; a0180 := 180; a0181 := 181; a0182 := 182; a0183 := 183; a0184 := 184; a0185 := 185; a0186 := 186; a0187 := 187; a0188 := 188; a0189 := 189; a0190 := 190; a0191 := 191; a0192 := 192; a0193 := 193; a0194 := 194; a0195 := 195; a0196 := 196; a0197 := 197; a0198 := 198; a0199 := 199; a0200 := 200; a0201 := 201; a0202 := 202; a0203 := 203; a0204 := 204; a0205 := 205; a0206 := 206; a0207 := 207; a0208 := 208; a0209 := 209; a0210 := 210; a0211 := 211; a0212 := 212; a0213 := 213; a0214 := 214; a0215 := 215; a0216 := 216; a0217 := 217; a0218 := 218; a0219 := 219; a0220 := 220; a0221 := 221; a0222 := 222; a0223 := 223; a0224 := 224; a0225 := 225; a0226 := 226; a0227 := 227; a0228 := 228; a0229 := 229; a0230 := 230; a0231 := 231; a0232 := 232; a0233 := 233; a0234 := 234; a0235 := 235; a0236 := 236; a0237 := 237; a0238 := 238; a0239 := 239; a0240 := 240; a0241 := 241; a0242 := 242; a0243 := 243; a0244 := 244; a0245 := 245; a0246 := 246; a0247 := 247; a0248 := 248; a0249 := 249; a0250 := 250; a0251 := 251; a0252 := 252; a0253 := 253; a0254 := 254; a0255 := 255; a0256 := 256; a0257 := 257; a0258 := 258; a0259 := 259; a0260 := 260; a0261 := 261; a0262 := 262; a0263 := 263; a0264 := 264; a0265 := 265; a0266 := 266; a0267 := 267; a0268 := 268; a0269 := 269; a0270 := 270; a0271 := 271; a0272 := 272; a0273 := 273; a0274 := 274; a0275 := 275; a0276 := 276; a0277 := 277; a0278 := 278; a0279 := 279; a0280 := 280; a0281 := 281; a0282 := 282; a0283 := 283; a0284 := 284; a0285 := 285; a0286 := 286; a0287 := 287; a0288 := 288; a0289 := 289; a0290 := 290; a0291 := 291; a0292 := 292; a0293 := 293; a0294 := 294; a0295 := 295; a0296 := 296; a0297 := 297; a0298 := 298; a0299 := 299; a0300 := 300; a0301 := 301; a0302 := 302; a0303 := 303; a0304 := 304; a0305 := 305; a0306 := 306; a0307 := 307; a0308 := 308; a0309 := 309; a0310 := 310; a0311 := 311; a0312 := 312; a0313 := 313; a0314 := 314; a0315 := 315; a0316 := 316; a0317 := 317; a0318 := 318; a0319 := 319; a0320 := 320; a0321 := 321; a0322 := 322; a0323 := 323; a0324 := 324; a0325 := 325; a0326 := 326; a0327 := 327; a0328 := 328; a0329 := 329; a0330 := 330; a0331 := 331; a0332 := 332; a0333 := 333; a0334 := 334; a0335 := 335; a0336 := 336; a0337 := 337; a0338 := 338; a0339 := 339; a0340 := 340; a0341 := 341; a0342 := 342; a0343 := 343; a0344 := 344; a0345 := 345; a0346 := 346; a0347 := 347; a0348 := 348; a0349 := 349; a0350 := 350; a0351 := 351; a0352 := 352; a0353 := 353; a0354 := 354; a0355 := 355; a0356 := 356; a0357 := 357; a0358 := 358; a0359 := 359; a0360 := 360; a0361 := 361; a0362 := 362; a0363 := 363; a0364 := 364; a0365 := 365; a0366 := 366; a0367 := 367; a0368 := 368; a0369 := 369; a0370 := 370; a0371 := 371; a0372 := 372; a0373 := 373; a0374 := 374; a0375 := 375; a0376 := 376; a0377 := 377; a0378 := 378; a0379 := 379; a0380 := 380; a0381 := 381; a0382 := 382; a0383 := 383; a0384 := 384; a0385 := 385; a0386 := 386; a0387 := 387; a0388 := 388; a0389 := 389; a0390 := 390; a0391 := 391; a0392 := 392; a0393 := 393; a0394 := 394; a0395 := 395; a0396 := 396; a0397 := 397; a0398 := 398; a0399 := 399; a0400 := 400; a0401 := 401; a0402 := 402; a0403 := 403; a0404 := 404; a0405 := 405; a0406 := 406; a0407 := 407; a0408 := 408; a0409 := 409; a0410 := 410; a0411 := 411; a0412 := 412; a0413 := 413; a0414 := 414; a0415 := 415; a0416 := 416; a0417 := 417; a0418 := 418; a0419 := 419; a0420 := 420; a0421 := 421; a0422 := 422; a0423 := 423; a0424 := 424; a0425 := 425; a0426 := 426; a0427 := 427; a0428 := 428; a0429 := 429; a0430 := 430; a0431 := 431; a0432 := 432; a0433 := 433; a0434 := 434; a0435 := 435; a0436 := 436; a0437 := 437; a0438 := 438; a0439 := 439; a0440 := 440; a0441 := 441; a0442 := 442; a0443 := 443; a0444 := 444; a0445 := 445; a0446 := 446; a0447 := 447; a0448 := 448; a0449 := 449; a0450 := 450; a0451 := 451; a0452 := 452; a0453 := 453; a0454 := 454; a0455 := 455; a0456 := 456; a0457 := 457; a0458 := 458; a0459 := 459; a0460 := 460; a0461 := 461; a0462 := 462; a0463 := 463; a0464 := 464; a0465 := 465; a0466 := 466; a0467 := 467; a0468 := 468; a0469 := 469; a0470 := 470; a0471 := 471; a0472 := 472; a0473 := 473; a0474 := 474; a0475 := 475; a0476 := 476; a0477 := 477; a0478 := 478; a0479 := 479; a0480 := 480; a0481 := 481; a0482 := 482; a0483 := 483; a0484 := 484; a0485 := 485; a0486 := 486; a0487 := 487; a0488 := 488; a0489 := 489; a0490 := 490; a0491 := 491; a0492 := 492; a0493 := 493; a0494 := 494; a0495 := 495; a0496 := 496; a0497 := 497; a0498 := 498; a0499 := 499; a0500 := 500; a0501 := 501; a0502 := 502; a0503 := 503; a0504 := 504; a0505 := 505; a0506 := 506; a0507 := 507; a0508 := 508; a0509 := 509; a0510 := 510; a0511 := 511; a0512 := 512; a0513 := 513; a0514 := 514; a0515 := 515; a0516 := 516; a0517 := 517; a0518 := 518; a0519 := 519; a0520 := 520; a0521 := 521; a0522 := 522; a0523 := 523; a0524 := 524; a0525 := 525; a0526 := 526; a0527 := 527; a0528 := 528; a0529 := 529; a0530 := 530; a0531 := 531; a0532 := 532; a0533 := 533; a0534 := 534; a0535 := 535; a0536 := 536; a0537 := 537; a0538 := 538; a0539 := 539; a0540 := 540; a0541 := 541; a0542 := 542; a0543 := 543; a0544 := 544; a0545 := 545; a0546 := 546; a0547 := 547; a0548 := 548; a0549 := 549; a0550 := 550; a0551 := 551; a0552 := 552; a0553 := 553; a0554 := 554; a0555 := 555; a0556 := 556; a0557 := 557; a0558 := 558; a0559 := 559; a0560 := 560; a0561 := 561; a0562 := 562; a0563 := 563; a0564 := 564; a0565 := 565; a0566 := 566; a0567 := 567; a0568 := 568; a0569 := 569; a0570 := 570; a0571 := 571; a0572 := 572; a0573 := 573; a0574 := 574; a0575 := 575; a0576 := 576; a0577 := 577; a0578 := 578; a0579 := 579; a0580 := 580; a0581 := 581; a0582 := 582; a0583 := 583; a0584 := 584; a0585 := 585; a0586 := 586; a0587 := 587; a0588 := 588; a0589 := 589; a0590 := 590; a0591 := 591; a0592 := 592; a0593 := 593; a0594 := 594; a0595 := 595; a0596 := 596; a0597 := 597; a0598 := 598; a0599 := 599; a0600 := 600; a0601 := 601; a0602 := 602; a0603 := 603; a0604 := 604; a0605 := 605; a0606 := 606; a0607 := 607; a0608 := 608; a0609 := 609; a0610 := 610; a0611 := 611; a0612 := 612; a0613 := 613; a0614 := 614; a0615 := 615; a0616 := 616; a0617 := 617; a0618 := 618; a0619 := 619; a0620 := 620; a0621 := 621; a0622 := 622; a0623 := 623; a0624 := 624; a0625 := 625; a0626 := 626; a0627 := 627; a0628 := 628; a0629 := 629; a0630 := 630; a0631 := 631; a0632 := 632; a0633 := 633; a0634 := 634; a0635 := 635; a0636 := 636; a0637 := 637; a0638 := 638; a0639 := 639; a0640 := 640; a0641 := 641; a0642 := 642; a0643 := 643; a0644 := 644; a0645 := 645; a0646 := 646; a0647 := 647; a0648 := 648; a0649 := 649; a0650 := 650; a0651 := 651; a0652 := 652; a0653 := 653; a0654 := 654; a0655 := 655; a0656 := 656; a0657 := 657; a0658 := 658; a0659 := 659; a0660 := 660; a0661 := 661; a0662 := 662; a0663 := 663; a0664 := 664; a0665 := 665; a0666 := 666; a0667 := 667; a0668 := 668; a0669 := 669; a0670 := 670; a0671 := 671; a0672 := 672; a0673 := 673; a0674 := 674; a0675 := 675; a0676 := 676; a0677 := 677; a0678 := 678; a0679 := 679; a0680 := 680; a0681 := 681; a0682 := 682; a0683 := 683; a0684 := 684; a0685 := 685; a0686 := 686; a0687 := 687; a0688 := 688; a0689 := 689; a0690 := 690; a0691 := 691; a0692 := 692; a0693 := 693; a0694 := 694; a0695 := 695; a0696 := 696; a0697 := 697; a0698 := 698; a0699 := 699; a0700 := 700; a0701 := 701; a0702 := 702; a0703 := 703; a0704 := 704; a0705 := 705; a0706 := 706; a0707 := 707; a0708 := 708; a0709 := 709; a0710 := 710; a0711 := 711; a0712 := 712; a0713 := 713; a0714 := 714; a0715 := 715; a0716 := 716; a0717 := 717; a0718 := 718; a0719 := 719; a0720 := 720; a0721 := 721; a0722 := 722; a0723 := 723; a0724 := 724; a0725 := 725; a0726 := 726; a0727 := 727; a0728 := 728; a0729 := 729; a0730 := 730; a0731 := 731; a0732 := 732; a0733 := 733; a0734 := 734; a0735 := 735; a0736 := 736; a0737 := 737; a0738 := 738; a0739 := 739; a0740 := 740; a0741 := 741; a0742 := 742; a0743 := 743; a0744 := 744; a0745 := 745; a0746 := 746; a0747 := 747; a0748 := 748; a0749 := 749; a0750 := 750; a0751 := 751; a0752 := 752; a0753 := 753; a0754 := 754; a0755 := 755; a0756 := 756; a0757 := 757; a0758 := 758; a0759 := 759; a0760 := 760; a0761 := 761; a0762 := 762; a0763 := 763; a0764 := 764; a0765 := 765; a0766 := 766; a0767 := 767; a0768 := 768; a0769 := 769; a0770 := 770; a0771 := 771; a0772 := 772; a0773 := 773; a0774 := 774; a0775 := 775; a0776 := 776; a0777 := 777; a0778 := 778; a0779 := 779; a0780 := 780; a0781 := 781; a0782 := 782; a0783 := 783; a0784 := 784; a0785 := 785; a0786 := 786; a0787 := 787; a0788 := 788; a0789 := 789; a0790 := 790; a0791 := 791; a0792 := 792; a0793 := 793; a0794 := 794; a0795 := 795; a0796 := 796; a0797 := 797; a0798 := 798; a0799 := 799; a0800 := 800; a0801 := 801; a0802 := 802; a0803 := 803; a0804 := 804; a0805 := 805; a0806 := 806; a0807 := 807; a0808 := 808; a0809 := 809; a0810 := 810; a0811 := 811; a0812 := 812; a0813 := 813; a0814 := 814; a0815 := 815; a0816 := 816; a0817 := 817; a0818 := 818; a0819 := 819; a0820 := 820; a0821 := 821; a0822 := 822; a0823 := 823; a0824 := 824; a0825 := 825; a0826 := 826; a0827 := 827; a0828 := 828; a0829 := 829; a0830 := 830; a0831 := 831; a0832 := 832; a0833 := 833; a0834 := 834; a0835 := 835; a0836 := 836; a0837 := 837; a0838 := 838; a0839 := 839; a0840 := 840; a0841 := 841; a0842 := 842; a0843 := 843; a0844 := 844; a0845 := 845; a0846 := 846; a0847 := 847; a0848 := 848; a0849 := 849; a0850 := 850; a0851 := 851; a0852 := 852; a0853 := 853; a0854 := 854; a0855 := 855; a0856 := 856; a0857 := 857; a0858 := 858; a0859 := 859; a0860 := 860; a0861 := 861; a0862 := 862; a0863 := 863; a0864 := 864; a0865 := 865; a0866 := 866; a0867 := 867; a0868 := 868; a0869 := 869; a0870 := 870; a0871 := 871; a0872 := 872; a0873 := 873; a0874 := 874; a0875 := 875; a0876 := 876; a0877 := 877; a0878 := 878; a0879 := 879; a0880 := 880; a0881 := 881; a0882 := 882; a0883 := 883; a0884 := 884; a0885 := 885; a0886 := 886; a0887 := 887; a0888 := 888; a0889 := 889; a0890 := 890; a0891 := 891; a0892 := 892; a0893 := 893; a0894 := 894; a0895 := 895; a0896 := 896; a0897 := 897; a0898 := 898; a0899 := 899; a0900 := 900; a0901 := 901; a0902 := 902; a0903 := 903; a0904 := 904; a0905 := 905; a0906 := 906; a0907 := 907; a0908 := 908; a0909 := 909; a0910 := 910; a0911 := 911; a0912 := 912; a0913 := 913; a0914 := 914; a0915 := 915; a0916 := 916; a0917 := 917; a0918 := 918; a0919 := 919; a0920 := 920; a0921 := 921; a0922 := 922; a0923 := 923; a0924 := 924; a0925 := 925; a0926 := 926; a0927 := 927; a0928 := 928; a0929 := 929; a0930 := 930; a0931 := 931; a0932 := 932; a0933 := 933; a0934 := 934; a0935 := 935; a0936 := 936; a0937 := 937; a0938 := 938; a0939 := 939; a0940 := 940; a0941 := 941; a0942 := 942; a0943 := 943; a0944 := 944; a0945 := 945; a0946 := 946; a0947 := 947; a0948 := 948; a0949 := 949; a0950 := 950; a0951 := 951; a0952 := 952; a0953 := 953; a0954 := 954; a0955 := 955; a0956 := 956; a0957 := 957; a0958 := 958; a0959 := 959; a0960 := 960; a0961 := 961; a0962 := 962; a0963 := 963; a0964 := 964; a0965 := 965; a0966 := 966; a0967 := 967; a0968 := 968; a0969 := 969; a0970 := 970; a0971 := 971; a0972 := 972; a0973 := 973; a0974 := 974; a0975 := 975; a0976 := 976; a0977 := 977; a0978 := 978; a0979 := 979; a0980 := 980; a0981 := 981; a0982 := 982; a0983 := 983; a0984 := 984; a0985 := 985; a0986 := 986; a0987 := 987; a0988 := 988; a0989 := 989; a0990 := 990; a0991 := 991; a0992 := 992; a0993 := 993; a0994 := 994; a0995 := 995; a0996 := 996; a0997 := 997; a0998 := 998; a0999 := 999; a1000 := 1000; -- report "tick"; --}}} end process; terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; clk <= (clk+1) after 1 us; end;
gpl-3.0
9a60428ae88c54541c7a36af54c00cdd
0.635687
2.787671
false
false
false
false
grwlf/vsim
vhdl_ct/ct00124.vhd
1
33,147
-- NEED RESULT: ARCH00124.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00124: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00124 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00124 -- PKG00124/BODY -- ENT00124(ARCH00124) -- ENT00124_Test_Bench(ARCH00124_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00124 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00124 ; -- package body PKG00124 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00124 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00124.all ; entity ENT00124 is port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- -- procedure Proc1 ( signal s_r_st_arr1_vector : inout r_st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_r_st_arr2_vector : inout r_st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_r_st_arr3_vector : inout r_st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_r_st_rec1_vector : inout r_st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_r_st_rec2_vector : inout r_st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_r_st_rec3_vector : inout r_st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00124.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00124" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00124" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- -- end ENT00124 ; -- architecture ARCH00124 of ENT00124 is begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_r_st_arr1_vector, counter, correct, savtime, chk_r_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_r_st_arr2_vector, counter, correct, savtime, chk_r_st_arr2_vector ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_r_st_arr3_vector, counter, correct, savtime, chk_r_st_arr3_vector ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_r_st_rec1_vector, counter, correct, savtime, chk_r_st_rec1_vector ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_r_st_rec2_vector, counter, correct, savtime, chk_r_st_rec2_vector ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_r_st_rec3_vector, counter, correct, savtime, chk_r_st_rec3_vector ) ; end process P6 ; -- -- end ARCH00124 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00124.all ; entity ENT00124_Test_Bench is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- end ENT00124_Test_Bench ; -- architecture ARCH00124_Test_Bench of ENT00124_Test_Bench is begin L1: block component UUT port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00124 ( ARCH00124 ) ; begin CIS1 : UUT port map ( s_r_st_arr1_vector , s_r_st_arr2_vector , s_r_st_arr3_vector , s_r_st_rec1_vector , s_r_st_rec2_vector , s_r_st_rec3_vector ) ; end block L1 ; end ARCH00124_Test_Bench ;
gpl-3.0
2389f5d3bfd2f498ea2d7c3b86a20f4c
0.529218
3.328012
false
false
false
false
grwlf/vsim
vhdl_ct/pro000008.vhd
1
1,761
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, component, resolved, when-else. use work.std_logic_1164_for_tst.all; entity ENT00005 is port( latch : in boolean; io : inout std_logic ); end entity; architecture ARCH00005 of ENT00005 is signal power : boolean := false; signal en_out_z : boolean := false; begin power <= not power after 4 us; en_out_z <= not en_out_z after 10 us; io <= 'Z' when en_out_z else '1' when latch and power else 'H' when latch and not(power) else 'L' when not(latch) and not(power) else '0'; end ARCH00005; use work.std_logic_1164_for_tst.all; entity ENT00005_Test_Bench is end entity; architecture ARCH00005_Test_Bench of ENT00005_Test_Bench is component ENT00005 is port( latch : in boolean; io : inout std_logic ); end component; signal latch : boolean := false; signal io1, io2 : std_logic; signal input_z : std_logic; signal en_z : boolean := false; signal en_in_z : boolean := false; begin en_z <= not en_z after 3 us; en_in_z <= not en_in_z after 5 us; input_z <= 'Z' when en_z else 'H'; io1 <= 'H' when (not latch) else input_z when en_in_z else '0'; io2 <= 'H' when (not latch) else input_z when en_in_z else '0'; latch <= not latch after 1 us; UUT1: ENT00005 port map ( latch => latch , io => io1 ); end ARCH00005_Test_Bench;
gpl-3.0
a46c19c0b19836480717ebf1fe2de22d
0.594549
3.237132
false
true
false
false
wsoltys/AtomFpga
mist/clk_div.vhd
1
580
library ieee; use ieee.std_logic_1164.all; entity clk_div is generic ( DIVISOR : natural ); port ( clk : in std_logic; reset : in std_logic; clk_en : out std_logic ); end clk_div; architecture SYN of clk_div is begin process (clk, reset) variable count : integer range 0 to DIVISOR-1; begin if reset = '1' then count := 0; clk_en <= '0'; elsif rising_edge(clk) then clk_en <= '0'; if count = DIVISOR-1 then clk_en <= '1'; count := 0; else count := count + 1; end if; end if; end process; end SYN;
apache-2.0
a775571e91bba8b097623ccbcc254718
0.577586
2.723005
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/Interface.vhd
1
9,183
--***************************************************************************** -- @Copyright All rights reserved. -- Module name : Interface -- Call by : -- Description : -- IC : EP2S60F672I4 -- Version : 1.0 -- Note: : -- Author : Weibao Qiu -- Date : 2009.05.24 -- Update : -- --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Interface is port ( I_reset_n : in std_logic; I_sys_clk : in std_logic; --work control O_register : out std_logic_vector(31 downto 0); --image data output I_data_en : in std_logic; I_data_symbol : in std_logic; I_data : in std_logic_vector(15 downto 0); ---usb FIFO O_wfifo_reset : out std_logic; O_usb_wrreq : out std_logic; O_usb_din : out std_logic_vector(15 downto 0); O_usb_rdreq : out std_logic; I_usb_dout : in std_logic_vector(31 downto 0); I_usb_rdempty : in std_logic ); end Interface; architecture rtl of Interface is ----------------------------- constant c_speed_test : integer := 180000;--40000; signal s_work_start : std_logic := '0'; signal s_work_mode : std_logic_vector (1 downto 0); --signal s_scan_trig : std_logic; signal S_usb_wrreq : std_logic; signal S_usb_din : std_logic_vector(15 downto 0); signal S_usb_rdreq : std_logic; signal S_usb_dout : std_logic_vector(31 downto 0); signal S_usb_rdempty : std_logic; ------------usb read state-------------- signal S_usb_pulse_state : std_logic_vector(1 downto 0); -------constant for reset and logic judgement------------------ constant C_RST_ON : std_logic := '0'; --reset signal the system is low reset constant C_ACT_ON : std_logic := '1'; --logic judgement signal constant C_ACT_OFF : std_logic := '0'; signal S_case_test : std_logic_vector(1 downto 0); signal S_case_work : std_logic_vector(1 downto 0); signal S_register : std_logic_vector(31 downto 0):="00000000000000000000000000000000"; signal s_test_cn : std_logic_vector(19 downto 0); signal s_work_cn : std_logic_vector(19 downto 0); signal s_line_no : std_logic_vector(15 downto 0); signal s_line_comb : std_logic_vector(15 downto 0); begin O_usb_wrreq <= S_usb_wrreq; O_usb_din <= S_usb_din; O_usb_rdreq <= S_usb_rdreq; S_usb_dout <= I_usb_dout; S_usb_rdempty <= I_usb_rdempty; --------- s_work_start <= '1';--S_register(0); s_work_mode <= "00";--S_register(3 downto 2); O_register <= S_register ; O_wfifo_reset <= '0';--not S_register(0); --s_scan_trig <= I_data_symbol; --------------------------------------------------------------------- -- To navigate the dsc data between the test and work --------------------------------------------------------------------- process(I_reset_n, I_sys_clk) begin if(I_reset_n = '0')then S_usb_wrreq <= '0'; S_usb_din <= (others => '0'); s_test_cn <= (others => '0'); s_work_cn <= (others => '0'); S_case_test <= (others => '0'); S_case_work <= (others => '0'); s_line_no <= (others => '0'); s_line_comb <= (others => '0'); elsif rising_edge(I_sys_clk) then case s_work_mode is when "10" => --Test USB 这种模式不用,可忽略。 case S_case_test is when "00" => if (s_work_start = '1') then S_case_test <= "01"; else S_case_test <= "00"; s_test_cn <= (others => '0'); s_line_no <= (others => '0'); s_line_comb <= (others => '0'); end if; when "01" => s_test_cn <= s_test_cn + 1; if s_test_cn < 1024 then-- fpga 512 * 32 -> cpu 1024 *16 S_usb_wrreq <= '1';--wr fifo else S_usb_wrreq <= '0'; S_case_test <= "10"; end if; if S_usb_wrreq = '1' then S_usb_din <= S_usb_din + x"0001";--s_line_comb + x"0001"; else S_usb_din <= (others => '0'); end if; when "10" => if (s_work_start = '0') then S_case_test <= "00"; elsif(s_test_cn > c_speed_test)then S_case_test <= "00"; s_test_cn <= (others => '0'); if(s_line_no < 499)then s_line_no <= s_line_no + '1'; else s_line_no <= (others => '0'); end if; s_line_comb <= "000" & s_line_no(15 downto 3); else s_test_cn <= s_test_cn + '1'; end if; when others => S_case_test <= "00"; s_test_cn <= (others => '0'); s_line_no <= (others => '0'); s_line_comb <= (others => '0'); end case; when "00" =>--"01" => --Work 只用这一种模式 S_usb_din <= I_data; if (s_work_start = '1' and I_data_en = '1') then S_usb_wrreq <= I_data_symbol; else S_usb_wrreq <= '0'; end if; when OTHERS => S_usb_wrreq <= '0'; S_usb_din <= (others => '0'); s_test_cn <= (others => '0'); s_work_cn <= (others => '0'); S_case_test <= (others => '0'); S_case_work <= (others => '0'); end case; end if; end process; ------------read data from usb 3.0 to FPGA----------work well process(I_sys_clk,I_reset_n) begin if I_reset_n = '0' then -- 此进程用于校验上位机通过USB主通道下发的数据的头。 S_usb_rdreq <= C_ACT_OFF; S_usb_pulse_state <= (others=> '0'); S_register <= (others=> '0'); elsif rising_edge(I_sys_clk) then if S_usb_rdempty = C_ACT_OFF then --data not empty usb has write data into fifo S_usb_rdreq <= C_ACT_ON; else S_usb_rdreq <= C_ACT_OFF; end if; case S_usb_pulse_state is --execute and pause correct when "00" => if S_usb_dout = x"5b5a0000" then S_usb_pulse_state <= S_usb_pulse_state + 1; else S_usb_pulse_state <= "00"; end if; when "01" => if S_usb_dout = x"7f7e0000" then S_usb_pulse_state <= S_usb_pulse_state + 1; else S_usb_pulse_state <= "01"; end if; when "10" => if S_usb_dout /= x"7f7e0000" then S_usb_pulse_state <= "00" ; S_register <= S_usb_dout; end if; when others=> S_usb_pulse_state <= "00" ; end case; end if; end process; end rtl;
apache-2.0
28ecf2a1dcbf28e3ab45d694b24381d5
0.348973
3.958678
false
true
false
false
progranism/Open-Source-FPGA-Bitcoin-Miner
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_logic_pkt_fifo.vhd
9
31,657
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ceM0ajQGyV4xEt0HrG/fuB+3NVFdwQkEyjC4haRoZWslKKs4yl4ILq7RT/jKXnsVkAWmSwMkAIVY ybpeP1wARw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block kukT7WQifxjY3WsecmUkERV4ZFv3OuhEihgSM4IB88HBbnFE5FquXt3wzdA0zFDlpG683lT2dqcQ e8+DpghsVaFxyA0HhLpe+Uj3VPXCqAamsXiyfOV9FRW5tZT6n2RrABDrg190ZlCTDqzvDTosUPWF LMSAKBUUZLDH1kIj7P0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dU1lj3wLYN2oBu3b76t4HEt238DNk5+Obmy1zgJeHU7rLBtTHV8UnHhRI8PwXXRPMJgrJSDjBzNQ +ZLOT+PNgKe7NXaY01MJhUg5IzH9X6ZAbG3w3IL1/7gL7K6upxJUT61Am45EblqoUFtRFVJDxUNh Bd8MVvlvXZZ66YB0ezm0hTdwdHAYwZ92l9kdTDjIOUN+Jrn85yeycl9Cxu8aIJaiJpiPjNggt0r7 W0kCE0hFF+swK8rZcxOqOLnQ5Uw2Ji8S+E4OYHjUu5yMJL7V5wNFfUHmF9Sc5jyP/mtan4mmu5J4 a/+rlOaidyY5SAZA+m4p3+hj+JN1qzj8TeLhtg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block awqcS4G1ayV64bhRxb2ad9Xg57ysH9KZCzgHZHu8Tmnl74kk+tHqUQBvhiolD+v8jr8AGMVo4blw g75xmAibXafuL9Iv+WrFhYMVK6o+zPGZZLMkNtFS8zqdWka/9Q7TQ7QQbuzZUEZbJM/3vYY1iWRq Y/oB/ixzA+Df5gDA5bY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block JeYOat6TeNOn0Lwfj9kOs9eB1tXhm0apFaxmaQldY51fS0eKT90XxV+wEmwhre/Q9kRs/refblVV DzXaATdPK7kvWKItPjzGkuwjoIEdIAYiZEyE5+ZwIqPH2W6BCpzMHIAHRXYo6tSScrR2uqBcPQGy c8HaUqIW6z94Rr+QjtUESf9429NBJLRTbe5wnn4DHy20T/ChW4iPiERY98llpk4l8EtLJJsHABPK yuTMFmtAnHva77c6Vi4OoiqkulSg5fyKN8MjtOlM/t3fozgQ4XTYiAOfp2kAU5dB96L6n1GJDuUa UNpiYImHNxB5zlUsj9IoVRfTiotfmqiGSgaOMw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696) `protect data_block C53OVwDqMXlTNw9pB2Hq6A5xiWfoHSH6cEmfLsvGpBYSOdu9gNCQxjnmkbrES23nFuGSXc7/NXDa vr26m1N9Qo8J5ciD9k2o2RtBNHyps/N5oDLbC0BvT1X2ghGMhuXwoPeJeed749L53iSCRQ/M1KgD X3Q4fit+I2ESvjToxtvDm/wLwSCPe2Arp90dxXiOQ+x5ulGBuyifbwEkG8MGeI5b3wJe3IB6hkgm dw/lhkH80LFuLEnmOjQvuYLFrUzTMXXlclXQNQIXxcFVFQmqvAFSgWNhPmH64IatUVBCeoU5l1DT f3zJYgxRWsil2S5lT8v3SeeyXaanVkYBxhm2vJYyQGLfGmzQ7wj5pz+uFPgjlfnauUI3qRa22b92 uzCQI5LftJuWd3FHOPETfH496iKqXK1IvLXogGE8+/M66dmfRVJiqxXfegKhmund9Amz3b9FqqMk Tn/jnyyRgRRx0CKSHiIU4MyT7Le3YjUVyNOcmDfFLf/TJmvxi9AtA4h6V804+iyU/USIdZREg9SF nrzOapqCrp+cZjzdixBgtOkVxhdFSUntSxR8wnivupwaQctoaNTkrAtV5qw8kpSBIXykQW6kX+ie OwmijHRPmxg4JZoCc8YggBO1h9t22Iq50PbnDAmdC+DwJVnQA+NGfDUTLwvHgZ7759a4DYANg1Yi 7m3f5y6CgUwGcz7npQm6PgHbwFWQrzAInUe3kdlsauKYDetghTYY9g2AjcvstonkRpM37CZpGYYb Sce72s9pQiiXMvGf7/Pkex+NbGNlY7uw8GKjslVmYDaloBPzchifNc5Ory7IKh5/WSAVXcz9INXn VF0MHHzrBHjA2GmI6EzzK+AtUY9JB5f1uqF2LiGiBkW3Dfqz+elJ2iQpYsU2A6heuvZ5aaS6DqTh wLv1fZeBfHA1bPrFve1kGmLxvViUgyP8NolyNabhxpV7jo5sf2HM74/uHPbdlkSJIqGevOjYsbpb Mz4dn12jYDEEQpTg+lTzEZK2EY5eZ5ak9cEgaQIDZ1rlsE+ikIXczo/7VXc89ePJ+BvIB3Lm2rzm P2NPYqc4LwN6yqDm2jw2v0NdBGtbTfBh9vqrYK9pJljXzqMg4Z+CM9I3HV6YkG2QQNsSrbu0fBpc foX3dalHm18wkKUwsFY2ldsmB5cVZmOngKhnG1X9hQsKOiMnX3c3dCoFKXaaq+SE1dG2HhYPvTEH oylq1L7BekNR3FhSsPZwIcP7egQQda9iPdjucoLziHl7or9J0YEyzxhKaLaXwTT5p+zXLeIx/2X4 pPDPztM7wfMgPH44Ziml1Z3olFgG5XLsdaQJjTklSll2wiqvZ/PLjTKJ0fBeGxMKaY7anAvk477j aOTzuLdgebaUVmx62NqgswZdfJlPMHv2vS0SgCHjaU8Wx9lSGuaoOZb7WxgEUPTYlwSZpQjgtbNV WFEQMByIFOpvGKrAg/tapRHYsOnlyH3A6slIkoRs50fCjzQO98XdMEaFOwWX7WeAM6JZakkx4vyh BX8mvrNhIFw7xZZG9PyEfr6Tw6yRjArIvB65dt5JFonY5iTH9LRmthM+nMR3AoJE8/tPqvYeIdE2 aDt3LpH3eDzfQKCR1gynGxDPEUVfyzx+Wo8EUNpgh7sYhUvajPGyiR8TVfqa+ZPnpV1koAKb2pKU NikYnMePc5JZqgvSSoxi51Z0p6CzGUQ+ASMg/6N2xxAO+YjPPkf7euroG/bGYoiUSEGCjclewTen k7jHy2fRkBWXe9LTDuPxCOTC/MhbCL3oyHhOOWTX7+GzA7cjvmRH3zQV/YpdabWOx1gBbUSxzckB KiB+TigN3O/ZljHJRkXSJSo/fUv6R/auvqUvH4FDjoS3eYrnCUUK405KbduKO41/sK5pWVf/YVqh wFmT/iXgzk3zTLEXvazql2dg+C8BY2Yxw67CnpZzPedU2kRRduZzybNr2xY3HAB3H9bo/iqlkiPR rVkxSjKTR0gCVI+z6oD858UR/beL3pcGXK4evDMkwjmH7ylrtzt8QqYhZV7iKhJhmmMWoIu5pvGe ls+IC7cSbkp7FuESLGV/ahDDZWMbgHMjAjBaE1IrrZtQXK1TpBe0qfayrHIclurFBRNg2WM41PVT mHMm5orT9gmDpFuJI6WzCnIg1fHrNFwRVw/ymCYzVcfcm5r0xqSL42mc+0ytOHPh2F0lZWsnNy5N CoRRjyH9asAK/ObN1YF7g/CxJhAEYTIMhMrL6YYU5DFUkPz2bBEt7vAswDRIF+3SUEDqDJmTLzr4 0RyQZoVbHSlIiNBH/uBYApj1Kgm9G1Zs5vukau5udE9ikAwA6eHuFl+XmyJXeeQBy8iTPZWpnf+U otSN00qN5n37gallnJBbvImn/1rBwMgWFJwcS68Y9zJumXMm/ITYRJpgc9mCKHOm+JUBCGvMUhXA 2lBJGWMfvmjDwKHMqqIDMjHJyOv2xkcEisAHLW90avIDM2M6ftVFYoAPkuSL41EgS8/piM8LBYyO aFifxREzwhq6AyPC2hsUZxxZjc9f2eAmB/NRSXRx4xqx0T5tH2aSadyWiOGtF4BIfclGHBQ/yXoE zIsg+Jbobg3Xa5YKAcIAWiACY/Hx2MA++2suYLV7Cw1kUun7LmWVdopa9jH10xfYkPjCmIfGO1gK Q3H56oZTsSBwKQnEShrwozI460wDqBCZxfteJy3uy49V8G6AAwcojnzIJcpHYC8Rb2XIV9SQUV+S LCqrDlbJuBL4cywHYNvb6BtSJ7mMv3iMyleEcU0eMwUDfHdAZgk6TU7t4raOVSoQ+dZ3MIla4q7M U/UzOX+99hKY91hIw10Az6i/0oK99uJDcVJpqNUYR+cUgjDMusNsGAj2ClWMBeqrgetETcWTa6Oz JP12B+T6VDneqUcfsOIKTT0G4lacToJ1JYoPT4y4ki2si21JPdwu0abibo5MGw7TJlR6D1j8eGlW K1fgkpgIJ/+ab2UM7yEm3wV4lhMSxoXElJv6gCJnAJw7a8VAgKmsJVaIKh4u67dS3l6aGvGnGAKk jgKyGWyEHzO6Y/hthaGmG6VDqjdtE0Q5K88lqzvb4uYGBQD3DpFhxvkI1QtQtSt/aymXc8ZwC+df gu1TopD4Tw3Vx/v5v4kCNHOEo8+R4+QmY2l+78WT6+Bsba68A9vTjjpH0PoGLaHKYvXfgfgbTBqq cnfFD7EH5bdOffD2z/Ua0kRk7dtO4T61+/SGgTp/UeZq6xDxViVVoPMOXKEuWryvLQuHbc8rtchu ewtAPhZ1aMfY5EPfc4zw8fjg6LHjLOWNZnkec+T6+AEGynt3jmhqsvWktR20/O+8jYoAonXG/8Ad LgtoFevcpo558j8ACn1mS369T2bFAA8Y8rr2P9XJFamI0JGtrQZESaI6GOnPbBOebvaI25IIQA3V +twOKs9rYt4WUqC3FcHNGo0hHn1x6tO1Dbl3Iq2n1omrOzNmDmDDHoMpzLBmphDsnY9rny/o1Bl7 IBwk33Ne5SV0SsdErjUJrgwOcmamHAChm8RaiQVfp8nV2GCfDyiCxaxp0Fws25q9IlyXoiL/QneR 9EuKCOZSlSPlsfL7mEPQNp1NXLDKa10Ey/x1PCQa489WhC7cSEpBM1v0/beOHwOsSXiXKED1t6P8 lj1ajiMfPUSs2i5nX970xpO4pAqTpuqbFxitPN4k6eP/fQhaQnfSYqYIUz9vMOS7A2vWriIfOZBc nNrRWbxWovsGP3QqkbNCN7h/X6gtJqwPELHSD9s7deDgCj9iyBNx206+fnJnVSf03SF9fKAXIxKK q3hR/sIKnpPGtPsmbdvgHugGlNTFCGF81S4Eodlyyz9kEImxCPEwOKrMOK6r5IsduMalawGXr0Zk cw369zsEmKVb2vcYuZOxCRW2RTMBA18RJtVeAgvhpkKauFt3I3IbpbRNGqtzscMVFRE7mfl3SaZm s7j5XRJHZZ2ZZkVt/VtxQxIgzSti/ssZWjbccNohjk9wV+6QsQarkcCr9Cvey3Basjc561Vzc5ra 6ptvsXgxOBeen8S1NBo5MDrjTrLYGvTPFqXoOsI1p9cX1OczHck/e+cmD3q5AgPDwXv1OCGg8qro d4CNXsFbqgP6S1I7HIG5XYqxGVAZHdtMZadSxju0sCqgcPqaRg4jMFM8467Lgq8X1Jf5NF1GWPcI wiaMvt7c8zNvGgN5f112Xz8FpmXZ/QZUwN8UqB5W99D8CeV0RMTj3kyao5YIalvqMv/S0p2RdUQW RtlC9MOXpwLGw6veJPVk8BfUIyFOCF0i+3sfQnc78eg1oOp3aCbxlSfhdx5ox4wedQGB9SH7T/KT xn6SRXt3vm5DDQ0/9bP+i0TnVXFUIlGOyibKm7FPQ7mH7aLr9WXu91EHKsdSg7UUNVNKxgoU0mxE hOhDnvr74xD5Pi6scFlrIQPjQHpkwVIUPFl2Xh6elyYG8vMXyADm2ZGaIwzk+mvptQZXKf6wKUIi t9NbTy7LND4KdoMv5M0JcPeTk22R7HFDW5VFNiciXXqkRgq2fWKlO8Rb7CyQm0bPZLqkH9Bs8D+4 iuE8AhLx7wn1sHPgF68zuxlL+8vwoa84GVPtLAwGCcHseXIiQvA5nhGGal15PFed9D8mo05PTN/A ivqT6XbyWN7fN0FB6Bdpu++mKamvTov+H7IDpDqnu6bIBcRwqLHPv/EwJjl6Q8kVAuIeCCDhd8NZ 6zzTRRFs7JRDnICzxw6s/j5zVA3dsWrhoag5YU2rG3fj1nbC58mux9bj2YEGPyEhXTcLaicuRfr0 U1zbTxzXyUfNfh8FQBR7ysSbRsWvPO8bfOebHyrG27cxG0iEVsEerFZy/QFYCa1ZGb18pUl/qrf2 4ACQ1J4oz7o3kv8wmi/KIj3w8XmfBSEYRc/7/z3zVdNusStu9m0fdiThqWdQ0/B3MZ4ulMU74DM2 i44dHl6T8A8NQSsLIKIksgIKfWtnCJXCGbQr0cyf3mn2BPWt1lt6Rudct7JoeKP7WUiwPTkMJ7jj DfSo/SbhjnoyyqFgliybqDDAbFBGzP9cjOPiNPyVlkmUhmxppF3Fgp+JC9FXj/5UzMkgIi7CQjMz LciwEVectxGWIfMCn1DlhYm/5SvctzoiVqzKe3Rb61LuW9GRQSK268PfL5qBtl7YLaeiq9tNpuBw DRsm/jcJeNPEt4b0i/guH7l1FVNNW97WoyT46mnv3ET7cwSibG+nc/EcD/dKVL0LXB8HfHasJDbW yUeVxICuOsEidvsNN1OPGKKrMnsxEpAqi7Ip1b+dqaJgFbOJQAfLWPSpasYQOqwiSFoD4m71TWky vYSbzzQI+3pn4mz/poRIm2cnARbXqWB502EWcWMqXLq+6dfi1ZT8hWkoHDTQam2zpTzDu+iem8c/ aJxdoNS9mfDForpi810KsXpZ2qtF7vMHhHEM1kuBrox8bet0aUcgbEXYOvO5zQ65eT1SsSxzgmju cR8MI/sQ4Mr7gEqkA5hyxk89oxzVstfwCiaFFYJqx2TxXGE9qyN6bE1bgaFRV8shDlniJyEh7Kqx QioFNvFhXrvZ6QQ0yxM0VePwhW2tGJsKXRXDTJmvZnooe2Aj0aTER2QtHwH/G3O0sb50128FoXoI eUVkOaYPLM4ghTL2Ic8XGc3i2AZiOKMs9Mtt2R4rCJo8J2WKJ68E+INR2CwEjq1diHB/MHHBkq6+ hv8YaVirTb6b0WmCg/0yMVlk/elNTcel8LPL8Ao7RltwM4eRN5MoUtHytilrmazHZk9j9GhlYVo6 u4eiBS09gNaPcrMjPUVUUBIeXW0QylRusmkYk1RdOrvDM0opTcuT/cXarcNjU+afkAscEL6Z9mjL jEWNgNvAP5ZhO4txLXTkeuuNUNF1hk2xkVq5/yzWlmi3UC6aRFx6qKk8vFwUsV5WpnYBDDWvJOBP nzOS5xzxoPMoqYhGx4W+Zj8yMYbN+fLkRmfYCB+zKY1jZxqO7pw+6ZIecqltT01WHWa5A3a67smd sKgQ9jJH6bOgXiGXA7gJolaGBiAsTk9fDUq9vhx4GpXNL/3c0m1xcb7H4k+Fm3vkALUlK0jXZTjR 4bX8Ezk4ulCDmqe3rDbcSBbITqrACpa8QM2Qg1pWcl2UVYxK0J16SKZx3iymIzgu2fCI2BWygDlZ cZXpiPiCMQzCmACeqL+NUSPBML8FsEc1EymstkQixl1yP9i+2im6ZWASkbKd8JAmd8IXVlUWoiKF OXPPAFeXF3D2yzDE2tnUHl3mgdPyqT3FZSv1I1r/FcZ+hGoM9NUSEfaiN0oF2BmB4kjoGW79BGE7 yDoXIez5Atkw0c9S9LF4PYhEdRw16AIw7G5M2u1NFOeOkcsoMpculS1+GHg3kWtHQulLgUaRuvHZ XMSauTJ9Jxke4nmlztoV45WxWwFBJMfDQx0/zMripmTOGVLKIASl3aJRX0CuGxu1rxqYum/odSxy laTrLZVkJZ9P9ZBn9uh//qLwtEUhYQOO0SpuVlm1Mh69XJHWfphCoB+uptE1IGNWzCsJSc5znqp7 4NcsJM/enE+v2QCEjtDfeKEmwqUXkxJ7s+8l76iaw6w4vOHA1ivzIhmfOV8j0uq9Fk6p89E0vM4U XB6E4/j+K0pstDQ7Ml4wplByY/OnRnwC5ZQcBoawLEoCyCi5PCiLRBdQGO9WOS5E7u4fc8nSg9fy 27RJIfKrS9XrE4b5mdy1EQyMHbLw5lTWMWMwaU1eU9qU4y50IORZsWVdnRqxpfKZ+oCa3RSvPfKd JHJcCGGpD6nNEjkSpYrPHfmE7l8QKXgGcblIpsYcHb161BF6gPijlCz016WntKB4RZhlRwcoUQOe Hd3Mjx6/IVtsztuMqWV/npqmD3TXvqqUQgIpVNEwXBRdYm4d4CyJEJDsSjpI8wzRyR/b8H1GvRDH QXCFPquKHSsYjFFNSHg4EyW38g6bBsOuv7VGEm27jc7ujNVTuYt32Lk/oHBToUTlLOb1Q6+Ya/JB qpL75CRCYMY3kLuLuijiaoUgZdXtIb+TXZjMoYIGhsOzkIzUDONjjsgQ3juiJFbtvzkDpth1XMGt SF4DSAJQDh2hIYYv9FP1V43UL5YO1RK4sQZX3ZsOmW9pdrtD6avdgEVmELyk3bgukVNbr22uO0un qBsaxpq1gnB2lF6RwclKPgrf7q/O79e96Yzdnu1GzUcZ1YhXvkcC75fIA0q8Wpf7eJEMK01J0xJx UAYQriyMXhYmE+E3AjgqtBR79B4PX16g0infInY3N1ggoUOFaDrx4dzH3/4x+34OgvrfbUuocblS KVgWLk3FRpvZPYfMB4WcSV4ji7e/IhWWmBD0dNFlpTX0RISb0MARbK2BUE0o3t80yT7ZznPUmrYU SZMgi0N99zeqpo6XonPPgnghh0TANf6vQrxZlSPCCmWwlK3eXdDAUwElwEDKg28nZtLVLjqhYbIT kCNsbaLi7TBtHcYcMUHNsdpxOKuv8bBRwfqHLydZnC4R+SIa/aEniUR7YWKYKRR0/P0XqBdDkknk LREmwLtcLgxXKPDWqA0QsU47t8tUSvTN5zk7wU23Q0M1tgz8RMBeYhCU7tO3Wi2GBqxKJWJoBzrC HQCzaj6qo9EkWjmGb/T88Pq3sTluwq0chvf5bXlmZcEdEaE0p3BPxkD/5lF4t2kfK7bovpIkk6kI Jelr+dmdBwzkb6LnGifFwD8IBJ6XCkegnL8W6/b99iL24dEbNS/0ayab5jDy22EW9FWODuSmesNy sU8tXAotqpzhHZs4hcDq2Bik0qhpSRjmZ1c21qOplvxAT8cCxtjxt2YvihtnOcKCq7LpCfd0EWM/ 7L0AmVfo7civazcySENRnykvcg6GbjBXLEdiQ8LIkMfuD+bhGDenUDcmql+bzcMdzN3G7XOBcdBN A/HsbdpmVKGe8LNR67ycW59+JJnJJJUIcvmviVi8cToiNZEoTthAyXza45doj6JFZHUVXEN0xt/G iacU+8I9et6zXG5XdSf4ILfZWXIZV9bbmUryw9CXDcK8mMjhJPzMHUX/El1+Jshg1BkixszwUFnn B2Dzok8bkFwluiIXpoaqtWIRRLKxxJbV1XKB11TysW8RjdA8IR4I1LGIsd8N0fPGQI9g3HquWW+/ ZaFQ9uszawcVZBrr85oJDTqOVZAcHNFl2GeZaj4SiWXF2dru6r4OReAAmZnO0+Tt9d2ZZQnXuHRU E0wb8J8NIBZCvAkGDVSEaMqgTdMqjz7MRBwWmw/PSU8U8P4Ty8D8EyMNYTnqor0owwpGMgtP+Hsb 65bS1+aUoAmMRpSvJuN2ZP/SQ3TQo3Cyu3Ezgbn3HxtvYzqxpnNwhDJWELRNm87BYHtjzcU+Hjc+ SP9Vt66s1FkY1qzrLRvL3RWpLKpG5tSGitCRkEZX502iNAndAyEsF325LE3rPh39VJZ6jERJY0cr qMTJ+14Kew9kEkfz/PIyeTUazzeVstTcoGrpj/Bf6bv+3y9zSTOpYPsGpftGHf2KxL7gP61nYMSz SJdK380V//QxqhDKk3H9fTACheuiaHSwodEd/udqUUSoBi/0PiVVqkvQwiQk14l/ds1zeRWSCK2x cBqysfwfrxEi9ZVFIyV5Vk2vwATDkRZrnuKZmk56sCyRSyRsODwAkusUjWAhtE+lMH5pWoEHO4h5 E+sBIxdFSQjTgETVhR78I7UTTv83EW34BKEb7MHSgeHZV/rDBGfsd5KWY+1zwY4FhC9cPHZ4MTJp TivgPyRIpCNH4ir4j89A7qU6ltFW/JslIvUcr8Pgam2lNlwx09USwnfjQk7rvazRClwOvNyJvMz9 IDyp0jkjyJimVtvUzu+471fcs6zHtdA5w8S+0S2RWhpRmvQsBX2RHn82d0xJC50e+GBzoIDXY6IC 9PWz5/lVEclckkQiaXcLvg86WKiDXYGd6g3ixg1Djzo8miUR+1lqMlLGiaretyjQqkz/y2KuyYFw 8jpG78LGV3N1ciWASEazyXqDkNTXZujKN8LqZjsqTR1wXznsSXk7+z2zWnC3NuEIWvEb+bCw+9BK bPCf/Nuds7s16qsxtT9sU1uFmAyZmrkl2AdthCTRO2b8/40HvG75g1eWUlrKq87IEC95fbdDeXAa dWWQHKUgAYGpgHBXXBzrqOeScJpTu4ovxmHqrXYXP25QjDKjJBYt/mQjuSKIh1pWxeBMdBPLJEcz 8QjWWCBACse7h02V1GNeC9YZhadOEKHWwV7xerEUMguiV1Gd+qksyRswdSyxSOzXqyIlWd+YX742 3IiDKnZ/ngbj+Z/+AlABpPH1ofGAKGYti+SUKMfiufF9ZF+QsvbZqXlsObWjqARzCTSIXWsCm5Gx diPTN1YakBEMNVmFpHYoKFhnVsB8gngc7TLIY4kjM69CfAKNv0HRqTLFXr/CVuqVWuictp103QX6 oUu9iC4BydO55oos2A0ZUNTcJdnCWUI9gHrr8pY9dNW1KNPtJ91dxyfakxdmZUcR2uOHv5WYO4K4 yR2EdY6mPpaL7LQ+CicA/SSA0E8xKUZ6JdIBMhIWeWHXh/2IwfVR7UExqMciVXwjEINRLjFgiaEn vLMzPg/1jo8x07y3CdlTqtzpnUf2Z/8/Oo+Kzfk5M0EuPyF3TKMXHCFalfpviBuw0l1MQf94rVYu RJg5fo0s5aRrLW6LBqtW/5FeJqYyxE926oOYbVbP3RxaU9aSPAUEHK+kgWjArboN+JLv9yNbIJOc Ce7ximXV3VlF+Tn8gnFffg5VIYcTDi2pszp001RWjmVWarF7FShyP6Aqh0KCTWc5Q42nZP9Ctybs bKpSsIq05Ua6dBnOi5mEJBhmM56lrcV15Zvf8u5EI592bvT0SY81+NSINuGPvTrFkn7/t+HsT6Mz APA6j7P2XdyZXVpksAfo5R6OvRxtnzgkHLGA2ZiKcLChBaRfFfxNExO1uZwbV82e9g65CZ6mHwzs VebDyZPcM9P/90J4+sBeq62VkKS1R8FMdJ3G/jjyshMRwh9qLil21KegroW1t7yH4wPoO+dfCpmg C37hF88/UKEReq46QWlLUffYNim48OEm6jpd/6ZelhoUPlAAx655Fd68SLcLhIvZ0N0A87v2vsV4 CFLQd8BaL68AIKlw8vo005Hd9AUA42vMMe6wJiAfues9EftCw6HE1ddAPGPVgBwzq+pNv5riyxrO z0eDzZ2HcBCNsBEvRLATJtLgNV+TJv3LuXTGVnuWmhxLUef1kUsOdtRAa+yC84afeI4hFa1yKqPZ 5zZb2N11s2dudc2seJ3dk182izO5JMm1H6Ba1k6dOdB5SPHI3c7KCnshWA7d04ZXHgYAqsD65g7Q JbCse++Kwueu1pXxkJIjlsiTZxlPu2qQPiLMJJUhjD57seXY5e9dcNfKUZTZeWzfgpPo67C2CEZr KVH6jvQtorLiOpjYIACnkcpcJBw/Ie/m+IK3e3GRWj15V0XpZH+cdjlK+XPtWc0Bj8OERdimO89C CXNbKt+usuI3ecFYyqDE20EO9Ln8l3RFiedUM5QlSrBLv66J3dFefrDRasscBxPjBYt2nuqSHUG/ HDb71FF+ZM7w0rHCURAfaXw39V8NoGvVjVNptNpeZVup9d+dlYECIRswQxdV6Zq/WVc3TLdyVEaZ M44fQO453d/61Z4I6cJxF1LUWjvBHOvXYOmX+GVwXwVdYoELfZwsfytBo+JMlFdIqo86Hn/c9YCv g1L+2ey6oYvL/QdvnpaMOni1o1pY8mwZUJUVqYeD5cHfUUcoCPfyJN0cZG2x99ofzA2wijs3VmCm +evlT7gEFSaTX2WH60EAXQL+oOtUXn6D7Ts7XaBaFIJoK+HrrfTrtuAgoPCVzWLBHRupUIezWQgr 1baCLje7cMGMu6LeA5LqwI0BAsx6AUG3Dj5ztGToZArTtcqAzQ9WERrISfrIZq4MzFAJWcmAgmCn gaRkvn1hsiQTHOqi6OM2HnCR/qNNXwa3UIdCyVvj0Dp9r9jiA0cF6k414XFTL/q8eKe+oIt/oXqC LEIg3m3RRamx8b+oNP+HJU3YKlvbR7+fzHVAlyfpwRRS6v4fo8xTRJav1MJPHur+Z/95dbJqvrv6 95Ilk8jRsYYX+/B+HV2UpPnf1shBFkFxWPd+iNYtfUI6duJAei/jHKrJQa9jTlcUlJMKA9r8kjmj bUWi/kDDTY+JhI9C8058VB036DbTGG73MUkOuCi+PoWC4dAb5Nf5aiINsQ33TEqBx4ii2x4iEiyR gSrEISi3uV1MB897O9+i4lU2B4BtQQ8iJUeqgVAdI5V6YNMOY1uh/HsTUgbBZCO5zmn9LMO2bfeG Ok0T8f//Q3jZxzLKutWEgcGKLDDB1VN5PpqXxelBKeDXJADk+mDLv0pgTH+6Eud6dNwbAmkwtXH7 kiX2s24HeEpgzY7s9pGb3A1tCUjj74c9wKJVn9BHiZVOeDZET3w9gdTmvqu03XBWGeh54xOfEzmm RSrBbAfus/tHk/uJyRFW5RBYVYxZFIg861qg85cSlkLHEVL9Vrt1JMCunEuIdvFOM4JFDlIxn+fa sDOvFDxjCIA9gT5F1b6TR1iwBBPkLAgB5ogtM0EY3A6BjRceAFo5yJFEkEx7e3t/5wWMBCBmEhYe 7ByvayEeZ1hrKEfcD+KuAK8FUi2GxgypRDeP3GHMDRfCC199enT1gLP86ZwCzPY53tZf09J3Qk7n s1w0ts3Tumka2IR92KTsGpaOhbaZhcbzOf1fX9Xci0aI8ieMy8OpfDrFFVdsfDpZWbBDuIGfmmtZ hXPT8PrlG54R4QasrfgOfZWyuYPhScLh1BIRxLIV8H4O2jZKmAfJvpSOSdbL6y2/DL0otpyD6SIX hVk0l+f2ADTXCKiF2KmrrW6yUxSP9FI9t7YehxLgDPvFpBUhusLFKN1um02dXYhRz3zxmj+UIxkC cvL1To6pmih4fPDby3tj67+3GLBfrT0XhxsSS7TSw/vvO7ORpSAYEfFFN3s9GVweIVvlyCx/V7Rt xcrNXzBsxlYS4u5y6DlrmkDKM7u6vNaCufOjW5oGIGDjWdcUpGwMoUv817JW9hAwEkAkirnLbVRI faANn+Qg8hp//82+V+R5qpOHXsNrgSwR3GXVo2J4p96MzdsLd5ReF23S32Np8iJJ8AiaqEwCwFwf kxLcL1x744URtKwTJRcotlvWTqh/R2CGh6L2r88oowCrnXz69pudhjmn8T4if8GeQyXzr/I5zSdv i5C/iOVOOLJmv0N/O6Worjz+F8olue4QtKNWLc6JLqM3fikfa25ncFElDUE5O777LXwFLH7RDNa6 o+wQQosg7NQ8nFh8CT1xNr5U/YuD26v2pqQAplLDdzr2VjEEiGZ1ae6D6INPqCmsuuD4Wb6bF3qw xAqgqicLc5JxFc+lwu1lcYYuXlMK82Ch0BNgRZzgaqxx9a+dQnyCokA77UbT2uybNbJzlAbbjsMx 8QGevO7ax1a23bDnCGGNd9mRIJbBjDKoxZeT/igK8eLi8DMHBUswzzjCay9oZ4qkx6hbmQ9lDasm bHBE7OiOx1CU4Q5J9A1cQypi2Ns0WL45Bs0+nNSYIk2HOGtL18A2wydHFrnlhuH+9A1ZvFJkYcwD 3BpFWcWDhm7wZYNnqUKK4Ph+eQdbM3/mpHFxjaIjQG1gaJf7tWdk2VrlqodS6g834bgb0+lRjH3y n4oSAitXIm7Kb7LGPPK5JCHBcFEuylIhrzGnWT/dVaF9asWBE8CavtuuwB7AfSrLh6tF+YAZc1AY IBVHVGj4+nSJ3gqISZ8VxERWIaireIjg7aOMxytWkeVAFRB8WjT/XNqV56NVYjxxr4og0pha2EDg eCEYyrOknBlwGocSnZqMyb7YyZbMCu5iyYWJyUTDtwbe1RI0cdYy4UPqEb3qUwyplgZXNvMmhIzH AO0Tco6KVNVDLsRj4t4tvE30yzmexrzSq+PyXfxzs7ZKdPS9UAGrFDu3O8aqVSLe7aBFOKwCWdbO 3uGm7RdvJYn8WluH3cfdOSqQlzspF7Mgbg8vKgtjcP/9ewOJxgz+7qGFnqFl6q1wIeNlNcGeckSC mSVf5TfCVQ/rCLvGsSEZg7dFe0vleSrkrCm+oFCZNVbyKujOm0QVOzKfhDKMGY6LGJiOcAJVnLHA ZVtyeQVCcwxgKOxADvRMOrIK8OoKnbw+IVqTY4pCfwCTOH9bejc3rj9p04M2mYUGIIT4Tsg5ETK6 MhyI03o4w/Maa+4RcHoet76E87q1e9jzAueje6yGGe06DiNGmLYUvrr/n3yVt45YJSSwXumUl23d 6JVYKShf1gdCG6s4AB9mlfhfraC05CvTQeFTm3oPq68ntcfVG20LqefJfXTxT+yKnvHp3uMRm9xu 0QTdHWJu8CWna82QBq+0vwrlIcbUh2y2Sor/kghk1zaH8ShZFoZqlmBkk+VK5wV7zIdqSxSp34NP H95PdmbfMi8FpU16weX85Z3oQ4QYHHyDFUJdgqFB0d90pLT4bWf5FUJM6ggN+Mf3INnjK7vCG95H 3pLAElDIWIj+Ffc2hvc2LLwpHlrmjU9ADV1KIAD6KTI/BBDfKgnKk0ixPXSBiKWWkohqAnIlUEvq DL/tLvmRRYs2kYxsZRZQMuHcnvVF8dnyIbCit5mMWES+j0mFMzAHTiV3ek/ViQ3rDnVyb/0s3Irp U9Q7Rmx3RO2lNO+JQzfhg+Czy/5GwaEtw4PhveVnEEs15hN9jkL6Yp60yEJMnaZ+7oCT2q9ET8sq vMTspwzsw7MD6Vz46Lk4NRiUT19pveLeO+DdNZV5qquVUzwEeTwrpybSC7csWWl71ULXcsOL5mW7 e+nYLes9/Rh0kbBdkenmAqIc4gyxTfGNCU4Zo0sO+awd+cBwv3nzZoIu4cYtC8T/nftSa5r1GMxX 4lAz4VPS5tYZdgQBzRIbmxoNixEz3bbP2R1rfaVaVBnMix/Thh7HyhDX1tklu0lnoNh/6mPVRF57 cw/Q50eHJyX4BgMTTIk8qGqmEsrZky1fBBHgsu+eY/W37mLwd/b1zqdBHrhQKkfmGkICfG7TO1ou eaEW6TxzHfwWeW6qDVYKg/KBkJWjWpqn3LuQnO7xlz7f/rTld5uJH4brocgH5eRWcw40JRtQG3v3 j5IvRbx2BoIs3PmZFcHkAKLoR2OZFhlIT87NykYWn78Fl4UJ+xS0ufKF++9gefbyiV0UYySaqTPj aKRgoW2NWDj6tHaYyEAlwV1DQgVduzaA3Pcx2+XRTCNqazNXC5VDE0YqUphV15ycdl+94Yx04ggD M4D8ZV6cizLGI0rjhuQijCWFXvb+tPDU+mOCps5QFSdd9JhnXyLXxwA9VH4ACG7pHo+53K/0KDbq x1Iie9Y7vLnlPNK4RjlI3xinqeXlgBT8QEnj+Hqr5sum62ihsXZO1KYrgl62YEZ3B7GrFCfVLsyx DZ4odjpcajUaHtGGdyARlMul2KaAt23n8V4CWAc5RFfoMDyLaLVcbrmH5uD+ws409FYitEC3Rgtg JejV1k0RwOo4pvefjZXO/YP62xr8/pq/brJIurlIhZatKy+1QjHxlshFdVdqfm2Ikp0+tLUSfJTq BePVFtfxLNNPqS/Cnh1qgBkM9Vncotf2CAq6bSQpAqNdY2ZUKEKQb4u+P2HY0X21n4+gf6DUUDC1 3gvDHKYOvTGVmTLqdRoZqL9gZlW/s21iiKVY7Y4BJww6UVYX53BuUP4CdrvwcJNpwwS9vZBgsKaL IRTzjbIJ/zuRe7RXwCKnO9s7s9Vt4nqLU8HGEfy3I1xsW84OC7SrtLbJYyyl1ZwdV/8ZGUREKU0c T5r4AX/Q1Mx5Jaw95af2BZC6acAzCaWGmaBhRXzjcwNl/y9C96rdt0h40VitOOgx1Stt+O6XvsBi q39tS0hPXPETaNJ6DZtDwJ53PNgSLf9HtkOkgSISqIziwkaXNlj1z1fqaU6FSGzrh9zmow++Ykjp x51+lEvI/uZjz43vNURc4cX8ziu6LGYVj43HxQPYHibu9SD/8CoZeAYjdIyW+aNyLIWjwtMtcBVz wdXvXVL6yHxoacNqS7q+DTbPwQKYmRyQfW+iCYNR0nnNCTqjLlBfFeT6IMMuQglTy0DfZaMTObZS pNOWhdGjZnPwVvGSM3W+zUzK2kuDk0X7Advn6bbX8gNtul+WlnMkUak4ImKUBe0Jpz/fRmf0TLSB LlnbptgDegMaivLEDAsQmLNjIiLDelKtPzXGPyjrntSGfx2mE/SFdyEekUYDi+oywHU9BugMgYVd ONVUbbAMPk5qPnqhO0sb5qBPzCEIEOA5Qtf9qvhqMOgvwJE9wONJ+G2bQpm1pB5ogMtA18oSE1yR ugZPn2hdQLExb+7FWZSctLnBdWXhQc2G4WVlo3hZ259EVeycHRd8btmVcG/dwpzbWuayh9FT5XgV ClSaawwILGwht2VmQf6OHaIPzL1RZs+XGtkEdLoNcn0De4BY4RJM2hqm+/FjxeNn6FVq7LR0c2Ep mRxwCRlGg3PTZLFviFRaVf834MVceAMN6bfvM6dynaC8ZES5ZqlL0mIXT+3nCQPzRgpZgKxX2JjP gw+heqEangOXJOvCEEWMQXV29ORHFOoYgqsNqXiEbrCiJRltgcDHEAxEF624kHGlahLwzf9NjVRq nzWoq8p/Bxcegh2o8IxoO+6YgcE/k8dUt8SOTSO2GGkuv0VEWYpqsNMUwtQP0XWpLvr7Q5IOWzg7 YBKniU5SrXxQOE6vd1Xyd6OJt5vA0VYQ4Pcj76OhybDwdwoDXMg+RuZ+4ZAtTSDdKRsrPvAnK964 uwz4SPO4SZgXDtGiOnT1sP4JPJFJahZXHfMlAZjCfq9+emARksGNzcEtTJSPq1UHvF7+K4dmLJdC GtSyKxdZpy2lrSf8rFtD9HbOeFknc81WvlQporB5PxZ7FmgyTFrdoVSi4fzruC/0Hj5EGekphfcy JET9cHgDLofOs5G+CSHLyEtlJpDjDqyi5d3eSuunNgE9MIblddxmqjlc7O3IvWHlRfOK5OdWg6ap mXyT/n6A3QU0qI58fVZOTX2yitaPe1E3r7MEcXUAILxasRsh6mP7aXWSChEqELevhz+3eCLRMgi6 2tnu2bZvBfBrlXpCyokE3UphUghBvfjIEHVVAKXT9mMPMEPeSYz0Vq6l925Q0w6168sH7WdtiLXa 8j8dVEmKuznh9Dsk8T+SBtLckFCK3rmHbqhfcPFKLShqEftb0+ZxejnG+F6zHyTBaMzBIaE6J8rh UMvNAsVRHJ/rlKEMbHftPXodnQFQhvuV2luL7h1Dzf32oPo166eJmWYv0zSMxPjOFOgm91V8rnu7 iao1jbHKyQGI9Ik1TC8JIai/Gfq7Eehv85MFn3QOKSQ/DEXWbZUGwh3LOXlOysQhDCj1t5O/IXmB uW/8UAqS0CMPU1Mz6o3a1FK8f2TU1HYZsN1l3eStl8jJ8G4/o9rZz327QAw92872cXfoc9774Dwb Zjh6+TdM8nRuGSey5F4S4EzH1GH8GlrWcCKZW85Bbn3J43BqXJIrWefuAqu8TlrKOF7RVkhXKpUo WLv+61gX6yi5N5cTlRdKbB1Lo7XJOmjSqlCw5W5olTHazD8i1o7DwVxi0bVt6QmT2Ny/xY8jfjK+ ZMx8LDY6wcUv6ntwTSoFqzK0T6i5PryJjJ6vlsSy47jtXgky40X0ktHN4quMVJzXTx63SOfeJg+d XrLOCTx8j9wnmrEWosSKO9VyG7JoUGa/lZmSq1dlhZzlBBOCMe4VaFpbFaF+HvZZnm2FSETdCbsU pG9l+y7xNvb2ONN3g+QnnMuqKeAHc5Dh4iWq0ws6COP1RQaW4ydj978HOhQ3d1CYmwOBuGPJ1J4h vyddIsfQZnXg+Joq74qBi42RqAs1CenTqY4hoTnbw4oRK8cSO5alJaakK7Ji+MnXAL9KxK/FMXyE YGV2uhs92qcoTaR2YT0TAQwnx+JH0Lj/IHHMs1d7sHzMmlqesO1G13qtUwOUlhMM9jGRWFQpLbBE mkdP4XeITcJnhdKagpcn8NBmFXKOxb7DexaxPYsEE1UOea8e/T2RTv+ReyV68l3sfG7+tTO8L45/ vh5hOUeRqEXyqVO6rQarfRAImXAdj9CF/22L/Xl2n8xEeP/fVdrkCBrjw24BS43AuYcmRzWqYhKE 6cLw8mpB5fv8PX2foetJWLcWWiL0/+dhCR5P/hkjLbXFInuvpSuJgQ3v2vIewAYN1C6l9k81xiMf Y2lwxgdR2zt887S6aU0rkazstliJYXtSNO8u8LNXq7RWBKeIvQZYpDkX6iHAkCvxjDXSOeS7OwsR 0FX2xldegdB92QqmrAIt+igqnj+4X5ksJbYRWp+TAOMzS9PBg7JtjYE2pEgpdvpIp58J4RGgyWNf yufVRqGnYWm8EaIYU8faJhrTyRthypq4FGolkSxB8WskfKrKeHgg4z30F3Nv16Lynq/OjY4CjCUj dyMUWVn0txBY5hW0+1oN6YU7SnzQnJerojvTyLMfvfGpQ0nAuOGPSQouV0wubyfezAykWP3Wb5LH QCYtCRlOnaK0A8m9wOday0x4fxTUK+yjFShgnfW/B8onyPS3oYhA6NiAfnFvEEGDCUH1rXhYItvL eEZd2eHIiXRpKL7H79sMh7czHWdafRMi8iLsttlyUFbX9zDIRM2mWhCyDkmQ6c6zANrNNHl0wayd uzMeSRhT7fn6chNR5FrfcVnaJwweer8g7xiTcq2ilGMT7Pt1JLbKdJ5Qrih+Hmf4D4VK7LohNbV5 JYb8ceg/vDNEXk/iyFXiAeviDWjnGjX6MIAQUqICEQEMbzSfe5oKF1gc/BK3xlebvxcItkf9q3Cz yYto5oJFpX5BCHA22hMJejzuFTXlMNYcjR8ALiPIwsN61D37dEkYQmMPs7HY6OmdOXHvNuceO9Ga c2eWm++5qnE2eOYwfrX3p35AuoZwqzxLQz1YgkJVN44I6C00w/GV9bDEikFkWlyP6WSPlotO5Q4G WWDuaatFyBYoRp0ECiTKignKG9laWIXM+AVHxRddAU4GxBoeV604In50XynXGpCBwf+ydkhgnWw/ f6MpxCgGZaxU8AkxTS+lVB9jBnjYsXzYSXjaImUmYqHYJKK97RSRiLtSTQ3djlaCXcR7ubeFtee9 aFGCVmOcx4Lj5ZQ6ai5d7crDgk7w8WbT89dPOp6Q9ZgvW0qrQGqqXwD69farx9sUcJaVqDhC4iQ3 Wh38m6BfZ+w7JaR53MfkNy7RUZ4HHc+JvU+UuOPF8IrjWz5P4CnMZw7YTuFqVCIyFuBpM8F+Qsdg 1WD31ZYXM1+1e0NlqrH91cYCVLrB9DvBVZMkoOBUAFeU/IQ95eA7ikJ5MZEu/frOH9N6cNcSF1LI akpTu7whWfVJjotdXafIqU3rJjGf/dDn6RqFqoHgCAACaddKS4lyCB0DjWgr0KufGsCQVjmYObLo XH4ynzaUaRwoxuwY6NMXqEc8kT9h6QdTs7qHQZq4Oa9S55OnJC2dP4ufPJdF2cDG744cHWdzZ+RU 7YQogz1pL1SBOHIQP2uJBNCiJ1O6Ih0bF+2zeLjuiJ/1cHSPJVKt/7/lLdtYw/QcEc99VYMsklbY iaQJZaPdrFi/EKZ3imKi7bRemY8PxoCiHm3hf4VF+20+9+L6F7GDk4wZy7O6Y01OKfva+Nf9sHUZ RcECLR4MqTLDyK3vVQ0/BKkzGUITPrkIJSEL3I1MA0UZ1iYIOcYzro9xQUXeXGM3k5ko2om7JYJP vrMQn1j6If5IeM2RzEVChmKbgVmaRhaipHhWMFxYetL1FNeJwHx7KDdwlQU22W6XYwyzyZCjuFW3 Pcm2UIdnxd6Ep6ykTwyGku6qlbBtKbhbZzKFRqm3j5RidkRNTL4Ss4590A6E1RhHABQwfipoUBpY VZ4s+S3XZ7z5bug1J82qIWM3TbNi66rdb94pxouJqWJbOaYyJjmZR7YX9+EuPvs5HqRIpWUUDRP4 ejJVmFi+uKnNbnQ5+pot8Qrz3hCmXZiiTOOoLwNyklWhtawkdtPqtqlM79BKhfBXvRWTP2WoXQZe SyrdYFCzqZKGAdgWxa+CstCzexJuu0SYo6qPFVPz9gpMl/FEsJ/2+bsYq0LB8l2yR/X2vGmSuoUA L57quYTl72nRwpyyDR43gUfXU3uV+JtjmejTmqVaTJh4mif2I3M+VxGduMpWs7ycBYZqFVwgbGxu M7IsXt+lSPb9ku636Eq1eKeLz/tD7/S9dEp8l6GBbrRn+DyuGzrtH0fujC2bXlG0hEDAxcbayjuO N2JieATBHAcfu+oqJAmYaMNkRGfwTFiHrLa4e0LnokHJgE/CdqDSQ609w4umFTGTSZJSWZAGhpyW 3WklIXJB+E+1Kunt0L/PbNkbYctw585D3aXYBxS0B3t+22J4uGPDuiS7vj5m2aS9bWomb/UFx8nf BH9TYw103FEkoXM0RPxC4FSj+N9916VSwz59vIu/Jz2tTFBWKIkwFX527VMlMmf/+icf8Loxjxpp RKJ+tufylY0Znsiy4jCCem6B6JDfFaQWYa//0Vvxadz4/82F/zb8U54C4ZdlHNpXTEpgWsMDX+Bk 3M3kx/tZdazTPFsNbmXARSUBK//h+QpHaeGQdVM+0Mxt6qxqe3SrbwyFNCklx8h+uhiRoADqqENt f5FuXvoc+FVMT1FAQXUQok1mc6tlG+nU3Np9x3mKKcZhRHWMVxG3LMgu25ZIm+wq3IBiccvIdROj bJcX8AYpwabeDqgy0oYh5l5pV4PVZAj96/pxy3OCzDju9xSCqF+3OagKw7O7POvUT1jp8huAj4DF WYgFXXO5/JtXr6qWPfLVoMaG8WAC6yXUr2Bo5b148rIB9P25j8T5PZwKZKhJRgd7VqithDH1qVBX /UTfmoh+1511Dv2caE/Is3BF2TC4oQj5/mDiMxd0H+7K3FtNX19N4lp0yF5vd78OIQgFokkJ5Z2X XK3XcIVmOY9q8cnvtn1esdZxzcwZLsmb+kmOzpj2wSgqWHsjiKgc24yA0DDyImv3riJgwWEY1zGF PKjR5bgoQLE+x6gG6CpXVGi/wdEfzoQnFHpfb25RyQ862+PnjL5ttuIfbLcvW57xAlLTuVrd7Wuu G1devwHKzzmE4AmdcR/sfmC3I3cQNLPVHQunwuD1CWoU9vhXxpKML2Ndk4EFWQM38s2miV+NnAYk sSFJP7rZNYp/AS28YwYObI4f/mSlKjNuKgc7/BLWrdUXcs8ctz1VKwlQOIQXB78Z+6w3kvF9IyhW I1PYT6r9v2/Kk5EXVKXrvuana7FjAtBRK7C4l2bn7udmMmiLqcJTwHAaVa2fLeERCYn1GXXe6ll0 +N2AmU2mkjjFyoiQQ/Dk4NxkUHMnxqjiX/t1PGtyK2CyY4Djl2IVWMesbLfqHCp5jxtccgikyk62 lxVIWMGHHQtCpJKk0un5G1SE+48MXSaQTPct3wWOc9EtBnJy8tyOXPj7lawUutszvBMQ7P94WcAg 2vnQDkTqohx8Fx1GAW76d3HFOUK1i4jpZg2DurAJd4Rf8s1KF9O5gXEZvdzrderQFaXpNK3SkEKq +46nigTWzOpvW42Sk8IZV3eQ1fWxWAI8y3WPIeotHaTBDRW8v80F+UdrJqaY6m3HDDtcXbrqMzG6 tXzpELsG1eZOX61ukCTTkUc1GrqlmAzgyxRIJGOial7Ctx/bqoSj1AkMg0tv4KwO6QhFA878xxWu I8mAlpAMd3Cl68El38GN6ZrpNbEhD/lIqqOuKsdasMgw9G97Bq5rSV25RhrTSnZhhTXBDjzR+kwE 3478YjRW7ukTQAB1ETHHqcuyOIhkpShfthjW+bGLs+dTz5S2kZOcNwaIP5VxZiOblMutw8sAUY8Z Cdiym9anrSeEUTzRo753xj30ZhIPuS6YfDhqDMoP+ZR4XMdXi5K5wIv16ysS8VSFBvHBoGgWn4U8 EtKzodS5CNVmn8keMNoHQnTuVfKoZHFgZkSPIjpljVmQd5hDqY8GVmwIh/9EEs6aK87aIZ95ZpmY rwFOTohcilojmm+m8cRGfrFAvWg5OS6C1tGXHySC2TRasfs+Ed+vaoVAka/ZnEnsTLtRj6c3kmHP PpANep2RsKaEQ03w95X44JFi2huX4Y2noKIff0O6qoZdeTNJezGEJBUzMcCVdmYxqaT79LS/E5Ux td+lwZizypVVQWYTlTHMDaPPeYtFsap8LG3aw5tx6pKNxjs6PaKTffVvgjT3khyLG8b8Ou/MCiqL Mmij95shFu4BggdqTu98cyknrmMhdrCd7E6kr1nxa43DrgVnlLuvKWy9AUqDXsPhidoyabghp+kS egyzg9gzmykbh82YqqK+7TGJC/nsyT32R57Nhw5cAOkq2mpyZo3R//YIu3nhKiaqb9/zt2a07orL 2uV+KAhKlpxD5m3naepYSe0pfJp6ZQbeT85KCNNerJW3+VU/JtjTgFVDHzb2B4CW+SGzCRZvbcAR kEzwbhTuuNvyTVp/eKytCVaAjSDi4Ho/Hv9/dRJCEWvAet9c4jnp8p3pWH4B+i/vTcLY8oxVnaZh ce9PlvqyRYvN4CeePI6kae1xu3/r+38/7u6ML/fAhnsNN66vRf3JqTgmCBM97DWUm3gLUngLYLeX 9sYih9DnK8bOu30AXSotB+fOmY6ApVsaC6rq77xfQg0uxV3NUNBe0D/Rn/F3ezh0O/0YNspUFkq8 cdacrPMHvbEeyFXlcICEggw3EkHB12ADzSnhXJqomZJG+jAsgERQ06IbDeANR7uDG2bCYasSzHci hTUsPZiOzKUvoS5B4yyVe9aHK86KHSyTJXaGc8ddy10bX1s/Vbr7qPrkX097SyB0Ak0uRiWfwDJB kCUXh5DMb6gLUrRxzyzIdB6DCjkHd8C9A7h8t4ILaQDo7u1WU75UHiqC2AgQa3xcwqGbx4on4ebv PSWdHR8y8RXQXuaR3hTZel6GXURStk9PaVz1zewULL1jKeCaEUQVFkFkeKimhmXfe/sVoEoRN1Jv LTAXwTtDu2x+3UcFSg3CBVx4SsYCv/X/uCjQrykJaffTJ5qOMN983vhBX7tr7OutBkQZ8FTWzhWn 5Pio3GPKrnC6jTAx5apL2wVuRzJVPCqllutF078yktI/t60syklW/Vl8ENJhM/TAFGAVEMkDrS8i TBK+81/ilK+URjQumb88oL0no4+BqF9UBKMeZYuKBSTyiOdF312RLolsj1cEMDryCscCoNw07GXZ qUiqGKQpmAMlhx8xdmRAXe0NWO9Fzv3wCNe6V1C1fMv3+mNtB3dEHvDyfV1oftnoAAzOeSkzAp7g 3qfzKd0vQRhi0J0GICDVPZZwnNXuAtNMkkMw0M7KxE6n9IRCDCSq3h+rcSKTa2qy2ATpC0er6DPY IWQxXwCgJBm1w6sjUibxNBGKqYIV3fDlnTfVvxWdt+SXVbCwZaH4LayNwM6n+xU2QeZo0b3iD507 snNSHz0lYzMGTVnXLLB9zoLmjtmeUScLFb5yuzwxk1jq3pzPdG0/50N0bxBHkRHofttB6F7CUsnP r0qjykFFaMVKeLMGznusZAmyl4ThODmgJC7Cjr2hmCEqiZvomDQtHzxuO5MOQQs43ljQsxD1vgls TcDwWejOpetivlHd709NzHLxHBHFES+Cef3flgbU6IjA4EfSNzXkjbY/I0eia4O0adkpFqKVf79E WNxfrJZyorgK7P2ixpW+V/lTPSXnJN2eeSFJ4LsClyX62R5HjRwgaEpCumyjayHHFOyYqbwAOtl/ W3J6KTWBwba1X1GyYRP2NxajfADjSdrn3VP/RwPNszM1v06nGr3OaByKbCpID6TEtx9h1qsLwye1 TtXxMkiwWrpph/U66NVxMAHB/QmqqnGexXKNqZ/T9J338iLWm4R7UCBH9JCeYTNucLY4ftG+sDhN FV2aG2ol2RtxoznrogF/vAK6UWn7ccguPF8ItRUtzmMvsYK+i/ISu/iuFR38TIZDj0qn3QrYYrh6 r7I9AjsSE68xqwYTnGmobk/s4k4z0aCG+n2wecvdNDjbvgYg1iHCz8OLHo/s6QkjMTQXxA8sd5lO qnAjUpwduHgoeosZD1eFRKl3SCiOWNMNdAcyh9GDVsOi2U5+5cOIlBT2EXrNy0LKtto3GQwk0no9 BrtHebT1jqmzlQK6U/KWbp4TcK4OkM84a05359Y2C9V6WdxQraFZ5i6Yj9u9xFjjHIu/DQOz7iKi I9aduq4c+qx/u5i52c4Y923S65rd7Kzv4OKjSZa42FQ2ZpREzQgSLIYWIiTP2+wv0Tx+SnAcQG/Y vXsOD7c0va/scnZJiWg1H0Ce1S8fBuDDhyZq+RNzRqlCOY6Hew1D+9h26eFWM0rnLcKz3D65E4JP vkrxM8zihQgYo046SuTJLW5sTmFXrYSVJS/iY3cLKFZdRz3csApg//FD647x+OChGYOhj6MQxAb8 WgDanwrSsz3qNDpxi8guIMF3PvMVacz2sEBxdTSx6xAvTC17qgnCfO5/aGig5KxKkpGXJMPsaSeR juFAKgmBzlh2TEqG41mQzYRfA5t3uds5wehbE3barYJXQd08dOXB0i10jBrnTj9Jabb2a7DPBJvQ W4hIlSF3ZiNnWlzbvT0POs4PwHnZE9nSR0RXdfWz9h5LH/zTBOQAR4lPhhNJZ7TbsBDF8qQfqnfj pmlB27yw8M+HYoJMtYQsqzF4YU31aevF/Bu1T/33hUG1xRv4OYS3voNN78CIq0v8pO0Cl1b20/zX CSYi8aOC6/9uswwK8UQ0p+M425gSVp0dYWT+HepCU3MjilwD2mKfIGLF1BY6pnnUQJllLDLVVtc6 tjkCDCI0o/KIRMGFDgc/y4DIobv370gcc+Opnt4itJk94XGNKTWp2SZuMTC/Lz3DFX7/cgx9MjgJ 1eab3mxLBvABEWeXdZqtxUAZdb1nv+EF66rCfX/c8aZT/yvaNBruvvzz53kQ+xdQx3RHJeha3G9Y zxH86gSM7LO9fZlPVxj7ugqaMwLuBT0hil+RDw9kpYlz2Ckno09xqD/p+QfSg4EPTIsyklHRDKf5 txV0Sf2ZSWB4VMRRQxLMwj/GFUxgKaRUbtZP5Z0sx0m0RG7p82+uqGIsUX1lwqT1/GAlPacWeBnZ kNu35HeAUWj/DR3YwyPV3w+bdt/Hr6DGJtJOsrzQexahVnGueBDF6vSGEYTGJcy76y0mM8eVHgLg +9WPzaRiDHqg58dVSVzDjpff39vRRPOSz3je04++Fju5BL72ix5jvpIQ85wfNLcTgnv08m15M/u5 DkjTeMGgt8q50s5q9kfBmr65eEkdjz2IuFqVwdZQK5fIUWCKNDRNQEQSoLcZL5lzBcbKEM1TgYaK 4C8mQkYJQVtGlLM2Kb7aSfHHAgonrWgeyhVFmwnpjkPjJ2fLZ0oA4kO7TFP6kaEZXQGQt0eekZdU NgDbTrOtX5CK6dutgfNb3jhmljk97SDiwCFad0Cgy72pFybaCyPnbj7e61kXv7bHh1TnQosd0wtT 7Qn/BPBROxHnDo60zo2VDQhQrXQr0Lv12ullur8xYTT2FEEEcUGVolCvtSYOzi7iPCrKmJvx9CkC CQK1nYJxRErHxmEiLPWcNnQmUQ0/hxGTgH8BeQg6U0uOjsV1ea7Y2jeOad9Z3Z0wlszhQhh8lMlO ElSW0lXtw9vPFQWjeI4Km56Dxro2si2sOKcVhLsVID9PYGGJq/OWACth84pC274o0+UtzaSEJDtC 1lF+svN45aVaNWi5PKZKPUbySDLzR1XCj3M28pYh1SCUOmJ8zApMq6WR7lNphTYYkk8QNX5j8cps cag33nvrPrkomfFQ2gXuHdOVeMn/RNNjH6RxkUgZiNVKf6fY1QD5WZptMMCLwKpa3/QFnQaKQNGY cQDd7FdmQK54bUYg7lOeMmNfs7szw4j10LuiPZ+VotziHt03l0Q8sE5Z5iMfMzukGCpB6pFEfEFG k116kooduhycYflubTOwvBKfDSpEGCUAcUSXltWDUILc118wph2Fv05oAFZNkgk2uaZFrWLuGiBc GuCwfdKckE0p9V22jvPJwJGaQNRknA9YqCu9wFbIEVTDm2adwH8Z+BfLdGNBPFG6bF7wkchhzDz6 jnytoWxreHpv19fG7LFfln59bigfDYw7Z3kboSN4yXABFfo1o0/UVQ27HsDWDeLy/7HJhFYTcqa2 TXw2AqtT5YS6cbhTFkRwqPQ/iygru1AoxNjrozYuhrfVzSJRArSb+gmiZ6Cb4gB8VwffNL/FlEaL 5Ohp90ULZFSRPAfMCIAUVigEl3MD2IWLHD0owZaK9TEiiFdBksdYCWZMQEGuxy/IXdWoqgH8tmRE nySdxs5cSZMhfNa4Nd9xJDoLQqEjM/UJlSENZscHxRCqL5VT5TZ41pWeAaIDP5Q4svXHdHSExRs+ X/PSZCHfl0KFXWq0LUqO+nOLekQkJVfqAkplv/L8XCFuUkMc80z10ULNWJv8fJyVfvykTGwajEoU TzozfcWodQg1Sfkvod84ZrD/BginpRjseGAjpDHwCTC7Y8cbLipQrBrKCafMictnRtUjSPCc8OLY ggV6P4RFNXWsEkDjjVJS7YSKSS9s48r1Oq35+DpHDmIZZeiTmam0XykS+u/IQ0AJQhOambHp+rLc 7aX0Mpdpsb1kxeX5ZvOpKLTGzlxcVbuo31/ky185GmdHg7Gzq8cdTn5t4GgylmbYY6xIv5H0RprN 7TKVg3GIPD/TQhww2xhJfb2RFA98vVbZuk0E+3dv3OZCjTMVlCu4+VGftjw1HUP+ts3QOu90uJrO LTkuQ8QaA6Cj5tbt57cIMW1TQMs90uQnj9Q5dmVEUhFZbYKxINhSrJ6Aoip5qtId2jlxHFCfmgPM YITsv7NDFANve8d0mYtbaSIgHVhWp3HhS/CIwM57gMpYdRmkT5JV3ULOkAlNUVI+Qo/JmhEuqP9x Tb1kLxNZamiVKmJoG1thFXopl7aQW/vDr6eOiM+v8T6iYMGoTP5vUQKFHjoKIrj3xq3w84txIyrU J6y4E5ar3T7bQwphDJdc3+Egi4Ko2ntyOce38V/KsqjZKBqggbK2eRw8zGnbFmhIEnS+o1znUBiN 4wMS6snGWjlgtWBv80DdeLZYW323nohx37dx/l46KizQUc6Sp21wnGjVHC3mmmtLHTpWKjR5iQ/J /VAHbNV+2yJKKntLXLvsz4CN9VblmM/iFegv+WrmhZNcJ9g+LPym8X7y+Fg8UVYVprCvhDB2q6zi cMYwML14sNLR1BzyJK7miZu+nukmLtbzSqvtkfWZWk1SRm3TOyk6meh9EQO1IQqWwxQ7l39ctVmI ZxXMSrw10CDXlIBAhR8YwNizQB/1D8fJskvHaicoz1vOZLiee3SPi0AyQDg5FUhi+IqvS9iManf9 aeksg+3llpsjGs41dCfV8r5TMTRV26HdELuFEHV8eebCyYkCSndPHw0hJuTtHW8ZK+YcxJLYvZ1I vb8NRUK1s74IMFK7VrvX8zebRw0LziFK03Iwi8ObRs9H41nanHyFltE/1U91827xgYZgxnRC2/Uv MmHimiHMnum5ySRhbbnPVrwM62ZZNJf4+M8ivxKhAE/AI2jDPpcVjfWo2nPubmy1FnWClsL+vDdP s2+cD5gtso9EttP060RmDa7VXvLD7zsqrBdPbIPIrtMpTedYIotrMTq7iqYq1pXA9Lqlstbnqwl6 gm0oUn1kZWga9fzaB6BwwR8ZX/yPYPGkOt39PNCE+ekmVnTKTa9RoFmqrs6p4mEwdwWNmzm1lg0f IYzpwqvdjWe5Gc7uygF9ZdgS2dcsXlVML1cwzxIoCWX/fWvpuRV6RqQn1uAV5ie5bp1oC6v99vnF UGyM5MJ8EZJJySvhCaPMOT85FjYiV9GIsS8adTsL3LagJ/Rsbg/fqfO0S53OT8D36V+m3V2eXlSw efqrptcs/9p+L9gnLSfWu5hnwgLoF3KDnOOABwuZgCQWSGQVpTL7c5Hg7k4V2FWAoZ481nVqXqLu cTVkbZsD/bZOrAVXghAz+/egttOt8iKvxTuvfjSnB6vaPjhWBZ9OVkM5GAHL/JMDyIGL5w5a92ee 0b6vqcoiOoYEAJ//m/3ckm3bcDJqnWmhfoKf+fI7a+E0An6/8E22zC/fUh9oNN/hd1g9DNLH3r7D PV6OuON5E0Rr4MzmkqgxKSAAUWPSw61M3c8qnQeZR1ahkc7ZeddaCRLPmNHcpxEKbIq5WHaQRcXT qbb1jB4XP7eY5/uO/Ye3ecYYlWJBWqVpqQ4ovB5hTYNnWNpXsdqjsMKHCE9WnBWLz1FTFi5D64yU NwEhGOKmxBbQ+HqcFMJGFNtIGrhgPP8s0/GaJu8iAwwIfJ+2/pU2hzam0CMpPVEcSRaL0KYVs6Vc jgSyN8/luKceJVeWHVfP9y0h8B6p8cwytqJfBeGsDvJxrKhKsnpocee0w0UieNgxXEQRpG1ZUO/p MToQldM/MENm2Oe1FPMhVODawZpCtcHyvJ8s36ytKotowCWSAlfRpftOgZpFx86/vkUONvOE3Nz4 8ykLS09g/rrw07h9KhOsrvINFVio5fdD64VBpgdsomc3u2aZ594eOXafzAvGM5LrEZ1vlNdLavSh asVwoXfpHW0wHKu1hCHNmAVpZ8k/WACAEsHlo7gd+o88mnTHB6Ci7G3Sv6Y/ZsGbAb0FkP310mFl bl0Sq7LgeCF6jCLumKNhEo4TETgnpg/FS0BwIER5ndeDzpPPtsXIzAXptkiMqvyXSbBGFKI6mBCO XhTRg441eRUB/VrpoLJ/yAcJhja9uY2qYWek8xnn5kfY7s4+gyvIe1D1CfiZQhHPSKoNLbj0YObt 86pwOVONx+SIoEoH7xMyCZcvvwrC3tp0hEuxnCSHSnhE2L4LimHzJaUoFaIngURc+gcb84VD6hFT +9gwqDkh3mk8WH5yNIrW2t+JT+YuG+iPJQBJmL4B1+zA+WWSSh/CoW8ikccgSJICA8PeDs1W+NJk U+brh4F28VayIGC7+8OfiJ3hFVlSqMAgAG3DQHfC1yQVl9n0YisYdMub7WA9ljEGCEae44Q/fh5C 4YDp/+Kw5+kBsQS/SHgjB0P7yN7AOLIaD+jyFNcdlsJZS0u/+uymb4aEgBVoPFUjEBaylbY/33fY Z/eflMBe328VZ+h8td7mFSg+arD3KXUpnqi9N6597D9r2afvSCpoyKvpckmnDFoNZEafNWpmv/XX Gq3odhe2w1UKetRVirkZqUAB6W4aXpwRw9wbNI06GvxgPSnaAzJ6ynusvtAHOFiq66VatonfP1B7 HYpXeqWnRhZgNdsV9GDsU30HxtXLR0kZJ2GCt79nmQ/oTxH3HDx35dZQFieDfN6cC4iuPltoyWdm 2XEYYOkcUmmX5vGgDosTGenOeV9c+it02Y6tAfJHMSHeoEXyLaKyGiuMJ85DMZyp9bEfAgjYWHhr 9xpLLSbMenYlUqSZwjlw8oF/BF8Z7gTthj+KsqAfAUJ0s/4WAVKqE1yyFsxJcNB+63KA3GnIWuCT +SqsXxiLNQzXcUPIqewJWZGavKappfYNATJ7awQzTjHKkjRlTLlQ4pFaZDUiyT4Q71XZJDdwEoLs HLzFSN8yZSVnyimyw6NQyT6GuOBI09/BiFzQhKyJcIsRK9V72+zBniXjafYAU6VOu7T24Di835a+ Ukn7ewwh25WxrTYYA8epIEsLoKbhceR1oK0yQb+OqufleJHwswrfW757UJclmLPNWVGOCZgVby28 cxJvqgzas4JCS7odvnOwzuI3fTElIYdokWp1owavYOtJpES1EEesh3ZJFEujCK+3oy3H+eB3pa4t Kwja0zyxKLT06xsg7fLKBtqsyELNLLodF3TQQRN8ctZ50IMU `protect end_protected
gpl-3.0
9c7ed6f8ff4d62164d45d29dc4012a7b
0.948195
1.839881
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/adc/AD9634.vhd
1
2,312
--***************************************************************************** -- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved. -- Module name : AD9634 -- Call by : -- Description : this module is the top module of AD9634. -- IC : 5CGXFC7D7F31C8N -- Version : A -- Note: : -- Author : Peitian Mu -- Date : 2013.11.29 -- Update : --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity AD9634 is port ( I_adce_clk : in std_logic; I_adce_d : in std_logic_vector(5 downto 0); I_adce_or : in std_logic;--LVDS O_adce_csb : out std_logic; O_adce_sdio : out std_logic; O_adce_sclk : out std_logic; O_adce_data : out std_logic_vector(11 downto 0) ); end AD9634; architecture rtl of AD9634 is component ADC_DDIO port( datain : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; dataout_h : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); dataout_l : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); end component; signal S_adc_ad_12 : std_logic_vector(11 downto 0); begin U0_ddio_in: ADC_DDIO port map( datain => I_adce_d, inclock => I_adce_clk, dataout_h => S_adc_ad_12(11 downto 6), dataout_l => S_adc_ad_12(5 downto 0) ); process(I_adce_clk) begin if rising_edge(I_adce_clk) then O_adce_data(11) <= S_adc_ad_12(11); O_adce_data(10) <= S_adc_ad_12(5); O_adce_data(9) <= S_adc_ad_12(10); O_adce_data(8) <= S_adc_ad_12(4); O_adce_data(7) <= S_adc_ad_12(9); O_adce_data(6) <= S_adc_ad_12(3); O_adce_data(5) <= S_adc_ad_12(8); O_adce_data(4) <= S_adc_ad_12(2); O_adce_data(3) <= S_adc_ad_12(7); O_adce_data(2) <= S_adc_ad_12(1); O_adce_data(1) <= S_adc_ad_12(6); O_adce_data(0) <= S_adc_ad_12(0); end if; end process; end rtl;
apache-2.0
b28468c3cedcccef8a43628d208a7516
0.454152
2.911839
false
false
false
false
Given-Jiang/Binarization
Binarization_dspbuilder/hdl/Binarization_GN_Binarization_Binarization_Module.vhd
2
32,131
-- Binarization_GN_Binarization_Binarization_Module.vhd -- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Binarization_GN_Binarization_Binarization_Module is port ( Clock : in std_logic := '0'; -- Clock.clk aclr : in std_logic := '0'; -- .reset data_out : out std_logic_vector(23 downto 0); -- data_out.wire addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire eop : in std_logic := '0'; -- eop.wire sop : in std_logic := '0'; -- sop.wire writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire write : in std_logic := '0' -- write.wire ); end entity Binarization_GN_Binarization_Binarization_Module; architecture rtl of Binarization_GN_Binarization_Binarization_Module is component alt_dspbuilder_clock_GNQFU4PUDH is port ( aclr : in std_logic := 'X'; -- reset aclr_n : in std_logic := 'X'; -- reset_n aclr_out : out std_logic; -- reset clock : in std_logic := 'X'; -- clk clock_out : out std_logic -- clk ); end component alt_dspbuilder_clock_GNQFU4PUDH; component alt_dspbuilder_cast_GNKXX25S2S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNKXX25S2S; component alt_dspbuilder_port_GNEPKLLZKY is port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_port_GNEPKLLZKY; component alt_dspbuilder_multiplexer_GNCALBUTDR is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; use_one_hot_select_bus : natural := 0; width : positive := 8; pipeline : natural := 0; number_inputs : natural := 4 ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire result : out std_logic_vector(23 downto 0); -- wire ena : in std_logic := 'X'; -- wire user_aclr : in std_logic := 'X'; -- wire in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_multiplexer_GNCALBUTDR; component alt_dspbuilder_gnd_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_gnd_GN; component alt_dspbuilder_vcc_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_vcc_GN; component alt_dspbuilder_constant_GNZEH3JAKA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNZEH3JAKA; component alt_dspbuilder_port_GN6TDLHAW6 is port ( input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_port_GN6TDLHAW6; component alt_dspbuilder_constant_GNNKZSYI73 is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNNKZSYI73; component alt_dspbuilder_constant_GNLMV7GZFA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNLMV7GZFA; component alt_dspbuilder_if_statement_GNYT6HZJI5 is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GNYT6HZJI5; component alt_dspbuilder_delay_GNUECIBFDH is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNUECIBFDH; component alt_dspbuilder_port_GN37ALZBS4 is port ( input : in std_logic := 'X'; -- wire output : out std_logic -- wire ); end component alt_dspbuilder_port_GN37ALZBS4; component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is generic ( LogicalOp : string := "AltAND"; number_inputs : positive := 2 ); port ( result : out std_logic; -- wire data0 : in std_logic := 'X'; -- wire data1 : in std_logic := 'X' -- wire ); end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V; component alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNSCEXJCJK; component alt_dspbuilder_delay_GNHYCSAEGT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNHYCSAEGT; component alt_dspbuilder_delay_GNVTJPHWYT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNVTJPHWYT; component alt_dspbuilder_if_statement_GN7VA7SRUP is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GN7VA7SRUP; component alt_dspbuilder_port_GNOC3SGKQJ is port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_port_GNOC3SGKQJ; component alt_dspbuilder_decoder_GNM4LOIHXZ is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNM4LOIHXZ; component alt_dspbuilder_cast_GN7PRGDOVA is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_cast_GN7PRGDOVA; component alt_dspbuilder_cast_GNSB3OXIQS is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire output : out std_logic -- wire ); end component alt_dspbuilder_cast_GNSB3OXIQS; component alt_dspbuilder_cast_GN46N4UJ5S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic := 'X'; -- wire output : out std_logic_vector(0 downto 0) -- wire ); end component alt_dspbuilder_cast_GN46N4UJ5S; signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> Decoder:data signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast2:input] signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion:input, Decoder1:data, If_Statement1:a, Multiplexer:in0] signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> If_Statement:b signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0 signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator:data1] signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0 signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0 signal write_0_output_wire : std_logic; -- write_0:output -> Logical_Bit_Operator2:data1 signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1 signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast4:input] signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0 signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1 signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> Multiplexer:in1 signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> cast0:input signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Bus_Conversion1:input signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast1:input signal cast1_output_wire : std_logic; -- cast1:output -> Delay:sclr signal cast2_output_wire : std_logic; -- cast2:output -> Delay:ena signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast3:input signal cast3_output_wire : std_logic_vector(0 downto 0); -- cast3:output -> Delay4:input signal cast4_output_wire : std_logic; -- cast4:output -> Logical_Bit_Operator1:data1 signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast5:input signal cast5_output_wire : std_logic_vector(0 downto 0); -- cast5:output -> Delay1:input signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast6:input signal cast6_output_wire : std_logic_vector(0 downto 0); -- cast6:output -> Multiplexer1:sel signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer:aclr] signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay:clock, Multiplexer1:clock, Multiplexer:clock] begin clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH port map ( clock_out => clock_0_clock_output_clk, -- clock_output.clk aclr_out => clock_0_clock_output_reset, -- .reset clock => Clock, -- clock.clk aclr => aclr -- .reset ); bus_conversion1 : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => cast0_output_wire, -- input.wire output => bus_conversion1_output_wire -- output.wire ); writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY port map ( input => writedata, -- input.wire output => writedata_0_output_wire -- output.wire ); multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => delay_output_wire, -- sel.wire result => multiplexer_result_wire, -- result.wire ena => multiplexerenavcc_output_wire, -- ena.wire user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire in0 => data_in_0_output_wire, -- in0.wire in1 => multiplexer1_result_wire -- in1.wire ); multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexeruser_aclrgnd_output_wire -- output.wire ); multiplexerenavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexerenavcc_output_wire -- output.wire ); bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion_output_wire -- output.wire ); constant4 : component alt_dspbuilder_constant_GNZEH3JAKA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000001111", width => 24 ) port map ( output => constant4_output_wire -- output.wire ); addr_0 : component alt_dspbuilder_port_GN6TDLHAW6 port map ( input => addr, -- input.wire output => addr_0_output_wire -- output.wire ); constant3 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant3_output_wire -- output.wire ); constant2 : component alt_dspbuilder_constant_GNLMV7GZFA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "111111111111111111111111", width => 24 ) port map ( output => constant2_output_wire -- output.wire ); if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5 generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "a>b", number_inputs => 2, width => 8 ) port map ( true => if_statement_true_wire, -- true.wire a => bus_conversion_output_wire, -- a.wire b => delay3_output_wire -- b.wire ); constant1 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant1_output_wire -- output.wire ); delay : component alt_dspbuilder_delay_GNUECIBFDH generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "0", width => 1 ) port map ( input => delay4_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay_output_wire, -- output.wire sclr => cast1_output_wire, -- sclr.wire ena => cast2_output_wire -- ena.wire ); write_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => write, -- input.wire output => write_0_output_wire -- output.wire ); logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator3_result_wire, -- result.wire data0 => sop_0_output_wire, -- data0.wire data1 => decoder1_dec_wire -- data1.wire ); eop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => eop, -- input.wire output => eop_0_output_wire -- output.wire ); logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator2_result_wire, -- result.wire data0 => decoder_dec_wire, -- data0.wire data1 => write_0_output_wire -- data1.wire ); logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator1_result_wire, -- result.wire data0 => eop_0_output_wire, -- data0.wire data1 => cast4_output_wire -- data1.wire ); decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK generic map ( decode => "000000000000000000001111", pipeline => 0, width => 24 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => data_in_0_output_wire, -- data.wire dec => decoder1_dec_wire, -- dec.wire sclr => decoder1sclrgnd_output_wire, -- sclr.wire ena => decoder1enavcc_output_wire -- ena.wire ); decoder1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder1sclrgnd_output_wire -- output.wire ); decoder1enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder1enavcc_output_wire -- output.wire ); logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator_result_wire, -- result.wire data0 => if_statement1_true_wire, -- data0.wire data1 => sop_0_output_wire -- data1.wire ); delay4 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast3_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay4_output_wire, -- output.wire sclr => delay4sclrgnd_output_wire, -- sclr.wire ena => delay4enavcc_output_wire -- ena.wire ); delay4sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay4sclrgnd_output_wire -- output.wire ); delay4enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay4enavcc_output_wire -- output.wire ); delay3 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => delay2_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay3_output_wire, -- output.wire sclr => delay3sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator3_result_wire -- ena.wire ); delay3sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay3sclrgnd_output_wire -- output.wire ); if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "(a=b) and (a /= c)", number_inputs => 3, width => 24 ) port map ( true => if_statement1_true_wire, -- true.wire a => data_in_0_output_wire, -- a.wire b => constant3_output_wire, -- b.wire c => constant4_output_wire -- c.wire ); sop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => sop, -- input.wire output => sop_0_output_wire -- output.wire ); multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => cast6_output_wire, -- sel.wire result => multiplexer1_result_wire, -- result.wire ena => multiplexer1enavcc_output_wire, -- ena.wire user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire in0 => constant1_output_wire, -- in0.wire in1 => constant2_output_wire -- in1.wire ); multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexer1user_aclrgnd_output_wire -- output.wire ); multiplexer1enavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexer1enavcc_output_wire -- output.wire ); delay1 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast5_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay1_output_wire, -- output.wire sclr => delay1sclrgnd_output_wire, -- sclr.wire ena => delay1enavcc_output_wire -- ena.wire ); delay1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay1sclrgnd_output_wire -- output.wire ); delay1enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay1enavcc_output_wire -- output.wire ); delay2 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => bus_conversion1_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay2_output_wire, -- output.wire sclr => delay2sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator2_result_wire -- ena.wire ); delay2sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay2sclrgnd_output_wire -- output.wire ); data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => multiplexer_result_wire, -- input.wire output => data_out -- output.wire ); data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => data_in, -- input.wire output => data_in_0_output_wire -- output.wire ); decoder : component alt_dspbuilder_decoder_GNM4LOIHXZ generic map ( decode => "01", pipeline => 1, width => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => addr_0_output_wire, -- data.wire dec => decoder_dec_wire, -- dec.wire sclr => decodersclrgnd_output_wire, -- sclr.wire ena => decoderenavcc_output_wire -- ena.wire ); decodersclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decodersclrgnd_output_wire -- output.wire ); decoderenavcc : component alt_dspbuilder_vcc_GN port map ( output => decoderenavcc_output_wire -- output.wire ); cast0 : component alt_dspbuilder_cast_GN7PRGDOVA generic map ( round => 0, saturate => 0 ) port map ( input => writedata_0_output_wire, -- input.wire output => cast0_output_wire -- output.wire ); cast1 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay1_output_wire, -- input.wire output => cast1_output_wire -- output.wire ); cast2 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay4_output_wire, -- input.wire output => cast2_output_wire -- output.wire ); cast3 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator_result_wire, -- input.wire output => cast3_output_wire -- output.wire ); cast4 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay_output_wire, -- input.wire output => cast4_output_wire -- output.wire ); cast5 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator1_result_wire, -- input.wire output => cast5_output_wire -- output.wire ); cast6 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => if_statement_true_wire, -- input.wire output => cast6_output_wire -- output.wire ); end architecture rtl; -- of Binarization_GN_Binarization_Binarization_Module
mit
11c67a220c2bd354293216581c97c6ed
0.560144
3.391493
false
false
false
false
grwlf/vsim
vhdl_ct/ct00085.vhd
1
70,077
-- NEED RESULT: ARCH00085.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P3: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P4: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P5: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P6: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P7: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P8: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P9: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P10: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P11: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P12: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P13: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P14: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P15: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P16: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085.P17: Multi transport transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00085 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00085(ARCH00085) -- ENT00085_Test_Bench(ARCH00085_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00085 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_bit_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_int1_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_phys1_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_real1_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_st_boolean_vector : inout st_boolean_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_boolean_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_boolean_vector (lowb+1 to lowb+3) <= transport c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P1" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_boolean_vector (lowb+1 to lowb+3) <= transport c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_boolean_vector (lowb+1 to lowb+3) <= transport c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_boolean_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_st_bit_vector : inout st_bit_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_bit_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_bit_vector (lowb+1 to lowb+3) <= transport c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P2" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_bit_vector (lowb+1 to lowb+3) <= transport c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_bit_vector (lowb+1 to lowb+3) <= transport c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_bit_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_st_severity_level_vector : inout st_severity_level_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_severity_level_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_severity_level_vector (lowb+1 to lowb+3) <= transport c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P3" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_severity_level_vector (lowb+1 to lowb+3) <= transport c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_severity_level_vector (lowb+1 to lowb+3) <= transport c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_severity_level_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_st_string : inout st_string ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_string : out chk_sig_type ) is begin case counter is when 0 => s_st_string (lowb+1 to lowb+3) <= transport c_st_string_2 (lowb+1 to lowb+3) after 10 ns, c_st_string_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P4" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_string (lowb+1 to lowb+3) <= transport c_st_string_2 (lowb+1 to lowb+3) after 10 ns , c_st_string_1 (lowb+1 to lowb+3) after 20 ns , c_st_string_2 (lowb+1 to lowb+3) after 30 ns , c_st_string_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_string (lowb+1 to lowb+3) <= transport c_st_string_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_string <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_st_enum1_vector : inout st_enum1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_enum1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_enum1_vector (lowb+1 to lowb+3) <= transport c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P5" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_enum1_vector (lowb+1 to lowb+3) <= transport c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1_vector (lowb+1 to lowb+3) <= transport c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_st_integer_vector : inout st_integer_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_integer_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_integer_vector (lowb+1 to lowb+3) <= transport c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P6" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_integer_vector (lowb+1 to lowb+3) <= transport c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_integer_vector (lowb+1 to lowb+3) <= transport c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_integer_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- procedure Proc7 ( signal s_st_int1_vector : inout st_int1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_int1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_int1_vector (lowb+1 to lowb+3) <= transport c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P7" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_int1_vector (lowb+1 to lowb+3) <= transport c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1_vector (lowb+1 to lowb+3) <= transport c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc7 ; -- procedure Proc8 ( signal s_st_time_vector : inout st_time_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_time_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_time_vector (lowb+1 to lowb+3) <= transport c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P8" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_time_vector (lowb+1 to lowb+3) <= transport c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_time_vector (lowb+1 to lowb+3) <= transport c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_time_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc8 ; -- procedure Proc9 ( signal s_st_phys1_vector : inout st_phys1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_phys1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_phys1_vector (lowb+1 to lowb+3) <= transport c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P9" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_phys1_vector (lowb+1 to lowb+3) <= transport c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1_vector (lowb+1 to lowb+3) <= transport c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc9 ; -- procedure Proc10 ( signal s_st_real_vector : inout st_real_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_real_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_real_vector (lowb+1 to lowb+3) <= transport c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P10" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real_vector (lowb+1 to lowb+3) <= transport c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_real_vector (lowb+1 to lowb+3) <= transport c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc10 ; -- procedure Proc11 ( signal s_st_real1_vector : inout st_real1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_real1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_real1_vector (lowb+1 to lowb+3) <= transport c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P11" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real1_vector (lowb+1 to lowb+3) <= transport c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1_vector (lowb+1 to lowb+3) <= transport c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc11 ; -- procedure Proc12 ( signal s_st_rec1_vector : inout st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec1_vector (lowb+1 to lowb+3) <= transport c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P12" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec1_vector (lowb+1 to lowb+3) <= transport c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1_vector (lowb+1 to lowb+3) <= transport c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc12 ; -- procedure Proc13 ( signal s_st_rec2_vector : inout st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec2_vector (lowb+1 to lowb+3) <= transport c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P13" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec2_vector (lowb+1 to lowb+3) <= transport c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2_vector (lowb+1 to lowb+3) <= transport c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc13 ; -- procedure Proc14 ( signal s_st_rec3_vector : inout st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec3_vector (lowb+1 to lowb+3) <= transport c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P14" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec3_vector (lowb+1 to lowb+3) <= transport c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3_vector (lowb+1 to lowb+3) <= transport c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc14 ; -- procedure Proc15 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector (lowb+1 to lowb+3) <= transport c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P15" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr1_vector (lowb+1 to lowb+3) <= transport c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector (lowb+1 to lowb+3) <= transport c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc15 ; -- procedure Proc16 ( signal s_st_arr2_vector : inout st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr2_vector (lowb+1 to lowb+3) <= transport c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P16" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr2_vector (lowb+1 to lowb+3) <= transport c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector (lowb+1 to lowb+3) <= transport c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc16 ; -- procedure Proc17 ( signal s_st_arr3_vector : inout st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr3_vector (lowb+1 to lowb+3) <= transport c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00085.P17" , "Multi transport transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr3_vector (lowb+1 to lowb+3) <= transport c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector (lowb+1 to lowb+3) <= transport c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00085" , "One transport transaction occurred on signal " & "asg with slice name on LHS", correct ) ; test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00085" , "Old transactions were removed on signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc17 ; -- -- end ENT00085 ; -- architecture ARCH00085 of ENT00085 is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_boolean_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_st_boolean_vector, counter, correct, savtime, chk_st_boolean_vector ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_bit_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_bit_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_bit_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_st_bit_vector, counter, correct, savtime, chk_st_bit_vector ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_severity_level_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_st_severity_level_vector, counter, correct, savtime, chk_st_severity_level_vector ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_st_string ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_st_string, counter, correct, savtime, chk_st_string ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_st_enum1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_st_enum1_vector, counter, correct, savtime, chk_st_enum1_vector ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_st_integer_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_st_integer_vector, counter, correct, savtime, chk_st_integer_vector ) ; end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process ( s_st_int1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc7 ( s_st_int1_vector, counter, correct, savtime, chk_st_int1_vector ) ; end process P7 ; -- PGEN_CHKP_8 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process ( s_st_time_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc8 ( s_st_time_vector, counter, correct, savtime, chk_st_time_vector ) ; end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process ( s_st_phys1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc9 ( s_st_phys1_vector, counter, correct, savtime, chk_st_phys1_vector ) ; end process P9 ; -- PGEN_CHKP_10 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process ( s_st_real_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc10 ( s_st_real_vector, counter, correct, savtime, chk_st_real_vector ) ; end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1_vector = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process ( s_st_real1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc11 ( s_st_real1_vector, counter, correct, savtime, chk_st_real1_vector ) ; end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process ( s_st_rec1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc12 ( s_st_rec1_vector, counter, correct, savtime, chk_st_rec1_vector ) ; end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process ( s_st_rec2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc13 ( s_st_rec2_vector, counter, correct, savtime, chk_st_rec2_vector ) ; end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process ( s_st_rec3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc14 ( s_st_rec3_vector, counter, correct, savtime, chk_st_rec3_vector ) ; end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process ( s_st_arr1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc15 ( s_st_arr1_vector, counter, correct, savtime, chk_st_arr1_vector ) ; end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process ( s_st_arr2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc16 ( s_st_arr2_vector, counter, correct, savtime, chk_st_arr2_vector ) ; end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process ( s_st_arr3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc17 ( s_st_arr3_vector, counter, correct, savtime, chk_st_arr3_vector ) ; end process P17 ; -- -- end ARCH00085 ; -- entity ENT00085_Test_Bench is end ENT00085_Test_Bench ; -- architecture ARCH00085_Test_Bench of ENT00085_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00085 ( ARCH00085 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00085_Test_Bench ;
gpl-3.0
7e78986793d226596b8bf29e280539da
0.522682
3.702293
false
false
false
false
dcliche/mdsynth
rtl/src/Flasher.vhd
1
3,369
--===========================================================================-- -- -- -- LED Flasher -- -- -- --===========================================================================-- -- -- File name : flasher.vhd -- -- Entity name : flasher -- -- Purpose : Implements a long counter used to flash a LED -- to indicate code has loaded correctly -- -- Dependencies : ieee.std_logic_1164 -- ieee.numeric_std -- ieee.std_logic_unsigned -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- -- Copyright (C) 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Changes -- -- 0.1 John Kent 2010-08-28 Made separate module -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; --library unisim; -- use unisim.vcomponents.all; ----------------------------------------------------------------------- -- Entity for B3_SRAM -- ----------------------------------------------------------------------- entity flasher is port ( clk : in std_logic; -- Clock input rst : in std_logic; -- Reset input (active high) LED : out Std_Logic -- LED output ); end flasher; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for Flasher ------------------------------------------------------------------------------- architecture rtl of flasher is -- Flashing LED test signals signal countL : std_logic_vector(23 downto 0); begin -- -- LED Flasher to indicate code has loaded -- my_LED_Flasher : process (clk, rst, CountL ) begin if falling_edge(clk) then if rst = '1' then countL <= (others=>'0'); else countL <= countL + 1; end if; end if; LED <= countL(23); end process; end rtl;
gpl-3.0
0a59a85de372862b73e241254cb3e2b4
0.405462
5.135671
false
false
false
false
grwlf/vsim
vhdl_ct/ct00122.vhd
1
30,295
-- NEED RESULT: ARCH00122.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00122: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00122 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00122 -- PKG00122/BODY -- ENT00122(ARCH00122) -- ENT00122_Test_Bench(ARCH00122_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00122 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00122 ; -- package body PKG00122 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00122 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00122.all ; entity ENT00122 is port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00122 ; -- architecture ARCH00122 of ENT00122 is begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00122.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00122" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00122" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P6 ; -- -- end ARCH00122 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00122.all ; entity ENT00122_Test_Bench is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- end ENT00122_Test_Bench ; -- architecture ARCH00122_Test_Bench of ENT00122_Test_Bench is begin L1: block component UUT port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00122 ( ARCH00122 ) ; begin CIS1 : UUT port map ( s_r_st_arr1_vector , s_r_st_arr2_vector , s_r_st_arr3_vector , s_r_st_rec1_vector , s_r_st_rec2_vector , s_r_st_rec3_vector ) ; end block L1 ; end ARCH00122_Test_Bench ;
gpl-3.0
b3e2514a0b4b7291e3c8009b499cfd3b
0.532299
3.267717
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/system_dlmb_cntlr_wrapper.vhd
1
18,331
------------------------------------------------------------------------------- -- system_dlmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v3_10_c; use lmb_bram_if_cntlr_v3_10_c.all; entity system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end system_dlmb_cntlr_wrapper; architecture STRUCTURE of system_dlmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_FAMILY : string; C_MASK : std_logic_vector(0 to 31); C_MASK1 : std_logic_vector(0 to 31); C_MASK2 : std_logic_vector(0 to 31); C_MASK3 : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_ECC : integer; C_INTERCONNECT : integer; C_FAULT_INJECT : integer; C_CE_FAILING_REGISTERS : integer; C_UE_FAILING_REGISTERS : integer; C_ECC_STATUS_REGISTERS : integer; C_ECC_ONOFF_REGISTER : integer; C_ECC_ONOFF_RESET_VALUE : integer; C_CE_COUNTER_WIDTH : integer; C_WRITE_ACCESS : integer; C_NUM_LMB : integer; C_SPLB_CTRL_BASEADDR : std_logic_vector; C_SPLB_CTRL_HIGHADDR : std_logic_vector; C_SPLB_CTRL_AWIDTH : INTEGER; C_SPLB_CTRL_DWIDTH : INTEGER; C_SPLB_CTRL_P2P : INTEGER; C_SPLB_CTRL_MID_WIDTH : INTEGER; C_SPLB_CTRL_NUM_MASTERS : INTEGER; C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER; C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER; C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1)); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1)); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; begin dlmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00003FFF", C_FAMILY => "virtex5", C_MASK => X"80000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_NUM_LMB => 1, C_SPLB_CTRL_BASEADDR => X"FFFFFFFF", C_SPLB_CTRL_HIGHADDR => X"00000000", C_SPLB_CTRL_AWIDTH => 32, C_SPLB_CTRL_DWIDTH => 32, C_SPLB_CTRL_P2P => 0, C_SPLB_CTRL_MID_WIDTH => 1, C_SPLB_CTRL_NUM_MASTERS => 1, C_SPLB_CTRL_SUPPORT_BURSTS => 0, C_SPLB_CTRL_NATIVE_DWIDTH => 32, C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF", C_S_AXI_CTRL_HIGHADDR => X"00000000", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => LMB1_ABus, LMB1_WriteDBus => LMB1_WriteDBus, LMB1_AddrStrobe => LMB1_AddrStrobe, LMB1_ReadStrobe => LMB1_ReadStrobe, LMB1_WriteStrobe => LMB1_WriteStrobe, LMB1_BE => LMB1_BE, Sl1_DBus => Sl1_DBus, Sl1_Ready => Sl1_Ready, Sl1_Wait => Sl1_Wait, Sl1_UE => Sl1_UE, Sl1_CE => Sl1_CE, LMB2_ABus => LMB2_ABus, LMB2_WriteDBus => LMB2_WriteDBus, LMB2_AddrStrobe => LMB2_AddrStrobe, LMB2_ReadStrobe => LMB2_ReadStrobe, LMB2_WriteStrobe => LMB2_WriteStrobe, LMB2_BE => LMB2_BE, Sl2_DBus => Sl2_DBus, Sl2_Ready => Sl2_Ready, Sl2_Wait => Sl2_Wait, Sl2_UE => Sl2_UE, Sl2_CE => Sl2_CE, LMB3_ABus => LMB3_ABus, LMB3_WriteDBus => LMB3_WriteDBus, LMB3_AddrStrobe => LMB3_AddrStrobe, LMB3_ReadStrobe => LMB3_ReadStrobe, LMB3_WriteStrobe => LMB3_WriteStrobe, LMB3_BE => LMB3_BE, Sl3_DBus => Sl3_DBus, Sl3_Ready => Sl3_Ready, Sl3_Wait => Sl3_Wait, Sl3_UE => Sl3_UE, Sl3_CE => Sl3_CE, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, Interrupt => Interrupt, UE => UE, CE => CE, SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus, SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid, SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID, SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW, SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE, SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size, SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type, SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus, SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck, SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize, SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait, SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate, SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck, SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp, SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus, SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck, SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp, SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy, SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr, SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr, SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus, SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid, SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim, SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim, SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort, SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock, SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize, SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr, SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst, SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst, SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq, SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq, SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri, SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri, SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri, SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute, SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm, SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr, SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm, SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ, S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK, S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN, S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR, S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID, S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY, S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA, S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB, S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID, S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY, S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP, S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID, S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY, S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR, S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID, S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY, S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA, S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP, S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID, S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ); end architecture STRUCTURE;
lgpl-3.0
9f801fdc40f6c38e24e9e083af2336a0
0.615078
2.93296
false
false
false
false
grwlf/vsim
vhdl_ct/ct00553.vhd
1
5,009
-- NEED RESULT: ARCH00553: Signal declarations - scalar globally static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00553 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.2 (8) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00553) -- ENT00553_Test_Bench(ARCH00553_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00553 of GENERIC_STANDARD_TYPES is signal si_boolean_1 : boolean := c_boolean_1 ; signal si_bit_1 : bit := c_bit_1 ; signal si_severity_level_1 : severity_level := c_severity_level_1 ; signal si_character_1 : character := c_character_1 ; signal si_t_enum1_1 : t_enum1 := c_t_enum1_1 ; signal si_st_enum1_1 : st_enum1 := c_st_enum1_1 ; signal si_integer_1 : integer := c_integer_1 ; signal si_t_int1_1 : t_int1 := c_t_int1_1 ; signal si_st_int1_1 : st_int1 := c_st_int1_1 ; signal si_time_1 : time := c_time_1 ; signal si_t_phys1_1 : t_phys1 := c_t_phys1_1 ; signal si_st_phys1_1 : st_phys1 := c_st_phys1_1 ; signal si_real_1 : real := c_real_1 ; signal si_t_real1_1 : t_real1 := c_t_real1_1 ; signal si_st_real1_1 : st_real1 := c_st_real1_1 ; signal synch : boolean := false ; signal s_correct : boolean := true ; begin process variable correct : boolean := true ; begin correct := correct and si_boolean_1 = c_boolean_1 ; correct := correct and si_bit_1 = c_bit_1 ; correct := correct and si_severity_level_1 = c_severity_level_1 ; correct := correct and si_character_1 = c_character_1 ; correct := correct and si_t_enum1_1 = c_t_enum1_1 ; correct := correct and si_st_enum1_1 = c_st_enum1_1 ; correct := correct and si_integer_1 = c_integer_1 ; correct := correct and si_t_int1_1 = c_t_int1_1 ; correct := correct and si_st_int1_1 = c_st_int1_1 ; correct := correct and si_time_1 = c_time_1 ; correct := correct and si_t_phys1_1 = c_t_phys1_1 ; correct := correct and si_st_phys1_1 = c_st_phys1_1 ; correct := correct and si_real_1 = c_real_1 ; correct := correct and si_t_real1_1 = c_t_real1_1 ; correct := correct and si_st_real1_1 = c_st_real1_1 ; si_boolean_1 <= c_boolean_2 ; si_bit_1 <= c_bit_2 ; si_severity_level_1 <= c_severity_level_2 ; si_character_1 <= c_character_2 ; si_t_enum1_1 <= c_t_enum1_2 ; si_st_enum1_1 <= c_st_enum1_2 ; si_integer_1 <= c_integer_2 ; si_t_int1_1 <= c_t_int1_2 ; si_st_int1_1 <= c_st_int1_2 ; si_time_1 <= c_time_2 ; si_t_phys1_1 <= c_t_phys1_2 ; si_st_phys1_1 <= c_st_phys1_2 ; si_real_1 <= c_real_2 ; si_t_real1_1 <= c_t_real1_2 ; si_st_real1_1 <= c_st_real1_2 ; synch <= true ; s_correct <= s_correct and correct ; wait ; end process ; process (synch) variable correct : boolean ; begin correct := s_correct ; if synch = true then correct := correct and si_boolean_1 = c_boolean_2 ; correct := correct and si_bit_1 = c_bit_2 ; correct := correct and si_severity_level_1 = c_severity_level_2 ; correct := correct and si_character_1 = c_character_2 ; correct := correct and si_t_enum1_1 = c_t_enum1_2 ; correct := correct and si_st_enum1_1 = c_st_enum1_2 ; correct := correct and si_integer_1 = c_integer_2 ; correct := correct and si_t_int1_1 = c_t_int1_2 ; correct := correct and si_st_int1_1 = c_st_int1_2 ; correct := correct and si_time_1 = c_time_2 ; correct := correct and si_t_phys1_1 = c_t_phys1_2 ; correct := correct and si_st_phys1_1 = c_st_phys1_2 ; correct := correct and si_real_1 = c_real_2 ; correct := correct and si_t_real1_1 = c_t_real1_2 ; correct := correct and si_st_real1_1 = c_st_real1_2 ; test_report ( "ARCH00553" , "Signal declarations - scalar globally static subtypes" , correct) ; end if ; end process ; end ARCH00553 ; -- entity ENT00553_Test_Bench is end ENT00553_Test_Bench ; -- architecture ARCH00553_Test_Bench of ENT00553_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00553 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00553_Test_Bench ;
gpl-3.0
d33045393af7b64f22119d0827922165
0.539429
3.008408
false
true
false
false
grwlf/vsim
vhdl_ct/ct00045.vhd
1
5,089
-- NEED RESULT: ARCH00045.P1: Target of a variable assignment may be a slice prefixed by a selected name passed -- NEED RESULT: ARCH00045.P2: Target of a variable assignment may be a slice prefixed by a selected name passed -- NEED RESULT: ARCH00045.P3: Target of a variable assignment may be a slice prefixed by a selected name passed -- NEED RESULT: ARCH00045.P4: Target of a variable assignment may be a slice prefixed by a selected name passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00045 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00045) -- ENT00045_Test_Bench(ARCH00045_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00045 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; -- variable correct : boolean := true ; begin v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) := c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- correct := correct and v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) = c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- test_report ( "ARCH00045.P1" , "Target of a variable assignment may be a " & "slice prefixed by a selected name" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; -- begin v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) := c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- correct := correct and v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) = c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00045.P2" , "Target of a variable assignment may be a " & "slice prefixed by a selected name" , correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) := c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) = c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- test_report ( "ARCH00045.P3" , "Target of a variable assignment may be a " & "slice prefixed by a selected name" , correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_rec3 : inout st_rec3 ) is begin v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) := c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ( v_st_rec3 ) ; correct := correct and v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) (lowb+1 to highb-1) = c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) (lowb+1 to highb-1) ; -- test_report ( "ARCH00045.P4" , "Target of a variable assignment may be a " & "slice prefixed by a selected name" , correct) ; end process P4 ; -- end ARCH00045 ; -- entity ENT00045_Test_Bench is end ENT00045_Test_Bench ; -- architecture ARCH00045_Test_Bench of ENT00045_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00045 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00045_Test_Bench ;
gpl-3.0
138efd9cdda0470a665be3d8f4d6e794
0.496758
3.124002
false
true
false
false
wsoltys/AtomFpga
src/DCM/dcm2.vhd
1
2,087
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm2 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end dcm2; architecture BEHAVIORAL of dcm2 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM -- DCM_SP_INST : DCM_SP generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, -- 16.000 = 25MHz * 16 / 25 CLKFX_DIVIDE => 25, CLKFX_MULTIPLY => 16, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 40.000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;
apache-2.0
193279baec1334a037ca002b06072afa
0.404408
4.267894
false
false
false
false
grwlf/vsim
vhdl_ct/ct00123.vhd
1
31,915
-- NEED RESULT: ARCH00123.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00123: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00123 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00123 -- PKG00123/BODY -- ENT00123(ARCH00123) -- ENT00123_Test_Bench(ARCH00123_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00123 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00123 ; -- package body PKG00123 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00123 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00123.all ; entity ENT00123 is port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00123 ; -- architecture ARCH00123 of ENT00123 is begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00123.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00123" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00123" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; end process P6 ; -- -- end ARCH00123 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00123.all ; entity ENT00123_Test_Bench is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- end ENT00123_Test_Bench ; -- architecture ARCH00123_Test_Bench of ENT00123_Test_Bench is begin L1: block component UUT port ( s_r_st_arr1_vector : inout r_st_arr1_vector ; s_r_st_arr2_vector : inout r_st_arr2_vector ; s_r_st_arr3_vector : inout r_st_arr3_vector ; s_r_st_rec1_vector : inout r_st_rec1_vector ; s_r_st_rec2_vector : inout r_st_rec2_vector ; s_r_st_rec3_vector : inout r_st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00123 ( ARCH00123 ) ; begin CIS1 : UUT port map ( s_r_st_arr1_vector , s_r_st_arr2_vector , s_r_st_arr3_vector , s_r_st_rec1_vector , s_r_st_rec2_vector , s_r_st_rec3_vector ) ; end block L1 ; end ARCH00123_Test_Bench ;
gpl-3.0
bb417d7e2024a3850074b3182166bff9
0.511672
3.39413
false
false
false
false
Given-Jiang/Binarization
Binarization_dspbuilder/hdl/tb_Binarization.vhd
2
15,890
-- tb_Binarization.vhd -- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity tb_Binarization is end entity tb_Binarization; architecture rtl of tb_Binarization is component Binarization_GN is port ( Clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset_n Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire Avalon_ST_Source_valid : out std_logic; -- wire Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire Avalon_ST_Source_endofpacket : out std_logic; -- wire Avalon_ST_Source_startofpacket : out std_logic; -- wire Avalon_ST_Source_ready : in std_logic := 'X'; -- wire Avalon_MM_Slave_write : in std_logic := 'X'; -- wire Avalon_ST_Sink_ready : out std_logic; -- wire Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire Avalon_ST_Source_data : out std_logic_vector(23 downto 0) -- wire ); end component Binarization_GN; component alt_dspbuilder_testbench_clock_GNXGQJH2DS is generic ( SIMULATION_START_CYCLE : natural := 4; RESET_LATENCY : natural := 0; RESET_REGISTER_CASCADE_DEPTH : natural := 0 ); port ( aclr_out : out std_logic; -- reset clock_out : out std_logic; -- clk reg_aclr_out : out std_logic; -- reset tb_aclr : out std_logic -- reset ); end component alt_dspbuilder_testbench_clock_GNXGQJH2DS; component alt_dspbuilder_testbench_salt_GNOXVOQUET is generic ( XFILE : string := "default" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_testbench_salt_GNOXVOQUET; component alt_dspbuilder_testbench_salt_GNDBMPYDND is generic ( XFILE : string := "default" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset output : out std_logic -- wire ); end component alt_dspbuilder_testbench_salt_GNDBMPYDND; component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is generic ( XFILE : string := "default" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M; component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is generic ( XFILE : string := "default" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK; component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is generic ( XFILE : string := "default"; DSPBTYPE : string := "" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset input : in std_logic := 'X' -- wire ); end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ; component alt_dspbuilder_testbench_capture_GNHCRI5YMO is generic ( XFILE : string := "default"; DSPBTYPE : string := "" ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_testbench_capture_GNHCRI5YMO; signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr] signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock] signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr] signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr begin dut : component Binarization_GN port map ( Clock => clock_clock_tb_clk, -- Clock.clk aclr => clock_clock_output_reset_ports_inv, -- .reset_n Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire, -- Avalon_ST_Source_ready.wire Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire Avalon_ST_Source_data => dut_avalon_st_source_data_wire -- Avalon_ST_Source_data.wire ); clock : component alt_dspbuilder_testbench_clock_GNXGQJH2DS generic map ( SIMULATION_START_CYCLE => 5, RESET_LATENCY => 0, RESET_REGISTER_CASCADE_DEPTH => 0 ) port map ( clock_out => clock_clock_tb_clk, -- clock_tb.clk tb_aclr => clock_clock_tb_reset, -- .reset aclr_out => clock_clock_output_reset, -- clock_output.reset reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset ); salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET generic map ( XFILE => "Binarization_Avalon-ST+Sink_data.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_st_sink_data_output_wire -- output.wire ); salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND generic map ( XFILE => "Binarization_Avalon-ST+Sink_endofpacket.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire ); salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M generic map ( XFILE => "Binarization_Avalon-MM+Slave_address.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_mm_slave_address_output_wire -- output.wire ); salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK generic map ( XFILE => "Binarization_Avalon-MM+Slave_writedata.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_mm_slave_writedata_output_wire -- output.wire ); salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND generic map ( XFILE => "Binarization_Avalon-ST+Sink_valid.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_st_sink_valid_output_wire -- output.wire ); salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND generic map ( XFILE => "Binarization_Avalon-ST+Source_ready.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_st_source_ready_output_wire -- output.wire ); salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND generic map ( XFILE => "Binarization_Avalon-MM+Slave_write.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_mm_slave_write_output_wire -- output.wire ); salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND generic map ( XFILE => "Binarization_Avalon-ST+Sink_startofpacket.salt" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_tb_reset, -- .reset output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire ); capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ generic map ( XFILE => "Binarization_Avalon-ST+Source_valid.capture.msim", DSPBTYPE => "BIT [1, 0]" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_reg_reset_reset, -- .reset input => dut_avalon_st_source_valid_wire -- input.wire ); capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ generic map ( XFILE => "Binarization_Avalon-ST+Source_endofpacket.capture.msim", DSPBTYPE => "BIT [1, 0]" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_reg_reset_reset, -- .reset input => dut_avalon_st_source_endofpacket_wire -- input.wire ); capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ generic map ( XFILE => "Binarization_Avalon-ST+Source_startofpacket.capture.msim", DSPBTYPE => "BIT [1, 0]" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_reg_reset_reset, -- .reset input => dut_avalon_st_source_startofpacket_wire -- input.wire ); capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ generic map ( XFILE => "Binarization_Avalon-ST+Sink_ready.capture.msim", DSPBTYPE => "BIT [1, 0]" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_reg_reset_reset, -- .reset input => dut_avalon_st_sink_ready_wire -- input.wire ); capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO generic map ( XFILE => "Binarization_Avalon-ST+Source_data.capture.msim", DSPBTYPE => "UINT [24, 0]" ) port map ( clock => clock_clock_tb_clk, -- clock_aclr.clk aclr => clock_clock_reg_reset_reset, -- .reset input => dut_avalon_st_source_data_wire -- input.wire ); clock_clock_output_reset_ports_inv <= not clock_clock_output_reset; end architecture rtl; -- of tb_Binarization
mit
cadf94608c15a1625ad6d79c150c0985
0.592574
3.446855
false
true
false
false
TWW12/lzw
ip_repo/axi_compression_1.0/src/input_fifo_1/synth/input_fifo.vhd
3
38,816
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:13.1 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v13_1_3; USE fifo_generator_v13_1_3.fifo_generator_v13_1_3; ENTITY input_fifo IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END input_fifo; ARCHITECTURE input_fifo_arch OF input_fifo IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_fifo_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v13_1_3 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_SELECT_XPM : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v13_1_3; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF input_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF input_fifo_arch : ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF input_fifo_arch: ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_" & "FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=1,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NE" & "GATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TY" & "PE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C" & "_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH" & "=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_I" & "NJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_" & "PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_P" & "ROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL" & "_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v13_1_3 GENERIC MAP ( C_COMMON_CLOCK => 1, C_SELECT_XPM => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 11, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 8, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 8, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 1, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 0, C_PRELOAD_REGS => 1, C_PRIM_FIFO_TYPE => "1kx18", C_PROG_EMPTY_THRESH_ASSERT_VAL => 4, C_PROG_EMPTY_THRESH_NEGATE_VAL => 5, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 1023, C_PROG_FULL_THRESH_NEGATE_VAL => 1022, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 11, C_RD_DEPTH => 1024, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 10, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 1, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 11, C_WR_DEPTH => 1024, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 10, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_EN_SAFETY_CKT => 0, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 1, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, wr_ack => wr_ack, empty => empty, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END input_fifo_arch;
unlicense
eb2eeb8905e4f9a5b062f4216ac688b1
0.626906
2.909745
false
false
false
false
grwlf/vsim
vhdl_ct/ct00047.vhd
1
35,133
-- NEED RESULT: ARCH00047.P1: Implicit array subtype conversion occurs for simple names passed -- NEED RESULT: ARCH00047.P2: Implicit array subtype conversion occurs for simple names passed -- NEED RESULT: ARCH00047.P3: Implicit array subtype conversion occurs for simple names passed -- NEED RESULT: ARCH00047.P4: Implicit array subtype conversion occurs for simple names passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00047 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (2) -- 8.4.1 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00047) -- ENT00047_Test_Bench(ARCH00047_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00047 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; begin v_st_boolean_vector_1 := c_st_boolean_vector_2 ; v_st_bit_vector_1 := c_st_bit_vector_2 ; v_st_severity_level_vector_1 := c_st_severity_level_vector_2 ; v_st_string_1 := c_st_string_2 ; v_st_enum1_vector_1 := c_st_enum1_vector_2 ; v_st_integer_vector_1 := c_st_integer_vector_2 ; v_st_int1_vector_1 := c_st_int1_vector_2 ; v_st_time_vector_1 := c_st_time_vector_2 ; v_st_phys1_vector_1 := c_st_phys1_vector_2 ; v_st_real_vector_1 := c_st_real_vector_2 ; v_st_real1_vector_1 := c_st_real1_vector_2 ; v_st_rec1_vector_1 := c_st_rec1_vector_2 ; v_st_rec2_vector_1 := c_st_rec2_vector_2 ; v_st_rec3_vector_1 := c_st_rec3_vector_2 ; v_st_arr1_vector_1 := c_st_arr1_vector_2 ; v_st_arr2_vector_1 := c_st_arr2_vector_2 ; v_st_arr3_vector_1 := c_st_arr3_vector_2 ; -- correct := correct and v_st_boolean_vector_1 = c_st_boolean_vector_2 ; correct := correct and v_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and v_st_severity_level_vector_1 = c_st_severity_level_vector_2 ; correct := correct and v_st_string_1 = c_st_string_2 ; correct := correct and v_st_enum1_vector_1 = c_st_enum1_vector_2 ; correct := correct and v_st_integer_vector_1 = c_st_integer_vector_2 ; correct := correct and v_st_int1_vector_1 = c_st_int1_vector_2 ; correct := correct and v_st_time_vector_1 = c_st_time_vector_2 ; correct := correct and v_st_phys1_vector_1 = c_st_phys1_vector_2 ; correct := correct and v_st_real_vector_1 = c_st_real_vector_2 ; correct := correct and v_st_real1_vector_1 = c_st_real1_vector_2 ; correct := correct and v_st_rec1_vector_1 = c_st_rec1_vector_2 ; correct := correct and v_st_rec2_vector_1 = c_st_rec2_vector_2 ; correct := correct and v_st_rec3_vector_1 = c_st_rec3_vector_2 ; correct := correct and v_st_arr1_vector_1 = c_st_arr1_vector_2 ; correct := correct and v_st_arr2_vector_1 = c_st_arr2_vector_2 ; correct := correct and v_st_arr3_vector_1 = c_st_arr3_vector_2 ; -- test_report ( "ARCH00047.P1" , "Implicit array subtype conversion occurs "& "for simple names", correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- begin v_st_boolean_vector_1 := c_st_boolean_vector_2 ; v_st_bit_vector_1 := c_st_bit_vector_2 ; v_st_severity_level_vector_1 := c_st_severity_level_vector_2 ; v_st_string_1 := c_st_string_2 ; v_st_enum1_vector_1 := c_st_enum1_vector_2 ; v_st_integer_vector_1 := c_st_integer_vector_2 ; v_st_int1_vector_1 := c_st_int1_vector_2 ; v_st_time_vector_1 := c_st_time_vector_2 ; v_st_phys1_vector_1 := c_st_phys1_vector_2 ; v_st_real_vector_1 := c_st_real_vector_2 ; v_st_real1_vector_1 := c_st_real1_vector_2 ; v_st_rec1_vector_1 := c_st_rec1_vector_2 ; v_st_rec2_vector_1 := c_st_rec2_vector_2 ; v_st_rec3_vector_1 := c_st_rec3_vector_2 ; v_st_arr1_vector_1 := c_st_arr1_vector_2 ; v_st_arr2_vector_1 := c_st_arr2_vector_2 ; v_st_arr3_vector_1 := c_st_arr3_vector_2 ; -- correct := correct and v_st_boolean_vector_1 = c_st_boolean_vector_2 ; correct := correct and v_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and v_st_severity_level_vector_1 = c_st_severity_level_vector_2 ; correct := correct and v_st_string_1 = c_st_string_2 ; correct := correct and v_st_enum1_vector_1 = c_st_enum1_vector_2 ; correct := correct and v_st_integer_vector_1 = c_st_integer_vector_2 ; correct := correct and v_st_int1_vector_1 = c_st_int1_vector_2 ; correct := correct and v_st_time_vector_1 = c_st_time_vector_2 ; correct := correct and v_st_phys1_vector_1 = c_st_phys1_vector_2 ; correct := correct and v_st_real_vector_1 = c_st_real_vector_2 ; correct := correct and v_st_real1_vector_1 = c_st_real1_vector_2 ; correct := correct and v_st_rec1_vector_1 = c_st_rec1_vector_2 ; correct := correct and v_st_rec2_vector_1 = c_st_rec2_vector_2 ; correct := correct and v_st_rec3_vector_1 = c_st_rec3_vector_2 ; correct := correct and v_st_arr1_vector_1 = c_st_arr1_vector_2 ; correct := correct and v_st_arr2_vector_1 = c_st_arr2_vector_2 ; correct := correct and v_st_arr3_vector_1 = c_st_arr3_vector_2 ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00047.P2" , "Implicit array subtype conversion occurs "& "for simple names", correct) ; end process P2 ; -- P3 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; -- procedure Proc1 is begin v_st_boolean_vector_1 := c_st_boolean_vector_2 ; v_st_bit_vector_1 := c_st_bit_vector_2 ; v_st_severity_level_vector_1 := c_st_severity_level_vector_2 ; v_st_string_1 := c_st_string_2 ; v_st_enum1_vector_1 := c_st_enum1_vector_2 ; v_st_integer_vector_1 := c_st_integer_vector_2 ; v_st_int1_vector_1 := c_st_int1_vector_2 ; v_st_time_vector_1 := c_st_time_vector_2 ; v_st_phys1_vector_1 := c_st_phys1_vector_2 ; v_st_real_vector_1 := c_st_real_vector_2 ; v_st_real1_vector_1 := c_st_real1_vector_2 ; v_st_rec1_vector_1 := c_st_rec1_vector_2 ; v_st_rec2_vector_1 := c_st_rec2_vector_2 ; v_st_rec3_vector_1 := c_st_rec3_vector_2 ; v_st_arr1_vector_1 := c_st_arr1_vector_2 ; v_st_arr2_vector_1 := c_st_arr2_vector_2 ; v_st_arr3_vector_1 := c_st_arr3_vector_2 ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_boolean_vector_1 = c_st_boolean_vector_2 ; correct := correct and v_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and v_st_severity_level_vector_1 = c_st_severity_level_vector_2 ; correct := correct and v_st_string_1 = c_st_string_2 ; correct := correct and v_st_enum1_vector_1 = c_st_enum1_vector_2 ; correct := correct and v_st_integer_vector_1 = c_st_integer_vector_2 ; correct := correct and v_st_int1_vector_1 = c_st_int1_vector_2 ; correct := correct and v_st_time_vector_1 = c_st_time_vector_2 ; correct := correct and v_st_phys1_vector_1 = c_st_phys1_vector_2 ; correct := correct and v_st_real_vector_1 = c_st_real_vector_2 ; correct := correct and v_st_real1_vector_1 = c_st_real1_vector_2 ; correct := correct and v_st_rec1_vector_1 = c_st_rec1_vector_2 ; correct := correct and v_st_rec2_vector_1 = c_st_rec2_vector_2 ; correct := correct and v_st_rec3_vector_1 = c_st_rec3_vector_2 ; correct := correct and v_st_arr1_vector_1 = c_st_arr1_vector_2 ; correct := correct and v_st_arr2_vector_1 = c_st_arr2_vector_2 ; correct := correct and v_st_arr3_vector_1 = c_st_arr3_vector_2 ; -- test_report ( "ARCH00047.P3" , "Implicit array subtype conversion occurs "& "for simple names", correct) ; end process P3 ; -- P4 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_boolean_vector_1 : inout boolean_vector ; v_st_bit_vector_1 : inout bit_vector ; v_st_severity_level_vector_1 : inout severity_level_vector ; v_st_string_1 : inout string ; v_st_enum1_vector_1 : inout enum1_vector ; v_st_integer_vector_1 : inout integer_vector ; v_st_int1_vector_1 : inout int1_vector ; v_st_time_vector_1 : inout time_vector ; v_st_phys1_vector_1 : inout phys1_vector ; v_st_real_vector_1 : inout real_vector ; v_st_real1_vector_1 : inout real1_vector ; v_st_rec1_vector_1 : inout rec1_vector ; v_st_rec2_vector_1 : inout rec2_vector ; v_st_rec3_vector_1 : inout rec3_vector ; v_st_arr1_vector_1 : inout arr1_vector ; v_st_arr2_vector_1 : inout arr2_vector ; v_st_arr3_vector_1 : inout arr3_vector ) is begin v_st_boolean_vector_1 := c_st_boolean_vector_2 ; v_st_bit_vector_1 := c_st_bit_vector_2 ; v_st_severity_level_vector_1 := c_st_severity_level_vector_2 ; v_st_string_1 := c_st_string_2 ; v_st_enum1_vector_1 := c_st_enum1_vector_2 ; v_st_integer_vector_1 := c_st_integer_vector_2 ; v_st_int1_vector_1 := c_st_int1_vector_2 ; v_st_time_vector_1 := c_st_time_vector_2 ; v_st_phys1_vector_1 := c_st_phys1_vector_2 ; v_st_real_vector_1 := c_st_real_vector_2 ; v_st_real1_vector_1 := c_st_real1_vector_2 ; v_st_rec1_vector_1 := c_st_rec1_vector_2 ; v_st_rec2_vector_1 := c_st_rec2_vector_2 ; v_st_rec3_vector_1 := c_st_rec3_vector_2 ; v_st_arr1_vector_1 := c_st_arr1_vector_2 ; v_st_arr2_vector_1 := c_st_arr2_vector_2 ; v_st_arr3_vector_1 := c_st_arr3_vector_2 ; -- end Proc1 ; begin Proc1 ( v_st_boolean_vector_1 , v_st_bit_vector_1 , v_st_severity_level_vector_1 , v_st_string_1 , v_st_enum1_vector_1 , v_st_integer_vector_1 , v_st_int1_vector_1 , v_st_time_vector_1 , v_st_phys1_vector_1 , v_st_real_vector_1 , v_st_real1_vector_1 , v_st_rec1_vector_1 , v_st_rec2_vector_1 , v_st_rec3_vector_1 , v_st_arr1_vector_1 , v_st_arr2_vector_1 , v_st_arr3_vector_1 ) ; correct := correct and v_st_boolean_vector_1 = c_st_boolean_vector_2 ; correct := correct and v_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and v_st_severity_level_vector_1 = c_st_severity_level_vector_2 ; correct := correct and v_st_string_1 = c_st_string_2 ; correct := correct and v_st_enum1_vector_1 = c_st_enum1_vector_2 ; correct := correct and v_st_integer_vector_1 = c_st_integer_vector_2 ; correct := correct and v_st_int1_vector_1 = c_st_int1_vector_2 ; correct := correct and v_st_time_vector_1 = c_st_time_vector_2 ; correct := correct and v_st_phys1_vector_1 = c_st_phys1_vector_2 ; correct := correct and v_st_real_vector_1 = c_st_real_vector_2 ; correct := correct and v_st_real1_vector_1 = c_st_real1_vector_2 ; correct := correct and v_st_rec1_vector_1 = c_st_rec1_vector_2 ; correct := correct and v_st_rec2_vector_1 = c_st_rec2_vector_2 ; correct := correct and v_st_rec3_vector_1 = c_st_rec3_vector_2 ; correct := correct and v_st_arr1_vector_1 = c_st_arr1_vector_2 ; correct := correct and v_st_arr2_vector_1 = c_st_arr2_vector_2 ; correct := correct and v_st_arr3_vector_1 = c_st_arr3_vector_2 ; -- test_report ( "ARCH00047.P4" , "Implicit array subtype conversion occurs "& "for simple names", correct) ; end process P4 ; -- end ARCH00047 ; -- entity ENT00047_Test_Bench is end ENT00047_Test_Bench ; -- architecture ARCH00047_Test_Bench of ENT00047_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00047 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00047_Test_Bench ;
gpl-3.0
c0e0962a395043e5060109cb0f6b34d3
0.506817
3.378823
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_finals_buckets_if.vhd
2
27,916
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_finals_buckets_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3; USER_DATA_WIDTH : integer := 32; USER_DATA_WIDTH_2N : integer := 32; USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width) REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000" ); port ( -- Bus protocol ports, do not add to or delete MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_UABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); M_wrBurst : out std_logic; M_rdBurst : out std_logic; PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MBusy : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; -- signals from user logic USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS USER_size : in std_logic_vector(31 downto 0); -- burst size of word USER_req_nRW : in std_logic; -- req type 0: Read, 1: write USER_req_full_n : out std_logic; -- req Fifo full USER_req_push : in std_logic; -- req Fifo push (new request in) USER_rsp_empty_n : out std_logic; -- return data FIFO empty USER_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of MPLB_Clk : signal is "Clk"; attribute SIGIS of MPLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of nfa_finals_buckets_if is component nfa_finals_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) ); end component; component nfa_finals_buckets_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3); port ( -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n : out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); end component; -- type state_type is (IDLE, ); -- signal cs, ns : st_type; constant PLB_BW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8; constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8; constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data constant REQ_FIFO_ADDR_WIDTH : integer := 5; constant REQ_FIFO_DEPTH : integer := 32; constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW; constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8; signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0); -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0); signal req_fifo_dout_req_nRW : STD_LOGIC; signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0); -- internal request information signal req_nRW : STD_LOGIC; signal req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0); signal req_size_user : STD_LOGIC_VECTOR(31 downto 0); signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0); signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0); signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0); signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0); signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC; signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0); signal req_burst_mode, req_last_burst: STD_LOGIC; -- interface to PLB_master_if module signal PLB_master_if_req_full_n : STD_LOGIC; signal PLB_master_if_req_push : STD_LOGIC; signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0); signal PLB_master_if_rsp_nRW : STD_LOGIC; signal PLB_master_if_rsp_empty_n : STD_LOGIC; signal PLB_master_if_rsp_pop : STD_LOGIC; signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0); -- rsp FIFO constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size constant RSP_FIFO_ADDR_WIDTH : integer := 6; constant RSP_FIFO_DEPTH : integer := 64; signal rsp_fifo_empty_n : STD_LOGIC; signal rsp_fifo_pop : STD_LOGIC; signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0); signal rsp_fifo_full_n : STD_LOGIC; signal rsp_fifo_push : STD_LOGIC; signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0); signal rsp_valid, rsp_SOP : STD_LOGIC; signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0); signal rsp_size : STD_LOGIC_VECTOR(31 downto 0); signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0); signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0); -- rd data user FIFO signal rd_data_user_fifo_empty_n : STD_LOGIC; signal rd_data_user_fifo_pop : STD_LOGIC; signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_data_user_fifo_full_n : STD_LOGIC; signal rd_data_user_fifo_push : STD_LOGIC; signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0); signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0); begin BE_ALL_ONE <= (others => '1'); M_UABus <= (others => '0'); M_TAttribute <= (others => '0'); -- interface to user logic user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0); user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1); USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size; USER_req_full_n <= req_fifo_full_n; process(USER_WrData) variable i: integer; begin user_WrData_2N <= (others=> '0'); for i in 0 to USER_WrData'length -1 loop user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i); end loop; end process; req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local; req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0); req_fifo_push <= USER_req_push; U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_DATA_WIDTH, ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH, DEPTH => REQ_FIFO_DEPTH) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1); req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32); req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32); req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0); req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0'); process(req_fifo_empty_n, req_valid) begin req_fifo_pop <= '0'; if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request req_fifo_pop <= '1'; end if; end process; process (MPLB_Clk, MPLB_Rst) variable offset: integer; begin if (MPLB_Rst = '1') then req_nRW <= '0'; burst_size <= (others => '0'); req_size_user <= (others => '0'); req_address <= (others => '0'); req_WrData <= (others => '0'); -- set possible MSB to ZERO req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO req_valid <= '0'; req_EOP <= '0'; req_burst_write_counter <= (others => '0'); req_burst_mode <= '0'; elsif (MPLB_Clk'event and MPLB_Clk = '1') then if (req_fifo_pop = '1') then -- lunch next request req_valid <= '1'; if (req_burst_mode = '0') then if (req_fifo_dout_req_nRW = '0') then if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT); elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) + ('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1; else burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2; end if; else burst_size <= X"00000001"; -- single by default if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or (conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT); else burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1; end if; end if; end if; offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)); if (req_fifo_dout_req_nRW = '1') then req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0); req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1'); end if; req_size_user <= req_fifo_dout_req_size; -- for read operation req_nRW <= req_fifo_dout_req_nRW; req_EOP <= '1'; req_address <= req_fifo_dout_req_address; req_burst_write_counter <= req_fifo_dout_req_size; req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT; if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_mode <= '1'; req_EOP <= '0'; end if; else -- in a burst write process req_burst_write_counter <= req_burst_write_counter -1; offset := conv_integer(req_WrData_byte_p); req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0); req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1'); req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT; if (req_last_burst = '1') then req_burst_mode <= '0'; req_EOP <= '1'; end if; end if; elsif (req_valid = '1') then if (req_nRW = '0' and PLB_master_if_req_push = '1') then req_valid <= '0'; elsif (req_nRW = '1') then if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then req_valid <= '0'; req_EOP <= '0'; req_WrData <= (others=>'0'); req_WrData_BE <= (others => '0'); else req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0'); req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW); req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0'); req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT); req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1; req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0'); end if; elsif (req_EOP = '0') then if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then req_valid <= '0'; elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0'); req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW); req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0'); req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT); req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1; req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0'); end if; end if; end if; end if; end if; end process; req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0'; process(req_nRW, req_WrData_BE, burst_size) begin req_size <= (others => '0'); if (req_nRW = '0') then req_size <= burst_size; elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then req_size <= burst_size; else req_size <= X"00000001"; end if; end process; process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE) begin PLB_master_if_req_push <= '0'; if (req_valid = '1' and PLB_master_if_req_full_n = '1') then if (req_nRW = '0') then PLB_master_if_req_push <= '1'; -- only push when the last byte been push elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then PLB_master_if_req_push <= '1'; -- only push when the last byte been push end if; end if; end process; req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1'); U_nfa_finals_buckets_if_plb_master_if: component nfa_finals_buckets_if_plb_master_if generic map( C_PLB_AWIDTH => C_PLB_AWIDTH, C_PLB_DWIDTH => C_PLB_DWIDTH, PLB_ADDR_SHIFT => PLB_ADDR_SHIFT) port map ( -- Bus protocol ports, do not add to or delete PLB_Clk => MPLB_Clk, PLB_Rst => MPLB_Rst, M_abort => M_abort, M_ABus => M_ABus, M_BE => M_BE, M_busLock => M_busLock, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_RNW => M_RNW, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, PLB_MBusy => PLB_MBusy, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MAddrAck => PLB_MAddrAck, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MSSize => PLB_MSSize, -- signals from user logic BUS_RdData => PLB_master_if_dataout, BUS_WrData => req_WrData(PLB_BW-1 downto 0), BUS_address => req_address, BUS_size => req_size, BUS_req_nRW => req_nRW, BUS_req_BE => req_BE, BUS_req_full_n => PLB_master_if_req_full_n, BUS_req_push => PLB_master_if_req_push, BUS_rsp_nRW => PLB_master_if_rsp_nRW, BUS_rsp_empty_n => PLB_master_if_rsp_empty_n, BUS_rsp_pop => PLB_master_if_rsp_pop ); -- below is the response (bus read data) part U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo generic map( DATA_WIDTH => RSP_FIFO_DATA_WIDTH, ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH, DEPTH => RSP_FIFO_DEPTH) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => rsp_fifo_empty_n, if_read => rsp_fifo_pop, if_dout => rsp_fifo_dout, if_full_n => rsp_fifo_full_n, if_write => rsp_fifo_push, if_din => rsp_fifo_din ); rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0); rsp_fifo_din(31 downto 0) <= req_size_user; rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW); process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count) begin PLB_master_if_rsp_pop <= '0'; -- fetch data to rsp_rd_data until enough bytes if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then PLB_master_if_rsp_pop <= '1'; end if; end process; process (MPLB_Clk, MPLB_Rst) begin if (MPLB_Rst = '1') then rsp_valid <= '0'; rsp_addr <= (others=> '0'); rsp_size <= (others=> '0'); rsp_SOP <= '1'; rsp_rd_data_byte_count <= (others => '0'); rsp_rd_data <= (others=>'0'); rsp_fifo_pop <= '0'; elsif (MPLB_Clk'event and MPLB_Clk = '1') then rsp_fifo_pop <= '0'; if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then rsp_valid <= '1'; rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32); rsp_size <= rsp_fifo_dout(31 downto 0); rsp_fifo_pop <= '1'; rsp_rd_data_byte_count <= (others=>'0'); rsp_SOP <= '1'; end if; -- fetch data to rsp_rd_data until enough bytes if (PLB_master_if_rsp_pop = '1') then rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW); rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout; if (rsp_SOP = '1') then rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr; rsp_SOP <= '0'; else rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT; end if; end if; -- write one unit of data to USER LOGIC if (rd_data_user_fifo_push = '1') then rsp_size <= rsp_size -1; rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT; rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT; if (rsp_size = X"00000001") then rsp_valid <= '0'; end if; end if; end if; end process; process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N) variable i: integer; begin case CONV_INTEGER(rsp_addr) is when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32); when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40); when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48); when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56); when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64); when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8); when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16); when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24); when others => null; end case; for i in 0 to USER_DATA_WIDTH -1 loop rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i); end loop; rd_data_user_fifo_push <= '0'; if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then rd_data_user_fifo_push <= '1'; end if; end process; U_nfa_finals_buckets_if_rd_data_user_fifo: component nfa_finals_buckets_if_ap_fifo generic map( DATA_WIDTH => USER_DATA_WIDTH, ADDR_WIDTH => 5, DEPTH => 32) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => rd_data_user_fifo_empty_n, if_read => USER_rsp_pop, if_dout => rd_data_user_fifo_dout, if_full_n => rd_data_user_fifo_full_n, if_write => rd_data_user_fifo_push, if_din => rd_data_user_fifo_din ); USER_RdData <= rd_data_user_fifo_dout; USER_rsp_empty_n <= rd_data_user_fifo_empty_n; end IMP;
lgpl-3.0
5f2618defb0b860bfc97444fb1b6d2e8
0.551977
3.25627
false
false
false
false
grwlf/vsim
vhdl_ct/ct00589.vhd
1
6,637
-- NEED RESULT: ARCH00589: Variable declarations - composite static access subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00589 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (10) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00589) -- ENT00589_Test_Bench(ARCH00589_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00589 of E00000 is begin process variable correct : boolean := true ; type a_bit_vector is access bit_vector ; variable av_bit_vector_1, av_bit_vector_2 : a_bit_vector := new st_bit_vector ; type a_string is access string ; variable av_string_1, av_string_2 : a_string := new st_string ; type a_t_rec1 is access t_rec1 ; variable av_t_rec1_1, av_t_rec1_2 : a_t_rec1 := new st_rec1 ; type a_st_rec1 is access st_rec1 ; variable av_st_rec1_1, av_st_rec1_2 : a_st_rec1 := new st_rec1 ; type a_t_rec2 is access t_rec2 ; variable av_t_rec2_1, av_t_rec2_2 : a_t_rec2 := new st_rec2 ; type a_st_rec2 is access st_rec2 ; variable av_st_rec2_1, av_st_rec2_2 : a_st_rec2 := new st_rec2 ; type a_t_rec3 is access t_rec3 ; variable av_t_rec3_1, av_t_rec3_2 : a_t_rec3 := new st_rec3 ; type a_st_rec3 is access st_rec3 ; variable av_st_rec3_1, av_st_rec3_2 : a_st_rec3 := new st_rec3 ; type a_t_arr1 is access t_arr1 ; variable av_t_arr1_1, av_t_arr1_2 : a_t_arr1 := new st_arr1 ; type a_st_arr1 is access st_arr1 ; variable av_st_arr1_1, av_st_arr1_2 : a_st_arr1 := new st_arr1 ; type a_t_arr2 is access t_arr2 ; variable av_t_arr2_1, av_t_arr2_2 : a_t_arr2 := new st_arr2 ; type a_st_arr2 is access st_arr2 ; variable av_st_arr2_1, av_st_arr2_2 : a_st_arr2 := new st_arr2 ; type a_t_arr3 is access t_arr3 ; variable av_t_arr3_1, av_t_arr3_2 : a_t_arr3 := new st_arr3 ; type a_st_arr3 is access st_arr3 ; variable av_st_arr3_1, av_st_arr3_2 : a_st_arr3 := new st_arr3 ; begin av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ; av_string_1 := new st_string'(c_st_string_1) ; av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ; av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ; av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ; av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ; av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ; av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ; av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ; av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ; av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ; av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ; av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ; av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ; correct := correct and av_bit_vector_1.all = c_st_bit_vector_1 ; correct := correct and av_string_1.all = c_st_string_1 ; correct := correct and av_t_rec1_1.all = c_st_rec1_1 ; correct := correct and av_st_rec1_1.all = c_st_rec1_1 ; correct := correct and av_t_rec2_1.all = c_st_rec2_1 ; correct := correct and av_st_rec2_1.all = c_st_rec2_1 ; correct := correct and av_t_rec3_1.all = c_st_rec3_1 ; correct := correct and av_st_rec3_1.all = c_st_rec3_1 ; correct := correct and av_t_arr1_1.all = c_st_arr1_1 ; correct := correct and av_st_arr1_1.all = c_st_arr1_1 ; correct := correct and av_t_arr2_1.all = c_st_arr2_1 ; correct := correct and av_st_arr2_1.all = c_st_arr2_1 ; correct := correct and av_t_arr3_1.all = c_st_arr3_1 ; correct := correct and av_st_arr3_1.all = c_st_arr3_1 ; av_bit_vector_1.all := c_st_bit_vector_1 ; av_string_1.all := c_st_string_1 ; av_t_rec1_1.all := c_st_rec1_1 ; av_st_rec1_1.all := c_st_rec1_1 ; av_t_rec2_1.all := c_st_rec2_1 ; av_st_rec2_1.all := c_st_rec2_1 ; av_t_rec3_1.all := c_st_rec3_1 ; av_st_rec3_1.all := c_st_rec3_1 ; av_t_arr1_1.all := c_st_arr1_1 ; av_st_arr1_1.all := c_st_arr1_1 ; av_t_arr2_1.all := c_st_arr2_1 ; av_st_arr2_1.all := c_st_arr2_1 ; av_t_arr3_1.all := c_st_arr3_1 ; av_st_arr3_1.all := c_st_arr3_1 ; correct := correct and av_bit_vector_1.all = c_st_bit_vector_1 ; correct := correct and av_string_1.all = c_st_string_1 ; correct := correct and av_t_rec1_1.all = c_st_rec1_1 ; correct := correct and av_st_rec1_1.all = c_st_rec1_1 ; correct := correct and av_t_rec2_1.all = c_st_rec2_1 ; correct := correct and av_st_rec2_1.all = c_st_rec2_1 ; correct := correct and av_t_rec3_1.all = c_st_rec3_1 ; correct := correct and av_st_rec3_1.all = c_st_rec3_1 ; correct := correct and av_t_arr1_1.all = c_st_arr1_1 ; correct := correct and av_st_arr1_1.all = c_st_arr1_1 ; correct := correct and av_t_arr2_1.all = c_st_arr2_1 ; correct := correct and av_st_arr2_1.all = c_st_arr2_1 ; correct := correct and av_t_arr3_1.all = c_st_arr3_1 ; correct := correct and av_st_arr3_1.all = c_st_arr3_1 ; test_report ( "ARCH00589" , "Variable declarations - composite static access subtypes" , correct) ; wait ; end process ; end ARCH00589 ; -- entity ENT00589_Test_Bench is end ENT00589_Test_Bench ; -- architecture ARCH00589_Test_Bench of ENT00589_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00589 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00589_Test_Bench ;
gpl-3.0
946df1b28939f8fb8a6bce9222cdcd8a
0.506253
2.731276
false
true
false
false
jairov4/accel-oil
impl/impl_test_single/hdl/system_dlmb_cntlr_wrapper.vhd
1
18,461
------------------------------------------------------------------------------- -- system_dlmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v3_10_c; use lmb_bram_if_cntlr_v3_10_c.all; entity system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c"; end system_dlmb_cntlr_wrapper; architecture STRUCTURE of system_dlmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_FAMILY : string; C_MASK : std_logic_vector(0 to 31); C_MASK1 : std_logic_vector(0 to 31); C_MASK2 : std_logic_vector(0 to 31); C_MASK3 : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_ECC : integer; C_INTERCONNECT : integer; C_FAULT_INJECT : integer; C_CE_FAILING_REGISTERS : integer; C_UE_FAILING_REGISTERS : integer; C_ECC_STATUS_REGISTERS : integer; C_ECC_ONOFF_REGISTER : integer; C_ECC_ONOFF_RESET_VALUE : integer; C_CE_COUNTER_WIDTH : integer; C_WRITE_ACCESS : integer; C_NUM_LMB : integer; C_SPLB_CTRL_BASEADDR : std_logic_vector; C_SPLB_CTRL_HIGHADDR : std_logic_vector; C_SPLB_CTRL_AWIDTH : INTEGER; C_SPLB_CTRL_DWIDTH : INTEGER; C_SPLB_CTRL_P2P : INTEGER; C_SPLB_CTRL_MID_WIDTH : INTEGER; C_SPLB_CTRL_NUM_MASTERS : INTEGER; C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER; C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER; C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1)); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1)); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; begin dlmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00003FFF", C_FAMILY => "virtex5", C_MASK => X"80000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_NUM_LMB => 1, C_SPLB_CTRL_BASEADDR => X"FFFFFFFF", C_SPLB_CTRL_HIGHADDR => X"00000000", C_SPLB_CTRL_AWIDTH => 32, C_SPLB_CTRL_DWIDTH => 32, C_SPLB_CTRL_P2P => 0, C_SPLB_CTRL_MID_WIDTH => 1, C_SPLB_CTRL_NUM_MASTERS => 1, C_SPLB_CTRL_SUPPORT_BURSTS => 0, C_SPLB_CTRL_NATIVE_DWIDTH => 32, C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF", C_S_AXI_CTRL_HIGHADDR => X"00000000", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => LMB1_ABus, LMB1_WriteDBus => LMB1_WriteDBus, LMB1_AddrStrobe => LMB1_AddrStrobe, LMB1_ReadStrobe => LMB1_ReadStrobe, LMB1_WriteStrobe => LMB1_WriteStrobe, LMB1_BE => LMB1_BE, Sl1_DBus => Sl1_DBus, Sl1_Ready => Sl1_Ready, Sl1_Wait => Sl1_Wait, Sl1_UE => Sl1_UE, Sl1_CE => Sl1_CE, LMB2_ABus => LMB2_ABus, LMB2_WriteDBus => LMB2_WriteDBus, LMB2_AddrStrobe => LMB2_AddrStrobe, LMB2_ReadStrobe => LMB2_ReadStrobe, LMB2_WriteStrobe => LMB2_WriteStrobe, LMB2_BE => LMB2_BE, Sl2_DBus => Sl2_DBus, Sl2_Ready => Sl2_Ready, Sl2_Wait => Sl2_Wait, Sl2_UE => Sl2_UE, Sl2_CE => Sl2_CE, LMB3_ABus => LMB3_ABus, LMB3_WriteDBus => LMB3_WriteDBus, LMB3_AddrStrobe => LMB3_AddrStrobe, LMB3_ReadStrobe => LMB3_ReadStrobe, LMB3_WriteStrobe => LMB3_WriteStrobe, LMB3_BE => LMB3_BE, Sl3_DBus => Sl3_DBus, Sl3_Ready => Sl3_Ready, Sl3_Wait => Sl3_Wait, Sl3_UE => Sl3_UE, Sl3_CE => Sl3_CE, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, Interrupt => Interrupt, UE => UE, CE => CE, SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus, SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid, SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID, SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW, SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE, SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size, SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type, SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus, SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck, SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize, SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait, SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate, SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck, SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp, SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus, SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck, SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp, SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy, SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr, SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr, SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus, SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid, SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim, SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim, SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort, SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock, SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize, SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr, SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst, SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst, SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq, SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq, SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri, SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri, SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri, SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute, SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm, SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr, SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm, SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ, S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK, S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN, S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR, S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID, S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY, S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA, S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB, S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID, S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY, S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP, S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID, S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY, S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR, S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID, S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY, S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA, S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP, S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID, S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ); end architecture STRUCTURE;
lgpl-3.0
d06ed33d318840f5a288bab581e18dbb
0.615785
2.932645
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/system.vhd
1
141,049
------------------------------------------------------------------------------- -- system.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic ); end system; architecture STRUCTURE of system is component system_microblaze_0_wrapper is port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; INTERRUPT_ADDRESS : in std_logic_vector(0 to 31); INTERRUPT_ACK : out std_logic_vector(0 to 1); EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; WAKEUP : in std_logic_vector(0 to 1); SLEEP : out std_logic; DBG_WAKEUP : out std_logic; LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095); LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095); LOCKSTEP_OUT : out std_logic_vector(0 to 4095); INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to 7); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to 63); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to 63); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to 7); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to 63); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to 63); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector(0 downto 0); M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector(31 downto 0); M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector(0 downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector(0 downto 0); M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector(0 downto 0); M_AXI_IP_RDATA : in std_logic_vector(31 downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector(0 downto 0); M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector(31 downto 0); M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector(0 downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector(0 downto 0); M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector(0 downto 0); M_AXI_DP_RDATA : in std_logic_vector(31 downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector(0 downto 0); M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_IC_WDATA : out std_logic_vector(31 downto 0); M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_WUSER : out std_logic_vector(0 downto 0); M_AXI_IC_BID : in std_logic_vector(0 downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_BUSER : in std_logic_vector(0 downto 0); M_AXI_IC_WACK : out std_logic; M_AXI_IC_ARID : out std_logic_vector(0 downto 0); M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_IC_RID : in std_logic_vector(0 downto 0); M_AXI_IC_RDATA : in std_logic_vector(31 downto 0); M_AXI_IC_RRESP : in std_logic_vector(1 downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_IC_RUSER : in std_logic_vector(0 downto 0); M_AXI_IC_RACK : out std_logic; M_AXI_IC_ACVALID : in std_logic; M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_IC_ACREADY : out std_logic; M_AXI_IC_CRREADY : in std_logic; M_AXI_IC_CRVALID : out std_logic; M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_IC_CDVALID : out std_logic; M_AXI_IC_CDREADY : in std_logic; M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_IC_CDLAST : out std_logic; M_AXI_DC_AWID : out std_logic_vector(0 downto 0); M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_DC_WDATA : out std_logic_vector(31 downto 0); M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_WUSER : out std_logic_vector(0 downto 0); M_AXI_DC_BID : in std_logic_vector(0 downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_BUSER : in std_logic_vector(0 downto 0); M_AXI_DC_WACK : out std_logic; M_AXI_DC_ARID : out std_logic_vector(0 downto 0); M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_DC_RID : in std_logic_vector(0 downto 0); M_AXI_DC_RDATA : in std_logic_vector(31 downto 0); M_AXI_DC_RRESP : in std_logic_vector(1 downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; M_AXI_DC_RUSER : in std_logic_vector(0 downto 0); M_AXI_DC_RACK : out std_logic; M_AXI_DC_ACVALID : in std_logic; M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_DC_ACREADY : out std_logic; M_AXI_DC_CRREADY : in std_logic; M_AXI_DC_CRVALID : out std_logic; M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_DC_CDVALID : out std_logic; M_AXI_DC_CDREADY : in std_logic; M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_DC_CDLAST : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to 31); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to 31); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to 31); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to 31); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to 31); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to 31); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to 31); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to 31); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to 31); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to 31); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to 31); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to 31); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to 31); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to 31); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to 31); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to 31); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to 31); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to 31); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to 31); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to 31); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to 31); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to 31); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to 31); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to 31); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to 31); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to 31); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to 31); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to 31); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to 31); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to 31); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to 31); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to 31); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(31 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(31 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(31 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(31 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(31 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(31 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(31 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(31 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(31 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(31 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(31 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(31 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(31 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(31 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(31 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(31 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(31 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(31 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(31 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(31 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(31 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(31 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(31 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(31 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(31 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(31 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(31 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(31 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(31 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(31 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(31 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(31 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end component; component system_mb_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 1); MPLB_Rst : out std_logic_vector(0 to 6); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 223); M_UABus : in std_logic_vector(0 to 223); M_BE : in std_logic_vector(0 to 55); M_RNW : in std_logic_vector(0 to 6); M_abort : in std_logic_vector(0 to 6); M_busLock : in std_logic_vector(0 to 6); M_TAttribute : in std_logic_vector(0 to 111); M_lockErr : in std_logic_vector(0 to 6); M_MSize : in std_logic_vector(0 to 13); M_priority : in std_logic_vector(0 to 13); M_rdBurst : in std_logic_vector(0 to 6); M_request : in std_logic_vector(0 to 6); M_size : in std_logic_vector(0 to 27); M_type : in std_logic_vector(0 to 20); M_wrBurst : in std_logic_vector(0 to 6); M_wrDBus : in std_logic_vector(0 to 447); Sl_addrAck : in std_logic_vector(0 to 1); Sl_MRdErr : in std_logic_vector(0 to 13); Sl_MWrErr : in std_logic_vector(0 to 13); Sl_MBusy : in std_logic_vector(0 to 13); Sl_rdBTerm : in std_logic_vector(0 to 1); Sl_rdComp : in std_logic_vector(0 to 1); Sl_rdDAck : in std_logic_vector(0 to 1); Sl_rdDBus : in std_logic_vector(0 to 127); Sl_rdWdAddr : in std_logic_vector(0 to 7); Sl_rearbitrate : in std_logic_vector(0 to 1); Sl_SSize : in std_logic_vector(0 to 3); Sl_wait : in std_logic_vector(0 to 1); Sl_wrBTerm : in std_logic_vector(0 to 1); Sl_wrComp : in std_logic_vector(0 to 1); Sl_wrDAck : in std_logic_vector(0 to 1); Sl_MIRQ : in std_logic_vector(0 to 13); PLB_MIRQ : out std_logic_vector(0 to 6); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 6); PLB_MTimeout : out std_logic_vector(0 to 6); PLB_MBusy : out std_logic_vector(0 to 6); PLB_MRdErr : out std_logic_vector(0 to 6); PLB_MWrErr : out std_logic_vector(0 to 6); PLB_MRdBTerm : out std_logic_vector(0 to 6); PLB_MRdDAck : out std_logic_vector(0 to 6); PLB_MRdDBus : out std_logic_vector(0 to 447); PLB_MRdWdAddr : out std_logic_vector(0 to 27); PLB_MRearbitrate : out std_logic_vector(0 to 6); PLB_MWrBTerm : out std_logic_vector(0 to 6); PLB_MWrDAck : out std_logic_vector(0 to 6); PLB_MSSize : out std_logic_vector(0 to 13); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 2); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 6); PLB_SMWrErr : out std_logic_vector(0 to 6); PLB_SMBusy : out std_logic_vector(0 to 6); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ilmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_ilmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end component; component system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; component system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 6); Sl_MWrErr : out std_logic_vector(0 to 6); Sl_MRdErr : out std_logic_vector(0 to 6); Sl_MIRQ : out std_logic_vector(0 to 6); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; component system_proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); end component; component system_nfa_accept_samples_generic_hw_top_0_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 6); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 6); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 6); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 6) ); end component; -- Internal signals signal CLK_S : std_logic; signal Dcm_all_locked : std_logic; signal Debug_SYS_Rst : std_logic; signal Ext_BRK : std_logic; signal Ext_NM_BRK : std_logic; signal clk_50_0000MHz : std_logic; signal dlmb_LMB_ABus : std_logic_vector(0 to 31); signal dlmb_LMB_AddrStrobe : std_logic; signal dlmb_LMB_BE : std_logic_vector(0 to 3); signal dlmb_LMB_CE : std_logic; signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal dlmb_LMB_ReadStrobe : std_logic; signal dlmb_LMB_Ready : std_logic; signal dlmb_LMB_Rst : std_logic; signal dlmb_LMB_UE : std_logic; signal dlmb_LMB_Wait : std_logic; signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal dlmb_LMB_WriteStrobe : std_logic; signal dlmb_M_ABus : std_logic_vector(0 to 31); signal dlmb_M_AddrStrobe : std_logic; signal dlmb_M_BE : std_logic_vector(0 to 3); signal dlmb_M_DBus : std_logic_vector(0 to 31); signal dlmb_M_ReadStrobe : std_logic; signal dlmb_M_WriteStrobe : std_logic; signal dlmb_Sl_CE : std_logic_vector(0 to 0); signal dlmb_Sl_DBus : std_logic_vector(0 to 31); signal dlmb_Sl_Ready : std_logic_vector(0 to 0); signal dlmb_Sl_UE : std_logic_vector(0 to 0); signal dlmb_Sl_Wait : std_logic_vector(0 to 0); signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Clk : std_logic; signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal dlmb_port_BRAM_EN : std_logic; signal dlmb_port_BRAM_Rst : std_logic; signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal ilmb_LMB_ABus : std_logic_vector(0 to 31); signal ilmb_LMB_AddrStrobe : std_logic; signal ilmb_LMB_BE : std_logic_vector(0 to 3); signal ilmb_LMB_CE : std_logic; signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal ilmb_LMB_ReadStrobe : std_logic; signal ilmb_LMB_Ready : std_logic; signal ilmb_LMB_Rst : std_logic; signal ilmb_LMB_UE : std_logic; signal ilmb_LMB_Wait : std_logic; signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal ilmb_LMB_WriteStrobe : std_logic; signal ilmb_M_ABus : std_logic_vector(0 to 31); signal ilmb_M_AddrStrobe : std_logic; signal ilmb_M_ReadStrobe : std_logic; signal ilmb_Sl_CE : std_logic_vector(0 to 0); signal ilmb_Sl_DBus : std_logic_vector(0 to 31); signal ilmb_Sl_Ready : std_logic_vector(0 to 0); signal ilmb_Sl_UE : std_logic_vector(0 to 0); signal ilmb_Sl_Wait : std_logic_vector(0 to 0); signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Clk : std_logic; signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal ilmb_port_BRAM_EN : std_logic; signal ilmb_port_BRAM_Rst : std_logic; signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal mb_plb_MPLB_Rst : std_logic_vector(0 to 6); signal mb_plb_M_ABort : std_logic_vector(0 to 6); signal mb_plb_M_ABus : std_logic_vector(0 to 223); signal mb_plb_M_BE : std_logic_vector(0 to 55); signal mb_plb_M_MSize : std_logic_vector(0 to 13); signal mb_plb_M_RNW : std_logic_vector(0 to 6); signal mb_plb_M_TAttribute : std_logic_vector(0 to 111); signal mb_plb_M_UABus : std_logic_vector(0 to 223); signal mb_plb_M_busLock : std_logic_vector(0 to 6); signal mb_plb_M_lockErr : std_logic_vector(0 to 6); signal mb_plb_M_priority : std_logic_vector(0 to 13); signal mb_plb_M_rdBurst : std_logic_vector(0 to 6); signal mb_plb_M_request : std_logic_vector(0 to 6); signal mb_plb_M_size : std_logic_vector(0 to 27); signal mb_plb_M_type : std_logic_vector(0 to 20); signal mb_plb_M_wrBurst : std_logic_vector(0 to 6); signal mb_plb_M_wrDBus : std_logic_vector(0 to 447); signal mb_plb_PLB_ABus : std_logic_vector(0 to 31); signal mb_plb_PLB_BE : std_logic_vector(0 to 7); signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 6); signal mb_plb_PLB_MBusy : std_logic_vector(0 to 6); signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 6); signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 6); signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 6); signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 447); signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 6); signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 27); signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 6); signal mb_plb_PLB_MSSize : std_logic_vector(0 to 13); signal mb_plb_PLB_MSize : std_logic_vector(0 to 1); signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 6); signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 6); signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 6); signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 6); signal mb_plb_PLB_PAValid : std_logic; signal mb_plb_PLB_RNW : std_logic; signal mb_plb_PLB_SAValid : std_logic; signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal mb_plb_PLB_UABus : std_logic_vector(0 to 31); signal mb_plb_PLB_abort : std_logic; signal mb_plb_PLB_busLock : std_logic; signal mb_plb_PLB_lockErr : std_logic; signal mb_plb_PLB_masterID : std_logic_vector(0 to 2); signal mb_plb_PLB_rdBurst : std_logic; signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_rdPendReq : std_logic; signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 1); signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1); signal mb_plb_PLB_size : std_logic_vector(0 to 3); signal mb_plb_PLB_type : std_logic_vector(0 to 2); signal mb_plb_PLB_wrBurst : std_logic; signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_wrPendReq : std_logic; signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 1); signal mb_plb_SPLB_Rst : std_logic_vector(0 to 1); signal mb_plb_Sl_MBusy : std_logic_vector(0 to 13); signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 13); signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 13); signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 13); signal mb_plb_Sl_SSize : std_logic_vector(0 to 3); signal mb_plb_Sl_addrAck : std_logic_vector(0 to 1); signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 1); signal mb_plb_Sl_rdComp : std_logic_vector(0 to 1); signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 1); signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 127); signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 7); signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 1); signal mb_plb_Sl_wait : std_logic_vector(0 to 1); signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 1); signal mb_plb_Sl_wrComp : std_logic_vector(0 to 1); signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 1); signal mb_reset : std_logic; signal microblaze_0_mdm_bus_Dbg_Capture : std_logic; signal microblaze_0_mdm_bus_Dbg_Clk : std_logic; signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7); signal microblaze_0_mdm_bus_Dbg_Shift : std_logic; signal microblaze_0_mdm_bus_Dbg_TDI : std_logic; signal microblaze_0_mdm_bus_Dbg_TDO : std_logic; signal microblaze_0_mdm_bus_Dbg_Update : std_logic; signal microblaze_0_mdm_bus_Debug_Rst : std_logic; signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 downto 0); signal net_gnd2 : std_logic_vector(0 to 1); signal net_gnd3 : std_logic_vector(2 downto 0); signal net_gnd4 : std_logic_vector(0 to 3); signal net_gnd10 : std_logic_vector(0 to 9); signal net_gnd16 : std_logic_vector(0 to 15); signal net_gnd32 : std_logic_vector(0 to 31); signal net_gnd4096 : std_logic_vector(0 to 4095); signal net_vcc0 : std_logic; signal sys_bus_reset : std_logic_vector(0 to 0); signal sys_periph_reset : std_logic_vector(0 to 0); signal sys_rst_s : std_logic; begin -- Internal assignments CLK_S <= fpga_0_clk_1_sys_clk_pin; sys_rst_s <= fpga_0_rst_1_sys_rst_pin; net_gnd0 <= '0'; net_gnd1(0 downto 0) <= B"0"; net_gnd10(0 to 9) <= B"0000000000"; net_gnd16(0 to 15) <= B"0000000000000000"; net_gnd2(0 to 1) <= B"00"; net_gnd3(2 downto 0) <= B"000"; net_gnd32(0 to 31) <= B"00000000000000000000000000000000"; net_gnd4(0 to 3) <= B"0000"; net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; net_vcc0 <= '1'; microblaze_0 : system_microblaze_0_wrapper port map ( CLK => clk_50_0000MHz, RESET => dlmb_LMB_Rst, MB_RESET => mb_reset, INTERRUPT => net_gnd0, INTERRUPT_ADDRESS => net_gnd32, INTERRUPT_ACK => open, EXT_BRK => Ext_BRK, EXT_NM_BRK => Ext_NM_BRK, DBG_STOP => net_gnd0, MB_Halted => open, MB_Error => open, WAKEUP => net_gnd2, SLEEP => open, DBG_WAKEUP => open, LOCKSTEP_MASTER_OUT => open, LOCKSTEP_SLAVE_IN => net_gnd4096, LOCKSTEP_OUT => open, INSTR => ilmb_LMB_ReadDBus, IREADY => ilmb_LMB_Ready, IWAIT => ilmb_LMB_Wait, ICE => ilmb_LMB_CE, IUE => ilmb_LMB_UE, INSTR_ADDR => ilmb_M_ABus, IFETCH => ilmb_M_ReadStrobe, I_AS => ilmb_M_AddrStrobe, IPLB_M_ABort => mb_plb_M_ABort(1), IPLB_M_ABus => mb_plb_M_ABus(32 to 63), IPLB_M_UABus => mb_plb_M_UABus(32 to 63), IPLB_M_BE => mb_plb_M_BE(8 to 15), IPLB_M_busLock => mb_plb_M_busLock(1), IPLB_M_lockErr => mb_plb_M_lockErr(1), IPLB_M_MSize => mb_plb_M_MSize(2 to 3), IPLB_M_priority => mb_plb_M_priority(2 to 3), IPLB_M_rdBurst => mb_plb_M_rdBurst(1), IPLB_M_request => mb_plb_M_request(1), IPLB_M_RNW => mb_plb_M_RNW(1), IPLB_M_size => mb_plb_M_size(4 to 7), IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31), IPLB_M_type => mb_plb_M_type(3 to 5), IPLB_M_wrBurst => mb_plb_M_wrBurst(1), IPLB_M_wrDBus => mb_plb_M_wrDBus(64 to 127), IPLB_MBusy => mb_plb_PLB_MBusy(1), IPLB_MRdErr => mb_plb_PLB_MRdErr(1), IPLB_MWrErr => mb_plb_PLB_MWrErr(1), IPLB_MIRQ => mb_plb_PLB_MIRQ(1), IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1), IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1), IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1), IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1), IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1), IPLB_MRdDBus => mb_plb_PLB_MRdDBus(64 to 127), IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7), IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1), IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3), IPLB_MTimeout => mb_plb_PLB_MTimeout(1), DATA_READ => dlmb_LMB_ReadDBus, DREADY => dlmb_LMB_Ready, DWAIT => dlmb_LMB_Wait, DCE => dlmb_LMB_CE, DUE => dlmb_LMB_UE, DATA_WRITE => dlmb_M_DBus, DATA_ADDR => dlmb_M_ABus, D_AS => dlmb_M_AddrStrobe, READ_STROBE => dlmb_M_ReadStrobe, WRITE_STROBE => dlmb_M_WriteStrobe, BYTE_ENABLE => dlmb_M_BE, DPLB_M_ABort => mb_plb_M_ABort(0), DPLB_M_ABus => mb_plb_M_ABus(0 to 31), DPLB_M_UABus => mb_plb_M_UABus(0 to 31), DPLB_M_BE => mb_plb_M_BE(0 to 7), DPLB_M_busLock => mb_plb_M_busLock(0), DPLB_M_lockErr => mb_plb_M_lockErr(0), DPLB_M_MSize => mb_plb_M_MSize(0 to 1), DPLB_M_priority => mb_plb_M_priority(0 to 1), DPLB_M_rdBurst => mb_plb_M_rdBurst(0), DPLB_M_request => mb_plb_M_request(0), DPLB_M_RNW => mb_plb_M_RNW(0), DPLB_M_size => mb_plb_M_size(0 to 3), DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15), DPLB_M_type => mb_plb_M_type(0 to 2), DPLB_M_wrBurst => mb_plb_M_wrBurst(0), DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 63), DPLB_MBusy => mb_plb_PLB_MBusy(0), DPLB_MRdErr => mb_plb_PLB_MRdErr(0), DPLB_MWrErr => mb_plb_PLB_MWrErr(0), DPLB_MIRQ => mb_plb_PLB_MIRQ(0), DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0), DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0), DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0), DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0), DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0), DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 63), DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3), DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0), DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1), DPLB_MTimeout => mb_plb_PLB_MTimeout(0), M_AXI_IP_AWID => open, M_AXI_IP_AWADDR => open, M_AXI_IP_AWLEN => open, M_AXI_IP_AWSIZE => open, M_AXI_IP_AWBURST => open, M_AXI_IP_AWLOCK => open, M_AXI_IP_AWCACHE => open, M_AXI_IP_AWPROT => open, M_AXI_IP_AWQOS => open, M_AXI_IP_AWVALID => open, M_AXI_IP_AWREADY => net_gnd0, M_AXI_IP_WDATA => open, M_AXI_IP_WSTRB => open, M_AXI_IP_WLAST => open, M_AXI_IP_WVALID => open, M_AXI_IP_WREADY => net_gnd0, M_AXI_IP_BID => net_gnd1(0 downto 0), M_AXI_IP_BRESP => net_gnd2(0 to 1), M_AXI_IP_BVALID => net_gnd0, M_AXI_IP_BREADY => open, M_AXI_IP_ARID => open, M_AXI_IP_ARADDR => open, M_AXI_IP_ARLEN => open, M_AXI_IP_ARSIZE => open, M_AXI_IP_ARBURST => open, M_AXI_IP_ARLOCK => open, M_AXI_IP_ARCACHE => open, M_AXI_IP_ARPROT => open, M_AXI_IP_ARQOS => open, M_AXI_IP_ARVALID => open, M_AXI_IP_ARREADY => net_gnd0, M_AXI_IP_RID => net_gnd1(0 downto 0), M_AXI_IP_RDATA => net_gnd32(0 to 31), M_AXI_IP_RRESP => net_gnd2(0 to 1), M_AXI_IP_RLAST => net_gnd0, M_AXI_IP_RVALID => net_gnd0, M_AXI_IP_RREADY => open, M_AXI_DP_AWID => open, M_AXI_DP_AWADDR => open, M_AXI_DP_AWLEN => open, M_AXI_DP_AWSIZE => open, M_AXI_DP_AWBURST => open, M_AXI_DP_AWLOCK => open, M_AXI_DP_AWCACHE => open, M_AXI_DP_AWPROT => open, M_AXI_DP_AWQOS => open, M_AXI_DP_AWVALID => open, M_AXI_DP_AWREADY => net_gnd0, M_AXI_DP_WDATA => open, M_AXI_DP_WSTRB => open, M_AXI_DP_WLAST => open, M_AXI_DP_WVALID => open, M_AXI_DP_WREADY => net_gnd0, M_AXI_DP_BID => net_gnd1(0 downto 0), M_AXI_DP_BRESP => net_gnd2(0 to 1), M_AXI_DP_BVALID => net_gnd0, M_AXI_DP_BREADY => open, M_AXI_DP_ARID => open, M_AXI_DP_ARADDR => open, M_AXI_DP_ARLEN => open, M_AXI_DP_ARSIZE => open, M_AXI_DP_ARBURST => open, M_AXI_DP_ARLOCK => open, M_AXI_DP_ARCACHE => open, M_AXI_DP_ARPROT => open, M_AXI_DP_ARQOS => open, M_AXI_DP_ARVALID => open, M_AXI_DP_ARREADY => net_gnd0, M_AXI_DP_RID => net_gnd1(0 downto 0), M_AXI_DP_RDATA => net_gnd32(0 to 31), M_AXI_DP_RRESP => net_gnd2(0 to 1), M_AXI_DP_RLAST => net_gnd0, M_AXI_DP_RVALID => net_gnd0, M_AXI_DP_RREADY => open, M_AXI_IC_AWID => open, M_AXI_IC_AWADDR => open, M_AXI_IC_AWLEN => open, M_AXI_IC_AWSIZE => open, M_AXI_IC_AWBURST => open, M_AXI_IC_AWLOCK => open, M_AXI_IC_AWCACHE => open, M_AXI_IC_AWPROT => open, M_AXI_IC_AWQOS => open, M_AXI_IC_AWVALID => open, M_AXI_IC_AWREADY => net_gnd0, M_AXI_IC_AWUSER => open, M_AXI_IC_AWDOMAIN => open, M_AXI_IC_AWSNOOP => open, M_AXI_IC_AWBAR => open, M_AXI_IC_WDATA => open, M_AXI_IC_WSTRB => open, M_AXI_IC_WLAST => open, M_AXI_IC_WVALID => open, M_AXI_IC_WREADY => net_gnd0, M_AXI_IC_WUSER => open, M_AXI_IC_BID => net_gnd1(0 downto 0), M_AXI_IC_BRESP => net_gnd2(0 to 1), M_AXI_IC_BVALID => net_gnd0, M_AXI_IC_BREADY => open, M_AXI_IC_BUSER => net_gnd1(0 downto 0), M_AXI_IC_WACK => open, M_AXI_IC_ARID => open, M_AXI_IC_ARADDR => open, M_AXI_IC_ARLEN => open, M_AXI_IC_ARSIZE => open, M_AXI_IC_ARBURST => open, M_AXI_IC_ARLOCK => open, M_AXI_IC_ARCACHE => open, M_AXI_IC_ARPROT => open, M_AXI_IC_ARQOS => open, M_AXI_IC_ARVALID => open, M_AXI_IC_ARREADY => net_gnd0, M_AXI_IC_ARUSER => open, M_AXI_IC_ARDOMAIN => open, M_AXI_IC_ARSNOOP => open, M_AXI_IC_ARBAR => open, M_AXI_IC_RID => net_gnd1(0 downto 0), M_AXI_IC_RDATA => net_gnd32(0 to 31), M_AXI_IC_RRESP => net_gnd2(0 to 1), M_AXI_IC_RLAST => net_gnd0, M_AXI_IC_RVALID => net_gnd0, M_AXI_IC_RREADY => open, M_AXI_IC_RUSER => net_gnd1(0 downto 0), M_AXI_IC_RACK => open, M_AXI_IC_ACVALID => net_gnd0, M_AXI_IC_ACADDR => net_gnd32(0 to 31), M_AXI_IC_ACSNOOP => net_gnd4(0 to 3), M_AXI_IC_ACPROT => net_gnd3, M_AXI_IC_ACREADY => open, M_AXI_IC_CRREADY => net_gnd0, M_AXI_IC_CRVALID => open, M_AXI_IC_CRRESP => open, M_AXI_IC_CDVALID => open, M_AXI_IC_CDREADY => net_gnd0, M_AXI_IC_CDDATA => open, M_AXI_IC_CDLAST => open, M_AXI_DC_AWID => open, M_AXI_DC_AWADDR => open, M_AXI_DC_AWLEN => open, M_AXI_DC_AWSIZE => open, M_AXI_DC_AWBURST => open, M_AXI_DC_AWLOCK => open, M_AXI_DC_AWCACHE => open, M_AXI_DC_AWPROT => open, M_AXI_DC_AWQOS => open, M_AXI_DC_AWVALID => open, M_AXI_DC_AWREADY => net_gnd0, M_AXI_DC_AWUSER => open, M_AXI_DC_AWDOMAIN => open, M_AXI_DC_AWSNOOP => open, M_AXI_DC_AWBAR => open, M_AXI_DC_WDATA => open, M_AXI_DC_WSTRB => open, M_AXI_DC_WLAST => open, M_AXI_DC_WVALID => open, M_AXI_DC_WREADY => net_gnd0, M_AXI_DC_WUSER => open, M_AXI_DC_BID => net_gnd1(0 downto 0), M_AXI_DC_BRESP => net_gnd2(0 to 1), M_AXI_DC_BVALID => net_gnd0, M_AXI_DC_BREADY => open, M_AXI_DC_BUSER => net_gnd1(0 downto 0), M_AXI_DC_WACK => open, M_AXI_DC_ARID => open, M_AXI_DC_ARADDR => open, M_AXI_DC_ARLEN => open, M_AXI_DC_ARSIZE => open, M_AXI_DC_ARBURST => open, M_AXI_DC_ARLOCK => open, M_AXI_DC_ARCACHE => open, M_AXI_DC_ARPROT => open, M_AXI_DC_ARQOS => open, M_AXI_DC_ARVALID => open, M_AXI_DC_ARREADY => net_gnd0, M_AXI_DC_ARUSER => open, M_AXI_DC_ARDOMAIN => open, M_AXI_DC_ARSNOOP => open, M_AXI_DC_ARBAR => open, M_AXI_DC_RID => net_gnd1(0 downto 0), M_AXI_DC_RDATA => net_gnd32(0 to 31), M_AXI_DC_RRESP => net_gnd2(0 to 1), M_AXI_DC_RLAST => net_gnd0, M_AXI_DC_RVALID => net_gnd0, M_AXI_DC_RREADY => open, M_AXI_DC_RUSER => net_gnd1(0 downto 0), M_AXI_DC_RACK => open, M_AXI_DC_ACVALID => net_gnd0, M_AXI_DC_ACADDR => net_gnd32(0 to 31), M_AXI_DC_ACSNOOP => net_gnd4(0 to 3), M_AXI_DC_ACPROT => net_gnd3, M_AXI_DC_ACREADY => open, M_AXI_DC_CRREADY => net_gnd0, M_AXI_DC_CRVALID => open, M_AXI_DC_CRRESP => open, M_AXI_DC_CDVALID => open, M_AXI_DC_CDREADY => net_gnd0, M_AXI_DC_CDDATA => open, M_AXI_DC_CDLAST => open, DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk, DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI, DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO, DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En, DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift, DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture, DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update, DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst, Trace_Instruction => open, Trace_Valid_Instr => open, Trace_PC => open, Trace_Reg_Write => open, Trace_Reg_Addr => open, Trace_MSR_Reg => open, Trace_PID_Reg => open, Trace_New_Reg_Value => open, Trace_Exception_Taken => open, Trace_Exception_Kind => open, Trace_Jump_Taken => open, Trace_Delay_Slot => open, Trace_Data_Address => open, Trace_Data_Access => open, Trace_Data_Read => open, Trace_Data_Write => open, Trace_Data_Write_Value => open, Trace_Data_Byte_Enable => open, Trace_DCache_Req => open, Trace_DCache_Hit => open, Trace_DCache_Rdy => open, Trace_DCache_Read => open, Trace_ICache_Req => open, Trace_ICache_Hit => open, Trace_ICache_Rdy => open, Trace_OF_PipeRun => open, Trace_EX_PipeRun => open, Trace_MEM_PipeRun => open, Trace_MB_Halted => open, Trace_Jump_Hit => open, FSL0_S_CLK => open, FSL0_S_READ => open, FSL0_S_DATA => net_gnd32, FSL0_S_CONTROL => net_gnd0, FSL0_S_EXISTS => net_gnd0, FSL0_M_CLK => open, FSL0_M_WRITE => open, FSL0_M_DATA => open, FSL0_M_CONTROL => open, FSL0_M_FULL => net_gnd0, FSL1_S_CLK => open, FSL1_S_READ => open, FSL1_S_DATA => net_gnd32, FSL1_S_CONTROL => net_gnd0, FSL1_S_EXISTS => net_gnd0, FSL1_M_CLK => open, FSL1_M_WRITE => open, FSL1_M_DATA => open, FSL1_M_CONTROL => open, FSL1_M_FULL => net_gnd0, FSL2_S_CLK => open, FSL2_S_READ => open, FSL2_S_DATA => net_gnd32, FSL2_S_CONTROL => net_gnd0, FSL2_S_EXISTS => net_gnd0, FSL2_M_CLK => open, FSL2_M_WRITE => open, FSL2_M_DATA => open, FSL2_M_CONTROL => open, FSL2_M_FULL => net_gnd0, FSL3_S_CLK => open, FSL3_S_READ => open, FSL3_S_DATA => net_gnd32, FSL3_S_CONTROL => net_gnd0, FSL3_S_EXISTS => net_gnd0, FSL3_M_CLK => open, FSL3_M_WRITE => open, FSL3_M_DATA => open, FSL3_M_CONTROL => open, FSL3_M_FULL => net_gnd0, FSL4_S_CLK => open, FSL4_S_READ => open, FSL4_S_DATA => net_gnd32, FSL4_S_CONTROL => net_gnd0, FSL4_S_EXISTS => net_gnd0, FSL4_M_CLK => open, FSL4_M_WRITE => open, FSL4_M_DATA => open, FSL4_M_CONTROL => open, FSL4_M_FULL => net_gnd0, FSL5_S_CLK => open, FSL5_S_READ => open, FSL5_S_DATA => net_gnd32, FSL5_S_CONTROL => net_gnd0, FSL5_S_EXISTS => net_gnd0, FSL5_M_CLK => open, FSL5_M_WRITE => open, FSL5_M_DATA => open, FSL5_M_CONTROL => open, FSL5_M_FULL => net_gnd0, FSL6_S_CLK => open, FSL6_S_READ => open, FSL6_S_DATA => net_gnd32, FSL6_S_CONTROL => net_gnd0, FSL6_S_EXISTS => net_gnd0, FSL6_M_CLK => open, FSL6_M_WRITE => open, FSL6_M_DATA => open, FSL6_M_CONTROL => open, FSL6_M_FULL => net_gnd0, FSL7_S_CLK => open, FSL7_S_READ => open, FSL7_S_DATA => net_gnd32, FSL7_S_CONTROL => net_gnd0, FSL7_S_EXISTS => net_gnd0, FSL7_M_CLK => open, FSL7_M_WRITE => open, FSL7_M_DATA => open, FSL7_M_CONTROL => open, FSL7_M_FULL => net_gnd0, FSL8_S_CLK => open, FSL8_S_READ => open, FSL8_S_DATA => net_gnd32, FSL8_S_CONTROL => net_gnd0, FSL8_S_EXISTS => net_gnd0, FSL8_M_CLK => open, FSL8_M_WRITE => open, FSL8_M_DATA => open, FSL8_M_CONTROL => open, FSL8_M_FULL => net_gnd0, FSL9_S_CLK => open, FSL9_S_READ => open, FSL9_S_DATA => net_gnd32, FSL9_S_CONTROL => net_gnd0, FSL9_S_EXISTS => net_gnd0, FSL9_M_CLK => open, FSL9_M_WRITE => open, FSL9_M_DATA => open, FSL9_M_CONTROL => open, FSL9_M_FULL => net_gnd0, FSL10_S_CLK => open, FSL10_S_READ => open, FSL10_S_DATA => net_gnd32, FSL10_S_CONTROL => net_gnd0, FSL10_S_EXISTS => net_gnd0, FSL10_M_CLK => open, FSL10_M_WRITE => open, FSL10_M_DATA => open, FSL10_M_CONTROL => open, FSL10_M_FULL => net_gnd0, FSL11_S_CLK => open, FSL11_S_READ => open, FSL11_S_DATA => net_gnd32, FSL11_S_CONTROL => net_gnd0, FSL11_S_EXISTS => net_gnd0, FSL11_M_CLK => open, FSL11_M_WRITE => open, FSL11_M_DATA => open, FSL11_M_CONTROL => open, FSL11_M_FULL => net_gnd0, FSL12_S_CLK => open, FSL12_S_READ => open, FSL12_S_DATA => net_gnd32, FSL12_S_CONTROL => net_gnd0, FSL12_S_EXISTS => net_gnd0, FSL12_M_CLK => open, FSL12_M_WRITE => open, FSL12_M_DATA => open, FSL12_M_CONTROL => open, FSL12_M_FULL => net_gnd0, FSL13_S_CLK => open, FSL13_S_READ => open, FSL13_S_DATA => net_gnd32, FSL13_S_CONTROL => net_gnd0, FSL13_S_EXISTS => net_gnd0, FSL13_M_CLK => open, FSL13_M_WRITE => open, FSL13_M_DATA => open, FSL13_M_CONTROL => open, FSL13_M_FULL => net_gnd0, FSL14_S_CLK => open, FSL14_S_READ => open, FSL14_S_DATA => net_gnd32, FSL14_S_CONTROL => net_gnd0, FSL14_S_EXISTS => net_gnd0, FSL14_M_CLK => open, FSL14_M_WRITE => open, FSL14_M_DATA => open, FSL14_M_CONTROL => open, FSL14_M_FULL => net_gnd0, FSL15_S_CLK => open, FSL15_S_READ => open, FSL15_S_DATA => net_gnd32, FSL15_S_CONTROL => net_gnd0, FSL15_S_EXISTS => net_gnd0, FSL15_M_CLK => open, FSL15_M_WRITE => open, FSL15_M_DATA => open, FSL15_M_CONTROL => open, FSL15_M_FULL => net_gnd0, M0_AXIS_TLAST => open, M0_AXIS_TDATA => open, M0_AXIS_TVALID => open, M0_AXIS_TREADY => net_gnd0, S0_AXIS_TLAST => net_gnd0, S0_AXIS_TDATA => net_gnd32(0 to 31), S0_AXIS_TVALID => net_gnd0, S0_AXIS_TREADY => open, M1_AXIS_TLAST => open, M1_AXIS_TDATA => open, M1_AXIS_TVALID => open, M1_AXIS_TREADY => net_gnd0, S1_AXIS_TLAST => net_gnd0, S1_AXIS_TDATA => net_gnd32(0 to 31), S1_AXIS_TVALID => net_gnd0, S1_AXIS_TREADY => open, M2_AXIS_TLAST => open, M2_AXIS_TDATA => open, M2_AXIS_TVALID => open, M2_AXIS_TREADY => net_gnd0, S2_AXIS_TLAST => net_gnd0, S2_AXIS_TDATA => net_gnd32(0 to 31), S2_AXIS_TVALID => net_gnd0, S2_AXIS_TREADY => open, M3_AXIS_TLAST => open, M3_AXIS_TDATA => open, M3_AXIS_TVALID => open, M3_AXIS_TREADY => net_gnd0, S3_AXIS_TLAST => net_gnd0, S3_AXIS_TDATA => net_gnd32(0 to 31), S3_AXIS_TVALID => net_gnd0, S3_AXIS_TREADY => open, M4_AXIS_TLAST => open, M4_AXIS_TDATA => open, M4_AXIS_TVALID => open, M4_AXIS_TREADY => net_gnd0, S4_AXIS_TLAST => net_gnd0, S4_AXIS_TDATA => net_gnd32(0 to 31), S4_AXIS_TVALID => net_gnd0, S4_AXIS_TREADY => open, M5_AXIS_TLAST => open, M5_AXIS_TDATA => open, M5_AXIS_TVALID => open, M5_AXIS_TREADY => net_gnd0, S5_AXIS_TLAST => net_gnd0, S5_AXIS_TDATA => net_gnd32(0 to 31), S5_AXIS_TVALID => net_gnd0, S5_AXIS_TREADY => open, M6_AXIS_TLAST => open, M6_AXIS_TDATA => open, M6_AXIS_TVALID => open, M6_AXIS_TREADY => net_gnd0, S6_AXIS_TLAST => net_gnd0, S6_AXIS_TDATA => net_gnd32(0 to 31), S6_AXIS_TVALID => net_gnd0, S6_AXIS_TREADY => open, M7_AXIS_TLAST => open, M7_AXIS_TDATA => open, M7_AXIS_TVALID => open, M7_AXIS_TREADY => net_gnd0, S7_AXIS_TLAST => net_gnd0, S7_AXIS_TDATA => net_gnd32(0 to 31), S7_AXIS_TVALID => net_gnd0, S7_AXIS_TREADY => open, M8_AXIS_TLAST => open, M8_AXIS_TDATA => open, M8_AXIS_TVALID => open, M8_AXIS_TREADY => net_gnd0, S8_AXIS_TLAST => net_gnd0, S8_AXIS_TDATA => net_gnd32(0 to 31), S8_AXIS_TVALID => net_gnd0, S8_AXIS_TREADY => open, M9_AXIS_TLAST => open, M9_AXIS_TDATA => open, M9_AXIS_TVALID => open, M9_AXIS_TREADY => net_gnd0, S9_AXIS_TLAST => net_gnd0, S9_AXIS_TDATA => net_gnd32(0 to 31), S9_AXIS_TVALID => net_gnd0, S9_AXIS_TREADY => open, M10_AXIS_TLAST => open, M10_AXIS_TDATA => open, M10_AXIS_TVALID => open, M10_AXIS_TREADY => net_gnd0, S10_AXIS_TLAST => net_gnd0, S10_AXIS_TDATA => net_gnd32(0 to 31), S10_AXIS_TVALID => net_gnd0, S10_AXIS_TREADY => open, M11_AXIS_TLAST => open, M11_AXIS_TDATA => open, M11_AXIS_TVALID => open, M11_AXIS_TREADY => net_gnd0, S11_AXIS_TLAST => net_gnd0, S11_AXIS_TDATA => net_gnd32(0 to 31), S11_AXIS_TVALID => net_gnd0, S11_AXIS_TREADY => open, M12_AXIS_TLAST => open, M12_AXIS_TDATA => open, M12_AXIS_TVALID => open, M12_AXIS_TREADY => net_gnd0, S12_AXIS_TLAST => net_gnd0, S12_AXIS_TDATA => net_gnd32(0 to 31), S12_AXIS_TVALID => net_gnd0, S12_AXIS_TREADY => open, M13_AXIS_TLAST => open, M13_AXIS_TDATA => open, M13_AXIS_TVALID => open, M13_AXIS_TREADY => net_gnd0, S13_AXIS_TLAST => net_gnd0, S13_AXIS_TDATA => net_gnd32(0 to 31), S13_AXIS_TVALID => net_gnd0, S13_AXIS_TREADY => open, M14_AXIS_TLAST => open, M14_AXIS_TDATA => open, M14_AXIS_TVALID => open, M14_AXIS_TREADY => net_gnd0, S14_AXIS_TLAST => net_gnd0, S14_AXIS_TDATA => net_gnd32(0 to 31), S14_AXIS_TVALID => net_gnd0, S14_AXIS_TREADY => open, M15_AXIS_TLAST => open, M15_AXIS_TDATA => open, M15_AXIS_TVALID => open, M15_AXIS_TREADY => net_gnd0, S15_AXIS_TLAST => net_gnd0, S15_AXIS_TDATA => net_gnd32(0 to 31), S15_AXIS_TVALID => net_gnd0, S15_AXIS_TREADY => open, ICACHE_FSL_IN_CLK => open, ICACHE_FSL_IN_READ => open, ICACHE_FSL_IN_DATA => net_gnd32, ICACHE_FSL_IN_CONTROL => net_gnd0, ICACHE_FSL_IN_EXISTS => net_gnd0, ICACHE_FSL_OUT_CLK => open, ICACHE_FSL_OUT_WRITE => open, ICACHE_FSL_OUT_DATA => open, ICACHE_FSL_OUT_CONTROL => open, ICACHE_FSL_OUT_FULL => net_gnd0, DCACHE_FSL_IN_CLK => open, DCACHE_FSL_IN_READ => open, DCACHE_FSL_IN_DATA => net_gnd32, DCACHE_FSL_IN_CONTROL => net_gnd0, DCACHE_FSL_IN_EXISTS => net_gnd0, DCACHE_FSL_OUT_CLK => open, DCACHE_FSL_OUT_WRITE => open, DCACHE_FSL_OUT_DATA => open, DCACHE_FSL_OUT_CONTROL => open, DCACHE_FSL_OUT_FULL => net_gnd0 ); mb_plb : system_mb_plb_wrapper port map ( PLB_Clk => clk_50_0000MHz, SYS_Rst => sys_bus_reset(0), PLB_Rst => open, SPLB_Rst => mb_plb_SPLB_Rst, MPLB_Rst => mb_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => mb_plb_M_ABus, M_UABus => mb_plb_M_UABus, M_BE => mb_plb_M_BE, M_RNW => mb_plb_M_RNW, M_abort => mb_plb_M_ABort, M_busLock => mb_plb_M_busLock, M_TAttribute => mb_plb_M_TAttribute, M_lockErr => mb_plb_M_lockErr, M_MSize => mb_plb_M_MSize, M_priority => mb_plb_M_priority, M_rdBurst => mb_plb_M_rdBurst, M_request => mb_plb_M_request, M_size => mb_plb_M_size, M_type => mb_plb_M_type, M_wrBurst => mb_plb_M_wrBurst, M_wrDBus => mb_plb_M_wrDBus, Sl_addrAck => mb_plb_Sl_addrAck, Sl_MRdErr => mb_plb_Sl_MRdErr, Sl_MWrErr => mb_plb_Sl_MWrErr, Sl_MBusy => mb_plb_Sl_MBusy, Sl_rdBTerm => mb_plb_Sl_rdBTerm, Sl_rdComp => mb_plb_Sl_rdComp, Sl_rdDAck => mb_plb_Sl_rdDAck, Sl_rdDBus => mb_plb_Sl_rdDBus, Sl_rdWdAddr => mb_plb_Sl_rdWdAddr, Sl_rearbitrate => mb_plb_Sl_rearbitrate, Sl_SSize => mb_plb_Sl_SSize, Sl_wait => mb_plb_Sl_wait, Sl_wrBTerm => mb_plb_Sl_wrBTerm, Sl_wrComp => mb_plb_Sl_wrComp, Sl_wrDAck => mb_plb_Sl_wrDAck, Sl_MIRQ => mb_plb_Sl_MIRQ, PLB_MIRQ => mb_plb_PLB_MIRQ, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_BE => mb_plb_PLB_BE, PLB_MAddrAck => mb_plb_PLB_MAddrAck, PLB_MTimeout => mb_plb_PLB_MTimeout, PLB_MBusy => mb_plb_PLB_MBusy, PLB_MRdErr => mb_plb_PLB_MRdErr, PLB_MWrErr => mb_plb_PLB_MWrErr, PLB_MRdBTerm => mb_plb_PLB_MRdBTerm, PLB_MRdDAck => mb_plb_PLB_MRdDAck, PLB_MRdDBus => mb_plb_PLB_MRdDBus, PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr, PLB_MRearbitrate => mb_plb_PLB_MRearbitrate, PLB_MWrBTerm => mb_plb_PLB_MWrBTerm, PLB_MWrDAck => mb_plb_PLB_MWrDAck, PLB_MSSize => mb_plb_PLB_MSSize, PLB_PAValid => mb_plb_PLB_PAValid, PLB_RNW => mb_plb_PLB_RNW, PLB_SAValid => mb_plb_PLB_SAValid, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_TAttribute => mb_plb_PLB_TAttribute, PLB_lockErr => mb_plb_PLB_lockErr, PLB_masterID => mb_plb_PLB_masterID, PLB_MSize => mb_plb_PLB_MSize, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_rdPrim => mb_plb_PLB_rdPrim, PLB_reqPri => mb_plb_PLB_reqPri, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrPrim => mb_plb_PLB_wrPrim, PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ilmb : system_ilmb_wrapper port map ( LMB_Clk => clk_50_0000MHz, SYS_Rst => sys_bus_reset(0), LMB_Rst => ilmb_LMB_Rst, M_ABus => ilmb_M_ABus, M_ReadStrobe => ilmb_M_ReadStrobe, M_WriteStrobe => net_gnd0, M_AddrStrobe => ilmb_M_AddrStrobe, M_DBus => net_gnd32, M_BE => net_gnd4, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0 to 0), Sl_Wait => ilmb_Sl_Wait(0 to 0), Sl_UE => ilmb_Sl_UE(0 to 0), Sl_CE => ilmb_Sl_CE(0 to 0), LMB_ABus => ilmb_LMB_ABus, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadDBus => ilmb_LMB_ReadDBus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_Ready => ilmb_LMB_Ready, LMB_Wait => ilmb_LMB_Wait, LMB_UE => ilmb_LMB_UE, LMB_CE => ilmb_LMB_CE, LMB_BE => ilmb_LMB_BE ); dlmb : system_dlmb_wrapper port map ( LMB_Clk => clk_50_0000MHz, SYS_Rst => sys_bus_reset(0), LMB_Rst => dlmb_LMB_Rst, M_ABus => dlmb_M_ABus, M_ReadStrobe => dlmb_M_ReadStrobe, M_WriteStrobe => dlmb_M_WriteStrobe, M_AddrStrobe => dlmb_M_AddrStrobe, M_DBus => dlmb_M_DBus, M_BE => dlmb_M_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0 to 0), Sl_Wait => dlmb_Sl_Wait(0 to 0), Sl_UE => dlmb_Sl_UE(0 to 0), Sl_CE => dlmb_Sl_CE(0 to 0), LMB_ABus => dlmb_LMB_ABus, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadDBus => dlmb_LMB_ReadDBus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_Ready => dlmb_LMB_Ready, LMB_Wait => dlmb_LMB_Wait, LMB_UE => dlmb_LMB_UE, LMB_CE => dlmb_LMB_CE, LMB_BE => dlmb_LMB_BE ); dlmb_cntlr : system_dlmb_cntlr_wrapper port map ( LMB_Clk => clk_50_0000MHz, LMB_Rst => dlmb_LMB_Rst, LMB_ABus => dlmb_LMB_ABus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_BE => dlmb_LMB_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0), Sl_Wait => dlmb_Sl_Wait(0), Sl_UE => dlmb_Sl_UE(0), Sl_CE => dlmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => dlmb_port_BRAM_Rst, BRAM_Clk_A => dlmb_port_BRAM_Clk, BRAM_EN_A => dlmb_port_BRAM_EN, BRAM_WEN_A => dlmb_port_BRAM_WEN, BRAM_Addr_A => dlmb_port_BRAM_Addr, BRAM_Din_A => dlmb_port_BRAM_Din, BRAM_Dout_A => dlmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); ilmb_cntlr : system_ilmb_cntlr_wrapper port map ( LMB_Clk => clk_50_0000MHz, LMB_Rst => ilmb_LMB_Rst, LMB_ABus => ilmb_LMB_ABus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_BE => ilmb_LMB_BE, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0), Sl_Wait => ilmb_Sl_Wait(0), Sl_UE => ilmb_Sl_UE(0), Sl_CE => ilmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); lmb_bram : system_lmb_bram_wrapper port map ( BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, BRAM_Rst_B => dlmb_port_BRAM_Rst, BRAM_Clk_B => dlmb_port_BRAM_Clk, BRAM_EN_B => dlmb_port_BRAM_EN, BRAM_WEN_B => dlmb_port_BRAM_WEN, BRAM_Addr_B => dlmb_port_BRAM_Addr, BRAM_Din_B => dlmb_port_BRAM_Din, BRAM_Dout_B => dlmb_port_BRAM_Dout ); clock_generator_0 : system_clock_generator_0_wrapper port map ( CLKIN => CLK_S, CLKOUT0 => clk_50_0000MHz, CLKOUT1 => open, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, CLKOUT7 => open, CLKOUT8 => open, CLKOUT9 => open, CLKOUT10 => open, CLKOUT11 => open, CLKOUT12 => open, CLKOUT13 => open, CLKOUT14 => open, CLKOUT15 => open, CLKFBIN => net_gnd0, CLKFBOUT => open, PSCLK => net_gnd0, PSEN => net_gnd0, PSINCDEC => net_gnd0, PSDONE => open, RST => sys_rst_s, LOCKED => Dcm_all_locked ); mdm_0 : system_mdm_0_wrapper port map ( Interrupt => open, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => net_gnd0, S_AXI_ARESETN => net_gnd0, S_AXI_AWADDR => net_gnd32(0 to 31), S_AXI_AWVALID => net_gnd0, S_AXI_AWREADY => open, S_AXI_WDATA => net_gnd32(0 to 31), S_AXI_WSTRB => net_gnd4(0 to 3), S_AXI_WVALID => net_gnd0, S_AXI_WREADY => open, S_AXI_BRESP => open, S_AXI_BVALID => open, S_AXI_BREADY => net_gnd0, S_AXI_ARADDR => net_gnd32(0 to 31), S_AXI_ARVALID => net_gnd0, S_AXI_ARREADY => open, S_AXI_RDATA => open, S_AXI_RRESP => open, S_AXI_RVALID => open, S_AXI_RREADY => net_gnd0, SPLB_Clk => clk_50_0000MHz, SPLB_Rst => mb_plb_SPLB_Rst(0), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(0), PLB_wrPrim => mb_plb_PLB_wrPrim(0), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(0), Sl_SSize => mb_plb_Sl_SSize(0 to 1), Sl_wait => mb_plb_Sl_wait(0), Sl_rearbitrate => mb_plb_Sl_rearbitrate(0), Sl_wrDAck => mb_plb_Sl_wrDAck(0), Sl_wrComp => mb_plb_Sl_wrComp(0), Sl_wrBTerm => mb_plb_Sl_wrBTerm(0), Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 63), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3), Sl_rdDAck => mb_plb_Sl_rdDAck(0), Sl_rdComp => mb_plb_Sl_rdComp(0), Sl_rdBTerm => mb_plb_Sl_rdBTerm(0), Sl_MBusy => mb_plb_Sl_MBusy(0 to 6), Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 6), Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 6), Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 6), Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk, Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI, Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO, Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En, Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture, Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift, Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update, Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst, Dbg_Clk_1 => open, Dbg_TDI_1 => open, Dbg_TDO_1 => net_gnd0, Dbg_Reg_En_1 => open, Dbg_Capture_1 => open, Dbg_Shift_1 => open, Dbg_Update_1 => open, Dbg_Rst_1 => open, Dbg_Clk_2 => open, Dbg_TDI_2 => open, Dbg_TDO_2 => net_gnd0, Dbg_Reg_En_2 => open, Dbg_Capture_2 => open, Dbg_Shift_2 => open, Dbg_Update_2 => open, Dbg_Rst_2 => open, Dbg_Clk_3 => open, Dbg_TDI_3 => open, Dbg_TDO_3 => net_gnd0, Dbg_Reg_En_3 => open, Dbg_Capture_3 => open, Dbg_Shift_3 => open, Dbg_Update_3 => open, Dbg_Rst_3 => open, Dbg_Clk_4 => open, Dbg_TDI_4 => open, Dbg_TDO_4 => net_gnd0, Dbg_Reg_En_4 => open, Dbg_Capture_4 => open, Dbg_Shift_4 => open, Dbg_Update_4 => open, Dbg_Rst_4 => open, Dbg_Clk_5 => open, Dbg_TDI_5 => open, Dbg_TDO_5 => net_gnd0, Dbg_Reg_En_5 => open, Dbg_Capture_5 => open, Dbg_Shift_5 => open, Dbg_Update_5 => open, Dbg_Rst_5 => open, Dbg_Clk_6 => open, Dbg_TDI_6 => open, Dbg_TDO_6 => net_gnd0, Dbg_Reg_En_6 => open, Dbg_Capture_6 => open, Dbg_Shift_6 => open, Dbg_Update_6 => open, Dbg_Rst_6 => open, Dbg_Clk_7 => open, Dbg_TDI_7 => open, Dbg_TDO_7 => net_gnd0, Dbg_Reg_En_7 => open, Dbg_Capture_7 => open, Dbg_Shift_7 => open, Dbg_Update_7 => open, Dbg_Rst_7 => open, Dbg_Clk_8 => open, Dbg_TDI_8 => open, Dbg_TDO_8 => net_gnd0, Dbg_Reg_En_8 => open, Dbg_Capture_8 => open, Dbg_Shift_8 => open, Dbg_Update_8 => open, Dbg_Rst_8 => open, Dbg_Clk_9 => open, Dbg_TDI_9 => open, Dbg_TDO_9 => net_gnd0, Dbg_Reg_En_9 => open, Dbg_Capture_9 => open, Dbg_Shift_9 => open, Dbg_Update_9 => open, Dbg_Rst_9 => open, Dbg_Clk_10 => open, Dbg_TDI_10 => open, Dbg_TDO_10 => net_gnd0, Dbg_Reg_En_10 => open, Dbg_Capture_10 => open, Dbg_Shift_10 => open, Dbg_Update_10 => open, Dbg_Rst_10 => open, Dbg_Clk_11 => open, Dbg_TDI_11 => open, Dbg_TDO_11 => net_gnd0, Dbg_Reg_En_11 => open, Dbg_Capture_11 => open, Dbg_Shift_11 => open, Dbg_Update_11 => open, Dbg_Rst_11 => open, Dbg_Clk_12 => open, Dbg_TDI_12 => open, Dbg_TDO_12 => net_gnd0, Dbg_Reg_En_12 => open, Dbg_Capture_12 => open, Dbg_Shift_12 => open, Dbg_Update_12 => open, Dbg_Rst_12 => open, Dbg_Clk_13 => open, Dbg_TDI_13 => open, Dbg_TDO_13 => net_gnd0, Dbg_Reg_En_13 => open, Dbg_Capture_13 => open, Dbg_Shift_13 => open, Dbg_Update_13 => open, Dbg_Rst_13 => open, Dbg_Clk_14 => open, Dbg_TDI_14 => open, Dbg_TDO_14 => net_gnd0, Dbg_Reg_En_14 => open, Dbg_Capture_14 => open, Dbg_Shift_14 => open, Dbg_Update_14 => open, Dbg_Rst_14 => open, Dbg_Clk_15 => open, Dbg_TDI_15 => open, Dbg_TDO_15 => net_gnd0, Dbg_Reg_En_15 => open, Dbg_Capture_15 => open, Dbg_Shift_15 => open, Dbg_Update_15 => open, Dbg_Rst_15 => open, Dbg_Clk_16 => open, Dbg_TDI_16 => open, Dbg_TDO_16 => net_gnd0, Dbg_Reg_En_16 => open, Dbg_Capture_16 => open, Dbg_Shift_16 => open, Dbg_Update_16 => open, Dbg_Rst_16 => open, Dbg_Clk_17 => open, Dbg_TDI_17 => open, Dbg_TDO_17 => net_gnd0, Dbg_Reg_En_17 => open, Dbg_Capture_17 => open, Dbg_Shift_17 => open, Dbg_Update_17 => open, Dbg_Rst_17 => open, Dbg_Clk_18 => open, Dbg_TDI_18 => open, Dbg_TDO_18 => net_gnd0, Dbg_Reg_En_18 => open, Dbg_Capture_18 => open, Dbg_Shift_18 => open, Dbg_Update_18 => open, Dbg_Rst_18 => open, Dbg_Clk_19 => open, Dbg_TDI_19 => open, Dbg_TDO_19 => net_gnd0, Dbg_Reg_En_19 => open, Dbg_Capture_19 => open, Dbg_Shift_19 => open, Dbg_Update_19 => open, Dbg_Rst_19 => open, Dbg_Clk_20 => open, Dbg_TDI_20 => open, Dbg_TDO_20 => net_gnd0, Dbg_Reg_En_20 => open, Dbg_Capture_20 => open, Dbg_Shift_20 => open, Dbg_Update_20 => open, Dbg_Rst_20 => open, Dbg_Clk_21 => open, Dbg_TDI_21 => open, Dbg_TDO_21 => net_gnd0, Dbg_Reg_En_21 => open, Dbg_Capture_21 => open, Dbg_Shift_21 => open, Dbg_Update_21 => open, Dbg_Rst_21 => open, Dbg_Clk_22 => open, Dbg_TDI_22 => open, Dbg_TDO_22 => net_gnd0, Dbg_Reg_En_22 => open, Dbg_Capture_22 => open, Dbg_Shift_22 => open, Dbg_Update_22 => open, Dbg_Rst_22 => open, Dbg_Clk_23 => open, Dbg_TDI_23 => open, Dbg_TDO_23 => net_gnd0, Dbg_Reg_En_23 => open, Dbg_Capture_23 => open, Dbg_Shift_23 => open, Dbg_Update_23 => open, Dbg_Rst_23 => open, Dbg_Clk_24 => open, Dbg_TDI_24 => open, Dbg_TDO_24 => net_gnd0, Dbg_Reg_En_24 => open, Dbg_Capture_24 => open, Dbg_Shift_24 => open, Dbg_Update_24 => open, Dbg_Rst_24 => open, Dbg_Clk_25 => open, Dbg_TDI_25 => open, Dbg_TDO_25 => net_gnd0, Dbg_Reg_En_25 => open, Dbg_Capture_25 => open, Dbg_Shift_25 => open, Dbg_Update_25 => open, Dbg_Rst_25 => open, Dbg_Clk_26 => open, Dbg_TDI_26 => open, Dbg_TDO_26 => net_gnd0, Dbg_Reg_En_26 => open, Dbg_Capture_26 => open, Dbg_Shift_26 => open, Dbg_Update_26 => open, Dbg_Rst_26 => open, Dbg_Clk_27 => open, Dbg_TDI_27 => open, Dbg_TDO_27 => net_gnd0, Dbg_Reg_En_27 => open, Dbg_Capture_27 => open, Dbg_Shift_27 => open, Dbg_Update_27 => open, Dbg_Rst_27 => open, Dbg_Clk_28 => open, Dbg_TDI_28 => open, Dbg_TDO_28 => net_gnd0, Dbg_Reg_En_28 => open, Dbg_Capture_28 => open, Dbg_Shift_28 => open, Dbg_Update_28 => open, Dbg_Rst_28 => open, Dbg_Clk_29 => open, Dbg_TDI_29 => open, Dbg_TDO_29 => net_gnd0, Dbg_Reg_En_29 => open, Dbg_Capture_29 => open, Dbg_Shift_29 => open, Dbg_Update_29 => open, Dbg_Rst_29 => open, Dbg_Clk_30 => open, Dbg_TDI_30 => open, Dbg_TDO_30 => net_gnd0, Dbg_Reg_En_30 => open, Dbg_Capture_30 => open, Dbg_Shift_30 => open, Dbg_Update_30 => open, Dbg_Rst_30 => open, Dbg_Clk_31 => open, Dbg_TDI_31 => open, Dbg_TDO_31 => net_gnd0, Dbg_Reg_En_31 => open, Dbg_Capture_31 => open, Dbg_Shift_31 => open, Dbg_Update_31 => open, Dbg_Rst_31 => open, bscan_tdi => open, bscan_reset => open, bscan_shift => open, bscan_update => open, bscan_capture => open, bscan_sel1 => open, bscan_drck1 => open, bscan_tdo1 => net_gnd0, bscan_ext_tdi => net_gnd0, bscan_ext_reset => net_gnd0, bscan_ext_shift => net_gnd0, bscan_ext_update => net_gnd0, bscan_ext_capture => net_gnd0, bscan_ext_sel => net_gnd0, bscan_ext_drck => net_gnd0, bscan_ext_tdo => open, Ext_JTAG_DRCK => open, Ext_JTAG_RESET => open, Ext_JTAG_SEL => open, Ext_JTAG_CAPTURE => open, Ext_JTAG_SHIFT => open, Ext_JTAG_UPDATE => open, Ext_JTAG_TDI => open, Ext_JTAG_TDO => net_gnd0 ); proc_sys_reset_0 : system_proc_sys_reset_0_wrapper port map ( Slowest_sync_clk => clk_50_0000MHz, Ext_Reset_In => sys_rst_s, Aux_Reset_In => net_gnd0, MB_Debug_Sys_Rst => Debug_SYS_Rst, Core_Reset_Req_0 => net_gnd0, Chip_Reset_Req_0 => net_gnd0, System_Reset_Req_0 => net_gnd0, Core_Reset_Req_1 => net_gnd0, Chip_Reset_Req_1 => net_gnd0, System_Reset_Req_1 => net_gnd0, Dcm_locked => Dcm_all_locked, RstcPPCresetcore_0 => open, RstcPPCresetchip_0 => open, RstcPPCresetsys_0 => open, RstcPPCresetcore_1 => open, RstcPPCresetchip_1 => open, RstcPPCresetsys_1 => open, MB_Reset => mb_reset, Bus_Struct_Reset => sys_bus_reset(0 to 0), Peripheral_Reset => sys_periph_reset(0 to 0), Interconnect_aresetn => open, Peripheral_aresetn => open ); nfa_accept_samples_generic_hw_top_0 : system_nfa_accept_samples_generic_hw_top_0_wrapper port map ( aclk => clk_50_0000MHz, aresetn => sys_periph_reset(0), indices_MPLB_Clk => clk_50_0000MHz, indices_MPLB_Rst => mb_plb_MPLB_Rst(2), indices_M_request => mb_plb_M_request(2), indices_M_priority => mb_plb_M_priority(4 to 5), indices_M_busLock => mb_plb_M_busLock(2), indices_M_RNW => mb_plb_M_RNW(2), indices_M_BE => mb_plb_M_BE(16 to 23), indices_M_MSize => mb_plb_M_MSize(4 to 5), indices_M_size => mb_plb_M_size(8 to 11), indices_M_type => mb_plb_M_type(6 to 8), indices_M_TAttribute => mb_plb_M_TAttribute(32 to 47), indices_M_lockErr => mb_plb_M_lockErr(2), indices_M_abort => mb_plb_M_ABort(2), indices_M_UABus => mb_plb_M_UABus(64 to 95), indices_M_ABus => mb_plb_M_ABus(64 to 95), indices_M_wrDBus => mb_plb_M_wrDBus(128 to 191), indices_M_wrBurst => mb_plb_M_wrBurst(2), indices_M_rdBurst => mb_plb_M_rdBurst(2), indices_PLB_MAddrAck => mb_plb_PLB_MAddrAck(2), indices_PLB_MSSize => mb_plb_PLB_MSSize(4 to 5), indices_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(2), indices_PLB_MTimeout => mb_plb_PLB_MTimeout(2), indices_PLB_MBusy => mb_plb_PLB_MBusy(2), indices_PLB_MRdErr => mb_plb_PLB_MRdErr(2), indices_PLB_MWrErr => mb_plb_PLB_MWrErr(2), indices_PLB_MIRQ => mb_plb_PLB_MIRQ(2), indices_PLB_MRdDBus => mb_plb_PLB_MRdDBus(128 to 191), indices_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(8 to 11), indices_PLB_MRdDAck => mb_plb_PLB_MRdDAck(2), indices_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(2), indices_PLB_MWrDAck => mb_plb_PLB_MWrDAck(2), indices_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(2), nfa_finals_buckets_MPLB_Clk => clk_50_0000MHz, nfa_finals_buckets_MPLB_Rst => mb_plb_MPLB_Rst(3), nfa_finals_buckets_M_request => mb_plb_M_request(3), nfa_finals_buckets_M_priority => mb_plb_M_priority(6 to 7), nfa_finals_buckets_M_busLock => mb_plb_M_busLock(3), nfa_finals_buckets_M_RNW => mb_plb_M_RNW(3), nfa_finals_buckets_M_BE => mb_plb_M_BE(24 to 31), nfa_finals_buckets_M_MSize => mb_plb_M_MSize(6 to 7), nfa_finals_buckets_M_size => mb_plb_M_size(12 to 15), nfa_finals_buckets_M_type => mb_plb_M_type(9 to 11), nfa_finals_buckets_M_TAttribute => mb_plb_M_TAttribute(48 to 63), nfa_finals_buckets_M_lockErr => mb_plb_M_lockErr(3), nfa_finals_buckets_M_abort => mb_plb_M_ABort(3), nfa_finals_buckets_M_UABus => mb_plb_M_UABus(96 to 127), nfa_finals_buckets_M_ABus => mb_plb_M_ABus(96 to 127), nfa_finals_buckets_M_wrDBus => mb_plb_M_wrDBus(192 to 255), nfa_finals_buckets_M_wrBurst => mb_plb_M_wrBurst(3), nfa_finals_buckets_M_rdBurst => mb_plb_M_rdBurst(3), nfa_finals_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(3), nfa_finals_buckets_PLB_MSSize => mb_plb_PLB_MSSize(6 to 7), nfa_finals_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(3), nfa_finals_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(3), nfa_finals_buckets_PLB_MBusy => mb_plb_PLB_MBusy(3), nfa_finals_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(3), nfa_finals_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(3), nfa_finals_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(3), nfa_finals_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(192 to 255), nfa_finals_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(12 to 15), nfa_finals_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(3), nfa_finals_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(3), nfa_finals_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(3), nfa_finals_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(3), nfa_forward_buckets_MPLB_Clk => clk_50_0000MHz, nfa_forward_buckets_MPLB_Rst => mb_plb_MPLB_Rst(4), nfa_forward_buckets_M_request => mb_plb_M_request(4), nfa_forward_buckets_M_priority => mb_plb_M_priority(8 to 9), nfa_forward_buckets_M_busLock => mb_plb_M_busLock(4), nfa_forward_buckets_M_RNW => mb_plb_M_RNW(4), nfa_forward_buckets_M_BE => mb_plb_M_BE(32 to 39), nfa_forward_buckets_M_MSize => mb_plb_M_MSize(8 to 9), nfa_forward_buckets_M_size => mb_plb_M_size(16 to 19), nfa_forward_buckets_M_type => mb_plb_M_type(12 to 14), nfa_forward_buckets_M_TAttribute => mb_plb_M_TAttribute(64 to 79), nfa_forward_buckets_M_lockErr => mb_plb_M_lockErr(4), nfa_forward_buckets_M_abort => mb_plb_M_ABort(4), nfa_forward_buckets_M_UABus => mb_plb_M_UABus(128 to 159), nfa_forward_buckets_M_ABus => mb_plb_M_ABus(128 to 159), nfa_forward_buckets_M_wrDBus => mb_plb_M_wrDBus(256 to 319), nfa_forward_buckets_M_wrBurst => mb_plb_M_wrBurst(4), nfa_forward_buckets_M_rdBurst => mb_plb_M_rdBurst(4), nfa_forward_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(4), nfa_forward_buckets_PLB_MSSize => mb_plb_PLB_MSSize(8 to 9), nfa_forward_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(4), nfa_forward_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(4), nfa_forward_buckets_PLB_MBusy => mb_plb_PLB_MBusy(4), nfa_forward_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(4), nfa_forward_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(4), nfa_forward_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(4), nfa_forward_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(256 to 319), nfa_forward_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(16 to 19), nfa_forward_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(4), nfa_forward_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(4), nfa_forward_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(4), nfa_forward_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(4), nfa_initials_buckets_MPLB_Clk => clk_50_0000MHz, nfa_initials_buckets_MPLB_Rst => mb_plb_MPLB_Rst(5), nfa_initials_buckets_M_request => mb_plb_M_request(5), nfa_initials_buckets_M_priority => mb_plb_M_priority(10 to 11), nfa_initials_buckets_M_busLock => mb_plb_M_busLock(5), nfa_initials_buckets_M_RNW => mb_plb_M_RNW(5), nfa_initials_buckets_M_BE => mb_plb_M_BE(40 to 47), nfa_initials_buckets_M_MSize => mb_plb_M_MSize(10 to 11), nfa_initials_buckets_M_size => mb_plb_M_size(20 to 23), nfa_initials_buckets_M_type => mb_plb_M_type(15 to 17), nfa_initials_buckets_M_TAttribute => mb_plb_M_TAttribute(80 to 95), nfa_initials_buckets_M_lockErr => mb_plb_M_lockErr(5), nfa_initials_buckets_M_abort => mb_plb_M_ABort(5), nfa_initials_buckets_M_UABus => mb_plb_M_UABus(160 to 191), nfa_initials_buckets_M_ABus => mb_plb_M_ABus(160 to 191), nfa_initials_buckets_M_wrDBus => mb_plb_M_wrDBus(320 to 383), nfa_initials_buckets_M_wrBurst => mb_plb_M_wrBurst(5), nfa_initials_buckets_M_rdBurst => mb_plb_M_rdBurst(5), nfa_initials_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(5), nfa_initials_buckets_PLB_MSSize => mb_plb_PLB_MSSize(10 to 11), nfa_initials_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(5), nfa_initials_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(5), nfa_initials_buckets_PLB_MBusy => mb_plb_PLB_MBusy(5), nfa_initials_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(5), nfa_initials_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(5), nfa_initials_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(5), nfa_initials_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(320 to 383), nfa_initials_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(20 to 23), nfa_initials_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(5), nfa_initials_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(5), nfa_initials_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(5), nfa_initials_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(5), sample_buffer_MPLB_Clk => clk_50_0000MHz, sample_buffer_MPLB_Rst => mb_plb_MPLB_Rst(6), sample_buffer_M_request => mb_plb_M_request(6), sample_buffer_M_priority => mb_plb_M_priority(12 to 13), sample_buffer_M_busLock => mb_plb_M_busLock(6), sample_buffer_M_RNW => mb_plb_M_RNW(6), sample_buffer_M_BE => mb_plb_M_BE(48 to 55), sample_buffer_M_MSize => mb_plb_M_MSize(12 to 13), sample_buffer_M_size => mb_plb_M_size(24 to 27), sample_buffer_M_type => mb_plb_M_type(18 to 20), sample_buffer_M_TAttribute => mb_plb_M_TAttribute(96 to 111), sample_buffer_M_lockErr => mb_plb_M_lockErr(6), sample_buffer_M_abort => mb_plb_M_ABort(6), sample_buffer_M_UABus => mb_plb_M_UABus(192 to 223), sample_buffer_M_ABus => mb_plb_M_ABus(192 to 223), sample_buffer_M_wrDBus => mb_plb_M_wrDBus(384 to 447), sample_buffer_M_wrBurst => mb_plb_M_wrBurst(6), sample_buffer_M_rdBurst => mb_plb_M_rdBurst(6), sample_buffer_PLB_MAddrAck => mb_plb_PLB_MAddrAck(6), sample_buffer_PLB_MSSize => mb_plb_PLB_MSSize(12 to 13), sample_buffer_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(6), sample_buffer_PLB_MTimeout => mb_plb_PLB_MTimeout(6), sample_buffer_PLB_MBusy => mb_plb_PLB_MBusy(6), sample_buffer_PLB_MRdErr => mb_plb_PLB_MRdErr(6), sample_buffer_PLB_MWrErr => mb_plb_PLB_MWrErr(6), sample_buffer_PLB_MIRQ => mb_plb_PLB_MIRQ(6), sample_buffer_PLB_MRdDBus => mb_plb_PLB_MRdDBus(384 to 447), sample_buffer_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(24 to 27), sample_buffer_PLB_MRdDAck => mb_plb_PLB_MRdDAck(6), sample_buffer_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(6), sample_buffer_PLB_MWrDAck => mb_plb_PLB_MWrDAck(6), sample_buffer_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(6), splb_slv0_SPLB_Clk => clk_50_0000MHz, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(1), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(1), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(1), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(1), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(2 to 3), splb_slv0_Sl_wait => mb_plb_Sl_wait(1), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(1), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(1), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(1), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(1), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 127), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(1), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(1), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(1), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(7 to 13), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(7 to 13), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(7 to 13), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(7 to 13) ); end architecture STRUCTURE;
lgpl-3.0
83cff50b41456654cb970518a741455e
0.597991
2.912972
false
false
false
false
grwlf/vsim
vhdl_ct/ct00343.vhd
1
40,250
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00343 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00343(ARCH00343) -- ENT00343_Test_Bench(ARCH00343_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00343 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr2 : inout st_arr2 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; -- end ENT00343 ; -- -- architecture ARCH00343 of ENT00343 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; -- begin CHG1 : process ( s_st_boolean_vector ) variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns, -- c_st_boolean_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_boolean_vector_select <= transport 2 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns , -- c_st_boolean_vector_1(lowb) after 20 ns , -- c_st_boolean_vector_2(lowb) after 30 ns , -- c_st_boolean_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; st_boolean_vector_select <= transport 3 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_1(lowb) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_boolean_vector_savt <= transport Std.Standard.Now ; chk_st_boolean_vector <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_boolean_vector(lowb) <= transport c_st_boolean_vector_2(lowb) after 10 ns, c_st_boolean_vector_1(lowb) after 20 ns when st_boolean_vector_select = 1 else -- c_st_boolean_vector_2(lowb) after 10 ns , c_st_boolean_vector_1(lowb) after 20 ns , c_st_boolean_vector_2(lowb) after 30 ns , c_st_boolean_vector_1(lowb) after 40 ns when st_boolean_vector_select = 2 else -- c_st_boolean_vector_1(lowb) after 5 ns ; -- CHG2 : process ( s_st_severity_level_vector ) variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns, -- c_st_severity_level_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_severity_level_vector_select <= transport 2 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns , -- c_st_severity_level_vector_1(lowb) after 20 ns , -- c_st_severity_level_vector_2(lowb) after 30 ns , -- c_st_severity_level_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; st_severity_level_vector_select <= transport 3 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_1(lowb) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_severity_level_vector_savt <= transport Std.Standard.Now ; chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_severity_level_vector(lowb) <= transport c_st_severity_level_vector_2(lowb) after 10 ns, c_st_severity_level_vector_1(lowb) after 20 ns when st_severity_level_vector_select = 1 else -- c_st_severity_level_vector_2(lowb) after 10 ns , c_st_severity_level_vector_1(lowb) after 20 ns , c_st_severity_level_vector_2(lowb) after 30 ns , c_st_severity_level_vector_1(lowb) after 40 ns when st_severity_level_vector_select = 2 else -- c_st_severity_level_vector_1(lowb) after 5 ns ; -- CHG3 : process ( s_st_string ) variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns, -- c_st_string_1(highb) after 20 ns ; -- when 1 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_string_select <= transport 2 ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns , -- c_st_string_1(highb) after 20 ns , -- c_st_string_2(highb) after 30 ns , -- c_st_string_1(highb) after 40 ns ; -- when 3 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; st_string_select <= transport 3 ; -- s_st_string(highb) <= transport -- c_st_string_1(highb) after 5 ns ; -- when 4 => correct := correct and s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_string_savt <= transport Std.Standard.Now ; chk_st_string <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; s_st_string_cnt <= transport s_st_string_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_string(highb) <= transport c_st_string_2(highb) after 10 ns, c_st_string_1(highb) after 20 ns when st_string_select = 1 else -- c_st_string_2(highb) after 10 ns , c_st_string_1(highb) after 20 ns , c_st_string_2(highb) after 30 ns , c_st_string_1(highb) after 40 ns when st_string_select = 2 else -- c_st_string_1(highb) after 5 ns ; -- CHG4 : process ( s_st_enum1_vector ) variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns, -- c_st_enum1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_vector_select <= transport 2 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns , -- c_st_enum1_vector_1(highb) after 20 ns , -- c_st_enum1_vector_2(highb) after 30 ns , -- c_st_enum1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; st_enum1_vector_select <= transport 3 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_1(highb) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_enum1_vector_savt <= transport Std.Standard.Now ; chk_st_enum1_vector <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_st_enum1_vector(highb) <= transport c_st_enum1_vector_2(highb) after 10 ns, c_st_enum1_vector_1(highb) after 20 ns when st_enum1_vector_select = 1 else -- c_st_enum1_vector_2(highb) after 10 ns , c_st_enum1_vector_1(highb) after 20 ns , c_st_enum1_vector_2(highb) after 30 ns , c_st_enum1_vector_1(highb) after 40 ns when st_enum1_vector_select = 2 else -- c_st_enum1_vector_1(highb) after 5 ns ; -- CHG5 : process ( s_st_integer_vector ) variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns, -- c_st_integer_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_integer_vector_select <= transport 2 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns , -- c_st_integer_vector_1(lowb) after 20 ns , -- c_st_integer_vector_2(lowb) after 30 ns , -- c_st_integer_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; st_integer_vector_select <= transport 3 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_1(lowb) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_integer_vector_savt <= transport Std.Standard.Now ; chk_st_integer_vector <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_integer_vector(lowb) <= transport c_st_integer_vector_2(lowb) after 10 ns, c_st_integer_vector_1(lowb) after 20 ns when st_integer_vector_select = 1 else -- c_st_integer_vector_2(lowb) after 10 ns , c_st_integer_vector_1(lowb) after 20 ns , c_st_integer_vector_2(lowb) after 30 ns , c_st_integer_vector_1(lowb) after 40 ns when st_integer_vector_select = 2 else -- c_st_integer_vector_1(lowb) after 5 ns ; -- CHG6 : process ( s_st_time_vector ) variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns, -- c_st_time_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_time_vector_select <= transport 2 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns , -- c_st_time_vector_1(lowb) after 20 ns , -- c_st_time_vector_2(lowb) after 30 ns , -- c_st_time_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; st_time_vector_select <= transport 3 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_1(lowb) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_time_vector_savt <= transport Std.Standard.Now ; chk_st_time_vector <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_st_time_vector(lowb) <= transport c_st_time_vector_2(lowb) after 10 ns, c_st_time_vector_1(lowb) after 20 ns when st_time_vector_select = 1 else -- c_st_time_vector_2(lowb) after 10 ns , c_st_time_vector_1(lowb) after 20 ns , c_st_time_vector_2(lowb) after 30 ns , c_st_time_vector_1(lowb) after 40 ns when st_time_vector_select = 2 else -- c_st_time_vector_1(lowb) after 5 ns ; -- CHG7 : process ( s_st_real_vector ) variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns, -- c_st_real_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real_vector_select <= transport 2 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns , -- c_st_real_vector_1(highb) after 20 ns , -- c_st_real_vector_2(highb) after 30 ns , -- c_st_real_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; st_real_vector_select <= transport 3 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_1(highb) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_real_vector_savt <= transport Std.Standard.Now ; chk_st_real_vector <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_real_vector(highb) <= transport c_st_real_vector_2(highb) after 10 ns, c_st_real_vector_1(highb) after 20 ns when st_real_vector_select = 1 else -- c_st_real_vector_2(highb) after 10 ns , c_st_real_vector_1(highb) after 20 ns , c_st_real_vector_2(highb) after 30 ns , c_st_real_vector_1(highb) after 40 ns when st_real_vector_select = 2 else -- c_st_real_vector_1(highb) after 5 ns ; -- CHG8 : process ( s_st_rec1_vector ) variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns, -- c_st_rec1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns , -- c_st_rec1_vector_1(highb) after 20 ns , -- c_st_rec1_vector_2(highb) after 30 ns , -- c_st_rec1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_1(highb) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_st_rec1_vector(highb) <= transport c_st_rec1_vector_2(highb) after 10 ns, c_st_rec1_vector_1(highb) after 20 ns when st_rec1_vector_select = 1 else -- c_st_rec1_vector_2(highb) after 10 ns , c_st_rec1_vector_1(highb) after 20 ns , c_st_rec1_vector_2(highb) after 30 ns , c_st_rec1_vector_1(highb) after 40 ns when st_rec1_vector_select = 2 else -- c_st_rec1_vector_1(highb) after 5 ns ; -- CHG9 : process ( s_st_arr2_vector ) variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns, -- c_st_arr2_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_vector_select <= transport 2 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns , -- c_st_arr2_vector_1(lowb) after 20 ns , -- c_st_arr2_vector_2(lowb) after 30 ns , -- c_st_arr2_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; st_arr2_vector_select <= transport 3 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_1(lowb) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr2_vector_savt <= transport Std.Standard.Now ; chk_st_arr2_vector <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_arr2_vector(lowb) <= transport c_st_arr2_vector_2(lowb) after 10 ns, c_st_arr2_vector_1(lowb) after 20 ns when st_arr2_vector_select = 1 else -- c_st_arr2_vector_2(lowb) after 10 ns , c_st_arr2_vector_1(lowb) after 20 ns , c_st_arr2_vector_2(lowb) after 30 ns , c_st_arr2_vector_1(lowb) after 40 ns when st_arr2_vector_select = 2 else -- c_st_arr2_vector_1(lowb) after 5 ns ; -- CHG10 : process ( s_st_arr2 ) variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns, -- c_st_arr2_1(highb,false) after 20 ns ; -- when 1 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00343.P10" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns , -- c_st_arr2_1(highb,false) after 20 ns , -- c_st_arr2_2(highb,false) after 30 ns , -- c_st_arr2_1(highb,false) after 40 ns ; -- when 3 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_1(highb,false) after 5 ns ; -- when 4 => correct := correct and s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00343" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00343" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions completed entirely", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_st_arr2(highb,false) <= transport c_st_arr2_2(highb,false) after 10 ns, c_st_arr2_1(highb,false) after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2(highb,false) after 10 ns , c_st_arr2_1(highb,false) after 20 ns , c_st_arr2_2(highb,false) after 30 ns , c_st_arr2_1(highb,false) after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1(highb,false) after 5 ns ; -- end ARCH00343 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00343_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; -- end ENT00343_Test_Bench ; -- -- architecture ARCH00343_Test_Bench of ENT00343_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr2 : inout st_arr2 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00343 ( ARCH00343 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector , s_st_arr2 ) ; end block L1 ; end ARCH00343_Test_Bench ;
gpl-3.0
a2c61b99c617b9027f3d21ca9bb5768d
0.518112
3.398345
false
true
false
false
grwlf/vsim
vhdl_ct/ct00237.vhd
1
9,432
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00237 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (6) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00237) -- ENT00237_Test_Bench(ARCH00237_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES ; use STANDARD_TYPES.test_report, STANDARD_TYPES.switch, STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle, STANDARD_TYPES."=" ; architecture ARCH00237 of GENERIC_STANDARD_TYPES is signal i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; signal i_bit_1, i_bit_2 : bit := c_bit_1 ; signal i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; signal i_character_1, i_character_2 : character := c_character_1 ; signal i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; signal i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; signal i_integer_1, i_integer_2 : integer := c_integer_1 ; signal i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; signal i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; signal i_time_1, i_time_2 : time := c_time_1 ; signal i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; signal i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; signal i_real_1, i_real_2 : real := c_real_1 ; signal i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; signal i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ; -- begin L1: block port ( toggle : buffer switch := down; i_boolean_1, i_boolean_2 : buffer boolean := c_boolean_1 ; i_bit_1, i_bit_2 : buffer bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : buffer severity_level := c_severity_level_1 ; i_character_1, i_character_2 : buffer character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : buffer t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : buffer st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : buffer integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : buffer t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : buffer st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : buffer time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : buffer t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : buffer st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : buffer real := c_real_1 ; i_t_real1_1, i_t_real1_2 : buffer t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : buffer st_real1 := c_st_real1_1 ) ; port map ( toggle , i_boolean_1, i_boolean_2, i_bit_1, i_bit_2, i_severity_level_1, i_severity_level_2, i_character_1, i_character_2, i_t_enum1_1, i_t_enum1_2, i_st_enum1_1, i_st_enum1_2, i_integer_1, i_integer_2, i_t_int1_1, i_t_int1_2, i_st_int1_1, i_st_int1_2, i_time_1, i_time_2, i_t_phys1_1, i_t_phys1_2, i_st_phys1_1, i_st_phys1_2, i_real_1, i_real_2, i_t_real1_1, i_t_real1_2, i_st_real1_1, i_st_real1_2 ) ; -- begin process variable correct : boolean := true ; begin correct := correct and i_boolean_1 = c_boolean_1 and i_boolean_2 = c_boolean_1 ; correct := correct and i_bit_1 = c_bit_1 and i_bit_2 = c_bit_1 ; correct := correct and i_severity_level_1 = c_severity_level_1 and i_severity_level_2 = c_severity_level_1 ; correct := correct and i_character_1 = c_character_1 and i_character_2 = c_character_1 ; correct := correct and i_t_enum1_1 = c_t_enum1_1 and i_t_enum1_2 = c_t_enum1_1 ; correct := correct and i_st_enum1_1 = c_st_enum1_1 and i_st_enum1_2 = c_st_enum1_1 ; correct := correct and i_integer_1 = c_integer_1 and i_integer_2 = c_integer_1 ; correct := correct and i_t_int1_1 = c_t_int1_1 and i_t_int1_2 = c_t_int1_1 ; correct := correct and i_st_int1_1 = c_st_int1_1 and i_st_int1_2 = c_st_int1_1 ; correct := correct and i_time_1 = c_time_1 and i_time_2 = c_time_1 ; correct := correct and i_t_phys1_1 = c_t_phys1_1 and i_t_phys1_2 = c_t_phys1_1 ; correct := correct and i_st_phys1_1 = c_st_phys1_1 and i_st_phys1_2 = c_st_phys1_1 ; correct := correct and i_real_1 = c_real_1 and i_real_2 = c_real_1 ; correct := correct and i_t_real1_1 = c_t_real1_1 and i_t_real1_2 = c_t_real1_1 ; correct := correct and i_st_real1_1 = c_st_real1_1 and i_st_real1_2 = c_st_real1_1 ; -- test_report ( "ENT00237" , "Associated scalar buffer ports with generic subtypes" , correct) ; -- toggle <= up ; i_boolean_1 <= c_boolean_2 ; i_boolean_2 <= c_boolean_2 ; i_bit_1 <= c_bit_2 ; i_bit_2 <= c_bit_2 ; i_severity_level_1 <= c_severity_level_2 ; i_severity_level_2 <= c_severity_level_2 ; i_character_1 <= c_character_2 ; i_character_2 <= c_character_2 ; i_t_enum1_1 <= c_t_enum1_2 ; i_t_enum1_2 <= c_t_enum1_2 ; i_st_enum1_1 <= c_st_enum1_2 ; i_st_enum1_2 <= c_st_enum1_2 ; i_integer_1 <= c_integer_2 ; i_integer_2 <= c_integer_2 ; i_t_int1_1 <= c_t_int1_2 ; i_t_int1_2 <= c_t_int1_2 ; i_st_int1_1 <= c_st_int1_2 ; i_st_int1_2 <= c_st_int1_2 ; i_time_1 <= c_time_2 ; i_time_2 <= c_time_2 ; i_t_phys1_1 <= c_t_phys1_2 ; i_t_phys1_2 <= c_t_phys1_2 ; i_st_phys1_1 <= c_st_phys1_2 ; i_st_phys1_2 <= c_st_phys1_2 ; i_real_1 <= c_real_2 ; i_real_2 <= c_real_2 ; i_t_real1_1 <= c_t_real1_2 ; i_t_real1_2 <= c_t_real1_2 ; i_st_real1_1 <= c_st_real1_2 ; i_st_real1_2 <= c_st_real1_2 ; wait ; end process ; end block L1 ; P00237 : process ( toggle ) variable correct : boolean := true ; begin if toggle = up then correct := correct and i_boolean_1 = c_boolean_2 and i_boolean_2 = c_boolean_2 ; correct := correct and i_bit_1 = c_bit_2 and i_bit_2 = c_bit_2 ; correct := correct and i_severity_level_1 = c_severity_level_2 and i_severity_level_2 = c_severity_level_2 ; correct := correct and i_character_1 = c_character_2 and i_character_2 = c_character_2 ; correct := correct and i_t_enum1_1 = c_t_enum1_2 and i_t_enum1_2 = c_t_enum1_2 ; correct := correct and i_st_enum1_1 = c_st_enum1_2 and i_st_enum1_2 = c_st_enum1_2 ; correct := correct and i_integer_1 = c_integer_2 and i_integer_2 = c_integer_2 ; correct := correct and i_t_int1_1 = c_t_int1_2 and i_t_int1_2 = c_t_int1_2 ; correct := correct and i_st_int1_1 = c_st_int1_2 and i_st_int1_2 = c_st_int1_2 ; correct := correct and i_time_1 = c_time_2 and i_time_2 = c_time_2 ; correct := correct and i_t_phys1_1 = c_t_phys1_2 and i_t_phys1_2 = c_t_phys1_2 ; correct := correct and i_st_phys1_1 = c_st_phys1_2 and i_st_phys1_2 = c_st_phys1_2 ; correct := correct and i_real_1 = c_real_2 and i_real_2 = c_real_2 ; correct := correct and i_t_real1_1 = c_t_real1_2 and i_t_real1_2 = c_t_real1_2 ; correct := correct and i_st_real1_1 = c_st_real1_2 and i_st_real1_2 = c_st_real1_2 ; end if ; -- test_report ( "ENT00237.P00237" , "Associated scalar buffer ports with generic subtypes", correct) ; end process P00237 ; end ARCH00237 ; -- entity ENT00237_Test_Bench is end ENT00237_Test_Bench ; -- architecture ARCH00237_Test_Bench of ENT00237_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00237 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00237_Test_Bench ;
gpl-3.0
b2ac52976aa6bc972f8f96dcb70e1864
0.481446
2.887052
false
false
false
false
grwlf/vsim
vhdl_ct/ct00392.vhd
1
70,588
-- NEED RESULT: ARCH00392.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P4: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P5: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P6: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P7: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P8: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392.P9: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00392: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P9: Inertial transactions completed entirely passed -- NEED RESULT: P8: Inertial transactions completed entirely passed -- NEED RESULT: P7: Inertial transactions completed entirely passed -- NEED RESULT: P6: Inertial transactions completed entirely passed -- NEED RESULT: P5: Inertial transactions completed entirely passed -- NEED RESULT: P4: Inertial transactions completed entirely passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00392 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00392(ARCH00392) -- ENT00392_Test_Bench(ARCH00392_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00392 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; -- end ENT00392 ; -- -- architecture ARCH00392 of ENT00392 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns, -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_boolean_vector_select <= transport 2 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; st_boolean_vector_select <= transport 3 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 4 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 5 ; -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_boolean_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_boolean_vector(lowb to highb-1) <= -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_boolean_vector_savt <= transport Std.Standard.Now ; chk_st_boolean_vector <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ; wait until (not s_st_boolean_vector(lowb to highb-1)'Quiet) and (s_st_boolean_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_boolean_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_boolean_vector(lowb to highb-1) <= c_st_boolean_vector_2(lowb to highb-1) after 10 ns, c_st_boolean_vector_1(lowb to highb-1) after 20 ns when st_boolean_vector_select = 1 else -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when st_boolean_vector_select = 2 else -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns when st_boolean_vector_select = 3 else -- c_st_boolean_vector_1(lowb to highb-1) after 100 ns when st_boolean_vector_select = 4 else -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when st_boolean_vector_select = 5 else -- -- Last transaction above is marked c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_severity_level_vector_select <= transport 2 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; st_severity_level_vector_select <= transport 3 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 4 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 5 ; -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_severity_level_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_severity_level_vector(lowb to highb-1) <= -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_severity_level_vector_savt <= transport Std.Standard.Now ; chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt + 1 ; wait until (not s_st_severity_level_vector(lowb to highb-1)'Quiet) and (s_st_severity_level_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_severity_level_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_severity_level_vector(lowb to highb-1) <= c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, c_st_severity_level_vector_1(lowb to highb-1) after 20 ns when st_severity_level_vector_select = 1 else -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when st_severity_level_vector_select = 2 else -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when st_severity_level_vector_select = 3 else -- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns when st_severity_level_vector_select = 4 else -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when st_severity_level_vector_select = 5 else -- -- Last transaction above is marked c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns, -- c_st_string_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_string_select <= transport 2 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; st_string_select <= transport 3 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 4 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 5 ; -- s_st_string(highb-1 to highb-1) <= -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_string_select <= transport 6 ; -- Last transaction above is marked -- s_st_string(highb-1 to highb-1) <= -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_string_savt <= transport Std.Standard.Now ; chk_st_string <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; s_st_string_cnt <= transport s_st_string_cnt + 1 ; wait until (not s_st_string(highb-1 to highb-1)'Quiet) and (s_st_string_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_st_string = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_string(highb-1 to highb-1) <= c_st_string_2(highb-1 to highb-1) after 10 ns, c_st_string_1(highb-1 to highb-1) after 20 ns when st_string_select = 1 else -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when st_string_select = 2 else -- c_st_string_1(highb-1 to highb-1) after 5 ns when st_string_select = 3 else -- c_st_string_1(highb-1 to highb-1) after 100 ns when st_string_select = 4 else -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when st_string_select = 5 else -- -- Last transaction above is marked c_st_string_1(highb-1 to highb-1) after 40 ns ; -- CHG4 : process variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P4" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_vector_select <= transport 2 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; st_enum1_vector_select <= transport 3 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 4 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 5 ; -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_enum1_vector(highb-1 to highb-1) <= -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_enum1_vector_savt <= transport Std.Standard.Now ; chk_st_enum1_vector <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ; wait until (not s_st_enum1_vector(highb-1 to highb-1)'Quiet) and (s_st_enum1_vector_savt /= Std.Standard.Now) ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions completed entirely", chk_st_enum1_vector = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_st_enum1_vector(highb-1 to highb-1) <= c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns when st_enum1_vector_select = 1 else -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when st_enum1_vector_select = 2 else -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when st_enum1_vector_select = 3 else -- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns when st_enum1_vector_select = 4 else -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when st_enum1_vector_select = 5 else -- -- Last transaction above is marked c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- CHG5 : process variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns, -- c_st_integer_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P5" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_integer_vector_select <= transport 2 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; st_integer_vector_select <= transport 3 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 4 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 5 ; -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_integer_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_integer_vector(lowb to highb-1) <= -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_integer_vector_savt <= transport Std.Standard.Now ; chk_st_integer_vector <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ; wait until (not s_st_integer_vector(lowb to highb-1)'Quiet) and (s_st_integer_vector_savt /= Std.Standard.Now) ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions completed entirely", chk_st_integer_vector = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_integer_vector(lowb to highb-1) <= c_st_integer_vector_2(lowb to highb-1) after 10 ns, c_st_integer_vector_1(lowb to highb-1) after 20 ns when st_integer_vector_select = 1 else -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when st_integer_vector_select = 2 else -- c_st_integer_vector_1(lowb to highb-1) after 5 ns when st_integer_vector_select = 3 else -- c_st_integer_vector_1(lowb to highb-1) after 100 ns when st_integer_vector_select = 4 else -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when st_integer_vector_select = 5 else -- -- Last transaction above is marked c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- CHG6 : process variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns, -- c_st_time_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P6" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_time_vector_select <= transport 2 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; st_time_vector_select <= transport 3 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 4 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 5 ; -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_time_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_time_vector(lowb to highb-1) <= -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_time_vector_savt <= transport Std.Standard.Now ; chk_st_time_vector <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ; wait until (not s_st_time_vector(lowb to highb-1)'Quiet) and (s_st_time_vector_savt /= Std.Standard.Now) ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions completed entirely", chk_st_time_vector = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_st_time_vector(lowb to highb-1) <= c_st_time_vector_2(lowb to highb-1) after 10 ns, c_st_time_vector_1(lowb to highb-1) after 20 ns when st_time_vector_select = 1 else -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when st_time_vector_select = 2 else -- c_st_time_vector_1(lowb to highb-1) after 5 ns when st_time_vector_select = 3 else -- c_st_time_vector_1(lowb to highb-1) after 100 ns when st_time_vector_select = 4 else -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when st_time_vector_select = 5 else -- -- Last transaction above is marked c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- CHG7 : process variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P7" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real_vector_select <= transport 2 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; st_real_vector_select <= transport 3 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 4 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 5 ; -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_real_vector(highb-1 to highb-1) <= -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_real_vector_savt <= transport Std.Standard.Now ; chk_st_real_vector <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ; wait until (not s_st_real_vector(highb-1 to highb-1)'Quiet) and (s_st_real_vector_savt /= Std.Standard.Now) ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions completed entirely", chk_st_real_vector = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_real_vector(highb-1 to highb-1) <= c_st_real_vector_2(highb-1 to highb-1) after 10 ns, c_st_real_vector_1(highb-1 to highb-1) after 20 ns when st_real_vector_select = 1 else -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when st_real_vector_select = 2 else -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns when st_real_vector_select = 3 else -- c_st_real_vector_1(highb-1 to highb-1) after 100 ns when st_real_vector_select = 4 else -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when st_real_vector_select = 5 else -- -- Last transaction above is marked c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- CHG8 : process variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P8" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 4 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 5 ; -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1_vector(highb-1 to highb-1) <= -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; wait until (not s_st_rec1_vector(highb-1 to highb-1)'Quiet) and (s_st_rec1_vector_savt /= Std.Standard.Now) ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions completed entirely", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_st_rec1_vector(highb-1 to highb-1) <= c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns when st_rec1_vector_select = 1 else -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when st_rec1_vector_select = 2 else -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when st_rec1_vector_select = 3 else -- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns when st_rec1_vector_select = 4 else -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when st_rec1_vector_select = 5 else -- -- Last transaction above is marked c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- CHG9 : process variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns, -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392.P9" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_vector_select <= transport 2 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; st_arr2_vector_select <= transport 3 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 4 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 5 ; -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2_vector(lowb to highb-1) <= -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00392" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_vector_savt <= transport Std.Standard.Now ; chk_st_arr2_vector <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ; wait until (not s_st_arr2_vector(lowb to highb-1)'Quiet) and (s_st_arr2_vector_savt /= Std.Standard.Now) ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions completed entirely", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_arr2_vector(lowb to highb-1) <= c_st_arr2_vector_2(lowb to highb-1) after 10 ns, c_st_arr2_vector_1(lowb to highb-1) after 20 ns when st_arr2_vector_select = 1 else -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when st_arr2_vector_select = 2 else -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns when st_arr2_vector_select = 3 else -- c_st_arr2_vector_1(lowb to highb-1) after 100 ns when st_arr2_vector_select = 4 else -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when st_arr2_vector_select = 5 else -- -- Last transaction above is marked c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- end ARCH00392 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00392_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; -- end ENT00392_Test_Bench ; -- -- architecture ARCH00392_Test_Bench of ENT00392_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00392 ( ARCH00392 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector ) ; end block L1 ; end ARCH00392_Test_Bench ;
gpl-3.0
8a5f1c0b2669387a08289b458b062a5a
0.531408
3.403143
false
false
false
false
KaskMartin/Digiloogika_ALU
ALU_FPGA/func_3.vhdl
2
965
LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; -- Fun3 = clr A, B (seada sõna A B-nda biti väärtuseks '0') entity func3 is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output end func3; architecture design of func3 is signal a_sign, b_sign, o_sign: signed(3 downto 0); signal pos_sign: signed(1 downto 0); begin a_sign <= signed(a); b_sign <= signed(b); pos_sign <= b_sign(1 downto 0); DISP_F3: process ( a_sign , o_sign , pos_sign ) begin case pos_sign is when "00" => o_sign <= ("1110" and a_sign); when "01" => o_sign <= ("1101" and a_sign); when "10" => o_sign <= ("1011" and a_sign); when "11" => o_sign <= ("0111" and a_sign); when others => o_sign <= a_sign; end case; end process DISP_F3; o <= std_logic_vector(o_sign); end design;
mit
5c665865ca30b8e41e8dc059730bcf62
0.590674
2.658402
false
false
false
false
MrDoomBringer/DSD-Labs
Lab 7/up_counter.vhd
1
1,045
-- 8 bit up counter with parallel load -- (c) Cliff Chapman 2013 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY up_counter IS PORT ( -- Load. When run is low used for parallel load load : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Clock Input clk : IN STD_LOGIC; -- Run/Set. High to run, low to set from load input run : IN STD_LOGIC; -- Async reset. rst : IN STD_LOGIC := '0'; -- Output value v : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END up_counter; ARCHITECTURE counter OF up_counter IS SIGNAL reg_count : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN -- Count up on rising clock while running counter : PROCESS (clk, run, load, rst, reg_count) BEGIN IF (rst = '1') THEN reg_count <= "00000000"; ELSIF (run = '0') THEN reg_count <= load; ELSIF (rising_edge(clk)) THEN IF (run = '1') THEN -- Regular run reg_count <= reg_count + 1; END IF; ELSE reg_count <= reg_count; END IF; END PROCESS counter; v <= reg_count; END ARCHITECTURE;
mit
ffd1371f5ab4daa5e4761da16b759bba
0.648804
2.855191
false
false
false
false
grwlf/vsim
vhdl_ct/ct00235.vhd
1
11,764
-- NEED RESULT: ENT00235.P00235: Associated scalar buffer ports with static subtypes passed -- NEED RESULT: ENT00235: Associated scalar buffer ports with static subtypes passed -- NEED RESULT: ENT00235.P00235: Associated scalar buffer ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00235 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (4) -- 1.1.1.2 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00235(ARCH00235) -- ENT00235_Test_Bench(ARCH00235_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00235 is port ( toggle : buffer switch := down; i_boolean_1, i_boolean_2 : buffer boolean := c_boolean_1 ; i_bit_1, i_bit_2 : buffer bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : buffer severity_level := c_severity_level_1 ; i_character_1, i_character_2 : buffer character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : buffer t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : buffer st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : buffer integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : buffer t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : buffer st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : buffer time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : buffer t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : buffer st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : buffer real := c_real_1 ; i_t_real1_1, i_t_real1_2 : buffer t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : buffer st_real1 := c_st_real1_1 ) ; begin end ENT00235 ; -- architecture ARCH00235 of ENT00235 is begin process variable correct : boolean := true ; begin correct := correct and i_boolean_1 = c_boolean_1 and i_boolean_2 = c_boolean_1 ; correct := correct and i_bit_1 = c_bit_1 and i_bit_2 = c_bit_1 ; correct := correct and i_severity_level_1 = c_severity_level_1 and i_severity_level_2 = c_severity_level_1 ; correct := correct and i_character_1 = c_character_1 and i_character_2 = c_character_1 ; correct := correct and i_t_enum1_1 = c_t_enum1_1 and i_t_enum1_2 = c_t_enum1_1 ; correct := correct and i_st_enum1_1 = c_st_enum1_1 and i_st_enum1_2 = c_st_enum1_1 ; correct := correct and i_integer_1 = c_integer_1 and i_integer_2 = c_integer_1 ; correct := correct and i_t_int1_1 = c_t_int1_1 and i_t_int1_2 = c_t_int1_1 ; correct := correct and i_st_int1_1 = c_st_int1_1 and i_st_int1_2 = c_st_int1_1 ; correct := correct and i_time_1 = c_time_1 and i_time_2 = c_time_1 ; correct := correct and i_t_phys1_1 = c_t_phys1_1 and i_t_phys1_2 = c_t_phys1_1 ; correct := correct and i_st_phys1_1 = c_st_phys1_1 and i_st_phys1_2 = c_st_phys1_1 ; correct := correct and i_real_1 = c_real_1 and i_real_2 = c_real_1 ; correct := correct and i_t_real1_1 = c_t_real1_1 and i_t_real1_2 = c_t_real1_1 ; correct := correct and i_st_real1_1 = c_st_real1_1 and i_st_real1_2 = c_st_real1_1 ; -- test_report ( "ENT00235" , "Associated scalar buffer ports with static subtypes" , correct) ; -- toggle <= up ; i_boolean_1 <= c_boolean_2 ; i_boolean_2 <= c_boolean_2 ; i_bit_1 <= c_bit_2 ; i_bit_2 <= c_bit_2 ; i_severity_level_1 <= c_severity_level_2 ; i_severity_level_2 <= c_severity_level_2 ; i_character_1 <= c_character_2 ; i_character_2 <= c_character_2 ; i_t_enum1_1 <= c_t_enum1_2 ; i_t_enum1_2 <= c_t_enum1_2 ; i_st_enum1_1 <= c_st_enum1_2 ; i_st_enum1_2 <= c_st_enum1_2 ; i_integer_1 <= c_integer_2 ; i_integer_2 <= c_integer_2 ; i_t_int1_1 <= c_t_int1_2 ; i_t_int1_2 <= c_t_int1_2 ; i_st_int1_1 <= c_st_int1_2 ; i_st_int1_2 <= c_st_int1_2 ; i_time_1 <= c_time_2 ; i_time_2 <= c_time_2 ; i_t_phys1_1 <= c_t_phys1_2 ; i_t_phys1_2 <= c_t_phys1_2 ; i_st_phys1_1 <= c_st_phys1_2 ; i_st_phys1_2 <= c_st_phys1_2 ; i_real_1 <= c_real_2 ; i_real_2 <= c_real_2 ; i_t_real1_1 <= c_t_real1_2 ; i_t_real1_2 <= c_t_real1_2 ; i_st_real1_1 <= c_st_real1_2 ; i_st_real1_2 <= c_st_real1_2 ; wait ; end process ; end ARCH00235 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00235_Test_Bench is end ENT00235_Test_Bench ; -- architecture ARCH00235_Test_Bench of ENT00235_Test_Bench is begin L1: block signal i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; signal i_bit_1, i_bit_2 : bit := c_bit_1 ; signal i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; signal i_character_1, i_character_2 : character := c_character_1 ; signal i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; signal i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; signal i_integer_1, i_integer_2 : integer := c_integer_1 ; signal i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; signal i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; signal i_time_1, i_time_2 : time := c_time_1 ; signal i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; signal i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; signal i_real_1, i_real_2 : real := c_real_1 ; signal i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; signal i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ; -- component UUT port ( toggle : buffer switch ; i_boolean_1, i_boolean_2 : buffer boolean := c_boolean_1 ; i_bit_1, i_bit_2 : buffer bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : buffer severity_level := c_severity_level_1 ; i_character_1, i_character_2 : buffer character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : buffer t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : buffer st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : buffer integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : buffer t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : buffer st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : buffer time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : buffer t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : buffer st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : buffer real := c_real_1 ; i_t_real1_1, i_t_real1_2 : buffer t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : buffer st_real1 := c_st_real1_1 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00235 ( ARCH00235 ) ; -- begin CIS1 : UUT port map ( toggle , i_boolean_1, i_boolean_2, i_bit_1, i_bit_2, i_severity_level_1, i_severity_level_2, i_character_1, i_character_2, i_t_enum1_1, i_t_enum1_2, i_st_enum1_1, i_st_enum1_2, i_integer_1, i_integer_2, i_t_int1_1, i_t_int1_2, i_st_int1_1, i_st_int1_2, i_time_1, i_time_2, i_t_phys1_1, i_t_phys1_2, i_st_phys1_1, i_st_phys1_2, i_real_1, i_real_2, i_t_real1_1, i_t_real1_2, i_st_real1_1, i_st_real1_2 ) ; P00235 : process ( toggle ) variable correct : boolean := true ; begin if toggle = up then correct := correct and i_boolean_1 = c_boolean_2 and i_boolean_2 = c_boolean_2 ; correct := correct and i_bit_1 = c_bit_2 and i_bit_2 = c_bit_2 ; correct := correct and i_severity_level_1 = c_severity_level_2 and i_severity_level_2 = c_severity_level_2 ; correct := correct and i_character_1 = c_character_2 and i_character_2 = c_character_2 ; correct := correct and i_t_enum1_1 = c_t_enum1_2 and i_t_enum1_2 = c_t_enum1_2 ; correct := correct and i_st_enum1_1 = c_st_enum1_2 and i_st_enum1_2 = c_st_enum1_2 ; correct := correct and i_integer_1 = c_integer_2 and i_integer_2 = c_integer_2 ; correct := correct and i_t_int1_1 = c_t_int1_2 and i_t_int1_2 = c_t_int1_2 ; correct := correct and i_st_int1_1 = c_st_int1_2 and i_st_int1_2 = c_st_int1_2 ; correct := correct and i_time_1 = c_time_2 and i_time_2 = c_time_2 ; correct := correct and i_t_phys1_1 = c_t_phys1_2 and i_t_phys1_2 = c_t_phys1_2 ; correct := correct and i_st_phys1_1 = c_st_phys1_2 and i_st_phys1_2 = c_st_phys1_2 ; correct := correct and i_real_1 = c_real_2 and i_real_2 = c_real_2 ; correct := correct and i_t_real1_1 = c_t_real1_2 and i_t_real1_2 = c_t_real1_2 ; correct := correct and i_st_real1_1 = c_st_real1_2 and i_st_real1_2 = c_st_real1_2 ; end if ; -- test_report ( "ENT00235.P00235" , "Associated scalar buffer ports with static subtypes", correct) ; end process P00235 ; end block L1 ; end ARCH00235_Test_Bench ;
gpl-3.0
ff74ddfd40b3db1e6e42ab23643b7fa2
0.445767
3.069136
false
false
false
false
grwlf/vsim
vhdl_ct/ct00567.vhd
1
9,252
-- NEED RESULT: ARCH00567: Attribute declarations - scalar generic subtypes with static initial values passed -- NEED RESULT: ARCH00567: Attribute declarations - scalar generic subtypes with generic initial values passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00567 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.4 (5) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00567) -- ENT00567_Test_Bench(ARCH00567_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00567 of GENERIC_STANDARD_TYPES is begin B1 : block generic ( i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; i_bit_1, i_bit_2 : bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; i_character_1, i_character_2 : character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : real := c_real_1 ; i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ) ; generic map ( open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open, open ) ; attribute at_boolean_1 : boolean ; attribute at_bit_1 : bit ; attribute at_severity_level_1 : severity_level ; attribute at_character_1 : character ; attribute at_t_enum1_1 : t_enum1 ; attribute at_st_enum1_1 : st_enum1 ; attribute at_integer_1 : integer ; attribute at_t_int1_1 : t_int1 ; attribute at_st_int1_1 : st_int1 ; attribute at_time_1 : time ; attribute at_t_phys1_1 : t_phys1 ; attribute at_st_phys1_1 : st_phys1 ; attribute at_real_1 : real ; attribute at_t_real1_1 : t_real1 ; attribute at_st_real1_1 : st_real1 ; begin process variable correct : boolean := true ; procedure p1 ; attribute at_boolean_1 of p1 : procedure is c_boolean_1 ; attribute at_bit_1 of p1 : procedure is c_bit_1 ; attribute at_severity_level_1 of p1 : procedure is c_severity_level_1 ; attribute at_character_1 of p1 : procedure is c_character_1 ; attribute at_t_enum1_1 of p1 : procedure is c_t_enum1_1 ; attribute at_st_enum1_1 of p1 : procedure is c_st_enum1_1 ; attribute at_integer_1 of p1 : procedure is c_integer_1 ; attribute at_t_int1_1 of p1 : procedure is c_t_int1_1 ; attribute at_st_int1_1 of p1 : procedure is c_st_int1_1 ; attribute at_time_1 of p1 : procedure is c_time_1 ; attribute at_t_phys1_1 of p1 : procedure is c_t_phys1_1 ; attribute at_st_phys1_1 of p1 : procedure is c_st_phys1_1 ; attribute at_real_1 of p1 : procedure is c_real_1 ; attribute at_t_real1_1 of p1 : procedure is c_t_real1_1 ; attribute at_st_real1_1 of p1 : procedure is c_st_real1_1 ; procedure p1 is begin correct := correct and p1'at_boolean_1 = c_boolean_1 ; correct := correct and p1'at_bit_1 = c_bit_1 ; correct := correct and p1'at_severity_level_1 = c_severity_level_1 ; correct := correct and p1'at_character_1 = c_character_1 ; correct := correct and p1'at_t_enum1_1 = c_t_enum1_1 ; correct := correct and p1'at_st_enum1_1 = c_st_enum1_1 ; correct := correct and p1'at_integer_1 = c_integer_1 ; correct := correct and p1'at_t_int1_1 = c_t_int1_1 ; correct := correct and p1'at_st_int1_1 = c_st_int1_1 ; correct := correct and p1'at_time_1 = c_time_1 ; correct := correct and p1'at_t_phys1_1 = c_t_phys1_1 ; correct := correct and p1'at_st_phys1_1 = c_st_phys1_1 ; correct := correct and p1'at_real_1 = c_real_1 ; correct := correct and p1'at_t_real1_1 = c_t_real1_1 ; correct := correct and p1'at_st_real1_1 = c_st_real1_1 ; test_report ( "ARCH00567" , "Attribute declarations - scalar generic subtypes" & " with static initial values" , correct) ; end p1 ; begin p1 ; wait ; end process ; process variable correct : boolean := true ; procedure p1 ; attribute at_boolean_1 of p1 : procedure is i_boolean_1 ; attribute at_bit_1 of p1 : procedure is i_bit_1 ; attribute at_severity_level_1 of p1 : procedure is i_severity_level_1 ; attribute at_character_1 of p1 : procedure is i_character_1 ; attribute at_t_enum1_1 of p1 : procedure is i_t_enum1_1 ; attribute at_st_enum1_1 of p1 : procedure is i_st_enum1_1 ; attribute at_integer_1 of p1 : procedure is i_integer_1 ; attribute at_t_int1_1 of p1 : procedure is i_t_int1_1 ; attribute at_st_int1_1 of p1 : procedure is i_st_int1_1 ; attribute at_time_1 of p1 : procedure is i_time_1 ; attribute at_t_phys1_1 of p1 : procedure is i_t_phys1_1 ; attribute at_st_phys1_1 of p1 : procedure is i_st_phys1_1 ; attribute at_real_1 of p1 : procedure is i_real_1 ; attribute at_t_real1_1 of p1 : procedure is i_t_real1_1 ; attribute at_st_real1_1 of p1 : procedure is i_st_real1_1 ; procedure p1 is begin correct := correct and p1'at_boolean_1 = c_boolean_1 ; correct := correct and p1'at_bit_1 = c_bit_1 ; correct := correct and p1'at_severity_level_1 = c_severity_level_1 ; correct := correct and p1'at_character_1 = c_character_1 ; correct := correct and p1'at_t_enum1_1 = c_t_enum1_1 ; correct := correct and p1'at_st_enum1_1 = c_st_enum1_1 ; correct := correct and p1'at_integer_1 = c_integer_1 ; correct := correct and p1'at_t_int1_1 = c_t_int1_1 ; correct := correct and p1'at_st_int1_1 = c_st_int1_1 ; correct := correct and p1'at_time_1 = c_time_1 ; correct := correct and p1'at_t_phys1_1 = c_t_phys1_1 ; correct := correct and p1'at_st_phys1_1 = c_st_phys1_1 ; correct := correct and p1'at_real_1 = c_real_1 ; correct := correct and p1'at_t_real1_1 = c_t_real1_1 ; correct := correct and p1'at_st_real1_1 = c_st_real1_1 ; test_report ( "ARCH00567" , "Attribute declarations - scalar generic subtypes" & " with generic initial values" , correct) ; end p1 ; begin p1 ; wait ; end process ; end block B1 ; end ARCH00567 ; -- entity ENT00567_Test_Bench is end ENT00567_Test_Bench ; -- architecture ARCH00567_Test_Bench of ENT00567_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00567 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00567_Test_Bench ;
gpl-3.0
4f446ec41d2fb4210a38f99b08111b70
0.484436
3.429207
false
false
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/bitset_next.vhd
2
25,956
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bitset_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end; architecture behav of bitset_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_true : BOOLEAN := true; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal reg_123 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_5_reg_232 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_1_reg_236 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_reg_240 : STD_LOGIC_VECTOR (0 downto 0); signal r_bucket_read_reg_194 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal r_bit_read_reg_200 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 : STD_LOGIC_VECTOR (7 downto 0); signal p_read_1_reg_206 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it3 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it6 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it7 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it9 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal grp_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_3_reg_220 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_225 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_141_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_5_reg_232_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_1_fu_146_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_fu_151_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_118_ap_ce : STD_LOGIC; signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 : STD_LOGIC_VECTOR (0 downto 0); signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bit_write_assign_trunc3_ext_fu_161_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_trunc_ext_fu_156_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_131_p1 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_write_assign_cast_fu_166_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_ce : STD_LOGIC; signal ap_sig_bdd_139 : BOOLEAN; signal ap_sig_bdd_143 : BOOLEAN; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_p_bsf32_hw_fu_118 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_118_bus_r, ap_return => grp_p_bsf32_hw_fu_118_ap_return, ap_ce => grp_p_bsf32_hw_fu_118_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32s_32_8_U11 : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 generic map ( ID => 11, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_131_p0, din1 => grp_fu_131_p1, ce => grp_fu_131_ce, dout => grp_fu_131_p2); -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_5_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_5_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_reg_236)) and not((ap_const_lv1_0 = tmp_11_1_reg_240))))) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it9; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_5_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_5_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_reg_236)) and not((ap_const_lv1_0 = tmp_11_1_reg_240))))) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_const_lv2_2; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_143) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; elsif (ap_sig_bdd_139) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_const_lv32_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10; end if; end if; end if; end process; -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then ap_reg_ppstg_bus_assign_reg_225_pp0_it10 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it9; ap_reg_ppstg_bus_assign_reg_225_pp0_it9 <= bus_assign_reg_225; ap_reg_ppstg_p_read_1_reg_206_pp0_it1 <= p_read_1_reg_206; ap_reg_ppstg_p_read_1_reg_206_pp0_it10 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; ap_reg_ppstg_p_read_1_reg_206_pp0_it2 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it1; ap_reg_ppstg_p_read_1_reg_206_pp0_it3 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it2; ap_reg_ppstg_p_read_1_reg_206_pp0_it4 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it3; ap_reg_ppstg_p_read_1_reg_206_pp0_it5 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it4; ap_reg_ppstg_p_read_1_reg_206_pp0_it6 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it5; ap_reg_ppstg_p_read_1_reg_206_pp0_it7 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it6; ap_reg_ppstg_p_read_1_reg_206_pp0_it8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it7; ap_reg_ppstg_p_read_1_reg_206_pp0_it9 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 <= r_bit_read_reg_200; ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it1; ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it2; ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it3; ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it4; ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it5; ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it6; ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it7; ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it8; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 <= r_bucket_read_reg_194; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6; ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10 <= tmp_11_1_reg_240; ap_reg_ppstg_tmp_5_reg_232_pp0_it10 <= tmp_5_reg_232; ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10 <= tmp_9_1_reg_236; ap_reg_ppstg_tmp_reg_214_pp0_it1 <= tmp_reg_214; ap_reg_ppstg_tmp_reg_214_pp0_it10 <= ap_reg_ppstg_tmp_reg_214_pp0_it9; ap_reg_ppstg_tmp_reg_214_pp0_it2 <= ap_reg_ppstg_tmp_reg_214_pp0_it1; ap_reg_ppstg_tmp_reg_214_pp0_it3 <= ap_reg_ppstg_tmp_reg_214_pp0_it2; ap_reg_ppstg_tmp_reg_214_pp0_it4 <= ap_reg_ppstg_tmp_reg_214_pp0_it3; ap_reg_ppstg_tmp_reg_214_pp0_it5 <= ap_reg_ppstg_tmp_reg_214_pp0_it4; ap_reg_ppstg_tmp_reg_214_pp0_it6 <= ap_reg_ppstg_tmp_reg_214_pp0_it5; ap_reg_ppstg_tmp_reg_214_pp0_it7 <= ap_reg_ppstg_tmp_reg_214_pp0_it6; ap_reg_ppstg_tmp_reg_214_pp0_it8 <= ap_reg_ppstg_tmp_reg_214_pp0_it7; ap_reg_ppstg_tmp_reg_214_pp0_it9 <= ap_reg_ppstg_tmp_reg_214_pp0_it8; bus_assign_reg_225 <= bus_assign_fu_137_p2; p_read_1_reg_206 <= p_read; r_bit_read_reg_200 <= r_bit; r_bucket_read_reg_194 <= r_bucket; tmp_3_reg_220 <= grp_fu_131_p2; tmp_5_reg_232 <= tmp_5_fu_141_p2; tmp_reg_214 <= tmp_fu_127_p1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and (tmp_5_reg_232 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_ce) and not((tmp_5_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_reg_236)) and (ap_const_lv1_0 = tmp_11_1_reg_240)))) then reg_123 <= grp_p_bsf32_hw_fu_118_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_5_fu_141_p2)) and not((ap_const_lv1_0 = tmp_9_1_fu_146_p2)))) then tmp_11_1_reg_240 <= tmp_11_1_fu_151_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_5_fu_141_p2)))) then tmp_9_1_reg_236 <= tmp_9_1_fu_146_p2; end if; end if; end process; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11(0) <= '1'; -- agg_result_bit_write_assign_phi_fu_107_p8 assign process. -- agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(ap_reg_ppstg_tmp_5_reg_232_pp0_it10, ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10, agg_result_bit_write_assign_trunc3_ext_fu_161_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11, agg_result_bit_write_assign_trunc_ext_fu_156_p1) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_156_p1; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10))) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_161_p1; else agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11; end if; end process; agg_result_bit_write_assign_trunc3_ext_fu_161_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bit_write_assign_trunc_ext_fu_156_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bucket_index_write_assign_cast_fu_166_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8)); -- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. -- agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_214_pp0_it10, ap_reg_ppstg_tmp_5_reg_232_pp0_it10, ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_214_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10))) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1; else agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11; end if; end process; -- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. -- agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it10, ap_reg_ppstg_bus_assign_reg_225_pp0_it10, ap_reg_ppstg_tmp_5_reg_232_pp0_it10, ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10))) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it10; else agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11; end if; end process; -- agg_result_end_write_assign_phi_fu_73_p8 assign process. -- agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_reg_ppstg_tmp_5_reg_232_pp0_it10, ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11) begin if (((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_5_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_9_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_11_1_reg_240_pp0_it10)))) then agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0; else agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11; end if; end process; ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 <= ap_const_lv8_1; ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 <= ap_const_lv2_1; ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 <= ap_const_lv32_1; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 <= ap_const_lv1_1; ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8; ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_166_p1; ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8; ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8; -- ap_sig_bdd_139 assign process. -- ap_sig_bdd_139_assign_proc : process(tmp_5_reg_232, tmp_9_1_reg_236) begin ap_sig_bdd_139 <= (not((tmp_5_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_reg_236)); end process; -- ap_sig_bdd_143 assign process. -- ap_sig_bdd_143_assign_proc : process(tmp_5_reg_232, tmp_9_1_reg_236, tmp_11_1_reg_240) begin ap_sig_bdd_143 <= (not((tmp_5_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_reg_236)) and not((ap_const_lv1_0 = tmp_11_1_reg_240))); end process; bus_assign_fu_137_p2 <= (tmp_3_reg_220 and ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7); -- grp_fu_131_ce assign process. -- grp_fu_131_ce_assign_proc : process(ap_ce) begin if (not((ap_const_logic_1 = ap_ce))) then grp_fu_131_ce <= ap_const_logic_0; else grp_fu_131_ce <= ap_const_logic_1; end if; end process; grp_fu_131_p0 <= r_bucket; grp_fu_131_p1 <= ap_const_lv32_FFFFFFFF; -- grp_p_bsf32_hw_fu_118_ap_ce assign process. -- grp_p_bsf32_hw_fu_118_ap_ce_assign_proc : process(ap_ce, tmp_5_reg_232, tmp_9_1_reg_236, tmp_11_1_reg_240, tmp_5_fu_141_p2, tmp_9_1_fu_146_p2, tmp_11_1_fu_151_p2) begin if (((ap_const_logic_1 = ap_ce) and ((tmp_5_reg_232 = ap_const_lv1_0) or (not((tmp_5_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_reg_236)) and (ap_const_lv1_0 = tmp_11_1_reg_240)) or (ap_const_lv1_0 = tmp_5_fu_141_p2) or (not((ap_const_lv1_0 = tmp_5_fu_141_p2)) and not((ap_const_lv1_0 = tmp_9_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_151_p2))))) then grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_0; end if; end process; -- grp_p_bsf32_hw_fu_118_bus_r assign process. -- grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it8, bus_assign_reg_225, tmp_5_fu_141_p2, tmp_9_1_fu_146_p2, tmp_11_1_fu_151_p2) begin if ((not((ap_const_lv1_0 = tmp_5_fu_141_p2)) and not((ap_const_lv1_0 = tmp_9_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_151_p2))) then grp_p_bsf32_hw_fu_118_bus_r <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; elsif ((ap_const_lv1_0 = tmp_5_fu_141_p2)) then grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_225; else grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; tmp_11_1_fu_151_p2 <= "1" when (ap_reg_ppstg_p_read_1_reg_206_pp0_it8 = ap_const_lv32_0) else "0"; tmp_5_fu_141_p2 <= "1" when (bus_assign_reg_225 = ap_const_lv32_0) else "0"; tmp_9_1_fu_146_p2 <= "1" when (ap_reg_ppstg_tmp_reg_214_pp0_it8 = ap_const_lv2_0) else "0"; tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0); end behav;
lgpl-3.0
bd4deeec83c6685dbd0da32aef5dad3a
0.628564
2.54072
false
false
false
false
pepo27/electronica
arquitectura/sumadorNBits/acarreoCascada/sumadorAcarreoCascada.vhdl
2
641
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Prueba is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); op : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end Prueba; architecture A_Prueba of Prueba is signal eb : std_logic_vector (3 downto 0); signal c : std_logic_vector (4 downto 0); begin c(0) <= op; sumador : for i in 0 to 3 generate EB(i) <= B(i) xor OP; S(i) <= A(i) xor EB(i) xor C(i); C(i+1) <= (EB(i) and C(i)) or (A(i) and C(i)) or(A(i) and EB(i)); end generate; cout <= c(4); end A_Prueba;
gpl-3.0
db0c57c1b7cf0b0df47cd5eda0b43197
0.572543
2.605691
false
false
false
false
grwlf/vsim
vhdl_ct/ct00013.vhd
1
5,606
-- NEED RESULT: ENT00013: Associated scalar generics with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00013 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.1 (2) -- 1.1.1.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00013(ARCH00013) -- ENT00013_Test_Bench(ARCH00013_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00013 is generic ( i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; i_bit_1, i_bit_2 : bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; i_character_1, i_character_2 : character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : real := c_real_1 ; i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ) ; begin end ENT00013 ; -- architecture ARCH00013 of ENT00013 is begin process variable correct : boolean := true ; begin correct := correct and i_boolean_1 = c_boolean_2 and i_boolean_2 = c_boolean_2 ; correct := correct and i_bit_1 = c_bit_2 and i_bit_2 = c_bit_2 ; correct := correct and i_severity_level_1 = c_severity_level_2 and i_severity_level_2 = c_severity_level_2 ; correct := correct and i_character_1 = c_character_2 and i_character_2 = c_character_2 ; correct := correct and i_t_enum1_1 = c_t_enum1_2 and i_t_enum1_2 = c_t_enum1_2 ; correct := correct and i_st_enum1_1 = c_st_enum1_2 and i_st_enum1_2 = c_st_enum1_2 ; correct := correct and i_integer_1 = c_integer_2 and i_integer_2 = c_integer_2 ; correct := correct and i_t_int1_1 = c_t_int1_2 and i_t_int1_2 = c_t_int1_2 ; correct := correct and i_st_int1_1 = c_st_int1_2 and i_st_int1_2 = c_st_int1_2 ; correct := correct and i_time_1 = c_time_2 and i_time_2 = c_time_2 ; correct := correct and i_t_phys1_1 = c_t_phys1_2 and i_t_phys1_2 = c_t_phys1_2 ; correct := correct and i_st_phys1_1 = c_st_phys1_2 and i_st_phys1_2 = c_st_phys1_2 ; correct := correct and i_real_1 = c_real_2 and i_real_2 = c_real_2 ; correct := correct and i_t_real1_1 = c_t_real1_2 and i_t_real1_2 = c_t_real1_2 ; correct := correct and i_st_real1_1 = c_st_real1_2 and i_st_real1_2 = c_st_real1_2 ; test_report ( "ENT00013" , "Associated scalar generics with static subtypes" , correct) ; wait ; end process ; end ARCH00013 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00013_Test_Bench is end ENT00013_Test_Bench ; -- architecture ARCH00013_Test_Bench of ENT00013_Test_Bench is begin L1: block component UUT generic ( i_boolean_1, i_boolean_2 : boolean ; i_bit_1, i_bit_2 : bit ; i_severity_level_1, i_severity_level_2 : severity_level ; i_character_1, i_character_2 : character ; i_t_enum1_1, i_t_enum1_2 : t_enum1 ; i_st_enum1_1, i_st_enum1_2 : st_enum1 ; i_integer_1, i_integer_2 : integer ; i_t_int1_1, i_t_int1_2 : t_int1 ; i_st_int1_1, i_st_int1_2 : st_int1 ; i_time_1, i_time_2 : time ; i_t_phys1_1, i_t_phys1_2 : t_phys1 ; i_st_phys1_1, i_st_phys1_2 : st_phys1 ; i_real_1, i_real_2 : real ; i_t_real1_1, i_t_real1_2 : t_real1 ; i_st_real1_1, i_st_real1_2 : st_real1 ) ; end component ; for CIS1 : UUT use entity WORK.ENT00013 ( ARCH00013 ) ; begin CIS1 : UUT generic map ( c_boolean_2, c_boolean_2, c_bit_2, c_bit_2, c_severity_level_2, c_severity_level_2, c_character_2, c_character_2, c_t_enum1_2, c_t_enum1_2, c_st_enum1_2, c_st_enum1_2, c_integer_2, c_integer_2, c_t_int1_2, c_t_int1_2, c_st_int1_2, c_st_int1_2, c_time_2, c_time_2, c_t_phys1_2, c_t_phys1_2, c_st_phys1_2, c_st_phys1_2, c_real_2, c_real_2, c_t_real1_2, c_t_real1_2, c_st_real1_2, c_st_real1_2 ) ; end block L1 ; end ARCH00013_Test_Bench ;
gpl-3.0
95ab920442215f8b9354280dc81d69ff
0.480021
2.838481
false
true
false
false
jairov4/accel-oil
impl/impl_test_single/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
1
37,679
------------------------------------------------------------------------------ -- C:/Users/JairoAndres/Documents/Vivado/oil_plainc_hls/impl/impl_test_single/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd ------------------------------------------------------------------------------ -- ClkGen Wrapper HDL file generated by ClkGen's TCL generator library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; library Unisim; use Unisim.vcomponents.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity clock_generator is generic ( C_FAMILY : string := "virtex5" ; C_DEVICE : string := "5vlx50t"; C_PACKAGE : string := "ff1136"; C_SPEEDGRADE : string := "-2"; C_CLK_GEN : string := "PASSED" ); port ( -- clock generation CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; -- external feedback CLKFBIN : in std_logic; CLKFBOUT : out std_logic; -- variable phase shift PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; -- reset RST : in std_logic; LOCKED : out std_logic ); end clock_generator; architecture STRUCTURE of clock_generator is ---------------------------------------------------------------------------- -- Components ( copy from entity, exact the same in low level parameters ) ---------------------------------------------------------------------------- component pll_module is generic ( C_BANDWIDTH : string := "OPTIMIZED"; C_CLKFBOUT_MULT : integer := 1; C_CLKFBOUT_PHASE : real := 0.0; C_CLKIN1_PERIOD : real := 0.000; -- C_CLKIN2_PERIOD : real := 0.000; C_CLKOUT0_DIVIDE : integer := 1; C_CLKOUT0_DUTY_CYCLE : real := 0.5; C_CLKOUT0_PHASE : real := 0.0; C_CLKOUT1_DIVIDE : integer := 1; C_CLKOUT1_DUTY_CYCLE : real := 0.5; C_CLKOUT1_PHASE : real := 0.0; C_CLKOUT2_DIVIDE : integer := 1; C_CLKOUT2_DUTY_CYCLE : real := 0.5; C_CLKOUT2_PHASE : real := 0.0; C_CLKOUT3_DIVIDE : integer := 1; C_CLKOUT3_DUTY_CYCLE : real := 0.5; C_CLKOUT3_PHASE : real := 0.0; C_CLKOUT4_DIVIDE : integer := 1; C_CLKOUT4_DUTY_CYCLE : real := 0.5; C_CLKOUT4_PHASE : real := 0.0; C_CLKOUT5_DIVIDE : integer := 1; C_CLKOUT5_DUTY_CYCLE : real := 0.5; C_CLKOUT5_PHASE : real := 0.0; C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS"; C_DIVCLK_DIVIDE : integer := 1; -- C_EN_REL : boolean := false; -- C_PLL_PMCD_MODE : boolean := false; C_REF_JITTER : real := 0.100; C_RESET_ON_LOSS_OF_LOCK : boolean := false; C_RST_DEASSERT_CLK : string := "CLKIN1"; C_CLKOUT0_DESKEW_ADJUST : string := "NONE"; C_CLKOUT1_DESKEW_ADJUST : string := "NONE"; C_CLKOUT2_DESKEW_ADJUST : string := "NONE"; C_CLKOUT3_DESKEW_ADJUST : string := "NONE"; C_CLKOUT4_DESKEW_ADJUST : string := "NONE"; C_CLKOUT5_DESKEW_ADJUST : string := "NONE"; C_CLKFBOUT_DESKEW_ADJUST : string := "NONE"; C_CLKIN1_BUF : boolean := false; -- C_CLKIN2_BUF : boolean := false; C_CLKFBOUT_BUF : boolean := false; C_CLKOUT0_BUF : boolean := false; C_CLKOUT1_BUF : boolean := false; C_CLKOUT2_BUF : boolean := false; C_CLKOUT3_BUF : boolean := false; C_CLKOUT4_BUF : boolean := false; C_CLKOUT5_BUF : boolean := false; C_EXT_RESET_HIGH : integer := 1; C_FAMILY : string := "spartan6" ); port ( CLKFBDCM : out std_logic; CLKFBOUT : out std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUTDCM0 : out std_logic; CLKOUTDCM1 : out std_logic; CLKOUTDCM2 : out std_logic; CLKOUTDCM3 : out std_logic; CLKOUTDCM4 : out std_logic; CLKOUTDCM5 : out std_logic; -- DO : out std_logic_vector (15 downto 0); -- DRDY : out std_logic; LOCKED : out std_logic; CLKFBIN : in std_logic; CLKIN1 : in std_logic; -- CLKIN2 : in std_logic; -- CLKINSEL : in std_logic; -- DADDR : in std_logic_vector (4 downto 0); -- DCLK : in std_logic; -- DEN : in std_logic; -- DI : in std_logic_vector (15 downto 0); -- DWE : in std_logic; -- REL : in std_logic; RST : in std_logic ); end component; ---------------------------------------------------------------------------- -- Functions ---------------------------------------------------------------------------- -- Note : The string functions are put here to remove dependency to other pcore level libraries function UpperCase_Char(char : character) return character is begin -- If char is not an upper case letter then return char if char < 'a' or char > 'z' then return char; end if; -- Otherwise map char to its corresponding lower case character and -- return that case char is when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D'; when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H'; when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L'; when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P'; when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T'; when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X'; when 'y' => return 'Y'; when 'z' => return 'Z'; when others => return char; end case; end UpperCase_Char; function UpperCase_String (s : string) return string is variable res : string(s'range); begin -- function LoweerCase_String for I in s'range loop res(I) := UpperCase_Char(s(I)); end loop; -- I return res; end function UpperCase_String; -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal function equalString( str1, str2 : string ) return boolean is constant len1 : integer := str1'length; constant len2 : integer := str2'length; variable equal : boolean := true; begin if not (len1 = len2) then equal := false; else for i in str1'range loop if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then equal := false; end if; end loop; end if; return equal; end equalString; ---------------------------------------------------------------------------- -- Signals ---------------------------------------------------------------------------- -- signals: gnd signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 to 0); signal net_gnd16 : std_logic_vector(0 to 15); -- signals: vdd signal net_vdd0 : std_logic; -- signals : PLL0 wrapper signal SIG_PLL0_CLKFBDCM : std_logic; signal SIG_PLL0_CLKFBOUT : std_logic; signal SIG_PLL0_CLKOUT0 : std_logic; signal SIG_PLL0_CLKOUT1 : std_logic; signal SIG_PLL0_CLKOUT2 : std_logic; signal SIG_PLL0_CLKOUT3 : std_logic; signal SIG_PLL0_CLKOUT4 : std_logic; signal SIG_PLL0_CLKOUT5 : std_logic; signal SIG_PLL0_CLKOUTDCM0 : std_logic; signal SIG_PLL0_CLKOUTDCM1 : std_logic; signal SIG_PLL0_CLKOUTDCM2 : std_logic; signal SIG_PLL0_CLKOUTDCM3 : std_logic; signal SIG_PLL0_CLKOUTDCM4 : std_logic; signal SIG_PLL0_CLKOUTDCM5 : std_logic; signal SIG_PLL0_LOCKED : std_logic; signal SIG_PLL0_CLKFBIN : std_logic; signal SIG_PLL0_CLKIN1 : std_logic; signal SIG_PLL0_RST : std_logic; signal SIG_PLL0_CLKFBOUT_BUF : std_logic; signal SIG_PLL0_CLKOUT0_BUF : std_logic; signal SIG_PLL0_CLKOUT1_BUF : std_logic; signal SIG_PLL0_CLKOUT2_BUF : std_logic; signal SIG_PLL0_CLKOUT3_BUF : std_logic; signal SIG_PLL0_CLKOUT4_BUF : std_logic; signal SIG_PLL0_CLKOUT5_BUF : std_logic; begin ---------------------------------------------------------------------------- -- GND and VCC signals ---------------------------------------------------------------------------- net_gnd0 <= '0'; net_gnd1(0 to 0) <= B"0"; net_gnd16(0 to 15) <= B"0000000000000000"; net_vdd0 <= '1'; ---------------------------------------------------------------------------- -- DCM wrappers ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- PLL wrappers ---------------------------------------------------------------------------- -- PLL0 wrapper PLL0_INST : pll_module generic map ( C_BANDWIDTH => "OPTIMIZED", C_CLKFBOUT_MULT => 12, C_CLKFBOUT_PHASE => 0.0, C_CLKIN1_PERIOD => 10.000000, C_CLKOUT0_DIVIDE => 24, C_CLKOUT0_DUTY_CYCLE => 0.5, C_CLKOUT0_PHASE => 0.0000, C_CLKOUT1_DIVIDE => 1, C_CLKOUT1_DUTY_CYCLE => 0.5, C_CLKOUT1_PHASE => 0.0, C_CLKOUT2_DIVIDE => 1, C_CLKOUT2_DUTY_CYCLE => 0.5, C_CLKOUT2_PHASE => 0.0, C_CLKOUT3_DIVIDE => 1, C_CLKOUT3_DUTY_CYCLE => 0.5, C_CLKOUT3_PHASE => 0.0, C_CLKOUT4_DIVIDE => 1, C_CLKOUT4_DUTY_CYCLE => 0.5, C_CLKOUT4_PHASE => 0.0, C_CLKOUT5_DIVIDE => 1, C_CLKOUT5_DUTY_CYCLE => 0.5, C_CLKOUT5_PHASE => 0.0, C_COMPENSATION => "SYSTEM_SYNCHRONOUS", C_DIVCLK_DIVIDE => 1, C_REF_JITTER => 0.100, C_RESET_ON_LOSS_OF_LOCK => false, C_RST_DEASSERT_CLK => "CLKIN1", C_CLKOUT0_DESKEW_ADJUST => "NONE", C_CLKOUT1_DESKEW_ADJUST => "NONE", C_CLKOUT2_DESKEW_ADJUST => "NONE", C_CLKOUT3_DESKEW_ADJUST => "NONE", C_CLKOUT4_DESKEW_ADJUST => "NONE", C_CLKOUT5_DESKEW_ADJUST => "NONE", C_CLKFBOUT_DESKEW_ADJUST => "NONE", C_CLKIN1_BUF => false, C_CLKFBOUT_BUF => false, C_CLKOUT0_BUF => false, C_CLKOUT1_BUF => false, C_CLKOUT2_BUF => false, C_CLKOUT3_BUF => false, C_CLKOUT4_BUF => false, C_CLKOUT5_BUF => false, C_EXT_RESET_HIGH => 0, C_FAMILY => "virtex5" ) port map ( CLKFBDCM => SIG_PLL0_CLKFBDCM, CLKFBOUT => SIG_PLL0_CLKFBOUT, CLKOUT0 => SIG_PLL0_CLKOUT0, CLKOUT1 => SIG_PLL0_CLKOUT1, CLKOUT2 => SIG_PLL0_CLKOUT2, CLKOUT3 => SIG_PLL0_CLKOUT3, CLKOUT4 => SIG_PLL0_CLKOUT4, CLKOUT5 => SIG_PLL0_CLKOUT5, CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0, CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1, CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2, CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3, CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4, CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5, -- DO -- DRDY LOCKED => SIG_PLL0_LOCKED, CLKFBIN => SIG_PLL0_CLKFBIN, CLKIN1 => SIG_PLL0_CLKIN1, -- CLKIN2 -- CLKINSEL -- DADDR -- DCLK -- DEN -- DI -- DWE -- REL RST => SIG_PLL0_RST ); -- wrapper of clkout : CLKOUT0 PLL0_CLKOUT0_BUFG_INST : BUFG port map ( I => SIG_PLL0_CLKOUT0, O => SIG_PLL0_CLKOUT0_BUF ); -- wrapper of clkout : CLKOUT1 SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1; -- wrapper of clkout : CLKOUT2 SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2; -- wrapper of clkout : CLKOUT3 SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3; -- wrapper of clkout : CLKOUT4 SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4; -- wrapper of clkout : CLKOUT5 SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5; -- wrapper of clkout : CLKFBOUT PLL0_CLKFBOUT_BUFG_INST : BUFG port map ( I => SIG_PLL0_CLKFBOUT, O => SIG_PLL0_CLKFBOUT_BUF ); ---------------------------------------------------------------------------- -- MMCM wrappers ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- PLLE wrappers ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- DCMs CLKIN, CLKFB and RST signal connection ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- PLLs CLKIN1, CLKFBIN and RST signal connection ---------------------------------------------------------------------------- -- PLL0 CLKIN1 SIG_PLL0_CLKIN1 <= CLKIN; -- PLL0 CLKFBIN SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT; -- PLL0 RST SIG_PLL0_RST <= RST; ---------------------------------------------------------------------------- -- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection ---------------------------------------------------------------------------- -- CLKGEN CLKOUT CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF; CLKOUT1 <= '0'; CLKOUT2 <= '0'; CLKOUT3 <= '0'; CLKOUT4 <= '0'; CLKOUT5 <= '0'; CLKOUT6 <= '0'; CLKOUT7 <= '0'; CLKOUT8 <= '0'; CLKOUT9 <= '0'; CLKOUT10 <= '0'; CLKOUT11 <= '0'; CLKOUT12 <= '0'; CLKOUT13 <= '0'; CLKOUT14 <= '0'; CLKOUT15 <= '0'; -- CLKGEN CLKFBOUT -- CLKGEN LOCKED LOCKED <= SIG_PLL0_LOCKED; end architecture STRUCTURE; ------------------------------------------------------------------------------ -- High level parameters ------------------------------------------------------------------------------ -- C_CLK_GEN = PASSED -- C_ELABORATE_DIR = -- C_ELABORATE_RES = NOT_SET -- C_FAMILY = virtex5 -- C_DEVICE = 5vlx50t -- C_PACKAGE = ff1136 -- C_SPEEDGRADE = -2 ---------------------------------------- -- C_EXTRA_MMCM_FOR_DESKEW = -- C_MMCMExtra_CLKIN_FREQ = -- C_MMCMExtra_CLKOUT0 = -- C_MMCMExtra_CLKOUT1 = -- C_MMCMExtra_CLKOUT2 = -- C_MMCMExtra_CLKOUT3 = -- C_MMCMExtra_CLKOUT4 = -- C_MMCMExtra_CLKOUT5 = -- C_MMCMExtra_CLKOUT6 = -- C_MMCMExtra_CLKOUT7 = -- C_MMCMExtra_CLKOUT8 = -- C_MMCMExtra_CLKOUT9 = -- C_MMCMExtra_CLKOUT10 = -- C_MMCMExtra_CLKOUT11 = -- C_MMCMExtra_CLKOUT12 = -- C_MMCMExtra_CLKOUT13 = -- C_MMCMExtra_CLKOUT14 = -- C_MMCMExtra_CLKOUT15 = -- C_MMCMExtra_CLKFBOUT_MULT = -- C_MMCMExtra_DIVCLK_DIVIDE = -- C_MMCMExtra_CLKOUT0_DIVIDE = -- C_MMCMExtra_CLKOUT1_DIVIDE = -- C_MMCMExtra_CLKOUT2_DIVIDE = -- C_MMCMExtra_CLKOUT3_DIVIDE = -- C_MMCMExtra_CLKOUT4_DIVIDE = -- C_MMCMExtra_CLKOUT5_DIVIDE = -- C_MMCMExtra_CLKOUT6_DIVIDE = -- C_MMCMExtra_CLKOUT0_BUF = -- C_MMCMExtra_CLKOUT1_BUF = -- C_MMCMExtra_CLKOUT2_BUF = -- C_MMCMExtra_CLKOUT3_BUF = -- C_MMCMExtra_CLKOUT4_BUF = -- C_MMCMExtra_CLKOUT5_BUF = -- C_MMCMExtra_CLKOUT6_BUF = -- C_MMCMExtra_CLKFBOUT_BUF = -- C_MMCMExtra_CLKOUT0_PHASE = -- C_MMCMExtra_CLKOUT1_PHASE = -- C_MMCMExtra_CLKOUT2_PHASE = -- C_MMCMExtra_CLKOUT3_PHASE = -- C_MMCMExtra_CLKOUT4_PHASE = -- C_MMCMExtra_CLKOUT5_PHASE = -- C_MMCMExtra_CLKOUT6_PHASE = ---------------------------------------- -- C_CLKIN_FREQ = 100000000 -- C_CLKOUT0_FREQ = 50000000 -- C_CLKOUT0_PHASE = 0 -- C_CLKOUT0_GROUP = NONE -- C_CLKOUT0_BUF = TRUE -- C_CLKOUT0_VARIABLE_PHASE = FALSE -- C_CLKOUT1_FREQ = 0 -- C_CLKOUT1_PHASE = 0 -- C_CLKOUT1_GROUP = NONE -- C_CLKOUT1_BUF = TRUE -- C_CLKOUT1_VARIABLE_PHASE = FALSE -- C_CLKOUT2_FREQ = 0 -- C_CLKOUT2_PHASE = 0 -- C_CLKOUT2_GROUP = NONE -- C_CLKOUT2_BUF = TRUE -- C_CLKOUT2_VARIABLE_PHASE = FALSE -- C_CLKOUT3_FREQ = 0 -- C_CLKOUT3_PHASE = 0 -- C_CLKOUT3_GROUP = NONE -- C_CLKOUT3_BUF = TRUE -- C_CLKOUT3_VARIABLE_PHASE = FALSE -- C_CLKOUT4_FREQ = 0 -- C_CLKOUT4_PHASE = 0 -- C_CLKOUT4_GROUP = NONE -- C_CLKOUT4_BUF = TRUE -- C_CLKOUT4_VARIABLE_PHASE = FALSE -- C_CLKOUT5_FREQ = 0 -- C_CLKOUT5_PHASE = 0 -- C_CLKOUT5_GROUP = NONE -- C_CLKOUT5_BUF = TRUE -- C_CLKOUT5_VARIABLE_PHASE = FALSE -- C_CLKOUT6_FREQ = 0 -- C_CLKOUT6_PHASE = 0 -- C_CLKOUT6_GROUP = NONE -- C_CLKOUT6_BUF = TRUE -- C_CLKOUT6_VARIABLE_PHASE = FALSE -- C_CLKOUT7_FREQ = 0 -- C_CLKOUT7_PHASE = 0 -- C_CLKOUT7_GROUP = NONE -- C_CLKOUT7_BUF = TRUE -- C_CLKOUT7_VARIABLE_PHASE = FALSE -- C_CLKOUT8_FREQ = 0 -- C_CLKOUT8_PHASE = 0 -- C_CLKOUT8_GROUP = NONE -- C_CLKOUT8_BUF = TRUE -- C_CLKOUT8_VARIABLE_PHASE = FALSE -- C_CLKOUT9_FREQ = 0 -- C_CLKOUT9_PHASE = 0 -- C_CLKOUT9_GROUP = NONE -- C_CLKOUT9_BUF = TRUE -- C_CLKOUT9_VARIABLE_PHASE = FALSE -- C_CLKOUT10_FREQ = 0 -- C_CLKOUT10_PHASE = 0 -- C_CLKOUT10_GROUP = NONE -- C_CLKOUT10_BUF = TRUE -- C_CLKOUT10_VARIABLE_PHASE = FALSE -- C_CLKOUT11_FREQ = 0 -- C_CLKOUT11_PHASE = 0 -- C_CLKOUT11_GROUP = NONE -- C_CLKOUT11_BUF = TRUE -- C_CLKOUT11_VARIABLE_PHASE = FALSE -- C_CLKOUT12_FREQ = 0 -- C_CLKOUT12_PHASE = 0 -- C_CLKOUT12_GROUP = NONE -- C_CLKOUT12_BUF = TRUE -- C_CLKOUT12_VARIABLE_PHASE = FALSE -- C_CLKOUT13_FREQ = 0 -- C_CLKOUT13_PHASE = 0 -- C_CLKOUT13_GROUP = NONE -- C_CLKOUT13_BUF = TRUE -- C_CLKOUT13_VARIABLE_PHASE = FALSE -- C_CLKOUT14_FREQ = 0 -- C_CLKOUT14_PHASE = 0 -- C_CLKOUT14_GROUP = NONE -- C_CLKOUT14_BUF = TRUE -- C_CLKOUT14_VARIABLE_PHASE = FALSE -- C_CLKOUT15_FREQ = 0 -- C_CLKOUT15_PHASE = 0 -- C_CLKOUT15_GROUP = NONE -- C_CLKOUT15_BUF = TRUE -- C_CLKOUT15_VARIABLE_PHASE = FALSE ---------------------------------------- -- C_CLKFBIN_FREQ = 0 -- C_CLKFBIN_DESKEW = NONE -- C_CLKFBOUT_FREQ = 0 -- C_CLKFBOUT_GROUP = NONE -- C_CLKFBOUT_BUF = TRUE ---------------------------------------- -- C_PSDONE_GROUP = NONE ------------------------------------------------------------------------------ -- Low level parameters ------------------------------------------------------------------------------ -- C_CLKOUT0_MODULE = PLL0 -- C_CLKOUT0_PORT = CLKOUT0B -- C_CLKOUT1_MODULE = NONE -- C_CLKOUT1_PORT = NONE -- C_CLKOUT2_MODULE = NONE -- C_CLKOUT2_PORT = NONE -- C_CLKOUT3_MODULE = NONE -- C_CLKOUT3_PORT = NONE -- C_CLKOUT4_MODULE = NONE -- C_CLKOUT4_PORT = NONE -- C_CLKOUT5_MODULE = NONE -- C_CLKOUT5_PORT = NONE -- C_CLKOUT6_MODULE = NONE -- C_CLKOUT6_PORT = NONE -- C_CLKOUT7_MODULE = NONE -- C_CLKOUT7_PORT = NONE -- C_CLKOUT8_MODULE = NONE -- C_CLKOUT8_PORT = NONE -- C_CLKOUT9_MODULE = NONE -- C_CLKOUT9_PORT = NONE -- C_CLKOUT10_MODULE = NONE -- C_CLKOUT10_PORT = NONE -- C_CLKOUT11_MODULE = NONE -- C_CLKOUT11_PORT = NONE -- C_CLKOUT12_MODULE = NONE -- C_CLKOUT12_PORT = NONE -- C_CLKOUT13_MODULE = NONE -- C_CLKOUT13_PORT = NONE -- C_CLKOUT14_MODULE = NONE -- C_CLKOUT14_PORT = NONE -- C_CLKOUT15_MODULE = NONE -- C_CLKOUT15_PORT = NONE ---------------------------------------- -- C_CLKFBOUT_MODULE = NONE -- C_CLKFBOUT_PORT = NONE -- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE ---------------------------------------- -- C_PSDONE_MODULE = NONE ---------------------------------------- -- C_DCM0_DFS_FREQUENCY_MODE = "LOW" -- C_DCM0_DLL_FREQUENCY_MODE = "LOW" -- C_DCM0_DUTY_CYCLE_CORRECTION = true -- C_DCM0_CLKIN_DIVIDE_BY_2 = false -- C_DCM0_CLK_FEEDBACK = "1X" -- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM0_DSS_MODE = "NONE" -- C_DCM0_STARTUP_WAIT = false -- C_DCM0_PHASE_SHIFT = 0 -- C_DCM0_CLKFX_MULTIPLY = 4 -- C_DCM0_CLKFX_DIVIDE = 1 -- C_DCM0_CLKDV_DIVIDE = 2.0 -- C_DCM0_CLKIN_PERIOD = 41.6666666 -- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM0_CLKIN_BUF = false -- C_DCM0_CLKFB_BUF = false -- C_DCM0_CLK0_BUF = false -- C_DCM0_CLK90_BUF = false -- C_DCM0_CLK180_BUF = false -- C_DCM0_CLK270_BUF = false -- C_DCM0_CLKDV_BUF = false -- C_DCM0_CLK2X_BUF = false -- C_DCM0_CLK2X180_BUF = false -- C_DCM0_CLKFX_BUF = false -- C_DCM0_CLKFX180_BUF = false -- C_DCM0_EXT_RESET_HIGH = 1 -- C_DCM0_FAMILY = "virtex5" -- C_DCM0_CLKIN_MODULE = NONE -- C_DCM0_CLKIN_PORT = NONE -- C_DCM0_CLKFB_MODULE = NONE -- C_DCM0_CLKFB_PORT = NONE -- C_DCM0_RST_MODULE = NONE -- C_DCM1_DFS_FREQUENCY_MODE = "LOW" -- C_DCM1_DLL_FREQUENCY_MODE = "LOW" -- C_DCM1_DUTY_CYCLE_CORRECTION = true -- C_DCM1_CLKIN_DIVIDE_BY_2 = false -- C_DCM1_CLK_FEEDBACK = "1X" -- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM1_DSS_MODE = "NONE" -- C_DCM1_STARTUP_WAIT = false -- C_DCM1_PHASE_SHIFT = 0 -- C_DCM1_CLKFX_MULTIPLY = 4 -- C_DCM1_CLKFX_DIVIDE = 1 -- C_DCM1_CLKDV_DIVIDE = 2.0 -- C_DCM1_CLKIN_PERIOD = 41.6666666 -- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM1_CLKIN_BUF = false -- C_DCM1_CLKFB_BUF = false -- C_DCM1_CLK0_BUF = false -- C_DCM1_CLK90_BUF = false -- C_DCM1_CLK180_BUF = false -- C_DCM1_CLK270_BUF = false -- C_DCM1_CLKDV_BUF = false -- C_DCM1_CLK2X_BUF = false -- C_DCM1_CLK2X180_BUF = false -- C_DCM1_CLKFX_BUF = false -- C_DCM1_CLKFX180_BUF = false -- C_DCM1_EXT_RESET_HIGH = 1 -- C_DCM1_FAMILY = "virtex5" -- C_DCM1_CLKIN_MODULE = NONE -- C_DCM1_CLKIN_PORT = NONE -- C_DCM1_CLKFB_MODULE = NONE -- C_DCM1_CLKFB_PORT = NONE -- C_DCM1_RST_MODULE = NONE -- C_DCM2_DFS_FREQUENCY_MODE = "LOW" -- C_DCM2_DLL_FREQUENCY_MODE = "LOW" -- C_DCM2_DUTY_CYCLE_CORRECTION = true -- C_DCM2_CLKIN_DIVIDE_BY_2 = false -- C_DCM2_CLK_FEEDBACK = "1X" -- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM2_DSS_MODE = "NONE" -- C_DCM2_STARTUP_WAIT = false -- C_DCM2_PHASE_SHIFT = 0 -- C_DCM2_CLKFX_MULTIPLY = 4 -- C_DCM2_CLKFX_DIVIDE = 1 -- C_DCM2_CLKDV_DIVIDE = 2.0 -- C_DCM2_CLKIN_PERIOD = 41.6666666 -- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM2_CLKIN_BUF = false -- C_DCM2_CLKFB_BUF = false -- C_DCM2_CLK0_BUF = false -- C_DCM2_CLK90_BUF = false -- C_DCM2_CLK180_BUF = false -- C_DCM2_CLK270_BUF = false -- C_DCM2_CLKDV_BUF = false -- C_DCM2_CLK2X_BUF = false -- C_DCM2_CLK2X180_BUF = false -- C_DCM2_CLKFX_BUF = false -- C_DCM2_CLKFX180_BUF = false -- C_DCM2_EXT_RESET_HIGH = 1 -- C_DCM2_FAMILY = "virtex5" -- C_DCM2_CLKIN_MODULE = NONE -- C_DCM2_CLKIN_PORT = NONE -- C_DCM2_CLKFB_MODULE = NONE -- C_DCM2_CLKFB_PORT = NONE -- C_DCM2_RST_MODULE = NONE -- C_DCM3_DFS_FREQUENCY_MODE = "LOW" -- C_DCM3_DLL_FREQUENCY_MODE = "LOW" -- C_DCM3_DUTY_CYCLE_CORRECTION = true -- C_DCM3_CLKIN_DIVIDE_BY_2 = false -- C_DCM3_CLK_FEEDBACK = "1X" -- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE" -- C_DCM3_DSS_MODE = "NONE" -- C_DCM3_STARTUP_WAIT = false -- C_DCM3_PHASE_SHIFT = 0 -- C_DCM3_CLKFX_MULTIPLY = 4 -- C_DCM3_CLKFX_DIVIDE = 1 -- C_DCM3_CLKDV_DIVIDE = 2.0 -- C_DCM3_CLKIN_PERIOD = 41.6666666 -- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS" -- C_DCM3_CLKIN_BUF = false -- C_DCM3_CLKFB_BUF = false -- C_DCM3_CLK0_BUF = false -- C_DCM3_CLK90_BUF = false -- C_DCM3_CLK180_BUF = false -- C_DCM3_CLK270_BUF = false -- C_DCM3_CLKDV_BUF = false -- C_DCM3_CLK2X_BUF = false -- C_DCM3_CLK2X180_BUF = false -- C_DCM3_CLKFX_BUF = false -- C_DCM3_CLKFX180_BUF = false -- C_DCM3_EXT_RESET_HIGH = 1 -- C_DCM3_FAMILY = "virtex5" -- C_DCM3_CLKIN_MODULE = NONE -- C_DCM3_CLKIN_PORT = NONE -- C_DCM3_CLKFB_MODULE = NONE -- C_DCM3_CLKFB_PORT = NONE -- C_DCM3_RST_MODULE = NONE ---------------------------------------- -- C_PLL0_BANDWIDTH = "OPTIMIZED" -- C_PLL0_CLKFBOUT_MULT = 12 -- C_PLL0_CLKFBOUT_PHASE = 0.0 -- C_PLL0_CLKIN1_PERIOD = 10.000000 -- C_PLL0_CLKOUT0_DIVIDE = 24 -- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT0_PHASE = 0.0000 -- C_PLL0_CLKOUT1_DIVIDE = 1 -- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT1_PHASE = 0.0 -- C_PLL0_CLKOUT2_DIVIDE = 1 -- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT2_PHASE = 0.0 -- C_PLL0_CLKOUT3_DIVIDE = 1 -- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT3_PHASE = 0.0 -- C_PLL0_CLKOUT4_DIVIDE = 1 -- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT4_PHASE = 0.0 -- C_PLL0_CLKOUT5_DIVIDE = 1 -- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5 -- C_PLL0_CLKOUT5_PHASE = 0.0 -- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS" -- C_PLL0_DIVCLK_DIVIDE = 1 -- C_PLL0_REF_JITTER = 0.100 -- C_PLL0_RESET_ON_LOSS_OF_LOCK = false -- C_PLL0_RST_DEASSERT_CLK = "CLKIN1" -- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE" -- C_PLL0_CLKIN1_BUF = false -- C_PLL0_CLKFBOUT_BUF = TRUE -- C_PLL0_CLKOUT0_BUF = TRUE -- C_PLL0_CLKOUT1_BUF = false -- C_PLL0_CLKOUT2_BUF = false -- C_PLL0_CLKOUT3_BUF = false -- C_PLL0_CLKOUT4_BUF = false -- C_PLL0_CLKOUT5_BUF = false -- C_PLL0_EXT_RESET_HIGH = 0 -- C_PLL0_FAMILY = "virtex5" -- C_PLL0_CLKIN1_MODULE = CLKGEN -- C_PLL0_CLKIN1_PORT = CLKIN -- C_PLL0_CLKFBIN_MODULE = PLL0 -- C_PLL0_CLKFBIN_PORT = CLKFBOUT -- C_PLL0_RST_MODULE = CLKGEN -- C_PLL1_BANDWIDTH = "OPTIMIZED" -- C_PLL1_CLKFBOUT_MULT = 1 -- C_PLL1_CLKFBOUT_PHASE = 0.0 -- C_PLL1_CLKIN1_PERIOD = 0.000 -- C_PLL1_CLKOUT0_DIVIDE = 1 -- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT0_PHASE = 0.0 -- C_PLL1_CLKOUT1_DIVIDE = 1 -- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT1_PHASE = 0.0 -- C_PLL1_CLKOUT2_DIVIDE = 1 -- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT2_PHASE = 0.0 -- C_PLL1_CLKOUT3_DIVIDE = 1 -- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT3_PHASE = 0.0 -- C_PLL1_CLKOUT4_DIVIDE = 1 -- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT4_PHASE = 0.0 -- C_PLL1_CLKOUT5_DIVIDE = 1 -- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5 -- C_PLL1_CLKOUT5_PHASE = 0.0 -- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS" -- C_PLL1_DIVCLK_DIVIDE = 1 -- C_PLL1_REF_JITTER = 0.100 -- C_PLL1_RESET_ON_LOSS_OF_LOCK = false -- C_PLL1_RST_DEASSERT_CLK = "CLKIN1" -- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE" -- C_PLL1_CLKIN1_BUF = false -- C_PLL1_CLKFBOUT_BUF = false -- C_PLL1_CLKOUT0_BUF = false -- C_PLL1_CLKOUT1_BUF = false -- C_PLL1_CLKOUT2_BUF = false -- C_PLL1_CLKOUT3_BUF = false -- C_PLL1_CLKOUT4_BUF = false -- C_PLL1_CLKOUT5_BUF = false -- C_PLL1_EXT_RESET_HIGH = 1 -- C_PLL1_FAMILY = "virtex5" -- C_PLL1_CLKIN1_MODULE = NONE -- C_PLL1_CLKIN1_PORT = NONE -- C_PLL1_CLKFBIN_MODULE = NONE -- C_PLL1_CLKFBIN_PORT = NONE -- C_PLL1_RST_MODULE = NONE ---------------------------------------- -- C_MMCM0_BANDWIDTH = "OPTIMIZED" -- C_MMCM0_CLKFBOUT_MULT_F = 1.0 -- C_MMCM0_CLKFBOUT_PHASE = 0.0 -- C_MMCM0_CLKFBOUT_USE_FINE_PS = false -- C_MMCM0_CLKIN1_PERIOD = 0.000 -- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT0_PHASE = 0.0 -- C_MMCM0_CLKOUT1_DIVIDE = 1 -- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT1_PHASE = 0.0 -- C_MMCM0_CLKOUT2_DIVIDE = 1 -- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT2_PHASE = 0.0 -- C_MMCM0_CLKOUT3_DIVIDE = 1 -- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT3_PHASE = 0.0 -- C_MMCM0_CLKOUT4_DIVIDE = 1 -- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT4_PHASE = 0.0 -- C_MMCM0_CLKOUT4_CASCADE = false -- C_MMCM0_CLKOUT5_DIVIDE = 1 -- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT5_PHASE = 0.0 -- C_MMCM0_CLKOUT6_DIVIDE = 1 -- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM0_CLKOUT6_PHASE = 0.0 -- C_MMCM0_CLKOUT0_USE_FINE_PS = false -- C_MMCM0_CLKOUT1_USE_FINE_PS = false -- C_MMCM0_CLKOUT2_USE_FINE_PS = false -- C_MMCM0_CLKOUT3_USE_FINE_PS = false -- C_MMCM0_CLKOUT4_USE_FINE_PS = false -- C_MMCM0_CLKOUT5_USE_FINE_PS = false -- C_MMCM0_CLKOUT6_USE_FINE_PS = false -- C_MMCM0_COMPENSATION = "ZHOLD" -- C_MMCM0_DIVCLK_DIVIDE = 1 -- C_MMCM0_REF_JITTER1 = 0.010 -- C_MMCM0_CLKIN1_BUF = false -- C_MMCM0_CLKFBOUT_BUF = false -- C_MMCM0_CLKOUT0_BUF = false -- C_MMCM0_CLKOUT1_BUF = false -- C_MMCM0_CLKOUT2_BUF = false -- C_MMCM0_CLKOUT3_BUF = false -- C_MMCM0_CLKOUT4_BUF = false -- C_MMCM0_CLKOUT5_BUF = false -- C_MMCM0_CLKOUT6_BUF = false -- C_MMCM0_CLOCK_HOLD = false -- C_MMCM0_STARTUP_WAIT = false -- C_MMCM0_EXT_RESET_HIGH = 1 -- C_MMCM0_FAMILY = "virtex5" -- C_MMCM0_CLKIN1_MODULE = NONE -- C_MMCM0_CLKIN1_PORT = NONE -- C_MMCM0_CLKFBIN_MODULE = NONE -- C_MMCM0_CLKFBIN_PORT = NONE -- C_MMCM0_RST_MODULE = NONE -- C_MMCM1_BANDWIDTH = "OPTIMIZED" -- C_MMCM1_CLKFBOUT_MULT_F = 1.0 -- C_MMCM1_CLKFBOUT_PHASE = 0.0 -- C_MMCM1_CLKFBOUT_USE_FINE_PS = false -- C_MMCM1_CLKIN1_PERIOD = 0.000 -- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT0_PHASE = 0.0 -- C_MMCM1_CLKOUT1_DIVIDE = 1 -- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT1_PHASE = 0.0 -- C_MMCM1_CLKOUT2_DIVIDE = 1 -- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT2_PHASE = 0.0 -- C_MMCM1_CLKOUT3_DIVIDE = 1 -- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT3_PHASE = 0.0 -- C_MMCM1_CLKOUT4_DIVIDE = 1 -- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT4_PHASE = 0.0 -- C_MMCM1_CLKOUT4_CASCADE = false -- C_MMCM1_CLKOUT5_DIVIDE = 1 -- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT5_PHASE = 0.0 -- C_MMCM1_CLKOUT6_DIVIDE = 1 -- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM1_CLKOUT6_PHASE = 0.0 -- C_MMCM1_CLKOUT0_USE_FINE_PS = false -- C_MMCM1_CLKOUT1_USE_FINE_PS = false -- C_MMCM1_CLKOUT2_USE_FINE_PS = false -- C_MMCM1_CLKOUT3_USE_FINE_PS = false -- C_MMCM1_CLKOUT4_USE_FINE_PS = false -- C_MMCM1_CLKOUT5_USE_FINE_PS = false -- C_MMCM1_CLKOUT6_USE_FINE_PS = false -- C_MMCM1_COMPENSATION = "ZHOLD" -- C_MMCM1_DIVCLK_DIVIDE = 1 -- C_MMCM1_REF_JITTER1 = 0.010 -- C_MMCM1_CLKIN1_BUF = false -- C_MMCM1_CLKFBOUT_BUF = false -- C_MMCM1_CLKOUT0_BUF = false -- C_MMCM1_CLKOUT1_BUF = false -- C_MMCM1_CLKOUT2_BUF = false -- C_MMCM1_CLKOUT3_BUF = false -- C_MMCM1_CLKOUT4_BUF = false -- C_MMCM1_CLKOUT5_BUF = false -- C_MMCM1_CLKOUT6_BUF = false -- C_MMCM1_CLOCK_HOLD = false -- C_MMCM1_STARTUP_WAIT = false -- C_MMCM1_EXT_RESET_HIGH = 1 -- C_MMCM1_FAMILY = "virtex5" -- C_MMCM1_CLKIN1_MODULE = NONE -- C_MMCM1_CLKIN1_PORT = NONE -- C_MMCM1_CLKFBIN_MODULE = NONE -- C_MMCM1_CLKFBIN_PORT = NONE -- C_MMCM1_RST_MODULE = NONE -- C_MMCM2_BANDWIDTH = "OPTIMIZED" -- C_MMCM2_CLKFBOUT_MULT_F = 1.0 -- C_MMCM2_CLKFBOUT_PHASE = 0.0 -- C_MMCM2_CLKFBOUT_USE_FINE_PS = false -- C_MMCM2_CLKIN1_PERIOD = 0.000 -- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT0_PHASE = 0.0 -- C_MMCM2_CLKOUT1_DIVIDE = 1 -- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT1_PHASE = 0.0 -- C_MMCM2_CLKOUT2_DIVIDE = 1 -- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT2_PHASE = 0.0 -- C_MMCM2_CLKOUT3_DIVIDE = 1 -- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT3_PHASE = 0.0 -- C_MMCM2_CLKOUT4_DIVIDE = 1 -- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT4_PHASE = 0.0 -- C_MMCM2_CLKOUT4_CASCADE = false -- C_MMCM2_CLKOUT5_DIVIDE = 1 -- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT5_PHASE = 0.0 -- C_MMCM2_CLKOUT6_DIVIDE = 1 -- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM2_CLKOUT6_PHASE = 0.0 -- C_MMCM2_CLKOUT0_USE_FINE_PS = false -- C_MMCM2_CLKOUT1_USE_FINE_PS = false -- C_MMCM2_CLKOUT2_USE_FINE_PS = false -- C_MMCM2_CLKOUT3_USE_FINE_PS = false -- C_MMCM2_CLKOUT4_USE_FINE_PS = false -- C_MMCM2_CLKOUT5_USE_FINE_PS = false -- C_MMCM2_CLKOUT6_USE_FINE_PS = false -- C_MMCM2_COMPENSATION = "ZHOLD" -- C_MMCM2_DIVCLK_DIVIDE = 1 -- C_MMCM2_REF_JITTER1 = 0.010 -- C_MMCM2_CLKIN1_BUF = false -- C_MMCM2_CLKFBOUT_BUF = false -- C_MMCM2_CLKOUT0_BUF = false -- C_MMCM2_CLKOUT1_BUF = false -- C_MMCM2_CLKOUT2_BUF = false -- C_MMCM2_CLKOUT3_BUF = false -- C_MMCM2_CLKOUT4_BUF = false -- C_MMCM2_CLKOUT5_BUF = false -- C_MMCM2_CLKOUT6_BUF = false -- C_MMCM2_CLOCK_HOLD = false -- C_MMCM2_STARTUP_WAIT = false -- C_MMCM2_EXT_RESET_HIGH = 1 -- C_MMCM2_FAMILY = "virtex5" -- C_MMCM2_CLKIN1_MODULE = NONE -- C_MMCM2_CLKIN1_PORT = NONE -- C_MMCM2_CLKFBIN_MODULE = NONE -- C_MMCM2_CLKFBIN_PORT = NONE -- C_MMCM2_RST_MODULE = NONE -- C_MMCM3_BANDWIDTH = "OPTIMIZED" -- C_MMCM3_CLKFBOUT_MULT_F = 1.0 -- C_MMCM3_CLKFBOUT_PHASE = 0.0 -- C_MMCM3_CLKFBOUT_USE_FINE_PS = false -- C_MMCM3_CLKIN1_PERIOD = 0.000 -- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0 -- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT0_PHASE = 0.0 -- C_MMCM3_CLKOUT1_DIVIDE = 1 -- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT1_PHASE = 0.0 -- C_MMCM3_CLKOUT2_DIVIDE = 1 -- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT2_PHASE = 0.0 -- C_MMCM3_CLKOUT3_DIVIDE = 1 -- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT3_PHASE = 0.0 -- C_MMCM3_CLKOUT4_DIVIDE = 1 -- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT4_PHASE = 0.0 -- C_MMCM3_CLKOUT4_CASCADE = false -- C_MMCM3_CLKOUT5_DIVIDE = 1 -- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT5_PHASE = 0.0 -- C_MMCM3_CLKOUT6_DIVIDE = 1 -- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5 -- C_MMCM3_CLKOUT6_PHASE = 0.0 -- C_MMCM3_CLKOUT0_USE_FINE_PS = false -- C_MMCM3_CLKOUT1_USE_FINE_PS = false -- C_MMCM3_CLKOUT2_USE_FINE_PS = false -- C_MMCM3_CLKOUT3_USE_FINE_PS = false -- C_MMCM3_CLKOUT4_USE_FINE_PS = false -- C_MMCM3_CLKOUT5_USE_FINE_PS = false -- C_MMCM3_CLKOUT6_USE_FINE_PS = false -- C_MMCM3_COMPENSATION = "ZHOLD" -- C_MMCM3_DIVCLK_DIVIDE = 1 -- C_MMCM3_REF_JITTER1 = 0.010 -- C_MMCM3_CLKIN1_BUF = false -- C_MMCM3_CLKFBOUT_BUF = false -- C_MMCM3_CLKOUT0_BUF = false -- C_MMCM3_CLKOUT1_BUF = false -- C_MMCM3_CLKOUT2_BUF = false -- C_MMCM3_CLKOUT3_BUF = false -- C_MMCM3_CLKOUT4_BUF = false -- C_MMCM3_CLKOUT5_BUF = false -- C_MMCM3_CLKOUT6_BUF = false -- C_MMCM3_CLOCK_HOLD = false -- C_MMCM3_STARTUP_WAIT = false -- C_MMCM3_EXT_RESET_HIGH = 1 -- C_MMCM3_FAMILY = "virtex5" -- C_MMCM3_CLKIN1_MODULE = NONE -- C_MMCM3_CLKIN1_PORT = NONE -- C_MMCM3_CLKFBIN_MODULE = NONE -- C_MMCM3_CLKFBIN_PORT = NONE -- C_MMCM3_RST_MODULE = NONE ---------------------------------------- -- C_PLLE0_BANDWIDTH = "OPTIMIZED" -- C_PLLE0_CLKFBOUT_MULT = 1 -- C_PLLE0_CLKFBOUT_PHASE = 0.0 -- C_PLLE0_CLKIN1_PERIOD = 0.000 -- C_PLLE0_CLKOUT0_DIVIDE = 1 -- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT0_PHASE = 0.0 -- C_PLLE0_CLKOUT1_DIVIDE = 1 -- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT1_PHASE = 0.0 -- C_PLLE0_CLKOUT2_DIVIDE = 1 -- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT2_PHASE = 0.0 -- C_PLLE0_CLKOUT3_DIVIDE = 1 -- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT3_PHASE = 0.0 -- C_PLLE0_CLKOUT4_DIVIDE = 1 -- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT4_PHASE = 0.0 -- C_PLLE0_CLKOUT5_DIVIDE = 1 -- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5 -- C_PLLE0_CLKOUT5_PHASE = 0.0 -- C_PLLE0_COMPENSATION = "ZHOLD" -- C_PLLE0_DIVCLK_DIVIDE = 1 -- C_PLLE0_REF_JITTER1 = 0.010 -- C_PLLE0_CLKIN1_BUF = false -- C_PLLE0_CLKFBOUT_BUF = false -- C_PLLE0_CLKOUT0_BUF = false -- C_PLLE0_CLKOUT1_BUF = false -- C_PLLE0_CLKOUT2_BUF = false -- C_PLLE0_CLKOUT3_BUF = false -- C_PLLE0_CLKOUT4_BUF = false -- C_PLLE0_CLKOUT5_BUF = false -- C_PLLE0_STARTUP_WAIT = "false" -- C_PLLE0_EXT_RESET_HIGH = 1 -- C_PLLE0_FAMILY = "virtex7" -- C_PLLE0_CLKIN1_MODULE = NONE -- C_PLLE0_CLKIN1_PORT = NONE -- C_PLLE0_CLKFBIN_MODULE = NONE -- C_PLLE0_CLKFBIN_PORT = NONE -- C_PLLE0_RST_MODULE = NONE ----------------------------------------
lgpl-3.0
72683f563d25d10ec1eb265bbb4be7d6
0.551766
2.945973
false
false
false
false
jairov4/accel-oil
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_finals_buckets_if.vhd
2
21,268
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_finals_buckets_if is generic( MPMC_BASE_ADDRESS : std_logic_vector := X"00000000"; USER_DATA_WIDTH : integer := 32; USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width) ); port( --/////////////////////////////////////////////////////////////////////////////// --// MPMC Port Interface - Bus is prefixed with NPI_ NPI_clk : in std_logic; NPI_reset : in std_logic; NPI_Addr : out std_logic_vector(31 downto 0); NPI_AddrReq : out std_logic; NPI_AddrAck : in std_logic; NPI_RNW : out std_logic; NPI_Size : out std_logic_vector(3 downto 0); NPI_WrFIFO_Data : out std_logic_vector(63 downto 0); NPI_WrFIFO_BE : out std_logic_vector(7 downto 0); NPI_WrFIFO_Push : out std_logic; NPI_RdFIFO_Data : in std_logic_vector(63 downto 0); NPI_RdFIFO_Pop : out std_logic; NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0); NPI_WrFIFO_Empty : in std_logic; NPI_WrFIFO_AlmostFull : in std_logic; NPI_WrFIFO_Flush : out std_logic; NPI_RdFIFO_Empty : in std_logic; NPI_RdFIFO_Flush : out std_logic; NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0); NPI_RdModWr : out std_logic; NPI_InitDone : in std_logic; -- signals from user logic ap_clk : in std_logic; ap_reset : in std_logic; USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS USER_size : in std_logic_vector(31 downto 0); -- burst size of word USER_req_nRW : in std_logic; -- req type 0: Read, 1: write USER_req_full_n : out std_logic; -- req Fifo full USER_req_push : in std_logic; -- req Fifo push (new request in) USER_rsp_empty_n: out std_logic; -- return data FIFO empty USER_rsp_pop : in std_logic -- return data FIFO pop ); end entity; architecture arch_nfa_finals_buckets_if OF nfa_finals_buckets_if IS component nfa_finals_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : IN STD_LOGIC; clk_r : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_finals_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_finals_buckets_if_ap_fifo_af is generic ( DATA_WIDTH : integer := 64; ADDR_WIDTH : integer := 6; DEPTH : integer := 64; ALMOST_FULL_MARGIN : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; constant C_PI_ADDR_WIDTH : integer := 32; constant C_PI_DATA_WIDTH : integer := 64; constant C_PI_BE_WIDTH : integer := 8; constant C_PI_RDWDADDR_WIDTH: integer := 4; constant RSW : integer := 7; -- req size width constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data constant REQ_FIFO_ADDR_WIDTH : integer := 3; constant REQ_FIFO_DEPTH : integer := 8; type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ); signal req_cs, req_ns : req_state_type; type rdata_state_type is (RESET, IDLE, RDATA); signal rdata_cs, rdata_ns : rdata_state_type; -- User interface signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0); signal User_address_local : STD_LOGIC_VECTOR(31 downto 0); -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_dout_req_nRW : STD_LOGIC; signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_reg_en : STD_LOGIC; signal nRW_reg : STD_LOGIC; signal address_reg : STD_LOGIC_VECTOR(31 downto 0); signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0); -- internal request information signal req_nRW : STD_LOGIC; signal req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_WrData_wdAddr : STD_LOGIC; signal req_WrData_reg_en : STD_LOGIC; signal req_WrData_push : STD_LOGIC; signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_valid : STD_LOGIC; -- burst write signal burst_write_reg_en : STD_LOGIC; signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits -- burst read signal burst_read_reg_en : STD_LOGIC; signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0); signal burst_read_wdAddr : STD_LOGIC; -- rsp FIFO constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2) constant RSP_FIFO_ADDR_WIDTH : integer := 2; constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation signal rsp_fifo_empty_n : STD_LOGIC; signal rsp_fifo_pop : STD_LOGIC; signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); signal rsp_fifo_full_n : STD_LOGIC; signal rsp_fifo_push : STD_LOGIC; signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); -- internal rdata pop logic signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC; -- rd FIFO: input: MPMC data out, output: user async fifo signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); -- rd user FIFO: async fifo to user signal rd_user_fifo_empty_n : STD_LOGIC; signal rd_user_fifo_pop : STD_LOGIC; signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_user_fifo_full_n : STD_LOGIC; signal rd_user_fifo_push : STD_LOGIC; signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); begin -- NPI interface NPI_WrFIFO_Flush <= '0'; NPI_RdFIFO_Flush <= '0'; NPI_RdModWr <= '0'; NPI_AddrReq <= req_valid; NPI_Addr <= address_reg; NPI_RNW <= not nRW_reg; NPI_WrFIFO_Push <= req_WrData_push; NPI_WrFIFO_BE <= req_WrData_BE; NPI_RdFIFO_Pop <= rdata_pop; process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data) begin NPI_WrFIFO_Data <= (others => '0'); if (req_WrData_wdAddr = '0') then NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low; else NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data; end if; end process; process (size_reg) begin NPI_Size <= (others => '0'); if (size_reg = "0000100") then --4w NPI_Size <= "0001"; elsif (size_reg = "0001000") then --8w NPI_Size <= "0010"; elsif (size_reg = "0010000") then --16w NPI_Size <= "0011"; elsif (size_reg = "0100000") then --32w NPI_Size <= "0100"; elsif (size_reg = "1000000") then --64w NPI_Size <= "0101"; end if; end process; -- User interface USER_req_full_n <= req_fifo_full_n; USER_rsp_empty_n <= rd_user_fifo_empty_n; USER_RdData <= rd_user_fifo_dout; rd_user_fifo_pop <= USER_rsp_pop; USER_size_local <= User_size(RSW-1 downto 0) when User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW); USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0); USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0'); -- reqest fifo logics req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0); req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData; req_fifo_push <= USER_req_push; U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_async_fifo generic map( DATA_WIDTH => REQ_FIFO_DATA_WIDTH, ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH, DEPTH => REQ_FIFO_DEPTH) port map( clk_w => ap_clk, clk_r => NPI_clk, reset => NPI_reset, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1); req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32); req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW); process(req_fifo_dout) variable i,j: integer; begin -- change byte endian to big endian for i in 0 to USER_DATA_WIDTH/8-1 loop j := USER_DATA_WIDTH/8 -1 -i; req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8); end loop; end process; p_req_fifo_out_reg: process (NPI_clk, NPI_reset) variable i,j: integer; begin if (NPI_reset = '1') then nRW_reg <= '0'; address_reg <= (others => '0'); size_reg <= (others => '0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_reg_en = '1') then nRW_reg <= req_fifo_dout_req_nRW; address_reg <= req_fifo_dout_req_address; size_reg <= req_fifo_dout_req_size; end if; end if; end process; -- write and burst write will be controlled by state machine due to MPMC limitation -- read and burst read will have seperate return data phase logic for a pipelined access p_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then req_cs <= req_ns; end if; end process; -- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq -- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW, NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count, req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull) begin req_ns <= FETCH_REQ; req_reg_en <= '0'; req_fifo_pop <= '0'; rsp_fifo_push <= '0'; req_WrData_reg_en <= '0'; burst_write_reg_en <= '0'; req_valid <= '0'; req_WrData_push <= '0'; req_WrData_BE <= "11111111"; case req_cs is when RESET => req_ns <= RESET; if (NPI_InitDone = '1') then req_ns <= FETCH_REQ; end if; when FETCH_REQ => req_ns <= FETCH_REQ; if (req_fifo_empty_n = '1') then if (req_fifo_dout_req_nRW = '1') then req_reg_en <= '1'; req_ns <= REQ; elsif (rsp_fifo_full_n = '1') then req_reg_en <= '1'; req_fifo_pop <= '1'; rsp_fifo_push <= '1'; req_ns <= REQ; end if; end if; when REQ => req_ns <= REQ; if (nRW_reg = '0') then req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then req_valid <= '1'; if (NPI_AddrAck = '1') then req_WrData_reg_en <= '1'; req_ns <= WD_SINGLE; end if; elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then burst_write_reg_en <= '1'; req_ns <= WD_BURST1; end if; when WD_SINGLE => req_ns <= WD_SINGLE; if (NPI_WrFIFO_AlmostFull = '0') then req_WrData_push <= '1'; req_fifo_pop <= '1'; req_ns <= FETCH_REQ; end if; if (req_WrData_wdAddr = '0') then req_WrData_BE <= "00001111"; else req_WrData_BE <= "11110000"; end if; when WD_BURST1 => req_ns <= WD_BURST1; if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; req_WrData_reg_en <= '1'; req_ns <= WD_BURST2; end if; when WD_BURST2 => req_ns <= WD_BURST2; if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then req_fifo_pop <= '1'; req_WrData_push <= '1'; if (burst_write_count /= "000001") then -- not last word req_ns <= WD_BURST1; else req_ns <= WD_BURST_REQ; end if; end if; when WD_BURST_REQ => req_ns <= WD_BURST_REQ; req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_WrData_low <= (others =>'0'); req_WrData_wdAddr <= '0'; burst_write_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_WrData_reg_en = '1') then req_WrData_low <= req_fifo_dout_wr_data; req_WrData_wdAddr <= req_fifo_dout_req_address(2); end if; if (burst_write_reg_en = '1') then burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6); elsif (req_WrData_push = '1') then burst_write_count <= burst_write_count-1; end if; end if; end process; -- below is the response (read data) part U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo generic map( DATA_WIDTH => RSP_FIFO_DATA_WIDTH, ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH, DEPTH => RSP_FIFO_DEPTH) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rsp_fifo_empty_n, if_read => rsp_fifo_pop, if_dout => rsp_fifo_dout, if_full_n => rsp_fifo_full_n, if_write => rsp_fifo_push, if_din => rsp_fifo_din ); rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size; rsp_fifo_din(0) <= req_fifo_dout_req_address(2); rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_pop_reg1 <= '0'; rdata_pop_reg2 <= '0'; elsif (NPI_clk'event and NPI_clk = '1') then rdata_pop_reg1 <= rdata_pop; rdata_pop_reg2 <= rdata_pop_reg1; end if; end process; process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2) begin if (NPI_RdFIFO_Latency = "00") then rd_fifo_push <= rdata_pop; elsif (NPI_RdFIFO_Latency = "01") then rd_fifo_push <= rdata_pop_reg1; else rd_fifo_push <= rdata_pop_reg2; end if; end process; rd_fifo_din <= NPI_RdFIFO_Data; -- 1. this fifo provide two 64w burst storage -- 2. with almost full signal for MPMC has potential 2 latency from pop to data -- 3. can't replace this fifo with asyn fifo which doesn't support almost_full U_nfa_finals_buckets_if_rd_fifo: component nfa_finals_buckets_if_ap_fifo_af generic map( DATA_WIDTH => C_PI_DATA_WIDTH, ADDR_WIDTH => 6, DEPTH => 64, ALMOST_FULL_MARGIN => 2) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, -- this is almost_full signal if_write => rd_fifo_push, if_din => rd_fifo_din ); process(rd_fifo_dout) variable i,j : integer; begin -- change byte endian to big endian for i in 0 to C_PI_BE_WIDTH-1 loop j := C_PI_BE_WIDTH-1 -i; rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8); end loop; end process; p_rdata_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then rdata_cs <= rdata_ns; end if; end process; p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count) begin rdata_ns <= RESET; case rdata_cs is when RESET => if (NPI_InitDone = '1') then rdata_ns <= IDLE; end if; when IDLE => rdata_ns <= IDLE; if (rsp_fifo_empty_n = '1') then rdata_ns <= RDATA; end if; when RDATA => rdata_ns <= RDATA; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then rdata_ns <= IDLE; end if; when others => null; end case; end process; p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count, rd_fifo_empty_n, rd_user_fifo_full_n) begin burst_read_reg_en <= '0'; rd_fifo_pop <= '0'; rd_user_fifo_push <= '0'; rsp_fifo_pop <= '0'; case rdata_cs is when RESET => null; when IDLE => if (rsp_fifo_empty_n = '1') then burst_read_reg_en <= '1'; end if; when RDATA => if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and rd_user_fifo_full_n = '1') then if (burst_read_count(0) = '1') then rd_fifo_pop <= '1'; end if; rd_user_fifo_push <= '1'; end if; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then rsp_fifo_pop <= '1'; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then burst_read_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (burst_read_reg_en = '1') then burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW); burst_read_wdAddr <= rsp_fifo_dout(0); elsif (rd_user_fifo_push = '1') then burst_read_count <= burst_read_count -1; burst_read_wdAddr <= not burst_read_wdAddr; end if; end if; end process; rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH); U_nfa_finals_buckets_if_rd_user_fifo: component nfa_finals_buckets_if_async_fifo generic map( DATA_WIDTH => USER_DATA_WIDTH, ADDR_WIDTH => 3, DEPTH => 8) port map( clk_w => NPI_clk, clk_r => ap_clk, reset => NPI_reset, if_empty_n => rd_user_fifo_empty_n, if_read => rd_user_fifo_pop, if_dout => rd_user_fifo_dout, if_full_n => rd_user_fifo_full_n, if_write => rd_user_fifo_push, if_din => rd_user_fifo_din ); end arch_nfa_finals_buckets_if;
lgpl-3.0
1aa04c762abf84506d31af118d264c39
0.576735
3.088586
false
false
false
false
TWW12/lzw
final_project/lzw_compression/lzw_compression.ip_user_files/bd/design_1/hdl/design_1.vhd
1
58,845
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --Date : Tue Apr 18 19:52:27 2017 --Host : Shaun running 64-bit major release (build 9200) --Command : generate_target design_1.bd --Design : design_1 --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_UYSKKA is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC; M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC; S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s00_couplers_imp_UYSKKA; architecture STRUCTURE of s00_couplers_imp_UYSKKA is component design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_0; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC; signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; begin M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0); M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0); M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0); M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1 <= S_ARESETN; S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_0 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1, m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0), m_axi_arready => auto_pc_to_s00_couplers_ARREADY, m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0), m_axi_awready => auto_pc_to_s00_couplers_AWREADY, m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, m_axi_bready => auto_pc_to_s00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_s00_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => s00_couplers_to_auto_pc_ARREADY, s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => s00_couplers_to_auto_pc_AWREADY, s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => s00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => s00_couplers_to_auto_pc_RLAST, s_axi_rready => s00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), s_axi_wlast => s00_couplers_to_auto_pc_WLAST, s_axi_wready => s00_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => s00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_ps7_0_axi_periph_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC; M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC; M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_wready : in STD_LOGIC; M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC; S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC ); end design_1_ps7_0_axi_periph_0; architecture STRUCTURE of design_1_ps7_0_axi_periph_0 is signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC; signal ps7_0_axi_periph_ACLK_net : STD_LOGIC; signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC; signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC; signal s00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC; begin M00_AXI_araddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0); M00_AXI_arprot(2 downto 0) <= s00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0); M00_AXI_arvalid <= s00_couplers_to_ps7_0_axi_periph_ARVALID; M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0); M00_AXI_awprot(2 downto 0) <= s00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0); M00_AXI_awvalid <= s00_couplers_to_ps7_0_axi_periph_AWVALID; M00_AXI_bready <= s00_couplers_to_ps7_0_axi_periph_BREADY; M00_AXI_rready <= s00_couplers_to_ps7_0_axi_periph_RREADY; M00_AXI_wdata(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0); M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0); M00_AXI_wvalid <= s00_couplers_to_ps7_0_axi_periph_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1 <= S00_ARESETN; S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY; S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY; S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0); S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0); S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID; S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0); S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID; S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY; ps7_0_axi_periph_ACLK_net <= M00_ACLK; ps7_0_axi_periph_ARESETN_net <= M00_ARESETN; ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid; ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid; ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready; ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready; ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast; ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid; s00_couplers_to_ps7_0_axi_periph_ARREADY <= M00_AXI_arready; s00_couplers_to_ps7_0_axi_periph_AWREADY <= M00_AXI_awready; s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); s00_couplers_to_ps7_0_axi_periph_BVALID <= M00_AXI_bvalid; s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); s00_couplers_to_ps7_0_axi_periph_RVALID <= M00_AXI_rvalid; s00_couplers_to_ps7_0_axi_periph_WREADY <= M00_AXI_wready; s00_couplers: entity work.s00_couplers_imp_UYSKKA port map ( M_ACLK => ps7_0_axi_periph_ACLK_net, M_ARESETN => ps7_0_axi_periph_ARESETN_net, M_AXI_araddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arprot(2 downto 0) => s00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0), M_AXI_arready => s00_couplers_to_ps7_0_axi_periph_ARREADY, M_AXI_arvalid => s00_couplers_to_ps7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awprot(2 downto 0) => s00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0), M_AXI_awready => s00_couplers_to_ps7_0_axi_periph_AWREADY, M_AXI_awvalid => s00_couplers_to_ps7_0_axi_periph_AWVALID, M_AXI_bready => s00_couplers_to_ps7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => s00_couplers_to_ps7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => s00_couplers_to_ps7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_ps7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => s00_couplers_to_ps7_0_axi_periph_WREADY, M_AXI_wstrb(3 downto 0) => s00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0), M_AXI_wvalid => s00_couplers_to_ps7_0_axi_periph_WVALID, S_ACLK => S00_ACLK_1, S_ARESETN => S00_ARESETN_1, S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0), S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0), S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0), S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0), S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID, S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0), S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0), S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0), S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0), S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0), S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY, S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID, S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0), S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY, S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0), S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID, S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0), S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST, S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID, S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0), S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0), S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST, S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY, S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0), S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1 is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_ps7_cnt=1,synth_mode=Global}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef"; end design_1; architecture STRUCTURE of design_1 is component design_1_processing_system7_0_0 is port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component design_1_processing_system7_0_0; component design_1_rst_ps7_0_100M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component design_1_rst_ps7_0_100M_0; component design_1_axi_compression_0_0 is port ( s00_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); end component design_1_axi_compression_0_0; signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; signal processing_system7_0_DDR_CKE : STD_LOGIC; signal processing_system7_0_DDR_CK_N : STD_LOGIC; signal processing_system7_0_DDR_CK_P : STD_LOGIC; signal processing_system7_0_DDR_CS_N : STD_LOGIC; signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ODT : STD_LOGIC; signal processing_system7_0_DDR_RAS_N : STD_LOGIC; signal processing_system7_0_DDR_RESET_N : STD_LOGIC; signal processing_system7_0_DDR_WE_N : STD_LOGIC; signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC; signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin axi_compression_0: component design_1_axi_compression_0_0 port map ( s00_axi_aclk => processing_system7_0_FCLK_CLK0, s00_axi_araddr(5 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(5 downto 0), s00_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0), s00_axi_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0), s00_axi_arready => ps7_0_axi_periph_M00_AXI_ARREADY, s00_axi_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, s00_axi_awaddr(5 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(5 downto 0), s00_axi_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0), s00_axi_awready => ps7_0_axi_periph_M00_AXI_AWREADY, s00_axi_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, s00_axi_bready => ps7_0_axi_periph_M00_AXI_BREADY, s00_axi_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), s00_axi_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, s00_axi_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), s00_axi_rready => ps7_0_axi_periph_M00_AXI_RREADY, s00_axi_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), s00_axi_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, s00_axi_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), s00_axi_wready => ps7_0_axi_periph_M00_AXI_WREADY, s00_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), s00_axi_wvalid => ps7_0_axi_periph_M00_AXI_WVALID ); processing_system7_0: component design_1_processing_system7_0_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, FCLK_CLK0 => processing_system7_0_FCLK_CLK0, FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED ); ps7_0_axi_periph: entity work.design_1_ps7_0_axi_periph_0 port map ( ACLK => processing_system7_0_FCLK_CLK0, ARESETN => rst_ps7_0_100M_interconnect_aresetn(0), M00_ACLK => processing_system7_0_FCLK_CLK0, M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), M00_AXI_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0), M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY, M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID, M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), M00_AXI_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0), M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY, M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID, M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID, M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0), M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID, M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0), M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY, M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID ); rst_ps7_0_100M: component design_1_rst_ps7_0_100M_0 port map ( aux_reset_in => '1', bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0), dcm_locked => '1', ext_reset_in => processing_system7_0_FCLK_RESET0_N, interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0), mb_debug_sys_rst => '0', mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED, peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0), peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0), slowest_sync_clk => processing_system7_0_FCLK_CLK0 ); end STRUCTURE;
unlicense
165261a958013b0db05ed12542b33fea
0.672699
2.721911
false
false
false
false
jairov4/accel-oil
solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_16ns_16ns_16_4.vhd
3
9,512
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3 is component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(15 downto 0); signal b_reg : std_logic_vector(15 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(3 downto 0); signal b0_cb : std_logic_vector(3 downto 0); signal a1_cb : std_logic_vector(7 downto 4); signal b1_cb : std_logic_vector(7 downto 4); signal a2_cb : std_logic_vector(11 downto 8); signal b2_cb : std_logic_vector(11 downto 8); signal a3_cb : std_logic_vector(15 downto 12); signal b3_cb : std_logic_vector(15 downto 12); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; -- wires for each full adder sum signal fas : std_logic_vector(15 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal s0_ca_rego0 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal s1_ca_rego1 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal s2_ca_rego2 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(15 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(3 downto 0); b0_cb <= b_reg(3 downto 0); a1_cb <= a_reg(7 downto 4); b1_cb <= b_reg(7 downto 4); a2_cb <= a_reg(11 downto 8); b2_cb <= b_reg(11 downto 8); a3_cb <= a_reg(15 downto 12); b3_cb <= b_reg(15 downto 12); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(3 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(7 downto 4), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(11 downto 8), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(15 downto 12), facout => faccout3_co3); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(3 downto 0); s1_ca_rego1 (0) <= fas(7 downto 4); s2_ca_rego2 (0) <= fas(11 downto 8); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s1_ca_rego1 (1) <= s1_ca_rego1 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(3 downto 0) <= s0_ca_rego0(2); s_tmp(7 downto 4) <= s1_ca_rego1(1); s_tmp(11 downto 8) <= s2_ca_rego2(0); s_tmp(15 downto 12) <= fas(15 downto 12); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_U : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
7b9dcf233c08f8972ebb6ac44f6a90cc
0.608705
2.867651
false
false
false
false
MilosSubotic/huffman_coding
RTL/src/rtl/sort_syms_by_freq.vhd
1
15,668
------------------------------------------------------------------------------ -- @license MIT -- @brief Sorting symbols by count. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.global.all; entity sort_syms_by_freq is port( i_clk : in std_logic; in_rst : in std_logic; i_stage : in t_stage; i_pipe_en : in std_logic; i_hist : in t_freq_array(0 to 15); o_sorted_by_freq : out t_sym_and_freq_array(0 to 15) ); end entity sort_syms_by_freq; architecture arch_sort_syms_by_freq_v1 of sort_syms_by_freq is -- TODO Rename stuff. signal sym : t_sym_array(0 to 15); signal freq : t_freq_array(0 to 15); signal next_freq : t_freq_array(0 to 15); signal en_freq : t_freq_array(0 to 15); signal stage_16_freq : t_freq_array(0 to 15); signal sort_freq : t_freq_array(0 to 15); signal sort_freq_even : t_freq_array(0 to 15); signal sort_freq_odd : t_freq_array(0 to 15); signal next_sym : t_sym_array(0 to 15); signal stage_16_sym : t_sym_array(0 to 15); signal sort_sym : t_sym_array(0 to 15); signal sort_sym_even : t_sym_array(0 to 15); signal sort_sym_odd : t_sym_array(0 to 15); signal swap_even_01 : std_logic; signal swap_odd_12 : std_logic; signal swap_even_23 : std_logic; signal swap_odd_34 : std_logic; signal swap_even_45 : std_logic; signal swap_odd_56 : std_logic; signal swap_even_67 : std_logic; signal swap_odd_78 : std_logic; signal swap_even_89 : std_logic; signal swap_odd_9a : std_logic; signal swap_even_ab : std_logic; signal swap_odd_bc : std_logic; signal swap_even_cd : std_logic; signal swap_odd_de : std_logic; signal swap_even_ef : std_logic; begin -- Bubble sort. -- On stage 16 pass histogram results, if 0 put it to all 1s. -- On even stage (check LSB of i_stage) -- swap even and higher odd possitions if needed. -- On odd stage swap odd and higher even possitions if needed. -- Swap only if higher possition have lower frequency (low > high). swap_even_01 <= '1' when freq(0) > freq(1) else '0'; swap_odd_12 <= '1' when freq(1) > freq(2) else '0'; swap_even_23 <= '1' when freq(2) > freq(3) else '0'; swap_odd_34 <= '1' when freq(3) > freq(4) else '0'; swap_even_45 <= '1' when freq(4) > freq(5) else '0'; swap_odd_56 <= '1' when freq(5) > freq(6) else '0'; swap_even_67 <= '1' when freq(6) > freq(7) else '0'; swap_odd_78 <= '1' when freq(7) > freq(8) else '0'; swap_even_89 <= '1' when freq(8) > freq(9) else '0'; swap_odd_9a <= '1' when freq(9) > freq(10) else '0'; swap_even_ab <= '1' when freq(10) > freq(11) else '0'; swap_odd_bc <= '1' when freq(11) > freq(12) else '0'; swap_even_cd <= '1' when freq(12) > freq(13) else '0'; swap_odd_de <= '1' when freq(13) > freq(14) else '0'; swap_even_ef <= '1' when freq(14) > freq(15) else '0'; next_freq(0) <= en_freq(0) when i_pipe_en = '1' else freq(0); en_freq(0) <= stage_16_freq(0) when i_stage = 16 else sort_freq(0); stage_16_freq(0) <= "11111" when i_hist(0) = 0 else i_hist(0); sort_freq(0) <= sort_freq_even(0) when i_stage(0) = '0' else sort_freq_odd(0); sort_freq_even(0) <= freq(1) when swap_even_01 = '1' else freq(0); sort_freq_odd(0) <= freq(0); next_sym(0) <= stage_16_sym(0) when i_stage = 16 else sort_sym(0); stage_16_sym(0) <= conv_std_logic_vector(0, t_sym'length); sort_sym(0) <= sort_sym_even(0) when i_stage(0) = '0' else sort_sym_odd(0); sort_sym_even(0) <= sym(1) when swap_even_01 = '1' else sym(0); sort_sym_odd(0) <= sym(0); next_freq(1) <= en_freq(1) when i_pipe_en = '1' else freq(1); en_freq(1) <= stage_16_freq(1) when i_stage = 16 else sort_freq(1); stage_16_freq(1) <= "11111" when i_hist(1) = 0 else i_hist(1); sort_freq(1) <= sort_freq_even(1) when i_stage(0) = '0' else sort_freq_odd(1); sort_freq_even(1) <= freq(0) when swap_even_01 = '1' else freq(1); sort_freq_odd(1) <= freq(2) when swap_odd_12 = '1' else freq(1); next_sym(1) <= stage_16_sym(1) when i_stage = 16 else sort_sym(1); stage_16_sym(1) <= conv_std_logic_vector(1, t_sym'length); sort_sym(1) <= sort_sym_even(1) when i_stage(0) = '0' else sort_sym_odd(1); sort_sym_even(1) <= sym(0) when swap_even_01 = '1' else sym(1); sort_sym_odd(1) <= sym(2) when swap_odd_12 = '1' else sym(1); next_freq(2) <= en_freq(2) when i_pipe_en = '1' else freq(2); en_freq(2) <= stage_16_freq(2) when i_stage = 16 else sort_freq(2); stage_16_freq(2) <= "11111" when i_hist(2) = 0 else i_hist(2); sort_freq(2) <= sort_freq_even(2) when i_stage(0) = '0' else sort_freq_odd(2); sort_freq_even(2) <= freq(3) when swap_even_23 = '1' else freq(2); sort_freq_odd(2) <= freq(1) when swap_odd_12 = '1' else freq(2); next_sym(2) <= stage_16_sym(2) when i_stage = 16 else sort_sym(2); stage_16_sym(2) <= conv_std_logic_vector(2, t_sym'length); sort_sym(2) <= sort_sym_even(2) when i_stage(0) = '0' else sort_sym_odd(2); sort_sym_even(2) <= sym(3) when swap_even_23 = '1' else sym(2); sort_sym_odd(2) <= sym(1) when swap_odd_12 = '1' else sym(2); next_freq(3) <= en_freq(3) when i_pipe_en = '1' else freq(3); en_freq(3) <= stage_16_freq(3) when i_stage = 16 else sort_freq(3); stage_16_freq(3) <= "11111" when i_hist(3) = 0 else i_hist(3); sort_freq(3) <= sort_freq_even(3) when i_stage(0) = '0' else sort_freq_odd(3); sort_freq_even(3) <= freq(2) when swap_even_23 = '1' else freq(3); sort_freq_odd(3) <= freq(4) when swap_odd_34 = '1' else freq(3); next_sym(3) <= stage_16_sym(3) when i_stage = 16 else sort_sym(3); stage_16_sym(3) <= conv_std_logic_vector(3, t_sym'length); sort_sym(3) <= sort_sym_even(3) when i_stage(0) = '0' else sort_sym_odd(3); sort_sym_even(3) <= sym(2) when swap_even_23 = '1' else sym(3); sort_sym_odd(3) <= sym(4) when swap_odd_34 = '1' else sym(3); next_freq(4) <= en_freq(4) when i_pipe_en = '1' else freq(4); en_freq(4) <= stage_16_freq(4) when i_stage = 16 else sort_freq(4); stage_16_freq(4) <= "11111" when i_hist(4) = 0 else i_hist(4); sort_freq(4) <= sort_freq_even(4) when i_stage(0) = '0' else sort_freq_odd(4); sort_freq_even(4) <= freq(5) when swap_even_45 = '1' else freq(4); sort_freq_odd(4) <= freq(3) when swap_odd_34 = '1' else freq(4); next_sym(4) <= stage_16_sym(4) when i_stage = 16 else sort_sym(4); stage_16_sym(4) <= conv_std_logic_vector(4, t_sym'length); sort_sym(4) <= sort_sym_even(4) when i_stage(0) = '0' else sort_sym_odd(4); sort_sym_even(4) <= sym(5) when swap_even_45 = '1' else sym(4); sort_sym_odd(4) <= sym(3) when swap_odd_34 = '1' else sym(4); next_freq(5) <= en_freq(5) when i_pipe_en = '1' else freq(5); en_freq(5) <= stage_16_freq(5) when i_stage = 16 else sort_freq(5); stage_16_freq(5) <= "11111" when i_hist(5) = 0 else i_hist(5); sort_freq(5) <= sort_freq_even(5) when i_stage(0) = '0' else sort_freq_odd(5); sort_freq_even(5) <= freq(4) when swap_even_45 = '1' else freq(5); sort_freq_odd(5) <= freq(6) when swap_odd_56 = '1' else freq(5); next_sym(5) <= stage_16_sym(5) when i_stage = 16 else sort_sym(5); stage_16_sym(5) <= conv_std_logic_vector(5, t_sym'length); sort_sym(5) <= sort_sym_even(5) when i_stage(0) = '0' else sort_sym_odd(5); sort_sym_even(5) <= sym(4) when swap_even_45 = '1' else sym(5); sort_sym_odd(5) <= sym(6) when swap_odd_56 = '1' else sym(5); next_freq(6) <= en_freq(6) when i_pipe_en = '1' else freq(6); en_freq(6) <= stage_16_freq(6) when i_stage = 16 else sort_freq(6); stage_16_freq(6) <= "11111" when i_hist(6) = 0 else i_hist(6); sort_freq(6) <= sort_freq_even(6) when i_stage(0) = '0' else sort_freq_odd(6); sort_freq_even(6) <= freq(7) when swap_even_67 = '1' else freq(6); sort_freq_odd(6) <= freq(5) when swap_odd_56 = '1' else freq(6); next_sym(6) <= stage_16_sym(6) when i_stage = 16 else sort_sym(6); stage_16_sym(6) <= conv_std_logic_vector(6, t_sym'length); sort_sym(6) <= sort_sym_even(6) when i_stage(0) = '0' else sort_sym_odd(6); sort_sym_even(6) <= sym(7) when swap_even_67 = '1' else sym(6); sort_sym_odd(6) <= sym(5) when swap_odd_56 = '1' else sym(6); next_freq(7) <= en_freq(7) when i_pipe_en = '1' else freq(7); en_freq(7) <= stage_16_freq(7) when i_stage = 16 else sort_freq(7); stage_16_freq(7) <= "11111" when i_hist(7) = 0 else i_hist(7); sort_freq(7) <= sort_freq_even(7) when i_stage(0) = '0' else sort_freq_odd(7); sort_freq_even(7) <= freq(6) when swap_even_67 = '1' else freq(7); sort_freq_odd(7) <= freq(8) when swap_odd_78 = '1' else freq(7); next_sym(7) <= stage_16_sym(7) when i_stage = 16 else sort_sym(7); stage_16_sym(7) <= conv_std_logic_vector(7, t_sym'length); sort_sym(7) <= sort_sym_even(7) when i_stage(0) = '0' else sort_sym_odd(7); sort_sym_even(7) <= sym(6) when swap_even_67 = '1' else sym(7); sort_sym_odd(7) <= sym(8) when swap_odd_78 = '1' else sym(7); next_freq(8) <= en_freq(8) when i_pipe_en = '1' else freq(8); en_freq(8) <= stage_16_freq(8) when i_stage = 16 else sort_freq(8); stage_16_freq(8) <= "11111" when i_hist(8) = 0 else i_hist(8); sort_freq(8) <= sort_freq_even(8) when i_stage(0) = '0' else sort_freq_odd(8); sort_freq_even(8) <= freq(9) when swap_even_89 = '1' else freq(8); sort_freq_odd(8) <= freq(7) when swap_odd_78 = '1' else freq(8); next_sym(8) <= stage_16_sym(8) when i_stage = 16 else sort_sym(8); stage_16_sym(8) <= conv_std_logic_vector(8, t_sym'length); sort_sym(8) <= sort_sym_even(8) when i_stage(0) = '0' else sort_sym_odd(8); sort_sym_even(8) <= sym(9) when swap_even_89 = '1' else sym(8); sort_sym_odd(8) <= sym(7) when swap_odd_78 = '1' else sym(8); next_freq(9) <= en_freq(9) when i_pipe_en = '1' else freq(9); en_freq(9) <= stage_16_freq(9) when i_stage = 16 else sort_freq(9); stage_16_freq(9) <= "11111" when i_hist(9) = 0 else i_hist(9); sort_freq(9) <= sort_freq_even(9) when i_stage(0) = '0' else sort_freq_odd(9); sort_freq_even(9) <= freq(8) when swap_even_89 = '1' else freq(9); sort_freq_odd(9) <= freq(10) when swap_odd_9a = '1' else freq(9); next_sym(9) <= stage_16_sym(9) when i_stage = 16 else sort_sym(9); stage_16_sym(9) <= conv_std_logic_vector(9, t_sym'length); sort_sym(9) <= sort_sym_even(9) when i_stage(0) = '0' else sort_sym_odd(9); sort_sym_even(9) <= sym(8) when swap_even_89 = '1' else sym(9); sort_sym_odd(9) <= sym(10) when swap_odd_9a = '1' else sym(9); next_freq(10) <= en_freq(10) when i_pipe_en = '1' else freq(10); en_freq(10) <= stage_16_freq(10) when i_stage = 16 else sort_freq(10); stage_16_freq(10) <= "11111" when i_hist(10) = 0 else i_hist(10); sort_freq(10) <= sort_freq_even(10) when i_stage(0) = '0' else sort_freq_odd(10); sort_freq_even(10) <= freq(11) when swap_even_ab = '1' else freq(10); sort_freq_odd(10) <= freq(9) when swap_odd_9a = '1' else freq(10); next_sym(10) <= stage_16_sym(10) when i_stage = 16 else sort_sym(10); stage_16_sym(10) <= conv_std_logic_vector(10, t_sym'length); sort_sym(10) <= sort_sym_even(10) when i_stage(0) = '0' else sort_sym_odd(10); sort_sym_even(10) <= sym(11) when swap_even_ab = '1' else sym(10); sort_sym_odd(10) <= sym(9) when swap_odd_9a = '1' else sym(10); next_freq(11) <= en_freq(11) when i_pipe_en = '1' else freq(11); en_freq(11) <= stage_16_freq(11) when i_stage = 16 else sort_freq(11); stage_16_freq(11) <= "11111" when i_hist(11) = 0 else i_hist(11); sort_freq(11) <= sort_freq_even(11) when i_stage(0) = '0' else sort_freq_odd(11); sort_freq_even(11) <= freq(10) when swap_even_ab = '1' else freq(11); sort_freq_odd(11) <= freq(12) when swap_odd_bc = '1' else freq(11); next_sym(11) <= stage_16_sym(11) when i_stage = 16 else sort_sym(11); stage_16_sym(11) <= conv_std_logic_vector(11, t_sym'length); sort_sym(11) <= sort_sym_even(11) when i_stage(0) = '0' else sort_sym_odd(11); sort_sym_even(11) <= sym(10) when swap_even_ab = '1' else sym(11); sort_sym_odd(11) <= sym(12) when swap_odd_bc = '1' else sym(11); next_freq(12) <= en_freq(12) when i_pipe_en = '1' else freq(12); en_freq(12) <= stage_16_freq(12) when i_stage = 16 else sort_freq(12); stage_16_freq(12) <= "11111" when i_hist(12) = 0 else i_hist(12); sort_freq(12) <= sort_freq_even(12) when i_stage(0) = '0' else sort_freq_odd(12); sort_freq_even(12) <= freq(13) when swap_even_cd = '1' else freq(12); sort_freq_odd(12) <= freq(11) when swap_odd_bc = '1' else freq(12); next_sym(12) <= stage_16_sym(12) when i_stage = 16 else sort_sym(12); stage_16_sym(12) <= conv_std_logic_vector(12, t_sym'length); sort_sym(12) <= sort_sym_even(12) when i_stage(0) = '0' else sort_sym_odd(12); sort_sym_even(12) <= sym(13) when swap_even_cd = '1' else sym(12); sort_sym_odd(12) <= sym(11) when swap_odd_bc = '1' else sym(12); next_freq(13) <= en_freq(13) when i_pipe_en = '1' else freq(13); en_freq(13) <= stage_16_freq(13) when i_stage = 16 else sort_freq(13); stage_16_freq(13) <= "11111" when i_hist(13) = 0 else i_hist(13); sort_freq(13) <= sort_freq_even(13) when i_stage(0) = '0' else sort_freq_odd(13); sort_freq_even(13) <= freq(12) when swap_even_cd = '1' else freq(13); sort_freq_odd(13) <= freq(14) when swap_odd_de = '1' else freq(13); next_sym(13) <= stage_16_sym(13) when i_stage = 16 else sort_sym(13); stage_16_sym(13) <= conv_std_logic_vector(13, t_sym'length); sort_sym(13) <= sort_sym_even(13) when i_stage(0) = '0' else sort_sym_odd(13); sort_sym_even(13) <= sym(12) when swap_even_cd = '1' else sym(13); sort_sym_odd(13) <= sym(14) when swap_odd_de = '1' else sym(13); next_freq(14) <= en_freq(14) when i_pipe_en = '1' else freq(14); en_freq(14) <= stage_16_freq(14) when i_stage = 16 else sort_freq(14); stage_16_freq(14) <= "11111" when i_hist(14) = 0 else i_hist(14); sort_freq(14) <= sort_freq_even(14) when i_stage(0) = '0' else sort_freq_odd(14); sort_freq_even(14) <= freq(15) when swap_even_ef = '1' else freq(14); sort_freq_odd(14) <= freq(13) when swap_odd_de = '1' else freq(14); next_sym(14) <= stage_16_sym(14) when i_stage = 16 else sort_sym(14); stage_16_sym(14) <= conv_std_logic_vector(14, t_sym'length); sort_sym(14) <= sort_sym_even(14) when i_stage(0) = '0' else sort_sym_odd(14); sort_sym_even(14) <= sym(15) when swap_even_ef = '1' else sym(14); sort_sym_odd(14) <= sym(13) when swap_odd_de = '1' else sym(14); next_freq(15) <= en_freq(15) when i_pipe_en = '1' else freq(15); en_freq(15) <= stage_16_freq(15) when i_stage = 16 else sort_freq(15); stage_16_freq(15) <= "11111" when i_hist(15) = 0 else i_hist(15); sort_freq(15) <= sort_freq_even(15) when i_stage(0) = '0' else sort_freq_odd(15); sort_freq_even(15) <= freq(14) when swap_even_ef = '1' else freq(15); sort_freq_odd(15) <= freq(15); next_sym(15) <= stage_16_sym(15) when i_stage = 16 else sort_sym(15); stage_16_sym(15) <= conv_std_logic_vector(15, t_sym'length); sort_sym(15) <= sort_sym_even(15) when i_stage(0) = '0' else sort_sym_odd(15); sort_sym_even(15) <= sym(14) when swap_even_ef = '1' else sym(15); sort_sym_odd(15) <= sym(15); process(i_clk, in_rst) begin if in_rst = '0' then sym <= (others => (others => '0')); freq <= (others => (others => '0')); elsif rising_edge(i_clk) then sym <= next_sym; freq <= next_freq; end if; end process; output: for i in 0 to 15 generate o_sorted_by_freq(i).sym <= sym(i); o_sorted_by_freq(i).freq <= freq(i); end generate; end architecture arch_sort_syms_by_freq_v1;
mit
18be8efdc0935b463fb043c1ca9ccd0e
0.601481
2.332936
false
false
false
false
grwlf/vsim
vhdl_ct/ct00132.vhd
1
83,180
-- NEED RESULT: ARCH00132.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: One inertial transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: ARCH00132: Inertial semantics check on a signal asg with simple name on LHS passed -- NEED RESULT: P17: Inertial transactions entirely completed passed -- NEED RESULT: P16: Inertial transactions entirely completed passed -- NEED RESULT: P15: Inertial transactions entirely completed passed -- NEED RESULT: P14: Inertial transactions entirely completed passed -- NEED RESULT: P13: Inertial transactions entirely completed passed -- NEED RESULT: P12: Inertial transactions entirely completed passed -- NEED RESULT: P11: Inertial transactions entirely completed passed -- NEED RESULT: P10: Inertial transactions entirely completed passed -- NEED RESULT: P9: Inertial transactions entirely completed passed -- NEED RESULT: P8: Inertial transactions entirely completed passed -- NEED RESULT: P7: Inertial transactions entirely completed passed -- NEED RESULT: P6: Inertial transactions entirely completed passed -- NEED RESULT: P5: Inertial transactions entirely completed passed -- NEED RESULT: P4: Inertial transactions entirely completed passed -- NEED RESULT: P3: Inertial transactions entirely completed passed -- NEED RESULT: P2: Inertial transactions entirely completed passed -- NEED RESULT: P1: Inertial transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00132 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00132) -- ENT00132_Test_Bench(ARCH00132_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00132 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_boolean <= c_boolean_2 after 10 ns, c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P1" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; s_boolean <= c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= transport c_boolean_1 after 100 ns ; -- when 5 => correct := s_boolean = c_boolean_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 6 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= -- Last transaction above is marked c_boolean_1 after 40 ns ; -- when 7 => correct := s_boolean = c_boolean_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_boolean'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_boolean = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_bit <= c_bit_2 after 10 ns, c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P2" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; s_bit <= c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= transport c_bit_1 after 100 ns ; -- when 5 => correct := s_bit = c_bit_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_bit <= c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 6 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= -- Last transaction above is marked c_bit_1 after 40 ns ; -- when 7 => correct := s_bit = c_bit_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_bit'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_bit = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_severity_level <= c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P3" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; s_severity_level <= c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= transport c_severity_level_1 after 100 ns ; -- when 5 => correct := s_severity_level = c_severity_level_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 6 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= -- Last transaction above is marked c_severity_level_1 after 40 ns ; -- when 7 => correct := s_severity_level = c_severity_level_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_severity_level'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_severity_level = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- P4 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_character <= c_character_2 after 10 ns, c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P4" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; s_character <= c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= transport c_character_1 after 100 ns ; -- when 5 => correct := s_character = c_character_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_character <= c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 6 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= -- Last transaction above is marked c_character_1 after 40 ns ; -- when 7 => correct := s_character = c_character_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_character'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions entirely completed", chk_character = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- P5 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_enum1 <= c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P5" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1 <= c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= transport c_st_enum1_1 after 100 ns ; -- when 5 => correct := s_st_enum1 = c_st_enum1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 6 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= -- Last transaction above is marked c_st_enum1_1 after 40 ns ; -- when 7 => correct := s_st_enum1 = c_st_enum1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_enum1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions entirely completed", chk_st_enum1 = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- P6 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_integer <= c_integer_2 after 10 ns, c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P6" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; s_integer <= c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= transport c_integer_1 after 100 ns ; -- when 5 => correct := s_integer = c_integer_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_integer <= c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 6 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= -- Last transaction above is marked c_integer_1 after 40 ns ; -- when 7 => correct := s_integer = c_integer_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_integer'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions entirely completed", chk_integer = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- P7 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_int1 <= c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P7" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1 <= c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= transport c_st_int1_1 after 100 ns ; -- when 5 => correct := s_st_int1 = c_st_int1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 6 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= -- Last transaction above is marked c_st_int1_1 after 40 ns ; -- when 7 => correct := s_st_int1 = c_st_int1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_int1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions entirely completed", chk_st_int1 = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- P8 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_time <= c_time_2 after 10 ns, c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P8" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; s_time <= c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= transport c_time_1 after 100 ns ; -- when 5 => correct := s_time = c_time_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_time <= c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 6 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= -- Last transaction above is marked c_time_1 after 40 ns ; -- when 7 => correct := s_time = c_time_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_time'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions entirely completed", chk_time = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- P9 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_phys1 <= c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P9" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1 <= c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= transport c_st_phys1_1 after 100 ns ; -- when 5 => correct := s_st_phys1 = c_st_phys1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 6 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= -- Last transaction above is marked c_st_phys1_1 after 40 ns ; -- when 7 => correct := s_st_phys1 = c_st_phys1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_phys1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions entirely completed", chk_st_phys1 = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- P10 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_real <= c_real_2 after 10 ns, c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P10" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; s_real <= c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= transport c_real_1 after 100 ns ; -- when 5 => correct := s_real = c_real_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_real <= c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 6 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= -- Last transaction above is marked c_real_1 after 40 ns ; -- when 7 => correct := s_real = c_real_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_real'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Inertial transactions entirely completed", chk_real = 8 ) ; end if ; end process PGEN_CHKP_10 ; -- P11 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_real1 <= c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P11" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1 <= c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= transport c_st_real1_1 after 100 ns ; -- when 5 => correct := s_st_real1 = c_st_real1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 6 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= -- Last transaction above is marked c_st_real1_1 after 40 ns ; -- when 7 => correct := s_st_real1 = c_st_real1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_real1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Inertial transactions entirely completed", chk_st_real1 = 8 ) ; end if ; end process PGEN_CHKP_11 ; -- P12 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_rec1 <= c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P12" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1 <= c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= transport c_st_rec1_1 after 100 ns ; -- when 5 => correct := s_st_rec1 = c_st_rec1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 6 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= -- Last transaction above is marked c_st_rec1_1 after 40 ns ; -- when 7 => correct := s_st_rec1 = c_st_rec1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_rec1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Inertial transactions entirely completed", chk_st_rec1 = 8 ) ; end if ; end process PGEN_CHKP_12 ; -- P13 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_rec2 <= c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P13" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2 <= c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= transport c_st_rec2_1 after 100 ns ; -- when 5 => correct := s_st_rec2 = c_st_rec2_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 6 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= -- Last transaction above is marked c_st_rec2_1 after 40 ns ; -- when 7 => correct := s_st_rec2 = c_st_rec2_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_rec2'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Inertial transactions entirely completed", chk_st_rec2 = 8 ) ; end if ; end process PGEN_CHKP_13 ; -- P14 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_rec3 <= c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P14" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3 <= c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= transport c_st_rec3_1 after 100 ns ; -- when 5 => correct := s_st_rec3 = c_st_rec3_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 6 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= -- Last transaction above is marked c_st_rec3_1 after 40 ns ; -- when 7 => correct := s_st_rec3 = c_st_rec3_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_rec3'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Inertial transactions entirely completed", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_14 ; -- P15 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr1 <= c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P15" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 <= c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= transport c_st_arr1_1 after 100 ns ; -- when 5 => correct := s_st_arr1 = c_st_arr1_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 6 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= -- Last transaction above is marked c_st_arr1_1 after 40 ns ; -- when 7 => correct := s_st_arr1 = c_st_arr1_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Inertial transactions entirely completed", chk_st_arr1 = 8 ) ; end if ; end process PGEN_CHKP_15 ; -- P16 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr2 <= c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P16" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 <= c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= transport c_st_arr2_1 after 100 ns ; -- when 5 => correct := s_st_arr2 = c_st_arr2_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 6 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= -- Last transaction above is marked c_st_arr2_1 after 40 ns ; -- when 7 => correct := s_st_arr2 = c_st_arr2_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr2'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Inertial transactions entirely completed", chk_st_arr2 = 8 ) ; end if ; end process PGEN_CHKP_16 ; -- P17 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr3 <= c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132.P17" , "Multi inertial transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 <= c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= transport c_st_arr3_1 after 100 ns ; -- when 5 => correct := s_st_arr3 = c_st_arr3_1 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 6 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "One inertial transaction occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= -- Last transaction above is marked c_st_arr3_1 after 40 ns ; -- when 7 => correct := s_st_arr3 = c_st_arr3_1 and (savtime + 30 ns) = Std.Standard.Now ; -- -- when 8 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", correct ) ; -- when others => test_report ( "ARCH00132" , "Inertial semantics check on a signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr3'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Inertial transactions entirely completed", chk_st_arr3 = 8 ) ; end if ; end process PGEN_CHKP_17 ; -- -- end ARCH00132 ; -- entity ENT00132_Test_Bench is end ENT00132_Test_Bench ; -- architecture ARCH00132_Test_Bench of ENT00132_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00132 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00132_Test_Bench ;
gpl-3.0
9c571f8b5fb8f437cc4736200bb7ebd9
0.464943
4.181581
false
true
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/sample_iterator_get_offset.vhd
1
35,975
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0'; signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_reg_135 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_145 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_165 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_1_reg_170 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_110_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_ce : STD_LOGIC; signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_110_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_110_p0, din1 => grp_fu_110_p1, ce => grp_fu_110_ce, dout => grp_fu_110_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 1, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_125_p0, din1 => grp_fu_125_p1, ce => grp_fu_125_ce, dout => grp_fu_125_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it10 assign process. -- ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it10 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it11 assign process. -- ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it11 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it12 assign process. -- ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it12 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it13 assign process. -- ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it13 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130; ap_reg_ppstg_tmp_reg_135_pp0_it1(0) <= tmp_reg_135(0); ap_reg_ppstg_tmp_reg_135_pp0_it1(1) <= tmp_reg_135(1); ap_reg_ppstg_tmp_reg_135_pp0_it1(2) <= tmp_reg_135(2); ap_reg_ppstg_tmp_reg_135_pp0_it1(3) <= tmp_reg_135(3); ap_reg_ppstg_tmp_reg_135_pp0_it1(4) <= tmp_reg_135(4); ap_reg_ppstg_tmp_reg_135_pp0_it1(5) <= tmp_reg_135(5); ap_reg_ppstg_tmp_reg_135_pp0_it1(6) <= tmp_reg_135(6); ap_reg_ppstg_tmp_reg_135_pp0_it1(7) <= tmp_reg_135(7); ap_reg_ppstg_tmp_reg_135_pp0_it1(8) <= tmp_reg_135(8); ap_reg_ppstg_tmp_reg_135_pp0_it1(9) <= tmp_reg_135(9); ap_reg_ppstg_tmp_reg_135_pp0_it1(10) <= tmp_reg_135(10); ap_reg_ppstg_tmp_reg_135_pp0_it1(11) <= tmp_reg_135(11); ap_reg_ppstg_tmp_reg_135_pp0_it1(12) <= tmp_reg_135(12); ap_reg_ppstg_tmp_reg_135_pp0_it1(13) <= tmp_reg_135(13); ap_reg_ppstg_tmp_reg_135_pp0_it1(14) <= tmp_reg_135(14); ap_reg_ppstg_tmp_reg_135_pp0_it1(15) <= tmp_reg_135(15); ap_reg_ppstg_tmp_reg_135_pp0_it2(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(0); ap_reg_ppstg_tmp_reg_135_pp0_it2(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(1); ap_reg_ppstg_tmp_reg_135_pp0_it2(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(2); ap_reg_ppstg_tmp_reg_135_pp0_it2(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(3); ap_reg_ppstg_tmp_reg_135_pp0_it2(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(4); ap_reg_ppstg_tmp_reg_135_pp0_it2(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(5); ap_reg_ppstg_tmp_reg_135_pp0_it2(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(6); ap_reg_ppstg_tmp_reg_135_pp0_it2(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(7); ap_reg_ppstg_tmp_reg_135_pp0_it2(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(8); ap_reg_ppstg_tmp_reg_135_pp0_it2(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(9); ap_reg_ppstg_tmp_reg_135_pp0_it2(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(10); ap_reg_ppstg_tmp_reg_135_pp0_it2(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(11); ap_reg_ppstg_tmp_reg_135_pp0_it2(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(12); ap_reg_ppstg_tmp_reg_135_pp0_it2(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(13); ap_reg_ppstg_tmp_reg_135_pp0_it2(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(14); ap_reg_ppstg_tmp_reg_135_pp0_it2(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(15); ap_reg_ppstg_tmp_reg_135_pp0_it3(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(0); ap_reg_ppstg_tmp_reg_135_pp0_it3(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(1); ap_reg_ppstg_tmp_reg_135_pp0_it3(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(2); ap_reg_ppstg_tmp_reg_135_pp0_it3(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(3); ap_reg_ppstg_tmp_reg_135_pp0_it3(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(4); ap_reg_ppstg_tmp_reg_135_pp0_it3(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(5); ap_reg_ppstg_tmp_reg_135_pp0_it3(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(6); ap_reg_ppstg_tmp_reg_135_pp0_it3(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(7); ap_reg_ppstg_tmp_reg_135_pp0_it3(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(8); ap_reg_ppstg_tmp_reg_135_pp0_it3(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(9); ap_reg_ppstg_tmp_reg_135_pp0_it3(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(10); ap_reg_ppstg_tmp_reg_135_pp0_it3(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(11); ap_reg_ppstg_tmp_reg_135_pp0_it3(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(12); ap_reg_ppstg_tmp_reg_135_pp0_it3(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(13); ap_reg_ppstg_tmp_reg_135_pp0_it3(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(14); ap_reg_ppstg_tmp_reg_135_pp0_it3(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_130 <= i_sample; tmp_reg_135(0) <= tmp_fu_93_p1(0); tmp_reg_135(1) <= tmp_fu_93_p1(1); tmp_reg_135(2) <= tmp_fu_93_p1(2); tmp_reg_135(3) <= tmp_fu_93_p1(3); tmp_reg_135(4) <= tmp_fu_93_p1(4); tmp_reg_135(5) <= tmp_fu_93_p1(5); tmp_reg_135(6) <= tmp_fu_93_p1(6); tmp_reg_135(7) <= tmp_fu_93_p1(7); tmp_reg_135(8) <= tmp_fu_93_p1(8); tmp_reg_135(9) <= tmp_fu_93_p1(9); tmp_reg_135(10) <= tmp_fu_93_p1(10); tmp_reg_135(11) <= tmp_fu_93_p1(11); tmp_reg_135(12) <= tmp_fu_93_p1(12); tmp_reg_135(13) <= tmp_fu_93_p1(13); tmp_reg_135(14) <= tmp_fu_93_p1(14); tmp_reg_135(15) <= tmp_fu_93_p1(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_165 <= indices_begin_datain; tmp_1_reg_170 <= grp_fu_110_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_145 <= indices_stride_datain; end if; end if; end process; tmp_reg_135(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it2(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it3(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it5 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it13, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= grp_fu_125_p2; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_110_ce assign process. -- grp_fu_110_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_110_ce <= ap_const_logic_1; else grp_fu_110_ce <= ap_const_logic_0; end if; end process; grp_fu_110_p0 <= grp_fu_110_p00(16 - 1 downto 0); grp_fu_110_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1),24)); grp_fu_110_p1 <= grp_fu_110_p10(8 - 1 downto 0); grp_fu_110_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_145),24)); -- grp_fu_125_ce assign process. -- grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_125_ce <= ap_const_logic_1; else grp_fu_125_ce <= ap_const_logic_0; end if; end process; grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_1_reg_170),32)); grp_fu_125_p1 <= indices_begin_addr_read_reg_165; indices_begin_address <= ap_reg_ppstg_tmp_reg_135_pp0_it3; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1; indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),32)); end behav;
lgpl-3.0
bcefd20dc09e0e9f25c9b6b82e4d8bbc
0.607088
2.598786
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/p_bsf32_hw/_primary.vhd
1
8,984
library verilog; use verilog.vl_types.all; entity p_bsf32_hw is generic( ap_const_lv5_0 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi0); ap_true : vl_logic := Hi1; ap_const_lv1_0 : vl_logic := Hi0; ap_const_lv5_1 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi1); ap_const_lv5_2 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi0); ap_const_lv5_3 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi1); ap_const_lv5_4 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi0); ap_const_lv5_5 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi1); ap_const_lv5_6 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi0); ap_const_lv5_7 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi1); ap_const_lv5_8 : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi0); ap_const_lv5_9 : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi1); ap_const_lv5_A : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi1, Hi0); ap_const_lv5_B : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi1, Hi1); ap_const_lv5_C : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi0); ap_const_lv5_D : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi1); ap_const_lv5_E : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi0); ap_const_lv5_F : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi1); ap_const_lv5_10 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi0); ap_const_lv5_11 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi1); ap_const_lv5_12 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi1, Hi0); ap_const_lv5_13 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi1, Hi1); ap_const_lv5_14 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi1, Hi0, Hi0); ap_const_lv5_15 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi1, Hi0, Hi1); ap_const_lv5_16 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi1, Hi1, Hi0); ap_const_lv5_17 : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi1, Hi1, Hi1); ap_const_lv5_18 : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0); ap_const_lv5_19 : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi1); ap_const_lv5_1A : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi1, Hi0); ap_const_lv5_1B : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi1, Hi1); ap_const_lv5_1C : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi1, Hi0, Hi0); ap_const_lv5_1D : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi1, Hi0, Hi1); ap_const_lv5_1E : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi1, Hi1, Hi0); ap_const_lv5_1F : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi1, Hi1, Hi1); ap_const_lv32_1 : integer := 1; ap_const_lv32_2 : integer := 2; ap_const_lv32_3 : integer := 3; ap_const_lv32_4 : integer := 4; ap_const_lv32_5 : integer := 5; ap_const_lv32_6 : integer := 6; ap_const_lv32_7 : integer := 7; ap_const_lv32_8 : integer := 8; ap_const_lv32_9 : integer := 9; ap_const_lv32_A : integer := 10; ap_const_lv32_B : integer := 11; ap_const_lv32_C : integer := 12; ap_const_lv32_D : integer := 13; ap_const_lv32_E : integer := 14; ap_const_lv32_F : integer := 15; ap_const_lv32_10: integer := 16; ap_const_lv32_11: integer := 17; ap_const_lv32_12: integer := 18; ap_const_lv32_13: integer := 19; ap_const_lv32_14: integer := 20; ap_const_lv32_15: integer := 21; ap_const_lv32_16: integer := 22; ap_const_lv32_17: integer := 23; ap_const_lv32_18: integer := 24; ap_const_lv32_19: integer := 25; ap_const_lv32_1A: integer := 26; ap_const_lv32_1B: integer := 27; ap_const_lv32_1C: integer := 28; ap_const_lv32_1D: integer := 29; ap_const_lv32_1E: integer := 30; ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0 ); port( bus_r : in vl_logic_vector(31 downto 0); ap_return : out vl_logic_vector(4 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_lv5_0 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; attribute mti_svvh_generic_type of ap_const_lv1_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_2 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_3 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_4 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_5 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_6 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_7 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_8 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_9 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_A : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_B : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_C : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_D : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_E : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_F : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_10 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_11 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_12 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_13 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_14 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_15 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_16 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_17 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_18 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_19 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1A : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1B : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1C : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1D : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1E : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_1F : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_2 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_3 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_4 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_5 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_6 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_7 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_8 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_9 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_A : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_B : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_C : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_D : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_E : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_F : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_10 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_11 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_12 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_13 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_14 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_15 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_16 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_17 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_18 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_19 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1A : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1B : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1C : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1D : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1E : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; end p_bsf32_hw;
lgpl-3.0
53510dae10b50ddf762f116ab0c77971
0.634795
2.718306
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/hdl/system_mb_plb_wrapper.vhd
1
14,662
------------------------------------------------------------------------------- -- system_mb_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_mb_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 1); MPLB_Rst : out std_logic_vector(0 to 6); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 223); M_UABus : in std_logic_vector(0 to 223); M_BE : in std_logic_vector(0 to 55); M_RNW : in std_logic_vector(0 to 6); M_abort : in std_logic_vector(0 to 6); M_busLock : in std_logic_vector(0 to 6); M_TAttribute : in std_logic_vector(0 to 111); M_lockErr : in std_logic_vector(0 to 6); M_MSize : in std_logic_vector(0 to 13); M_priority : in std_logic_vector(0 to 13); M_rdBurst : in std_logic_vector(0 to 6); M_request : in std_logic_vector(0 to 6); M_size : in std_logic_vector(0 to 27); M_type : in std_logic_vector(0 to 20); M_wrBurst : in std_logic_vector(0 to 6); M_wrDBus : in std_logic_vector(0 to 447); Sl_addrAck : in std_logic_vector(0 to 1); Sl_MRdErr : in std_logic_vector(0 to 13); Sl_MWrErr : in std_logic_vector(0 to 13); Sl_MBusy : in std_logic_vector(0 to 13); Sl_rdBTerm : in std_logic_vector(0 to 1); Sl_rdComp : in std_logic_vector(0 to 1); Sl_rdDAck : in std_logic_vector(0 to 1); Sl_rdDBus : in std_logic_vector(0 to 127); Sl_rdWdAddr : in std_logic_vector(0 to 7); Sl_rearbitrate : in std_logic_vector(0 to 1); Sl_SSize : in std_logic_vector(0 to 3); Sl_wait : in std_logic_vector(0 to 1); Sl_wrBTerm : in std_logic_vector(0 to 1); Sl_wrComp : in std_logic_vector(0 to 1); Sl_wrDAck : in std_logic_vector(0 to 1); Sl_MIRQ : in std_logic_vector(0 to 13); PLB_MIRQ : out std_logic_vector(0 to 6); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 6); PLB_MTimeout : out std_logic_vector(0 to 6); PLB_MBusy : out std_logic_vector(0 to 6); PLB_MRdErr : out std_logic_vector(0 to 6); PLB_MWrErr : out std_logic_vector(0 to 6); PLB_MRdBTerm : out std_logic_vector(0 to 6); PLB_MRdDAck : out std_logic_vector(0 to 6); PLB_MRdDBus : out std_logic_vector(0 to 447); PLB_MRdWdAddr : out std_logic_vector(0 to 27); PLB_MRearbitrate : out std_logic_vector(0 to 6); PLB_MWrBTerm : out std_logic_vector(0 to 6); PLB_MWrDAck : out std_logic_vector(0 to 6); PLB_MSSize : out std_logic_vector(0 to 13); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 2); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 6); PLB_SMWrErr : out std_logic_vector(0 to 6); PLB_SMBusy : out std_logic_vector(0 to 6); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_mb_plb_wrapper : entity is "plb_v46_v1_05_a"; end system_mb_plb_wrapper; architecture STRUCTURE of system_mb_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin mb_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 7, C_PLBV46_NUM_SLAVES => 2, C_PLBV46_MID_WIDTH => 3, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;
lgpl-3.0
ef2895d938fd3b25bdfe2c8a0c738998
0.611104
3.036868
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/frontend/fir_band_pass_ast.vhd
1
6,846
-- ================================================================================ -- Legal Notice: Copyright (C) 1991-2006 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- ================================================================================ -- -- Generated by: FIR Compiler 12.1 -- Generated on: 2013-11-15 19:24:19 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library auk_dspip_lib; use auk_dspip_lib.auk_dspip_lib_pkg_fir_121.all; entity fir_band_pass_ast is port( clk : in std_logic; reset_n : in std_logic; ast_sink_ready : out std_logic; ast_source_data : out std_logic_vector (16 -1 downto 0); ast_sink_data : in std_logic_vector (12 -1 downto 0); ast_sink_valid : in std_logic; ast_source_valid : out std_logic; ast_source_ready : in std_logic; ast_sink_error : in std_logic_vector (1 downto 0); ast_source_error : out std_logic_vector (1 downto 0) ); attribute altera_attribute : string; attribute altera_attribute of fir_band_pass_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036"; end fir_band_pass_ast; -- Warnings Suppression On -- altera message_off 10036 architecture struct of fir_band_pass_ast is signal sink_packet_error : std_logic_vector(1 downto 0); signal data_in : std_logic_vector(12 -1 downto 0); signal data_out : std_logic_vector(16 -1 downto 0); signal core_out : std_logic_vector(16 -1 downto 0); signal ready : std_logic; signal reset_fir : std_logic; signal sink_ready_ctrl : std_logic; signal sink_stall : std_logic; signal source_packet_error : std_logic_vector(1 downto 0); signal source_stall : std_logic; signal source_valid_ctrl : std_logic; signal stall : std_logic; signal valid : std_logic; signal core_valid : std_logic; signal enable_in : std_logic; signal stall_delayed : std_logic; constant ENABLE_PIPELINE_DEPTH_c : natural := 0; component fir_band_pass_st is port ( rst : in std_logic; clk : in std_logic; clk_en : in std_logic; rdy_to_ld : out std_logic; done : out std_logic; data_in : in std_logic_vector(12 - 1 downto 0); fir_result : out std_logic_vector(16 - 1 downto 0)); end component fir_band_pass_st; begin sink : auk_dspip_avalon_streaming_sink_fir_121 generic map ( WIDTH_g => 12, PACKET_SIZE_g => 1, FIFO_DEPTH_g => 7, FAMILY_g => "Cyclone III", MEM_TYPE_g => "Auto") port map ( clk => clk, reset_n => reset_n, data => data_in, sink_ready_ctrl => sink_ready_ctrl, sink_stall => sink_stall, packet_error => sink_packet_error, at_sink_ready => ast_sink_ready, at_sink_valid => ast_sink_valid, at_sink_data => ast_sink_data, at_sink_error => ast_sink_error); source : auk_dspip_avalon_streaming_source_fir_121 generic map ( WIDTH_g => 16, packet_size_g => 1) port map ( clk => clk, reset_n => reset_n, data => data_out, source_valid_ctrl => source_valid_ctrl, design_stall => stall_delayed, source_stall => source_stall, packet_error => source_packet_error, at_source_ready => ast_source_ready, at_source_valid => ast_source_valid, at_source_data => ast_source_data, at_source_error => ast_source_error); intf_ctrl : auk_dspip_avalon_streaming_controller_fir_121 port map ( clk => clk, ready => ready, reset_n => reset_n, sink_packet_error => sink_packet_error, sink_stall => sink_stall, source_stall => source_stall, valid => valid, reset_design => reset_fir, sink_ready_ctrl => sink_ready_ctrl, source_packet_error => source_packet_error, source_valid_ctrl => source_valid_ctrl, stall => stall); fircore: fir_band_pass_st port map ( rst => reset_fir, clk => clk, clk_en => enable_in, rdy_to_ld => ready, done => core_valid, data_in => data_in, fir_result => core_out); data_out <= core_out; valid <= core_valid; enable_in <= not stall; no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate stall_delayed <= stall; end generate no_enable_pipeline; enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate delay_core_enable : process (clk, reset_n) variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0); begin -- process delay_core_enable if reset_n = '0' then stall_delay := (others => '0'); elsif rising_edge(clk) then stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall; end if; stall_delayed <= stall_delay(stall_delay'high); end process delay_core_enable; end generate enable_pipeline; end struct;
apache-2.0
368c899e60ba638af2d2532f32538c2c
0.604879
3.78232
false
false
false
false
grwlf/vsim
vhdl_ct/ct00033.vhd
1
24,181
-- NEED RESULT: ARCH00033.P1: Target of a variable assignment may be a aggregate of indexed names passed -- NEED RESULT: ARCH00033.P2: Target of a variable assignment may be a aggregate of indexed names passed -- NEED RESULT: ARCH00033.P3: Target of a variable assignment may be a aggregate of indexed names passed -- NEED RESULT: ARCH00033.P4: Target of a variable assignment may be a aggregate of indexed names passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00033 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00033) -- ENT00033_Test_Bench(ARCH00033_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00033 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- variable v_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_2 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_2 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_3 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_3 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; begin ( v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ; -- ( v_st_arr1_1(st_arr1'Left) , v_st_arr1_2(st_arr1'Left) , v_st_arr1_3(st_arr1'Left) ) := arr_st_int1 ' ( (others => c_st_arr1_2(st_arr1'Right))) ; -- ( v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ; -- ( v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) ) := arr_st_rec3 ' ( (others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ; -- correct := correct and v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_1(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_2(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_3(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- test_report ( "ARCH00033.P1" , "Target of a variable assignment may be a " & "aggregate of indexed names" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- variable v_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_2 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_2 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_3 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_3 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- begin ( v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ; -- ( v_st_arr1_1(st_arr1'Left) , v_st_arr1_2(st_arr1'Left) , v_st_arr1_3(st_arr1'Left) ) := arr_st_int1 ' ( (others => c_st_arr1_2(st_arr1'Right))) ; -- ( v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ; -- ( v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) ) := arr_st_rec3 ' ( (others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ; -- correct := correct and v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_1(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_2(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_3(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00033.P2" , "Target of a variable assignment may be a " & "aggregate of indexed names" , correct) ; end process P2 ; -- P3 : process ( Dummy ) type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- variable v_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_2 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_2 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_3 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_3 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin ( v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ; -- ( v_st_arr1_1(st_arr1'Left) , v_st_arr1_2(st_arr1'Left) , v_st_arr1_3(st_arr1'Left) ) := arr_st_int1 ' ( (others => c_st_arr1_2(st_arr1'Right))) ; -- ( v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ; -- ( v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) ) := arr_st_rec3 ' ( (others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_1(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_2(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- correct := correct and v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_3(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- test_report ( "ARCH00033.P3" , "Target of a variable assignment may be a " & "aggregate of indexed names" , correct) ; end process P3 ; -- P4 : process ( Dummy ) type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- variable v_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_2 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_2 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- variable v_st_rec3_3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1_3 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2_3 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_rec3_2 : inout st_rec3 ; v_st_arr1_2 : inout st_arr1 ; v_st_arr2_2 : inout st_arr2 ; v_st_arr3_2 : inout st_arr3 ) is begin ( v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) , v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2) ))) ; -- ( v_st_arr1_1(st_arr1'Left) , v_st_arr1_2(st_arr1'Left) , v_st_arr1_3(st_arr1'Left) ) := arr_st_int1 ' ( (others => c_st_arr1_2(st_arr1'Right))) ; -- ( v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) , v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) ) := arr_st_arr1 ' ( (others => c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)))) ; -- ( v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) , v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) ) := arr_st_rec3 ' ( (others => c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)))) ; -- end Proc1 ; begin Proc1 ( v_st_rec3_1 , v_st_arr1_1 , v_st_arr2_1 , v_st_arr3_1 ) ; correct := correct and v_st_rec3_1.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_1(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_1(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_1(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- Proc1 ( v_st_rec3_2 , v_st_arr1_2 , v_st_arr2_2 , v_st_arr3_2 ) ; correct := correct and v_st_rec3_2.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_2(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_2(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- Proc1 ( v_st_rec3_3 , v_st_arr1_3 , v_st_arr2_3 , v_st_arr3_3 ) ; correct := correct and v_st_rec3_3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr1_3(st_arr1'Left) = c_st_int1_2 ; correct := correct and v_st_arr2_3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2 ; correct := correct and v_st_arr3_3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2 ; -- test_report ( "ARCH00033.P4" , "Target of a variable assignment may be a " & "aggregate of indexed names" , correct) ; end process P4 ; -- end ARCH00033 ; -- entity ENT00033_Test_Bench is end ENT00033_Test_Bench ; -- architecture ARCH00033_Test_Bench of ENT00033_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00033 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00033_Test_Bench ;
gpl-3.0
66efe1381ca3cd9aca3f9e2cc2dfee12
0.456929
3.010958
false
false
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_32ns_32s_32_8.vhd
6
15,847
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(31 downto 0); b: in std_logic_vector(31 downto 0); s: out std_logic_vector(31 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(31 downto 0); signal b_reg : std_logic_vector(31 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(3 downto 0); signal b0_cb : std_logic_vector(3 downto 0); signal a1_cb : std_logic_vector(7 downto 4); signal b1_cb : std_logic_vector(7 downto 4); signal a2_cb : std_logic_vector(11 downto 8); signal b2_cb : std_logic_vector(11 downto 8); signal a3_cb : std_logic_vector(15 downto 12); signal b3_cb : std_logic_vector(15 downto 12); signal a4_cb : std_logic_vector(19 downto 16); signal b4_cb : std_logic_vector(19 downto 16); signal a5_cb : std_logic_vector(23 downto 20); signal b5_cb : std_logic_vector(23 downto 20); signal a6_cb : std_logic_vector(27 downto 24); signal b6_cb : std_logic_vector(27 downto 24); signal a7_cb : std_logic_vector(31 downto 28); signal b7_cb : std_logic_vector(31 downto 28); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal a4_cb_regi4 : ramtypei3; signal b4_cb_regi4 : ramtypei3; type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal a5_cb_regi5 : ramtypei4; signal b5_cb_regi5 : ramtypei4; type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal a6_cb_regi6 : ramtypei5; signal b6_cb_regi6 : ramtypei5; type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal a7_cb_regi7 : ramtypei6; signal b7_cb_regi7 : ramtypei6; -- wires for each full adder sum signal fas : std_logic_vector(31 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout4_co4 : std_logic_vector (0 downto 0); signal faccout5_co5 : std_logic_vector (0 downto 0); signal faccout6_co6 : std_logic_vector (0 downto 0); signal faccout7_co7 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); signal faccout3_co3_reg : std_logic_vector (0 downto 0); signal faccout4_co4_reg : std_logic_vector (0 downto 0); signal faccout5_co5_reg : std_logic_vector (0 downto 0); signal faccout6_co6_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal s0_ca_rego0 : ramtypeo6; type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal s1_ca_rego1 : ramtypeo5; type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal s2_ca_rego2 : ramtypeo4; type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal s3_ca_rego3 : ramtypeo3; type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal s4_ca_rego4 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal s5_ca_rego5 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal s6_ca_rego6 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(31 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(3 downto 0); b0_cb <= b_reg(3 downto 0); a1_cb <= a_reg(7 downto 4); b1_cb <= b_reg(7 downto 4); a2_cb <= a_reg(11 downto 8); b2_cb <= b_reg(11 downto 8); a3_cb <= a_reg(15 downto 12); b3_cb <= b_reg(15 downto 12); a4_cb <= a_reg(19 downto 16); b4_cb <= b_reg(19 downto 16); a5_cb <= a_reg(23 downto 20); b5_cb <= b_reg(23 downto 20); a6_cb <= a_reg(27 downto 24); b6_cb <= b_reg(27 downto 24); a7_cb <= a_reg(31 downto 28); b7_cb <= b_reg(31 downto 28); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a4_cb_regi4 (0) <= a4_cb; b4_cb_regi4 (0) <= b4_cb; a5_cb_regi5 (0) <= a5_cb; b5_cb_regi5 (0) <= b5_cb; a6_cb_regi6 (0) <= a6_cb; b6_cb_regi6 (0) <= b6_cb; a7_cb_regi7 (0) <= a7_cb; b7_cb_regi7 (0) <= b7_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a4_cb_regi4 (1) <= a4_cb_regi4 (0); b4_cb_regi4 (1) <= b4_cb_regi4 (0); a5_cb_regi5 (1) <= a5_cb_regi5 (0); b5_cb_regi5 (1) <= b5_cb_regi5 (0); a6_cb_regi6 (1) <= a6_cb_regi6 (0); b6_cb_regi6 (1) <= b6_cb_regi6 (0); a7_cb_regi7 (1) <= a7_cb_regi7 (0); b7_cb_regi7 (1) <= b7_cb_regi7 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); a4_cb_regi4 (2) <= a4_cb_regi4 (1); b4_cb_regi4 (2) <= b4_cb_regi4 (1); a5_cb_regi5 (2) <= a5_cb_regi5 (1); b5_cb_regi5 (2) <= b5_cb_regi5 (1); a6_cb_regi6 (2) <= a6_cb_regi6 (1); b6_cb_regi6 (2) <= b6_cb_regi6 (1); a7_cb_regi7 (2) <= a7_cb_regi7 (1); b7_cb_regi7 (2) <= b7_cb_regi7 (1); a4_cb_regi4 (3) <= a4_cb_regi4 (2); b4_cb_regi4 (3) <= b4_cb_regi4 (2); a5_cb_regi5 (3) <= a5_cb_regi5 (2); b5_cb_regi5 (3) <= b5_cb_regi5 (2); a6_cb_regi6 (3) <= a6_cb_regi6 (2); b6_cb_regi6 (3) <= b6_cb_regi6 (2); a7_cb_regi7 (3) <= a7_cb_regi7 (2); b7_cb_regi7 (3) <= b7_cb_regi7 (2); a5_cb_regi5 (4) <= a5_cb_regi5 (3); b5_cb_regi5 (4) <= b5_cb_regi5 (3); a6_cb_regi6 (4) <= a6_cb_regi6 (3); b6_cb_regi6 (4) <= b6_cb_regi6 (3); a7_cb_regi7 (4) <= a7_cb_regi7 (3); b7_cb_regi7 (4) <= b7_cb_regi7 (3); a6_cb_regi6 (5) <= a6_cb_regi6 (4); b6_cb_regi6 (5) <= b6_cb_regi6 (4); a7_cb_regi7 (5) <= a7_cb_regi7 (4); b7_cb_regi7 (5) <= b7_cb_regi7 (4); a7_cb_regi7 (6) <= a7_cb_regi7 (5); b7_cb_regi7 (6) <= b7_cb_regi7 (5); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; faccout3_co3_reg <= faccout3_co3; faccout4_co4_reg <= faccout4_co4; faccout5_co5_reg <= faccout5_co5; faccout6_co6_reg <= faccout6_co6; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(3 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(7 downto 4), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(11 downto 8), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(15 downto 12), facout => faccout3_co3); u4 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a4_cb_regi4(3), fab => b4_cb_regi4(3), facin => faccout3_co3_reg, fas => fas(19 downto 16), facout => faccout4_co4); u5 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a5_cb_regi5(4), fab => b5_cb_regi5(4), facin => faccout4_co4_reg, fas => fas(23 downto 20), facout => faccout5_co5); u6 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder port map (faa => a6_cb_regi6(5), fab => b6_cb_regi6(5), facin => faccout5_co5_reg, fas => fas(27 downto 24), facout => faccout6_co6); u7 : nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f port map (faa => a7_cb_regi7(6), fab => b7_cb_regi7(6), facin => faccout6_co6_reg, fas => fas(31 downto 28), facout => faccout7_co7); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(3 downto 0); s1_ca_rego1 (0) <= fas(7 downto 4); s2_ca_rego2 (0) <= fas(11 downto 8); s3_ca_rego3 (0) <= fas(15 downto 12); s4_ca_rego4 (0) <= fas(19 downto 16); s5_ca_rego5 (0) <= fas(23 downto 20); s6_ca_rego6 (0) <= fas(27 downto 24); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s0_ca_rego0 (3) <= s0_ca_rego0 (2); s0_ca_rego0 (4) <= s0_ca_rego0 (3); s0_ca_rego0 (5) <= s0_ca_rego0 (4); s0_ca_rego0 (6) <= s0_ca_rego0 (5); s1_ca_rego1 (1) <= s1_ca_rego1 (0); s1_ca_rego1 (2) <= s1_ca_rego1 (1); s1_ca_rego1 (3) <= s1_ca_rego1 (2); s1_ca_rego1 (4) <= s1_ca_rego1 (3); s1_ca_rego1 (5) <= s1_ca_rego1 (4); s2_ca_rego2 (1) <= s2_ca_rego2 (0); s2_ca_rego2 (2) <= s2_ca_rego2 (1); s2_ca_rego2 (3) <= s2_ca_rego2 (2); s2_ca_rego2 (4) <= s2_ca_rego2 (3); s3_ca_rego3 (1) <= s3_ca_rego3 (0); s3_ca_rego3 (2) <= s3_ca_rego3 (1); s3_ca_rego3 (3) <= s3_ca_rego3 (2); s4_ca_rego4 (1) <= s4_ca_rego4 (0); s4_ca_rego4 (2) <= s4_ca_rego4 (1); s5_ca_rego5 (1) <= s5_ca_rego5 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(3 downto 0) <= s0_ca_rego0(6); s_tmp(7 downto 4) <= s1_ca_rego1(5); s_tmp(11 downto 8) <= s2_ca_rego2(4); s_tmp(15 downto 12) <= s3_ca_rego3(3); s_tmp(19 downto 16) <= s4_ca_rego4(2); s_tmp(23 downto 20) <= s5_ca_rego5(1); s_tmp(27 downto 24) <= s6_ca_rego6(0); s_tmp(31 downto 28) <= fas(31 downto 28); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_32ns_32s_32_8 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_32ns_32s_32_8 is component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_U : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
1462378d00d8bdcce44786bc064afd9a
0.584148
2.630207
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/frontend/tb_fir_band_pass.vhd
1
8,702
-- ================================================================================ -- Legal Notice: Copyright (C) 1991-2006 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- ================================================================================ -- -- Generated by: FIR Compiler 12.1 -- Generated on: 2013-11-15 19:24:19 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity tb_fir_band_pass is --START MEGAWIZARD INSERT CONSTANTS constant FIR_INPUT_FILE_c : string := "fir_band_pass_input.txt"; constant FIR_OUTPUT_FILE_c : string := "fir_band_pass_output.txt"; constant NUM_OF_CHANNELS_c : natural := 1; constant DATA_WIDTH_c : natural := 12; constant CHANNEL_OUT_WIDTH_c : natural := 0; constant OUT_WIDTH_c : natural := 16; constant COEF_SET_ADDRESS_WIDTH_c : natural := 0; constant COEF_RELOAD_BIT_WIDTH_c : natural := 14; --END MEGAWIZARD INSERT CONSTANTS end entity tb_fir_band_pass; --library work; --library auk_dspip_lib; ------------------------------------------------------------------------------- architecture rtl of tb_fir_band_pass is signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0'); signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0); signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0'); signal ast_source_error : std_logic_vector (1 downto 0); signal ast_sink_valid : std_logic := '0'; signal ast_source_valid : std_logic; signal ast_source_ready : std_logic := '0'; signal clk : std_logic := '0'; signal reset_testbench : std_logic := '0'; signal reset_design : std_logic; signal eof : std_logic; signal ast_sink_ready : std_logic; signal start : std_logic; signal cnt : natural range 0 to NUM_OF_CHANNELS_c; constant tclk : time := 10 ns; constant time_lapse_max : time := 60 us; signal time_lapse : time; begin DUT : entity work.fir_band_pass port map ( clk => clk, reset_n => reset_design, ast_sink_ready => ast_sink_ready, ast_sink_data => ast_sink_data, ast_source_data => ast_source_data, ast_sink_valid => ast_sink_valid, ast_source_valid => ast_source_valid, ast_source_ready => ast_source_ready, ast_sink_error => ast_sink_error, ast_source_error => ast_source_error); -- for example purposes, the ready signal is always asserted. ast_source_ready <= '1'; -- no input error ast_sink_error <= (others => '0'); -- start valid for first cycle to indicate that the file reading should start. start_p : process (clk, reset_testbench) begin if reset_testbench = '0' then start <= '1'; elsif rising_edge(clk) then if ast_sink_valid = '1' and ast_sink_ready = '1' then start <= '0'; end if; end if; end process start_p; ----------------------------------------------------------------------------------------------- -- Read input data from file ----------------------------------------------------------------------------------------------- source_model : process(clk) is file in_file : text open read_mode is FIR_INPUT_FILE_c; variable data_in : integer; variable indata : line; begin if rising_edge(clk) then if(reset_testbench = '0') then ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4; ast_sink_valid <= '0' after tclk/4; eof <= '0'; else if not endfile(in_file) and (eof = '0') then eof <= '0'; if((ast_sink_valid = '1' and ast_sink_ready = '1') or (start = '1'and not (ast_sink_valid = '1' and ast_sink_ready = '0'))) then readline(in_file, indata); read(indata, data_in); ast_sink_valid <= '1' after tclk/4; ast_sink_data <= std_logic_vector(to_signed(data_in, DATA_WIDTH_c)) after tclk/4; else ast_sink_valid <= '1' after tclk/4; ast_sink_data <= ast_sink_data after tclk/4; end if; else eof <= '1'; ast_sink_valid <= '0' after tclk/4; ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4; end if; end if; end if; end process source_model; --------------------------------------------------------------------------------------------- -- Write FIR output to file --------------------------------------------------------------------------------------------- sink_model : process(clk) is file ro_file : text open write_mode is FIR_OUTPUT_FILE_c; variable rdata : line; variable data_r : integer; begin if rising_edge(clk) then if(ast_source_valid = '1' and ast_source_ready = '1') then data_r := to_integer(signed(ast_source_data)); write(rdata, data_r); writeline(ro_file, rdata); end if; end if; end process sink_model; ------------------------------------------------------------------------------- -- clock generator ------------------------------------------------------------------------------- clkgen : process begin -- process clkgen if eof = '1' then clk <= '0'; assert FALSE report "NOTE: Stimuli ended" severity note; wait; elsif time_lapse >= time_lapse_max then clk <= '0'; assert FALSE report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error; wait; else clk <= '0'; wait for tclk/2; clk <= '1'; wait for tclk/2; end if; end process clkgen; monitor_toggling_activity : process(clk, reset_testbench, ast_source_data, ast_source_valid) begin if reset_testbench = '0' then time_lapse <= 0 ns; elsif ast_source_data'event or ast_source_valid'event then time_lapse <= 0 ns; elsif rising_edge(clk) then if time_lapse < time_lapse_max then time_lapse <= time_lapse + tclk; end if; end if; end process monitor_toggling_activity; ------------------------------------------------------------------------------- -- reset generator ------------------------------------------------------------------------------- reset_testbench_gen : process begin -- process resetgen reset_testbench <= '1'; wait for tclk/4; reset_testbench <= '0'; wait for tclk*2; reset_testbench <= '1'; wait; end process reset_testbench_gen; reset_design_gen : process begin -- process resetgen reset_design <= '1'; wait for tclk/4; reset_design <= '0'; wait for tclk*2; reset_design <= '1'; wait for tclk*80; reset_design <= '1'; wait for tclk*32*2; reset_design <= '1'; wait; end process reset_design_gen; ------------------------------------------------------------------------------- -- control signals ------------------------------------------------------------------------------- end architecture rtl;
apache-2.0
dec347cee67b0c20b4cbe7d09241bf34
0.535509
4.173621
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2.vhd
1
2,566
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is port ( clk: in std_logic; ce: in std_logic; a: in std_logic_vector(8 - 1 downto 0); b: in std_logic_vector(6 - 1 downto 0); p: out std_logic_vector(14 - 1 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is signal tmp_product : std_logic_vector(14 - 1 downto 0); signal a_i : std_logic_vector(8 - 1 downto 0); signal b_i : std_logic_vector(6 - 1 downto 0); signal p_tmp : std_logic_vector(14 - 1 downto 0); attribute keep : string; attribute keep of a_i : signal is "true"; attribute keep of b_i : signal is "true"; begin a_i <= a; b_i <= b; p <= p_tmp; tmp_product <= std_logic_vector(resize(unsigned(a_i) * unsigned(b_i), 14)); process(clk) begin if (clk'event and clk = '1') then if (ce = '1') then p_tmp <= tmp_product; end if; end if; end process; end architecture; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is port ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; p : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 port map ( clk => clk, ce => ce, a => din0, b => din1, p => dout); end architecture;
lgpl-3.0
842ad6102638b2ba11606bb27e68cff5
0.563913
3.171817
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/driver/led_handle.vhd
1
6,134
--***************************************************************************** -- @Copyright 2008 by guyoubao, All rights reserved. -- Module name : vhdl_code_demo -- Call by : -- Description : this module is the top module of demo. -- IC : EP1C4F400C8 -- Version : A -- Note: : this is a demo -- Author : guyoubao -- Date : 2003.09.07 -- Update : -- 2003.10.15 : xxx(who?) -- add xxxx -- modify xxxxx --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity LED_HANDLE is port ( I_26M_clk : in std_logic; I_reset_n : in std_logic; I_led_dis : in std_logic_vector(3 downto 0); I_adc_dis : in std_logic; I_fifo_full : in std_logic; O_fpga_led0 : out std_logic; O_fpga_led1 : out std_logic; O_fpga_led2 : out std_logic; --CPUд��ָʾ O_fpga_led3 : out std_logic --FPGA����ָʾ ); end LED_HANDLE; architecture ARC_LED_HANDLE of LED_HANDLE is signal S_case_cnt : std_logic_vector(23 downto 0);-- signal S_case : std_logic_vector(2 downto 0); signal S_init : std_logic; signal S_time_tick : std_logic; signal S_time_tick_buf : std_logic; signal S_fpga_led0 : std_logic; signal S_fpga_led1 : std_logic; signal S_fpga_led2 : std_logic; --CPUд��ָʾ signal S_fpga_led3 : std_logic; --FPGA����ָʾ begin O_fpga_led0 <= S_fpga_led0; O_fpga_led1 <= S_fpga_led1; O_fpga_led2 <= S_fpga_led2; O_fpga_led3 <= S_fpga_led3; ------------------------------- --The state transfer one time in 1 second ------------------------------- process(I_26M_clk, I_reset_n) begin if I_reset_n = '0' then S_case <= (others=>'0'); S_case_cnt <= (others=>'0'); S_init <= '0'; S_time_tick <= '0'; elsif rising_edge(I_26M_clk) then --if S_case_cnt >= x"10111110" then --200MHz --if S_case_cnt >= x"019B4E81" then --20MHz S_case_cnt <= S_case_cnt + 1; if (S_case_cnt = 0)then --20MHz S_time_tick <= not S_time_tick; --ʱ�ӽ��ģ�1Sһ�� if S_case >= "100" then S_init <= '1'; S_case <= (others=>'0'); else S_case <= S_case + 1; -- Increment state on one second end if; end if; else null; end if; end process; process(I_26M_clk, I_reset_n) begin if I_reset_n = '0' then S_fpga_led2 <= '1'; S_fpga_led3 <= '1'; elsif rising_edge(I_26M_clk) then if (I_adc_dis = '1') then if (S_time_tick = '1') then S_fpga_led2 <= '0'; else S_fpga_led2 <= '1'; end if; else S_fpga_led2 <= '1'; end if; if (I_fifo_full = '1') then --FIFO is full if (S_time_tick = '1') then S_fpga_led3 <= '0'; else S_fpga_led3 <= '1'; end if; else S_fpga_led3 <= '1'; end if; else null; end if; end process; ------------------------------- --Output the led signal one second ------------------------------- process(I_reset_n,I_26M_clk) begin if I_reset_n = '0' then S_fpga_led0 <= '1'; S_fpga_led1 <= '1'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '1'; else if rising_edge(I_26M_clk) then -- if (S_init = '0') then case S_case is when "001" => S_fpga_led0 <= '0'; S_fpga_led1 <= '1'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '1'; when "010" => S_fpga_led0 <= '1'; S_fpga_led1 <= '0'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '1'; when "011" => S_fpga_led0 <= '1'; S_fpga_led1 <= '1'; -- S_fpga_led2 <= '0'; -- S_fpga_led3 <= '1'; when "100" => S_fpga_led0 <= '0'; S_fpga_led1 <= '0'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '0'; -- when "101" => -- S_fpga_led0 <= '1'; -- S_fpga_led1 <= '1'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '1'; -- when "110" => -- S_fpga_led0 <= '0'; -- S_fpga_led1 <= '0'; -- S_fpga_led2 <= '0'; -- S_fpga_led3 <= '0'; when others => S_fpga_led0 <= '1'; S_fpga_led1 <= '1'; -- S_fpga_led2 <= '1'; -- S_fpga_led3 <= '1'; end case; -- else -- S_time_tick_buf <= S_time_tick; -- if(S_time_tick_buf = not S_time_tick)then -- S_fpga_led3 <= not S_fpga_led3; --FPGA��������ָʾ�� -- end if; else null; end if; end if; end process; end ARC_LED_HANDLE;
apache-2.0
95caf9ad735adef58062491408f9912c
0.352689
3.362174
false
false
false
false
SamuelLBau/Pool-Shot-Tracking-using-FPGA
examples/sparse_mm/solution1/syn/vhdl/sparse_mm_mul_31ns_32s_32_3.vhd
1
2,718
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sparse_mm_mul_31ns_32s_32_3_Mul3S_1 is port ( clk: in std_logic; ce: in std_logic; a: in std_logic_vector(31 - 1 downto 0); b: in std_logic_vector(32 - 1 downto 0); p: out std_logic_vector(32 - 1 downto 0)); end entity; architecture behav of sparse_mm_mul_31ns_32s_32_3_Mul3S_1 is signal tmp_product : std_logic_vector(32 - 1 downto 0); signal a_i : std_logic_vector(31 - 1 downto 0); signal b_i : std_logic_vector(32 - 1 downto 0); signal p_tmp : std_logic_vector(32 - 1 downto 0); signal a_reg0 : std_logic_vector(31 - 1 downto 0); signal b_reg0 : std_logic_vector(32 - 1 downto 0); attribute keep : string; attribute keep of a_i : signal is "true"; attribute keep of b_i : signal is "true"; signal buff0 : std_logic_vector(32 - 1 downto 0); begin a_i <= a; b_i <= b; p <= p_tmp; p_tmp <= buff0; tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' & a_reg0) * signed(b_reg0))), 32)); process(clk) begin if (clk'event and clk = '1') then if (ce = '1') then a_reg0 <= a_i; b_reg0 <= b_i; buff0 <= tmp_product; end if; end if; end process; end architecture; Library IEEE; use IEEE.std_logic_1164.all; entity sparse_mm_mul_31ns_32s_32_3 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of sparse_mm_mul_31ns_32s_32_3 is component sparse_mm_mul_31ns_32s_32_3_Mul3S_1 is port ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; p : OUT STD_LOGIC_VECTOR); end component; begin sparse_mm_mul_31ns_32s_32_3_Mul3S_1_U : component sparse_mm_mul_31ns_32s_32_3_Mul3S_1 port map ( clk => clk, ce => ce, a => din0, b => din1, p => dout); end architecture;
gpl-3.0
1f520f2c50b0c68fbf7f6272ec6a9905
0.549301
3.18267
false
false
false
false
grwlf/vsim
vhdl_ct/ct00664.vhd
1
2,377
-- NEED RESULT: ARCH00664: Ports on blocks and entities of mode 'linkage' may appear as an actual corresponding to an interface object of mode linkage passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00664 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 4.3.3 (20) -- 4.3.3.1 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00664(ARCH00664) -- ENT00664_Test_Bench(ARCH00664_Test_Bench) -- -- REVISION HISTORY: -- -- 26-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES.all ; entity ENT00664 is port ( Pt1 : linkage Integer ) ; end ENT00664 ; -- architecture ARCH00664 of ENT00664 is function To_Integer ( P : Real ) return Integer is begin if P = -1.0 then return -1 ; else return -2 ; end if ; end To_Integer ; function To_Real ( P : Integer ) return Real is begin if P = -1 then return -1.0 ; else return -2.0 ; end if ; end To_Real ; begin L1 : block port ( Pt1 : linkage Real ) ; port map ( To_Integer(Pt1) => To_Real(Pt1) ) ; -- Check block 'linkage' p begin BP1 : process begin wait ; end process BP1 ; end block L1 ; end ARCH00664 ; -- use WORK.STANDARD_TYPES.all; entity ENT00664_Test_Bench is end ENT00664_Test_Bench ; architecture ARCH00664_Test_Bench of ENT00664_Test_Bench is begin L1: block component UUT end component ; signal S1 : Integer := -2 ; for CIS1 : UUT use entity WORK.ENT00664 ( ARCH00664 ) port map ( S1 ) ; -- Check entity 'linkage' port begin CIS1 : UUT ; process begin test_report ( "ARCH00664" , "Ports on blocks and entities "& "of mode 'linkage' may appear as an actual "& "corresponding to an interface object of "& "mode linkage" , S1 = -2 ) ; wait ; end process ; end block L1 ; end ARCH00664_Test_Bench ; --
gpl-3.0
97407f29b22cc4ea3bb3e865120f0acb
0.503155
3.5059
false
true
false
false
jairov4/accel-oil
solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_6ns_6ns_6_2.vhd
3
7,081
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(5 downto 0); b: in std_logic_vector(5 downto 0); s: out std_logic_vector(5 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is port ( faa : IN STD_LOGIC_VECTOR (3-1 downto 0); fab : IN STD_LOGIC_VECTOR (3-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (3-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (3-1 downto 0); fab : IN STD_LOGIC_VECTOR (3-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (3-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(5 downto 0); signal b_reg : std_logic_vector(5 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(2 downto 0); signal b0_cb : std_logic_vector(2 downto 0); signal a1_cb : std_logic_vector(5 downto 3); signal b1_cb : std_logic_vector(5 downto 3); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; -- wires for each full adder sum signal fas : std_logic_vector(5 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0); signal s0_ca_rego0 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(5 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(2 downto 0); b0_cb <= b_reg(2 downto 0); a1_cb <= a_reg(5 downto 3); b1_cb <= b_reg(5 downto 3); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(2 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(5 downto 3), facout => faccout1_co1); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(2 downto 0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(2 downto 0) <= s0_ca_rego0(0); s_tmp(5 downto 3) <= fas(5 downto 3); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is generic(N : natural :=3); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is generic(N : natural :=3); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_4 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
edbcd0b5e688987b3d27a0c87b5ddfed
0.615873
3.001696
false
false
false
false
TWW12/lzw
final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_sim_netlist.vhdl
1
60,755
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:15:18 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_sim_netlist.vhdl -- Design : bram_2048_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_2048_1_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_2048_1_blk_mem_gen_prim_wrapper_init is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000080000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"403E3C3A38363432302E2C2A28262422201E1C1A18161412100E0C0A08060402", INIT_01 => X"807E7C7A78767472706E6C6A68666462605E5C5A58565452504E4C4A48464442", INIT_02 => X"C0BEBCBAB8B6B4B2B0AEACAAA8A6A4A2A09E9C9A98969492908E8C8A88868482", INIT_03 => X"00FEFCFAF8F6F4F2F0EEECEAE8E6E4E2E0DEDCDAD8D6D4D2D0CECCCAC8C6C4C2", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 0) => B"00000000000000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1) => '0', DIPADIP(0) => dina(8), DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), DOADO(7 downto 0) => douta(7 downto 0), DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), DOPADOP(0) => douta(8), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ena, ENBWREN => '0', REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_2048_1_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 10 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 10 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_2048_1_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_2048_1_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \bram_2048_1_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 4) => addra(10 downto 0), ADDRARDADDR(3 downto 0) => B"1111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 13) => B"0000000000000000000", DIADI(12 downto 8) => dina(10 downto 6), DIADI(7 downto 6) => B"00", DIADI(5 downto 0) => dina(5 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\, DOADO(12 downto 8) => douta(10 downto 6), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\, DOADO(5 downto 0) => douta(5 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_2048_1_blk_mem_gen_prim_width; architecture STRUCTURE of bram_2048_1_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_2048_1_blk_mem_gen_prim_wrapper_init port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_2048_1_blk_mem_gen_prim_width__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 10 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 10 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_2048_1_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \bram_2048_1_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \bram_2048_1_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\bram_2048_1_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(10 downto 0) => dina(10 downto 0), douta(10 downto 0) => douta(10 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_2048_1_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_2048_1_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bram_2048_1_blk_mem_gen_prim_width port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\bram_2048_1_blk_mem_gen_prim_width__parameterized0\ port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(10 downto 0) => dina(19 downto 9), douta(10 downto 0) => douta(19 downto 9), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_2048_1_blk_mem_gen_top; architecture STRUCTURE of bram_2048_1_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_2048_1_blk_mem_gen_generic_cstr port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_2048_1_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_2048_1_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_2048_1_blk_mem_gen_top port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 11; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 11; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.9373 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "bram_2048_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "bram_2048_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_2048_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_2048_1_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_2048_1_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_2048_1_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_2048_1_blk_mem_gen_v8_3_5_synth port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_2048_1 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_2048_1 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_2048_1 : entity is "bram_2048_1,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_2048_1 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_2048_1 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_2048_1; architecture STRUCTURE of bram_2048_1 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 11; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 11; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.9373 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_2048_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_2048_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 2048; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 2048; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 2048; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 2048; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_2048_1_blk_mem_gen_v8_3_5 port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => B"00000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
a516c80e9b91fe372a8ca8fee74d7b9c
0.706938
3.695335
false
false
false
false
grwlf/vsim
vhdl_ct/ct00263.vhd
1
2,734
-- NEED RESULT: Assertion statement in architecture body -- NEED RESULT: ARCH00263: Block statements, process_statements, signal assignment statements, component instantiation statements, concurrent procedure call statements and generate statements in architecture statement part passed -- NEED RESULT: *** Check simulation log for the following message: -- NEED RESULT: Assertion statement in architecture body ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00263 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.2.2 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00263) -- ENT00263_Test_Bench(ARCH00263_Test_Bench) -- -- REVISION HISTORY: -- -- 16-JUL-1987 - initial revision -- -- NOTES: -- -- partially self checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00263 of E00000 is signal s1, s2, s3, s4, s5, s6 : integer := 0 ; constant c1 : boolean := false ; procedure p1 ( signal s : inout integer ) is begin s <= 5 ; end p1 ; begin Bl1 : block begin s1 <= 5 ; end block Bl1 ; P01 : process begin s2 <= 5 ; wait ; end process P01 ; s3 <= 5 ; with c1 select s4 <= 5 when false, 0 when true ; G1 : if not c1 generate s5 <= 5 ; end generate G1 ; p1 ( s6 ) ; assert false report "Assertion statement in architecture body" severity note ; process ( s1, s2, s3, s4, s5, s6 ) begin if s1 = 5 and s2 = 5 and s3 = 5 and s4 = 5 and s5 = 5 and s6 = 5 then test_report ( "ARCH00263" , "Block statements, process_statements, signal" & " assignment statements, component instantiation" & " statements, concurrent procedure call statements" & " and generate statements in architecture" & " statement part" , true ) ; print ( "*** Check simulation log for the following message:" ) ; print ( "Assertion statement in architecture body" ) ; end if ; end process ; end ARCH00263 ; entity ENT00263_Test_Bench is end ENT00263_Test_Bench ; architecture ARCH00263_Test_Bench of ENT00263_Test_Bench is component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00263 ) ; begin CIS1 : UUT ; -- component instantiation in architecture end ARCH00263_Test_Bench ;
gpl-3.0
48e2af31e8558ad14e78757e04df68bb
0.553402
3.834502
false
true
false
false
grwlf/vsim
vhdl_ct/ct00145.vhd
1
108,663
-- NEED RESULT: ARCH00145.P1: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P2: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P3: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P4: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P5: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P6: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P7: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P8: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P9: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P10: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P11: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P12: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P13: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P14: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P15: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P16: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145.P17: Multi inertial transactions occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed -- NEED RESULT: P17: Inertial transactions entirely completed failed -- NEED RESULT: P16: Inertial transactions entirely completed failed -- NEED RESULT: P15: Inertial transactions entirely completed failed -- NEED RESULT: P14: Inertial transactions entirely completed failed -- NEED RESULT: P13: Inertial transactions entirely completed failed -- NEED RESULT: P12: Inertial transactions entirely completed failed -- NEED RESULT: P11: Inertial transactions entirely completed failed -- NEED RESULT: P10: Inertial transactions entirely completed failed -- NEED RESULT: P9: Inertial transactions entirely completed failed -- NEED RESULT: P8: Inertial transactions entirely completed failed -- NEED RESULT: P7: Inertial transactions entirely completed failed -- NEED RESULT: P6: Inertial transactions entirely completed failed -- NEED RESULT: P5: Inertial transactions entirely completed failed -- NEED RESULT: P4: Inertial transactions entirely completed failed -- NEED RESULT: P3: Inertial transactions entirely completed failed -- NEED RESULT: P2: Inertial transactions entirely completed failed -- NEED RESULT: P1: Inertial transactions entirely completed failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00145 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- ENT00145(ARCH00145) -- ENT00145_Test_Bench(ARCH00145_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00145 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_bit_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_int1_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_phys1_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_real1_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_st_boolean_vector : inout st_boolean_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_boolean_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_boolean_vector (lowb+1 to lowb+3) <= c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P1" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_boolean_vector (lowb+1 to lowb+3) <= c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_boolean_vector (lowb+1 to lowb+3) <= c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_boolean_vector (lowb+1 to lowb+3) <= transport c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_boolean_vector (lowb+1 to lowb+3) <= c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_boolean_vector (lowb+1 to lowb+3) <= c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_boolean_vector (lowb+1 to lowb+3) = c_st_boolean_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_boolean_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_st_bit_vector : inout st_bit_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_bit_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_bit_vector (lowb+1 to lowb+3) <= c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P2" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_bit_vector (lowb+1 to lowb+3) <= c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_bit_vector (lowb+1 to lowb+3) <= c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_bit_vector (lowb+1 to lowb+3) <= transport c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_bit_vector (lowb+1 to lowb+3) <= c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_bit_vector (lowb+1 to lowb+3) <= c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_bit_vector (lowb+1 to lowb+3) = c_st_bit_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_bit_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_st_severity_level_vector : inout st_severity_level_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_severity_level_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_severity_level_vector (lowb+1 to lowb+3) <= c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P3" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_severity_level_vector (lowb+1 to lowb+3) <= c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_severity_level_vector (lowb+1 to lowb+3) <= c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_severity_level_vector (lowb+1 to lowb+3) <= transport c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_severity_level_vector (lowb+1 to lowb+3) <= c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_severity_level_vector (lowb+1 to lowb+3) <= c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_severity_level_vector (lowb+1 to lowb+3) = c_st_severity_level_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_severity_level_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_st_string : inout st_string ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_string : out chk_sig_type ) is begin case counter is when 0 => s_st_string (lowb+1 to lowb+3) <= c_st_string_2 (lowb+1 to lowb+3) after 10 ns, c_st_string_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P4" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_string (lowb+1 to lowb+3) <= c_st_string_2 (lowb+1 to lowb+3) after 10 ns , c_st_string_1 (lowb+1 to lowb+3) after 20 ns , c_st_string_2 (lowb+1 to lowb+3) after 30 ns , c_st_string_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_string (lowb+1 to lowb+3) <= c_st_string_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_string (lowb+1 to lowb+3) <= transport c_st_string_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_string (lowb+1 to lowb+3) <= c_st_string_2 (lowb+1 to lowb+3) after 10 ns , c_st_string_1 (lowb+1 to lowb+3) after 20 ns , c_st_string_2 (lowb+1 to lowb+3) after 30 ns , c_st_string_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_string (lowb+1 to lowb+3) <= c_st_string_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_string (lowb+1 to lowb+3) = c_st_string_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_string <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_st_enum1_vector : inout st_enum1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_enum1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_enum1_vector (lowb+1 to lowb+3) <= c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P5" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_enum1_vector (lowb+1 to lowb+3) <= c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1_vector (lowb+1 to lowb+3) <= c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_enum1_vector (lowb+1 to lowb+3) <= transport c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_enum1_vector (lowb+1 to lowb+3) <= c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_enum1_vector (lowb+1 to lowb+3) <= c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1_vector (lowb+1 to lowb+3) = c_st_enum1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_st_integer_vector : inout st_integer_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_integer_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_integer_vector (lowb+1 to lowb+3) <= c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P6" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_integer_vector (lowb+1 to lowb+3) <= c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_integer_vector (lowb+1 to lowb+3) <= c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_integer_vector (lowb+1 to lowb+3) <= transport c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_integer_vector (lowb+1 to lowb+3) <= c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_integer_vector (lowb+1 to lowb+3) <= c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_integer_vector (lowb+1 to lowb+3) = c_st_integer_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_integer_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- procedure Proc7 ( signal s_st_int1_vector : inout st_int1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_int1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_int1_vector (lowb+1 to lowb+3) <= c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P7" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_int1_vector (lowb+1 to lowb+3) <= c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1_vector (lowb+1 to lowb+3) <= c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_int1_vector (lowb+1 to lowb+3) <= transport c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_int1_vector (lowb+1 to lowb+3) <= c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_int1_vector (lowb+1 to lowb+3) <= c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_int1_vector (lowb+1 to lowb+3) = c_st_int1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc7 ; -- procedure Proc8 ( signal s_st_time_vector : inout st_time_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_time_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_time_vector (lowb+1 to lowb+3) <= c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P8" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_time_vector (lowb+1 to lowb+3) <= c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_time_vector (lowb+1 to lowb+3) <= c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_time_vector (lowb+1 to lowb+3) <= transport c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_time_vector (lowb+1 to lowb+3) <= c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_time_vector (lowb+1 to lowb+3) <= c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_time_vector (lowb+1 to lowb+3) = c_st_time_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_time_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc8 ; -- procedure Proc9 ( signal s_st_phys1_vector : inout st_phys1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_phys1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_phys1_vector (lowb+1 to lowb+3) <= c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P9" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_phys1_vector (lowb+1 to lowb+3) <= c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1_vector (lowb+1 to lowb+3) <= c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_phys1_vector (lowb+1 to lowb+3) <= transport c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_phys1_vector (lowb+1 to lowb+3) <= c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_phys1_vector (lowb+1 to lowb+3) <= c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_phys1_vector (lowb+1 to lowb+3) = c_st_phys1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc9 ; -- procedure Proc10 ( signal s_st_real_vector : inout st_real_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_real_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_real_vector (lowb+1 to lowb+3) <= c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P10" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real_vector (lowb+1 to lowb+3) <= c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_real_vector (lowb+1 to lowb+3) <= c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real_vector (lowb+1 to lowb+3) <= transport c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_real_vector (lowb+1 to lowb+3) <= c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_real_vector (lowb+1 to lowb+3) <= c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real_vector (lowb+1 to lowb+3) = c_st_real_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc10 ; -- procedure Proc11 ( signal s_st_real1_vector : inout st_real1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_real1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_real1_vector (lowb+1 to lowb+3) <= c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P11" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real1_vector (lowb+1 to lowb+3) <= c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1_vector (lowb+1 to lowb+3) <= c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_real1_vector (lowb+1 to lowb+3) <= transport c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_real1_vector (lowb+1 to lowb+3) <= c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_real1_vector (lowb+1 to lowb+3) <= c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real1_vector (lowb+1 to lowb+3) = c_st_real1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc11 ; -- procedure Proc12 ( signal s_st_rec1_vector : inout st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec1_vector (lowb+1 to lowb+3) <= c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P12" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec1_vector (lowb+1 to lowb+3) <= c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1_vector (lowb+1 to lowb+3) <= c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec1_vector (lowb+1 to lowb+3) <= transport c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_rec1_vector (lowb+1 to lowb+3) <= c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_rec1_vector (lowb+1 to lowb+3) <= c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector (lowb+1 to lowb+3) = c_st_rec1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc12 ; -- procedure Proc13 ( signal s_st_rec2_vector : inout st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec2_vector (lowb+1 to lowb+3) <= c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P13" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec2_vector (lowb+1 to lowb+3) <= c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2_vector (lowb+1 to lowb+3) <= c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec2_vector (lowb+1 to lowb+3) <= transport c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_rec2_vector (lowb+1 to lowb+3) <= c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_rec2_vector (lowb+1 to lowb+3) <= c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2_vector (lowb+1 to lowb+3) = c_st_rec2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc13 ; -- procedure Proc14 ( signal s_st_rec3_vector : inout st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_rec3_vector (lowb+1 to lowb+3) <= c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P14" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec3_vector (lowb+1 to lowb+3) <= c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3_vector (lowb+1 to lowb+3) <= c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_rec3_vector (lowb+1 to lowb+3) <= transport c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_rec3_vector (lowb+1 to lowb+3) <= c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_rec3_vector (lowb+1 to lowb+3) <= c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3_vector (lowb+1 to lowb+3) = c_st_rec3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc14 ; -- procedure Proc15 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector (lowb+1 to lowb+3) <= c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P15" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr1_vector (lowb+1 to lowb+3) <= c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector (lowb+1 to lowb+3) <= c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr1_vector (lowb+1 to lowb+3) <= transport c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_arr1_vector (lowb+1 to lowb+3) <= c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_arr1_vector (lowb+1 to lowb+3) <= c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1_vector (lowb+1 to lowb+3) = c_st_arr1_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc15 ; -- procedure Proc16 ( signal s_st_arr2_vector : inout st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr2_vector (lowb+1 to lowb+3) <= c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P16" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr2_vector (lowb+1 to lowb+3) <= c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector (lowb+1 to lowb+3) <= c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr2_vector (lowb+1 to lowb+3) <= transport c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_arr2_vector (lowb+1 to lowb+3) <= c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_arr2_vector (lowb+1 to lowb+3) <= c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector (lowb+1 to lowb+3) = c_st_arr2_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc16 ; -- procedure Proc17 ( signal s_st_arr3_vector : inout st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr3_vector (lowb+1 to lowb+3) <= c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns, c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ; -- when 1 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145.P17" , "Multi inertial transactions occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr3_vector (lowb+1 to lowb+3) <= c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 3 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector (lowb+1 to lowb+3) <= c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ; -- when 4 => correct := correct and s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; s_st_arr3_vector (lowb+1 to lowb+3) <= transport c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ; -- when 5 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Old transactions were removed on signal " & "asg with slice name on LHS", correct ) ; s_st_arr3_vector (lowb+1 to lowb+3) <= c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns , c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns , c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 6 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_2 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "One inertial transaction occurred on signal " & "asg with slice name on LHS", correct ) ; -- Last transaction above is marked by following s_st_arr3_vector (lowb+1 to lowb+3) <= c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ; -- when 7 => correct := s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3_vector (lowb+1 to lowb+3) = c_st_arr3_vector_1 (lowb+1 to lowb+3) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", correct ) ; -- when others => test_report ( "ARCH00145" , "Inertial semantics check on a signal " & "asg with slice name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc17 ; -- -- end ENT00145 ; -- architecture ARCH00145 of ENT00145 is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_st_boolean_vector, counter, correct, savtime, chk_st_boolean_vector ) ; wait until (not s_st_boolean_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_st_boolean_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- P2 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_st_bit_vector, counter, correct, savtime, chk_st_bit_vector ) ; wait until (not s_st_bit_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_st_bit_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_st_bit_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- P3 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_st_severity_level_vector, counter, correct, savtime, chk_st_severity_level_vector ) ; wait until (not s_st_severity_level_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_st_severity_level_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- P4 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_st_string, counter, correct, savtime, chk_st_string ) ; wait until (not s_st_string'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P4 ; -- PGEN_CHKP_4 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions entirely completed", chk_st_string = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- P5 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_st_enum1_vector, counter, correct, savtime, chk_st_enum1_vector ) ; wait until (not s_st_enum1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions entirely completed", chk_st_enum1_vector = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- P6 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_st_integer_vector, counter, correct, savtime, chk_st_integer_vector ) ; wait until (not s_st_integer_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P6 ; -- PGEN_CHKP_6 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions entirely completed", chk_st_integer_vector = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- P7 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc7 ( s_st_int1_vector, counter, correct, savtime, chk_st_int1_vector ) ; wait until (not s_st_int1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P7 ; -- PGEN_CHKP_7 : process ( chk_st_int1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions entirely completed", chk_st_int1_vector = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- P8 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc8 ( s_st_time_vector, counter, correct, savtime, chk_st_time_vector ) ; wait until (not s_st_time_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P8 ; -- PGEN_CHKP_8 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions entirely completed", chk_st_time_vector = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- P9 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc9 ( s_st_phys1_vector, counter, correct, savtime, chk_st_phys1_vector ) ; wait until (not s_st_phys1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions entirely completed", chk_st_phys1_vector = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- P10 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc10 ( s_st_real_vector, counter, correct, savtime, chk_st_real_vector ) ; wait until (not s_st_real_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P10 ; -- PGEN_CHKP_10 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Inertial transactions entirely completed", chk_st_real_vector = 8 ) ; end if ; end process PGEN_CHKP_10 ; -- P11 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc11 ( s_st_real1_vector, counter, correct, savtime, chk_st_real1_vector ) ; wait until (not s_st_real1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P11 ; -- PGEN_CHKP_11 : process ( chk_st_real1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Inertial transactions entirely completed", chk_st_real1_vector = 8 ) ; end if ; end process PGEN_CHKP_11 ; -- P12 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc12 ( s_st_rec1_vector, counter, correct, savtime, chk_st_rec1_vector ) ; wait until (not s_st_rec1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Inertial transactions entirely completed", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_12 ; -- P13 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc13 ( s_st_rec2_vector, counter, correct, savtime, chk_st_rec2_vector ) ; wait until (not s_st_rec2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Inertial transactions entirely completed", chk_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_13 ; -- P14 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc14 ( s_st_rec3_vector, counter, correct, savtime, chk_st_rec3_vector ) ; wait until (not s_st_rec3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Inertial transactions entirely completed", chk_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_14 ; -- P15 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc15 ( s_st_arr1_vector, counter, correct, savtime, chk_st_arr1_vector ) ; wait until (not s_st_arr1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Inertial transactions entirely completed", chk_st_arr1_vector = 8 ) ; end if ; end process PGEN_CHKP_15 ; -- P16 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc16 ( s_st_arr2_vector, counter, correct, savtime, chk_st_arr2_vector ) ; wait until (not s_st_arr2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Inertial transactions entirely completed", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_16 ; -- P17 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc17 ( s_st_arr3_vector, counter, correct, savtime, chk_st_arr3_vector ) ; wait until (not s_st_arr3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Inertial transactions entirely completed", chk_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_17 ; -- -- end ARCH00145 ; -- entity ENT00145_Test_Bench is end ENT00145_Test_Bench ; -- architecture ARCH00145_Test_Bench of ENT00145_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00145 ( ARCH00145 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00145_Test_Bench ;
gpl-3.0
9a6a7f1e6bfbb56f7eaa09f0ed2b4e80
0.519993
3.605634
false
false
false
false
MrDoomBringer/DSD-Labs
Lab 6/display_tb.vhd
1
3,571
--***************************************************************************** --*************************** VHDL Source Code ****************************** --********* Copyright 2011, Rochester Institute of Technology *************** --***************************************************************************** -- -- DESIGNER NAME: Jeanne Christman -- -- LAB NAME: ALU with 7-segment Display -- -- FILE NAME: display_tb.vhd -- ------------------------------------------------------------------------------- -- -- DESCRIPTION -- -- This test bench will provide input to test an eight bit binary to -- seven-segment display driver. The inputs are an 8-bit binary number -- and a selector signal that selects between hexidecimal and signed decimal -- display. There are three outputs which go to the 7-segment displays -- ------------------------------------------------------------------------------- -- -- REVISION HISTORY -- -- _______________________________________________________________________ -- | DATE | USER | Ver | Description | -- |==========+======+=====+================================================ -- | | | | -- | 10/02/13 | JWC | 1.0 | Created -- | | | | -- --***************************************************************************** --***************************************************************************** LIBRARY IEEE; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY display_tb IS END ENTITY display_tb; ARCHITECTURE test OF display_tb IS --the component name MUST match the entity name of the VHDL module being tested COMPONENT sevenseg_out PORT ( R : in STD_LOGIC_VECTOR(7 downto 0); --8-bit input S : in STD_LOGIC; --Select decimal or hexidecimal HEX0,HEX1,HEX2 : out STD_LOGIC_VECTOR(6 downto 0)); --ssd outputs END COMPONENT; -- testbench signals. These do not need to be modified SIGNAL r_tb : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL s_tb : STD_LOGIC; -- SIGNAL HEX0_tb : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL HEX1_tb : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL HEX2_tb : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN --this must match component above UUT : sevenseg_out PORT MAP ( R => r_tb, S => s_tb, HEX0 => HEX0_tb, HEX1 => HEX1_tb, HEX2 => HEX2_tb ); --------------------------------------------------------------------------- -- NAME: Stimulus -- -- DESCRIPTION: -- This process will apply the stimulus to the UUT --------------------------------------------------------------------------- stimulus : PROCESS BEGIN -- create 2 loops to run through all the combinations of -- r numbers for each type of display FOR i IN STD_LOGIC RANGE '0' TO '1' LOOP s_tb <= i; FOR j IN 0 TO 255 LOOP r_tb <= std_logic_vector(to_unsigned(j,8)); WAIT FOR 10 ns; END LOOP; END LOOP; ----------------------------------------------------------------------- -- This last WAIT statement needs to be here to prevent the PROCESS -- sequence from restarting. ----------------------------------------------------------------------- WAIT; END PROCESS stimulus; END ARCHITECTURE test;
mit
df28df1ca2dee463de4cf92fe9c0ebff
0.395968
4.939142
false
true
false
false
MilosSubotic/huffman_coding
RTL/src/sim/sort_syms_by_freq_tb.vhd
1
6,005
------------------------------------------------------------------------------ -- @license MIT ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use std.textio.all; use work.global.all; use work.sort_syms_by_freq; entity sort_syms_by_freq_tb is end entity sort_syms_by_freq_tb; architecture arch_sort_syms_by_freq_tb of sort_syms_by_freq_tb is -- Possible values: note, warning, error, failure; constant assert_severity : severity_level := error; file stdout: text open write_mode is "STD_OUTPUT"; procedure println(s: string) is variable l: line; begin write(l, s); writeline(stdout, l); end procedure println; --Inputs signal i_clk : std_logic := '0'; signal in_rst : std_logic := '0'; signal i_stage : t_stage := (others => '0'); signal i_pipe_en : std_logic := '0'; signal i_hist : t_freq_array(0 to 15) := (others => (others => '0')); --Outputs signal o_sorted_by_freq : t_sym_and_freq_array(0 to 15); -- Clock period definitions constant i_clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity sort_syms_by_freq port map ( i_clk => i_clk, in_rst => in_rst, i_stage => i_stage, i_pipe_en => i_pipe_en, i_hist => i_hist, o_sorted_by_freq => o_sorted_by_freq ); -- Clock process definitions i_clk_proc: process begin i_clk <= '0'; wait for i_clk_period/2; i_clk <= '1'; wait for i_clk_period/2; end process; stim_proc: process begin i_stage <= conv_std_logic_vector(16, t_stage'length); wait for i_clk_period*2; in_rst <= '1'; wait for i_clk_period; for i in 0 to 15 loop i_hist(i) <= conv_std_logic_vector(20-i, t_freq'length); end loop; i_hist(4) <= conv_std_logic_vector(0, 5); i_pipe_en <= '1'; wait for i_clk_period; for s in 0 to 15 loop i_stage <= conv_std_logic_vector(s, t_stage'length); wait for i_clk_period; end loop; i_pipe_en <= '0'; assert o_sorted_by_freq(0).sym = 15 report "o_sorted_by_freq(0).sym wrong!" severity assert_severity; assert o_sorted_by_freq(1).sym = 14 report "o_sorted_by_freq(1).sym wrong!" severity assert_severity; assert o_sorted_by_freq(2).sym = 13 report "o_sorted_by_freq(2).sym wrong!" severity assert_severity; assert o_sorted_by_freq(3).sym = 12 report "o_sorted_by_freq(3).sym wrong!" severity assert_severity; assert o_sorted_by_freq(4).sym = 11 report "o_sorted_by_freq(4).sym wrong!" severity assert_severity; assert o_sorted_by_freq(5).sym = 10 report "o_sorted_by_freq(5).sym wrong!" severity assert_severity; assert o_sorted_by_freq(6).sym = 9 report "o_sorted_by_freq(6).sym wrong!" severity assert_severity; assert o_sorted_by_freq(7).sym = 8 report "o_sorted_by_freq(7).sym wrong!" severity assert_severity; assert o_sorted_by_freq(8).sym = 7 report "o_sorted_by_freq(8).sym wrong!" severity assert_severity; assert o_sorted_by_freq(9).sym = 6 report "o_sorted_by_freq(9).sym wrong!" severity assert_severity; assert o_sorted_by_freq(10).sym = 5 report "o_sorted_by_freq(10).sym wrong!" severity assert_severity; assert o_sorted_by_freq(11).sym = 3 report "o_sorted_by_freq(11).sym wrong!" severity assert_severity; assert o_sorted_by_freq(12).sym = 2 report "o_sorted_by_freq(12).sym wrong!" severity assert_severity; assert o_sorted_by_freq(13).sym = 1 report "o_sorted_by_freq(13).sym wrong!" severity assert_severity; assert o_sorted_by_freq(14).sym = 0 report "o_sorted_by_freq(14).sym wrong!" severity assert_severity; assert o_sorted_by_freq(15).sym = 4 report "o_sorted_by_freq(15).sym wrong!" severity assert_severity; assert o_sorted_by_freq(0).freq = 5 report "o_sorted_by_freq(0).freq wrong!" severity assert_severity; assert o_sorted_by_freq(1).freq = 6 report "o_sorted_by_freq(1).freq wrong!" severity assert_severity; assert o_sorted_by_freq(2).freq = 7 report "o_sorted_by_freq(2).freq wrong!" severity assert_severity; assert o_sorted_by_freq(3).freq = 8 report "o_sorted_by_freq(3).freq wrong!" severity assert_severity; assert o_sorted_by_freq(4).freq = 9 report "o_sorted_by_freq(4).freq wrong!" severity assert_severity; assert o_sorted_by_freq(5).freq = 10 report "o_sorted_by_freq(5).freq wrong!" severity assert_severity; assert o_sorted_by_freq(6).freq = 11 report "o_sorted_by_freq(6).freq wrong!" severity assert_severity; assert o_sorted_by_freq(7).freq = 12 report "o_sorted_by_freq(7).freq wrong!" severity assert_severity; assert o_sorted_by_freq(8).freq = 13 report "o_sorted_by_freq(8).freq wrong!" severity assert_severity; assert o_sorted_by_freq(9).freq = 14 report "o_sorted_by_freq(9).freq wrong!" severity assert_severity; assert o_sorted_by_freq(10).freq = 15 report "o_sorted_by_freq(10).freq wrong!" severity assert_severity; assert o_sorted_by_freq(11).freq = 17 report "o_sorted_by_freq(11).freq wrong!" severity assert_severity; assert o_sorted_by_freq(12).freq = 18 report "o_sorted_by_freq(12).freq wrong!" severity assert_severity; assert o_sorted_by_freq(13).freq = 19 report "o_sorted_by_freq(13).freq wrong!" severity assert_severity; assert o_sorted_by_freq(14).freq = 20 report "o_sorted_by_freq(14).freq wrong!" severity assert_severity; assert o_sorted_by_freq(15).freq = 31 report "o_sorted_by_freq(15).freq wrong!" severity assert_severity; println("--------------------------------------"); println("Testbench done!"); println("--------------------------------------"); wait; end process; end architecture arch_sort_syms_by_freq_tb;
mit
3aaef8187a74e7b42b3704f751e2dc6a
0.621649
2.812646
false
false
false
false
grwlf/vsim
vhdl/IEEE/synopsys/std_logic_signed.vhdl
13
12,622
-------------------------------------------------------------------------- -- -- -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. -- -- All rights reserved. -- -- -- -- This source file may be used and distributed without restriction -- -- provided that this copyright statement is not removed from the file -- -- and that any derivative work contains this copyright notice. -- -- -- -- Package name: STD_LOGIC_SIGNED -- -- -- -- -- -- Date: 09/11/91 KN -- -- 10/08/92 AMT change std_ulogic to signed std_logic -- -- 10/28/92 AMT added signed functions, -, ABS -- -- -- -- Purpose: -- -- A set of signed arithemtic, conversion, -- -- and comparision functions for STD_LOGIC_VECTOR. -- -- -- -- Note: Comparision of same length std_logic_vector is defined -- -- in the LRM. The interpretation is for unsigned vectors -- -- This package will "overload" that definition. -- -- -- -------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package STD_LOGIC_SIGNED is function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN; function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN; function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN; function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER; -- remove this since it is already in std_logic_arith -- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR; end STD_LOGIC_SIGNED; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package body STD_LOGIC_SIGNED is function maximum(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR (length-1 downto 0); begin result := SIGNED(L) + SIGNED(R); -- pragma label plus return std_logic_vector(result); end; function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus variable result : STD_LOGIC_VECTOR (L'range); begin result := SIGNED(L) + R; -- pragma label plus return std_logic_vector(result); end; function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus variable result : STD_LOGIC_VECTOR (R'range); begin result := L + SIGNED(R); -- pragma label plus return std_logic_vector(result); end; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus variable result : STD_LOGIC_VECTOR (L'range); begin result := SIGNED(L) + R; -- pragma label plus return std_logic_vector(result); end; function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus variable result : STD_LOGIC_VECTOR (R'range); begin result := L + SIGNED(R); -- pragma label plus return std_logic_vector(result); end; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR (length-1 downto 0); begin result := SIGNED(L) - SIGNED(R); -- pragma label minus return std_logic_vector(result); end; function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus variable result : STD_LOGIC_VECTOR (L'range); begin result := SIGNED(L) - R; -- pragma label minus return std_logic_vector(result); end; function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus variable result : STD_LOGIC_VECTOR (R'range); begin result := L - SIGNED(R); -- pragma label minus return std_logic_vector(result); end; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus variable result : STD_LOGIC_VECTOR (L'range); begin result := SIGNED(L) - R; -- pragma label minus return std_logic_vector(result); end; function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus variable result : STD_LOGIC_VECTOR (R'range); begin result := L - SIGNED(R); -- pragma label minus return std_logic_vector(result); end; function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to plus variable result : STD_LOGIC_VECTOR (L'range); begin result := + SIGNED(L); -- pragma label plus return std_logic_vector(result); end; function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to minus variable result : STD_LOGIC_VECTOR (L'range); begin result := - SIGNED(L); -- pragma label minus return std_logic_vector(result); end; function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (L'range); begin result := ABS( SIGNED(L)); return std_logic_vector(result); end; function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is -- pragma label_applies_to mult constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin result := SIGNED(L) * SIGNED(R); -- pragma label mult return std_logic_vector(result); end; function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to lt constant length: INTEGER := maximum(L'length, R'length); begin return SIGNED(L) < SIGNED(R); -- pragma label lt end; function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is -- pragma label_applies_to lt begin return SIGNED(L) < R; -- pragma label lt end; function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to lt begin return L < SIGNED(R); -- pragma label lt end; function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to leq begin return SIGNED(L) <= SIGNED(R); -- pragma label leq end; function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is -- pragma label_applies_to leq begin return SIGNED(L) <= R; -- pragma label leq end; function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to leq begin return L <= SIGNED(R); -- pragma label leq end; function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to gt begin return SIGNED(L) > SIGNED(R); -- pragma label gt end; function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is -- pragma label_applies_to gt begin return SIGNED(L) > R; -- pragma label gt end; function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to gt begin return L > SIGNED(R); -- pragma label gt end; function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to geq begin return SIGNED(L) >= SIGNED(R); -- pragma label geq end; function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is -- pragma label_applies_to geq begin return SIGNED(L) >= R; -- pragma label geq end; function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is -- pragma label_applies_to geq begin return L >= SIGNED(R); -- pragma label geq end; function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is begin return SIGNED(L) = SIGNED(R); end; function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is begin return SIGNED(L) = R; end; function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is begin return L = SIGNED(R); end; function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is begin return SIGNED(L) /= SIGNED(R); end; function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is begin return SIGNED(L) /= R; end; function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is begin return L /= SIGNED(R); end; function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT))); end; function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT))); end; -- This function converts std_logic_vector to a signed integer value -- using a conversion function in std_logic_arith function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is variable result : SIGNED(ARG'range); begin result := SIGNED(ARG); return CONV_INTEGER(result); end; end STD_LOGIC_SIGNED;
gpl-3.0
7bc0d7fd5ee8938e9a82858d54f599c1
0.592616
3.841144
false
false
false
false
jairov4/accel-oil
solution_kintex7/impl/vhdl/nfa_accept_sample.vhd
1
68,987
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_sample is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of nfa_accept_sample is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (6 downto 0) := "0001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (6 downto 0) := "0001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (6 downto 0) := "0001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (6 downto 0) := "0001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (6 downto 0) := "0001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (6 downto 0) := "0001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (6 downto 0) := "0010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (6 downto 0) := "0010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (6 downto 0) := "0010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (6 downto 0) := "0010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (6 downto 0) := "0010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (6 downto 0) := "0010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (6 downto 0) := "0011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (6 downto 0) := "0011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (6 downto 0) := "0011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (6 downto 0) := "0011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (6 downto 0) := "0011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (6 downto 0) := "0011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (6 downto 0) := "0011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (6 downto 0) := "0011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (6 downto 0) := "0100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (6 downto 0) := "0100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (6 downto 0) := "0100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (6 downto 0) := "0100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (6 downto 0) := "0100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (6 downto 0) := "0100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (6 downto 0) := "0100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (6 downto 0) := "0100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (6 downto 0) := "0101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (6 downto 0) := "0101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (6 downto 0) := "0101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (6 downto 0) := "0101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (6 downto 0) := "0101100"; constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (6 downto 0) := "0101101"; constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (6 downto 0) := "0101110"; constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (6 downto 0) := "0101111"; constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (6 downto 0) := "0110000"; constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (6 downto 0) := "0110001"; constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (6 downto 0) := "0110010"; constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (6 downto 0) := "0110011"; constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (6 downto 0) := "0110100"; constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (6 downto 0) := "0110101"; constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (6 downto 0) := "0110110"; constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (6 downto 0) := "0110111"; constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (6 downto 0) := "0111000"; constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (6 downto 0) := "0111001"; constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (6 downto 0) := "0111010"; constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (6 downto 0) := "0111011"; constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (6 downto 0) := "0111100"; constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (6 downto 0) := "0111101"; constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (6 downto 0) := "0111110"; constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (6 downto 0) := "0111111"; constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (6 downto 0) := "1000000"; constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (6 downto 0) := "1000001"; constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (6 downto 0) := "1000010"; constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (6 downto 0) := "1000011"; constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (6 downto 0) := "1000100"; constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (6 downto 0) := "1000101"; constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (6 downto 0) := "1000110"; constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (6 downto 0) := "1000111"; constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (6 downto 0) := "1001000"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; signal reg_378 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_reg_585 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_reg_590 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_14_cast_fu_390_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_14_cast_reg_600 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_fu_405_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_605 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_410_p2 : STD_LOGIC_VECTOR (15 downto 0); signal i_1_reg_609 : STD_LOGIC_VECTOR (15 downto 0); signal sample_addr_1_reg_614 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_19_i_fu_428_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_i_reg_620 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_422_p2 : STD_LOGIC_VECTOR (63 downto 0); signal p_rec_reg_624 : STD_LOGIC_VECTOR (63 downto 0); signal sym_reg_629 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_19_1_i_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_1_i_reg_634 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_372_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal r_bit_reg_638 : STD_LOGIC_VECTOR (4 downto 0); signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 : STD_LOGIC_VECTOR (1 downto 0); signal j_bucket_index1_ph_cast_fu_444_p1 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_ph_cast_fu_448_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_7_i_cast_fu_452_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_i_cast_reg_658 : STD_LOGIC_VECTOR (13 downto 0); signal j_end_phi_fu_316_p4 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_471_p2 : STD_LOGIC_VECTOR (5 downto 0); signal state_reg_673 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_484_p2 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_6_i_reg_688 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_490_p2 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_8_i_reg_693 : STD_LOGIC_VECTOR (13 downto 0); signal j_bit_reg_711 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_index_reg_716 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_reg_721 : STD_LOGIC_VECTOR (31 downto 0); signal p_s_reg_726 : STD_LOGIC_VECTOR (0 downto 0); signal next_buckets_0_1_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_1_reg_731 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_1_fu_552_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_reg_741 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_reg_756 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_fu_576_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_761 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_580_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_766 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_348_p_read : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_348_r_bit : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_348_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_348_r_bucket : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_348_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_348_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_348_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_348_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_348_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_360_ap_start : STD_LOGIC; signal grp_nfa_get_initials_fu_360_ap_done : STD_LOGIC; signal grp_nfa_get_initials_fu_360_ap_idle : STD_LOGIC; signal grp_nfa_get_initials_fu_360_ap_ready : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_360_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_360_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_360_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_ap_start : STD_LOGIC; signal grp_nfa_get_finals_fu_366_ap_done : STD_LOGIC; signal grp_nfa_get_finals_fu_366_ap_idle : STD_LOGIC; signal grp_nfa_get_finals_fu_366_ap_ready : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_ap_ce : STD_LOGIC; signal grp_nfa_get_finals_fu_366_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_366_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_372_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_372_ap_ce : STD_LOGIC; signal i_reg_138 : STD_LOGIC_VECTOR (15 downto 0); signal any_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0); signal p_01_rec_reg_150 : STD_LOGIC_VECTOR (63 downto 0); signal next_buckets_1_reg_162 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_reg_172 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_182 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_0_lcssa4_i_reg_194 : STD_LOGIC_VECTOR (0 downto 0); signal j_bucket1_ph_reg_207 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_ph_reg_220 : STD_LOGIC_VECTOR (1 downto 0); signal j_bit1_ph_reg_231 : STD_LOGIC_VECTOR (4 downto 0); signal j_end_ph_reg_242 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_buckets_1_3_reg_256 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_3_reg_269 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket1_reg_282 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_reg_293 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_reg_303 : STD_LOGIC_VECTOR (7 downto 0); signal j_end_reg_313 : STD_LOGIC_VECTOR (0 downto 0); signal any_reg_323 : STD_LOGIC_VECTOR (0 downto 0); signal p_0_reg_336 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0); signal grp_nfa_get_finals_fu_366_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_fu_400_p2 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_4_i_cast_fu_501_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_9_i_cast_fu_519_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_400_p0 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_400_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_410_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_410_p1 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_422_p0 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_422_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_31_fu_455_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_471_p0 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_471_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_484_p0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_484_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_490_p0 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_490_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_4_i_fu_494_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_9_i_fu_512_p3 : STD_LOGIC_VECTOR (14 downto 0); signal grp_fu_400_ce : STD_LOGIC; signal grp_fu_410_ce : STD_LOGIC; signal grp_fu_422_ce : STD_LOGIC; signal grp_fu_471_ce : STD_LOGIC; signal grp_fu_484_ce : STD_LOGIC; signal grp_fu_490_ce : STD_LOGIC; signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal grp_fu_484_p00 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_484_p10 : STD_LOGIC_VECTOR (13 downto 0); component bitset_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_get_initials IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_get_finals IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (63 downto 0); din1 : IN STD_LOGIC_VECTOR (63 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (63 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (15 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (5 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (5 downto 0) ); end component; component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (7 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (13 downto 0); din1 : IN STD_LOGIC_VECTOR (13 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; begin grp_bitset_next_fu_348 : component bitset_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, p_read => grp_bitset_next_fu_348_p_read, r_bit => grp_bitset_next_fu_348_r_bit, r_bucket_index => grp_bitset_next_fu_348_r_bucket_index, r_bucket => grp_bitset_next_fu_348_r_bucket, ap_return_0 => grp_bitset_next_fu_348_ap_return_0, ap_return_1 => grp_bitset_next_fu_348_ap_return_1, ap_return_2 => grp_bitset_next_fu_348_ap_return_2, ap_return_3 => grp_bitset_next_fu_348_ap_return_3, ap_ce => grp_bitset_next_fu_348_ap_ce); grp_nfa_get_initials_fu_360 : component nfa_get_initials port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_initials_fu_360_ap_start, ap_done => grp_nfa_get_initials_fu_360_ap_done, ap_idle => grp_nfa_get_initials_fu_360_ap_idle, ap_ready => grp_nfa_get_initials_fu_360_ap_ready, nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_get_initials_fu_360_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_get_initials_fu_360_nfa_initials_buckets_size, ap_ce => grp_nfa_get_initials_fu_360_ap_ce, ap_return_0 => grp_nfa_get_initials_fu_360_ap_return_0, ap_return_1 => grp_nfa_get_initials_fu_360_ap_return_1); grp_nfa_get_finals_fu_366 : component nfa_get_finals port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_finals_fu_366_ap_start, ap_done => grp_nfa_get_finals_fu_366_ap_done, ap_idle => grp_nfa_get_finals_fu_366_ap_idle, ap_ready => grp_nfa_get_finals_fu_366_ap_ready, nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_get_finals_fu_366_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_get_finals_fu_366_nfa_finals_buckets_size, ap_ce => grp_nfa_get_finals_fu_366_ap_ce, ap_return_0 => grp_nfa_get_finals_fu_366_ap_return_0, ap_return_1 => grp_nfa_get_finals_fu_366_ap_return_1); grp_p_bsf32_hw_fu_372 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_372_bus_r, ap_return => grp_p_bsf32_hw_fu_372_ap_return, ap_ce => grp_p_bsf32_hw_fu_372_ap_ce); nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U17 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 generic map ( ID => 17, NUM_STAGE => 16, din0_WIDTH => 64, din1_WIDTH => 64, dout_WIDTH => 64) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_400_p0, din1 => grp_fu_400_p1, ce => grp_fu_400_ce, dout => grp_fu_400_p2); nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 generic map ( ID => 18, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 16, dout_WIDTH => 16) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_410_p0, din1 => grp_fu_410_p1, ce => grp_fu_410_ce, dout => grp_fu_410_p2); nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U19 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 generic map ( ID => 19, NUM_STAGE => 16, din0_WIDTH => 64, din1_WIDTH => 64, dout_WIDTH => 64) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_422_p0, din1 => grp_fu_422_p1, ce => grp_fu_422_ce, dout => grp_fu_422_p2); nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 generic map ( ID => 20, NUM_STAGE => 2, din0_WIDTH => 6, din1_WIDTH => 6, dout_WIDTH => 6) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_471_p0, din1 => grp_fu_471_p1, ce => grp_fu_471_ce, dout => grp_fu_471_p2); nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 generic map ( ID => 21, NUM_STAGE => 4, din0_WIDTH => 8, din1_WIDTH => 6, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_484_p0, din1 => grp_fu_484_p1, ce => grp_fu_484_ce, dout => grp_fu_484_p2); nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 generic map ( ID => 22, NUM_STAGE => 4, din0_WIDTH => 14, din1_WIDTH => 14, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_490_p0, din1 => grp_fu_490_p1, ce => grp_fu_490_ce, dout => grp_fu_490_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_return_preg assign process. -- ap_return_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_return_preg <= ap_const_lv1_0; else if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then ap_return_preg <= p_0_reg_336; end if; end if; end if; end process; -- grp_nfa_get_finals_fu_366_ap_start_ap_start_reg assign process. -- grp_nfa_get_finals_fu_366_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st24_fsm_23 = ap_NS_fsm) and (ap_ST_st23_fsm_22 = ap_CS_fsm) and (tmp_s_reg_605 = ap_const_lv1_0))) then grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_366_ap_ready)) then grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- agg_result_bucket_index_0_lcssa4_i_reg_194 assign process. -- agg_result_bucket_index_0_lcssa4_i_reg_194_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_1; elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_0; end if; end if; end process; -- any_reg_323 assign process. -- any_reg_323_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then any_reg_323 <= ap_const_lv1_0; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then any_reg_323 <= ap_const_lv1_1; end if; end if; end process; -- bus_assign_reg_182 assign process. -- bus_assign_reg_182_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then bus_assign_reg_182 <= next_buckets_1_reg_162; elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then bus_assign_reg_182 <= next_buckets_0_reg_172; end if; end if; end process; -- i_reg_138 assign process. -- i_reg_138_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then i_reg_138 <= i_1_reg_609; elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then i_reg_138 <= ap_const_lv16_0; end if; end if; end process; -- j_bit1_reg_303 assign process. -- j_bit1_reg_303_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then j_bit1_reg_303 <= j_bit1_ph_cast_fu_448_p1; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then j_bit1_reg_303 <= j_bit_reg_711; end if; end if; end process; -- j_bucket1_ph_reg_207 assign process. -- j_bucket1_ph_reg_207_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bucket1_ph_reg_207 <= bus_assign_reg_182; elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then j_bucket1_ph_reg_207 <= ap_const_lv32_0; end if; end if; end process; -- j_bucket1_reg_282 assign process. -- j_bucket1_reg_282_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then j_bucket1_reg_282 <= j_bucket1_ph_reg_207; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then j_bucket1_reg_282 <= j_bucket_reg_721; end if; end if; end process; -- j_bucket_index1_ph_reg_220 assign process. -- j_bucket_index1_ph_reg_220_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bucket_index1_ph_reg_220 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1; elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then j_bucket_index1_ph_reg_220 <= ap_const_lv2_2; end if; end if; end process; -- j_bucket_index1_reg_293 assign process. -- j_bucket_index1_reg_293_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then j_bucket_index1_reg_293 <= j_bucket_index1_ph_cast_fu_444_p1; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then j_bucket_index1_reg_293 <= j_bucket_index_reg_716; end if; end if; end process; -- j_end_ph_reg_242 assign process. -- j_end_ph_reg_242_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_end_ph_reg_242 <= ap_const_lv1_0; elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then j_end_ph_reg_242 <= ap_const_lv1_1; end if; end if; end process; -- j_end_reg_313 assign process. -- j_end_reg_313_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then j_end_reg_313 <= j_end_ph_reg_242; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then j_end_reg_313 <= p_s_reg_726; end if; end if; end process; -- next_buckets_0_reg_172 assign process. -- next_buckets_0_reg_172_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then next_buckets_0_reg_172 <= tmp_buckets_0_3_reg_269; elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then next_buckets_0_reg_172 <= current_buckets_0_reg_585; end if; end if; end process; -- next_buckets_1_reg_162 assign process. -- next_buckets_1_reg_162_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then next_buckets_1_reg_162 <= tmp_buckets_1_3_reg_256; elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then next_buckets_1_reg_162 <= current_buckets_1_reg_590; end if; end if; end process; -- p_01_rec_reg_150 assign process. -- p_01_rec_reg_150_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then p_01_rec_reg_150 <= p_rec_reg_624; elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then p_01_rec_reg_150 <= ap_const_lv64_0; end if; end if; end process; -- p_0_reg_336 assign process. -- p_0_reg_336_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then p_0_reg_336 <= ap_const_lv1_0; elsif ((ap_ST_st72_fsm_71 = ap_CS_fsm)) then p_0_reg_336 <= tmp_2_reg_766; end if; end if; end process; -- tmp_buckets_0_3_reg_269 assign process. -- tmp_buckets_0_3_reg_269_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then tmp_buckets_0_3_reg_269 <= ap_const_lv32_0; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then tmp_buckets_0_3_reg_269 <= next_buckets_0_1_reg_731; end if; end if; end process; -- tmp_buckets_1_3_reg_256 assign process. -- tmp_buckets_1_3_reg_256_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then tmp_buckets_1_3_reg_256 <= ap_const_lv32_0; elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then tmp_buckets_1_3_reg_256 <= next_buckets_1_1_fu_552_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st69_fsm_68 = ap_CS_fsm)) then current_buckets_0_1_reg_751 <= current_buckets_0_1_fu_566_p2; current_buckets_1_1_reg_756 <= current_buckets_1_1_fu_571_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then current_buckets_0_reg_585 <= grp_nfa_get_initials_fu_360_ap_return_0; current_buckets_1_reg_590 <= grp_nfa_get_initials_fu_360_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then i_1_reg_609 <= grp_fu_410_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bit1_ph_reg_231 <= r_bit_reg_638; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then j_bit_reg_711 <= grp_bitset_next_fu_348_ap_return_0; j_bucket_index_reg_716 <= grp_bitset_next_fu_348_ap_return_1; j_bucket_reg_721 <= grp_bitset_next_fu_348_ap_return_2; p_s_reg_726 <= grp_bitset_next_fu_348_ap_return_3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm))) then next_buckets_0_1_reg_731 <= next_buckets_0_1_fu_546_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then p_rec_reg_624 <= grp_fu_422_p2; sym_reg_629 <= sample_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then r_bit_reg_638 <= grp_p_bsf32_hw_fu_372_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_st60_fsm_59 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm)))) then reg_378 <= nfa_forward_buckets_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then sample_addr_1_reg_614 <= grp_fu_400_p2(32 - 1 downto 0); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then state_reg_673 <= grp_fu_471_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then tmp_14_cast_reg_600(0) <= tmp_14_cast_fu_390_p1(0); tmp_14_cast_reg_600(1) <= tmp_14_cast_fu_390_p1(1); tmp_14_cast_reg_600(2) <= tmp_14_cast_fu_390_p1(2); tmp_14_cast_reg_600(3) <= tmp_14_cast_fu_390_p1(3); tmp_14_cast_reg_600(4) <= tmp_14_cast_fu_390_p1(4); tmp_14_cast_reg_600(5) <= tmp_14_cast_fu_390_p1(5); tmp_14_cast_reg_600(6) <= tmp_14_cast_fu_390_p1(6); tmp_14_cast_reg_600(7) <= tmp_14_cast_fu_390_p1(7); tmp_14_cast_reg_600(8) <= tmp_14_cast_fu_390_p1(8); tmp_14_cast_reg_600(9) <= tmp_14_cast_fu_390_p1(9); tmp_14_cast_reg_600(10) <= tmp_14_cast_fu_390_p1(10); tmp_14_cast_reg_600(11) <= tmp_14_cast_fu_390_p1(11); tmp_14_cast_reg_600(12) <= tmp_14_cast_fu_390_p1(12); tmp_14_cast_reg_600(13) <= tmp_14_cast_fu_390_p1(13); tmp_14_cast_reg_600(14) <= tmp_14_cast_fu_390_p1(14); tmp_14_cast_reg_600(15) <= tmp_14_cast_fu_390_p1(15); tmp_14_cast_reg_600(16) <= tmp_14_cast_fu_390_p1(16); tmp_14_cast_reg_600(17) <= tmp_14_cast_fu_390_p1(17); tmp_14_cast_reg_600(18) <= tmp_14_cast_fu_390_p1(18); tmp_14_cast_reg_600(19) <= tmp_14_cast_fu_390_p1(19); tmp_14_cast_reg_600(20) <= tmp_14_cast_fu_390_p1(20); tmp_14_cast_reg_600(21) <= tmp_14_cast_fu_390_p1(21); tmp_14_cast_reg_600(22) <= tmp_14_cast_fu_390_p1(22); tmp_14_cast_reg_600(23) <= tmp_14_cast_fu_390_p1(23); tmp_14_cast_reg_600(24) <= tmp_14_cast_fu_390_p1(24); tmp_14_cast_reg_600(25) <= tmp_14_cast_fu_390_p1(25); tmp_14_cast_reg_600(26) <= tmp_14_cast_fu_390_p1(26); tmp_14_cast_reg_600(27) <= tmp_14_cast_fu_390_p1(27); tmp_14_cast_reg_600(28) <= tmp_14_cast_fu_390_p1(28); tmp_14_cast_reg_600(29) <= tmp_14_cast_fu_390_p1(29); tmp_14_cast_reg_600(30) <= tmp_14_cast_fu_390_p1(30); tmp_14_cast_reg_600(31) <= tmp_14_cast_fu_390_p1(31); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then tmp_19_1_i_reg_634 <= tmp_19_1_i_fu_434_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then tmp_19_i_reg_620 <= tmp_19_i_fu_428_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st70_fsm_69 = ap_CS_fsm)) then tmp_1_reg_761 <= tmp_1_fu_576_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st71_fsm_70 = ap_CS_fsm)) then tmp_2_reg_766 <= tmp_2_fu_580_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st50_fsm_49 = ap_CS_fsm)) then tmp_6_i_reg_688 <= grp_fu_484_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then tmp_7_i_cast_reg_658(0) <= tmp_7_i_cast_fu_452_p1(0); tmp_7_i_cast_reg_658(1) <= tmp_7_i_cast_fu_452_p1(1); tmp_7_i_cast_reg_658(2) <= tmp_7_i_cast_fu_452_p1(2); tmp_7_i_cast_reg_658(3) <= tmp_7_i_cast_fu_452_p1(3); tmp_7_i_cast_reg_658(4) <= tmp_7_i_cast_fu_452_p1(4); tmp_7_i_cast_reg_658(5) <= tmp_7_i_cast_fu_452_p1(5); tmp_7_i_cast_reg_658(6) <= tmp_7_i_cast_fu_452_p1(6); tmp_7_i_cast_reg_658(7) <= tmp_7_i_cast_fu_452_p1(7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st54_fsm_53 = ap_CS_fsm)) then tmp_8_i_reg_693 <= grp_fu_490_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st68_fsm_67 = ap_CS_fsm)) then tmp_buckets_0_reg_741 <= grp_nfa_get_finals_fu_366_ap_return_0; tmp_buckets_1_reg_746 <= grp_nfa_get_finals_fu_366_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then tmp_s_reg_605 <= tmp_s_fu_405_p2; end if; end if; end process; tmp_14_cast_reg_600(63 downto 32) <= "00000000000000000000000000000000"; tmp_7_i_cast_reg_658(13 downto 8) <= "000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_605 , tmp_19_i_reg_620 , tmp_19_1_i_reg_634 , j_end_phi_fu_316_p4 , any_phi_fu_328_p4) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => if ((tmp_s_reg_605 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st63_fsm_62; else ap_NS_fsm <= ap_ST_st25_fsm_24; end if; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st41_fsm_40; elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st40_fsm_39; else ap_NS_fsm <= ap_ST_st39_fsm_38; end if; when ap_ST_st40_fsm_39 => if (not((tmp_19_1_i_reg_634 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st44_fsm_43; else ap_NS_fsm <= ap_ST_st41_fsm_40; end if; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st43_fsm_42; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st44_fsm_43; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => if ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then ap_NS_fsm <= ap_ST_st9_fsm_8; elsif ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then ap_NS_fsm <= ap_ST_st73_fsm_72; else ap_NS_fsm <= ap_ST_st46_fsm_45; end if; when ap_ST_st46_fsm_45 => ap_NS_fsm <= ap_ST_st47_fsm_46; when ap_ST_st47_fsm_46 => ap_NS_fsm <= ap_ST_st48_fsm_47; when ap_ST_st48_fsm_47 => ap_NS_fsm <= ap_ST_st49_fsm_48; when ap_ST_st49_fsm_48 => ap_NS_fsm <= ap_ST_st50_fsm_49; when ap_ST_st50_fsm_49 => ap_NS_fsm <= ap_ST_st51_fsm_50; when ap_ST_st51_fsm_50 => ap_NS_fsm <= ap_ST_st52_fsm_51; when ap_ST_st52_fsm_51 => ap_NS_fsm <= ap_ST_st53_fsm_52; when ap_ST_st53_fsm_52 => ap_NS_fsm <= ap_ST_st54_fsm_53; when ap_ST_st54_fsm_53 => ap_NS_fsm <= ap_ST_st55_fsm_54; when ap_ST_st55_fsm_54 => ap_NS_fsm <= ap_ST_st56_fsm_55; when ap_ST_st56_fsm_55 => ap_NS_fsm <= ap_ST_st57_fsm_56; when ap_ST_st57_fsm_56 => ap_NS_fsm <= ap_ST_st58_fsm_57; when ap_ST_st58_fsm_57 => ap_NS_fsm <= ap_ST_st59_fsm_58; when ap_ST_st59_fsm_58 => ap_NS_fsm <= ap_ST_st60_fsm_59; when ap_ST_st60_fsm_59 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st61_fsm_60; else ap_NS_fsm <= ap_ST_st60_fsm_59; end if; when ap_ST_st61_fsm_60 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st62_fsm_61; else ap_NS_fsm <= ap_ST_st61_fsm_60; end if; when ap_ST_st62_fsm_61 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st63_fsm_62 => ap_NS_fsm <= ap_ST_st64_fsm_63; when ap_ST_st64_fsm_63 => ap_NS_fsm <= ap_ST_st65_fsm_64; when ap_ST_st65_fsm_64 => ap_NS_fsm <= ap_ST_st66_fsm_65; when ap_ST_st66_fsm_65 => ap_NS_fsm <= ap_ST_st67_fsm_66; when ap_ST_st67_fsm_66 => ap_NS_fsm <= ap_ST_st68_fsm_67; when ap_ST_st68_fsm_67 => ap_NS_fsm <= ap_ST_st69_fsm_68; when ap_ST_st69_fsm_68 => ap_NS_fsm <= ap_ST_st70_fsm_69; when ap_ST_st70_fsm_69 => ap_NS_fsm <= ap_ST_st71_fsm_70; when ap_ST_st71_fsm_70 => ap_NS_fsm <= ap_ST_st72_fsm_71; when ap_ST_st72_fsm_71 => ap_NS_fsm <= ap_ST_st73_fsm_72; when ap_ST_st73_fsm_72 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXXX"; end case; end process; agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_194),2)); any_phi_fu_328_p4 <= any_reg_323; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st73_fsm_72 = ap_CS_fsm))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_return assign process. -- ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_336, ap_return_preg) begin if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then ap_return <= p_0_reg_336; else ap_return <= ap_return_preg; end if; end process; current_buckets_0_1_fu_566_p2 <= (next_buckets_0_reg_172 and tmp_buckets_0_reg_741); current_buckets_1_1_fu_571_p2 <= (next_buckets_1_reg_162 and tmp_buckets_1_reg_746); -- grp_bitset_next_fu_348_ap_ce assign process. -- grp_bitset_next_fu_348_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_316_p4) begin if ((((ap_ST_st45_fsm_44 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_316_p4)) or (ap_ST_st46_fsm_45 = ap_CS_fsm) or (ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st50_fsm_49 = ap_CS_fsm) or (ap_ST_st54_fsm_53 = ap_CS_fsm) or (ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm) or (ap_ST_st48_fsm_47 = ap_CS_fsm) or (ap_ST_st49_fsm_48 = ap_CS_fsm) or (ap_ST_st51_fsm_50 = ap_CS_fsm) or (ap_ST_st52_fsm_51 = ap_CS_fsm) or (ap_ST_st53_fsm_52 = ap_CS_fsm))) then grp_bitset_next_fu_348_ap_ce <= ap_const_logic_1; else grp_bitset_next_fu_348_ap_ce <= ap_const_logic_0; end if; end process; grp_bitset_next_fu_348_p_read <= next_buckets_1_reg_162; grp_bitset_next_fu_348_r_bit <= j_bit1_reg_303; grp_bitset_next_fu_348_r_bucket <= j_bucket1_reg_282; grp_bitset_next_fu_348_r_bucket_index <= j_bucket_index1_reg_293; grp_fu_400_ce <= ap_const_logic_1; grp_fu_400_p0 <= p_01_rec_reg_150; grp_fu_400_p1 <= tmp_14_cast_reg_600; grp_fu_410_ce <= ap_const_logic_1; grp_fu_410_p0 <= i_reg_138; grp_fu_410_p1 <= ap_const_lv16_1; -- grp_fu_422_ce assign process. -- grp_fu_422_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_605) begin if (((ap_ST_st38_fsm_37 = ap_CS_fsm) or ((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or ((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((tmp_s_reg_605 = ap_const_lv1_0))) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm))) then grp_fu_422_ce <= ap_const_logic_1; else grp_fu_422_ce <= ap_const_logic_0; end if; end process; grp_fu_422_p0 <= p_01_rec_reg_150; grp_fu_422_p1 <= ap_const_lv64_1; grp_fu_471_ce <= ap_const_logic_1; grp_fu_471_p0 <= (tmp_31_fu_455_p1 & ap_const_lv5_0); grp_fu_471_p1 <= j_bit1_reg_303(6 - 1 downto 0); grp_fu_484_ce <= ap_const_logic_1; grp_fu_484_p0 <= grp_fu_484_p00(8 - 1 downto 0); grp_fu_484_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14)); grp_fu_484_p1 <= grp_fu_484_p10(6 - 1 downto 0); grp_fu_484_p10 <= std_logic_vector(resize(unsigned(state_reg_673),14)); grp_fu_490_ce <= ap_const_logic_1; grp_fu_490_p0 <= tmp_6_i_reg_688; grp_fu_490_p1 <= tmp_7_i_cast_reg_658; grp_nfa_get_finals_fu_366_ap_ce <= ap_const_logic_1; grp_nfa_get_finals_fu_366_ap_start <= grp_nfa_get_finals_fu_366_ap_start_ap_start_reg; grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_get_initials_fu_360_ap_ce <= ap_const_logic_1; -- grp_nfa_get_initials_fu_360_ap_start assign process. -- grp_nfa_get_initials_fu_360_ap_start_assign_proc : process(ap_start, ap_CS_fsm) begin if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_1; else grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_0; end if; end process; grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; -- grp_p_bsf32_hw_fu_372_ap_ce assign process. -- grp_p_bsf32_hw_fu_372_ap_ce_assign_proc : process(ap_CS_fsm) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_0; end if; end process; grp_p_bsf32_hw_fu_372_bus_r <= bus_assign_reg_182; j_bit1_ph_cast_fu_448_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_231),8)); j_bucket_index1_ph_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_220),8)); j_end_phi_fu_316_p4 <= j_end_reg_313; next_buckets_0_1_fu_546_p2 <= (tmp_buckets_0_3_reg_269 or reg_378); next_buckets_1_1_fu_552_p2 <= (tmp_buckets_1_3_reg_256 or reg_378); nfa_finals_buckets_address <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_size; -- nfa_forward_buckets_address assign process. -- nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_4_i_cast_fu_501_p1, tmp_9_i_cast_fu_519_p1) begin if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then nfa_forward_buckets_address <= tmp_9_i_cast_fu_519_p1(32 - 1 downto 0); elsif ((ap_ST_st55_fsm_54 = ap_CS_fsm)) then nfa_forward_buckets_address <= tmp_4_i_cast_fu_501_p1(32 - 1 downto 0); else nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_forward_buckets_dataout <= ap_const_lv32_0; nfa_forward_buckets_req_din <= ap_const_logic_0; -- nfa_forward_buckets_req_write assign process. -- nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm) begin if (((ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm))) then nfa_forward_buckets_req_write <= ap_const_logic_1; else nfa_forward_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_forward_buckets_rsp_read assign process. -- nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st60_fsm_59 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm)))) then nfa_forward_buckets_rsp_read <= ap_const_logic_1; else nfa_forward_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_forward_buckets_size <= ap_const_lv32_1; nfa_initials_buckets_address <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_size; sample_address <= sample_addr_1_reg_614; sample_dataout <= ap_const_lv8_0; sample_req_din <= ap_const_logic_0; -- sample_req_write assign process. -- sample_req_write_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then sample_req_write <= ap_const_logic_1; else sample_req_write <= ap_const_logic_0; end if; end process; -- sample_rsp_read assign process. -- sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then sample_rsp_read <= ap_const_logic_1; else sample_rsp_read <= ap_const_logic_0; end if; end process; sample_size <= ap_const_lv32_1; tmp_14_cast_fu_390_p1 <= std_logic_vector(resize(unsigned(tmp_14),64)); tmp_19_1_i_fu_434_p2 <= "1" when (next_buckets_1_reg_162 = ap_const_lv32_0) else "0"; tmp_19_i_fu_428_p2 <= "1" when (next_buckets_0_reg_172 = ap_const_lv32_0) else "0"; tmp_1_fu_576_p2 <= (current_buckets_1_1_reg_756 or current_buckets_0_1_reg_751); tmp_2_fu_580_p2 <= "0" when (tmp_1_reg_761 = ap_const_lv32_0) else "1"; tmp_31_fu_455_p1 <= j_bucket_index1_reg_293(1 - 1 downto 0); tmp_4_i_cast_fu_501_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_494_p3),64)); tmp_4_i_fu_494_p3 <= (tmp_8_i_reg_693 & ap_const_lv1_0); tmp_7_i_cast_fu_452_p1 <= std_logic_vector(resize(unsigned(sym_reg_629),14)); tmp_9_i_cast_fu_519_p1 <= std_logic_vector(resize(unsigned(tmp_9_i_fu_512_p3),64)); tmp_9_i_fu_512_p3 <= (tmp_8_i_reg_693 & ap_const_lv1_1); tmp_s_fu_405_p2 <= "1" when (unsigned(i_reg_138) < unsigned(length_r)) else "0"; end behav;
lgpl-3.0
74cbe085053c6685fce27601e8ab425d
0.577384
2.743567
false
false
false
false
jairov4/accel-oil
impl/impl_test_pcie/simulation/behavioral/system_clock_generator_0_wrapper.vhd
1
3,128
------------------------------------------------------------------------------- -- system_clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_03_a; use clock_generator_0_v4_03_a.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end system_clock_generator_0_wrapper; architecture STRUCTURE of system_clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "virtex5", C_DEVICE => "5vlx50t", C_PACKAGE => "ff1136", C_SPEEDGRADE => "-1" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;
lgpl-3.0
3f4d0517e269881b3f10e6d6ce9f5368
0.569054
3.662763
false
false
false
false
dcliche/mdsynth
rtl/test_benches/channel_tb/src/sim_channel_tb.vhd
1
2,398
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use STD.TEXTIO.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; entity sim_channel_tb is generic ( log_file: string := "res.log" ); end sim_channel_tb; architecture sim_channel_tb_arch of sim_channel_tb is component channel_tb is port ( clk_50mhz: in std_logic; btn_south: in std_logic; btn_north: in std_logic; sw: in std_logic_vector(3 downto 0); aud_l: out std_logic; aud_r: out std_logic; aux_aud_l: out std_logic; aux_aud_r: out std_logic; output: out std_logic_vector(7 downto 0) ); end component; signal clk : std_logic := '0'; constant clk_half_period : time := 10 ns; signal btn_south : std_logic := '1'; signal btn_north : std_logic := '0'; signal sw : std_logic_vector(3 downto 0) := "0100"; signal aud_l : std_logic; signal aud_r : std_logic; signal aux_aud_l : std_logic; signal aux_aud_r : std_logic; signal output : std_logic_vector(7 downto 0); file l_file: TEXT open write_mode is log_file; begin channel_tb0: channel_tb port map ( clk_50mhz => clk, btn_south => btn_south, btn_north => btn_north, sw => sw, aud_l => aud_l, aud_r => aud_r, aux_aud_l => aux_aud_l, aux_aud_r => aux_aud_r, output => output ); clk <= not clk after clk_half_period; my_process : process begin wait for 1us; btn_south <= '0'; wait for 2us; btn_north <= '1'; while true loop wait until clk = '1'; end loop; end process; -- write data and control information to a file write_data: process variable my_line : line; variable my_counter : integer := 0; begin wait until btn_north='1'; while true loop if (my_counter mod (50000000 / 44100) = 0) then write(my_line, to_integer(unsigned(output))); writeline(l_file, my_line); end if; my_counter := my_counter + 1; wait until clk = '1'; end loop; end process; end sim_channel_tb_arch;
gpl-3.0
74671ad41dc476c1a44f3759fdb9eefa
0.516264
3.595202
false
false
false
false
grwlf/vsim
vhdl/sigloop1.vhd
1
478
entity ENT00001_Test_Bench is end entity ENT00001_Test_Bench; architecture arch of ENT00001_Test_Bench is constant CYCLES : integer := 1000; signal clk : integer := 0; signal sig1 : integer := 0; signal sig2 : integer := 1; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; sig1 <= sig1 + sig2 after 1 us; clk <= clk + 1 after 1 us; end;
gpl-3.0
e0b015718a89e27be48a87bcdda33cd4
0.679916
3.064103
false
true
false
false
dcliche/mdsynth
rtl/src/sys09bug_s3e_rom2k_b16.vhd
1
8,906
--===========================================================================-- -- -- -- sys09bug_s3e_rom2k_b16.vhd - Sys09bug monitor ROM for the Spartan 3E500 -- -- -- --===========================================================================-- -- -- File name : sys09bug_s3e_rom2k_b16.vhd -- -- Entity name : mon_rom -- -- Purpose : Implements 2K Monitor ROM for System09 -- using 1 x Spartan 3E RAMB16_S9 block ram -- Used in the Digilent Spartan 3E500 System09 design -- -- Dependencies : ieee.Std_Logic_1164 -- ieee.std_logic_arith -- unisim.vcomponents -- -- Uses : RAMB16_S9 -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- -- Copyright (C) 2008 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Changes -- 0.1 John Kent 2008-01-08 Initial Version -- 0.2 John Kent 2010-09-14 Added Header -- renamed rdata & wdata to data_out & data_in -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; library unisim; use unisim.vcomponents.all; entity mon_rom is Port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic_vector (10 downto 0); rw : in std_logic; data_in : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0) ); end mon_rom; architecture rtl of mon_rom is signal we : std_logic; signal dp : std_logic; begin MON_ROM : RAMB16_S9 generic map ( INIT_00 => x"A780A610C6C07F8E1060FE8EE0FE1FFB23FB94FBCFFCBAFC9CFCA2FC4BF814F8", INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6450117D07FBF00E08EF9265AA0", INIT_02 => x"092C2081891FF1270D817F844E0417CE021794FE8EDE01174C031770FE8EA404", INIT_03 => x"FE8C02300F2780E12AFE8E20C0022F60C15E0417630417408B981F6A04175E86", INIT_04 => x"1F8002179CFE8E121F2D298603173B341FBC2094ADC0200B031796FE8EF52660", INIT_05 => x"17275E81DD271881E127088111287903171E0417C00317A4A6260417C0031721", INIT_06 => x"321FBD0217BE203F31C2202131FC03173F86FF03170827A4A1A4A7390F260D81", INIT_07 => x"F0C4201F0634F0C41000C3101F390124E1AC2034062926031705201F30C07F8E", INIT_08 => x"10C6AD0317490317E4AE0902179CFE8E10343962320327B103170527E4AC011F", INIT_09 => x"03172E8602237E810425208180A610C6E1AE9D0317F5265AA5031747031780A6", INIT_0a => x"273F8184A60F2710355B8DFFFF8E10341A24C07F8C1E29D20217BC20EE265A8E", INIT_0b => x"431F39FB265A1E8D08C6D37F8E105D03163F866003173984A73F86A4AFA0A709", INIT_0c => x"A60A24C07F8C21AEB3FE16ED7FBF00008E6302170C8D4AAF04272C8D1F304AAE", INIT_0d => x"265A0427A1ACA0A608C6D37F8E1039A0A7A0A7A0A7FF8684A7A4A604263F8184", INIT_0e => x"7FBFE7F98EEB7FBFC07FBEED7FBF14294B02170003171C29710117393D3139F7", INIT_0f => x"27ED7FBE24273F8184A64AAEFE011770E0B671E0B73686431F392020450017C0", INIT_10 => x"3B71E0B73F8673E0B7368670E0B671E0B7368670E0B70D86341FED7FBF1F301F", INIT_11 => x"B7368672E0B7008670E0B7FF8673E0B73A8671E0B7328622FE16C07FBFEB7FBE", INIT_12 => x"81380217D27F7F7602171186E8FCBD8435FD265A20C604343973E0B73E8671E0", INIT_13 => x"E0EBE0E610342129A3011726290234BA0117F12631813D273981310217F92653", INIT_14 => x"FFC102355FEB2080A70527E46AE0EB02340C290435A001170434E46AE46AE4EB", INIT_15 => x"02161386D27F73DE0117E101177801177B01177E01178101172802173F86BA27", INIT_16 => x"062762A3E4ECF501171286E8FCBDE4AF0130492562AC4D2930344A0117E26F0E", INIT_17 => x"63EB62EB68011762AE750117981F03CB2F0017DDFE8E64E720C6022320008310", INIT_18 => x"8D396532B301171486C326E4AC62AF5B0117981F53F526646A65011780A684EB", INIT_19 => x"AF0229F68DF28D910017E50016F800169D011690356900178EFE8E1034712002", INIT_1a => x"0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE78D618D394A", INIT_1b => x"29B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D498D3944AF", INIT_1c => x"F48DA0FE8E39F726048180A63B011739C4A7808A0429A68DA58D5F8D3941A702", INIT_1d => x"2044AED78DB8FE8EB4001643A6E18DBEFE8EF42048AEEA8DACFE8EBF0016311F", INIT_1e => x"8DC9FE8ED92041A6BC8DC4FE8ECF204AAEC58DA6FE8ED82046AECE8DB2FE8EE1", INIT_1f => x"B88DB08DA98DA18D27FF179CFE8E900016D5FE8EC4A6AA8DCEFE8ED02042A6B3", INIT_20 => x"1F42290E8DB400172D86121F4D29098DD520CE8DC78DC08D17FF179CFE8EBF8D", INIT_21 => x"578D39E0AB04342829078D891F484848483229118D903561A710343C29088D01", INIT_22 => x"578003226681072561813937800322468112254181393080032239811D253081", INIT_23 => x"078B022F3981308B0F840235048D4444444402340235028D0235103439021A39", INIT_24 => x"7F84048D0627D27F7D8235F1265A3B8D3F8D2D860225E46880A608C602344D20", INIT_25 => x"D07F9FA60234903501A6EE27018584A620E08E0926018584A6D07FBE10342D20", INIT_26 => x"F6260885FA27028584A6D07FBE1234498D2086008D8235018520E0B605260185", INIT_27 => x"00CC30E08E39D27FB7FF86016D84A7518684A70386D07FBE138D903501A70235", INIT_28 => x"7D30E08E16345986028D1B86F27F7F01E702C6F17FFD04E703E702A7EF7FFD00", INIT_29 => x"815A271B81342708819635AF001784A70520098D042420810D20608D0427F27F", INIT_2a => x"C15CEF7FFC45260A810F270B8124270C81890027100D81382716817C0027101A", INIT_2b => x"20212750814CEF7FB662204A2C27EF7FB66D205A34275DEF7FFC8F0016792619", INIT_2c => x"F27F7F39F27FB704263D81312754816E27598114273DC1F27FF656200000CC58", INIT_2d => x"20E12218C120C0F17F7FF17FF6ED224F812080F27F7F39F17FB70426F17F7D39", INIT_2e => x"A7EF7FFDF07FF64F39F27F7FF726508102A74C84E720C6EF7FB6168D0000CC1B", INIT_2f => x"F604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CEF7FFC3903E702", INIT_30 => x"E4205F03E7F07FF7082719C15CF07FF6F42650C15C84A702E7EF7FF72086EF7F", INIT_31 => x"1958FB1842FB1536FB1063FB0484FB036EFB0279FB0139F27FF702E7EF7FF75F", INIT_32 => x"C5F95472F958DBF853F2FB5292F84DC1FA5051FA4C8FF847E7F84546F9424DFB", INIT_33 => x"4F462047554239305359530000000A0DFFFFFFFF7EF991F891F891F891F87EF9", INIT_34 => x"04202D20043F54414857043E040000000A0D4B04202D2048544E5953444D2052", INIT_35 => x"2020043D58492020043D59492020043D53552020043D43502020043D50532020", INIT_36 => x"04315343565A4E4948464504203A43432020043D422020043D412020043D5044", INIT_37 => x"7F9F6EC87F9F6EC67F9F6EC47F9F6EC07F9F6E27F916D27FF7535FC07FCE1039", INIT_38 => x"AEC4EC10340822CE7FBC8B300F27FFFF8CCC7FBE49584F4AAF80E64AAE431FCA", INIT_39 => x"000000000000000000000000000000000000000000C27F9F6E42EE1F37F16E44", INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3f => x"E1FEEDFEFDFEF9FEF5FEF1FE01FFEDFE00000000000000000000000000000000" ) port map ( do => data_out, dop(0) => dp, addr => addr, clk => clk, di => data_in, dip(0) => dp, en => cs, ssr => rst, we => we ); my_sbug : process ( rw ) begin we <= not rw; end process; end architecture rtl;
gpl-3.0
06990c3af8ace35f20bd7ad2735bfb72
0.676061
2.832697
false
false
false
false
wsoltys/AtomFpga
mist/Atomic_top_mist.vhd
1
18,308
-------------------------------------------------------------------------------- -- Copyright (c) 2009 Alan Daly. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : Atomic_top.vhf -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: Atomic_top --Device: spartan3E library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity Atomic_top_mist is port ( -- Clocks CLOCK_27 : in std_logic_vector(1 downto 0); -- 27 MHz -- SDRAM SDRAM_nCS : out std_logic; -- Chip Select SDRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits SDRAM_DQMH : out std_logic; -- SDRAM High Data Mask SDRAM_DQML : out std_logic; -- SDRAM Low-byte Data Mask SDRAM_nWE : out std_logic; -- SDRAM Write Enable SDRAM_nCAS : out std_logic; -- SDRAM Column Address Strobe SDRAM_nRAS : out std_logic; -- SDRAM Row Address Strobe SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM Bank Address SDRAM_CLK : out std_logic; -- SDRAM Clock SDRAM_CKE: out std_logic; -- SDRAM Clock Enable -- SPI SPI_SCK : in std_logic; SPI_DI : in std_logic; SPI_DO : out std_logic; SPI_SS2 : in std_logic; SPI_SS3 : in std_logic; CONF_DATA0 : in std_logic; -- VGA output VGA_HS, -- H_SYNC VGA_VS : out std_logic; -- V_SYNC VGA_R, -- Red[5:0] VGA_G, -- Green[5:0] VGA_B : out std_logic_vector(5 downto 0); -- Blue[5:0] -- Audio AUDIO_L, AUDIO_R : out std_logic; -- LEDG LED : out std_logic ); end Atomic_top_mist; architecture behavioral of Atomic_top_mist is component dcm4 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component dcm5 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component RAM_2K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (10 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component RAM_8K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (12 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component InternalROM port ( CLK : in std_logic; ADDR : in std_logic_vector(16 downto 0); DATA : out std_logic_vector(7 downto 0) ); end component; component fpgautils port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component Atomic_core generic ( CImplSDDOS : boolean; CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; MainClockSpeed : integer; DefaultBaud : integer ); port ( clk_vga : in std_logic; clk_16M00 : in std_logic; clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERSTn : in std_logic; IRSTn : out std_logic; SDMISO : in std_logic; red : out std_logic_vector(2 downto 0); green : out std_logic_vector(2 downto 0); blue : out std_logic_vector(2 downto 0); vsync : out std_logic; hsync : out std_logic; RamCE : out std_logic; RomCE : out std_logic; Phi2 : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (16 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0); audiol : out std_logic; audioR : out std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; uart_RxD : in std_logic; uart_TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic ); end component; -- config string used by the io controller to fill the OSD constant CONF_STR : string := "Atom;;S1,BIN;"; function to_slv(s: string) return std_logic_vector is constant ss: string(1 to s'length) := s; variable rval: std_logic_vector(1 to 8 * s'length); variable p: integer; variable c: integer; begin for i in ss'range loop p := 8 * i; c := character'pos(ss(i)); rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); end loop; return rval; end function; component user_io generic ( STRLEN : integer := 0 ); port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic; SPI_MISO : out std_logic; conf_str : in std_logic_vector(8*STRLEN-1 downto 0); joystick_0 : out std_logic_vector(5 downto 0); joystick_1 : out std_logic_vector(5 downto 0); joystick_analog_0 : out std_logic_vector(15 downto 0); joystick_analog_1 : out std_logic_vector(15 downto 0); status: out std_logic_vector(7 downto 0); switches : out std_logic_vector(1 downto 0); buttons : out std_logic_vector(1 downto 0); sd_lba : in std_logic_vector(31 downto 0); sd_rd : in std_logic; sd_wr : in std_logic; sd_ack : out std_logic; sd_conf : in std_logic; sd_sdhc : in std_logic; sd_dout : out std_logic_vector(7 downto 0); sd_dout_strobe : out std_logic; sd_din : in std_logic_vector(7 downto 0); sd_din_strobe : out std_logic; sd_change : out std_logic; ps2_clk : in std_logic; ps2_kbd_clk : out std_logic; ps2_kbd_data : out std_logic; ps2_mouse_clk : out std_logic; ps2_mouse_data : out std_logic; serial_data : in std_logic_vector(7 downto 0); serial_strobe : in std_logic ); end component user_io; component mist_console generic ( CLKFREQ : integer := 100 ); port ( clk : in std_logic; n_reset: in std_logic; ser_in : in std_logic; par_out_data : out std_logic_vector(7 downto 0); par_out_strobe : out std_logic ); end component mist_console; component sd_card port (io_lba : out std_logic_vector(31 downto 0); io_rd : out std_logic; io_wr : out std_logic; io_ack : in std_logic; io_sdhc : out std_logic; io_conf : out std_logic; io_din : in std_logic_vector(7 downto 0); io_din_strobe : in std_logic; io_dout : out std_logic_vector(7 downto 0); io_dout_strobe : in std_logic; allow_sdhc : in std_logic; sd_cs : in std_logic; sd_sck : in std_logic; sd_sdi : in std_logic; sd_sdo : out std_logic ); end component sd_card; component osd port ( pclk, sck, ss, sdi, hs_in, vs_in, scanline_ena_h : in std_logic; red_in, blue_in, green_in : in std_logic_vector(5 downto 0); red_out, blue_out, green_out : out std_logic_vector(5 downto 0); hs_out, vs_out : out std_logic ); end component osd; signal clk_vga : std_logic; signal clk_32M00 : std_logic; signal clk_16M00 : std_logic; signal clk_osd : std_logic; signal clk12k : std_logic; signal r : std_logic_vector(2 downto 0); signal g : std_logic_vector(2 downto 0); signal b : std_logic_vector(2 downto 0); signal ERSTn : std_logic; signal RamCE : std_logic; signal RomCE : std_logic; signal RomCE1 : std_logic; signal RomCE2 : std_logic; signal RamCE1 : std_logic; signal RamCE2 : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector (16 downto 0); signal ExternDin : std_logic_vector (7 downto 0); signal ExternDout: std_logic_vector (7 downto 0); signal RamDout1 : std_logic_vector (7 downto 0); signal RamDout2 : std_logic_vector (7 downto 0); signal RomDout1 : std_logic_vector (7 downto 0); signal RomDout2 : std_logic_vector (7 downto 0); signal pll_locked : std_logic := '0'; -- user_io signal buttons: std_logic_vector(1 downto 0); signal status: std_logic_vector(7 downto 0); signal joy_0: std_logic_vector(5 downto 0); signal joy_1: std_logic_vector(5 downto 0); signal joyn_0: std_logic_vector(5 downto 0); signal joyn_1: std_logic_vector(5 downto 0); signal joy_ana_0: std_logic_vector(15 downto 0); signal joy_ana_1: std_logic_vector(15 downto 0); signal txd: std_logic; signal par_out_data: std_logic_vector(7 downto 0); signal par_out_strobe: std_logic; -- PS/2 signal ps2_clk : std_logic; signal ps2counter : unsigned(10 downto 0); -- PS/2 Keyboard signal ps2_keyboard_clk_in : std_logic; signal ps2_keyboard_dat_in : std_logic; -- PS/2 Mouse signal ps2_mouse_clk_in : std_logic; signal ps2_mouse_dat_in : std_logic; signal ps2_mouse_clk_out : std_logic; signal ps2_mouse_dat_out : std_logic; -- signals to connect sd card emulation with io controller signal sd_lba: std_logic_vector(31 downto 0); signal sd_rd: std_logic; signal sd_wr: std_logic; signal sd_ack: std_logic; signal sd_conf: std_logic; signal sd_sdhc: std_logic; -- data from io controller to sd card emulation signal sd_data_in: std_logic_vector(7 downto 0); signal sd_data_in_strobe: std_logic; signal sd_data_out: std_logic_vector(7 downto 0); signal sd_data_out_strobe: std_logic; -- sd card emulation signal sd_cs: std_logic; signal sd_sck: std_logic; signal sd_sdi: std_logic; signal sd_sdo: std_logic; signal VGA_HS_O: std_logic; signal VGA_VS_O: std_logic; signal reset_counter : std_logic_vector(7 downto 0); begin pllInstance : entity work.mist_pll port map ( inclk0 => CLOCK_27(0), c0 => clk_32M00, c1 => clk_vga, c2 => clk12k, locked => pll_locked ); plldiv1 : entity work.clk_div generic map ( DIVISOR => 2 ) port map ( clk => clk_32M00, reset => '0', clk_en => clk_16M00 ); plldiv2 : entity work.clk_div generic map ( DIVISOR => 2 ) port map ( clk => clk_vga, reset => '0', clk_en => clk_osd ); ram_0000_07ff : RAM_2K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE1, addr_uP => ExternA (10 downto 0), D_uP => ExternDin, Q_uP => RamDout1 ); ram_2000_3fff : RAM_8K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE2, addr_uP => ExternA (12 downto 0), D_uP => ExternDin, Q_uP => RamDout2 ); rom_c000_ffff : InternalROM port map( CLK => clk_16M00, ADDR => ExternA, DATA => RomDout1 ); rom_a000 : fpgautils port map( CLK => clk_16M00, ADDR => ExternA(11 downto 0), DATA => RomDout2 ); RamCE1 <= '1' when RamCE = '1' and ExternA(14 downto 11) = "0000" else '0'; RamCE2 <= '1' when RamCE = '1' and ExternA(14 downto 13) = "01" else '0'; RomCE1 <= '1' when RomCE = '1' and ExternA(15 downto 14) = "11" else '0'; RomCE2 <= '1' when RomCE = '1' and ExternA(15 downto 12) = "1010" else '0'; ExternDout(7 downto 0) <= RamDout1 when RamCE1 = '1' else RamDout2 when RamCE2 = '1' else RomDout1 when RomCE1 = '1' else RomDout2 when RomCE2 = '1' else "11110001"; -- ERSTn <= not (status(0) or buttons(1) or not pll_locked); process(clk_32M00) begin if rising_edge(clk_32M00) then ERSTn <= '0'; if status(0)='1' or pll_locked = '0' or buttons(1) = '1' then reset_counter <= (others => '0'); else if reset_counter = X"FF" then ERSTn <= '1'; else reset_counter <= std_logic_vector(unsigned(reset_counter)+1); end if; end if; end if; end process; inst_Atomic_core : Atomic_core generic map ( CImplSDDOS => true, CImplGraphicsExt => true, CImplSoftChar => false, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, MainClockSpeed => 16000000, DefaultBaud => 115200 ) port map( clk_vga => clk_vga, clk_16M00 => clk_16M00, clk_32M00 => clk_32M00, ps2_clk => ps2_keyboard_clk_in, ps2_data => ps2_keyboard_dat_in, ps2_mouse_clk => 'Z', ps2_mouse_data => 'Z', ERSTn => ERSTn, red => r, green => g, blue => b, vsync => VGA_VS_O, hsync => VGA_HS_O, Phi2 => open, RamCE => RamCE, RomCE => RomCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout=> ExternDout, audiol => AUDIO_L, audioR => AUDIO_R, SDMISO => sd_sdo, SDSS => sd_cs, SDCLK => sd_sck, SDMOSI => sd_sdi, uart_RxD => 'Z', uart_TxD => txd, LED1 => open, --LED1, LED2 => open --LED2 ); osd_inst : osd port map ( pclk => clk_osd, sdi => SPI_DI, sck => SPI_SCK, ss => SPI_SS3, red_in => r & r, green_in => g &g, blue_in => b & b, hs_in => VGA_HS_O, vs_in => VGA_VS_O, scanline_ena_h => '0', red_out => VGA_R, green_out => VGA_G, blue_out => VGA_B, hs_out => VGA_HS, vs_out => VGA_VS ); -- MiST SDRAM_nCAS <= '1'; -- disable sdram user_io_d : user_io generic map (STRLEN => CONF_STR'length) port map ( SPI_CLK => SPI_SCK, SPI_SS_IO => CONF_DATA0, SPI_MISO => SPI_DO, SPI_MOSI => SPI_DI, conf_str => to_slv(CONF_STR), status => status, -- connection to io controller sd_lba => sd_lba, sd_rd => sd_rd, sd_wr => sd_wr, sd_ack => sd_ack, sd_sdhc => sd_sdhc, sd_conf => sd_conf, sd_dout => sd_data_in, sd_dout_strobe => sd_data_in_strobe, sd_din => sd_data_out, sd_din_strobe => sd_data_out_strobe, joystick_0 => joy_0, joystick_1 => joy_1, joystick_analog_0 => joy_ana_0, joystick_analog_1 => joy_ana_1, -- switches => switches, BUTTONS => buttons, ps2_clk => clk12k, ps2_kbd_clk => ps2_keyboard_clk_in, ps2_kbd_data => ps2_keyboard_dat_in, ps2_mouse_clk => ps2_mouse_clk_in, ps2_mouse_data => ps2_mouse_dat_in, serial_data => par_out_data, serial_strobe => par_out_strobe ); mist_console_d: component mist_console generic map ( CLKFREQ => 32) port map ( clk => clk_32M00, n_reset => ERSTn, ser_in => txd, par_out_data => par_out_data, par_out_strobe => par_out_strobe ); sd_card_d: component sd_card port map ( -- connection to io controller io_lba => sd_lba, io_rd => sd_rd, io_wr => sd_wr, io_ack => sd_ack, io_conf => sd_conf, io_sdhc => sd_sdhc, io_din => sd_data_in, io_din_strobe => sd_data_in_strobe, io_dout => sd_data_out, io_dout_strobe => sd_data_out_strobe, allow_sdhc => '1', -- connection to host sd_cs => sd_cs, sd_sck => sd_sck, sd_sdi => sd_sdi, sd_sdo => sd_sdo ); end behavioral;
apache-2.0
71d5dbbae09d6006d09cbb5d98d70fdd
0.488366
3.515361
false
false
false
false
grwlf/vsim
vhdl/resolver2.vhd
1
619
entity test is end entity test; architecture test_arch of test is -- constant size : integer := 16#10000#; constant size : integer := 2; type vector_t is array (0 to size-1) of bit; signal big_vector : vector_t; signal clk : integer := 0; begin main: process(clk) variable vbit : bit := '1'; begin for i in 0 to clk-1 loop big_vector(i) <= '1'; if False then big_vector(i) <= not big_vector(i); end if; end loop; assert false report "end of simulation" severity failure; end process; clk <= (clk + 1) after 1 us; end architecture test_arch;
gpl-3.0
666758c1bc3058d1f5f7dc53783c64be
0.610662
3.31016
false
true
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4.vhd
4
2,896
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is port ( clk: in std_logic; ce: in std_logic; a: in std_logic_vector(8 - 1 downto 0); b: in std_logic_vector(6 - 1 downto 0); p: out std_logic_vector(14 - 1 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is signal tmp_product : std_logic_vector(14 - 1 downto 0); signal a_i : std_logic_vector(8 - 1 downto 0); signal b_i : std_logic_vector(6 - 1 downto 0); signal p_tmp : std_logic_vector(14 - 1 downto 0); signal a_reg : std_logic_vector(8 - 1 downto 0); signal b_reg : std_logic_vector(6 - 1 downto 0); attribute keep : string; attribute keep of a_i : signal is "true"; attribute keep of b_i : signal is "true"; signal buff0 : std_logic_vector(14 - 1 downto 0); signal buff1 : std_logic_vector(14 - 1 downto 0); begin a_i <= a; b_i <= b; p <= p_tmp; p_tmp <= buff1; tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14)); process(clk) begin if (clk'event and clk = '1') then if (ce = '1') then a_reg <= a_i; b_reg <= b_i; buff0 <= tmp_product; buff1 <= buff0; end if; end if; end process; end architecture; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 is port ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; p : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MulnS_1 port map ( clk => clk, ce => ce, a => din0, b => din1, p => dout); end architecture;
lgpl-3.0
da358ccff77327a95bf14e02744069b0
0.559047
3.217778
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2/_primary.vhd
1
1,039
library verilog; use verilog.vl_types.all; entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is generic( ID : integer := 1; NUM_STAGE : integer := 1; din0_WIDTH : integer := 1; din1_WIDTH : integer := 1; dout_WIDTH : integer := 1 ); port( clk : in vl_logic; reset : in vl_logic; ce : in vl_logic; din0 : in vl_logic_vector; din1 : in vl_logic_vector; dout : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ID : constant is 1; attribute mti_svvh_generic_type of NUM_STAGE : constant is 1; attribute mti_svvh_generic_type of din0_WIDTH : constant is 1; attribute mti_svvh_generic_type of din1_WIDTH : constant is 1; attribute mti_svvh_generic_type of dout_WIDTH : constant is 1; end nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2;
lgpl-3.0
08c38da63f42e4b306a1808d3b6990b0
0.551492
3.558219
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/frontend/r2p_CordicPipe.vhd
1
3,882
-- -- file: r2p_CordicPipe.vhd -- author: Richard Herveille -- rev. 1.0 initial release -- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now -- rev. 1.2 May 18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request). -- rev. 1.3 June 4th, 2001. Richard Herveille. Revised design (made it simpler and easier to understand). library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity r2p_CordicPipe is generic( WIDTH : natural := 16; PIPEID : natural := 1 ); port( clk : in std_logic; ena : in std_logic; Xi : in signed(WIDTH -1 downto 0); Yi : in signed(WIDTH -1 downto 0); Zi : in signed(19 downto 0); Xo : out signed(WIDTH -1 downto 0); Yo : out signed(WIDTH -1 downto 0); Zo : out signed(19 downto 0) ); end entity r2p_CordicPipe; architecture dataflow of r2p_CordicPipe is -- -- functions -- -- Function CATAN (constante arc-tangent). -- This is a lookup table containing pre-calculated arc-tangents. -- 'n' is the number of the pipe, returned is a 20bit arc-tangent value. -- The numbers are calculated as follows: Z(n) = atan(1/2^n) -- examples: -- 20bit values => 2^20 = 2pi(rad) -- 1(rad) = 2^20/2pi = 166886.053.... -- n:1, atan(1/2) = 0.4636...(rad) -- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex) -- n:2, atan(1/4) = 0.2449...(rad) -- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex) -- n:3, atan(1/8) = 0.1243...(rad) -- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex) -- function CATAN(n :natural) return integer is variable result :integer; begin case n is when 0 => result := 16#020000#; when 1 => result := 16#012E40#; when 2 => result := 16#09FB4#; when 3 => result := 16#05111#; when 4 => result := 16#028B1#; when 5 => result := 16#0145D#; when 6 => result := 16#0A2F#; when 7 => result := 16#0518#; when 8 => result := 16#028C#; when 9 => result := 16#0146#; when 10 => result := 16#0A3#; when 11 => result := 16#051#; when 12 => result := 16#029#; when 13 => result := 16#014#; when 14 => result := 16#0A#; when 15 => result := 16#05#; when 16 => result := 16#03#; when 17 => result := 16#01#; when others => result := 16#0#; end case; return result; end CATAN; -- function Delta is actually an arithmatic shift right -- This strange construction is needed for compatibility with Xilinx WebPack function Delta(Arg : signed; Cnt : natural) return signed is variable tmp : signed(Arg'range); constant lo : integer := Arg'high -cnt +1; begin for n in Arg'high downto lo loop tmp(n) := Arg(Arg'high); end loop; for n in Arg'high -cnt downto 0 loop tmp(n) := Arg(n +cnt); end loop; return tmp; end function Delta; function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is begin if (add_sub = '1') then return dataa + datab; else return dataa - datab; end if; end; -- -- ARCHITECTURE BODY -- signal dX, Xresult : signed(WIDTH -1 downto 0); signal dY, Yresult : signed(WIDTH -1 downto 0); signal atan, Zresult : signed(19 downto 0); signal Yneg, Ypos : std_logic; begin dX <= Delta(Xi, PIPEID); dY <= Delta(Yi, PIPEID); atan <= conv_signed( catan(PIPEID), 20); -- Angle can not be negative, catan never returns a negative value, so conv_signed can be used -- generate adder structures Yneg <= Yi(WIDTH -1); Ypos <= not Yi(WIDTH -1); -- xadd Xresult <= AddSub(Xi, dY, YPos); -- yadd Yresult <= AddSub(Yi, dX, Yneg); -- zadd Zresult <= AddSub(Zi, atan, Ypos); gen_regs: process(clk) begin if(clk'event and clk='1') then if (ena = '1') then Xo <= Xresult; Yo <= Yresult; Zo <= Zresult; end if; end if; end process; end architecture dataflow;
apache-2.0
cd49beefa2b3fad2c8e1be2faeda541b
0.624936
2.806941
false
false
false
false
wsoltys/AtomFpga
src/i82C55/i82c55.vhd
1
2,880
--------------------------------------------------- -- Alan Daly 2009(c) -- AtomIC project -- minimal implementation of an 8255 -- just enough for the machine to function --------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity I82C55 is port ( I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 O_DATA : out std_logic_vector(7 downto 0); CS_H : in std_logic; WR_L : in std_logic; O_PA : out std_logic_vector(7 downto 0); I_PB : in std_logic_vector(7 downto 0); I_PC : in std_logic_vector(3 downto 0); O_PC : out std_logic_vector(3 downto 0); RESET : in std_logic; ENA : in std_logic; -- (CPU) clk enable CLK : in std_logic); end; architecture RTL of I82C55 is -- registers signal r_porta : std_logic_vector(7 downto 0); signal r_portb : std_logic_vector(7 downto 0); signal l_portc : std_logic_vector(3 downto 0); signal h_portc : std_logic_vector(3 downto 0); signal ctrl_reg : std_logic_vector(7 downto 0); begin p_write_reg_reset : process(RESET, CLK) begin if (RESET = '0') then r_porta <= x"00"; r_portb <= x"00"; l_portc <= x"0"; h_portc <= x"0"; ctrl_reg <= x"00"; elsif rising_edge(CLK) then O_PA <= r_porta; r_portb <= I_PB; h_portc <= I_PC; O_PC <= l_portc; if (CS_H = '1') then if (WR_L = '0') then case I_ADDR is when "00" => r_porta <= I_DATA; --when "01" => r_portb <= I_DATA; when "10" => l_portc <= I_DATA (3 downto 0); when "11" => if (I_DATA(7) = '0') then -- set/clr l_portc(2) <= I_DATA(0); else ctrl_reg <= I_DATA; end if; when others => null; end case; else -- read ports case I_ADDR is when "00" => O_DATA <= r_porta; when "01" => O_DATA <= r_portb; when "10" => O_DATA <= h_portc & l_portc; when "11" => O_DATA <= ctrl_reg; when others => null; end case; end if; end if; end if; end process; end architecture RTL;
apache-2.0
e8edd9c68915b96e82cc52aa7bdd9ba4
0.404167
3.819629
false
false
false
false
grwlf/vsim
vhdl_ct/ct00366.vhd
1
14,635
-- NEED RESULT: ARCH00366.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00366.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00366.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00366 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00366(ARCH00366) -- ENT00366_Test_Bench(ARCH00366_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00366 is port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00366 ; -- -- architecture ARCH00366 of ENT00366 is subtype chk_time_type is Time ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_rec2_vector_savt : chk_time_type := 0 ns ; signal s_st_rec3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_rec1_vector_select : select_type := 1 ; signal st_rec2_vector_select : select_type := 1 ; signal st_rec3_vector_select : select_type := 1 ; -- begin CHG1 : process ( s_st_rec1_vector ) variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(lowb).f2 <= transport -- c_st_rec1_vector_2(lowb).f2 after 10 ns, -- c_st_rec1_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00366.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(lowb).f2 <= transport -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(lowb).f2 <= transport -- c_st_rec1_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00366" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(lowb).f2 after 10 ns, c_st_rec1_vector_1(lowb).f2 after 20 ns when st_rec1_vector_select = 1 else -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when st_rec1_vector_select = 2 else -- c_st_rec1_vector_1(lowb).f2 after 5 ns ; -- CHG2 : process ( s_st_rec2_vector ) variable correct : boolean ; begin case s_st_rec2_vector_cnt is when 0 => null ; -- s_st_rec2_vector(lowb).f2 <= transport -- c_st_rec2_vector_2(lowb).f2 after 10 ns, -- c_st_rec2_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00366.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_vector_select <= transport 2 ; -- s_st_rec2_vector(lowb).f2 <= transport -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; st_rec2_vector_select <= transport 3 ; -- s_st_rec2_vector(lowb).f2 <= transport -- c_st_rec2_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00366" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec2_vector_savt <= transport Std.Standard.Now ; chk_st_rec2_vector <= transport s_st_rec2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(lowb).f2 after 10 ns, c_st_rec2_vector_1(lowb).f2 after 20 ns when st_rec2_vector_select = 1 else -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when st_rec2_vector_select = 2 else -- c_st_rec2_vector_1(lowb).f2 after 5 ns ; -- CHG3 : process ( s_st_rec3_vector ) variable correct : boolean ; begin case s_st_rec3_vector_cnt is when 0 => null ; -- s_st_rec3_vector(highb).f3 <= transport -- c_st_rec3_vector_2(highb).f3 after 10 ns, -- c_st_rec3_vector_1(highb).f3 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00366.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_vector_select <= transport 2 ; -- s_st_rec3_vector(highb).f3 <= transport -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; st_rec3_vector_select <= transport 3 ; -- s_st_rec3_vector(highb).f3 <= transport -- c_st_rec3_vector_1(highb).f3 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00366" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00366" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec3_vector_savt <= transport Std.Standard.Now ; chk_st_rec3_vector <= transport s_st_rec3_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_rec3_vector(highb).f3 <= transport c_st_rec3_vector_2(highb).f3 after 10 ns, c_st_rec3_vector_1(highb).f3 after 20 ns when st_rec3_vector_select = 1 else -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when st_rec3_vector_select = 2 else -- c_st_rec3_vector_1(highb).f3 after 5 ns ; -- end ARCH00366 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00366_Test_Bench is signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- end ENT00366_Test_Bench ; -- -- architecture ARCH00366_Test_Bench of ENT00366_Test_Bench is begin L1: block component UUT port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00366 ( ARCH00366 ) ; begin CIS1 : UUT port map ( s_st_rec1_vector , s_st_rec2_vector , s_st_rec3_vector ) ; end block L1 ; end ARCH00366_Test_Bench ;
gpl-3.0
85b48591e48bc04ca966fcbf873080ad
0.521285
3.271122
false
true
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_get_initials.vhd
3
13,072
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_get_initials is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_get_initials is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal nfa_initials_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_117 : BOOLEAN; signal ap_sig_bdd_119 : BOOLEAN; signal ap_sig_bdd_116 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it0_preg assign process. -- ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then ap_reg_ppiten_pp0_it0_preg <= ap_start; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then nfa_initials_buckets_read_reg_55 <= nfa_initials_buckets_datain; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_initials_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; end if; when ap_ST_pp0_stg1_fsm_1 => if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; end if; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_initials_buckets_rsp_empty_n, ap_ce) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg) begin if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then ap_reg_ppiten_pp0_it0 <= ap_start; else ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg; end if; end process; ap_return_0 <= nfa_initials_buckets_read_reg_55; ap_return_1 <= nfa_initials_buckets_datain; -- ap_sig_bdd_116 assign process. -- ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce) begin ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_117 assign process. -- ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n) begin ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))); end process; -- ap_sig_bdd_119 assign process. -- ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_initials_buckets_rsp_empty_n) begin ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- nfa_initials_buckets_address assign process. -- nfa_initials_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116) begin if (ap_sig_bdd_116) then if (ap_sig_bdd_119) then nfa_initials_buckets_address <= ap_const_lv32_1; elsif (ap_sig_bdd_117) then nfa_initials_buckets_address <= ap_const_lv32_0; else nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_initials_buckets_dataout <= ap_const_lv32_0; nfa_initials_buckets_req_din <= ap_const_logic_0; -- nfa_initials_buckets_req_write assign process. -- nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_initials_buckets_req_write <= ap_const_logic_1; else nfa_initials_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_initials_buckets_rsp_read assign process. -- nfa_initials_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_initials_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_initials_buckets_rsp_read <= ap_const_logic_1; else nfa_initials_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_initials_buckets_size <= ap_const_lv32_1; end behav;
lgpl-3.0
9b7f32fcb34b2092c1cb10a2fff5d4dd
0.599449
2.722199
false
false
false
false
jairov4/accel-oil
solution_kintex7/sim/vhdl/sample_iterator_get_offset.vhd
1
30,918
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal i_sample_read_reg_131 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_131_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal indices_begin_addr_reg_136 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_148 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_163 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_8_cast_fu_122_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_116_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_116_p0, din1 => grp_fu_116_p1, ce => grp_fu_116_ce, dout => grp_fu_116_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_131_pp0_it1 <= i_sample_read_reg_131; ap_reg_ppstg_i_sample_read_reg_131_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it1; ap_reg_ppstg_i_sample_read_reg_131_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it2; ap_reg_ppstg_i_sample_read_reg_131_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it3; ap_reg_ppstg_i_sample_read_reg_131_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_131_pp0_it4; ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(0) <= indices_begin_addr_reg_136(0); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(1) <= indices_begin_addr_reg_136(1); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(2) <= indices_begin_addr_reg_136(2); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(3) <= indices_begin_addr_reg_136(3); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(4) <= indices_begin_addr_reg_136(4); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(5) <= indices_begin_addr_reg_136(5); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(6) <= indices_begin_addr_reg_136(6); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(7) <= indices_begin_addr_reg_136(7); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(8) <= indices_begin_addr_reg_136(8); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(9) <= indices_begin_addr_reg_136(9); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(10) <= indices_begin_addr_reg_136(10); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(11) <= indices_begin_addr_reg_136(11); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(12) <= indices_begin_addr_reg_136(12); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(13) <= indices_begin_addr_reg_136(13); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(14) <= indices_begin_addr_reg_136(14); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(15) <= indices_begin_addr_reg_136(15); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(0); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(1); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(2); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(3); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(4); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(5); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(6); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(7); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(8); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(9); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(10); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(11); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(12); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(13); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(14); ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_131 <= i_sample; indices_begin_addr_reg_136(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0); indices_begin_addr_reg_136(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1); indices_begin_addr_reg_136(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2); indices_begin_addr_reg_136(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3); indices_begin_addr_reg_136(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4); indices_begin_addr_reg_136(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5); indices_begin_addr_reg_136(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6); indices_begin_addr_reg_136(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7); indices_begin_addr_reg_136(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8); indices_begin_addr_reg_136(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9); indices_begin_addr_reg_136(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10); indices_begin_addr_reg_136(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11); indices_begin_addr_reg_136(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12); indices_begin_addr_reg_136(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13); indices_begin_addr_reg_136(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14); indices_begin_addr_reg_136(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_163 <= indices_begin_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_148 <= indices_stride_datain; end if; end if; end process; indices_begin_addr_reg_136(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it8 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= std_logic_vector(unsigned(tmp_8_cast_fu_122_p1) + unsigned(indices_begin_addr_read_reg_163)); -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_116_ce assign process. -- grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_116_ce <= ap_const_logic_1; else grp_fu_116_ce <= ap_const_logic_0; end if; end process; grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0); grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_131_pp0_it5),24)); grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0); grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_148),24)); indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_136_pp0_it2; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0); indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_8_cast_fu_122_p1 <= std_logic_vector(resize(unsigned(grp_fu_116_p2),32)); tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64)); end behav;
lgpl-3.0
8e48410f0aaa9be86a9c467bf67aaf0e
0.621935
2.650266
false
false
false
false
jairov4/accel-oil
solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw.vhd
1
88,223
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_req_din : OUT STD_LOGIC; sample_buffer_req_full_n : IN STD_LOGIC; sample_buffer_req_write : OUT STD_LOGIC; sample_buffer_rsp_empty_n : IN STD_LOGIC; sample_buffer_rsp_read : OUT STD_LOGIC; sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_size : IN STD_LOGIC_VECTOR (15 downto 0); begin_index : IN STD_LOGIC_VECTOR (15 downto 0); begin_sample : IN STD_LOGIC_VECTOR (15 downto 0); end_index : IN STD_LOGIC_VECTOR (15 downto 0); end_sample : IN STD_LOGIC_VECTOR (15 downto 0); stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0); accept : IN STD_LOGIC_VECTOR (0 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_accept_samples_generic_hw is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc6slx9ftg256-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.000000,HLS_SYN_LAT=129180014,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_315 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_reg_320 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_fu_240_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_reg_325 : STD_LOGIC_VECTOR (0 downto 0); signal c_load_reg_329 : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_return : STD_LOGIC_VECTOR (31 downto 0); signal offset_reg_335 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal r_reg_340 : STD_LOGIC_VECTOR (0 downto 0); signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC; signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_345 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_251_p2 : STD_LOGIC_VECTOR (31 downto 0); signal c_1_reg_349 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_tmp_36 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_start : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_done : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_idle : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_ready : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_ce : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_length : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_start : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_done : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_idle : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_ready : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_ap_ce : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0); signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0); signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_sample_iterator_next_fu_211_ap_start_ap_start_reg : STD_LOGIC := '0'; signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_ce : STD_LOGIC; component nfa_accept_sample IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); tmp_36 : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component sample_iterator_get_offset IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sample_iterator_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_nfa_accept_sample_fu_178 : component nfa_accept_sample port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_accept_sample_fu_178_ap_start, ap_done => grp_nfa_accept_sample_fu_178_ap_done, ap_idle => grp_nfa_accept_sample_fu_178_ap_idle, ap_ready => grp_nfa_accept_sample_fu_178_ap_ready, nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size, nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size, nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din, nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n, nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write, nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n, nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read, nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address, nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain, nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout, nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size, nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols, sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din, sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n, sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write, sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n, sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read, sample_address => grp_nfa_accept_sample_fu_178_sample_address, sample_datain => grp_nfa_accept_sample_fu_178_sample_datain, sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout, sample_size => grp_nfa_accept_sample_fu_178_sample_size, tmp_36 => grp_nfa_accept_sample_fu_178_tmp_36, length_r => grp_nfa_accept_sample_fu_178_length_r, ap_return => grp_nfa_accept_sample_fu_178_ap_return); grp_sample_iterator_get_offset_fu_194 : component sample_iterator_get_offset port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_get_offset_fu_194_ap_start, ap_done => grp_sample_iterator_get_offset_fu_194_ap_done, ap_idle => grp_sample_iterator_get_offset_fu_194_ap_idle, ap_ready => grp_sample_iterator_get_offset_fu_194_ap_ready, indices_stride_req_din => grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_get_offset_fu_194_indices_stride_address, indices_stride_datain => grp_sample_iterator_get_offset_fu_194_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, indices_stride_size => grp_sample_iterator_get_offset_fu_194_indices_stride_size, indices_begin_req_din => grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_get_offset_fu_194_indices_begin_address, indices_begin_datain => grp_sample_iterator_get_offset_fu_194_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, indices_begin_size => grp_sample_iterator_get_offset_fu_194_indices_begin_size, ap_ce => grp_sample_iterator_get_offset_fu_194_ap_ce, i_index => grp_sample_iterator_get_offset_fu_194_i_index, i_sample => grp_sample_iterator_get_offset_fu_194_i_sample, indices_samples_req_din => grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_get_offset_fu_194_indices_samples_address, indices_samples_datain => grp_sample_iterator_get_offset_fu_194_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, indices_samples_size => grp_sample_iterator_get_offset_fu_194_indices_samples_size, sample_buffer_size => grp_sample_iterator_get_offset_fu_194_sample_buffer_size, sample_length => grp_sample_iterator_get_offset_fu_194_sample_length, ap_return => grp_sample_iterator_get_offset_fu_194_ap_return); grp_sample_iterator_next_fu_211 : component sample_iterator_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_next_fu_211_ap_start, ap_done => grp_sample_iterator_next_fu_211_ap_done, ap_idle => grp_sample_iterator_next_fu_211_ap_idle, ap_ready => grp_sample_iterator_next_fu_211_ap_ready, indices_samples_req_din => grp_sample_iterator_next_fu_211_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_next_fu_211_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_next_fu_211_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_next_fu_211_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_next_fu_211_indices_samples_address, indices_samples_datain => grp_sample_iterator_next_fu_211_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_next_fu_211_indices_samples_dataout, indices_samples_size => grp_sample_iterator_next_fu_211_indices_samples_size, ap_ce => grp_sample_iterator_next_fu_211_ap_ce, indices_begin_req_din => grp_sample_iterator_next_fu_211_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_next_fu_211_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_next_fu_211_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_next_fu_211_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_next_fu_211_indices_begin_address, indices_begin_datain => grp_sample_iterator_next_fu_211_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_next_fu_211_indices_begin_dataout, indices_begin_size => grp_sample_iterator_next_fu_211_indices_begin_size, indices_stride_req_din => grp_sample_iterator_next_fu_211_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_next_fu_211_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_next_fu_211_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_next_fu_211_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_next_fu_211_indices_stride_address, indices_stride_datain => grp_sample_iterator_next_fu_211_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_next_fu_211_indices_stride_dataout, indices_stride_size => grp_sample_iterator_next_fu_211_indices_stride_size, i_index => grp_sample_iterator_next_fu_211_i_index, i_sample => grp_sample_iterator_next_fu_211_i_sample, ap_return_0 => grp_sample_iterator_next_fu_211_ap_return_0, ap_return_1 => grp_sample_iterator_next_fu_211_ap_return_1); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 38, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_251_p0, din1 => grp_fu_251_p1, ce => grp_fu_251_ce, dout => grp_fu_251_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; else if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg assign process. -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_240_p2 = ap_const_lv1_0))) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_194_ap_ready)) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg assign process. -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st31_fsm_30 = ap_NS_fsm) and ((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm)))) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_211_ap_ready)) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- c_fu_94 assign process. -- c_fu_94_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st31_fsm_30 = ap_CS_fsm) and (or_cond_reg_345 = ap_const_lv1_0))) then c_fu_94 <= c_1_reg_349; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then c_fu_94 <= ap_const_lv32_0; end if; end if; end process; -- i_index_reg_146 assign process. -- i_index_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then i_index_reg_146 <= grp_sample_iterator_next_fu_211_ap_return_0; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_index_reg_146 <= begin_index; end if; end if; end process; -- i_sample_reg_156 assign process. -- i_sample_reg_156_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then i_sample_reg_156 <= grp_sample_iterator_next_fu_211_ap_return_1; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_sample_reg_156 <= begin_sample; end if; end if; end process; -- p_0_reg_166 assign process. -- p_0_reg_166_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st23_fsm_22 = ap_CS_fsm) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then p_0_reg_166 <= ap_const_lv32_1; elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_325 = ap_const_lv1_0)))) then p_0_reg_166 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then c_1_reg_349 <= grp_fu_251_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then c_load_reg_329 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then offset_reg_335 <= grp_sample_iterator_get_offset_fu_194_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then or_cond_reg_345 <= or_cond_fu_247_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then r_reg_340 <= grp_nfa_accept_sample_fu_178_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then tmp_i_10_reg_320 <= tmp_i_10_fu_235_p2; tmp_i_reg_315 <= tmp_i_fu_230_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then tmp_i_11_reg_325 <= tmp_i_11_fu_240_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , tmp_i_11_reg_325 , grp_nfa_accept_sample_fu_178_ap_done , or_cond_fu_247_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => if (not((tmp_i_11_reg_325 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st43_fsm_42; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done))) then ap_NS_fsm <= ap_ST_st23_fsm_22; else ap_NS_fsm <= ap_ST_st22_fsm_21; end if; when ap_ST_st23_fsm_22 => if ((not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st43_fsm_42; elsif (((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st24_fsm_23; else ap_NS_fsm <= ap_ST_st31_fsm_30; end if; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st2_fsm_1; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= p_0_reg_166; grp_fu_251_ce <= ap_const_logic_1; grp_fu_251_p0 <= c_load_reg_329; grp_fu_251_p1 <= ap_const_lv32_1; grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg; grp_nfa_accept_sample_fu_178_length_r <= sample_length; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols; grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain; grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n; grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n; grp_nfa_accept_sample_fu_178_tmp_36 <= offset_reg_335; grp_sample_iterator_get_offset_fu_194_ap_ce <= ap_const_logic_1; grp_sample_iterator_get_offset_fu_194_ap_start <= grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg; grp_sample_iterator_get_offset_fu_194_i_index <= i_index_reg_146; grp_sample_iterator_get_offset_fu_194_i_sample <= i_sample_reg_156; grp_sample_iterator_get_offset_fu_194_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_sample_buffer_size <= sample_buffer_length; grp_sample_iterator_get_offset_fu_194_sample_length <= sample_length; grp_sample_iterator_next_fu_211_ap_ce <= ap_const_logic_1; grp_sample_iterator_next_fu_211_ap_start <= grp_sample_iterator_next_fu_211_ap_start_ap_start_reg; grp_sample_iterator_next_fu_211_i_index <= i_index_reg_146; grp_sample_iterator_next_fu_211_i_sample <= i_sample_reg_156; grp_sample_iterator_next_fu_211_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_next_fu_211_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_next_fu_211_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_next_fu_211_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; -- indices_begin_address assign process. -- indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_address, grp_sample_iterator_next_fu_211_indices_begin_address) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_next_fu_211_indices_begin_address; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_get_offset_fu_194_indices_begin_address; else indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_dataout assign process. -- indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, grp_sample_iterator_next_fu_211_indices_begin_dataout) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_next_fu_211_indices_begin_dataout; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_get_offset_fu_194_indices_begin_dataout; else indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_req_din assign process. -- indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, grp_sample_iterator_next_fu_211_indices_begin_req_din) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_next_fu_211_indices_begin_req_din; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_din; else indices_begin_req_din <= 'X'; end if; end process; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, grp_sample_iterator_next_fu_211_indices_begin_req_write) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_next_fu_211_indices_begin_req_write; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_write; else indices_begin_req_write <= 'X'; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, grp_sample_iterator_next_fu_211_indices_begin_rsp_read) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_next_fu_211_indices_begin_rsp_read; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read; else indices_begin_rsp_read <= 'X'; end if; end process; -- indices_begin_size assign process. -- indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_size, grp_sample_iterator_next_fu_211_indices_begin_size) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_next_fu_211_indices_begin_size; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_get_offset_fu_194_indices_begin_size; else indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_address assign process. -- indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_address, grp_sample_iterator_next_fu_211_indices_samples_address) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_next_fu_211_indices_samples_address; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_get_offset_fu_194_indices_samples_address; else indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_dataout assign process. -- indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, grp_sample_iterator_next_fu_211_indices_samples_dataout) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_next_fu_211_indices_samples_dataout; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_get_offset_fu_194_indices_samples_dataout; else indices_samples_dataout <= "XXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_req_din assign process. -- indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, grp_sample_iterator_next_fu_211_indices_samples_req_din) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_next_fu_211_indices_samples_req_din; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_din; else indices_samples_req_din <= 'X'; end if; end process; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, grp_sample_iterator_next_fu_211_indices_samples_req_write) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_next_fu_211_indices_samples_req_write; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_write; else indices_samples_req_write <= 'X'; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, grp_sample_iterator_next_fu_211_indices_samples_rsp_read) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_next_fu_211_indices_samples_rsp_read; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read; else indices_samples_rsp_read <= 'X'; end if; end process; -- indices_samples_size assign process. -- indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_size, grp_sample_iterator_next_fu_211_indices_samples_size) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_next_fu_211_indices_samples_size; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_get_offset_fu_194_indices_samples_size; else indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_address assign process. -- indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_address, grp_sample_iterator_next_fu_211_indices_stride_address) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_next_fu_211_indices_stride_address; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_get_offset_fu_194_indices_stride_address; else indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_dataout assign process. -- indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, grp_sample_iterator_next_fu_211_indices_stride_dataout) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_next_fu_211_indices_stride_dataout; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_get_offset_fu_194_indices_stride_dataout; else indices_stride_dataout <= "XXXXXXXX"; end if; end process; -- indices_stride_req_din assign process. -- indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, grp_sample_iterator_next_fu_211_indices_stride_req_din) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_next_fu_211_indices_stride_req_din; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_din; else indices_stride_req_din <= 'X'; end if; end process; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, grp_sample_iterator_next_fu_211_indices_stride_req_write) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_next_fu_211_indices_stride_req_write; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_write; else indices_stride_req_write <= 'X'; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, grp_sample_iterator_next_fu_211_indices_stride_rsp_read) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_next_fu_211_indices_stride_rsp_read; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read; else indices_stride_rsp_read <= 'X'; end if; end process; -- indices_stride_size assign process. -- indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_size, grp_sample_iterator_next_fu_211_indices_stride_size) begin if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_next_fu_211_indices_stride_size; elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_get_offset_fu_194_indices_stride_size; else indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size; nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address; nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout; nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din; nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write; nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read; nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size; nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size; or_cond_fu_247_p2 <= (r_reg_340 xor accept); sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address; sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout; sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din; sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write; sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read; sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size; stop_on_first_read_read_fu_104_p2 <= stop_on_first; tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0"; tmp_i_11_fu_240_p2 <= (tmp_i_reg_315 and tmp_i_10_reg_320); tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0"; end behav;
lgpl-3.0
ba3c94d832869bfa3462d86322f1f9b8
0.641839
2.630068
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/slv0_if.vhd
4
25,424
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library plbv46_slave_single_v1_01_a; use plbv46_slave_single_v1_01_a.plbv46_slave_single; entity slv0_if is generic ( C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 32; C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 3; C_SPLB_NATIVE_DWIDTH : integer := 32; C_SPLB_P2P : integer := 0; C_SPLB_SUPPORT_BURSTS : integer := 0; C_SPLB_SMALLEST_MASTER : integer := 32; C_SPLB_CLK_PERIOD_PS : integer := 10000; C_INCLUDE_DPHASE_TIMER : integer := 0; C_FAMILY : string := "virtex5" ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); -- DO NOT EDIT ABOVE THIS LINE --------------------- DOUT_nfa_symbols : out std_logic_vector(8-1 downto 0); DOUT_sample_buffer_length : out std_logic_vector(32-1 downto 0); DOUT_sample_length : out std_logic_vector(16-1 downto 0); DOUT_i_size : out std_logic_vector(16-1 downto 0); DOUT_begin_index : out std_logic_vector(16-1 downto 0); DOUT_begin_sample : out std_logic_vector(16-1 downto 0); DOUT_end_index : out std_logic_vector(16-1 downto 0); DOUT_end_sample : out std_logic_vector(16-1 downto 0); DOUT_stop_on_first : out std_logic_vector(1-1 downto 0); DOUT_accept : out std_logic_vector(1-1 downto 0); DOUT_ap_start : out std_logic; DIN_ap_ready : in std_logic; DIN_ap_done : in std_logic; DIN_ap_idle : in std_logic; DIN_ap_return : in std_logic_vector(32-1 downto 0) ); attribute SIGIS : string; attribute SIGIS of SPLB_Clk : signal is "CLK"; attribute SIGIS of SPLB_Rst : signal is "RST"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of slv0_if is ------------------------------------------ -- Array of base/high address pairs for each address range ------------------------------------------ constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); ------------------------------------------ -- Array of desired number of chip enables for each address range ------------------------------------------ constant USER_SLV_NUM_REG : integer := 15; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Ratio of bus clock to core clock (for use in dual clock systems) -- 1 = ratio is 1:1 -- 2 = ratio is 2:1 ------------------------------------------ constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; ------------------------------------------ -- Width of the slave data bus (non-burst slave support 32 only) ------------------------------------------ constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal iBus2IP_Clk : std_logic; signal iBus2IP_Reset : std_logic; signal iIP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal iIP2Bus_WrAck : std_logic; signal iIP2Bus_RdAck : std_logic; signal iIP2Bus_Error : std_logic; signal iBus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); signal iBus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal iBus2IP_RNW : std_logic; signal iBus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); signal iBus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; -- signals for user logic constant USER_DWIDTH : integer := USER_SLV_DWIDTH; constant USER_NUM_CE : integer := 15; signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1); signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1); signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1); signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1); signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1); -- signals for slave port nfa_symbols signal sig_nfa_symbols : std_logic_vector(32-1 downto 0); -- offset: 0 -- signals for slave port sample_buffer_length signal sig_sample_buffer_length : std_logic_vector(32-1 downto 0); -- offset: 1 -- signals for slave port sample_length signal sig_sample_length : std_logic_vector(32-1 downto 0); -- offset: 2 -- signals for slave port i_size signal sig_i_size : std_logic_vector(32-1 downto 0); -- offset: 3 -- signals for slave port begin_index signal sig_begin_index : std_logic_vector(32-1 downto 0); -- offset: 4 -- signals for slave port begin_sample signal sig_begin_sample : std_logic_vector(32-1 downto 0); -- offset: 5 -- signals for slave port end_index signal sig_end_index : std_logic_vector(32-1 downto 0); -- offset: 6 -- signals for slave port end_sample signal sig_end_sample : std_logic_vector(32-1 downto 0); -- offset: 7 -- signals for slave port stop_on_first signal sig_stop_on_first : std_logic_vector(32-1 downto 0); -- offset: 8 -- signals for slave port accept signal sig_accept : std_logic_vector(32-1 downto 0); -- offset: 9 -- signals for slave port ap_start signal sig_ap_start : std_logic; -- offset: 10 -- signals for slave port ap_ready signal sig_ap_ready : std_logic; -- offset: 11 -- signals for slave port ap_done signal sig_ap_done : std_logic; -- offset: 12 -- signals for slave port ap_idle signal sig_ap_idle : std_logic; -- offset: 13 -- signals for slave port ap_return signal sig_ap_return : std_logic_vector(32-1 downto 0); -- offset: 14 type mem_array is array (USER_NUM_REG-1 downto 0) of std_logic_vector (USER_DWIDTH-1 downto 0); signal slave_read_mem : mem_array; signal sig_ap_start_reg : std_logic; signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin ------------------------------------------ -- instantiate plbv46_slave_single ------------------------------------------ PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single generic map ( C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_SPLB_P2P => C_SPLB_P2P, C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, C_SPLB_AWIDTH => C_SPLB_AWIDTH, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, C_FAMILY => C_FAMILY ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Bus2IP_Clk => iBus2IP_Clk, Bus2IP_Reset => iBus2IP_Reset, IP2Bus_Data => iIP2Bus_Data, IP2Bus_WrAck => iIP2Bus_WrAck, IP2Bus_RdAck => iIP2Bus_RdAck, IP2Bus_Error => iIP2Bus_Error, Bus2IP_Addr => iBus2IP_Addr, Bus2IP_Data => iBus2IP_Data, Bus2IP_RNW => iBus2IP_RNW, Bus2IP_BE => iBus2IP_BE, Bus2IP_CS => iBus2IP_CS, Bus2IP_RdCE => iBus2IP_RdCE, Bus2IP_WrCE => iBus2IP_WrCE ); ------------------------------------------ -- hooking up signal slicing ------------------------------------------ uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1); uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1); uBus2IP_RdCE <= iBus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_CE-1); uBus2IP_WrCE <= iBus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_CE-1); iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data; slv_write_ack <= '1' when uBus2IP_WrCE /= CONV_STD_LOGIC_VECTOR(0,USER_NUM_CE) else '0'; slv_read_ack <= '1' when uBus2IP_RdCE /= CONV_STD_LOGIC_VECTOR(0,USER_NUM_CE) else '0'; iIP2Bus_WrAck <= slv_write_ack; iIP2Bus_RdAck <= slv_read_ack; iIP2Bus_Error <= '0'; -- data from slave_if to DUT DOUT_nfa_symbols <= sig_nfa_symbols(8-1 downto 0); DOUT_sample_buffer_length <= sig_sample_buffer_length(32-1 downto 0); DOUT_sample_length <= sig_sample_length(16-1 downto 0); DOUT_i_size <= sig_i_size(16-1 downto 0); DOUT_begin_index <= sig_begin_index(16-1 downto 0); DOUT_begin_sample <= sig_begin_sample(16-1 downto 0); DOUT_end_index <= sig_end_index(16-1 downto 0); DOUT_end_sample <= sig_end_sample(16-1 downto 0); DOUT_stop_on_first <= sig_stop_on_first(1-1 downto 0); DOUT_accept <= sig_accept(1-1 downto 0); DOUT_ap_start <= '1' when sig_ap_start = '1' and sig_ap_start_reg = '0' else '0'; -- implement slave model register read mux SLAVE_REG_REGULAR_PROC : process( sig_nfa_symbols,sig_sample_buffer_length,sig_sample_length,sig_i_size,sig_begin_index, sig_begin_sample,sig_end_index,sig_end_sample,sig_stop_on_first,sig_accept, sig_ap_start,sig_ap_ready,sig_ap_done,sig_ap_idle,sig_ap_return ) is begin slave_read_mem(0) <= sig_nfa_symbols(31 downto 0); slave_read_mem(1) <= sig_sample_buffer_length(31 downto 0); slave_read_mem(2) <= sig_sample_length(31 downto 0); slave_read_mem(3) <= sig_i_size(31 downto 0); slave_read_mem(4) <= sig_begin_index(31 downto 0); slave_read_mem(5) <= sig_begin_sample(31 downto 0); slave_read_mem(6) <= sig_end_index(31 downto 0); slave_read_mem(7) <= sig_end_sample(31 downto 0); slave_read_mem(8) <= sig_stop_on_first(31 downto 0); slave_read_mem(9) <= sig_accept(31 downto 0); slave_read_mem(10)(31 downto 1) <= (others => '0'); slave_read_mem(10)(0) <= sig_ap_start; slave_read_mem(11)(31 downto 1) <= (others => '0'); slave_read_mem(11)(0) <= sig_ap_ready; slave_read_mem(12)(31 downto 1) <= (others => '0'); slave_read_mem(12)(0) <= sig_ap_done; slave_read_mem(13)(31 downto 1) <= (others => '0'); slave_read_mem(13)(0) <= sig_ap_idle; slave_read_mem(14) <= sig_ap_return(31 downto 0); end process SLAVE_REG_REGULAR_PROC; SLAVE_REG_READ_PROC : process( uBus2IP_RdCE, slave_read_mem) is variable i : integer; begin uIP2Bus_Data <= (others => '0'); for i in 0 to USER_NUM_CE - 1 loop if (uBus2IP_RdCE(i) = '1') then uIP2Bus_Data <= slave_read_mem(i); exit; end if; end loop; end process SLAVE_REG_READ_PROC; -- implement slave model register(s) SLAVE_REG_WRITE_PROC : process( iBus2IP_Clk ) is variable i, hi, lo : integer; begin if iBus2IP_Clk'event and iBus2IP_Clk = '1' then -- slave_reg : nfa_symbols if iBus2IP_Reset = '1' then sig_nfa_symbols <= (others => '0'); else if (uBus2IP_WrCE(0) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_nfa_symbols(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : sample_buffer_length if iBus2IP_Reset = '1' then sig_sample_buffer_length <= (others => '0'); else if (uBus2IP_WrCE(1) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_sample_buffer_length(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : sample_length if iBus2IP_Reset = '1' then sig_sample_length <= (others => '0'); else if (uBus2IP_WrCE(2) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_sample_length(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : i_size if iBus2IP_Reset = '1' then sig_i_size <= (others => '0'); else if (uBus2IP_WrCE(3) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_i_size(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : begin_index if iBus2IP_Reset = '1' then sig_begin_index <= (others => '0'); else if (uBus2IP_WrCE(4) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_begin_index(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : begin_sample if iBus2IP_Reset = '1' then sig_begin_sample <= (others => '0'); else if (uBus2IP_WrCE(5) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_begin_sample(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : end_index if iBus2IP_Reset = '1' then sig_end_index <= (others => '0'); else if (uBus2IP_WrCE(6) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_end_index(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : end_sample if iBus2IP_Reset = '1' then sig_end_sample <= (others => '0'); else if (uBus2IP_WrCE(7) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_end_sample(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : stop_on_first if iBus2IP_Reset = '1' then sig_stop_on_first <= (others => '0'); else if (uBus2IP_WrCE(8) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_stop_on_first(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : accept if iBus2IP_Reset = '1' then sig_accept <= (others => '0'); else if (uBus2IP_WrCE(9) = '1') then for byte_index in 0 to USER_SLV_DWIDTH/8-1 loop if ( uBus2IP_BE(byte_index) = '1' ) then hi := (1-0)*USER_SLV_DWIDTH - byte_index*8 - 1; lo := hi - 7; sig_accept(hi downto lo) <= uBus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; end if; end if; -- slave_reg : ap_start if iBus2IP_Reset = '1' then sig_ap_start_reg <= '0'; sig_ap_start <= '0'; else sig_ap_start_reg <= sig_ap_start; if (uBus2IP_WrCE(10) = '1') then if ( uBus2IP_BE(USER_SLV_DWIDTH/8-1) = '1' ) then sig_ap_start <= uBus2IP_Data(USER_SLV_DWIDTH-1); end if; end if; end if; -- slave_reg : ap_ready if iBus2IP_Reset = '1' then sig_ap_ready <= '0'; else sig_ap_ready <= DIN_ap_ready ; end if; -- slave_reg : ap_done if iBus2IP_Reset = '1' then sig_ap_done <= '0'; else sig_ap_done <= DIN_ap_done ; end if; -- slave_reg : ap_idle if iBus2IP_Reset = '1' then sig_ap_idle <= '0'; else sig_ap_idle <= DIN_ap_idle ; end if; -- slave_reg : ap_return if iBus2IP_Reset = '1' then sig_ap_return <= (others => '0'); else sig_ap_return(32-1 downto 0) <= DIN_ap_return ; end if; end if; end process SLAVE_REG_WRITE_PROC; end IMP;
lgpl-3.0
be63e1fde3537fa191f5c73d63013c95
0.490285
3.559787
false
false
false
false
dcliche/mdsynth
rtl/src/sound/sinewave.vhd
1
6,275
-- MDSynth Sound Chip -- -- Copyright (c) 2012, Meldora Inc. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the -- following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, this list of conditions and the -- following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the -- following disclaimer in the documentation and/or other materials provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity sinewave is port ( clk: in std_logic; gain: in unsigned(5 downto 0); phase: in unsigned(7 downto 0); waveform: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0) data_out: out integer range -128 to 127); end sinewave; architecture Behavioral of sinewave is type log_sine_type is array (0 to 64) of integer range 0 to 511; type log_gain_type is array (0 to 63) of integer range 0 to 511; type exp_table_type is array (0 to 1023) of integer range -128 to 127; signal log_sine : log_sine_type := (511,237,193,167,149,134,123,113,105,97,91,85,79,74,70,65,61,58,54,51,48,45,43,40,38,35,33,31,29,27,25,24,22,21,19,18,16,15,14,13,12,11,10,9,8,7,6,6,5,4,4,3,3,2,2,2,1,1,1,0,0,0,0,0,0); signal log_gain : log_gain_type := (511,265,221,195,176,162,150,141,132,125,118,112,106,101,96,92,88,84,80,77,73,70,67,64,62,59,57,54,52,50,47,45,43,41,39,38,36,34,32,31,29,27,26,24,23,22,20,19,17,16,15,14,12,11,10,9,8,6,5,4,3,2,1,0); signal exp_table : exp_table_type := (127,125,123,121,119,117,116,114,112,110,109,107,105,104,102,100,99,97,96,94,93,91,90,89,87,86,85,83,82,81,79,78,77,76,75,74,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,55,54,53,52,51,51,50,49,48,47,47,46,45,45,44,43,43,42,41,41,40,39,39,38,38,37,36,36,35,35,34,34,33,33,32,32,31,31,30,30,29,29,28,28,27,27,27,26,26,25,25,25,24,24,23,23,23,22,22,22,21,21,21,20,20,20,19,19,19,19,18,18,18,17,17,17,17,16,16,16,16,15,15,15,15,14,14,14,14,14,13,13,13,13,13,12,12,12,12,12,11,11,11,11,11,11,10,10,10,10,10,10,9,9,9,9,9,9,9,9,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,7,6,6,6,6,6,6,6,6,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); begin process(clk) begin if (rising_edge(clk)) then if (phase <= 64) then data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase))); elsif (phase > 64 and phase <= 128) then if (waveform = "00" or waveform = "01" or waveform = "10") then data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 64))); else data_out <= 0; end if; elsif (phase > 128 and phase <= 192) then if (waveform = "00") then data_out <= -exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase) - 128)); elsif (waveform = "10" or waveform = "11") then data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase) - 128)); else data_out <= 0; end if; else -- phase > 192 and phase < 256 if (waveform = "00") then data_out <= -exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 192))); elsif (waveform = "10") then data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 192))); else data_out <= 0; end if; end if; end if; end process; end Behavioral;
gpl-3.0
ef96964765c82ff2a7cc090943bdc72c
0.594741
1.942724
false
false
false
false
grwlf/vsim
vhdl_ct/ct00407.vhd
1
22,517
-- NEED RESULT: ARCH00407.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00407.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00407.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00407: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00407 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.2 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00407(ARCH00407) -- ENT00407_Test_Bench(ARCH00407_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00407 is port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00407 ; -- -- architecture ARCH00407 of ENT00407 is subtype chk_time_type is Time ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_rec2_vector_savt : chk_time_type := 0 ns ; signal s_st_rec3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_rec1_vector_select : select_type := 1 ; signal st_rec2_vector_select : select_type := 1 ; signal st_rec3_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns, -- c_st_rec1_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 4 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 5 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; wait until (not s_st_rec1_vector(lowb).f2'Quiet) and (s_st_rec1_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(lowb).f2 <= c_st_rec1_vector_2(lowb).f2 after 10 ns, c_st_rec1_vector_1(lowb).f2 after 20 ns when 1, -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when 2, -- c_st_rec1_vector_1(lowb).f2 after 5 ns when 3, -- c_st_rec1_vector_1(lowb).f2 after 100 ns when 4, -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when 5, -- -- Last transaction above is marked c_st_rec1_vector_1(lowb).f2 after 40 ns when 6 ; -- CHG2 : process variable correct : boolean ; begin case s_st_rec2_vector_cnt is when 0 => null ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns, -- c_st_rec2_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_vector_select <= transport 2 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; st_rec2_vector_select <= transport 3 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 4 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 5 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_vector_savt <= transport Std.Standard.Now ; chk_st_rec2_vector <= transport s_st_rec2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ; wait until (not s_st_rec2_vector(lowb).f2'Quiet) and (s_st_rec2_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_rec2_vector_select select s_st_rec2_vector(lowb).f2 <= c_st_rec2_vector_2(lowb).f2 after 10 ns, c_st_rec2_vector_1(lowb).f2 after 20 ns when 1, -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when 2, -- c_st_rec2_vector_1(lowb).f2 after 5 ns when 3, -- c_st_rec2_vector_1(lowb).f2 after 100 ns when 4, -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when 5, -- -- Last transaction above is marked c_st_rec2_vector_1(lowb).f2 after 40 ns when 6 ; -- CHG3 : process variable correct : boolean ; begin case s_st_rec3_vector_cnt is when 0 => null ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns, -- c_st_rec3_vector_1(highb).f3 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_vector_select <= transport 2 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; st_rec3_vector_select <= transport 3 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 4 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 100 ns ; -- when 5 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 5 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 6 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 7 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00407" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_vector_savt <= transport Std.Standard.Now ; chk_st_rec3_vector <= transport s_st_rec3_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ; wait until (not s_st_rec3_vector(highb).f3'Quiet) and (s_st_rec3_vector_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_rec3_vector_select select s_st_rec3_vector(highb).f3 <= c_st_rec3_vector_2(highb).f3 after 10 ns, c_st_rec3_vector_1(highb).f3 after 20 ns when 1, -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when 2, -- c_st_rec3_vector_1(highb).f3 after 5 ns when 3, -- c_st_rec3_vector_1(highb).f3 after 100 ns when 4, -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when 5, -- -- Last transaction above is marked c_st_rec3_vector_1(highb).f3 after 40 ns when 6 ; -- end ARCH00407 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00407_Test_Bench is signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- end ENT00407_Test_Bench ; -- -- architecture ARCH00407_Test_Bench of ENT00407_Test_Bench is begin L1: block component UUT port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00407 ( ARCH00407 ) ; begin CIS1 : UUT port map ( s_st_rec1_vector , s_st_rec2_vector , s_st_rec3_vector ) ; end block L1 ; end ARCH00407_Test_Bench ;
gpl-3.0
5a2d61154b8a58d775e286e4db2c3b4a
0.506639
3.301129
false
false
false
false
TWW12/lzw
ip_repo/axi_compression_1.0/src/bram_4096_1/synth/bram_4096.vhd
5
14,430
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY bram_4096 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END bram_4096; ARCHITECTURE bram_4096_arch OF bram_4096 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_4096_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF bram_4096_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF bram_4096_arch : ARCHITECTURE IS "bram_4096,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF bram_4096_arch: ARCHITECTURE IS "bram_4096,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_4096.mif,C_" & "INIT_FILE=bram_4096.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DEPTH_B=" & "4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_" & "BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.3587 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "bram_4096.mif", C_INIT_FILE => "bram_4096.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 20, C_READ_WIDTH_A => 20, C_WRITE_DEPTH_A => 4096, C_READ_DEPTH_A => 4096, C_ADDRA_WIDTH => 12, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 20, C_READ_WIDTH_B => 20, C_WRITE_DEPTH_B => 4096, C_READ_DEPTH_B => 4096, C_ADDRB_WIDTH => 12, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "2", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.3587 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END bram_4096_arch;
unlicense
12d0ca6948e0bbdebc11fc22255bf80f
0.62571
3.01946
false
false
false
false
grwlf/vsim
vhdl_ct/pro000015.vhd
1
4,253
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00012_Test_Bench is end ENT00012_Test_Bench; architecture ARCH00012_Test_Bench of ENT00012_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); signal I_saa_d : std_array_array; subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b1_d : byte; signal b2 : byte2 := x"00"; signal b2_d : byte2; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); signal I_baa_d : bit_array_array; type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; signal I_sa_d : std_array; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal e_d : enum; signal ea : enum_array(0 to 3) := (others => a_v); signal ea_d : enum_array(0 to 3); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal r_d : rec; signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal ra_d : rec_array(0 to 3); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal bv_d : bit_vector(15 downto 0); signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; signal clk_d : std_ulogic; signal clk2_d : std_ulogic; begin clk_d <= clk'Delayed(500 ns); clk2_d <= clk2'Delayed(300 ns); bv_d <= bv'Delayed(4 us); ra_d <= ra'Delayed(0.3 us); r_d <= r'Delayed(0.2 us); ea_d <= ea'Delayed(0.1 us); e_d <= e'Delayed(50 ns); I_sa_d <= I_sa'Delayed(3 us); I_baa_d <= I_baa'Delayed(2 us); I_saa_d <= I_saa'Delayed(1 us); b1_d <= b1'Delayed(5 us); b2_d <= b2'Delayed(5 us); clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00012_Test_Bench ;
gpl-3.0
4b6a1d94718203e1a52a8d7779c64613
0.548319
2.420603
false
false
false
false
TWW12/lzw
ip_repo/axi_compression_1.0/src/bram_2048_0/synth/bram_2048_0.vhd
4
14,460
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY bram_2048_0 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END bram_2048_0; ARCHITECTURE bram_2048_0_arch OF bram_2048_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_0_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF bram_2048_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_0_arch : ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_0_arch: ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_0.mi" & "f,C_INIT_FILE=bram_2048_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" & "PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" & "_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "bram_2048_0.mif", C_INIT_FILE => "bram_2048_0.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 20, C_READ_WIDTH_A => 20, C_WRITE_DEPTH_A => 2048, C_READ_DEPTH_A => 2048, C_ADDRA_WIDTH => 11, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 20, C_READ_WIDTH_B => 20, C_WRITE_DEPTH_B => 2048, C_READ_DEPTH_B => 2048, C_ADDRB_WIDTH => 11, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "1", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END bram_2048_0_arch;
unlicense
b04ac115f7a7cad03e7e941f8167da66
0.62545
3.003115
false
false
false
false
wsoltys/AtomFpga
src/AVR8/CommonPacks/AVRuCPackage.vhd
1
10,809
-- ***************************************************************************************** -- AVR constants and type declarations -- Version 1.0A(Special version for the JTAG OCD) -- Modified 05.05.2004 -- Designed by Ruslan Lepetenok -- ***************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use WORK.SynthCtrlPack.all; package AVRuCPackage is -- Old package type ext_mux_din_type is array(0 to CExtMuxInSize-1) of std_logic_vector(7 downto 0); subtype ext_mux_en_type is std_logic_vector(0 to CExtMuxInSize-1); -- End of old package constant IOAdrWidth : positive := 16; type AVRIOAdr_Type is array(0 to 63) of std_logic_vector(IOAdrWidth-1 downto 0); constant CAVRIOAdr : AVRIOAdr_Type :=("0000000000000000","0000000000000001","0000000000000010","0000000000000011", "0000000000000100","0000000000000101","0000000000000110","0000000000000111", "0000000000001000","0000000000001001","0000000000001010","0000000000001011", "0000000000001100","0000000000001101","0000000000001110","0000000000001111", "0000000000010000","0000000000010001","0000000000010010","0000000000010011", "0000000000010100","0000000000010101","0000000000010110","0000000000010111", "0000000000011000","0000000000011001","0000000000011010","0000000000011011", "0000000000011100","0000000000011101","0000000000011110","0000000000011111", "0000000000100000","0000000000100001","0000000000100010","0000000000100011", "0000000000100100","0000000000100101","0000000000100110","0000000000100111", "0000000000101000","0000000000101001","0000000000101010","0000000000101011", "0000000000101100","0000000000101101","0000000000101110","0000000000101111", "0000000000110000","0000000000110001","0000000000110010","0000000000110011", "0000000000110100","0000000000110101","0000000000110110","0000000000110111", "0000000000111000","0000000000111001","0000000000111010","0000000000111011", "0000000000111100","0000000000111101","0000000000111110","0000000000111111"); -- I/O port addresses -- I/O register file constant RAMPZ_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3B#); constant SPL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3D#); constant SPH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3E#); constant SREG_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3F#); -- End of I/O register file -- UART constant UDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0C#); constant UBRR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#09#); constant USR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0B#); constant UCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0A#); -- End of UART -- Timer/Counter constant TCCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#33#); constant TCCR1A_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2F#); constant TCCR1B_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2E#); constant TCCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#25#); constant ASSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#30#); constant TIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#37#); constant TIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#36#); constant TCNT0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#32#); constant TCNT2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#24#); constant OCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#); constant OCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#23#); constant TCNT1H_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2D#); constant TCNT1L_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2C#); constant OCR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2B#); constant OCR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2A#); constant OCR1BH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#29#); constant OCR1BL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#28#); constant ICR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#27#); constant ICR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#26#); -- End of Timer/Counter -- Service module constant MCUCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#35#); constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#); constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#); constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#); constant MCUSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#34#); constant XDIV_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3C#); -- End of service module -- EEPROM constant EEARH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1F#); constant EEARL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1E#); constant EEDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1D#); constant EECR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1C#); -- End of EEPROM -- SPI constant SPDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0F#); constant SPSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0E#); constant SPCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0D#); -- End of SPI -- PORTA addresses constant PORTA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1B#); constant DDRA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1A#); constant PINA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#19#); -- PORTB addresses constant PORTB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#18#); constant DDRB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#17#); constant PINB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#16#); -- PORTC addresses constant PORTC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#15#); constant DDRC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#14#); constant PINC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#13#); -- PORTD addresses constant PORTD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#12#); constant DDRD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#11#); constant PIND_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#10#); -- PORTE addresses constant PORTE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#03#); constant DDRE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#02#); constant PINE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#01#); -- PORTF addresses constant PORTF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#); constant DDRF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#); constant PINF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#00#); -- ******************** Parallel port address table ************************************** constant CMaxNumOfPPort : positive := 6; type PPortAdrTbl_Type is record Port_Adr : std_logic_vector(IOAdrWidth-1 downto 0); DDR_Adr : std_logic_vector(IOAdrWidth-1 downto 0); Pin_Adr : std_logic_vector(IOAdrWidth-1 downto 0); end record; type PPortAdrTblArray_Type is array (0 to CMaxNumOfPPort-1) of PPortAdrTbl_Type; constant PPortAdrArray : PPortAdrTblArray_Type := ((PORTA_Address,DDRA_Address,PINA_Address), -- PORTA (PORTB_Address,DDRB_Address,PINB_Address), -- PORTB (PORTC_Address,DDRC_Address,PINC_Address), -- PORTC (PORTD_Address,DDRD_Address,PIND_Address), -- PORTD (PORTE_Address,DDRE_Address,PINE_Address), -- PORTE (PORTF_Address,DDRF_Address,PINF_Address)); -- PORTF -- *************************************************************************************** -- Analog to digital converter constant ADCL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#04#); constant ADCH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#05#); constant ADCSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#06#); constant ADMUX_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#); -- Analog comparator constant ACSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#); -- Watchdog constant WDTCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#21#); -- JTAG OCDR (ATmega128) constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#22#); -- JTAG OCDR (ATmega16) --constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#); -- *************************************************************************************** -- Function declaration function LOG2(Number : positive) return natural; end AVRuCPackage; package body AVRuCPackage is -- Functions function LOG2(Number : positive) return natural is variable Temp : positive; begin Temp := 1; if Number=1 then return 0; else for i in 1 to integer'high loop Temp := 2*Temp; if Temp>=Number then return i; end if; end loop; end if; end LOG2; -- End of functions end AVRuCPackage;
apache-2.0
dcccfcfdccf71763ea682e683d5900e8
0.64067
3.417325
false
false
false
false
grwlf/vsim
vhdl_ct/ct00273.vhd
1
2,165
-- NEED RESULT: ARCH00273: Conformance checking passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00273 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 2.7 (1) -- 2.7 (2) -- 2.7 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00273 -- PKG00273/BODY -- E00000(ARCH00273) -- ENT00273_Test_Bench(ARCH00273_Test_Bench) -- -- REVISION HISTORY: -- -- 20-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; package PKG00273 is constant k : integer ; function func00273 (a : integer ; b : integer := 123456 ; c : integer := WORK.STANDARD_TYPES.highb) return integer; end PKG00273 ; package body PKG00273 is constant k : integer -- force a comment here to test objective 2.7 (3) := 4 ; function func00273 ( a : integer ; -- force a comment here for objective 2.7 (3) b : integer := 123_456 ; -- insert "_" for objective 2.7 (1) -- omit "STANDARD_TYPES." below for objective 2.7 (2) c : integer := highb) return integer is begin return a + b + c + k ; end func00273 ; end PKG00273 ; use WORK.STANDARD_TYPES.test_report; architecture ARCH00273 of E00000 is use WORK.PKG00273.all ; begin P : process begin test_report ( "ARCH00273" , "Conformance checking" , func00273 (2) = 2 + 123456 + 4 + WORK.STANDARD_TYPES.highb) ; wait ; end process P ; end ARCH00273 ; entity ENT00273_Test_Bench is end ENT00273_Test_Bench ; architecture ARCH00273_Test_Bench of ENT00273_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00273 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00273_Test_Bench ;
gpl-3.0
c0660dc674ffac9063a33406cd347cb7
0.516397
3.372274
false
true
false
false