AWfaw/ai-hdlcoder-dataset-clean · Datasets at Hugging Face

repo_name stringlengths 6 79	path stringlengths 6 236	copies int64 1 472	size int64 137 1.04M	content stringlengths 137 1.04M	license stringclasses 15 values	hash stringlengths 32 32	alpha_frac float64 0.25 0.96	ratio float64 1.51 17.5	autogenerated bool 1 class	config_or_test bool 2 classes	has_no_keywords bool 1 class	has_few_assignments bool 1 class
jairov4/accel-oil	impl/impl_test_pcie/simulation/behavioral/system.vhd	1	472,102	------------------------------------------------------------------------------- -- system.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0); fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0); fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30); fpga_0_SRAM_Mem_CEN_pin : out std_logic; fpga_0_SRAM_Mem_OEN_pin : out std_logic; fpga_0_SRAM_Mem_WEN_pin : out std_logic; fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3); fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic; fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31); fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic; fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic; fpga_0_PCIe_Bridge_RXN_pin : in std_logic; fpga_0_PCIe_Bridge_RXP_pin : in std_logic; fpga_0_PCIe_Bridge_TXN_pin : out std_logic; fpga_0_PCIe_Bridge_TXP_pin : out std_logic; fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic; fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic; fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic ); end system; architecture STRUCTURE of system is component system_microblaze_0_wrapper is port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; INTERRUPT_ADDRESS : in std_logic_vector(0 to 31); INTERRUPT_ACK : out std_logic_vector(0 to 1); EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; WAKEUP : in std_logic_vector(0 to 1); SLEEP : out std_logic; DBG_WAKEUP : out std_logic; LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095); LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095); LOCKSTEP_OUT : out std_logic_vector(0 to 4095); INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to 7); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to 63); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to 63); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to 7); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to 63); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to 63); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector(0 downto 0); M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector(31 downto 0); M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector(0 downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector(0 downto 0); M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector(0 downto 0); M_AXI_IP_RDATA : in std_logic_vector(31 downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector(0 downto 0); M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector(31 downto 0); M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector(0 downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector(0 downto 0); M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector(0 downto 0); M_AXI_DP_RDATA : in std_logic_vector(31 downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector(0 downto 0); M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_IC_WDATA : out std_logic_vector(31 downto 0); M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_WUSER : out std_logic_vector(0 downto 0); M_AXI_IC_BID : in std_logic_vector(0 downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_BUSER : in std_logic_vector(0 downto 0); M_AXI_IC_WACK : out std_logic; M_AXI_IC_ARID : out std_logic_vector(0 downto 0); M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_IC_RID : in std_logic_vector(0 downto 0); M_AXI_IC_RDATA : in std_logic_vector(31 downto 0); M_AXI_IC_RRESP : in std_logic_vector(1 downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_IC_RUSER : in std_logic_vector(0 downto 0); M_AXI_IC_RACK : out std_logic; M_AXI_IC_ACVALID : in std_logic; M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_IC_ACREADY : out std_logic; M_AXI_IC_CRREADY : in std_logic; M_AXI_IC_CRVALID : out std_logic; M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_IC_CDVALID : out std_logic; M_AXI_IC_CDREADY : in std_logic; M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_IC_CDLAST : out std_logic; M_AXI_DC_AWID : out std_logic_vector(0 downto 0); M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_DC_WDATA : out std_logic_vector(31 downto 0); M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_WUSER : out std_logic_vector(0 downto 0); M_AXI_DC_BID : in std_logic_vector(0 downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_BUSER : in std_logic_vector(0 downto 0); M_AXI_DC_WACK : out std_logic; M_AXI_DC_ARID : out std_logic_vector(0 downto 0); M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_DC_RID : in std_logic_vector(0 downto 0); M_AXI_DC_RDATA : in std_logic_vector(31 downto 0); M_AXI_DC_RRESP : in std_logic_vector(1 downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; M_AXI_DC_RUSER : in std_logic_vector(0 downto 0); M_AXI_DC_RACK : out std_logic; M_AXI_DC_ACVALID : in std_logic; M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_DC_ACREADY : out std_logic; M_AXI_DC_CRREADY : in std_logic; M_AXI_DC_CRVALID : out std_logic; M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_DC_CDVALID : out std_logic; M_AXI_DC_CDREADY : in std_logic; M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_DC_CDLAST : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to 31); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to 31); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to 31); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to 31); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to 31); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to 31); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to 31); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to 31); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to 31); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to 31); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to 31); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to 31); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to 31); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to 31); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to 31); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to 31); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to 31); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to 31); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to 31); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to 31); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to 31); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to 31); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to 31); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to 31); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to 31); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to 31); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to 31); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to 31); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to 31); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to 31); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to 31); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to 31); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(31 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(31 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(31 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(31 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(31 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(31 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(31 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(31 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(31 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(31 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(31 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(31 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(31 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(31 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(31 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(31 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(31 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(31 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(31 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(31 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(31 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(31 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(31 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(31 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(31 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(31 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(31 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(31 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(31 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(31 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(31 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(31 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end component; component system_mb_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 11); MPLB_Rst : out std_logic_vector(0 to 5); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 191); M_UABus : in std_logic_vector(0 to 191); M_BE : in std_logic_vector(0 to 47); M_RNW : in std_logic_vector(0 to 5); M_abort : in std_logic_vector(0 to 5); M_busLock : in std_logic_vector(0 to 5); M_TAttribute : in std_logic_vector(0 to 95); M_lockErr : in std_logic_vector(0 to 5); M_MSize : in std_logic_vector(0 to 11); M_priority : in std_logic_vector(0 to 11); M_rdBurst : in std_logic_vector(0 to 5); M_request : in std_logic_vector(0 to 5); M_size : in std_logic_vector(0 to 23); M_type : in std_logic_vector(0 to 17); M_wrBurst : in std_logic_vector(0 to 5); M_wrDBus : in std_logic_vector(0 to 383); Sl_addrAck : in std_logic_vector(0 to 11); Sl_MRdErr : in std_logic_vector(0 to 71); Sl_MWrErr : in std_logic_vector(0 to 71); Sl_MBusy : in std_logic_vector(0 to 71); Sl_rdBTerm : in std_logic_vector(0 to 11); Sl_rdComp : in std_logic_vector(0 to 11); Sl_rdDAck : in std_logic_vector(0 to 11); Sl_rdDBus : in std_logic_vector(0 to 767); Sl_rdWdAddr : in std_logic_vector(0 to 47); Sl_rearbitrate : in std_logic_vector(0 to 11); Sl_SSize : in std_logic_vector(0 to 23); Sl_wait : in std_logic_vector(0 to 11); Sl_wrBTerm : in std_logic_vector(0 to 11); Sl_wrComp : in std_logic_vector(0 to 11); Sl_wrDAck : in std_logic_vector(0 to 11); Sl_MIRQ : in std_logic_vector(0 to 71); PLB_MIRQ : out std_logic_vector(0 to 5); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 5); PLB_MTimeout : out std_logic_vector(0 to 5); PLB_MBusy : out std_logic_vector(0 to 5); PLB_MRdErr : out std_logic_vector(0 to 5); PLB_MWrErr : out std_logic_vector(0 to 5); PLB_MRdBTerm : out std_logic_vector(0 to 5); PLB_MRdDAck : out std_logic_vector(0 to 5); PLB_MRdDBus : out std_logic_vector(0 to 383); PLB_MRdWdAddr : out std_logic_vector(0 to 23); PLB_MRearbitrate : out std_logic_vector(0 to 5); PLB_MWrBTerm : out std_logic_vector(0 to 5); PLB_MWrDAck : out std_logic_vector(0 to 5); PLB_MSSize : out std_logic_vector(0 to 11); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 2); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 11); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 11); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 5); PLB_SMWrErr : out std_logic_vector(0 to 5); PLB_SMBusy : out std_logic_vector(0 to 5); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ilmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_ilmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end component; component system_ddr2_sdram_wrapper is port ( FSL0_M_Clk : in std_logic; FSL0_M_Write : in std_logic; FSL0_M_Data : in std_logic_vector(0 to 31); FSL0_M_Control : in std_logic; FSL0_M_Full : out std_logic; FSL0_S_Clk : in std_logic; FSL0_S_Read : in std_logic; FSL0_S_Data : out std_logic_vector(0 to 31); FSL0_S_Control : out std_logic; FSL0_S_Exists : out std_logic; FSL0_B_M_Clk : in std_logic; FSL0_B_M_Write : in std_logic; FSL0_B_M_Data : in std_logic_vector(0 to 31); FSL0_B_M_Control : in std_logic; FSL0_B_M_Full : out std_logic; FSL0_B_S_Clk : in std_logic; FSL0_B_S_Read : in std_logic; FSL0_B_S_Data : out std_logic_vector(0 to 31); FSL0_B_S_Control : out std_logic; FSL0_B_S_Exists : out std_logic; SPLB0_Clk : in std_logic; SPLB0_Rst : in std_logic; SPLB0_PLB_ABus : in std_logic_vector(0 to 31); SPLB0_PLB_PAValid : in std_logic; SPLB0_PLB_SAValid : in std_logic; SPLB0_PLB_masterID : in std_logic_vector(0 to 2); SPLB0_PLB_RNW : in std_logic; SPLB0_PLB_BE : in std_logic_vector(0 to 7); SPLB0_PLB_UABus : in std_logic_vector(0 to 31); SPLB0_PLB_rdPrim : in std_logic; SPLB0_PLB_wrPrim : in std_logic; SPLB0_PLB_abort : in std_logic; SPLB0_PLB_busLock : in std_logic; SPLB0_PLB_MSize : in std_logic_vector(0 to 1); SPLB0_PLB_size : in std_logic_vector(0 to 3); SPLB0_PLB_type : in std_logic_vector(0 to 2); SPLB0_PLB_lockErr : in std_logic; SPLB0_PLB_wrPendReq : in std_logic; SPLB0_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB0_PLB_rdPendReq : in std_logic; SPLB0_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB0_PLB_reqPri : in std_logic_vector(0 to 1); SPLB0_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB0_PLB_rdBurst : in std_logic; SPLB0_PLB_wrBurst : in std_logic; SPLB0_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB0_Sl_addrAck : out std_logic; SPLB0_Sl_SSize : out std_logic_vector(0 to 1); SPLB0_Sl_wait : out std_logic; SPLB0_Sl_rearbitrate : out std_logic; SPLB0_Sl_wrDAck : out std_logic; SPLB0_Sl_wrComp : out std_logic; SPLB0_Sl_wrBTerm : out std_logic; SPLB0_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB0_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB0_Sl_rdDAck : out std_logic; SPLB0_Sl_rdComp : out std_logic; SPLB0_Sl_rdBTerm : out std_logic; SPLB0_Sl_MBusy : out std_logic_vector(0 to 5); SPLB0_Sl_MRdErr : out std_logic_vector(0 to 5); SPLB0_Sl_MWrErr : out std_logic_vector(0 to 5); SPLB0_Sl_MIRQ : out std_logic_vector(0 to 5); SDMA0_Clk : in std_logic; SDMA0_Rx_IntOut : out std_logic; SDMA0_Tx_IntOut : out std_logic; SDMA0_RstOut : out std_logic; SDMA0_TX_D : out std_logic_vector(0 to 31); SDMA0_TX_Rem : out std_logic_vector(0 to 3); SDMA0_TX_SOF : out std_logic; SDMA0_TX_EOF : out std_logic; SDMA0_TX_SOP : out std_logic; SDMA0_TX_EOP : out std_logic; SDMA0_TX_Src_Rdy : out std_logic; SDMA0_TX_Dst_Rdy : in std_logic; SDMA0_RX_D : in std_logic_vector(0 to 31); SDMA0_RX_Rem : in std_logic_vector(0 to 3); SDMA0_RX_SOF : in std_logic; SDMA0_RX_EOF : in std_logic; SDMA0_RX_SOP : in std_logic; SDMA0_RX_EOP : in std_logic; SDMA0_RX_Src_Rdy : in std_logic; SDMA0_RX_Dst_Rdy : out std_logic; SDMA_CTRL0_Clk : in std_logic; SDMA_CTRL0_Rst : in std_logic; SDMA_CTRL0_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL0_PLB_PAValid : in std_logic; SDMA_CTRL0_PLB_SAValid : in std_logic; SDMA_CTRL0_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL0_PLB_RNW : in std_logic; SDMA_CTRL0_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL0_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL0_PLB_rdPrim : in std_logic; SDMA_CTRL0_PLB_wrPrim : in std_logic; SDMA_CTRL0_PLB_abort : in std_logic; SDMA_CTRL0_PLB_busLock : in std_logic; SDMA_CTRL0_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL0_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL0_PLB_lockErr : in std_logic; SDMA_CTRL0_PLB_wrPendReq : in std_logic; SDMA_CTRL0_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_rdPendReq : in std_logic; SDMA_CTRL0_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL0_PLB_rdBurst : in std_logic; SDMA_CTRL0_PLB_wrBurst : in std_logic; SDMA_CTRL0_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL0_Sl_addrAck : out std_logic; SDMA_CTRL0_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL0_Sl_wait : out std_logic; SDMA_CTRL0_Sl_rearbitrate : out std_logic; SDMA_CTRL0_Sl_wrDAck : out std_logic; SDMA_CTRL0_Sl_wrComp : out std_logic; SDMA_CTRL0_Sl_wrBTerm : out std_logic; SDMA_CTRL0_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL0_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL0_Sl_rdDAck : out std_logic; SDMA_CTRL0_Sl_rdComp : out std_logic; SDMA_CTRL0_Sl_rdBTerm : out std_logic; SDMA_CTRL0_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MIRQ : out std_logic_vector(0 to 0); PIM0_Addr : in std_logic_vector(31 downto 0); PIM0_AddrReq : in std_logic; PIM0_AddrAck : out std_logic; PIM0_RNW : in std_logic; PIM0_Size : in std_logic_vector(3 downto 0); PIM0_RdModWr : in std_logic; PIM0_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM0_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM0_WrFIFO_Push : in std_logic; PIM0_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM0_RdFIFO_Pop : in std_logic; PIM0_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM0_WrFIFO_Empty : out std_logic; PIM0_WrFIFO_AlmostFull : out std_logic; PIM0_WrFIFO_Flush : in std_logic; PIM0_RdFIFO_Empty : out std_logic; PIM0_RdFIFO_Flush : in std_logic; PIM0_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM0_InitDone : out std_logic; PPC440MC0_MIMCReadNotWrite : in std_logic; PPC440MC0_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC0_MIMCAddressValid : in std_logic; PPC440MC0_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC0_MIMCWriteDataValid : in std_logic; PPC440MC0_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC0_MIMCBankConflict : in std_logic; PPC440MC0_MIMCRowConflict : in std_logic; PPC440MC0_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC0_MCMIReadDataValid : out std_logic; PPC440MC0_MCMIReadDataErr : out std_logic; PPC440MC0_MCMIAddrReadyToAccept : out std_logic; VFBC0_Cmd_Clk : in std_logic; VFBC0_Cmd_Reset : in std_logic; VFBC0_Cmd_Data : in std_logic_vector(31 downto 0); VFBC0_Cmd_Write : in std_logic; VFBC0_Cmd_End : in std_logic; VFBC0_Cmd_Full : out std_logic; VFBC0_Cmd_Almost_Full : out std_logic; VFBC0_Cmd_Idle : out std_logic; VFBC0_Wd_Clk : in std_logic; VFBC0_Wd_Reset : in std_logic; VFBC0_Wd_Write : in std_logic; VFBC0_Wd_End_Burst : in std_logic; VFBC0_Wd_Flush : in std_logic; VFBC0_Wd_Data : in std_logic_vector(31 downto 0); VFBC0_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC0_Wd_Full : out std_logic; VFBC0_Wd_Almost_Full : out std_logic; VFBC0_Rd_Clk : in std_logic; VFBC0_Rd_Reset : in std_logic; VFBC0_Rd_Read : in std_logic; VFBC0_Rd_End_Burst : in std_logic; VFBC0_Rd_Flush : in std_logic; VFBC0_Rd_Data : out std_logic_vector(31 downto 0); VFBC0_Rd_Empty : out std_logic; VFBC0_Rd_Almost_Empty : out std_logic; MCB0_cmd_clk : in std_logic; MCB0_cmd_en : in std_logic; MCB0_cmd_instr : in std_logic_vector(2 downto 0); MCB0_cmd_bl : in std_logic_vector(5 downto 0); MCB0_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB0_cmd_empty : out std_logic; MCB0_cmd_full : out std_logic; MCB0_wr_clk : in std_logic; MCB0_wr_en : in std_logic; MCB0_wr_mask : in std_logic_vector(7 downto 0); MCB0_wr_data : in std_logic_vector(63 downto 0); MCB0_wr_full : out std_logic; MCB0_wr_empty : out std_logic; MCB0_wr_count : out std_logic_vector(6 downto 0); MCB0_wr_underrun : out std_logic; MCB0_wr_error : out std_logic; MCB0_rd_clk : in std_logic; MCB0_rd_en : in std_logic; MCB0_rd_data : out std_logic_vector(63 downto 0); MCB0_rd_full : out std_logic; MCB0_rd_empty : out std_logic; MCB0_rd_count : out std_logic_vector(6 downto 0); MCB0_rd_overflow : out std_logic; MCB0_rd_error : out std_logic; FSL1_M_Clk : in std_logic; FSL1_M_Write : in std_logic; FSL1_M_Data : in std_logic_vector(0 to 31); FSL1_M_Control : in std_logic; FSL1_M_Full : out std_logic; FSL1_S_Clk : in std_logic; FSL1_S_Read : in std_logic; FSL1_S_Data : out std_logic_vector(0 to 31); FSL1_S_Control : out std_logic; FSL1_S_Exists : out std_logic; FSL1_B_M_Clk : in std_logic; FSL1_B_M_Write : in std_logic; FSL1_B_M_Data : in std_logic_vector(0 to 31); FSL1_B_M_Control : in std_logic; FSL1_B_M_Full : out std_logic; FSL1_B_S_Clk : in std_logic; FSL1_B_S_Read : in std_logic; FSL1_B_S_Data : out std_logic_vector(0 to 31); FSL1_B_S_Control : out std_logic; FSL1_B_S_Exists : out std_logic; SPLB1_Clk : in std_logic; SPLB1_Rst : in std_logic; SPLB1_PLB_ABus : in std_logic_vector(0 to 31); SPLB1_PLB_PAValid : in std_logic; SPLB1_PLB_SAValid : in std_logic; SPLB1_PLB_masterID : in std_logic_vector(0 to 0); SPLB1_PLB_RNW : in std_logic; SPLB1_PLB_BE : in std_logic_vector(0 to 7); SPLB1_PLB_UABus : in std_logic_vector(0 to 31); SPLB1_PLB_rdPrim : in std_logic; SPLB1_PLB_wrPrim : in std_logic; SPLB1_PLB_abort : in std_logic; SPLB1_PLB_busLock : in std_logic; SPLB1_PLB_MSize : in std_logic_vector(0 to 1); SPLB1_PLB_size : in std_logic_vector(0 to 3); SPLB1_PLB_type : in std_logic_vector(0 to 2); SPLB1_PLB_lockErr : in std_logic; SPLB1_PLB_wrPendReq : in std_logic; SPLB1_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB1_PLB_rdPendReq : in std_logic; SPLB1_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB1_PLB_reqPri : in std_logic_vector(0 to 1); SPLB1_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB1_PLB_rdBurst : in std_logic; SPLB1_PLB_wrBurst : in std_logic; SPLB1_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB1_Sl_addrAck : out std_logic; SPLB1_Sl_SSize : out std_logic_vector(0 to 1); SPLB1_Sl_wait : out std_logic; SPLB1_Sl_rearbitrate : out std_logic; SPLB1_Sl_wrDAck : out std_logic; SPLB1_Sl_wrComp : out std_logic; SPLB1_Sl_wrBTerm : out std_logic; SPLB1_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB1_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB1_Sl_rdDAck : out std_logic; SPLB1_Sl_rdComp : out std_logic; SPLB1_Sl_rdBTerm : out std_logic; SPLB1_Sl_MBusy : out std_logic_vector(0 to 0); SPLB1_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB1_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB1_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA1_Clk : in std_logic; SDMA1_Rx_IntOut : out std_logic; SDMA1_Tx_IntOut : out std_logic; SDMA1_RstOut : out std_logic; SDMA1_TX_D : out std_logic_vector(0 to 31); SDMA1_TX_Rem : out std_logic_vector(0 to 3); SDMA1_TX_SOF : out std_logic; SDMA1_TX_EOF : out std_logic; SDMA1_TX_SOP : out std_logic; SDMA1_TX_EOP : out std_logic; SDMA1_TX_Src_Rdy : out std_logic; SDMA1_TX_Dst_Rdy : in std_logic; SDMA1_RX_D : in std_logic_vector(0 to 31); SDMA1_RX_Rem : in std_logic_vector(0 to 3); SDMA1_RX_SOF : in std_logic; SDMA1_RX_EOF : in std_logic; SDMA1_RX_SOP : in std_logic; SDMA1_RX_EOP : in std_logic; SDMA1_RX_Src_Rdy : in std_logic; SDMA1_RX_Dst_Rdy : out std_logic; SDMA_CTRL1_Clk : in std_logic; SDMA_CTRL1_Rst : in std_logic; SDMA_CTRL1_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL1_PLB_PAValid : in std_logic; SDMA_CTRL1_PLB_SAValid : in std_logic; SDMA_CTRL1_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL1_PLB_RNW : in std_logic; SDMA_CTRL1_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL1_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL1_PLB_rdPrim : in std_logic; SDMA_CTRL1_PLB_wrPrim : in std_logic; SDMA_CTRL1_PLB_abort : in std_logic; SDMA_CTRL1_PLB_busLock : in std_logic; SDMA_CTRL1_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL1_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL1_PLB_lockErr : in std_logic; SDMA_CTRL1_PLB_wrPendReq : in std_logic; SDMA_CTRL1_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_rdPendReq : in std_logic; SDMA_CTRL1_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL1_PLB_rdBurst : in std_logic; SDMA_CTRL1_PLB_wrBurst : in std_logic; SDMA_CTRL1_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL1_Sl_addrAck : out std_logic; SDMA_CTRL1_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL1_Sl_wait : out std_logic; SDMA_CTRL1_Sl_rearbitrate : out std_logic; SDMA_CTRL1_Sl_wrDAck : out std_logic; SDMA_CTRL1_Sl_wrComp : out std_logic; SDMA_CTRL1_Sl_wrBTerm : out std_logic; SDMA_CTRL1_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL1_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL1_Sl_rdDAck : out std_logic; SDMA_CTRL1_Sl_rdComp : out std_logic; SDMA_CTRL1_Sl_rdBTerm : out std_logic; SDMA_CTRL1_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MIRQ : out std_logic_vector(0 to 0); PIM1_Addr : in std_logic_vector(31 downto 0); PIM1_AddrReq : in std_logic; PIM1_AddrAck : out std_logic; PIM1_RNW : in std_logic; PIM1_Size : in std_logic_vector(3 downto 0); PIM1_RdModWr : in std_logic; PIM1_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM1_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM1_WrFIFO_Push : in std_logic; PIM1_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM1_RdFIFO_Pop : in std_logic; PIM1_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM1_WrFIFO_Empty : out std_logic; PIM1_WrFIFO_AlmostFull : out std_logic; PIM1_WrFIFO_Flush : in std_logic; PIM1_RdFIFO_Empty : out std_logic; PIM1_RdFIFO_Flush : in std_logic; PIM1_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM1_InitDone : out std_logic; PPC440MC1_MIMCReadNotWrite : in std_logic; PPC440MC1_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC1_MIMCAddressValid : in std_logic; PPC440MC1_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC1_MIMCWriteDataValid : in std_logic; PPC440MC1_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC1_MIMCBankConflict : in std_logic; PPC440MC1_MIMCRowConflict : in std_logic; PPC440MC1_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC1_MCMIReadDataValid : out std_logic; PPC440MC1_MCMIReadDataErr : out std_logic; PPC440MC1_MCMIAddrReadyToAccept : out std_logic; VFBC1_Cmd_Clk : in std_logic; VFBC1_Cmd_Reset : in std_logic; VFBC1_Cmd_Data : in std_logic_vector(31 downto 0); VFBC1_Cmd_Write : in std_logic; VFBC1_Cmd_End : in std_logic; VFBC1_Cmd_Full : out std_logic; VFBC1_Cmd_Almost_Full : out std_logic; VFBC1_Cmd_Idle : out std_logic; VFBC1_Wd_Clk : in std_logic; VFBC1_Wd_Reset : in std_logic; VFBC1_Wd_Write : in std_logic; VFBC1_Wd_End_Burst : in std_logic; VFBC1_Wd_Flush : in std_logic; VFBC1_Wd_Data : in std_logic_vector(31 downto 0); VFBC1_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC1_Wd_Full : out std_logic; VFBC1_Wd_Almost_Full : out std_logic; VFBC1_Rd_Clk : in std_logic; VFBC1_Rd_Reset : in std_logic; VFBC1_Rd_Read : in std_logic; VFBC1_Rd_End_Burst : in std_logic; VFBC1_Rd_Flush : in std_logic; VFBC1_Rd_Data : out std_logic_vector(31 downto 0); VFBC1_Rd_Empty : out std_logic; VFBC1_Rd_Almost_Empty : out std_logic; MCB1_cmd_clk : in std_logic; MCB1_cmd_en : in std_logic; MCB1_cmd_instr : in std_logic_vector(2 downto 0); MCB1_cmd_bl : in std_logic_vector(5 downto 0); MCB1_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB1_cmd_empty : out std_logic; MCB1_cmd_full : out std_logic; MCB1_wr_clk : in std_logic; MCB1_wr_en : in std_logic; MCB1_wr_mask : in std_logic_vector(7 downto 0); MCB1_wr_data : in std_logic_vector(63 downto 0); MCB1_wr_full : out std_logic; MCB1_wr_empty : out std_logic; MCB1_wr_count : out std_logic_vector(6 downto 0); MCB1_wr_underrun : out std_logic; MCB1_wr_error : out std_logic; MCB1_rd_clk : in std_logic; MCB1_rd_en : in std_logic; MCB1_rd_data : out std_logic_vector(63 downto 0); MCB1_rd_full : out std_logic; MCB1_rd_empty : out std_logic; MCB1_rd_count : out std_logic_vector(6 downto 0); MCB1_rd_overflow : out std_logic; MCB1_rd_error : out std_logic; FSL2_M_Clk : in std_logic; FSL2_M_Write : in std_logic; FSL2_M_Data : in std_logic_vector(0 to 31); FSL2_M_Control : in std_logic; FSL2_M_Full : out std_logic; FSL2_S_Clk : in std_logic; FSL2_S_Read : in std_logic; FSL2_S_Data : out std_logic_vector(0 to 31); FSL2_S_Control : out std_logic; FSL2_S_Exists : out std_logic; FSL2_B_M_Clk : in std_logic; FSL2_B_M_Write : in std_logic; FSL2_B_M_Data : in std_logic_vector(0 to 31); FSL2_B_M_Control : in std_logic; FSL2_B_M_Full : out std_logic; FSL2_B_S_Clk : in std_logic; FSL2_B_S_Read : in std_logic; FSL2_B_S_Data : out std_logic_vector(0 to 31); FSL2_B_S_Control : out std_logic; FSL2_B_S_Exists : out std_logic; SPLB2_Clk : in std_logic; SPLB2_Rst : in std_logic; SPLB2_PLB_ABus : in std_logic_vector(0 to 31); SPLB2_PLB_PAValid : in std_logic; SPLB2_PLB_SAValid : in std_logic; SPLB2_PLB_masterID : in std_logic_vector(0 to 0); SPLB2_PLB_RNW : in std_logic; SPLB2_PLB_BE : in std_logic_vector(0 to 7); SPLB2_PLB_UABus : in std_logic_vector(0 to 31); SPLB2_PLB_rdPrim : in std_logic; SPLB2_PLB_wrPrim : in std_logic; SPLB2_PLB_abort : in std_logic; SPLB2_PLB_busLock : in std_logic; SPLB2_PLB_MSize : in std_logic_vector(0 to 1); SPLB2_PLB_size : in std_logic_vector(0 to 3); SPLB2_PLB_type : in std_logic_vector(0 to 2); SPLB2_PLB_lockErr : in std_logic; SPLB2_PLB_wrPendReq : in std_logic; SPLB2_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB2_PLB_rdPendReq : in std_logic; SPLB2_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB2_PLB_reqPri : in std_logic_vector(0 to 1); SPLB2_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB2_PLB_rdBurst : in std_logic; SPLB2_PLB_wrBurst : in std_logic; SPLB2_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB2_Sl_addrAck : out std_logic; SPLB2_Sl_SSize : out std_logic_vector(0 to 1); SPLB2_Sl_wait : out std_logic; SPLB2_Sl_rearbitrate : out std_logic; SPLB2_Sl_wrDAck : out std_logic; SPLB2_Sl_wrComp : out std_logic; SPLB2_Sl_wrBTerm : out std_logic; SPLB2_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB2_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB2_Sl_rdDAck : out std_logic; SPLB2_Sl_rdComp : out std_logic; SPLB2_Sl_rdBTerm : out std_logic; SPLB2_Sl_MBusy : out std_logic_vector(0 to 0); SPLB2_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB2_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB2_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA2_Clk : in std_logic; SDMA2_Rx_IntOut : out std_logic; SDMA2_Tx_IntOut : out std_logic; SDMA2_RstOut : out std_logic; SDMA2_TX_D : out std_logic_vector(0 to 31); SDMA2_TX_Rem : out std_logic_vector(0 to 3); SDMA2_TX_SOF : out std_logic; SDMA2_TX_EOF : out std_logic; SDMA2_TX_SOP : out std_logic; SDMA2_TX_EOP : out std_logic; SDMA2_TX_Src_Rdy : out std_logic; SDMA2_TX_Dst_Rdy : in std_logic; SDMA2_RX_D : in std_logic_vector(0 to 31); SDMA2_RX_Rem : in std_logic_vector(0 to 3); SDMA2_RX_SOF : in std_logic; SDMA2_RX_EOF : in std_logic; SDMA2_RX_SOP : in std_logic; SDMA2_RX_EOP : in std_logic; SDMA2_RX_Src_Rdy : in std_logic; SDMA2_RX_Dst_Rdy : out std_logic; SDMA_CTRL2_Clk : in std_logic; SDMA_CTRL2_Rst : in std_logic; SDMA_CTRL2_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL2_PLB_PAValid : in std_logic; SDMA_CTRL2_PLB_SAValid : in std_logic; SDMA_CTRL2_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL2_PLB_RNW : in std_logic; SDMA_CTRL2_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL2_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL2_PLB_rdPrim : in std_logic; SDMA_CTRL2_PLB_wrPrim : in std_logic; SDMA_CTRL2_PLB_abort : in std_logic; SDMA_CTRL2_PLB_busLock : in std_logic; SDMA_CTRL2_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL2_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL2_PLB_lockErr : in std_logic; SDMA_CTRL2_PLB_wrPendReq : in std_logic; SDMA_CTRL2_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_rdPendReq : in std_logic; SDMA_CTRL2_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL2_PLB_rdBurst : in std_logic; SDMA_CTRL2_PLB_wrBurst : in std_logic; SDMA_CTRL2_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL2_Sl_addrAck : out std_logic; SDMA_CTRL2_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL2_Sl_wait : out std_logic; SDMA_CTRL2_Sl_rearbitrate : out std_logic; SDMA_CTRL2_Sl_wrDAck : out std_logic; SDMA_CTRL2_Sl_wrComp : out std_logic; SDMA_CTRL2_Sl_wrBTerm : out std_logic; SDMA_CTRL2_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL2_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL2_Sl_rdDAck : out std_logic; SDMA_CTRL2_Sl_rdComp : out std_logic; SDMA_CTRL2_Sl_rdBTerm : out std_logic; SDMA_CTRL2_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MIRQ : out std_logic_vector(0 to 0); PIM2_Addr : in std_logic_vector(31 downto 0); PIM2_AddrReq : in std_logic; PIM2_AddrAck : out std_logic; PIM2_RNW : in std_logic; PIM2_Size : in std_logic_vector(3 downto 0); PIM2_RdModWr : in std_logic; PIM2_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM2_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM2_WrFIFO_Push : in std_logic; PIM2_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM2_RdFIFO_Pop : in std_logic; PIM2_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM2_WrFIFO_Empty : out std_logic; PIM2_WrFIFO_AlmostFull : out std_logic; PIM2_WrFIFO_Flush : in std_logic; PIM2_RdFIFO_Empty : out std_logic; PIM2_RdFIFO_Flush : in std_logic; PIM2_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM2_InitDone : out std_logic; PPC440MC2_MIMCReadNotWrite : in std_logic; PPC440MC2_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC2_MIMCAddressValid : in std_logic; PPC440MC2_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC2_MIMCWriteDataValid : in std_logic; PPC440MC2_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC2_MIMCBankConflict : in std_logic; PPC440MC2_MIMCRowConflict : in std_logic; PPC440MC2_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC2_MCMIReadDataValid : out std_logic; PPC440MC2_MCMIReadDataErr : out std_logic; PPC440MC2_MCMIAddrReadyToAccept : out std_logic; VFBC2_Cmd_Clk : in std_logic; VFBC2_Cmd_Reset : in std_logic; VFBC2_Cmd_Data : in std_logic_vector(31 downto 0); VFBC2_Cmd_Write : in std_logic; VFBC2_Cmd_End : in std_logic; VFBC2_Cmd_Full : out std_logic; VFBC2_Cmd_Almost_Full : out std_logic; VFBC2_Cmd_Idle : out std_logic; VFBC2_Wd_Clk : in std_logic; VFBC2_Wd_Reset : in std_logic; VFBC2_Wd_Write : in std_logic; VFBC2_Wd_End_Burst : in std_logic; VFBC2_Wd_Flush : in std_logic; VFBC2_Wd_Data : in std_logic_vector(31 downto 0); VFBC2_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC2_Wd_Full : out std_logic; VFBC2_Wd_Almost_Full : out std_logic; VFBC2_Rd_Clk : in std_logic; VFBC2_Rd_Reset : in std_logic; VFBC2_Rd_Read : in std_logic; VFBC2_Rd_End_Burst : in std_logic; VFBC2_Rd_Flush : in std_logic; VFBC2_Rd_Data : out std_logic_vector(31 downto 0); VFBC2_Rd_Empty : out std_logic; VFBC2_Rd_Almost_Empty : out std_logic; MCB2_cmd_clk : in std_logic; MCB2_cmd_en : in std_logic; MCB2_cmd_instr : in std_logic_vector(2 downto 0); MCB2_cmd_bl : in std_logic_vector(5 downto 0); MCB2_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB2_cmd_empty : out std_logic; MCB2_cmd_full : out std_logic; MCB2_wr_clk : in std_logic; MCB2_wr_en : in std_logic; MCB2_wr_mask : in std_logic_vector(7 downto 0); MCB2_wr_data : in std_logic_vector(63 downto 0); MCB2_wr_full : out std_logic; MCB2_wr_empty : out std_logic; MCB2_wr_count : out std_logic_vector(6 downto 0); MCB2_wr_underrun : out std_logic; MCB2_wr_error : out std_logic; MCB2_rd_clk : in std_logic; MCB2_rd_en : in std_logic; MCB2_rd_data : out std_logic_vector(63 downto 0); MCB2_rd_full : out std_logic; MCB2_rd_empty : out std_logic; MCB2_rd_count : out std_logic_vector(6 downto 0); MCB2_rd_overflow : out std_logic; MCB2_rd_error : out std_logic; FSL3_M_Clk : in std_logic; FSL3_M_Write : in std_logic; FSL3_M_Data : in std_logic_vector(0 to 31); FSL3_M_Control : in std_logic; FSL3_M_Full : out std_logic; FSL3_S_Clk : in std_logic; FSL3_S_Read : in std_logic; FSL3_S_Data : out std_logic_vector(0 to 31); FSL3_S_Control : out std_logic; FSL3_S_Exists : out std_logic; FSL3_B_M_Clk : in std_logic; FSL3_B_M_Write : in std_logic; FSL3_B_M_Data : in std_logic_vector(0 to 31); FSL3_B_M_Control : in std_logic; FSL3_B_M_Full : out std_logic; FSL3_B_S_Clk : in std_logic; FSL3_B_S_Read : in std_logic; FSL3_B_S_Data : out std_logic_vector(0 to 31); FSL3_B_S_Control : out std_logic; FSL3_B_S_Exists : out std_logic; SPLB3_Clk : in std_logic; SPLB3_Rst : in std_logic; SPLB3_PLB_ABus : in std_logic_vector(0 to 31); SPLB3_PLB_PAValid : in std_logic; SPLB3_PLB_SAValid : in std_logic; SPLB3_PLB_masterID : in std_logic_vector(0 to 0); SPLB3_PLB_RNW : in std_logic; SPLB3_PLB_BE : in std_logic_vector(0 to 7); SPLB3_PLB_UABus : in std_logic_vector(0 to 31); SPLB3_PLB_rdPrim : in std_logic; SPLB3_PLB_wrPrim : in std_logic; SPLB3_PLB_abort : in std_logic; SPLB3_PLB_busLock : in std_logic; SPLB3_PLB_MSize : in std_logic_vector(0 to 1); SPLB3_PLB_size : in std_logic_vector(0 to 3); SPLB3_PLB_type : in std_logic_vector(0 to 2); SPLB3_PLB_lockErr : in std_logic; SPLB3_PLB_wrPendReq : in std_logic; SPLB3_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB3_PLB_rdPendReq : in std_logic; SPLB3_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB3_PLB_reqPri : in std_logic_vector(0 to 1); SPLB3_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB3_PLB_rdBurst : in std_logic; SPLB3_PLB_wrBurst : in std_logic; SPLB3_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB3_Sl_addrAck : out std_logic; SPLB3_Sl_SSize : out std_logic_vector(0 to 1); SPLB3_Sl_wait : out std_logic; SPLB3_Sl_rearbitrate : out std_logic; SPLB3_Sl_wrDAck : out std_logic; SPLB3_Sl_wrComp : out std_logic; SPLB3_Sl_wrBTerm : out std_logic; SPLB3_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB3_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB3_Sl_rdDAck : out std_logic; SPLB3_Sl_rdComp : out std_logic; SPLB3_Sl_rdBTerm : out std_logic; SPLB3_Sl_MBusy : out std_logic_vector(0 to 0); SPLB3_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB3_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB3_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA3_Clk : in std_logic; SDMA3_Rx_IntOut : out std_logic; SDMA3_Tx_IntOut : out std_logic; SDMA3_RstOut : out std_logic; SDMA3_TX_D : out std_logic_vector(0 to 31); SDMA3_TX_Rem : out std_logic_vector(0 to 3); SDMA3_TX_SOF : out std_logic; SDMA3_TX_EOF : out std_logic; SDMA3_TX_SOP : out std_logic; SDMA3_TX_EOP : out std_logic; SDMA3_TX_Src_Rdy : out std_logic; SDMA3_TX_Dst_Rdy : in std_logic; SDMA3_RX_D : in std_logic_vector(0 to 31); SDMA3_RX_Rem : in std_logic_vector(0 to 3); SDMA3_RX_SOF : in std_logic; SDMA3_RX_EOF : in std_logic; SDMA3_RX_SOP : in std_logic; SDMA3_RX_EOP : in std_logic; SDMA3_RX_Src_Rdy : in std_logic; SDMA3_RX_Dst_Rdy : out std_logic; SDMA_CTRL3_Clk : in std_logic; SDMA_CTRL3_Rst : in std_logic; SDMA_CTRL3_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL3_PLB_PAValid : in std_logic; SDMA_CTRL3_PLB_SAValid : in std_logic; SDMA_CTRL3_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL3_PLB_RNW : in std_logic; SDMA_CTRL3_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL3_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL3_PLB_rdPrim : in std_logic; SDMA_CTRL3_PLB_wrPrim : in std_logic; SDMA_CTRL3_PLB_abort : in std_logic; SDMA_CTRL3_PLB_busLock : in std_logic; SDMA_CTRL3_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL3_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL3_PLB_lockErr : in std_logic; SDMA_CTRL3_PLB_wrPendReq : in std_logic; SDMA_CTRL3_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_rdPendReq : in std_logic; SDMA_CTRL3_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL3_PLB_rdBurst : in std_logic; SDMA_CTRL3_PLB_wrBurst : in std_logic; SDMA_CTRL3_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL3_Sl_addrAck : out std_logic; SDMA_CTRL3_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL3_Sl_wait : out std_logic; SDMA_CTRL3_Sl_rearbitrate : out std_logic; SDMA_CTRL3_Sl_wrDAck : out std_logic; SDMA_CTRL3_Sl_wrComp : out std_logic; SDMA_CTRL3_Sl_wrBTerm : out std_logic; SDMA_CTRL3_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL3_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL3_Sl_rdDAck : out std_logic; SDMA_CTRL3_Sl_rdComp : out std_logic; SDMA_CTRL3_Sl_rdBTerm : out std_logic; SDMA_CTRL3_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MIRQ : out std_logic_vector(0 to 0); PIM3_Addr : in std_logic_vector(31 downto 0); PIM3_AddrReq : in std_logic; PIM3_AddrAck : out std_logic; PIM3_RNW : in std_logic; PIM3_Size : in std_logic_vector(3 downto 0); PIM3_RdModWr : in std_logic; PIM3_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM3_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM3_WrFIFO_Push : in std_logic; PIM3_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM3_RdFIFO_Pop : in std_logic; PIM3_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM3_WrFIFO_Empty : out std_logic; PIM3_WrFIFO_AlmostFull : out std_logic; PIM3_WrFIFO_Flush : in std_logic; PIM3_RdFIFO_Empty : out std_logic; PIM3_RdFIFO_Flush : in std_logic; PIM3_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM3_InitDone : out std_logic; PPC440MC3_MIMCReadNotWrite : in std_logic; PPC440MC3_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC3_MIMCAddressValid : in std_logic; PPC440MC3_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC3_MIMCWriteDataValid : in std_logic; PPC440MC3_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC3_MIMCBankConflict : in std_logic; PPC440MC3_MIMCRowConflict : in std_logic; PPC440MC3_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC3_MCMIReadDataValid : out std_logic; PPC440MC3_MCMIReadDataErr : out std_logic; PPC440MC3_MCMIAddrReadyToAccept : out std_logic; VFBC3_Cmd_Clk : in std_logic; VFBC3_Cmd_Reset : in std_logic; VFBC3_Cmd_Data : in std_logic_vector(31 downto 0); VFBC3_Cmd_Write : in std_logic; VFBC3_Cmd_End : in std_logic; VFBC3_Cmd_Full : out std_logic; VFBC3_Cmd_Almost_Full : out std_logic; VFBC3_Cmd_Idle : out std_logic; VFBC3_Wd_Clk : in std_logic; VFBC3_Wd_Reset : in std_logic; VFBC3_Wd_Write : in std_logic; VFBC3_Wd_End_Burst : in std_logic; VFBC3_Wd_Flush : in std_logic; VFBC3_Wd_Data : in std_logic_vector(31 downto 0); VFBC3_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC3_Wd_Full : out std_logic; VFBC3_Wd_Almost_Full : out std_logic; VFBC3_Rd_Clk : in std_logic; VFBC3_Rd_Reset : in std_logic; VFBC3_Rd_Read : in std_logic; VFBC3_Rd_End_Burst : in std_logic; VFBC3_Rd_Flush : in std_logic; VFBC3_Rd_Data : out std_logic_vector(31 downto 0); VFBC3_Rd_Empty : out std_logic; VFBC3_Rd_Almost_Empty : out std_logic; MCB3_cmd_clk : in std_logic; MCB3_cmd_en : in std_logic; MCB3_cmd_instr : in std_logic_vector(2 downto 0); MCB3_cmd_bl : in std_logic_vector(5 downto 0); MCB3_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB3_cmd_empty : out std_logic; MCB3_cmd_full : out std_logic; MCB3_wr_clk : in std_logic; MCB3_wr_en : in std_logic; MCB3_wr_mask : in std_logic_vector(7 downto 0); MCB3_wr_data : in std_logic_vector(63 downto 0); MCB3_wr_full : out std_logic; MCB3_wr_empty : out std_logic; MCB3_wr_count : out std_logic_vector(6 downto 0); MCB3_wr_underrun : out std_logic; MCB3_wr_error : out std_logic; MCB3_rd_clk : in std_logic; MCB3_rd_en : in std_logic; MCB3_rd_data : out std_logic_vector(63 downto 0); MCB3_rd_full : out std_logic; MCB3_rd_empty : out std_logic; MCB3_rd_count : out std_logic_vector(6 downto 0); MCB3_rd_overflow : out std_logic; MCB3_rd_error : out std_logic; FSL4_M_Clk : in std_logic; FSL4_M_Write : in std_logic; FSL4_M_Data : in std_logic_vector(0 to 31); FSL4_M_Control : in std_logic; FSL4_M_Full : out std_logic; FSL4_S_Clk : in std_logic; FSL4_S_Read : in std_logic; FSL4_S_Data : out std_logic_vector(0 to 31); FSL4_S_Control : out std_logic; FSL4_S_Exists : out std_logic; FSL4_B_M_Clk : in std_logic; FSL4_B_M_Write : in std_logic; FSL4_B_M_Data : in std_logic_vector(0 to 31); FSL4_B_M_Control : in std_logic; FSL4_B_M_Full : out std_logic; FSL4_B_S_Clk : in std_logic; FSL4_B_S_Read : in std_logic; FSL4_B_S_Data : out std_logic_vector(0 to 31); FSL4_B_S_Control : out std_logic; FSL4_B_S_Exists : out std_logic; SPLB4_Clk : in std_logic; SPLB4_Rst : in std_logic; SPLB4_PLB_ABus : in std_logic_vector(0 to 31); SPLB4_PLB_PAValid : in std_logic; SPLB4_PLB_SAValid : in std_logic; SPLB4_PLB_masterID : in std_logic_vector(0 to 0); SPLB4_PLB_RNW : in std_logic; SPLB4_PLB_BE : in std_logic_vector(0 to 7); SPLB4_PLB_UABus : in std_logic_vector(0 to 31); SPLB4_PLB_rdPrim : in std_logic; SPLB4_PLB_wrPrim : in std_logic; SPLB4_PLB_abort : in std_logic; SPLB4_PLB_busLock : in std_logic; SPLB4_PLB_MSize : in std_logic_vector(0 to 1); SPLB4_PLB_size : in std_logic_vector(0 to 3); SPLB4_PLB_type : in std_logic_vector(0 to 2); SPLB4_PLB_lockErr : in std_logic; SPLB4_PLB_wrPendReq : in std_logic; SPLB4_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB4_PLB_rdPendReq : in std_logic; SPLB4_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB4_PLB_reqPri : in std_logic_vector(0 to 1); SPLB4_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB4_PLB_rdBurst : in std_logic; SPLB4_PLB_wrBurst : in std_logic; SPLB4_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB4_Sl_addrAck : out std_logic; SPLB4_Sl_SSize : out std_logic_vector(0 to 1); SPLB4_Sl_wait : out std_logic; SPLB4_Sl_rearbitrate : out std_logic; SPLB4_Sl_wrDAck : out std_logic; SPLB4_Sl_wrComp : out std_logic; SPLB4_Sl_wrBTerm : out std_logic; SPLB4_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB4_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB4_Sl_rdDAck : out std_logic; SPLB4_Sl_rdComp : out std_logic; SPLB4_Sl_rdBTerm : out std_logic; SPLB4_Sl_MBusy : out std_logic_vector(0 to 0); SPLB4_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB4_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB4_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA4_Clk : in std_logic; SDMA4_Rx_IntOut : out std_logic; SDMA4_Tx_IntOut : out std_logic; SDMA4_RstOut : out std_logic; SDMA4_TX_D : out std_logic_vector(0 to 31); SDMA4_TX_Rem : out std_logic_vector(0 to 3); SDMA4_TX_SOF : out std_logic; SDMA4_TX_EOF : out std_logic; SDMA4_TX_SOP : out std_logic; SDMA4_TX_EOP : out std_logic; SDMA4_TX_Src_Rdy : out std_logic; SDMA4_TX_Dst_Rdy : in std_logic; SDMA4_RX_D : in std_logic_vector(0 to 31); SDMA4_RX_Rem : in std_logic_vector(0 to 3); SDMA4_RX_SOF : in std_logic; SDMA4_RX_EOF : in std_logic; SDMA4_RX_SOP : in std_logic; SDMA4_RX_EOP : in std_logic; SDMA4_RX_Src_Rdy : in std_logic; SDMA4_RX_Dst_Rdy : out std_logic; SDMA_CTRL4_Clk : in std_logic; SDMA_CTRL4_Rst : in std_logic; SDMA_CTRL4_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL4_PLB_PAValid : in std_logic; SDMA_CTRL4_PLB_SAValid : in std_logic; SDMA_CTRL4_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL4_PLB_RNW : in std_logic; SDMA_CTRL4_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL4_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL4_PLB_rdPrim : in std_logic; SDMA_CTRL4_PLB_wrPrim : in std_logic; SDMA_CTRL4_PLB_abort : in std_logic; SDMA_CTRL4_PLB_busLock : in std_logic; SDMA_CTRL4_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL4_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL4_PLB_lockErr : in std_logic; SDMA_CTRL4_PLB_wrPendReq : in std_logic; SDMA_CTRL4_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_rdPendReq : in std_logic; SDMA_CTRL4_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL4_PLB_rdBurst : in std_logic; SDMA_CTRL4_PLB_wrBurst : in std_logic; SDMA_CTRL4_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL4_Sl_addrAck : out std_logic; SDMA_CTRL4_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL4_Sl_wait : out std_logic; SDMA_CTRL4_Sl_rearbitrate : out std_logic; SDMA_CTRL4_Sl_wrDAck : out std_logic; SDMA_CTRL4_Sl_wrComp : out std_logic; SDMA_CTRL4_Sl_wrBTerm : out std_logic; SDMA_CTRL4_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL4_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL4_Sl_rdDAck : out std_logic; SDMA_CTRL4_Sl_rdComp : out std_logic; SDMA_CTRL4_Sl_rdBTerm : out std_logic; SDMA_CTRL4_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MIRQ : out std_logic_vector(0 to 0); PIM4_Addr : in std_logic_vector(31 downto 0); PIM4_AddrReq : in std_logic; PIM4_AddrAck : out std_logic; PIM4_RNW : in std_logic; PIM4_Size : in std_logic_vector(3 downto 0); PIM4_RdModWr : in std_logic; PIM4_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM4_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM4_WrFIFO_Push : in std_logic; PIM4_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM4_RdFIFO_Pop : in std_logic; PIM4_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM4_WrFIFO_Empty : out std_logic; PIM4_WrFIFO_AlmostFull : out std_logic; PIM4_WrFIFO_Flush : in std_logic; PIM4_RdFIFO_Empty : out std_logic; PIM4_RdFIFO_Flush : in std_logic; PIM4_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM4_InitDone : out std_logic; PPC440MC4_MIMCReadNotWrite : in std_logic; PPC440MC4_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC4_MIMCAddressValid : in std_logic; PPC440MC4_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC4_MIMCWriteDataValid : in std_logic; PPC440MC4_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC4_MIMCBankConflict : in std_logic; PPC440MC4_MIMCRowConflict : in std_logic; PPC440MC4_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC4_MCMIReadDataValid : out std_logic; PPC440MC4_MCMIReadDataErr : out std_logic; PPC440MC4_MCMIAddrReadyToAccept : out std_logic; VFBC4_Cmd_Clk : in std_logic; VFBC4_Cmd_Reset : in std_logic; VFBC4_Cmd_Data : in std_logic_vector(31 downto 0); VFBC4_Cmd_Write : in std_logic; VFBC4_Cmd_End : in std_logic; VFBC4_Cmd_Full : out std_logic; VFBC4_Cmd_Almost_Full : out std_logic; VFBC4_Cmd_Idle : out std_logic; VFBC4_Wd_Clk : in std_logic; VFBC4_Wd_Reset : in std_logic; VFBC4_Wd_Write : in std_logic; VFBC4_Wd_End_Burst : in std_logic; VFBC4_Wd_Flush : in std_logic; VFBC4_Wd_Data : in std_logic_vector(31 downto 0); VFBC4_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC4_Wd_Full : out std_logic; VFBC4_Wd_Almost_Full : out std_logic; VFBC4_Rd_Clk : in std_logic; VFBC4_Rd_Reset : in std_logic; VFBC4_Rd_Read : in std_logic; VFBC4_Rd_End_Burst : in std_logic; VFBC4_Rd_Flush : in std_logic; VFBC4_Rd_Data : out std_logic_vector(31 downto 0); VFBC4_Rd_Empty : out std_logic; VFBC4_Rd_Almost_Empty : out std_logic; MCB4_cmd_clk : in std_logic; MCB4_cmd_en : in std_logic; MCB4_cmd_instr : in std_logic_vector(2 downto 0); MCB4_cmd_bl : in std_logic_vector(5 downto 0); MCB4_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB4_cmd_empty : out std_logic; MCB4_cmd_full : out std_logic; MCB4_wr_clk : in std_logic; MCB4_wr_en : in std_logic; MCB4_wr_mask : in std_logic_vector(7 downto 0); MCB4_wr_data : in std_logic_vector(63 downto 0); MCB4_wr_full : out std_logic; MCB4_wr_empty : out std_logic; MCB4_wr_count : out std_logic_vector(6 downto 0); MCB4_wr_underrun : out std_logic; MCB4_wr_error : out std_logic; MCB4_rd_clk : in std_logic; MCB4_rd_en : in std_logic; MCB4_rd_data : out std_logic_vector(63 downto 0); MCB4_rd_full : out std_logic; MCB4_rd_empty : out std_logic; MCB4_rd_count : out std_logic_vector(6 downto 0); MCB4_rd_overflow : out std_logic; MCB4_rd_error : out std_logic; FSL5_M_Clk : in std_logic; FSL5_M_Write : in std_logic; FSL5_M_Data : in std_logic_vector(0 to 31); FSL5_M_Control : in std_logic; FSL5_M_Full : out std_logic; FSL5_S_Clk : in std_logic; FSL5_S_Read : in std_logic; FSL5_S_Data : out std_logic_vector(0 to 31); FSL5_S_Control : out std_logic; FSL5_S_Exists : out std_logic; FSL5_B_M_Clk : in std_logic; FSL5_B_M_Write : in std_logic; FSL5_B_M_Data : in std_logic_vector(0 to 31); FSL5_B_M_Control : in std_logic; FSL5_B_M_Full : out std_logic; FSL5_B_S_Clk : in std_logic; FSL5_B_S_Read : in std_logic; FSL5_B_S_Data : out std_logic_vector(0 to 31); FSL5_B_S_Control : out std_logic; FSL5_B_S_Exists : out std_logic; SPLB5_Clk : in std_logic; SPLB5_Rst : in std_logic; SPLB5_PLB_ABus : in std_logic_vector(0 to 31); SPLB5_PLB_PAValid : in std_logic; SPLB5_PLB_SAValid : in std_logic; SPLB5_PLB_masterID : in std_logic_vector(0 to 0); SPLB5_PLB_RNW : in std_logic; SPLB5_PLB_BE : in std_logic_vector(0 to 7); SPLB5_PLB_UABus : in std_logic_vector(0 to 31); SPLB5_PLB_rdPrim : in std_logic; SPLB5_PLB_wrPrim : in std_logic; SPLB5_PLB_abort : in std_logic; SPLB5_PLB_busLock : in std_logic; SPLB5_PLB_MSize : in std_logic_vector(0 to 1); SPLB5_PLB_size : in std_logic_vector(0 to 3); SPLB5_PLB_type : in std_logic_vector(0 to 2); SPLB5_PLB_lockErr : in std_logic; SPLB5_PLB_wrPendReq : in std_logic; SPLB5_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB5_PLB_rdPendReq : in std_logic; SPLB5_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB5_PLB_reqPri : in std_logic_vector(0 to 1); SPLB5_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB5_PLB_rdBurst : in std_logic; SPLB5_PLB_wrBurst : in std_logic; SPLB5_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB5_Sl_addrAck : out std_logic; SPLB5_Sl_SSize : out std_logic_vector(0 to 1); SPLB5_Sl_wait : out std_logic; SPLB5_Sl_rearbitrate : out std_logic; SPLB5_Sl_wrDAck : out std_logic; SPLB5_Sl_wrComp : out std_logic; SPLB5_Sl_wrBTerm : out std_logic; SPLB5_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB5_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB5_Sl_rdDAck : out std_logic; SPLB5_Sl_rdComp : out std_logic; SPLB5_Sl_rdBTerm : out std_logic; SPLB5_Sl_MBusy : out std_logic_vector(0 to 0); SPLB5_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB5_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB5_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA5_Clk : in std_logic; SDMA5_Rx_IntOut : out std_logic; SDMA5_Tx_IntOut : out std_logic; SDMA5_RstOut : out std_logic; SDMA5_TX_D : out std_logic_vector(0 to 31); SDMA5_TX_Rem : out std_logic_vector(0 to 3); SDMA5_TX_SOF : out std_logic; SDMA5_TX_EOF : out std_logic; SDMA5_TX_SOP : out std_logic; SDMA5_TX_EOP : out std_logic; SDMA5_TX_Src_Rdy : out std_logic; SDMA5_TX_Dst_Rdy : in std_logic; SDMA5_RX_D : in std_logic_vector(0 to 31); SDMA5_RX_Rem : in std_logic_vector(0 to 3); SDMA5_RX_SOF : in std_logic; SDMA5_RX_EOF : in std_logic; SDMA5_RX_SOP : in std_logic; SDMA5_RX_EOP : in std_logic; SDMA5_RX_Src_Rdy : in std_logic; SDMA5_RX_Dst_Rdy : out std_logic; SDMA_CTRL5_Clk : in std_logic; SDMA_CTRL5_Rst : in std_logic; SDMA_CTRL5_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL5_PLB_PAValid : in std_logic; SDMA_CTRL5_PLB_SAValid : in std_logic; SDMA_CTRL5_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL5_PLB_RNW : in std_logic; SDMA_CTRL5_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL5_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL5_PLB_rdPrim : in std_logic; SDMA_CTRL5_PLB_wrPrim : in std_logic; SDMA_CTRL5_PLB_abort : in std_logic; SDMA_CTRL5_PLB_busLock : in std_logic; SDMA_CTRL5_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL5_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL5_PLB_lockErr : in std_logic; SDMA_CTRL5_PLB_wrPendReq : in std_logic; SDMA_CTRL5_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_rdPendReq : in std_logic; SDMA_CTRL5_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL5_PLB_rdBurst : in std_logic; SDMA_CTRL5_PLB_wrBurst : in std_logic; SDMA_CTRL5_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL5_Sl_addrAck : out std_logic; SDMA_CTRL5_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL5_Sl_wait : out std_logic; SDMA_CTRL5_Sl_rearbitrate : out std_logic; SDMA_CTRL5_Sl_wrDAck : out std_logic; SDMA_CTRL5_Sl_wrComp : out std_logic; SDMA_CTRL5_Sl_wrBTerm : out std_logic; SDMA_CTRL5_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL5_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL5_Sl_rdDAck : out std_logic; SDMA_CTRL5_Sl_rdComp : out std_logic; SDMA_CTRL5_Sl_rdBTerm : out std_logic; SDMA_CTRL5_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MIRQ : out std_logic_vector(0 to 0); PIM5_Addr : in std_logic_vector(31 downto 0); PIM5_AddrReq : in std_logic; PIM5_AddrAck : out std_logic; PIM5_RNW : in std_logic; PIM5_Size : in std_logic_vector(3 downto 0); PIM5_RdModWr : in std_logic; PIM5_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM5_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM5_WrFIFO_Push : in std_logic; PIM5_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM5_RdFIFO_Pop : in std_logic; PIM5_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM5_WrFIFO_Empty : out std_logic; PIM5_WrFIFO_AlmostFull : out std_logic; PIM5_WrFIFO_Flush : in std_logic; PIM5_RdFIFO_Empty : out std_logic; PIM5_RdFIFO_Flush : in std_logic; PIM5_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM5_InitDone : out std_logic; PPC440MC5_MIMCReadNotWrite : in std_logic; PPC440MC5_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC5_MIMCAddressValid : in std_logic; PPC440MC5_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC5_MIMCWriteDataValid : in std_logic; PPC440MC5_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC5_MIMCBankConflict : in std_logic; PPC440MC5_MIMCRowConflict : in std_logic; PPC440MC5_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC5_MCMIReadDataValid : out std_logic; PPC440MC5_MCMIReadDataErr : out std_logic; PPC440MC5_MCMIAddrReadyToAccept : out std_logic; VFBC5_Cmd_Clk : in std_logic; VFBC5_Cmd_Reset : in std_logic; VFBC5_Cmd_Data : in std_logic_vector(31 downto 0); VFBC5_Cmd_Write : in std_logic; VFBC5_Cmd_End : in std_logic; VFBC5_Cmd_Full : out std_logic; VFBC5_Cmd_Almost_Full : out std_logic; VFBC5_Cmd_Idle : out std_logic; VFBC5_Wd_Clk : in std_logic; VFBC5_Wd_Reset : in std_logic; VFBC5_Wd_Write : in std_logic; VFBC5_Wd_End_Burst : in std_logic; VFBC5_Wd_Flush : in std_logic; VFBC5_Wd_Data : in std_logic_vector(31 downto 0); VFBC5_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC5_Wd_Full : out std_logic; VFBC5_Wd_Almost_Full : out std_logic; VFBC5_Rd_Clk : in std_logic; VFBC5_Rd_Reset : in std_logic; VFBC5_Rd_Read : in std_logic; VFBC5_Rd_End_Burst : in std_logic; VFBC5_Rd_Flush : in std_logic; VFBC5_Rd_Data : out std_logic_vector(31 downto 0); VFBC5_Rd_Empty : out std_logic; VFBC5_Rd_Almost_Empty : out std_logic; MCB5_cmd_clk : in std_logic; MCB5_cmd_en : in std_logic; MCB5_cmd_instr : in std_logic_vector(2 downto 0); MCB5_cmd_bl : in std_logic_vector(5 downto 0); MCB5_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB5_cmd_empty : out std_logic; MCB5_cmd_full : out std_logic; MCB5_wr_clk : in std_logic; MCB5_wr_en : in std_logic; MCB5_wr_mask : in std_logic_vector(7 downto 0); MCB5_wr_data : in std_logic_vector(63 downto 0); MCB5_wr_full : out std_logic; MCB5_wr_empty : out std_logic; MCB5_wr_count : out std_logic_vector(6 downto 0); MCB5_wr_underrun : out std_logic; MCB5_wr_error : out std_logic; MCB5_rd_clk : in std_logic; MCB5_rd_en : in std_logic; MCB5_rd_data : out std_logic_vector(63 downto 0); MCB5_rd_full : out std_logic; MCB5_rd_empty : out std_logic; MCB5_rd_count : out std_logic_vector(6 downto 0); MCB5_rd_overflow : out std_logic; MCB5_rd_error : out std_logic; FSL6_M_Clk : in std_logic; FSL6_M_Write : in std_logic; FSL6_M_Data : in std_logic_vector(0 to 31); FSL6_M_Control : in std_logic; FSL6_M_Full : out std_logic; FSL6_S_Clk : in std_logic; FSL6_S_Read : in std_logic; FSL6_S_Data : out std_logic_vector(0 to 31); FSL6_S_Control : out std_logic; FSL6_S_Exists : out std_logic; FSL6_B_M_Clk : in std_logic; FSL6_B_M_Write : in std_logic; FSL6_B_M_Data : in std_logic_vector(0 to 31); FSL6_B_M_Control : in std_logic; FSL6_B_M_Full : out std_logic; FSL6_B_S_Clk : in std_logic; FSL6_B_S_Read : in std_logic; FSL6_B_S_Data : out std_logic_vector(0 to 31); FSL6_B_S_Control : out std_logic; FSL6_B_S_Exists : out std_logic; SPLB6_Clk : in std_logic; SPLB6_Rst : in std_logic; SPLB6_PLB_ABus : in std_logic_vector(0 to 31); SPLB6_PLB_PAValid : in std_logic; SPLB6_PLB_SAValid : in std_logic; SPLB6_PLB_masterID : in std_logic_vector(0 to 0); SPLB6_PLB_RNW : in std_logic; SPLB6_PLB_BE : in std_logic_vector(0 to 7); SPLB6_PLB_UABus : in std_logic_vector(0 to 31); SPLB6_PLB_rdPrim : in std_logic; SPLB6_PLB_wrPrim : in std_logic; SPLB6_PLB_abort : in std_logic; SPLB6_PLB_busLock : in std_logic; SPLB6_PLB_MSize : in std_logic_vector(0 to 1); SPLB6_PLB_size : in std_logic_vector(0 to 3); SPLB6_PLB_type : in std_logic_vector(0 to 2); SPLB6_PLB_lockErr : in std_logic; SPLB6_PLB_wrPendReq : in std_logic; SPLB6_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB6_PLB_rdPendReq : in std_logic; SPLB6_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB6_PLB_reqPri : in std_logic_vector(0 to 1); SPLB6_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB6_PLB_rdBurst : in std_logic; SPLB6_PLB_wrBurst : in std_logic; SPLB6_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB6_Sl_addrAck : out std_logic; SPLB6_Sl_SSize : out std_logic_vector(0 to 1); SPLB6_Sl_wait : out std_logic; SPLB6_Sl_rearbitrate : out std_logic; SPLB6_Sl_wrDAck : out std_logic; SPLB6_Sl_wrComp : out std_logic; SPLB6_Sl_wrBTerm : out std_logic; SPLB6_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB6_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB6_Sl_rdDAck : out std_logic; SPLB6_Sl_rdComp : out std_logic; SPLB6_Sl_rdBTerm : out std_logic; SPLB6_Sl_MBusy : out std_logic_vector(0 to 0); SPLB6_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB6_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB6_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA6_Clk : in std_logic; SDMA6_Rx_IntOut : out std_logic; SDMA6_Tx_IntOut : out std_logic; SDMA6_RstOut : out std_logic; SDMA6_TX_D : out std_logic_vector(0 to 31); SDMA6_TX_Rem : out std_logic_vector(0 to 3); SDMA6_TX_SOF : out std_logic; SDMA6_TX_EOF : out std_logic; SDMA6_TX_SOP : out std_logic; SDMA6_TX_EOP : out std_logic; SDMA6_TX_Src_Rdy : out std_logic; SDMA6_TX_Dst_Rdy : in std_logic; SDMA6_RX_D : in std_logic_vector(0 to 31); SDMA6_RX_Rem : in std_logic_vector(0 to 3); SDMA6_RX_SOF : in std_logic; SDMA6_RX_EOF : in std_logic; SDMA6_RX_SOP : in std_logic; SDMA6_RX_EOP : in std_logic; SDMA6_RX_Src_Rdy : in std_logic; SDMA6_RX_Dst_Rdy : out std_logic; SDMA_CTRL6_Clk : in std_logic; SDMA_CTRL6_Rst : in std_logic; SDMA_CTRL6_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL6_PLB_PAValid : in std_logic; SDMA_CTRL6_PLB_SAValid : in std_logic; SDMA_CTRL6_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL6_PLB_RNW : in std_logic; SDMA_CTRL6_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL6_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL6_PLB_rdPrim : in std_logic; SDMA_CTRL6_PLB_wrPrim : in std_logic; SDMA_CTRL6_PLB_abort : in std_logic; SDMA_CTRL6_PLB_busLock : in std_logic; SDMA_CTRL6_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL6_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL6_PLB_lockErr : in std_logic; SDMA_CTRL6_PLB_wrPendReq : in std_logic; SDMA_CTRL6_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_rdPendReq : in std_logic; SDMA_CTRL6_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL6_PLB_rdBurst : in std_logic; SDMA_CTRL6_PLB_wrBurst : in std_logic; SDMA_CTRL6_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL6_Sl_addrAck : out std_logic; SDMA_CTRL6_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL6_Sl_wait : out std_logic; SDMA_CTRL6_Sl_rearbitrate : out std_logic; SDMA_CTRL6_Sl_wrDAck : out std_logic; SDMA_CTRL6_Sl_wrComp : out std_logic; SDMA_CTRL6_Sl_wrBTerm : out std_logic; SDMA_CTRL6_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL6_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL6_Sl_rdDAck : out std_logic; SDMA_CTRL6_Sl_rdComp : out std_logic; SDMA_CTRL6_Sl_rdBTerm : out std_logic; SDMA_CTRL6_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MIRQ : out std_logic_vector(0 to 0); PIM6_Addr : in std_logic_vector(31 downto 0); PIM6_AddrReq : in std_logic; PIM6_AddrAck : out std_logic; PIM6_RNW : in std_logic; PIM6_Size : in std_logic_vector(3 downto 0); PIM6_RdModWr : in std_logic; PIM6_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM6_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM6_WrFIFO_Push : in std_logic; PIM6_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM6_RdFIFO_Pop : in std_logic; PIM6_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM6_WrFIFO_Empty : out std_logic; PIM6_WrFIFO_AlmostFull : out std_logic; PIM6_WrFIFO_Flush : in std_logic; PIM6_RdFIFO_Empty : out std_logic; PIM6_RdFIFO_Flush : in std_logic; PIM6_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM6_InitDone : out std_logic; PPC440MC6_MIMCReadNotWrite : in std_logic; PPC440MC6_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC6_MIMCAddressValid : in std_logic; PPC440MC6_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC6_MIMCWriteDataValid : in std_logic; PPC440MC6_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC6_MIMCBankConflict : in std_logic; PPC440MC6_MIMCRowConflict : in std_logic; PPC440MC6_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC6_MCMIReadDataValid : out std_logic; PPC440MC6_MCMIReadDataErr : out std_logic; PPC440MC6_MCMIAddrReadyToAccept : out std_logic; VFBC6_Cmd_Clk : in std_logic; VFBC6_Cmd_Reset : in std_logic; VFBC6_Cmd_Data : in std_logic_vector(31 downto 0); VFBC6_Cmd_Write : in std_logic; VFBC6_Cmd_End : in std_logic; VFBC6_Cmd_Full : out std_logic; VFBC6_Cmd_Almost_Full : out std_logic; VFBC6_Cmd_Idle : out std_logic; VFBC6_Wd_Clk : in std_logic; VFBC6_Wd_Reset : in std_logic; VFBC6_Wd_Write : in std_logic; VFBC6_Wd_End_Burst : in std_logic; VFBC6_Wd_Flush : in std_logic; VFBC6_Wd_Data : in std_logic_vector(31 downto 0); VFBC6_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC6_Wd_Full : out std_logic; VFBC6_Wd_Almost_Full : out std_logic; VFBC6_Rd_Clk : in std_logic; VFBC6_Rd_Reset : in std_logic; VFBC6_Rd_Read : in std_logic; VFBC6_Rd_End_Burst : in std_logic; VFBC6_Rd_Flush : in std_logic; VFBC6_Rd_Data : out std_logic_vector(31 downto 0); VFBC6_Rd_Empty : out std_logic; VFBC6_Rd_Almost_Empty : out std_logic; MCB6_cmd_clk : in std_logic; MCB6_cmd_en : in std_logic; MCB6_cmd_instr : in std_logic_vector(2 downto 0); MCB6_cmd_bl : in std_logic_vector(5 downto 0); MCB6_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB6_cmd_empty : out std_logic; MCB6_cmd_full : out std_logic; MCB6_wr_clk : in std_logic; MCB6_wr_en : in std_logic; MCB6_wr_mask : in std_logic_vector(7 downto 0); MCB6_wr_data : in std_logic_vector(63 downto 0); MCB6_wr_full : out std_logic; MCB6_wr_empty : out std_logic; MCB6_wr_count : out std_logic_vector(6 downto 0); MCB6_wr_underrun : out std_logic; MCB6_wr_error : out std_logic; MCB6_rd_clk : in std_logic; MCB6_rd_en : in std_logic; MCB6_rd_data : out std_logic_vector(63 downto 0); MCB6_rd_full : out std_logic; MCB6_rd_empty : out std_logic; MCB6_rd_count : out std_logic_vector(6 downto 0); MCB6_rd_overflow : out std_logic; MCB6_rd_error : out std_logic; FSL7_M_Clk : in std_logic; FSL7_M_Write : in std_logic; FSL7_M_Data : in std_logic_vector(0 to 31); FSL7_M_Control : in std_logic; FSL7_M_Full : out std_logic; FSL7_S_Clk : in std_logic; FSL7_S_Read : in std_logic; FSL7_S_Data : out std_logic_vector(0 to 31); FSL7_S_Control : out std_logic; FSL7_S_Exists : out std_logic; FSL7_B_M_Clk : in std_logic; FSL7_B_M_Write : in std_logic; FSL7_B_M_Data : in std_logic_vector(0 to 31); FSL7_B_M_Control : in std_logic; FSL7_B_M_Full : out std_logic; FSL7_B_S_Clk : in std_logic; FSL7_B_S_Read : in std_logic; FSL7_B_S_Data : out std_logic_vector(0 to 31); FSL7_B_S_Control : out std_logic; FSL7_B_S_Exists : out std_logic; SPLB7_Clk : in std_logic; SPLB7_Rst : in std_logic; SPLB7_PLB_ABus : in std_logic_vector(0 to 31); SPLB7_PLB_PAValid : in std_logic; SPLB7_PLB_SAValid : in std_logic; SPLB7_PLB_masterID : in std_logic_vector(0 to 0); SPLB7_PLB_RNW : in std_logic; SPLB7_PLB_BE : in std_logic_vector(0 to 7); SPLB7_PLB_UABus : in std_logic_vector(0 to 31); SPLB7_PLB_rdPrim : in std_logic; SPLB7_PLB_wrPrim : in std_logic; SPLB7_PLB_abort : in std_logic; SPLB7_PLB_busLock : in std_logic; SPLB7_PLB_MSize : in std_logic_vector(0 to 1); SPLB7_PLB_size : in std_logic_vector(0 to 3); SPLB7_PLB_type : in std_logic_vector(0 to 2); SPLB7_PLB_lockErr : in std_logic; SPLB7_PLB_wrPendReq : in std_logic; SPLB7_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB7_PLB_rdPendReq : in std_logic; SPLB7_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB7_PLB_reqPri : in std_logic_vector(0 to 1); SPLB7_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB7_PLB_rdBurst : in std_logic; SPLB7_PLB_wrBurst : in std_logic; SPLB7_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB7_Sl_addrAck : out std_logic; SPLB7_Sl_SSize : out std_logic_vector(0 to 1); SPLB7_Sl_wait : out std_logic; SPLB7_Sl_rearbitrate : out std_logic; SPLB7_Sl_wrDAck : out std_logic; SPLB7_Sl_wrComp : out std_logic; SPLB7_Sl_wrBTerm : out std_logic; SPLB7_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB7_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB7_Sl_rdDAck : out std_logic; SPLB7_Sl_rdComp : out std_logic; SPLB7_Sl_rdBTerm : out std_logic; SPLB7_Sl_MBusy : out std_logic_vector(0 to 0); SPLB7_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB7_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB7_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA7_Clk : in std_logic; SDMA7_Rx_IntOut : out std_logic; SDMA7_Tx_IntOut : out std_logic; SDMA7_RstOut : out std_logic; SDMA7_TX_D : out std_logic_vector(0 to 31); SDMA7_TX_Rem : out std_logic_vector(0 to 3); SDMA7_TX_SOF : out std_logic; SDMA7_TX_EOF : out std_logic; SDMA7_TX_SOP : out std_logic; SDMA7_TX_EOP : out std_logic; SDMA7_TX_Src_Rdy : out std_logic; SDMA7_TX_Dst_Rdy : in std_logic; SDMA7_RX_D : in std_logic_vector(0 to 31); SDMA7_RX_Rem : in std_logic_vector(0 to 3); SDMA7_RX_SOF : in std_logic; SDMA7_RX_EOF : in std_logic; SDMA7_RX_SOP : in std_logic; SDMA7_RX_EOP : in std_logic; SDMA7_RX_Src_Rdy : in std_logic; SDMA7_RX_Dst_Rdy : out std_logic; SDMA_CTRL7_Clk : in std_logic; SDMA_CTRL7_Rst : in std_logic; SDMA_CTRL7_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL7_PLB_PAValid : in std_logic; SDMA_CTRL7_PLB_SAValid : in std_logic; SDMA_CTRL7_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL7_PLB_RNW : in std_logic; SDMA_CTRL7_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL7_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL7_PLB_rdPrim : in std_logic; SDMA_CTRL7_PLB_wrPrim : in std_logic; SDMA_CTRL7_PLB_abort : in std_logic; SDMA_CTRL7_PLB_busLock : in std_logic; SDMA_CTRL7_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL7_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL7_PLB_lockErr : in std_logic; SDMA_CTRL7_PLB_wrPendReq : in std_logic; SDMA_CTRL7_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_rdPendReq : in std_logic; SDMA_CTRL7_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL7_PLB_rdBurst : in std_logic; SDMA_CTRL7_PLB_wrBurst : in std_logic; SDMA_CTRL7_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL7_Sl_addrAck : out std_logic; SDMA_CTRL7_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL7_Sl_wait : out std_logic; SDMA_CTRL7_Sl_rearbitrate : out std_logic; SDMA_CTRL7_Sl_wrDAck : out std_logic; SDMA_CTRL7_Sl_wrComp : out std_logic; SDMA_CTRL7_Sl_wrBTerm : out std_logic; SDMA_CTRL7_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL7_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL7_Sl_rdDAck : out std_logic; SDMA_CTRL7_Sl_rdComp : out std_logic; SDMA_CTRL7_Sl_rdBTerm : out std_logic; SDMA_CTRL7_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MIRQ : out std_logic_vector(0 to 0); PIM7_Addr : in std_logic_vector(31 downto 0); PIM7_AddrReq : in std_logic; PIM7_AddrAck : out std_logic; PIM7_RNW : in std_logic; PIM7_Size : in std_logic_vector(3 downto 0); PIM7_RdModWr : in std_logic; PIM7_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM7_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM7_WrFIFO_Push : in std_logic; PIM7_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM7_RdFIFO_Pop : in std_logic; PIM7_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM7_WrFIFO_Empty : out std_logic; PIM7_WrFIFO_AlmostFull : out std_logic; PIM7_WrFIFO_Flush : in std_logic; PIM7_RdFIFO_Empty : out std_logic; PIM7_RdFIFO_Flush : in std_logic; PIM7_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM7_InitDone : out std_logic; PPC440MC7_MIMCReadNotWrite : in std_logic; PPC440MC7_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC7_MIMCAddressValid : in std_logic; PPC440MC7_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC7_MIMCWriteDataValid : in std_logic; PPC440MC7_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC7_MIMCBankConflict : in std_logic; PPC440MC7_MIMCRowConflict : in std_logic; PPC440MC7_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC7_MCMIReadDataValid : out std_logic; PPC440MC7_MCMIReadDataErr : out std_logic; PPC440MC7_MCMIAddrReadyToAccept : out std_logic; VFBC7_Cmd_Clk : in std_logic; VFBC7_Cmd_Reset : in std_logic; VFBC7_Cmd_Data : in std_logic_vector(31 downto 0); VFBC7_Cmd_Write : in std_logic; VFBC7_Cmd_End : in std_logic; VFBC7_Cmd_Full : out std_logic; VFBC7_Cmd_Almost_Full : out std_logic; VFBC7_Cmd_Idle : out std_logic; VFBC7_Wd_Clk : in std_logic; VFBC7_Wd_Reset : in std_logic; VFBC7_Wd_Write : in std_logic; VFBC7_Wd_End_Burst : in std_logic; VFBC7_Wd_Flush : in std_logic; VFBC7_Wd_Data : in std_logic_vector(31 downto 0); VFBC7_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC7_Wd_Full : out std_logic; VFBC7_Wd_Almost_Full : out std_logic; VFBC7_Rd_Clk : in std_logic; VFBC7_Rd_Reset : in std_logic; VFBC7_Rd_Read : in std_logic; VFBC7_Rd_End_Burst : in std_logic; VFBC7_Rd_Flush : in std_logic; VFBC7_Rd_Data : out std_logic_vector(31 downto 0); VFBC7_Rd_Empty : out std_logic; VFBC7_Rd_Almost_Empty : out std_logic; MCB7_cmd_clk : in std_logic; MCB7_cmd_en : in std_logic; MCB7_cmd_instr : in std_logic_vector(2 downto 0); MCB7_cmd_bl : in std_logic_vector(5 downto 0); MCB7_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB7_cmd_empty : out std_logic; MCB7_cmd_full : out std_logic; MCB7_wr_clk : in std_logic; MCB7_wr_en : in std_logic; MCB7_wr_mask : in std_logic_vector(7 downto 0); MCB7_wr_data : in std_logic_vector(63 downto 0); MCB7_wr_full : out std_logic; MCB7_wr_empty : out std_logic; MCB7_wr_count : out std_logic_vector(6 downto 0); MCB7_wr_underrun : out std_logic; MCB7_wr_error : out std_logic; MCB7_rd_clk : in std_logic; MCB7_rd_en : in std_logic; MCB7_rd_data : out std_logic_vector(63 downto 0); MCB7_rd_full : out std_logic; MCB7_rd_empty : out std_logic; MCB7_rd_count : out std_logic_vector(6 downto 0); MCB7_rd_overflow : out std_logic; MCB7_rd_error : out std_logic; MPMC_CTRL_Clk : in std_logic; MPMC_CTRL_Rst : in std_logic; MPMC_CTRL_PLB_ABus : in std_logic_vector(0 to 31); MPMC_CTRL_PLB_PAValid : in std_logic; MPMC_CTRL_PLB_SAValid : in std_logic; MPMC_CTRL_PLB_masterID : in std_logic_vector(0 to 0); MPMC_CTRL_PLB_RNW : in std_logic; MPMC_CTRL_PLB_BE : in std_logic_vector(0 to 7); MPMC_CTRL_PLB_UABus : in std_logic_vector(0 to 31); MPMC_CTRL_PLB_rdPrim : in std_logic; MPMC_CTRL_PLB_wrPrim : in std_logic; MPMC_CTRL_PLB_abort : in std_logic; MPMC_CTRL_PLB_busLock : in std_logic; MPMC_CTRL_PLB_MSize : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_size : in std_logic_vector(0 to 3); MPMC_CTRL_PLB_type : in std_logic_vector(0 to 2); MPMC_CTRL_PLB_lockErr : in std_logic; MPMC_CTRL_PLB_wrPendReq : in std_logic; MPMC_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_rdPendReq : in std_logic; MPMC_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); MPMC_CTRL_PLB_rdBurst : in std_logic; MPMC_CTRL_PLB_wrBurst : in std_logic; MPMC_CTRL_PLB_wrDBus : in std_logic_vector(0 to 63); MPMC_CTRL_Sl_addrAck : out std_logic; MPMC_CTRL_Sl_SSize : out std_logic_vector(0 to 1); MPMC_CTRL_Sl_wait : out std_logic; MPMC_CTRL_Sl_rearbitrate : out std_logic; MPMC_CTRL_Sl_wrDAck : out std_logic; MPMC_CTRL_Sl_wrComp : out std_logic; MPMC_CTRL_Sl_wrBTerm : out std_logic; MPMC_CTRL_Sl_rdDBus : out std_logic_vector(0 to 63); MPMC_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); MPMC_CTRL_Sl_rdDAck : out std_logic; MPMC_CTRL_Sl_rdComp : out std_logic; MPMC_CTRL_Sl_rdBTerm : out std_logic; MPMC_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); MPMC_Clk0 : in std_logic; MPMC_Clk0_DIV2 : in std_logic; MPMC_Clk90 : in std_logic; MPMC_Clk_200MHz : in std_logic; MPMC_Rst : in std_logic; MPMC_Clk_Mem : in std_logic; MPMC_Clk_Mem_2x : in std_logic; MPMC_Clk_Mem_2x_180 : in std_logic; MPMC_Clk_Mem_2x_CE0 : in std_logic; MPMC_Clk_Mem_2x_CE90 : in std_logic; MPMC_Clk_Rd_Base : in std_logic; MPMC_Clk_Mem_2x_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_180_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_CE0_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_CE90_bufpll_o : out std_logic; MPMC_PLL_Lock_bufpll_o : out std_logic; MPMC_PLL_Lock : in std_logic; MPMC_Idelayctrl_Rdy_I : in std_logic; MPMC_Idelayctrl_Rdy_O : out std_logic; MPMC_InitDone : out std_logic; MPMC_ECC_Intr : out std_logic; MPMC_DCM_PSEN : out std_logic; MPMC_DCM_PSINCDEC : out std_logic; MPMC_DCM_PSDONE : in std_logic; MPMC_MCB_DRP_Clk : in std_logic; SDRAM_Clk : out std_logic_vector(1 downto 0); SDRAM_CE : out std_logic_vector(1 downto 0); SDRAM_CS_n : out std_logic_vector(1 downto 0); SDRAM_RAS_n : out std_logic; SDRAM_CAS_n : out std_logic; SDRAM_WE_n : out std_logic; SDRAM_BankAddr : out std_logic_vector(1 downto 0); SDRAM_Addr : out std_logic_vector(12 downto 0); SDRAM_DQ : inout std_logic_vector(63 downto 0); SDRAM_DM : out std_logic_vector(7 downto 0); DDR_Clk : out std_logic_vector(1 downto 0); DDR_Clk_n : out std_logic_vector(1 downto 0); DDR_CE : out std_logic_vector(1 downto 0); DDR_CS_n : out std_logic_vector(1 downto 0); DDR_RAS_n : out std_logic; DDR_CAS_n : out std_logic; DDR_WE_n : out std_logic; DDR_BankAddr : out std_logic_vector(1 downto 0); DDR_Addr : out std_logic_vector(12 downto 0); DDR_DQ : inout std_logic_vector(63 downto 0); DDR_DM : out std_logic_vector(7 downto 0); DDR_DQS : inout std_logic_vector(7 downto 0); DDR_DQS_Div_O : out std_logic; DDR_DQS_Div_I : in std_logic; DDR2_Clk : out std_logic_vector(1 downto 0); DDR2_Clk_n : out std_logic_vector(1 downto 0); DDR2_CE : out std_logic_vector(1 downto 0); DDR2_CS_n : out std_logic_vector(1 downto 0); DDR2_ODT : out std_logic_vector(1 downto 0); DDR2_RAS_n : out std_logic; DDR2_CAS_n : out std_logic; DDR2_WE_n : out std_logic; DDR2_BankAddr : out std_logic_vector(1 downto 0); DDR2_Addr : out std_logic_vector(12 downto 0); DDR2_DQ : inout std_logic_vector(63 downto 0); DDR2_DM : out std_logic_vector(7 downto 0); DDR2_DQS : inout std_logic_vector(7 downto 0); DDR2_DQS_n : inout std_logic_vector(7 downto 0); DDR2_DQS_Div_O : out std_logic; DDR2_DQS_Div_I : in std_logic; DDR3_Clk : out std_logic_vector(1 downto 0); DDR3_Clk_n : out std_logic_vector(1 downto 0); DDR3_CE : out std_logic_vector(1 downto 0); DDR3_CS_n : out std_logic_vector(1 downto 0); DDR3_ODT : out std_logic_vector(1 downto 0); DDR3_RAS_n : out std_logic; DDR3_CAS_n : out std_logic; DDR3_WE_n : out std_logic; DDR3_BankAddr : out std_logic_vector(1 downto 0); DDR3_Addr : out std_logic_vector(12 downto 0); DDR3_DQ : inout std_logic_vector(63 downto 0); DDR3_DM : out std_logic_vector(7 downto 0); DDR3_Reset_n : out std_logic; DDR3_DQS : inout std_logic_vector(7 downto 0); DDR3_DQS_n : inout std_logic_vector(7 downto 0); mcbx_dram_addr : out std_logic_vector(12 downto 0); mcbx_dram_ba : out std_logic_vector(1 downto 0); mcbx_dram_ras_n : out std_logic; mcbx_dram_cas_n : out std_logic; mcbx_dram_we_n : out std_logic; mcbx_dram_cke : out std_logic; mcbx_dram_clk : out std_logic; mcbx_dram_clk_n : out std_logic; mcbx_dram_dq : inout std_logic_vector(63 downto 0); mcbx_dram_dqs : inout std_logic; mcbx_dram_dqs_n : inout std_logic; mcbx_dram_udqs : inout std_logic; mcbx_dram_udqs_n : inout std_logic; mcbx_dram_udm : out std_logic; mcbx_dram_ldm : out std_logic; mcbx_dram_odt : out std_logic; mcbx_dram_ddr3_rst : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic; calib_recal : in std_logic; rzq : inout std_logic; zio : inout std_logic ); end component; component system_sram_wrapper is port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to 31); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to 31); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to 31); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to 31); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to 31); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to 31); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to 31); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to 31); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Mem_DQ_I : in std_logic_vector(0 to 31); Mem_DQ_O : out std_logic_vector(0 to 31); Mem_DQ_T : out std_logic_vector(0 to 31); Mem_A : out std_logic_vector(0 to 31); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to 0); Mem_OEN : out std_logic_vector(0 to 0); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to 3); Mem_BEN : out std_logic_vector(0 to 3); Mem_CE : out std_logic_vector(0 to 0); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end component; component system_pcie_bridge_wrapper is port ( MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; PLB_MTimeout : in std_logic; PLB_MIRQ : in std_logic; PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MBusy : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MWrDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrBTerm : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_buslock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_lockErr : out std_logic; M_abort : out std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_UABus : out std_logic_vector(0 to 31); M_ABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to 63); M_wrBurst : out std_logic; M_rdBurst : out std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); REFCLK : in std_logic; Bridge_Clk : out std_logic; RXN : in std_logic_vector(0 to 0); RXP : in std_logic_vector(0 to 0); TXN : out std_logic_vector(0 to 0); TXP : out std_logic_vector(0 to 0); IP2INTC_Irpt : out std_logic; MSI_request : in std_logic ); end component; component system_xps_central_dma_1_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; SPLB_ABus : in std_logic_vector(0 to 31); SPLB_BE : in std_logic_vector(0 to 7); SPLB_UABus : in std_logic_vector(0 to 31); SPLB_PAValid : in std_logic; SPLB_SAValid : in std_logic; SPLB_rdPrim : in std_logic; SPLB_wrPrim : in std_logic; SPLB_masterID : in std_logic_vector(0 to 2); SPLB_abort : in std_logic; SPLB_busLock : in std_logic; SPLB_RNW : in std_logic; SPLB_MSize : in std_logic_vector(0 to 1); SPLB_size : in std_logic_vector(0 to 3); SPLB_type : in std_logic_vector(0 to 2); SPLB_lockErr : in std_logic; SPLB_wrDBus : in std_logic_vector(0 to 63); SPLB_wrBurst : in std_logic; SPLB_rdBurst : in std_logic; SPLB_wrPendReq : in std_logic; SPLB_rdPendReq : in std_logic; SPLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_reqPri : in std_logic_vector(0 to 1); SPLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); IP2INTC_Irpt : out std_logic; MPLB_MAddrAck : in std_logic; MPLB_MSSize : in std_logic_vector(0 to 1); MPLB_MRearbitrate : in std_logic; MPLB_MTimeout : in std_logic; MPLB_MBusy : in std_logic; MPLB_MRdErr : in std_logic; MPLB_MWrErr : in std_logic; MPLB_MIRQ : in std_logic; MPLB_MRdDBus : in std_logic_vector(0 to 63); MPLB_MRdWdAddr : in std_logic_vector(0 to 3); MPLB_MRdDAck : in std_logic; MPLB_MRdBTerm : in std_logic; MPLB_MWrDAck : in std_logic; MPLB_MWrBTerm : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); M_ABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to 63); M_wrBurst : out std_logic; M_rdBurst : out std_logic ); end component; component system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; component system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; component system_proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); end component; component system_xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 63); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 5); Intr : in std_logic_vector(1 downto 0); Irq : out std_logic ); end component; component system_nfa_accept_samples_generic_hw_top_0_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_1_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_2_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_3_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_4_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_ac0_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ac0_mb_bridge_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; IP2INTC_Irpt : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 3); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 14); Sl_MWrErr : out std_logic_vector(0 to 14); Sl_MRdErr : out std_logic_vector(0 to 14); Sl_MIRQ : out std_logic_vector(0 to 14); MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_ABus : out std_logic_vector(0 to 31); M_wrBurst : out std_logic; M_rdBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to 63); PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); PLB_MBusy : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdWdAddr : in std_logic_vector(0 to 3) ); end component; component system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ac1_mb_bridge_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; IP2INTC_Irpt : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 3); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 14); Sl_MWrErr : out std_logic_vector(0 to 14); Sl_MRdErr : out std_logic_vector(0 to 14); Sl_MIRQ : out std_logic_vector(0 to 14); MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_ABus : out std_logic_vector(0 to 31); M_wrBurst : out std_logic; M_rdBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to 63); PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); PLB_MBusy : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdWdAddr : in std_logic_vector(0 to 3) ); end component; component system_nfa_accept_samples_generic_hw_top_5_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component IOBUF is port ( I : in std_logic; IO : inout std_logic; O : out std_logic; T : in std_logic ); end component; component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- Internal signals signal CLK_S : std_logic; signal Dcm_all_locked : std_logic; signal Debug_SYS_Rst : std_logic; signal Ext_BRK : std_logic; signal Ext_NM_BRK : std_logic; signal PCIe_Bridge_IP2INTC_Irpt : std_logic; signal PCIe_Diff_Clk : std_logic; signal SRAM_CLK_FB_s : std_logic; signal SRAM_CLK_OUT_s : std_logic; signal ac0_plb_MPLB_Rst : std_logic_vector(0 to 14); signal ac0_plb_M_ABus : std_logic_vector(0 to 479); signal ac0_plb_M_BE : std_logic_vector(0 to 119); signal ac0_plb_M_MSize : std_logic_vector(0 to 29); signal ac0_plb_M_RNW : std_logic_vector(0 to 14); signal ac0_plb_M_TAttribute : std_logic_vector(0 to 239); signal ac0_plb_M_UABus : std_logic_vector(0 to 479); signal ac0_plb_M_abort : std_logic_vector(0 to 14); signal ac0_plb_M_busLock : std_logic_vector(0 to 14); signal ac0_plb_M_lockErr : std_logic_vector(0 to 14); signal ac0_plb_M_priority : std_logic_vector(0 to 29); signal ac0_plb_M_rdBurst : std_logic_vector(0 to 14); signal ac0_plb_M_request : std_logic_vector(0 to 14); signal ac0_plb_M_size : std_logic_vector(0 to 59); signal ac0_plb_M_type : std_logic_vector(0 to 44); signal ac0_plb_M_wrBurst : std_logic_vector(0 to 14); signal ac0_plb_M_wrDBus : std_logic_vector(0 to 959); signal ac0_plb_PLB_ABus : std_logic_vector(0 to 31); signal ac0_plb_PLB_BE : std_logic_vector(0 to 7); signal ac0_plb_PLB_MAddrAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MBusy : std_logic_vector(0 to 14); signal ac0_plb_PLB_MIRQ : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdBTerm : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdDAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdDBus : std_logic_vector(0 to 959); signal ac0_plb_PLB_MRdErr : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59); signal ac0_plb_PLB_MRearbitrate : std_logic_vector(0 to 14); signal ac0_plb_PLB_MSSize : std_logic_vector(0 to 29); signal ac0_plb_PLB_MSize : std_logic_vector(0 to 1); signal ac0_plb_PLB_MTimeout : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrBTerm : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrDAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrErr : std_logic_vector(0 to 14); signal ac0_plb_PLB_PAValid : std_logic; signal ac0_plb_PLB_RNW : std_logic; signal ac0_plb_PLB_SAValid : std_logic; signal ac0_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal ac0_plb_PLB_UABus : std_logic_vector(0 to 31); signal ac0_plb_PLB_abort : std_logic; signal ac0_plb_PLB_busLock : std_logic; signal ac0_plb_PLB_lockErr : std_logic; signal ac0_plb_PLB_masterID : std_logic_vector(0 to 3); signal ac0_plb_PLB_rdBurst : std_logic; signal ac0_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_rdPendReq : std_logic; signal ac0_plb_PLB_rdPrim : std_logic_vector(0 to 0); signal ac0_plb_PLB_reqPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_size : std_logic_vector(0 to 3); signal ac0_plb_PLB_type : std_logic_vector(0 to 2); signal ac0_plb_PLB_wrBurst : std_logic; signal ac0_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal ac0_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_wrPendReq : std_logic; signal ac0_plb_PLB_wrPrim : std_logic_vector(0 to 0); signal ac0_plb_SPLB_Rst : std_logic_vector(0 to 0); signal ac0_plb_Sl_MBusy : std_logic_vector(0 to 14); signal ac0_plb_Sl_MIRQ : std_logic_vector(0 to 14); signal ac0_plb_Sl_MRdErr : std_logic_vector(0 to 14); signal ac0_plb_Sl_MWrErr : std_logic_vector(0 to 14); signal ac0_plb_Sl_SSize : std_logic_vector(0 to 1); signal ac0_plb_Sl_addrAck : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdBTerm : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdComp : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdDAck : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdDBus : std_logic_vector(0 to 63); signal ac0_plb_Sl_rdWdAddr : std_logic_vector(0 to 3); signal ac0_plb_Sl_rearbitrate : std_logic_vector(0 to 0); signal ac0_plb_Sl_wait : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrBTerm : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrComp : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrDAck : std_logic_vector(0 to 0); signal ac1_plb_MPLB_Rst : std_logic_vector(0 to 14); signal ac1_plb_M_ABus : std_logic_vector(0 to 479); signal ac1_plb_M_BE : std_logic_vector(0 to 119); signal ac1_plb_M_MSize : std_logic_vector(0 to 29); signal ac1_plb_M_RNW : std_logic_vector(0 to 14); signal ac1_plb_M_TAttribute : std_logic_vector(0 to 239); signal ac1_plb_M_UABus : std_logic_vector(0 to 479); signal ac1_plb_M_abort : std_logic_vector(0 to 14); signal ac1_plb_M_busLock : std_logic_vector(0 to 14); signal ac1_plb_M_lockErr : std_logic_vector(0 to 14); signal ac1_plb_M_priority : std_logic_vector(0 to 29); signal ac1_plb_M_rdBurst : std_logic_vector(0 to 14); signal ac1_plb_M_request : std_logic_vector(0 to 14); signal ac1_plb_M_size : std_logic_vector(0 to 59); signal ac1_plb_M_type : std_logic_vector(0 to 44); signal ac1_plb_M_wrBurst : std_logic_vector(0 to 14); signal ac1_plb_M_wrDBus : std_logic_vector(0 to 959); signal ac1_plb_PLB_ABus : std_logic_vector(0 to 31); signal ac1_plb_PLB_BE : std_logic_vector(0 to 7); signal ac1_plb_PLB_MAddrAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MBusy : std_logic_vector(0 to 14); signal ac1_plb_PLB_MIRQ : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdBTerm : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdDAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdDBus : std_logic_vector(0 to 959); signal ac1_plb_PLB_MRdErr : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59); signal ac1_plb_PLB_MRearbitrate : std_logic_vector(0 to 14); signal ac1_plb_PLB_MSSize : std_logic_vector(0 to 29); signal ac1_plb_PLB_MSize : std_logic_vector(0 to 1); signal ac1_plb_PLB_MTimeout : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrBTerm : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrDAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrErr : std_logic_vector(0 to 14); signal ac1_plb_PLB_PAValid : std_logic; signal ac1_plb_PLB_RNW : std_logic; signal ac1_plb_PLB_SAValid : std_logic; signal ac1_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal ac1_plb_PLB_UABus : std_logic_vector(0 to 31); signal ac1_plb_PLB_abort : std_logic; signal ac1_plb_PLB_busLock : std_logic; signal ac1_plb_PLB_lockErr : std_logic; signal ac1_plb_PLB_masterID : std_logic_vector(0 to 3); signal ac1_plb_PLB_rdBurst : std_logic; signal ac1_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_rdPendReq : std_logic; signal ac1_plb_PLB_rdPrim : std_logic_vector(0 to 0); signal ac1_plb_PLB_reqPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_size : std_logic_vector(0 to 3); signal ac1_plb_PLB_type : std_logic_vector(0 to 2); signal ac1_plb_PLB_wrBurst : std_logic; signal ac1_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal ac1_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_wrPendReq : std_logic; signal ac1_plb_PLB_wrPrim : std_logic_vector(0 to 0); signal ac1_plb_SPLB_Rst : std_logic_vector(0 to 0); signal ac1_plb_Sl_MBusy : std_logic_vector(0 to 14); signal ac1_plb_Sl_MIRQ : std_logic_vector(0 to 14); signal ac1_plb_Sl_MRdErr : std_logic_vector(0 to 14); signal ac1_plb_Sl_MWrErr : std_logic_vector(0 to 14); signal ac1_plb_Sl_SSize : std_logic_vector(0 to 1); signal ac1_plb_Sl_addrAck : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdBTerm : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdComp : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdDAck : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdDBus : std_logic_vector(0 to 63); signal ac1_plb_Sl_rdWdAddr : std_logic_vector(0 to 3); signal ac1_plb_Sl_rearbitrate : std_logic_vector(0 to 0); signal ac1_plb_Sl_wait : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrBTerm : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrComp : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrDAck : std_logic_vector(0 to 0); signal clk_62_5000MHzPLL0 : std_logic; signal clk_125_0000MHz90PLL0 : std_logic; signal clk_125_0000MHzPLL0 : std_logic; signal clk_200_0000MHz : std_logic; signal dlmb_LMB_ABus : std_logic_vector(0 to 31); signal dlmb_LMB_AddrStrobe : std_logic; signal dlmb_LMB_BE : std_logic_vector(0 to 3); signal dlmb_LMB_CE : std_logic; signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal dlmb_LMB_ReadStrobe : std_logic; signal dlmb_LMB_Ready : std_logic; signal dlmb_LMB_Rst : std_logic; signal dlmb_LMB_UE : std_logic; signal dlmb_LMB_Wait : std_logic; signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal dlmb_LMB_WriteStrobe : std_logic; signal dlmb_M_ABus : std_logic_vector(0 to 31); signal dlmb_M_AddrStrobe : std_logic; signal dlmb_M_BE : std_logic_vector(0 to 3); signal dlmb_M_DBus : std_logic_vector(0 to 31); signal dlmb_M_ReadStrobe : std_logic; signal dlmb_M_WriteStrobe : std_logic; signal dlmb_Sl_CE : std_logic_vector(0 to 0); signal dlmb_Sl_DBus : std_logic_vector(0 to 31); signal dlmb_Sl_Ready : std_logic_vector(0 to 0); signal dlmb_Sl_UE : std_logic_vector(0 to 0); signal dlmb_Sl_Wait : std_logic_vector(0 to 0); signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Clk : std_logic; signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal dlmb_port_BRAM_EN : std_logic; signal dlmb_port_BRAM_Rst : std_logic; signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat : std_logic_vector(7 to 30); signal fpga_0_SRAM_Mem_DQ_pin_I : std_logic_vector(0 to 31); signal fpga_0_SRAM_Mem_DQ_pin_O : std_logic_vector(0 to 31); signal fpga_0_SRAM_Mem_DQ_pin_T : std_logic_vector(0 to 31); signal ilmb_LMB_ABus : std_logic_vector(0 to 31); signal ilmb_LMB_AddrStrobe : std_logic; signal ilmb_LMB_BE : std_logic_vector(0 to 3); signal ilmb_LMB_CE : std_logic; signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal ilmb_LMB_ReadStrobe : std_logic; signal ilmb_LMB_Ready : std_logic; signal ilmb_LMB_Rst : std_logic; signal ilmb_LMB_UE : std_logic; signal ilmb_LMB_Wait : std_logic; signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal ilmb_LMB_WriteStrobe : std_logic; signal ilmb_M_ABus : std_logic_vector(0 to 31); signal ilmb_M_AddrStrobe : std_logic; signal ilmb_M_ReadStrobe : std_logic; signal ilmb_Sl_CE : std_logic_vector(0 to 0); signal ilmb_Sl_DBus : std_logic_vector(0 to 31); signal ilmb_Sl_Ready : std_logic_vector(0 to 0); signal ilmb_Sl_UE : std_logic_vector(0 to 0); signal ilmb_Sl_Wait : std_logic_vector(0 to 0); signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Clk : std_logic; signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal ilmb_port_BRAM_EN : std_logic; signal ilmb_port_BRAM_Rst : std_logic; signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal mb_plb_MPLB_Rst : std_logic_vector(0 to 5); signal mb_plb_M_ABort : std_logic_vector(0 to 5); signal mb_plb_M_ABus : std_logic_vector(0 to 191); signal mb_plb_M_BE : std_logic_vector(0 to 47); signal mb_plb_M_MSize : std_logic_vector(0 to 11); signal mb_plb_M_RNW : std_logic_vector(0 to 5); signal mb_plb_M_TAttribute : std_logic_vector(0 to 95); signal mb_plb_M_UABus : std_logic_vector(0 to 191); signal mb_plb_M_busLock : std_logic_vector(0 to 5); signal mb_plb_M_lockErr : std_logic_vector(0 to 5); signal mb_plb_M_priority : std_logic_vector(0 to 11); signal mb_plb_M_rdBurst : std_logic_vector(0 to 5); signal mb_plb_M_request : std_logic_vector(0 to 5); signal mb_plb_M_size : std_logic_vector(0 to 23); signal mb_plb_M_type : std_logic_vector(0 to 17); signal mb_plb_M_wrBurst : std_logic_vector(0 to 5); signal mb_plb_M_wrDBus : std_logic_vector(0 to 383); signal mb_plb_PLB_ABus : std_logic_vector(0 to 31); signal mb_plb_PLB_BE : std_logic_vector(0 to 7); signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MBusy : std_logic_vector(0 to 5); signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 383); signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 23); signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 5); signal mb_plb_PLB_MSSize : std_logic_vector(0 to 11); signal mb_plb_PLB_MSize : std_logic_vector(0 to 1); signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 5); signal mb_plb_PLB_PAValid : std_logic; signal mb_plb_PLB_RNW : std_logic; signal mb_plb_PLB_SAValid : std_logic; signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal mb_plb_PLB_UABus : std_logic_vector(0 to 31); signal mb_plb_PLB_abort : std_logic; signal mb_plb_PLB_busLock : std_logic; signal mb_plb_PLB_lockErr : std_logic; signal mb_plb_PLB_masterID : std_logic_vector(0 to 2); signal mb_plb_PLB_rdBurst : std_logic; signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_rdPendReq : std_logic; signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 11); signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1); signal mb_plb_PLB_size : std_logic_vector(0 to 3); signal mb_plb_PLB_type : std_logic_vector(0 to 2); signal mb_plb_PLB_wrBurst : std_logic; signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_wrPendReq : std_logic; signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 11); signal mb_plb_SPLB_Rst : std_logic_vector(0 to 11); signal mb_plb_Sl_MBusy : std_logic_vector(0 to 71); signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 71); signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 71); signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 71); signal mb_plb_Sl_SSize : std_logic_vector(0 to 23); signal mb_plb_Sl_addrAck : std_logic_vector(0 to 11); signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 11); signal mb_plb_Sl_rdComp : std_logic_vector(0 to 11); signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 11); signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 767); signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 47); signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 11); signal mb_plb_Sl_wait : std_logic_vector(0 to 11); signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 11); signal mb_plb_Sl_wrComp : std_logic_vector(0 to 11); signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 11); signal mb_reset : std_logic; signal microblaze_0_Interrupt : std_logic; signal microblaze_0_mdm_bus_Dbg_Capture : std_logic; signal microblaze_0_mdm_bus_Dbg_Clk : std_logic; signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7); signal microblaze_0_mdm_bus_Dbg_Shift : std_logic; signal microblaze_0_mdm_bus_Dbg_TDI : std_logic; signal microblaze_0_mdm_bus_Dbg_TDO : std_logic; signal microblaze_0_mdm_bus_Dbg_Update : std_logic; signal microblaze_0_mdm_bus_Debug_Rst : std_logic; signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 downto 0); signal net_gnd2 : std_logic_vector(0 to 1); signal net_gnd3 : std_logic_vector(2 downto 0); signal net_gnd4 : std_logic_vector(0 to 3); signal net_gnd6 : std_logic_vector(5 downto 0); signal net_gnd8 : std_logic_vector(0 to 7); signal net_gnd10 : std_logic_vector(0 to 9); signal net_gnd16 : std_logic_vector(0 to 15); signal net_gnd30 : std_logic_vector(29 downto 0); signal net_gnd32 : std_logic_vector(0 to 31); signal net_gnd36 : std_logic_vector(0 to 35); signal net_gnd64 : std_logic_vector(0 to 63); signal net_gnd128 : std_logic_vector(0 to 127); signal net_gnd4096 : std_logic_vector(0 to 4095); signal net_vcc0 : std_logic; signal net_vcc4 : std_logic_vector(0 to 3); signal pgassign1 : std_logic_vector(0 to 0); signal pgassign2 : std_logic_vector(0 to 0); signal pgassign3 : std_logic_vector(0 to 0); signal pgassign4 : std_logic_vector(0 to 0); signal pgassign5 : std_logic_vector(0 to 0); signal pgassign6 : std_logic_vector(0 to 0); signal pgassign7 : std_logic_vector(0 to 6); signal pgassign8 : std_logic_vector(0 to 0); signal pgassign9 : std_logic_vector(0 to 31); signal pgassign10 : std_logic_vector(1 downto 0); signal proc_sys_reset_0_Peripheral_aresetn : std_logic_vector(0 to 0); signal sys_bus_reset : std_logic_vector(0 to 0); signal sys_periph_reset : std_logic_vector(0 to 0); signal sys_rst_s : std_logic; signal xps_central_dma_1_IP2INTC_Irpt : std_logic; begin -- Internal assignments fpga_0_SRAM_Mem_A_pin <= fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat; fpga_0_SRAM_ZBT_CLK_OUT_pin <= SRAM_CLK_OUT_s; SRAM_CLK_FB_s <= fpga_0_SRAM_ZBT_CLK_FB_pin; CLK_S <= fpga_0_clk_1_sys_clk_pin; sys_rst_s <= fpga_0_rst_1_sys_rst_pin; pgassign7(0 to 6) <= B"0000000"; pgassign8(0 to 0) <= B"0"; fpga_0_SRAM_Mem_CEN_pin <= pgassign1(0); fpga_0_SRAM_Mem_OEN_pin <= pgassign2(0); pgassign3(0) <= fpga_0_PCIe_Bridge_RXN_pin; pgassign4(0) <= fpga_0_PCIe_Bridge_RXP_pin; fpga_0_PCIe_Bridge_TXN_pin <= pgassign5(0); fpga_0_PCIe_Bridge_TXP_pin <= pgassign6(0); fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat(7 to 30) <= pgassign9(7 to 30); pgassign10(1) <= PCIe_Bridge_IP2INTC_Irpt; pgassign10(0) <= xps_central_dma_1_IP2INTC_Irpt; net_gnd0 <= '0'; net_gnd1(0 downto 0) <= B"0"; net_gnd10(0 to 9) <= B"0000000000"; net_gnd128(0 to 127) <= B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; net_gnd16(0 to 15) <= B"0000000000000000"; net_gnd2(0 to 1) <= B"00"; net_gnd3(2 downto 0) <= B"000"; net_gnd30(29 downto 0) <= B"000000000000000000000000000000"; net_gnd32(0 to 31) <= B"00000000000000000000000000000000"; net_gnd36(0 to 35) <= B"000000000000000000000000000000000000"; net_gnd4(0 to 3) <= B"0000"; net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; net_gnd6(5 downto 0) <= B"000000"; net_gnd64(0 to 63) <= B"0000000000000000000000000000000000000000000000000000000000000000"; net_gnd8(0 to 7) <= B"00000000"; net_vcc0 <= '1'; net_vcc4(0 to 3) <= B"1111"; microblaze_0 : system_microblaze_0_wrapper port map ( CLK => clk_125_0000MHzPLL0, RESET => dlmb_LMB_Rst, MB_RESET => mb_reset, INTERRUPT => microblaze_0_Interrupt, INTERRUPT_ADDRESS => net_gnd32, INTERRUPT_ACK => open, EXT_BRK => Ext_BRK, EXT_NM_BRK => Ext_NM_BRK, DBG_STOP => net_gnd0, MB_Halted => open, MB_Error => open, WAKEUP => net_gnd2, SLEEP => open, DBG_WAKEUP => open, LOCKSTEP_MASTER_OUT => open, LOCKSTEP_SLAVE_IN => net_gnd4096, LOCKSTEP_OUT => open, INSTR => ilmb_LMB_ReadDBus, IREADY => ilmb_LMB_Ready, IWAIT => ilmb_LMB_Wait, ICE => ilmb_LMB_CE, IUE => ilmb_LMB_UE, INSTR_ADDR => ilmb_M_ABus, IFETCH => ilmb_M_ReadStrobe, I_AS => ilmb_M_AddrStrobe, IPLB_M_ABort => mb_plb_M_ABort(1), IPLB_M_ABus => mb_plb_M_ABus(32 to 63), IPLB_M_UABus => mb_plb_M_UABus(32 to 63), IPLB_M_BE => mb_plb_M_BE(8 to 15), IPLB_M_busLock => mb_plb_M_busLock(1), IPLB_M_lockErr => mb_plb_M_lockErr(1), IPLB_M_MSize => mb_plb_M_MSize(2 to 3), IPLB_M_priority => mb_plb_M_priority(2 to 3), IPLB_M_rdBurst => mb_plb_M_rdBurst(1), IPLB_M_request => mb_plb_M_request(1), IPLB_M_RNW => mb_plb_M_RNW(1), IPLB_M_size => mb_plb_M_size(4 to 7), IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31), IPLB_M_type => mb_plb_M_type(3 to 5), IPLB_M_wrBurst => mb_plb_M_wrBurst(1), IPLB_M_wrDBus => mb_plb_M_wrDBus(64 to 127), IPLB_MBusy => mb_plb_PLB_MBusy(1), IPLB_MRdErr => mb_plb_PLB_MRdErr(1), IPLB_MWrErr => mb_plb_PLB_MWrErr(1), IPLB_MIRQ => mb_plb_PLB_MIRQ(1), IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1), IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1), IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1), IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1), IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1), IPLB_MRdDBus => mb_plb_PLB_MRdDBus(64 to 127), IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7), IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1), IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3), IPLB_MTimeout => mb_plb_PLB_MTimeout(1), DATA_READ => dlmb_LMB_ReadDBus, DREADY => dlmb_LMB_Ready, DWAIT => dlmb_LMB_Wait, DCE => dlmb_LMB_CE, DUE => dlmb_LMB_UE, DATA_WRITE => dlmb_M_DBus, DATA_ADDR => dlmb_M_ABus, D_AS => dlmb_M_AddrStrobe, READ_STROBE => dlmb_M_ReadStrobe, WRITE_STROBE => dlmb_M_WriteStrobe, BYTE_ENABLE => dlmb_M_BE, DPLB_M_ABort => mb_plb_M_ABort(0), DPLB_M_ABus => mb_plb_M_ABus(0 to 31), DPLB_M_UABus => mb_plb_M_UABus(0 to 31), DPLB_M_BE => mb_plb_M_BE(0 to 7), DPLB_M_busLock => mb_plb_M_busLock(0), DPLB_M_lockErr => mb_plb_M_lockErr(0), DPLB_M_MSize => mb_plb_M_MSize(0 to 1), DPLB_M_priority => mb_plb_M_priority(0 to 1), DPLB_M_rdBurst => mb_plb_M_rdBurst(0), DPLB_M_request => mb_plb_M_request(0), DPLB_M_RNW => mb_plb_M_RNW(0), DPLB_M_size => mb_plb_M_size(0 to 3), DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15), DPLB_M_type => mb_plb_M_type(0 to 2), DPLB_M_wrBurst => mb_plb_M_wrBurst(0), DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 63), DPLB_MBusy => mb_plb_PLB_MBusy(0), DPLB_MRdErr => mb_plb_PLB_MRdErr(0), DPLB_MWrErr => mb_plb_PLB_MWrErr(0), DPLB_MIRQ => mb_plb_PLB_MIRQ(0), DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0), DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0), DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0), DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0), DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0), DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 63), DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3), DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0), DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1), DPLB_MTimeout => mb_plb_PLB_MTimeout(0), M_AXI_IP_AWID => open, M_AXI_IP_AWADDR => open, M_AXI_IP_AWLEN => open, M_AXI_IP_AWSIZE => open, M_AXI_IP_AWBURST => open, M_AXI_IP_AWLOCK => open, M_AXI_IP_AWCACHE => open, M_AXI_IP_AWPROT => open, M_AXI_IP_AWQOS => open, M_AXI_IP_AWVALID => open, M_AXI_IP_AWREADY => net_gnd0, M_AXI_IP_WDATA => open, M_AXI_IP_WSTRB => open, M_AXI_IP_WLAST => open, M_AXI_IP_WVALID => open, M_AXI_IP_WREADY => net_gnd0, M_AXI_IP_BID => net_gnd1(0 downto 0), M_AXI_IP_BRESP => net_gnd2(0 to 1), M_AXI_IP_BVALID => net_gnd0, M_AXI_IP_BREADY => open, M_AXI_IP_ARID => open, M_AXI_IP_ARADDR => open, M_AXI_IP_ARLEN => open, M_AXI_IP_ARSIZE => open, M_AXI_IP_ARBURST => open, M_AXI_IP_ARLOCK => open, M_AXI_IP_ARCACHE => open, M_AXI_IP_ARPROT => open, M_AXI_IP_ARQOS => open, M_AXI_IP_ARVALID => open, M_AXI_IP_ARREADY => net_gnd0, M_AXI_IP_RID => net_gnd1(0 downto 0), M_AXI_IP_RDATA => net_gnd32(0 to 31), M_AXI_IP_RRESP => net_gnd2(0 to 1), M_AXI_IP_RLAST => net_gnd0, M_AXI_IP_RVALID => net_gnd0, M_AXI_IP_RREADY => open, M_AXI_DP_AWID => open, M_AXI_DP_AWADDR => open, M_AXI_DP_AWLEN => open, M_AXI_DP_AWSIZE => open, M_AXI_DP_AWBURST => open, M_AXI_DP_AWLOCK => open, M_AXI_DP_AWCACHE => open, M_AXI_DP_AWPROT => open, M_AXI_DP_AWQOS => open, M_AXI_DP_AWVALID => open, M_AXI_DP_AWREADY => net_gnd0, M_AXI_DP_WDATA => open, M_AXI_DP_WSTRB => open, M_AXI_DP_WLAST => open, M_AXI_DP_WVALID => open, M_AXI_DP_WREADY => net_gnd0, M_AXI_DP_BID => net_gnd1(0 downto 0), M_AXI_DP_BRESP => net_gnd2(0 to 1), M_AXI_DP_BVALID => net_gnd0, M_AXI_DP_BREADY => open, M_AXI_DP_ARID => open, M_AXI_DP_ARADDR => open, M_AXI_DP_ARLEN => open, M_AXI_DP_ARSIZE => open, M_AXI_DP_ARBURST => open, M_AXI_DP_ARLOCK => open, M_AXI_DP_ARCACHE => open, M_AXI_DP_ARPROT => open, M_AXI_DP_ARQOS => open, M_AXI_DP_ARVALID => open, M_AXI_DP_ARREADY => net_gnd0, M_AXI_DP_RID => net_gnd1(0 downto 0), M_AXI_DP_RDATA => net_gnd32(0 to 31), M_AXI_DP_RRESP => net_gnd2(0 to 1), M_AXI_DP_RLAST => net_gnd0, M_AXI_DP_RVALID => net_gnd0, M_AXI_DP_RREADY => open, M_AXI_IC_AWID => open, M_AXI_IC_AWADDR => open, M_AXI_IC_AWLEN => open, M_AXI_IC_AWSIZE => open, M_AXI_IC_AWBURST => open, M_AXI_IC_AWLOCK => open, M_AXI_IC_AWCACHE => open, M_AXI_IC_AWPROT => open, M_AXI_IC_AWQOS => open, M_AXI_IC_AWVALID => open, M_AXI_IC_AWREADY => net_gnd0, M_AXI_IC_AWUSER => open, M_AXI_IC_AWDOMAIN => open, M_AXI_IC_AWSNOOP => open, M_AXI_IC_AWBAR => open, M_AXI_IC_WDATA => open, M_AXI_IC_WSTRB => open, M_AXI_IC_WLAST => open, M_AXI_IC_WVALID => open, M_AXI_IC_WREADY => net_gnd0, M_AXI_IC_WUSER => open, M_AXI_IC_BID => net_gnd1(0 downto 0), M_AXI_IC_BRESP => net_gnd2(0 to 1), M_AXI_IC_BVALID => net_gnd0, M_AXI_IC_BREADY => open, M_AXI_IC_BUSER => net_gnd1(0 downto 0), M_AXI_IC_WACK => open, M_AXI_IC_ARID => open, M_AXI_IC_ARADDR => open, M_AXI_IC_ARLEN => open, M_AXI_IC_ARSIZE => open, M_AXI_IC_ARBURST => open, M_AXI_IC_ARLOCK => open, M_AXI_IC_ARCACHE => open, M_AXI_IC_ARPROT => open, M_AXI_IC_ARQOS => open, M_AXI_IC_ARVALID => open, M_AXI_IC_ARREADY => net_gnd0, M_AXI_IC_ARUSER => open, M_AXI_IC_ARDOMAIN => open, M_AXI_IC_ARSNOOP => open, M_AXI_IC_ARBAR => open, M_AXI_IC_RID => net_gnd1(0 downto 0), M_AXI_IC_RDATA => net_gnd32(0 to 31), M_AXI_IC_RRESP => net_gnd2(0 to 1), M_AXI_IC_RLAST => net_gnd0, M_AXI_IC_RVALID => net_gnd0, M_AXI_IC_RREADY => open, M_AXI_IC_RUSER => net_gnd1(0 downto 0), M_AXI_IC_RACK => open, M_AXI_IC_ACVALID => net_gnd0, M_AXI_IC_ACADDR => net_gnd32(0 to 31), M_AXI_IC_ACSNOOP => net_gnd4(0 to 3), M_AXI_IC_ACPROT => net_gnd3, M_AXI_IC_ACREADY => open, M_AXI_IC_CRREADY => net_gnd0, M_AXI_IC_CRVALID => open, M_AXI_IC_CRRESP => open, M_AXI_IC_CDVALID => open, M_AXI_IC_CDREADY => net_gnd0, M_AXI_IC_CDDATA => open, M_AXI_IC_CDLAST => open, M_AXI_DC_AWID => open, M_AXI_DC_AWADDR => open, M_AXI_DC_AWLEN => open, M_AXI_DC_AWSIZE => open, M_AXI_DC_AWBURST => open, M_AXI_DC_AWLOCK => open, M_AXI_DC_AWCACHE => open, M_AXI_DC_AWPROT => open, M_AXI_DC_AWQOS => open, M_AXI_DC_AWVALID => open, M_AXI_DC_AWREADY => net_gnd0, M_AXI_DC_AWUSER => open, M_AXI_DC_AWDOMAIN => open, M_AXI_DC_AWSNOOP => open, M_AXI_DC_AWBAR => open, M_AXI_DC_WDATA => open, M_AXI_DC_WSTRB => open, M_AXI_DC_WLAST => open, M_AXI_DC_WVALID => open, M_AXI_DC_WREADY => net_gnd0, M_AXI_DC_WUSER => open, M_AXI_DC_BID => net_gnd1(0 downto 0), M_AXI_DC_BRESP => net_gnd2(0 to 1), M_AXI_DC_BVALID => net_gnd0, M_AXI_DC_BREADY => open, M_AXI_DC_BUSER => net_gnd1(0 downto 0), M_AXI_DC_WACK => open, M_AXI_DC_ARID => open, M_AXI_DC_ARADDR => open, M_AXI_DC_ARLEN => open, M_AXI_DC_ARSIZE => open, M_AXI_DC_ARBURST => open, M_AXI_DC_ARLOCK => open, M_AXI_DC_ARCACHE => open, M_AXI_DC_ARPROT => open, M_AXI_DC_ARQOS => open, M_AXI_DC_ARVALID => open, M_AXI_DC_ARREADY => net_gnd0, M_AXI_DC_ARUSER => open, M_AXI_DC_ARDOMAIN => open, M_AXI_DC_ARSNOOP => open, M_AXI_DC_ARBAR => open, M_AXI_DC_RID => net_gnd1(0 downto 0), M_AXI_DC_RDATA => net_gnd32(0 to 31), M_AXI_DC_RRESP => net_gnd2(0 to 1), M_AXI_DC_RLAST => net_gnd0, M_AXI_DC_RVALID => net_gnd0, M_AXI_DC_RREADY => open, M_AXI_DC_RUSER => net_gnd1(0 downto 0), M_AXI_DC_RACK => open, M_AXI_DC_ACVALID => net_gnd0, M_AXI_DC_ACADDR => net_gnd32(0 to 31), M_AXI_DC_ACSNOOP => net_gnd4(0 to 3), M_AXI_DC_ACPROT => net_gnd3, M_AXI_DC_ACREADY => open, M_AXI_DC_CRREADY => net_gnd0, M_AXI_DC_CRVALID => open, M_AXI_DC_CRRESP => open, M_AXI_DC_CDVALID => open, M_AXI_DC_CDREADY => net_gnd0, M_AXI_DC_CDDATA => open, M_AXI_DC_CDLAST => open, DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk, DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI, DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO, DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En, DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift, DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture, DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update, DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst, Trace_Instruction => open, Trace_Valid_Instr => open, Trace_PC => open, Trace_Reg_Write => open, Trace_Reg_Addr => open, Trace_MSR_Reg => open, Trace_PID_Reg => open, Trace_New_Reg_Value => open, Trace_Exception_Taken => open, Trace_Exception_Kind => open, Trace_Jump_Taken => open, Trace_Delay_Slot => open, Trace_Data_Address => open, Trace_Data_Access => open, Trace_Data_Read => open, Trace_Data_Write => open, Trace_Data_Write_Value => open, Trace_Data_Byte_Enable => open, Trace_DCache_Req => open, Trace_DCache_Hit => open, Trace_DCache_Rdy => open, Trace_DCache_Read => open, Trace_ICache_Req => open, Trace_ICache_Hit => open, Trace_ICache_Rdy => open, Trace_OF_PipeRun => open, Trace_EX_PipeRun => open, Trace_MEM_PipeRun => open, Trace_MB_Halted => open, Trace_Jump_Hit => open, FSL0_S_CLK => open, FSL0_S_READ => open, FSL0_S_DATA => net_gnd32, FSL0_S_CONTROL => net_gnd0, FSL0_S_EXISTS => net_gnd0, FSL0_M_CLK => open, FSL0_M_WRITE => open, FSL0_M_DATA => open, FSL0_M_CONTROL => open, FSL0_M_FULL => net_gnd0, FSL1_S_CLK => open, FSL1_S_READ => open, FSL1_S_DATA => net_gnd32, FSL1_S_CONTROL => net_gnd0, FSL1_S_EXISTS => net_gnd0, FSL1_M_CLK => open, FSL1_M_WRITE => open, FSL1_M_DATA => open, FSL1_M_CONTROL => open, FSL1_M_FULL => net_gnd0, FSL2_S_CLK => open, FSL2_S_READ => open, FSL2_S_DATA => net_gnd32, FSL2_S_CONTROL => net_gnd0, FSL2_S_EXISTS => net_gnd0, FSL2_M_CLK => open, FSL2_M_WRITE => open, FSL2_M_DATA => open, FSL2_M_CONTROL => open, FSL2_M_FULL => net_gnd0, FSL3_S_CLK => open, FSL3_S_READ => open, FSL3_S_DATA => net_gnd32, FSL3_S_CONTROL => net_gnd0, FSL3_S_EXISTS => net_gnd0, FSL3_M_CLK => open, FSL3_M_WRITE => open, FSL3_M_DATA => open, FSL3_M_CONTROL => open, FSL3_M_FULL => net_gnd0, FSL4_S_CLK => open, FSL4_S_READ => open, FSL4_S_DATA => net_gnd32, FSL4_S_CONTROL => net_gnd0, FSL4_S_EXISTS => net_gnd0, FSL4_M_CLK => open, FSL4_M_WRITE => open, FSL4_M_DATA => open, FSL4_M_CONTROL => open, FSL4_M_FULL => net_gnd0, FSL5_S_CLK => open, FSL5_S_READ => open, FSL5_S_DATA => net_gnd32, FSL5_S_CONTROL => net_gnd0, FSL5_S_EXISTS => net_gnd0, FSL5_M_CLK => open, FSL5_M_WRITE => open, FSL5_M_DATA => open, FSL5_M_CONTROL => open, FSL5_M_FULL => net_gnd0, FSL6_S_CLK => open, FSL6_S_READ => open, FSL6_S_DATA => net_gnd32, FSL6_S_CONTROL => net_gnd0, FSL6_S_EXISTS => net_gnd0, FSL6_M_CLK => open, FSL6_M_WRITE => open, FSL6_M_DATA => open, FSL6_M_CONTROL => open, FSL6_M_FULL => net_gnd0, FSL7_S_CLK => open, FSL7_S_READ => open, FSL7_S_DATA => net_gnd32, FSL7_S_CONTROL => net_gnd0, FSL7_S_EXISTS => net_gnd0, FSL7_M_CLK => open, FSL7_M_WRITE => open, FSL7_M_DATA => open, FSL7_M_CONTROL => open, FSL7_M_FULL => net_gnd0, FSL8_S_CLK => open, FSL8_S_READ => open, FSL8_S_DATA => net_gnd32, FSL8_S_CONTROL => net_gnd0, FSL8_S_EXISTS => net_gnd0, FSL8_M_CLK => open, FSL8_M_WRITE => open, FSL8_M_DATA => open, FSL8_M_CONTROL => open, FSL8_M_FULL => net_gnd0, FSL9_S_CLK => open, FSL9_S_READ => open, FSL9_S_DATA => net_gnd32, FSL9_S_CONTROL => net_gnd0, FSL9_S_EXISTS => net_gnd0, FSL9_M_CLK => open, FSL9_M_WRITE => open, FSL9_M_DATA => open, FSL9_M_CONTROL => open, FSL9_M_FULL => net_gnd0, FSL10_S_CLK => open, FSL10_S_READ => open, FSL10_S_DATA => net_gnd32, FSL10_S_CONTROL => net_gnd0, FSL10_S_EXISTS => net_gnd0, FSL10_M_CLK => open, FSL10_M_WRITE => open, FSL10_M_DATA => open, FSL10_M_CONTROL => open, FSL10_M_FULL => net_gnd0, FSL11_S_CLK => open, FSL11_S_READ => open, FSL11_S_DATA => net_gnd32, FSL11_S_CONTROL => net_gnd0, FSL11_S_EXISTS => net_gnd0, FSL11_M_CLK => open, FSL11_M_WRITE => open, FSL11_M_DATA => open, FSL11_M_CONTROL => open, FSL11_M_FULL => net_gnd0, FSL12_S_CLK => open, FSL12_S_READ => open, FSL12_S_DATA => net_gnd32, FSL12_S_CONTROL => net_gnd0, FSL12_S_EXISTS => net_gnd0, FSL12_M_CLK => open, FSL12_M_WRITE => open, FSL12_M_DATA => open, FSL12_M_CONTROL => open, FSL12_M_FULL => net_gnd0, FSL13_S_CLK => open, FSL13_S_READ => open, FSL13_S_DATA => net_gnd32, FSL13_S_CONTROL => net_gnd0, FSL13_S_EXISTS => net_gnd0, FSL13_M_CLK => open, FSL13_M_WRITE => open, FSL13_M_DATA => open, FSL13_M_CONTROL => open, FSL13_M_FULL => net_gnd0, FSL14_S_CLK => open, FSL14_S_READ => open, FSL14_S_DATA => net_gnd32, FSL14_S_CONTROL => net_gnd0, FSL14_S_EXISTS => net_gnd0, FSL14_M_CLK => open, FSL14_M_WRITE => open, FSL14_M_DATA => open, FSL14_M_CONTROL => open, FSL14_M_FULL => net_gnd0, FSL15_S_CLK => open, FSL15_S_READ => open, FSL15_S_DATA => net_gnd32, FSL15_S_CONTROL => net_gnd0, FSL15_S_EXISTS => net_gnd0, FSL15_M_CLK => open, FSL15_M_WRITE => open, FSL15_M_DATA => open, FSL15_M_CONTROL => open, FSL15_M_FULL => net_gnd0, M0_AXIS_TLAST => open, M0_AXIS_TDATA => open, M0_AXIS_TVALID => open, M0_AXIS_TREADY => net_gnd0, S0_AXIS_TLAST => net_gnd0, S0_AXIS_TDATA => net_gnd32(0 to 31), S0_AXIS_TVALID => net_gnd0, S0_AXIS_TREADY => open, M1_AXIS_TLAST => open, M1_AXIS_TDATA => open, M1_AXIS_TVALID => open, M1_AXIS_TREADY => net_gnd0, S1_AXIS_TLAST => net_gnd0, S1_AXIS_TDATA => net_gnd32(0 to 31), S1_AXIS_TVALID => net_gnd0, S1_AXIS_TREADY => open, M2_AXIS_TLAST => open, M2_AXIS_TDATA => open, M2_AXIS_TVALID => open, M2_AXIS_TREADY => net_gnd0, S2_AXIS_TLAST => net_gnd0, S2_AXIS_TDATA => net_gnd32(0 to 31), S2_AXIS_TVALID => net_gnd0, S2_AXIS_TREADY => open, M3_AXIS_TLAST => open, M3_AXIS_TDATA => open, M3_AXIS_TVALID => open, M3_AXIS_TREADY => net_gnd0, S3_AXIS_TLAST => net_gnd0, S3_AXIS_TDATA => net_gnd32(0 to 31), S3_AXIS_TVALID => net_gnd0, S3_AXIS_TREADY => open, M4_AXIS_TLAST => open, M4_AXIS_TDATA => open, M4_AXIS_TVALID => open, M4_AXIS_TREADY => net_gnd0, S4_AXIS_TLAST => net_gnd0, S4_AXIS_TDATA => net_gnd32(0 to 31), S4_AXIS_TVALID => net_gnd0, S4_AXIS_TREADY => open, M5_AXIS_TLAST => open, M5_AXIS_TDATA => open, M5_AXIS_TVALID => open, M5_AXIS_TREADY => net_gnd0, S5_AXIS_TLAST => net_gnd0, S5_AXIS_TDATA => net_gnd32(0 to 31), S5_AXIS_TVALID => net_gnd0, S5_AXIS_TREADY => open, M6_AXIS_TLAST => open, M6_AXIS_TDATA => open, M6_AXIS_TVALID => open, M6_AXIS_TREADY => net_gnd0, S6_AXIS_TLAST => net_gnd0, S6_AXIS_TDATA => net_gnd32(0 to 31), S6_AXIS_TVALID => net_gnd0, S6_AXIS_TREADY => open, M7_AXIS_TLAST => open, M7_AXIS_TDATA => open, M7_AXIS_TVALID => open, M7_AXIS_TREADY => net_gnd0, S7_AXIS_TLAST => net_gnd0, S7_AXIS_TDATA => net_gnd32(0 to 31), S7_AXIS_TVALID => net_gnd0, S7_AXIS_TREADY => open, M8_AXIS_TLAST => open, M8_AXIS_TDATA => open, M8_AXIS_TVALID => open, M8_AXIS_TREADY => net_gnd0, S8_AXIS_TLAST => net_gnd0, S8_AXIS_TDATA => net_gnd32(0 to 31), S8_AXIS_TVALID => net_gnd0, S8_AXIS_TREADY => open, M9_AXIS_TLAST => open, M9_AXIS_TDATA => open, M9_AXIS_TVALID => open, M9_AXIS_TREADY => net_gnd0, S9_AXIS_TLAST => net_gnd0, S9_AXIS_TDATA => net_gnd32(0 to 31), S9_AXIS_TVALID => net_gnd0, S9_AXIS_TREADY => open, M10_AXIS_TLAST => open, M10_AXIS_TDATA => open, M10_AXIS_TVALID => open, M10_AXIS_TREADY => net_gnd0, S10_AXIS_TLAST => net_gnd0, S10_AXIS_TDATA => net_gnd32(0 to 31), S10_AXIS_TVALID => net_gnd0, S10_AXIS_TREADY => open, M11_AXIS_TLAST => open, M11_AXIS_TDATA => open, M11_AXIS_TVALID => open, M11_AXIS_TREADY => net_gnd0, S11_AXIS_TLAST => net_gnd0, S11_AXIS_TDATA => net_gnd32(0 to 31), S11_AXIS_TVALID => net_gnd0, S11_AXIS_TREADY => open, M12_AXIS_TLAST => open, M12_AXIS_TDATA => open, M12_AXIS_TVALID => open, M12_AXIS_TREADY => net_gnd0, S12_AXIS_TLAST => net_gnd0, S12_AXIS_TDATA => net_gnd32(0 to 31), S12_AXIS_TVALID => net_gnd0, S12_AXIS_TREADY => open, M13_AXIS_TLAST => open, M13_AXIS_TDATA => open, M13_AXIS_TVALID => open, M13_AXIS_TREADY => net_gnd0, S13_AXIS_TLAST => net_gnd0, S13_AXIS_TDATA => net_gnd32(0 to 31), S13_AXIS_TVALID => net_gnd0, S13_AXIS_TREADY => open, M14_AXIS_TLAST => open, M14_AXIS_TDATA => open, M14_AXIS_TVALID => open, M14_AXIS_TREADY => net_gnd0, S14_AXIS_TLAST => net_gnd0, S14_AXIS_TDATA => net_gnd32(0 to 31), S14_AXIS_TVALID => net_gnd0, S14_AXIS_TREADY => open, M15_AXIS_TLAST => open, M15_AXIS_TDATA => open, M15_AXIS_TVALID => open, M15_AXIS_TREADY => net_gnd0, S15_AXIS_TLAST => net_gnd0, S15_AXIS_TDATA => net_gnd32(0 to 31), S15_AXIS_TVALID => net_gnd0, S15_AXIS_TREADY => open, ICACHE_FSL_IN_CLK => open, ICACHE_FSL_IN_READ => open, ICACHE_FSL_IN_DATA => net_gnd32, ICACHE_FSL_IN_CONTROL => net_gnd0, ICACHE_FSL_IN_EXISTS => net_gnd0, ICACHE_FSL_OUT_CLK => open, ICACHE_FSL_OUT_WRITE => open, ICACHE_FSL_OUT_DATA => open, ICACHE_FSL_OUT_CONTROL => open, ICACHE_FSL_OUT_FULL => net_gnd0, DCACHE_FSL_IN_CLK => open, DCACHE_FSL_IN_READ => open, DCACHE_FSL_IN_DATA => net_gnd32, DCACHE_FSL_IN_CONTROL => net_gnd0, DCACHE_FSL_IN_EXISTS => net_gnd0, DCACHE_FSL_OUT_CLK => open, DCACHE_FSL_OUT_WRITE => open, DCACHE_FSL_OUT_DATA => open, DCACHE_FSL_OUT_CONTROL => open, DCACHE_FSL_OUT_FULL => net_gnd0 ); mb_plb : system_mb_plb_wrapper port map ( PLB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), PLB_Rst => open, SPLB_Rst => mb_plb_SPLB_Rst, MPLB_Rst => mb_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => mb_plb_M_ABus, M_UABus => mb_plb_M_UABus, M_BE => mb_plb_M_BE, M_RNW => mb_plb_M_RNW, M_abort => mb_plb_M_ABort, M_busLock => mb_plb_M_busLock, M_TAttribute => mb_plb_M_TAttribute, M_lockErr => mb_plb_M_lockErr, M_MSize => mb_plb_M_MSize, M_priority => mb_plb_M_priority, M_rdBurst => mb_plb_M_rdBurst, M_request => mb_plb_M_request, M_size => mb_plb_M_size, M_type => mb_plb_M_type, M_wrBurst => mb_plb_M_wrBurst, M_wrDBus => mb_plb_M_wrDBus, Sl_addrAck => mb_plb_Sl_addrAck, Sl_MRdErr => mb_plb_Sl_MRdErr, Sl_MWrErr => mb_plb_Sl_MWrErr, Sl_MBusy => mb_plb_Sl_MBusy, Sl_rdBTerm => mb_plb_Sl_rdBTerm, Sl_rdComp => mb_plb_Sl_rdComp, Sl_rdDAck => mb_plb_Sl_rdDAck, Sl_rdDBus => mb_plb_Sl_rdDBus, Sl_rdWdAddr => mb_plb_Sl_rdWdAddr, Sl_rearbitrate => mb_plb_Sl_rearbitrate, Sl_SSize => mb_plb_Sl_SSize, Sl_wait => mb_plb_Sl_wait, Sl_wrBTerm => mb_plb_Sl_wrBTerm, Sl_wrComp => mb_plb_Sl_wrComp, Sl_wrDAck => mb_plb_Sl_wrDAck, Sl_MIRQ => mb_plb_Sl_MIRQ, PLB_MIRQ => mb_plb_PLB_MIRQ, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_BE => mb_plb_PLB_BE, PLB_MAddrAck => mb_plb_PLB_MAddrAck, PLB_MTimeout => mb_plb_PLB_MTimeout, PLB_MBusy => mb_plb_PLB_MBusy, PLB_MRdErr => mb_plb_PLB_MRdErr, PLB_MWrErr => mb_plb_PLB_MWrErr, PLB_MRdBTerm => mb_plb_PLB_MRdBTerm, PLB_MRdDAck => mb_plb_PLB_MRdDAck, PLB_MRdDBus => mb_plb_PLB_MRdDBus, PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr, PLB_MRearbitrate => mb_plb_PLB_MRearbitrate, PLB_MWrBTerm => mb_plb_PLB_MWrBTerm, PLB_MWrDAck => mb_plb_PLB_MWrDAck, PLB_MSSize => mb_plb_PLB_MSSize, PLB_PAValid => mb_plb_PLB_PAValid, PLB_RNW => mb_plb_PLB_RNW, PLB_SAValid => mb_plb_PLB_SAValid, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_TAttribute => mb_plb_PLB_TAttribute, PLB_lockErr => mb_plb_PLB_lockErr, PLB_masterID => mb_plb_PLB_masterID, PLB_MSize => mb_plb_PLB_MSize, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_rdPrim => mb_plb_PLB_rdPrim, PLB_reqPri => mb_plb_PLB_reqPri, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrPrim => mb_plb_PLB_wrPrim, PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ilmb : system_ilmb_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), LMB_Rst => ilmb_LMB_Rst, M_ABus => ilmb_M_ABus, M_ReadStrobe => ilmb_M_ReadStrobe, M_WriteStrobe => net_gnd0, M_AddrStrobe => ilmb_M_AddrStrobe, M_DBus => net_gnd32, M_BE => net_gnd4, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0 to 0), Sl_Wait => ilmb_Sl_Wait(0 to 0), Sl_UE => ilmb_Sl_UE(0 to 0), Sl_CE => ilmb_Sl_CE(0 to 0), LMB_ABus => ilmb_LMB_ABus, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadDBus => ilmb_LMB_ReadDBus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_Ready => ilmb_LMB_Ready, LMB_Wait => ilmb_LMB_Wait, LMB_UE => ilmb_LMB_UE, LMB_CE => ilmb_LMB_CE, LMB_BE => ilmb_LMB_BE ); dlmb : system_dlmb_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), LMB_Rst => dlmb_LMB_Rst, M_ABus => dlmb_M_ABus, M_ReadStrobe => dlmb_M_ReadStrobe, M_WriteStrobe => dlmb_M_WriteStrobe, M_AddrStrobe => dlmb_M_AddrStrobe, M_DBus => dlmb_M_DBus, M_BE => dlmb_M_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0 to 0), Sl_Wait => dlmb_Sl_Wait(0 to 0), Sl_UE => dlmb_Sl_UE(0 to 0), Sl_CE => dlmb_Sl_CE(0 to 0), LMB_ABus => dlmb_LMB_ABus, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadDBus => dlmb_LMB_ReadDBus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_Ready => dlmb_LMB_Ready, LMB_Wait => dlmb_LMB_Wait, LMB_UE => dlmb_LMB_UE, LMB_CE => dlmb_LMB_CE, LMB_BE => dlmb_LMB_BE ); dlmb_cntlr : system_dlmb_cntlr_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, LMB_Rst => dlmb_LMB_Rst, LMB_ABus => dlmb_LMB_ABus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_BE => dlmb_LMB_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0), Sl_Wait => dlmb_Sl_Wait(0), Sl_UE => dlmb_Sl_UE(0), Sl_CE => dlmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => dlmb_port_BRAM_Rst, BRAM_Clk_A => dlmb_port_BRAM_Clk, BRAM_EN_A => dlmb_port_BRAM_EN, BRAM_WEN_A => dlmb_port_BRAM_WEN, BRAM_Addr_A => dlmb_port_BRAM_Addr, BRAM_Din_A => dlmb_port_BRAM_Din, BRAM_Dout_A => dlmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); ilmb_cntlr : system_ilmb_cntlr_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, LMB_Rst => ilmb_LMB_Rst, LMB_ABus => ilmb_LMB_ABus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_BE => ilmb_LMB_BE, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0), Sl_Wait => ilmb_Sl_Wait(0), Sl_UE => ilmb_Sl_UE(0), Sl_CE => ilmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); lmb_bram : system_lmb_bram_wrapper port map ( BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, BRAM_Rst_B => dlmb_port_BRAM_Rst, BRAM_Clk_B => dlmb_port_BRAM_Clk, BRAM_EN_B => dlmb_port_BRAM_EN, BRAM_WEN_B => dlmb_port_BRAM_WEN, BRAM_Addr_B => dlmb_port_BRAM_Addr, BRAM_Din_B => dlmb_port_BRAM_Din, BRAM_Dout_B => dlmb_port_BRAM_Dout ); DDR2_SDRAM : system_ddr2_sdram_wrapper port map ( FSL0_M_Clk => net_vcc0, FSL0_M_Write => net_gnd0, FSL0_M_Data => net_gnd32, FSL0_M_Control => net_gnd0, FSL0_M_Full => open, FSL0_S_Clk => net_gnd0, FSL0_S_Read => net_gnd0, FSL0_S_Data => open, FSL0_S_Control => open, FSL0_S_Exists => open, FSL0_B_M_Clk => net_vcc0, FSL0_B_M_Write => net_gnd0, FSL0_B_M_Data => net_gnd32, FSL0_B_M_Control => net_gnd0, FSL0_B_M_Full => open, FSL0_B_S_Clk => net_gnd0, FSL0_B_S_Read => net_gnd0, FSL0_B_S_Data => open, FSL0_B_S_Control => open, FSL0_B_S_Exists => open, SPLB0_Clk => clk_125_0000MHzPLL0, SPLB0_Rst => mb_plb_SPLB_Rst(0), SPLB0_PLB_ABus => mb_plb_PLB_ABus, SPLB0_PLB_PAValid => mb_plb_PLB_PAValid, SPLB0_PLB_SAValid => mb_plb_PLB_SAValid, SPLB0_PLB_masterID => mb_plb_PLB_masterID, SPLB0_PLB_RNW => mb_plb_PLB_RNW, SPLB0_PLB_BE => mb_plb_PLB_BE, SPLB0_PLB_UABus => mb_plb_PLB_UABus, SPLB0_PLB_rdPrim => mb_plb_PLB_rdPrim(0), SPLB0_PLB_wrPrim => mb_plb_PLB_wrPrim(0), SPLB0_PLB_abort => mb_plb_PLB_abort, SPLB0_PLB_busLock => mb_plb_PLB_busLock, SPLB0_PLB_MSize => mb_plb_PLB_MSize, SPLB0_PLB_size => mb_plb_PLB_size, SPLB0_PLB_type => mb_plb_PLB_type, SPLB0_PLB_lockErr => mb_plb_PLB_lockErr, SPLB0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, SPLB0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, SPLB0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, SPLB0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, SPLB0_PLB_reqPri => mb_plb_PLB_reqPri, SPLB0_PLB_TAttribute => mb_plb_PLB_TAttribute, SPLB0_PLB_rdBurst => mb_plb_PLB_rdBurst, SPLB0_PLB_wrBurst => mb_plb_PLB_wrBurst, SPLB0_PLB_wrDBus => mb_plb_PLB_wrDBus, SPLB0_Sl_addrAck => mb_plb_Sl_addrAck(0), SPLB0_Sl_SSize => mb_plb_Sl_SSize(0 to 1), SPLB0_Sl_wait => mb_plb_Sl_wait(0), SPLB0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(0), SPLB0_Sl_wrDAck => mb_plb_Sl_wrDAck(0), SPLB0_Sl_wrComp => mb_plb_Sl_wrComp(0), SPLB0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(0), SPLB0_Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 63), SPLB0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3), SPLB0_Sl_rdDAck => mb_plb_Sl_rdDAck(0), SPLB0_Sl_rdComp => mb_plb_Sl_rdComp(0), SPLB0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(0), SPLB0_Sl_MBusy => mb_plb_Sl_MBusy(0 to 5), SPLB0_Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 5), SPLB0_Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 5), SPLB0_Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 5), SDMA0_Clk => net_gnd0, SDMA0_Rx_IntOut => open, SDMA0_Tx_IntOut => open, SDMA0_RstOut => open, SDMA0_TX_D => open, SDMA0_TX_Rem => open, SDMA0_TX_SOF => open, SDMA0_TX_EOF => open, SDMA0_TX_SOP => open, SDMA0_TX_EOP => open, SDMA0_TX_Src_Rdy => open, SDMA0_TX_Dst_Rdy => net_vcc0, SDMA0_RX_D => net_gnd32, SDMA0_RX_Rem => net_vcc4, SDMA0_RX_SOF => net_vcc0, SDMA0_RX_EOF => net_vcc0, SDMA0_RX_SOP => net_vcc0, SDMA0_RX_EOP => net_vcc0, SDMA0_RX_Src_Rdy => net_vcc0, SDMA0_RX_Dst_Rdy => open, SDMA_CTRL0_Clk => net_vcc0, SDMA_CTRL0_Rst => net_gnd0, SDMA_CTRL0_PLB_ABus => net_gnd32, SDMA_CTRL0_PLB_PAValid => net_gnd0, SDMA_CTRL0_PLB_SAValid => net_gnd0, SDMA_CTRL0_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL0_PLB_RNW => net_gnd0, SDMA_CTRL0_PLB_BE => net_gnd8, SDMA_CTRL0_PLB_UABus => net_gnd32, SDMA_CTRL0_PLB_rdPrim => net_gnd0, SDMA_CTRL0_PLB_wrPrim => net_gnd0, SDMA_CTRL0_PLB_abort => net_gnd0, SDMA_CTRL0_PLB_busLock => net_gnd0, SDMA_CTRL0_PLB_MSize => net_gnd2, SDMA_CTRL0_PLB_size => net_gnd4, SDMA_CTRL0_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL0_PLB_lockErr => net_gnd0, SDMA_CTRL0_PLB_wrPendReq => net_gnd0, SDMA_CTRL0_PLB_wrPendPri => net_gnd2, SDMA_CTRL0_PLB_rdPendReq => net_gnd0, SDMA_CTRL0_PLB_rdPendPri => net_gnd2, SDMA_CTRL0_PLB_reqPri => net_gnd2, SDMA_CTRL0_PLB_TAttribute => net_gnd16, SDMA_CTRL0_PLB_rdBurst => net_gnd0, SDMA_CTRL0_PLB_wrBurst => net_gnd0, SDMA_CTRL0_PLB_wrDBus => net_gnd64, SDMA_CTRL0_Sl_addrAck => open, SDMA_CTRL0_Sl_SSize => open, SDMA_CTRL0_Sl_wait => open, SDMA_CTRL0_Sl_rearbitrate => open, SDMA_CTRL0_Sl_wrDAck => open, SDMA_CTRL0_Sl_wrComp => open, SDMA_CTRL0_Sl_wrBTerm => open, SDMA_CTRL0_Sl_rdDBus => open, SDMA_CTRL0_Sl_rdWdAddr => open, SDMA_CTRL0_Sl_rdDAck => open, SDMA_CTRL0_Sl_rdComp => open, SDMA_CTRL0_Sl_rdBTerm => open, SDMA_CTRL0_Sl_MBusy => open, SDMA_CTRL0_Sl_MRdErr => open, SDMA_CTRL0_Sl_MWrErr => open, SDMA_CTRL0_Sl_MIRQ => open, PIM0_Addr => net_gnd32(0 to 31), PIM0_AddrReq => net_gnd0, PIM0_AddrAck => open, PIM0_RNW => net_gnd0, PIM0_Size => net_gnd4(0 to 3), PIM0_RdModWr => net_gnd0, PIM0_WrFIFO_Data => net_gnd64(0 to 63), PIM0_WrFIFO_BE => net_gnd8(0 to 7), PIM0_WrFIFO_Push => net_gnd0, PIM0_RdFIFO_Data => open, PIM0_RdFIFO_Pop => net_gnd0, PIM0_RdFIFO_RdWdAddr => open, PIM0_WrFIFO_Empty => open, PIM0_WrFIFO_AlmostFull => open, PIM0_WrFIFO_Flush => net_gnd0, PIM0_RdFIFO_Empty => open, PIM0_RdFIFO_Flush => net_gnd0, PIM0_RdFIFO_Latency => open, PIM0_InitDone => open, PPC440MC0_MIMCReadNotWrite => net_gnd0, PPC440MC0_MIMCAddress => net_gnd36, PPC440MC0_MIMCAddressValid => net_gnd0, PPC440MC0_MIMCWriteData => net_gnd128, PPC440MC0_MIMCWriteDataValid => net_gnd0, PPC440MC0_MIMCByteEnable => net_gnd16, PPC440MC0_MIMCBankConflict => net_gnd0, PPC440MC0_MIMCRowConflict => net_gnd0, PPC440MC0_MCMIReadData => open, PPC440MC0_MCMIReadDataValid => open, PPC440MC0_MCMIReadDataErr => open, PPC440MC0_MCMIAddrReadyToAccept => open, VFBC0_Cmd_Clk => net_gnd0, VFBC0_Cmd_Reset => net_gnd0, VFBC0_Cmd_Data => net_gnd32(0 to 31), VFBC0_Cmd_Write => net_gnd0, VFBC0_Cmd_End => net_gnd0, VFBC0_Cmd_Full => open, VFBC0_Cmd_Almost_Full => open, VFBC0_Cmd_Idle => open, VFBC0_Wd_Clk => net_gnd0, VFBC0_Wd_Reset => net_gnd0, VFBC0_Wd_Write => net_gnd0, VFBC0_Wd_End_Burst => net_gnd0, VFBC0_Wd_Flush => net_gnd0, VFBC0_Wd_Data => net_gnd32(0 to 31), VFBC0_Wd_Data_BE => net_gnd4(0 to 3), VFBC0_Wd_Full => open, VFBC0_Wd_Almost_Full => open, VFBC0_Rd_Clk => net_gnd0, VFBC0_Rd_Reset => net_gnd0, VFBC0_Rd_Read => net_gnd0, VFBC0_Rd_End_Burst => net_gnd0, VFBC0_Rd_Flush => net_gnd0, VFBC0_Rd_Data => open, VFBC0_Rd_Empty => open, VFBC0_Rd_Almost_Empty => open, MCB0_cmd_clk => net_gnd0, MCB0_cmd_en => net_gnd0, MCB0_cmd_instr => net_gnd3, MCB0_cmd_bl => net_gnd6, MCB0_cmd_byte_addr => net_gnd30, MCB0_cmd_empty => open, MCB0_cmd_full => open, MCB0_wr_clk => net_gnd0, MCB0_wr_en => net_gnd0, MCB0_wr_mask => net_gnd8(0 to 7), MCB0_wr_data => net_gnd64(0 to 63), MCB0_wr_full => open, MCB0_wr_empty => open, MCB0_wr_count => open, MCB0_wr_underrun => open, MCB0_wr_error => open, MCB0_rd_clk => net_gnd0, MCB0_rd_en => net_gnd0, MCB0_rd_data => open, MCB0_rd_full => open, MCB0_rd_empty => open, MCB0_rd_count => open, MCB0_rd_overflow => open, MCB0_rd_error => open, FSL1_M_Clk => net_vcc0, FSL1_M_Write => net_gnd0, FSL1_M_Data => net_gnd32, FSL1_M_Control => net_gnd0, FSL1_M_Full => open, FSL1_S_Clk => net_gnd0, FSL1_S_Read => net_gnd0, FSL1_S_Data => open, FSL1_S_Control => open, FSL1_S_Exists => open, FSL1_B_M_Clk => net_vcc0, FSL1_B_M_Write => net_gnd0, FSL1_B_M_Data => net_gnd32, FSL1_B_M_Control => net_gnd0, FSL1_B_M_Full => open, FSL1_B_S_Clk => net_gnd0, FSL1_B_S_Read => net_gnd0, FSL1_B_S_Data => open, FSL1_B_S_Control => open, FSL1_B_S_Exists => open, SPLB1_Clk => net_vcc0, SPLB1_Rst => net_gnd0, SPLB1_PLB_ABus => net_gnd32, SPLB1_PLB_PAValid => net_gnd0, SPLB1_PLB_SAValid => net_gnd0, SPLB1_PLB_masterID => net_gnd1(0 downto 0), SPLB1_PLB_RNW => net_gnd0, SPLB1_PLB_BE => net_gnd8, SPLB1_PLB_UABus => net_gnd32, SPLB1_PLB_rdPrim => net_gnd0, SPLB1_PLB_wrPrim => net_gnd0, SPLB1_PLB_abort => net_gnd0, SPLB1_PLB_busLock => net_gnd0, SPLB1_PLB_MSize => net_gnd2, SPLB1_PLB_size => net_gnd4, SPLB1_PLB_type => net_gnd3(2 downto 0), SPLB1_PLB_lockErr => net_gnd0, SPLB1_PLB_wrPendReq => net_gnd0, SPLB1_PLB_wrPendPri => net_gnd2, SPLB1_PLB_rdPendReq => net_gnd0, SPLB1_PLB_rdPendPri => net_gnd2, SPLB1_PLB_reqPri => net_gnd2, SPLB1_PLB_TAttribute => net_gnd16, SPLB1_PLB_rdBurst => net_gnd0, SPLB1_PLB_wrBurst => net_gnd0, SPLB1_PLB_wrDBus => net_gnd64, SPLB1_Sl_addrAck => open, SPLB1_Sl_SSize => open, SPLB1_Sl_wait => open, SPLB1_Sl_rearbitrate => open, SPLB1_Sl_wrDAck => open, SPLB1_Sl_wrComp => open, SPLB1_Sl_wrBTerm => open, SPLB1_Sl_rdDBus => open, SPLB1_Sl_rdWdAddr => open, SPLB1_Sl_rdDAck => open, SPLB1_Sl_rdComp => open, SPLB1_Sl_rdBTerm => open, SPLB1_Sl_MBusy => open, SPLB1_Sl_MRdErr => open, SPLB1_Sl_MWrErr => open, SPLB1_Sl_MIRQ => open, SDMA1_Clk => net_gnd0, SDMA1_Rx_IntOut => open, SDMA1_Tx_IntOut => open, SDMA1_RstOut => open, SDMA1_TX_D => open, SDMA1_TX_Rem => open, SDMA1_TX_SOF => open, SDMA1_TX_EOF => open, SDMA1_TX_SOP => open, SDMA1_TX_EOP => open, SDMA1_TX_Src_Rdy => open, SDMA1_TX_Dst_Rdy => net_vcc0, SDMA1_RX_D => net_gnd32, SDMA1_RX_Rem => net_vcc4, SDMA1_RX_SOF => net_vcc0, SDMA1_RX_EOF => net_vcc0, SDMA1_RX_SOP => net_vcc0, SDMA1_RX_EOP => net_vcc0, SDMA1_RX_Src_Rdy => net_vcc0, SDMA1_RX_Dst_Rdy => open, SDMA_CTRL1_Clk => net_vcc0, SDMA_CTRL1_Rst => net_gnd0, SDMA_CTRL1_PLB_ABus => net_gnd32, SDMA_CTRL1_PLB_PAValid => net_gnd0, SDMA_CTRL1_PLB_SAValid => net_gnd0, SDMA_CTRL1_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL1_PLB_RNW => net_gnd0, SDMA_CTRL1_PLB_BE => net_gnd8, SDMA_CTRL1_PLB_UABus => net_gnd32, SDMA_CTRL1_PLB_rdPrim => net_gnd0, SDMA_CTRL1_PLB_wrPrim => net_gnd0, SDMA_CTRL1_PLB_abort => net_gnd0, SDMA_CTRL1_PLB_busLock => net_gnd0, SDMA_CTRL1_PLB_MSize => net_gnd2, SDMA_CTRL1_PLB_size => net_gnd4, SDMA_CTRL1_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL1_PLB_lockErr => net_gnd0, SDMA_CTRL1_PLB_wrPendReq => net_gnd0, SDMA_CTRL1_PLB_wrPendPri => net_gnd2, SDMA_CTRL1_PLB_rdPendReq => net_gnd0, SDMA_CTRL1_PLB_rdPendPri => net_gnd2, SDMA_CTRL1_PLB_reqPri => net_gnd2, SDMA_CTRL1_PLB_TAttribute => net_gnd16, SDMA_CTRL1_PLB_rdBurst => net_gnd0, SDMA_CTRL1_PLB_wrBurst => net_gnd0, SDMA_CTRL1_PLB_wrDBus => net_gnd64, SDMA_CTRL1_Sl_addrAck => open, SDMA_CTRL1_Sl_SSize => open, SDMA_CTRL1_Sl_wait => open, SDMA_CTRL1_Sl_rearbitrate => open, SDMA_CTRL1_Sl_wrDAck => open, SDMA_CTRL1_Sl_wrComp => open, SDMA_CTRL1_Sl_wrBTerm => open, SDMA_CTRL1_Sl_rdDBus => open, SDMA_CTRL1_Sl_rdWdAddr => open, SDMA_CTRL1_Sl_rdDAck => open, SDMA_CTRL1_Sl_rdComp => open, SDMA_CTRL1_Sl_rdBTerm => open, SDMA_CTRL1_Sl_MBusy => open, SDMA_CTRL1_Sl_MRdErr => open, SDMA_CTRL1_Sl_MWrErr => open, SDMA_CTRL1_Sl_MIRQ => open, PIM1_Addr => net_gnd32(0 to 31), PIM1_AddrReq => net_gnd0, PIM1_AddrAck => open, PIM1_RNW => net_gnd0, PIM1_Size => net_gnd4(0 to 3), PIM1_RdModWr => net_gnd0, PIM1_WrFIFO_Data => net_gnd64(0 to 63), PIM1_WrFIFO_BE => net_gnd8(0 to 7), PIM1_WrFIFO_Push => net_gnd0, PIM1_RdFIFO_Data => open, PIM1_RdFIFO_Pop => net_gnd0, PIM1_RdFIFO_RdWdAddr => open, PIM1_WrFIFO_Empty => open, PIM1_WrFIFO_AlmostFull => open, PIM1_WrFIFO_Flush => net_gnd0, PIM1_RdFIFO_Empty => open, PIM1_RdFIFO_Flush => net_gnd0, PIM1_RdFIFO_Latency => open, PIM1_InitDone => open, PPC440MC1_MIMCReadNotWrite => net_gnd0, PPC440MC1_MIMCAddress => net_gnd36, PPC440MC1_MIMCAddressValid => net_gnd0, PPC440MC1_MIMCWriteData => net_gnd128, PPC440MC1_MIMCWriteDataValid => net_gnd0, PPC440MC1_MIMCByteEnable => net_gnd16, PPC440MC1_MIMCBankConflict => net_gnd0, PPC440MC1_MIMCRowConflict => net_gnd0, PPC440MC1_MCMIReadData => open, PPC440MC1_MCMIReadDataValid => open, PPC440MC1_MCMIReadDataErr => open, PPC440MC1_MCMIAddrReadyToAccept => open, VFBC1_Cmd_Clk => net_gnd0, VFBC1_Cmd_Reset => net_gnd0, VFBC1_Cmd_Data => net_gnd32(0 to 31), VFBC1_Cmd_Write => net_gnd0, VFBC1_Cmd_End => net_gnd0, VFBC1_Cmd_Full => open, VFBC1_Cmd_Almost_Full => open, VFBC1_Cmd_Idle => open, VFBC1_Wd_Clk => net_gnd0, VFBC1_Wd_Reset => net_gnd0, VFBC1_Wd_Write => net_gnd0, VFBC1_Wd_End_Burst => net_gnd0, VFBC1_Wd_Flush => net_gnd0, VFBC1_Wd_Data => net_gnd32(0 to 31), VFBC1_Wd_Data_BE => net_gnd4(0 to 3), VFBC1_Wd_Full => open, VFBC1_Wd_Almost_Full => open, VFBC1_Rd_Clk => net_gnd0, VFBC1_Rd_Reset => net_gnd0, VFBC1_Rd_Read => net_gnd0, VFBC1_Rd_End_Burst => net_gnd0, VFBC1_Rd_Flush => net_gnd0, VFBC1_Rd_Data => open, VFBC1_Rd_Empty => open, VFBC1_Rd_Almost_Empty => open, MCB1_cmd_clk => net_gnd0, MCB1_cmd_en => net_gnd0, MCB1_cmd_instr => net_gnd3, MCB1_cmd_bl => net_gnd6, MCB1_cmd_byte_addr => net_gnd30, MCB1_cmd_empty => open, MCB1_cmd_full => open, MCB1_wr_clk => net_gnd0, MCB1_wr_en => net_gnd0, MCB1_wr_mask => net_gnd8(0 to 7), MCB1_wr_data => net_gnd64(0 to 63), MCB1_wr_full => open, MCB1_wr_empty => open, MCB1_wr_count => open, MCB1_wr_underrun => open, MCB1_wr_error => open, MCB1_rd_clk => net_gnd0, MCB1_rd_en => net_gnd0, MCB1_rd_data => open, MCB1_rd_full => open, MCB1_rd_empty => open, MCB1_rd_count => open, MCB1_rd_overflow => open, MCB1_rd_error => open, FSL2_M_Clk => net_vcc0, FSL2_M_Write => net_gnd0, FSL2_M_Data => net_gnd32, FSL2_M_Control => net_gnd0, FSL2_M_Full => open, FSL2_S_Clk => net_gnd0, FSL2_S_Read => net_gnd0, FSL2_S_Data => open, FSL2_S_Control => open, FSL2_S_Exists => open, FSL2_B_M_Clk => net_vcc0, FSL2_B_M_Write => net_gnd0, FSL2_B_M_Data => net_gnd32, FSL2_B_M_Control => net_gnd0, FSL2_B_M_Full => open, FSL2_B_S_Clk => net_gnd0, FSL2_B_S_Read => net_gnd0, FSL2_B_S_Data => open, FSL2_B_S_Control => open, FSL2_B_S_Exists => open, SPLB2_Clk => net_vcc0, SPLB2_Rst => net_gnd0, SPLB2_PLB_ABus => net_gnd32, SPLB2_PLB_PAValid => net_gnd0, SPLB2_PLB_SAValid => net_gnd0, SPLB2_PLB_masterID => net_gnd1(0 downto 0), SPLB2_PLB_RNW => net_gnd0, SPLB2_PLB_BE => net_gnd8, SPLB2_PLB_UABus => net_gnd32, SPLB2_PLB_rdPrim => net_gnd0, SPLB2_PLB_wrPrim => net_gnd0, SPLB2_PLB_abort => net_gnd0, SPLB2_PLB_busLock => net_gnd0, SPLB2_PLB_MSize => net_gnd2, SPLB2_PLB_size => net_gnd4, SPLB2_PLB_type => net_gnd3(2 downto 0), SPLB2_PLB_lockErr => net_gnd0, SPLB2_PLB_wrPendReq => net_gnd0, SPLB2_PLB_wrPendPri => net_gnd2, SPLB2_PLB_rdPendReq => net_gnd0, SPLB2_PLB_rdPendPri => net_gnd2, SPLB2_PLB_reqPri => net_gnd2, SPLB2_PLB_TAttribute => net_gnd16, SPLB2_PLB_rdBurst => net_gnd0, SPLB2_PLB_wrBurst => net_gnd0, SPLB2_PLB_wrDBus => net_gnd64, SPLB2_Sl_addrAck => open, SPLB2_Sl_SSize => open, SPLB2_Sl_wait => open, SPLB2_Sl_rearbitrate => open, SPLB2_Sl_wrDAck => open, SPLB2_Sl_wrComp => open, SPLB2_Sl_wrBTerm => open, SPLB2_Sl_rdDBus => open, SPLB2_Sl_rdWdAddr => open, SPLB2_Sl_rdDAck => open, SPLB2_Sl_rdComp => open, SPLB2_Sl_rdBTerm => open, SPLB2_Sl_MBusy => open, SPLB2_Sl_MRdErr => open, SPLB2_Sl_MWrErr => open, SPLB2_Sl_MIRQ => open, SDMA2_Clk => net_gnd0, SDMA2_Rx_IntOut => open, SDMA2_Tx_IntOut => open, SDMA2_RstOut => open, SDMA2_TX_D => open, SDMA2_TX_Rem => open, SDMA2_TX_SOF => open, SDMA2_TX_EOF => open, SDMA2_TX_SOP => open, SDMA2_TX_EOP => open, SDMA2_TX_Src_Rdy => open, SDMA2_TX_Dst_Rdy => net_vcc0, SDMA2_RX_D => net_gnd32, SDMA2_RX_Rem => net_vcc4, SDMA2_RX_SOF => net_vcc0, SDMA2_RX_EOF => net_vcc0, SDMA2_RX_SOP => net_vcc0, SDMA2_RX_EOP => net_vcc0, SDMA2_RX_Src_Rdy => net_vcc0, SDMA2_RX_Dst_Rdy => open, SDMA_CTRL2_Clk => net_vcc0, SDMA_CTRL2_Rst => net_gnd0, SDMA_CTRL2_PLB_ABus => net_gnd32, SDMA_CTRL2_PLB_PAValid => net_gnd0, SDMA_CTRL2_PLB_SAValid => net_gnd0, SDMA_CTRL2_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL2_PLB_RNW => net_gnd0, SDMA_CTRL2_PLB_BE => net_gnd8, SDMA_CTRL2_PLB_UABus => net_gnd32, SDMA_CTRL2_PLB_rdPrim => net_gnd0, SDMA_CTRL2_PLB_wrPrim => net_gnd0, SDMA_CTRL2_PLB_abort => net_gnd0, SDMA_CTRL2_PLB_busLock => net_gnd0, SDMA_CTRL2_PLB_MSize => net_gnd2, SDMA_CTRL2_PLB_size => net_gnd4, SDMA_CTRL2_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL2_PLB_lockErr => net_gnd0, SDMA_CTRL2_PLB_wrPendReq => net_gnd0, SDMA_CTRL2_PLB_wrPendPri => net_gnd2, SDMA_CTRL2_PLB_rdPendReq => net_gnd0, SDMA_CTRL2_PLB_rdPendPri => net_gnd2, SDMA_CTRL2_PLB_reqPri => net_gnd2, SDMA_CTRL2_PLB_TAttribute => net_gnd16, SDMA_CTRL2_PLB_rdBurst => net_gnd0, SDMA_CTRL2_PLB_wrBurst => net_gnd0, SDMA_CTRL2_PLB_wrDBus => net_gnd64, SDMA_CTRL2_Sl_addrAck => open, SDMA_CTRL2_Sl_SSize => open, SDMA_CTRL2_Sl_wait => open, SDMA_CTRL2_Sl_rearbitrate => open, SDMA_CTRL2_Sl_wrDAck => open, SDMA_CTRL2_Sl_wrComp => open, SDMA_CTRL2_Sl_wrBTerm => open, SDMA_CTRL2_Sl_rdDBus => open, SDMA_CTRL2_Sl_rdWdAddr => open, SDMA_CTRL2_Sl_rdDAck => open, SDMA_CTRL2_Sl_rdComp => open, SDMA_CTRL2_Sl_rdBTerm => open, SDMA_CTRL2_Sl_MBusy => open, SDMA_CTRL2_Sl_MRdErr => open, SDMA_CTRL2_Sl_MWrErr => open, SDMA_CTRL2_Sl_MIRQ => open, PIM2_Addr => net_gnd32(0 to 31), PIM2_AddrReq => net_gnd0, PIM2_AddrAck => open, PIM2_RNW => net_gnd0, PIM2_Size => net_gnd4(0 to 3), PIM2_RdModWr => net_gnd0, PIM2_WrFIFO_Data => net_gnd64(0 to 63), PIM2_WrFIFO_BE => net_gnd8(0 to 7), PIM2_WrFIFO_Push => net_gnd0, PIM2_RdFIFO_Data => open, PIM2_RdFIFO_Pop => net_gnd0, PIM2_RdFIFO_RdWdAddr => open, PIM2_WrFIFO_Empty => open, PIM2_WrFIFO_AlmostFull => open, PIM2_WrFIFO_Flush => net_gnd0, PIM2_RdFIFO_Empty => open, PIM2_RdFIFO_Flush => net_gnd0, PIM2_RdFIFO_Latency => open, PIM2_InitDone => open, PPC440MC2_MIMCReadNotWrite => net_gnd0, PPC440MC2_MIMCAddress => net_gnd36, PPC440MC2_MIMCAddressValid => net_gnd0, PPC440MC2_MIMCWriteData => net_gnd128, PPC440MC2_MIMCWriteDataValid => net_gnd0, PPC440MC2_MIMCByteEnable => net_gnd16, PPC440MC2_MIMCBankConflict => net_gnd0, PPC440MC2_MIMCRowConflict => net_gnd0, PPC440MC2_MCMIReadData => open, PPC440MC2_MCMIReadDataValid => open, PPC440MC2_MCMIReadDataErr => open, PPC440MC2_MCMIAddrReadyToAccept => open, VFBC2_Cmd_Clk => net_gnd0, VFBC2_Cmd_Reset => net_gnd0, VFBC2_Cmd_Data => net_gnd32(0 to 31), VFBC2_Cmd_Write => net_gnd0, VFBC2_Cmd_End => net_gnd0, VFBC2_Cmd_Full => open, VFBC2_Cmd_Almost_Full => open, VFBC2_Cmd_Idle => open, VFBC2_Wd_Clk => net_gnd0, VFBC2_Wd_Reset => net_gnd0, VFBC2_Wd_Write => net_gnd0, VFBC2_Wd_End_Burst => net_gnd0, VFBC2_Wd_Flush => net_gnd0, VFBC2_Wd_Data => net_gnd32(0 to 31), VFBC2_Wd_Data_BE => net_gnd4(0 to 3), VFBC2_Wd_Full => open, VFBC2_Wd_Almost_Full => open, VFBC2_Rd_Clk => net_gnd0, VFBC2_Rd_Reset => net_gnd0, VFBC2_Rd_Read => net_gnd0, VFBC2_Rd_End_Burst => net_gnd0, VFBC2_Rd_Flush => net_gnd0, VFBC2_Rd_Data => open, VFBC2_Rd_Empty => open, VFBC2_Rd_Almost_Empty => open, MCB2_cmd_clk => net_gnd0, MCB2_cmd_en => net_gnd0, MCB2_cmd_instr => net_gnd3, MCB2_cmd_bl => net_gnd6, MCB2_cmd_byte_addr => net_gnd30, MCB2_cmd_empty => open, MCB2_cmd_full => open, MCB2_wr_clk => net_gnd0, MCB2_wr_en => net_gnd0, MCB2_wr_mask => net_gnd8(0 to 7), MCB2_wr_data => net_gnd64(0 to 63), MCB2_wr_full => open, MCB2_wr_empty => open, MCB2_wr_count => open, MCB2_wr_underrun => open, MCB2_wr_error => open, MCB2_rd_clk => net_gnd0, MCB2_rd_en => net_gnd0, MCB2_rd_data => open, MCB2_rd_full => open, MCB2_rd_empty => open, MCB2_rd_count => open, MCB2_rd_overflow => open, MCB2_rd_error => open, FSL3_M_Clk => net_vcc0, FSL3_M_Write => net_gnd0, FSL3_M_Data => net_gnd32, FSL3_M_Control => net_gnd0, FSL3_M_Full => open, FSL3_S_Clk => net_gnd0, FSL3_S_Read => net_gnd0, FSL3_S_Data => open, FSL3_S_Control => open, FSL3_S_Exists => open, FSL3_B_M_Clk => net_vcc0, FSL3_B_M_Write => net_gnd0, FSL3_B_M_Data => net_gnd32, FSL3_B_M_Control => net_gnd0, FSL3_B_M_Full => open, FSL3_B_S_Clk => net_gnd0, FSL3_B_S_Read => net_gnd0, FSL3_B_S_Data => open, FSL3_B_S_Control => open, FSL3_B_S_Exists => open, SPLB3_Clk => net_vcc0, SPLB3_Rst => net_gnd0, SPLB3_PLB_ABus => net_gnd32, SPLB3_PLB_PAValid => net_gnd0, SPLB3_PLB_SAValid => net_gnd0, SPLB3_PLB_masterID => net_gnd1(0 downto 0), SPLB3_PLB_RNW => net_gnd0, SPLB3_PLB_BE => net_gnd8, SPLB3_PLB_UABus => net_gnd32, SPLB3_PLB_rdPrim => net_gnd0, SPLB3_PLB_wrPrim => net_gnd0, SPLB3_PLB_abort => net_gnd0, SPLB3_PLB_busLock => net_gnd0, SPLB3_PLB_MSize => net_gnd2, SPLB3_PLB_size => net_gnd4, SPLB3_PLB_type => net_gnd3(2 downto 0), SPLB3_PLB_lockErr => net_gnd0, SPLB3_PLB_wrPendReq => net_gnd0, SPLB3_PLB_wrPendPri => net_gnd2, SPLB3_PLB_rdPendReq => net_gnd0, SPLB3_PLB_rdPendPri => net_gnd2, SPLB3_PLB_reqPri => net_gnd2, SPLB3_PLB_TAttribute => net_gnd16, SPLB3_PLB_rdBurst => net_gnd0, SPLB3_PLB_wrBurst => net_gnd0, SPLB3_PLB_wrDBus => net_gnd64, SPLB3_Sl_addrAck => open, SPLB3_Sl_SSize => open, SPLB3_Sl_wait => open, SPLB3_Sl_rearbitrate => open, SPLB3_Sl_wrDAck => open, SPLB3_Sl_wrComp => open, SPLB3_Sl_wrBTerm => open, SPLB3_Sl_rdDBus => open, SPLB3_Sl_rdWdAddr => open, SPLB3_Sl_rdDAck => open, SPLB3_Sl_rdComp => open, SPLB3_Sl_rdBTerm => open, SPLB3_Sl_MBusy => open, SPLB3_Sl_MRdErr => open, SPLB3_Sl_MWrErr => open, SPLB3_Sl_MIRQ => open, SDMA3_Clk => net_gnd0, SDMA3_Rx_IntOut => open, SDMA3_Tx_IntOut => open, SDMA3_RstOut => open, SDMA3_TX_D => open, SDMA3_TX_Rem => open, SDMA3_TX_SOF => open, SDMA3_TX_EOF => open, SDMA3_TX_SOP => open, SDMA3_TX_EOP => open, SDMA3_TX_Src_Rdy => open, SDMA3_TX_Dst_Rdy => net_vcc0, SDMA3_RX_D => net_gnd32, SDMA3_RX_Rem => net_vcc4, SDMA3_RX_SOF => net_vcc0, SDMA3_RX_EOF => net_vcc0, SDMA3_RX_SOP => net_vcc0, SDMA3_RX_EOP => net_vcc0, SDMA3_RX_Src_Rdy => net_vcc0, SDMA3_RX_Dst_Rdy => open, SDMA_CTRL3_Clk => net_vcc0, SDMA_CTRL3_Rst => net_gnd0, SDMA_CTRL3_PLB_ABus => net_gnd32, SDMA_CTRL3_PLB_PAValid => net_gnd0, SDMA_CTRL3_PLB_SAValid => net_gnd0, SDMA_CTRL3_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL3_PLB_RNW => net_gnd0, SDMA_CTRL3_PLB_BE => net_gnd8, SDMA_CTRL3_PLB_UABus => net_gnd32, SDMA_CTRL3_PLB_rdPrim => net_gnd0, SDMA_CTRL3_PLB_wrPrim => net_gnd0, SDMA_CTRL3_PLB_abort => net_gnd0, SDMA_CTRL3_PLB_busLock => net_gnd0, SDMA_CTRL3_PLB_MSize => net_gnd2, SDMA_CTRL3_PLB_size => net_gnd4, SDMA_CTRL3_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL3_PLB_lockErr => net_gnd0, SDMA_CTRL3_PLB_wrPendReq => net_gnd0, SDMA_CTRL3_PLB_wrPendPri => net_gnd2, SDMA_CTRL3_PLB_rdPendReq => net_gnd0, SDMA_CTRL3_PLB_rdPendPri => net_gnd2, SDMA_CTRL3_PLB_reqPri => net_gnd2, SDMA_CTRL3_PLB_TAttribute => net_gnd16, SDMA_CTRL3_PLB_rdBurst => net_gnd0, SDMA_CTRL3_PLB_wrBurst => net_gnd0, SDMA_CTRL3_PLB_wrDBus => net_gnd64, SDMA_CTRL3_Sl_addrAck => open, SDMA_CTRL3_Sl_SSize => open, SDMA_CTRL3_Sl_wait => open, SDMA_CTRL3_Sl_rearbitrate => open, SDMA_CTRL3_Sl_wrDAck => open, SDMA_CTRL3_Sl_wrComp => open, SDMA_CTRL3_Sl_wrBTerm => open, SDMA_CTRL3_Sl_rdDBus => open, SDMA_CTRL3_Sl_rdWdAddr => open, SDMA_CTRL3_Sl_rdDAck => open, SDMA_CTRL3_Sl_rdComp => open, SDMA_CTRL3_Sl_rdBTerm => open, SDMA_CTRL3_Sl_MBusy => open, SDMA_CTRL3_Sl_MRdErr => open, SDMA_CTRL3_Sl_MWrErr => open, SDMA_CTRL3_Sl_MIRQ => open, PIM3_Addr => net_gnd32(0 to 31), PIM3_AddrReq => net_gnd0, PIM3_AddrAck => open, PIM3_RNW => net_gnd0, PIM3_Size => net_gnd4(0 to 3), PIM3_RdModWr => net_gnd0, PIM3_WrFIFO_Data => net_gnd64(0 to 63), PIM3_WrFIFO_BE => net_gnd8(0 to 7), PIM3_WrFIFO_Push => net_gnd0, PIM3_RdFIFO_Data => open, PIM3_RdFIFO_Pop => net_gnd0, PIM3_RdFIFO_RdWdAddr => open, PIM3_WrFIFO_Empty => open, PIM3_WrFIFO_AlmostFull => open, PIM3_WrFIFO_Flush => net_gnd0, PIM3_RdFIFO_Empty => open, PIM3_RdFIFO_Flush => net_gnd0, PIM3_RdFIFO_Latency => open, PIM3_InitDone => open, PPC440MC3_MIMCReadNotWrite => net_gnd0, PPC440MC3_MIMCAddress => net_gnd36, PPC440MC3_MIMCAddressValid => net_gnd0, PPC440MC3_MIMCWriteData => net_gnd128, PPC440MC3_MIMCWriteDataValid => net_gnd0, PPC440MC3_MIMCByteEnable => net_gnd16, PPC440MC3_MIMCBankConflict => net_gnd0, PPC440MC3_MIMCRowConflict => net_gnd0, PPC440MC3_MCMIReadData => open, PPC440MC3_MCMIReadDataValid => open, PPC440MC3_MCMIReadDataErr => open, PPC440MC3_MCMIAddrReadyToAccept => open, VFBC3_Cmd_Clk => net_gnd0, VFBC3_Cmd_Reset => net_gnd0, VFBC3_Cmd_Data => net_gnd32(0 to 31), VFBC3_Cmd_Write => net_gnd0, VFBC3_Cmd_End => net_gnd0, VFBC3_Cmd_Full => open, VFBC3_Cmd_Almost_Full => open, VFBC3_Cmd_Idle => open, VFBC3_Wd_Clk => net_gnd0, VFBC3_Wd_Reset => net_gnd0, VFBC3_Wd_Write => net_gnd0, VFBC3_Wd_End_Burst => net_gnd0, VFBC3_Wd_Flush => net_gnd0, VFBC3_Wd_Data => net_gnd32(0 to 31), VFBC3_Wd_Data_BE => net_gnd4(0 to 3), VFBC3_Wd_Full => open, VFBC3_Wd_Almost_Full => open, VFBC3_Rd_Clk => net_gnd0, VFBC3_Rd_Reset => net_gnd0, VFBC3_Rd_Read => net_gnd0, VFBC3_Rd_End_Burst => net_gnd0, VFBC3_Rd_Flush => net_gnd0, VFBC3_Rd_Data => open, VFBC3_Rd_Empty => open, VFBC3_Rd_Almost_Empty => open, MCB3_cmd_clk => net_gnd0, MCB3_cmd_en => net_gnd0, MCB3_cmd_instr => net_gnd3, MCB3_cmd_bl => net_gnd6, MCB3_cmd_byte_addr => net_gnd30, MCB3_cmd_empty => open, MCB3_cmd_full => open, MCB3_wr_clk => net_gnd0, MCB3_wr_en => net_gnd0, MCB3_wr_mask => net_gnd8(0 to 7), MCB3_wr_data => net_gnd64(0 to 63), MCB3_wr_full => open, MCB3_wr_empty => open, MCB3_wr_count => open, MCB3_wr_underrun => open, MCB3_wr_error => open, MCB3_rd_clk => net_gnd0, MCB3_rd_en => net_gnd0, MCB3_rd_data => open, MCB3_rd_full => open, MCB3_rd_empty => open, MCB3_rd_count => open, MCB3_rd_overflow => open, MCB3_rd_error => open, FSL4_M_Clk => net_vcc0, FSL4_M_Write => net_gnd0, FSL4_M_Data => net_gnd32, FSL4_M_Control => net_gnd0, FSL4_M_Full => open, FSL4_S_Clk => net_gnd0, FSL4_S_Read => net_gnd0, FSL4_S_Data => open, FSL4_S_Control => open, FSL4_S_Exists => open, FSL4_B_M_Clk => net_vcc0, FSL4_B_M_Write => net_gnd0, FSL4_B_M_Data => net_gnd32, FSL4_B_M_Control => net_gnd0, FSL4_B_M_Full => open, FSL4_B_S_Clk => net_gnd0, FSL4_B_S_Read => net_gnd0, FSL4_B_S_Data => open, FSL4_B_S_Control => open, FSL4_B_S_Exists => open, SPLB4_Clk => net_vcc0, SPLB4_Rst => net_gnd0, SPLB4_PLB_ABus => net_gnd32, SPLB4_PLB_PAValid => net_gnd0, SPLB4_PLB_SAValid => net_gnd0, SPLB4_PLB_masterID => net_gnd1(0 downto 0), SPLB4_PLB_RNW => net_gnd0, SPLB4_PLB_BE => net_gnd8, SPLB4_PLB_UABus => net_gnd32, SPLB4_PLB_rdPrim => net_gnd0, SPLB4_PLB_wrPrim => net_gnd0, SPLB4_PLB_abort => net_gnd0, SPLB4_PLB_busLock => net_gnd0, SPLB4_PLB_MSize => net_gnd2, SPLB4_PLB_size => net_gnd4, SPLB4_PLB_type => net_gnd3(2 downto 0), SPLB4_PLB_lockErr => net_gnd0, SPLB4_PLB_wrPendReq => net_gnd0, SPLB4_PLB_wrPendPri => net_gnd2, SPLB4_PLB_rdPendReq => net_gnd0, SPLB4_PLB_rdPendPri => net_gnd2, SPLB4_PLB_reqPri => net_gnd2, SPLB4_PLB_TAttribute => net_gnd16, SPLB4_PLB_rdBurst => net_gnd0, SPLB4_PLB_wrBurst => net_gnd0, SPLB4_PLB_wrDBus => net_gnd64, SPLB4_Sl_addrAck => open, SPLB4_Sl_SSize => open, SPLB4_Sl_wait => open, SPLB4_Sl_rearbitrate => open, SPLB4_Sl_wrDAck => open, SPLB4_Sl_wrComp => open, SPLB4_Sl_wrBTerm => open, SPLB4_Sl_rdDBus => open, SPLB4_Sl_rdWdAddr => open, SPLB4_Sl_rdDAck => open, SPLB4_Sl_rdComp => open, SPLB4_Sl_rdBTerm => open, SPLB4_Sl_MBusy => open, SPLB4_Sl_MRdErr => open, SPLB4_Sl_MWrErr => open, SPLB4_Sl_MIRQ => open, SDMA4_Clk => net_gnd0, SDMA4_Rx_IntOut => open, SDMA4_Tx_IntOut => open, SDMA4_RstOut => open, SDMA4_TX_D => open, SDMA4_TX_Rem => open, SDMA4_TX_SOF => open, SDMA4_TX_EOF => open, SDMA4_TX_SOP => open, SDMA4_TX_EOP => open, SDMA4_TX_Src_Rdy => open, SDMA4_TX_Dst_Rdy => net_vcc0, SDMA4_RX_D => net_gnd32, SDMA4_RX_Rem => net_vcc4, SDMA4_RX_SOF => net_vcc0, SDMA4_RX_EOF => net_vcc0, SDMA4_RX_SOP => net_vcc0, SDMA4_RX_EOP => net_vcc0, SDMA4_RX_Src_Rdy => net_vcc0, SDMA4_RX_Dst_Rdy => open, SDMA_CTRL4_Clk => net_vcc0, SDMA_CTRL4_Rst => net_gnd0, SDMA_CTRL4_PLB_ABus => net_gnd32, SDMA_CTRL4_PLB_PAValid => net_gnd0, SDMA_CTRL4_PLB_SAValid => net_gnd0, SDMA_CTRL4_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL4_PLB_RNW => net_gnd0, SDMA_CTRL4_PLB_BE => net_gnd8, SDMA_CTRL4_PLB_UABus => net_gnd32, SDMA_CTRL4_PLB_rdPrim => net_gnd0, SDMA_CTRL4_PLB_wrPrim => net_gnd0, SDMA_CTRL4_PLB_abort => net_gnd0, SDMA_CTRL4_PLB_busLock => net_gnd0, SDMA_CTRL4_PLB_MSize => net_gnd2, SDMA_CTRL4_PLB_size => net_gnd4, SDMA_CTRL4_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL4_PLB_lockErr => net_gnd0, SDMA_CTRL4_PLB_wrPendReq => net_gnd0, SDMA_CTRL4_PLB_wrPendPri => net_gnd2, SDMA_CTRL4_PLB_rdPendReq => net_gnd0, SDMA_CTRL4_PLB_rdPendPri => net_gnd2, SDMA_CTRL4_PLB_reqPri => net_gnd2, SDMA_CTRL4_PLB_TAttribute => net_gnd16, SDMA_CTRL4_PLB_rdBurst => net_gnd0, SDMA_CTRL4_PLB_wrBurst => net_gnd0, SDMA_CTRL4_PLB_wrDBus => net_gnd64, SDMA_CTRL4_Sl_addrAck => open, SDMA_CTRL4_Sl_SSize => open, SDMA_CTRL4_Sl_wait => open, SDMA_CTRL4_Sl_rearbitrate => open, SDMA_CTRL4_Sl_wrDAck => open, SDMA_CTRL4_Sl_wrComp => open, SDMA_CTRL4_Sl_wrBTerm => open, SDMA_CTRL4_Sl_rdDBus => open, SDMA_CTRL4_Sl_rdWdAddr => open, SDMA_CTRL4_Sl_rdDAck => open, SDMA_CTRL4_Sl_rdComp => open, SDMA_CTRL4_Sl_rdBTerm => open, SDMA_CTRL4_Sl_MBusy => open, SDMA_CTRL4_Sl_MRdErr => open, SDMA_CTRL4_Sl_MWrErr => open, SDMA_CTRL4_Sl_MIRQ => open, PIM4_Addr => net_gnd32(0 to 31), PIM4_AddrReq => net_gnd0, PIM4_AddrAck => open, PIM4_RNW => net_gnd0, PIM4_Size => net_gnd4(0 to 3), PIM4_RdModWr => net_gnd0, PIM4_WrFIFO_Data => net_gnd64(0 to 63), PIM4_WrFIFO_BE => net_gnd8(0 to 7), PIM4_WrFIFO_Push => net_gnd0, PIM4_RdFIFO_Data => open, PIM4_RdFIFO_Pop => net_gnd0, PIM4_RdFIFO_RdWdAddr => open, PIM4_WrFIFO_Empty => open, PIM4_WrFIFO_AlmostFull => open, PIM4_WrFIFO_Flush => net_gnd0, PIM4_RdFIFO_Empty => open, PIM4_RdFIFO_Flush => net_gnd0, PIM4_RdFIFO_Latency => open, PIM4_InitDone => open, PPC440MC4_MIMCReadNotWrite => net_gnd0, PPC440MC4_MIMCAddress => net_gnd36, PPC440MC4_MIMCAddressValid => net_gnd0, PPC440MC4_MIMCWriteData => net_gnd128, PPC440MC4_MIMCWriteDataValid => net_gnd0, PPC440MC4_MIMCByteEnable => net_gnd16, PPC440MC4_MIMCBankConflict => net_gnd0, PPC440MC4_MIMCRowConflict => net_gnd0, PPC440MC4_MCMIReadData => open, PPC440MC4_MCMIReadDataValid => open, PPC440MC4_MCMIReadDataErr => open, PPC440MC4_MCMIAddrReadyToAccept => open, VFBC4_Cmd_Clk => net_gnd0, VFBC4_Cmd_Reset => net_gnd0, VFBC4_Cmd_Data => net_gnd32(0 to 31), VFBC4_Cmd_Write => net_gnd0, VFBC4_Cmd_End => net_gnd0, VFBC4_Cmd_Full => open, VFBC4_Cmd_Almost_Full => open, VFBC4_Cmd_Idle => open, VFBC4_Wd_Clk => net_gnd0, VFBC4_Wd_Reset => net_gnd0, VFBC4_Wd_Write => net_gnd0, VFBC4_Wd_End_Burst => net_gnd0, VFBC4_Wd_Flush => net_gnd0, VFBC4_Wd_Data => net_gnd32(0 to 31), VFBC4_Wd_Data_BE => net_gnd4(0 to 3), VFBC4_Wd_Full => open, VFBC4_Wd_Almost_Full => open, VFBC4_Rd_Clk => net_gnd0, VFBC4_Rd_Reset => net_gnd0, VFBC4_Rd_Read => net_gnd0, VFBC4_Rd_End_Burst => net_gnd0, VFBC4_Rd_Flush => net_gnd0, VFBC4_Rd_Data => open, VFBC4_Rd_Empty => open, VFBC4_Rd_Almost_Empty => open, MCB4_cmd_clk => net_gnd0, MCB4_cmd_en => net_gnd0, MCB4_cmd_instr => net_gnd3, MCB4_cmd_bl => net_gnd6, MCB4_cmd_byte_addr => net_gnd30, MCB4_cmd_empty => open, MCB4_cmd_full => open, MCB4_wr_clk => net_gnd0, MCB4_wr_en => net_gnd0, MCB4_wr_mask => net_gnd8(0 to 7), MCB4_wr_data => net_gnd64(0 to 63), MCB4_wr_full => open, MCB4_wr_empty => open, MCB4_wr_count => open, MCB4_wr_underrun => open, MCB4_wr_error => open, MCB4_rd_clk => net_gnd0, MCB4_rd_en => net_gnd0, MCB4_rd_data => open, MCB4_rd_full => open, MCB4_rd_empty => open, MCB4_rd_count => open, MCB4_rd_overflow => open, MCB4_rd_error => open, FSL5_M_Clk => net_vcc0, FSL5_M_Write => net_gnd0, FSL5_M_Data => net_gnd32, FSL5_M_Control => net_gnd0, FSL5_M_Full => open, FSL5_S_Clk => net_gnd0, FSL5_S_Read => net_gnd0, FSL5_S_Data => open, FSL5_S_Control => open, FSL5_S_Exists => open, FSL5_B_M_Clk => net_vcc0, FSL5_B_M_Write => net_gnd0, FSL5_B_M_Data => net_gnd32, FSL5_B_M_Control => net_gnd0, FSL5_B_M_Full => open, FSL5_B_S_Clk => net_gnd0, FSL5_B_S_Read => net_gnd0, FSL5_B_S_Data => open, FSL5_B_S_Control => open, FSL5_B_S_Exists => open, SPLB5_Clk => net_vcc0, SPLB5_Rst => net_gnd0, SPLB5_PLB_ABus => net_gnd32, SPLB5_PLB_PAValid => net_gnd0, SPLB5_PLB_SAValid => net_gnd0, SPLB5_PLB_masterID => net_gnd1(0 downto 0), SPLB5_PLB_RNW => net_gnd0, SPLB5_PLB_BE => net_gnd8, SPLB5_PLB_UABus => net_gnd32, SPLB5_PLB_rdPrim => net_gnd0, SPLB5_PLB_wrPrim => net_gnd0, SPLB5_PLB_abort => net_gnd0, SPLB5_PLB_busLock => net_gnd0, SPLB5_PLB_MSize => net_gnd2, SPLB5_PLB_size => net_gnd4, SPLB5_PLB_type => net_gnd3(2 downto 0), SPLB5_PLB_lockErr => net_gnd0, SPLB5_PLB_wrPendReq => net_gnd0, SPLB5_PLB_wrPendPri => net_gnd2, SPLB5_PLB_rdPendReq => net_gnd0, SPLB5_PLB_rdPendPri => net_gnd2, SPLB5_PLB_reqPri => net_gnd2, SPLB5_PLB_TAttribute => net_gnd16, SPLB5_PLB_rdBurst => net_gnd0, SPLB5_PLB_wrBurst => net_gnd0, SPLB5_PLB_wrDBus => net_gnd64, SPLB5_Sl_addrAck => open, SPLB5_Sl_SSize => open, SPLB5_Sl_wait => open, SPLB5_Sl_rearbitrate => open, SPLB5_Sl_wrDAck => open, SPLB5_Sl_wrComp => open, SPLB5_Sl_wrBTerm => open, SPLB5_Sl_rdDBus => open, SPLB5_Sl_rdWdAddr => open, SPLB5_Sl_rdDAck => open, SPLB5_Sl_rdComp => open, SPLB5_Sl_rdBTerm => open, SPLB5_Sl_MBusy => open, SPLB5_Sl_MRdErr => open, SPLB5_Sl_MWrErr => open, SPLB5_Sl_MIRQ => open, SDMA5_Clk => net_gnd0, SDMA5_Rx_IntOut => open, SDMA5_Tx_IntOut => open, SDMA5_RstOut => open, SDMA5_TX_D => open, SDMA5_TX_Rem => open, SDMA5_TX_SOF => open, SDMA5_TX_EOF => open, SDMA5_TX_SOP => open, SDMA5_TX_EOP => open, SDMA5_TX_Src_Rdy => open, SDMA5_TX_Dst_Rdy => net_vcc0, SDMA5_RX_D => net_gnd32, SDMA5_RX_Rem => net_vcc4, SDMA5_RX_SOF => net_vcc0, SDMA5_RX_EOF => net_vcc0, SDMA5_RX_SOP => net_vcc0, SDMA5_RX_EOP => net_vcc0, SDMA5_RX_Src_Rdy => net_vcc0, SDMA5_RX_Dst_Rdy => open, SDMA_CTRL5_Clk => net_vcc0, SDMA_CTRL5_Rst => net_gnd0, SDMA_CTRL5_PLB_ABus => net_gnd32, SDMA_CTRL5_PLB_PAValid => net_gnd0, SDMA_CTRL5_PLB_SAValid => net_gnd0, SDMA_CTRL5_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL5_PLB_RNW => net_gnd0, SDMA_CTRL5_PLB_BE => net_gnd8, SDMA_CTRL5_PLB_UABus => net_gnd32, SDMA_CTRL5_PLB_rdPrim => net_gnd0, SDMA_CTRL5_PLB_wrPrim => net_gnd0, SDMA_CTRL5_PLB_abort => net_gnd0, SDMA_CTRL5_PLB_busLock => net_gnd0, SDMA_CTRL5_PLB_MSize => net_gnd2, SDMA_CTRL5_PLB_size => net_gnd4, SDMA_CTRL5_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL5_PLB_lockErr => net_gnd0, SDMA_CTRL5_PLB_wrPendReq => net_gnd0, SDMA_CTRL5_PLB_wrPendPri => net_gnd2, SDMA_CTRL5_PLB_rdPendReq => net_gnd0, SDMA_CTRL5_PLB_rdPendPri => net_gnd2, SDMA_CTRL5_PLB_reqPri => net_gnd2, SDMA_CTRL5_PLB_TAttribute => net_gnd16, SDMA_CTRL5_PLB_rdBurst => net_gnd0, SDMA_CTRL5_PLB_wrBurst => net_gnd0, SDMA_CTRL5_PLB_wrDBus => net_gnd64, SDMA_CTRL5_Sl_addrAck => open, SDMA_CTRL5_Sl_SSize => open, SDMA_CTRL5_Sl_wait => open, SDMA_CTRL5_Sl_rearbitrate => open, SDMA_CTRL5_Sl_wrDAck => open, SDMA_CTRL5_Sl_wrComp => open, SDMA_CTRL5_Sl_wrBTerm => open, SDMA_CTRL5_Sl_rdDBus => open, SDMA_CTRL5_Sl_rdWdAddr => open, SDMA_CTRL5_Sl_rdDAck => open, SDMA_CTRL5_Sl_rdComp => open, SDMA_CTRL5_Sl_rdBTerm => open, SDMA_CTRL5_Sl_MBusy => open, SDMA_CTRL5_Sl_MRdErr => open, SDMA_CTRL5_Sl_MWrErr => open, SDMA_CTRL5_Sl_MIRQ => open, PIM5_Addr => net_gnd32(0 to 31), PIM5_AddrReq => net_gnd0, PIM5_AddrAck => open, PIM5_RNW => net_gnd0, PIM5_Size => net_gnd4(0 to 3), PIM5_RdModWr => net_gnd0, PIM5_WrFIFO_Data => net_gnd64(0 to 63), PIM5_WrFIFO_BE => net_gnd8(0 to 7), PIM5_WrFIFO_Push => net_gnd0, PIM5_RdFIFO_Data => open, PIM5_RdFIFO_Pop => net_gnd0, PIM5_RdFIFO_RdWdAddr => open, PIM5_WrFIFO_Empty => open, PIM5_WrFIFO_AlmostFull => open, PIM5_WrFIFO_Flush => net_gnd0, PIM5_RdFIFO_Empty => open, PIM5_RdFIFO_Flush => net_gnd0, PIM5_RdFIFO_Latency => open, PIM5_InitDone => open, PPC440MC5_MIMCReadNotWrite => net_gnd0, PPC440MC5_MIMCAddress => net_gnd36, PPC440MC5_MIMCAddressValid => net_gnd0, PPC440MC5_MIMCWriteData => net_gnd128, PPC440MC5_MIMCWriteDataValid => net_gnd0, PPC440MC5_MIMCByteEnable => net_gnd16, PPC440MC5_MIMCBankConflict => net_gnd0, PPC440MC5_MIMCRowConflict => net_gnd0, PPC440MC5_MCMIReadData => open, PPC440MC5_MCMIReadDataValid => open, PPC440MC5_MCMIReadDataErr => open, PPC440MC5_MCMIAddrReadyToAccept => open, VFBC5_Cmd_Clk => net_gnd0, VFBC5_Cmd_Reset => net_gnd0, VFBC5_Cmd_Data => net_gnd32(0 to 31), VFBC5_Cmd_Write => net_gnd0, VFBC5_Cmd_End => net_gnd0, VFBC5_Cmd_Full => open, VFBC5_Cmd_Almost_Full => open, VFBC5_Cmd_Idle => open, VFBC5_Wd_Clk => net_gnd0, VFBC5_Wd_Reset => net_gnd0, VFBC5_Wd_Write => net_gnd0, VFBC5_Wd_End_Burst => net_gnd0, VFBC5_Wd_Flush => net_gnd0, VFBC5_Wd_Data => net_gnd32(0 to 31), VFBC5_Wd_Data_BE => net_gnd4(0 to 3), VFBC5_Wd_Full => open, VFBC5_Wd_Almost_Full => open, VFBC5_Rd_Clk => net_gnd0, VFBC5_Rd_Reset => net_gnd0, VFBC5_Rd_Read => net_gnd0, VFBC5_Rd_End_Burst => net_gnd0, VFBC5_Rd_Flush => net_gnd0, VFBC5_Rd_Data => open, VFBC5_Rd_Empty => open, VFBC5_Rd_Almost_Empty => open, MCB5_cmd_clk => net_gnd0, MCB5_cmd_en => net_gnd0, MCB5_cmd_instr => net_gnd3, MCB5_cmd_bl => net_gnd6, MCB5_cmd_byte_addr => net_gnd30, MCB5_cmd_empty => open, MCB5_cmd_full => open, MCB5_wr_clk => net_gnd0, MCB5_wr_en => net_gnd0, MCB5_wr_mask => net_gnd8(0 to 7), MCB5_wr_data => net_gnd64(0 to 63), MCB5_wr_full => open, MCB5_wr_empty => open, MCB5_wr_count => open, MCB5_wr_underrun => open, MCB5_wr_error => open, MCB5_rd_clk => net_gnd0, MCB5_rd_en => net_gnd0, MCB5_rd_data => open, MCB5_rd_full => open, MCB5_rd_empty => open, MCB5_rd_count => open, MCB5_rd_overflow => open, MCB5_rd_error => open, FSL6_M_Clk => net_vcc0, FSL6_M_Write => net_gnd0, FSL6_M_Data => net_gnd32, FSL6_M_Control => net_gnd0, FSL6_M_Full => open, FSL6_S_Clk => net_gnd0, FSL6_S_Read => net_gnd0, FSL6_S_Data => open, FSL6_S_Control => open, FSL6_S_Exists => open, FSL6_B_M_Clk => net_vcc0, FSL6_B_M_Write => net_gnd0, FSL6_B_M_Data => net_gnd32, FSL6_B_M_Control => net_gnd0, FSL6_B_M_Full => open, FSL6_B_S_Clk => net_gnd0, FSL6_B_S_Read => net_gnd0, FSL6_B_S_Data => open, FSL6_B_S_Control => open, FSL6_B_S_Exists => open, SPLB6_Clk => net_vcc0, SPLB6_Rst => net_gnd0, SPLB6_PLB_ABus => net_gnd32, SPLB6_PLB_PAValid => net_gnd0, SPLB6_PLB_SAValid => net_gnd0, SPLB6_PLB_masterID => net_gnd1(0 downto 0), SPLB6_PLB_RNW => net_gnd0, SPLB6_PLB_BE => net_gnd8, SPLB6_PLB_UABus => net_gnd32, SPLB6_PLB_rdPrim => net_gnd0, SPLB6_PLB_wrPrim => net_gnd0, SPLB6_PLB_abort => net_gnd0, SPLB6_PLB_busLock => net_gnd0, SPLB6_PLB_MSize => net_gnd2, SPLB6_PLB_size => net_gnd4, SPLB6_PLB_type => net_gnd3(2 downto 0), SPLB6_PLB_lockErr => net_gnd0, SPLB6_PLB_wrPendReq => net_gnd0, SPLB6_PLB_wrPendPri => net_gnd2, SPLB6_PLB_rdPendReq => net_gnd0, SPLB6_PLB_rdPendPri => net_gnd2, SPLB6_PLB_reqPri => net_gnd2, SPLB6_PLB_TAttribute => net_gnd16, SPLB6_PLB_rdBurst => net_gnd0, SPLB6_PLB_wrBurst => net_gnd0, SPLB6_PLB_wrDBus => net_gnd64, SPLB6_Sl_addrAck => open, SPLB6_Sl_SSize => open, SPLB6_Sl_wait => open, SPLB6_Sl_rearbitrate => open, SPLB6_Sl_wrDAck => open, SPLB6_Sl_wrComp => open, SPLB6_Sl_wrBTerm => open, SPLB6_Sl_rdDBus => open, SPLB6_Sl_rdWdAddr => open, SPLB6_Sl_rdDAck => open, SPLB6_Sl_rdComp => open, SPLB6_Sl_rdBTerm => open, SPLB6_Sl_MBusy => open, SPLB6_Sl_MRdErr => open, SPLB6_Sl_MWrErr => open, SPLB6_Sl_MIRQ => open, SDMA6_Clk => net_gnd0, SDMA6_Rx_IntOut => open, SDMA6_Tx_IntOut => open, SDMA6_RstOut => open, SDMA6_TX_D => open, SDMA6_TX_Rem => open, SDMA6_TX_SOF => open, SDMA6_TX_EOF => open, SDMA6_TX_SOP => open, SDMA6_TX_EOP => open, SDMA6_TX_Src_Rdy => open, SDMA6_TX_Dst_Rdy => net_vcc0, SDMA6_RX_D => net_gnd32, SDMA6_RX_Rem => net_vcc4, SDMA6_RX_SOF => net_vcc0, SDMA6_RX_EOF => net_vcc0, SDMA6_RX_SOP => net_vcc0, SDMA6_RX_EOP => net_vcc0, SDMA6_RX_Src_Rdy => net_vcc0, SDMA6_RX_Dst_Rdy => open, SDMA_CTRL6_Clk => net_vcc0, SDMA_CTRL6_Rst => net_gnd0, SDMA_CTRL6_PLB_ABus => net_gnd32, SDMA_CTRL6_PLB_PAValid => net_gnd0, SDMA_CTRL6_PLB_SAValid => net_gnd0, SDMA_CTRL6_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL6_PLB_RNW => net_gnd0, SDMA_CTRL6_PLB_BE => net_gnd8, SDMA_CTRL6_PLB_UABus => net_gnd32, SDMA_CTRL6_PLB_rdPrim => net_gnd0, SDMA_CTRL6_PLB_wrPrim => net_gnd0, SDMA_CTRL6_PLB_abort => net_gnd0, SDMA_CTRL6_PLB_busLock => net_gnd0, SDMA_CTRL6_PLB_MSize => net_gnd2, SDMA_CTRL6_PLB_size => net_gnd4, SDMA_CTRL6_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL6_PLB_lockErr => net_gnd0, SDMA_CTRL6_PLB_wrPendReq => net_gnd0, SDMA_CTRL6_PLB_wrPendPri => net_gnd2, SDMA_CTRL6_PLB_rdPendReq => net_gnd0, SDMA_CTRL6_PLB_rdPendPri => net_gnd2, SDMA_CTRL6_PLB_reqPri => net_gnd2, SDMA_CTRL6_PLB_TAttribute => net_gnd16, SDMA_CTRL6_PLB_rdBurst => net_gnd0, SDMA_CTRL6_PLB_wrBurst => net_gnd0, SDMA_CTRL6_PLB_wrDBus => net_gnd64, SDMA_CTRL6_Sl_addrAck => open, SDMA_CTRL6_Sl_SSize => open, SDMA_CTRL6_Sl_wait => open, SDMA_CTRL6_Sl_rearbitrate => open, SDMA_CTRL6_Sl_wrDAck => open, SDMA_CTRL6_Sl_wrComp => open, SDMA_CTRL6_Sl_wrBTerm => open, SDMA_CTRL6_Sl_rdDBus => open, SDMA_CTRL6_Sl_rdWdAddr => open, SDMA_CTRL6_Sl_rdDAck => open, SDMA_CTRL6_Sl_rdComp => open, SDMA_CTRL6_Sl_rdBTerm => open, SDMA_CTRL6_Sl_MBusy => open, SDMA_CTRL6_Sl_MRdErr => open, SDMA_CTRL6_Sl_MWrErr => open, SDMA_CTRL6_Sl_MIRQ => open, PIM6_Addr => net_gnd32(0 to 31), PIM6_AddrReq => net_gnd0, PIM6_AddrAck => open, PIM6_RNW => net_gnd0, PIM6_Size => net_gnd4(0 to 3), PIM6_RdModWr => net_gnd0, PIM6_WrFIFO_Data => net_gnd64(0 to 63), PIM6_WrFIFO_BE => net_gnd8(0 to 7), PIM6_WrFIFO_Push => net_gnd0, PIM6_RdFIFO_Data => open, PIM6_RdFIFO_Pop => net_gnd0, PIM6_RdFIFO_RdWdAddr => open, PIM6_WrFIFO_Empty => open, PIM6_WrFIFO_AlmostFull => open, PIM6_WrFIFO_Flush => net_gnd0, PIM6_RdFIFO_Empty => open, PIM6_RdFIFO_Flush => net_gnd0, PIM6_RdFIFO_Latency => open, PIM6_InitDone => open, PPC440MC6_MIMCReadNotWrite => net_gnd0, PPC440MC6_MIMCAddress => net_gnd36, PPC440MC6_MIMCAddressValid => net_gnd0, PPC440MC6_MIMCWriteData => net_gnd128, PPC440MC6_MIMCWriteDataValid => net_gnd0, PPC440MC6_MIMCByteEnable => net_gnd16, PPC440MC6_MIMCBankConflict => net_gnd0, PPC440MC6_MIMCRowConflict => net_gnd0, PPC440MC6_MCMIReadData => open, PPC440MC6_MCMIReadDataValid => open, PPC440MC6_MCMIReadDataErr => open, PPC440MC6_MCMIAddrReadyToAccept => open, VFBC6_Cmd_Clk => net_gnd0, VFBC6_Cmd_Reset => net_gnd0, VFBC6_Cmd_Data => net_gnd32(0 to 31), VFBC6_Cmd_Write => net_gnd0, VFBC6_Cmd_End => net_gnd0, VFBC6_Cmd_Full => open, VFBC6_Cmd_Almost_Full => open, VFBC6_Cmd_Idle => open, VFBC6_Wd_Clk => net_gnd0, VFBC6_Wd_Reset => net_gnd0, VFBC6_Wd_Write => net_gnd0, VFBC6_Wd_End_Burst => net_gnd0, VFBC6_Wd_Flush => net_gnd0, VFBC6_Wd_Data => net_gnd32(0 to 31), VFBC6_Wd_Data_BE => net_gnd4(0 to 3), VFBC6_Wd_Full => open, VFBC6_Wd_Almost_Full => open, VFBC6_Rd_Clk => net_gnd0, VFBC6_Rd_Reset => net_gnd0, VFBC6_Rd_Read => net_gnd0, VFBC6_Rd_End_Burst => net_gnd0, VFBC6_Rd_Flush => net_gnd0, VFBC6_Rd_Data => open, VFBC6_Rd_Empty => open, VFBC6_Rd_Almost_Empty => open, MCB6_cmd_clk => net_gnd0, MCB6_cmd_en => net_gnd0, MCB6_cmd_instr => net_gnd3, MCB6_cmd_bl => net_gnd6, MCB6_cmd_byte_addr => net_gnd30, MCB6_cmd_empty => open, MCB6_cmd_full => open, MCB6_wr_clk => net_gnd0, MCB6_wr_en => net_gnd0, MCB6_wr_mask => net_gnd8(0 to 7), MCB6_wr_data => net_gnd64(0 to 63), MCB6_wr_full => open, MCB6_wr_empty => open, MCB6_wr_count => open, MCB6_wr_underrun => open, MCB6_wr_error => open, MCB6_rd_clk => net_gnd0, MCB6_rd_en => net_gnd0, MCB6_rd_data => open, MCB6_rd_full => open, MCB6_rd_empty => open, MCB6_rd_count => open, MCB6_rd_overflow => open, MCB6_rd_error => open, FSL7_M_Clk => net_vcc0, FSL7_M_Write => net_gnd0, FSL7_M_Data => net_gnd32, FSL7_M_Control => net_gnd0, FSL7_M_Full => open, FSL7_S_Clk => net_gnd0, FSL7_S_Read => net_gnd0, FSL7_S_Data => open, FSL7_S_Control => open, FSL7_S_Exists => open, FSL7_B_M_Clk => net_vcc0, FSL7_B_M_Write => net_gnd0, FSL7_B_M_Data => net_gnd32, FSL7_B_M_Control => net_gnd0, FSL7_B_M_Full => open, FSL7_B_S_Clk => net_gnd0, FSL7_B_S_Read => net_gnd0, FSL7_B_S_Data => open, FSL7_B_S_Control => open, FSL7_B_S_Exists => open, SPLB7_Clk => net_vcc0, SPLB7_Rst => net_gnd0, SPLB7_PLB_ABus => net_gnd32, SPLB7_PLB_PAValid => net_gnd0, SPLB7_PLB_SAValid => net_gnd0, SPLB7_PLB_masterID => net_gnd1(0 downto 0), SPLB7_PLB_RNW => net_gnd0, SPLB7_PLB_BE => net_gnd8, SPLB7_PLB_UABus => net_gnd32, SPLB7_PLB_rdPrim => net_gnd0, SPLB7_PLB_wrPrim => net_gnd0, SPLB7_PLB_abort => net_gnd0, SPLB7_PLB_busLock => net_gnd0, SPLB7_PLB_MSize => net_gnd2, SPLB7_PLB_size => net_gnd4, SPLB7_PLB_type => net_gnd3(2 downto 0), SPLB7_PLB_lockErr => net_gnd0, SPLB7_PLB_wrPendReq => net_gnd0, SPLB7_PLB_wrPendPri => net_gnd2, SPLB7_PLB_rdPendReq => net_gnd0, SPLB7_PLB_rdPendPri => net_gnd2, SPLB7_PLB_reqPri => net_gnd2, SPLB7_PLB_TAttribute => net_gnd16, SPLB7_PLB_rdBurst => net_gnd0, SPLB7_PLB_wrBurst => net_gnd0, SPLB7_PLB_wrDBus => net_gnd64, SPLB7_Sl_addrAck => open, SPLB7_Sl_SSize => open, SPLB7_Sl_wait => open, SPLB7_Sl_rearbitrate => open, SPLB7_Sl_wrDAck => open, SPLB7_Sl_wrComp => open, SPLB7_Sl_wrBTerm => open, SPLB7_Sl_rdDBus => open, SPLB7_Sl_rdWdAddr => open, SPLB7_Sl_rdDAck => open, SPLB7_Sl_rdComp => open, SPLB7_Sl_rdBTerm => open, SPLB7_Sl_MBusy => open, SPLB7_Sl_MRdErr => open, SPLB7_Sl_MWrErr => open, SPLB7_Sl_MIRQ => open, SDMA7_Clk => net_gnd0, SDMA7_Rx_IntOut => open, SDMA7_Tx_IntOut => open, SDMA7_RstOut => open, SDMA7_TX_D => open, SDMA7_TX_Rem => open, SDMA7_TX_SOF => open, SDMA7_TX_EOF => open, SDMA7_TX_SOP => open, SDMA7_TX_EOP => open, SDMA7_TX_Src_Rdy => open, SDMA7_TX_Dst_Rdy => net_vcc0, SDMA7_RX_D => net_gnd32, SDMA7_RX_Rem => net_vcc4, SDMA7_RX_SOF => net_vcc0, SDMA7_RX_EOF => net_vcc0, SDMA7_RX_SOP => net_vcc0, SDMA7_RX_EOP => net_vcc0, SDMA7_RX_Src_Rdy => net_vcc0, SDMA7_RX_Dst_Rdy => open, SDMA_CTRL7_Clk => net_vcc0, SDMA_CTRL7_Rst => net_gnd0, SDMA_CTRL7_PLB_ABus => net_gnd32, SDMA_CTRL7_PLB_PAValid => net_gnd0, SDMA_CTRL7_PLB_SAValid => net_gnd0, SDMA_CTRL7_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL7_PLB_RNW => net_gnd0, SDMA_CTRL7_PLB_BE => net_gnd8, SDMA_CTRL7_PLB_UABus => net_gnd32, SDMA_CTRL7_PLB_rdPrim => net_gnd0, SDMA_CTRL7_PLB_wrPrim => net_gnd0, SDMA_CTRL7_PLB_abort => net_gnd0, SDMA_CTRL7_PLB_busLock => net_gnd0, SDMA_CTRL7_PLB_MSize => net_gnd2, SDMA_CTRL7_PLB_size => net_gnd4, SDMA_CTRL7_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL7_PLB_lockErr => net_gnd0, SDMA_CTRL7_PLB_wrPendReq => net_gnd0, SDMA_CTRL7_PLB_wrPendPri => net_gnd2, SDMA_CTRL7_PLB_rdPendReq => net_gnd0, SDMA_CTRL7_PLB_rdPendPri => net_gnd2, SDMA_CTRL7_PLB_reqPri => net_gnd2, SDMA_CTRL7_PLB_TAttribute => net_gnd16, SDMA_CTRL7_PLB_rdBurst => net_gnd0, SDMA_CTRL7_PLB_wrBurst => net_gnd0, SDMA_CTRL7_PLB_wrDBus => net_gnd64, SDMA_CTRL7_Sl_addrAck => open, SDMA_CTRL7_Sl_SSize => open, SDMA_CTRL7_Sl_wait => open, SDMA_CTRL7_Sl_rearbitrate => open, SDMA_CTRL7_Sl_wrDAck => open, SDMA_CTRL7_Sl_wrComp => open, SDMA_CTRL7_Sl_wrBTerm => open, SDMA_CTRL7_Sl_rdDBus => open, SDMA_CTRL7_Sl_rdWdAddr => open, SDMA_CTRL7_Sl_rdDAck => open, SDMA_CTRL7_Sl_rdComp => open, SDMA_CTRL7_Sl_rdBTerm => open, SDMA_CTRL7_Sl_MBusy => open, SDMA_CTRL7_Sl_MRdErr => open, SDMA_CTRL7_Sl_MWrErr => open, SDMA_CTRL7_Sl_MIRQ => open, PIM7_Addr => net_gnd32(0 to 31), PIM7_AddrReq => net_gnd0, PIM7_AddrAck => open, PIM7_RNW => net_gnd0, PIM7_Size => net_gnd4(0 to 3), PIM7_RdModWr => net_gnd0, PIM7_WrFIFO_Data => net_gnd64(0 to 63), PIM7_WrFIFO_BE => net_gnd8(0 to 7), PIM7_WrFIFO_Push => net_gnd0, PIM7_RdFIFO_Data => open, PIM7_RdFIFO_Pop => net_gnd0, PIM7_RdFIFO_RdWdAddr => open, PIM7_WrFIFO_Empty => open, PIM7_WrFIFO_AlmostFull => open, PIM7_WrFIFO_Flush => net_gnd0, PIM7_RdFIFO_Empty => open, PIM7_RdFIFO_Flush => net_gnd0, PIM7_RdFIFO_Latency => open, PIM7_InitDone => open, PPC440MC7_MIMCReadNotWrite => net_gnd0, PPC440MC7_MIMCAddress => net_gnd36, PPC440MC7_MIMCAddressValid => net_gnd0, PPC440MC7_MIMCWriteData => net_gnd128, PPC440MC7_MIMCWriteDataValid => net_gnd0, PPC440MC7_MIMCByteEnable => net_gnd16, PPC440MC7_MIMCBankConflict => net_gnd0, PPC440MC7_MIMCRowConflict => net_gnd0, PPC440MC7_MCMIReadData => open, PPC440MC7_MCMIReadDataValid => open, PPC440MC7_MCMIReadDataErr => open, PPC440MC7_MCMIAddrReadyToAccept => open, VFBC7_Cmd_Clk => net_gnd0, VFBC7_Cmd_Reset => net_gnd0, VFBC7_Cmd_Data => net_gnd32(0 to 31), VFBC7_Cmd_Write => net_gnd0, VFBC7_Cmd_End => net_gnd0, VFBC7_Cmd_Full => open, VFBC7_Cmd_Almost_Full => open, VFBC7_Cmd_Idle => open, VFBC7_Wd_Clk => net_gnd0, VFBC7_Wd_Reset => net_gnd0, VFBC7_Wd_Write => net_gnd0, VFBC7_Wd_End_Burst => net_gnd0, VFBC7_Wd_Flush => net_gnd0, VFBC7_Wd_Data => net_gnd32(0 to 31), VFBC7_Wd_Data_BE => net_gnd4(0 to 3), VFBC7_Wd_Full => open, VFBC7_Wd_Almost_Full => open, VFBC7_Rd_Clk => net_gnd0, VFBC7_Rd_Reset => net_gnd0, VFBC7_Rd_Read => net_gnd0, VFBC7_Rd_End_Burst => net_gnd0, VFBC7_Rd_Flush => net_gnd0, VFBC7_Rd_Data => open, VFBC7_Rd_Empty => open, VFBC7_Rd_Almost_Empty => open, MCB7_cmd_clk => net_gnd0, MCB7_cmd_en => net_gnd0, MCB7_cmd_instr => net_gnd3, MCB7_cmd_bl => net_gnd6, MCB7_cmd_byte_addr => net_gnd30, MCB7_cmd_empty => open, MCB7_cmd_full => open, MCB7_wr_clk => net_gnd0, MCB7_wr_en => net_gnd0, MCB7_wr_mask => net_gnd8(0 to 7), MCB7_wr_data => net_gnd64(0 to 63), MCB7_wr_full => open, MCB7_wr_empty => open, MCB7_wr_count => open, MCB7_wr_underrun => open, MCB7_wr_error => open, MCB7_rd_clk => net_gnd0, MCB7_rd_en => net_gnd0, MCB7_rd_data => open, MCB7_rd_full => open, MCB7_rd_empty => open, MCB7_rd_count => open, MCB7_rd_overflow => open, MCB7_rd_error => open, MPMC_CTRL_Clk => net_vcc0, MPMC_CTRL_Rst => net_gnd0, MPMC_CTRL_PLB_ABus => net_gnd32, MPMC_CTRL_PLB_PAValid => net_gnd0, MPMC_CTRL_PLB_SAValid => net_gnd0, MPMC_CTRL_PLB_masterID => net_gnd1(0 downto 0), MPMC_CTRL_PLB_RNW => net_gnd0, MPMC_CTRL_PLB_BE => net_gnd8, MPMC_CTRL_PLB_UABus => net_gnd32, MPMC_CTRL_PLB_rdPrim => net_gnd0, MPMC_CTRL_PLB_wrPrim => net_gnd0, MPMC_CTRL_PLB_abort => net_gnd0, MPMC_CTRL_PLB_busLock => net_gnd0, MPMC_CTRL_PLB_MSize => net_gnd2, MPMC_CTRL_PLB_size => net_gnd4, MPMC_CTRL_PLB_type => net_gnd3(2 downto 0), MPMC_CTRL_PLB_lockErr => net_gnd0, MPMC_CTRL_PLB_wrPendReq => net_gnd0, MPMC_CTRL_PLB_wrPendPri => net_gnd2, MPMC_CTRL_PLB_rdPendReq => net_gnd0, MPMC_CTRL_PLB_rdPendPri => net_gnd2, MPMC_CTRL_PLB_reqPri => net_gnd2, MPMC_CTRL_PLB_TAttribute => net_gnd16, MPMC_CTRL_PLB_rdBurst => net_gnd0, MPMC_CTRL_PLB_wrBurst => net_gnd0, MPMC_CTRL_PLB_wrDBus => net_gnd64, MPMC_CTRL_Sl_addrAck => open, MPMC_CTRL_Sl_SSize => open, MPMC_CTRL_Sl_wait => open, MPMC_CTRL_Sl_rearbitrate => open, MPMC_CTRL_Sl_wrDAck => open, MPMC_CTRL_Sl_wrComp => open, MPMC_CTRL_Sl_wrBTerm => open, MPMC_CTRL_Sl_rdDBus => open, MPMC_CTRL_Sl_rdWdAddr => open, MPMC_CTRL_Sl_rdDAck => open, MPMC_CTRL_Sl_rdComp => open, MPMC_CTRL_Sl_rdBTerm => open, MPMC_CTRL_Sl_MBusy => open, MPMC_CTRL_Sl_MRdErr => open, MPMC_CTRL_Sl_MWrErr => open, MPMC_CTRL_Sl_MIRQ => open, MPMC_Clk0 => clk_125_0000MHzPLL0, MPMC_Clk0_DIV2 => clk_62_5000MHzPLL0, MPMC_Clk90 => clk_125_0000MHz90PLL0, MPMC_Clk_200MHz => clk_200_0000MHz, MPMC_Rst => sys_periph_reset(0), MPMC_Clk_Mem => net_vcc0, MPMC_Clk_Mem_2x => net_vcc0, MPMC_Clk_Mem_2x_180 => net_vcc0, MPMC_Clk_Mem_2x_CE0 => net_vcc0, MPMC_Clk_Mem_2x_CE90 => net_vcc0, MPMC_Clk_Rd_Base => net_vcc0, MPMC_Clk_Mem_2x_bufpll_o => open, MPMC_Clk_Mem_2x_180_bufpll_o => open, MPMC_Clk_Mem_2x_CE0_bufpll_o => open, MPMC_Clk_Mem_2x_CE90_bufpll_o => open, MPMC_PLL_Lock_bufpll_o => open, MPMC_PLL_Lock => net_gnd0, MPMC_Idelayctrl_Rdy_I => net_vcc0, MPMC_Idelayctrl_Rdy_O => open, MPMC_InitDone => open, MPMC_ECC_Intr => open, MPMC_DCM_PSEN => open, MPMC_DCM_PSINCDEC => open, MPMC_DCM_PSDONE => net_gnd0, MPMC_MCB_DRP_Clk => net_vcc0, SDRAM_Clk => open, SDRAM_CE => open, SDRAM_CS_n => open, SDRAM_RAS_n => open, SDRAM_CAS_n => open, SDRAM_WE_n => open, SDRAM_BankAddr => open, SDRAM_Addr => open, SDRAM_DQ => open, SDRAM_DM => open, DDR_Clk => open, DDR_Clk_n => open, DDR_CE => open, DDR_CS_n => open, DDR_RAS_n => open, DDR_CAS_n => open, DDR_WE_n => open, DDR_BankAddr => open, DDR_Addr => open, DDR_DQ => open, DDR_DM => open, DDR_DQS => open, DDR_DQS_Div_O => open, DDR_DQS_Div_I => net_gnd0, DDR2_Clk => fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DDR2_Clk_n => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin, DDR2_CE => fpga_0_DDR2_SDRAM_DDR2_CE_pin, DDR2_CS_n => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin, DDR2_ODT => fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DDR2_RAS_n => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin, DDR2_CAS_n => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin, DDR2_WE_n => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin, DDR2_BankAddr => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DDR2_Addr => fpga_0_DDR2_SDRAM_DDR2_Addr_pin, DDR2_DQ => fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DDR2_DM => fpga_0_DDR2_SDRAM_DDR2_DM_pin, DDR2_DQS => fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DDR2_DQS_n => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin, DDR2_DQS_Div_O => open, DDR2_DQS_Div_I => net_gnd0, DDR3_Clk => open, DDR3_Clk_n => open, DDR3_CE => open, DDR3_CS_n => open, DDR3_ODT => open, DDR3_RAS_n => open, DDR3_CAS_n => open, DDR3_WE_n => open, DDR3_BankAddr => open, DDR3_Addr => open, DDR3_DQ => open, DDR3_DM => open, DDR3_Reset_n => open, DDR3_DQS => open, DDR3_DQS_n => open, mcbx_dram_addr => open, mcbx_dram_ba => open, mcbx_dram_ras_n => open, mcbx_dram_cas_n => open, mcbx_dram_we_n => open, mcbx_dram_cke => open, mcbx_dram_clk => open, mcbx_dram_clk_n => open, mcbx_dram_dq => open, mcbx_dram_dqs => open, mcbx_dram_dqs_n => open, mcbx_dram_udqs => open, mcbx_dram_udqs_n => open, mcbx_dram_udm => open, mcbx_dram_ldm => open, mcbx_dram_odt => open, mcbx_dram_ddr3_rst => open, selfrefresh_enter => net_gnd0, selfrefresh_mode => open, calib_recal => net_gnd0, rzq => open, zio => open ); SRAM : system_sram_wrapper port map ( MCH_SPLB_Clk => clk_125_0000MHzPLL0, RdClk => clk_125_0000MHzPLL0, MCH_SPLB_Rst => mb_plb_SPLB_Rst(1), MCH0_Access_Control => net_gnd0, MCH0_Access_Data => net_gnd32, MCH0_Access_Write => net_gnd0, MCH0_Access_Full => open, MCH0_ReadData_Control => open, MCH0_ReadData_Data => open, MCH0_ReadData_Read => net_gnd0, MCH0_ReadData_Exists => open, MCH1_Access_Control => net_gnd0, MCH1_Access_Data => net_gnd32, MCH1_Access_Write => net_gnd0, MCH1_Access_Full => open, MCH1_ReadData_Control => open, MCH1_ReadData_Data => open, MCH1_ReadData_Read => net_gnd0, MCH1_ReadData_Exists => open, MCH2_Access_Control => net_gnd0, MCH2_Access_Data => net_gnd32, MCH2_Access_Write => net_gnd0, MCH2_Access_Full => open, MCH2_ReadData_Control => open, MCH2_ReadData_Data => open, MCH2_ReadData_Read => net_gnd0, MCH2_ReadData_Exists => open, MCH3_Access_Control => net_gnd0, MCH3_Access_Data => net_gnd32, MCH3_Access_Write => net_gnd0, MCH3_Access_Full => open, MCH3_ReadData_Control => open, MCH3_ReadData_Data => open, MCH3_ReadData_Read => net_gnd0, MCH3_ReadData_Exists => open, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(1), PLB_wrPrim => mb_plb_PLB_wrPrim(1), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(1), Sl_SSize => mb_plb_Sl_SSize(2 to 3), Sl_wait => mb_plb_Sl_wait(1), Sl_rearbitrate => mb_plb_Sl_rearbitrate(1), Sl_wrDAck => mb_plb_Sl_wrDAck(1), Sl_wrComp => mb_plb_Sl_wrComp(1), Sl_wrBTerm => mb_plb_Sl_wrBTerm(1), Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 127), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7), Sl_rdDAck => mb_plb_Sl_rdDAck(1), Sl_rdComp => mb_plb_Sl_rdComp(1), Sl_rdBTerm => mb_plb_Sl_rdBTerm(1), Sl_MBusy => mb_plb_Sl_MBusy(6 to 11), Sl_MWrErr => mb_plb_Sl_MWrErr(6 to 11), Sl_MRdErr => mb_plb_Sl_MRdErr(6 to 11), Sl_MIRQ => mb_plb_Sl_MIRQ(6 to 11), Mem_DQ_I => fpga_0_SRAM_Mem_DQ_pin_I, Mem_DQ_O => fpga_0_SRAM_Mem_DQ_pin_O, Mem_DQ_T => fpga_0_SRAM_Mem_DQ_pin_T, Mem_A => pgassign9, Mem_RPN => open, Mem_CEN => pgassign1(0 to 0), Mem_OEN => pgassign2(0 to 0), Mem_WEN => fpga_0_SRAM_Mem_WEN_pin, Mem_QWEN => open, Mem_BEN => fpga_0_SRAM_Mem_BEN_pin, Mem_CE => open, Mem_ADV_LDN => fpga_0_SRAM_Mem_ADV_LDN_pin, Mem_LBON => open, Mem_CKEN => open, Mem_RNW => open ); PCIe_Bridge : system_pcie_bridge_wrapper port map ( MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(2), PLB_MTimeout => mb_plb_PLB_MTimeout(2), PLB_MIRQ => mb_plb_PLB_MIRQ(2), PLB_MAddrAck => mb_plb_PLB_MAddrAck(2), PLB_MSSize => mb_plb_PLB_MSSize(4 to 5), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(2), PLB_MBusy => mb_plb_PLB_MBusy(2), PLB_MRdErr => mb_plb_PLB_MRdErr(2), PLB_MWrErr => mb_plb_PLB_MWrErr(2), PLB_MWrDAck => mb_plb_PLB_MWrDAck(2), PLB_MRdDBus => mb_plb_PLB_MRdDBus(128 to 191), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(8 to 11), PLB_MRdDAck => mb_plb_PLB_MRdDAck(2), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(2), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(2), M_request => mb_plb_M_request(2), M_priority => mb_plb_M_priority(4 to 5), M_buslock => mb_plb_M_busLock(2), M_RNW => mb_plb_M_RNW(2), M_BE => mb_plb_M_BE(16 to 23), M_MSize => mb_plb_M_MSize(4 to 5), M_size => mb_plb_M_size(8 to 11), M_type => mb_plb_M_type(6 to 8), M_lockErr => mb_plb_M_lockErr(2), M_abort => mb_plb_M_ABort(2), M_TAttribute => mb_plb_M_TAttribute(32 to 47), M_UABus => mb_plb_M_UABus(64 to 95), M_ABus => mb_plb_M_ABus(64 to 95), M_wrDBus => mb_plb_M_wrDBus(128 to 191), M_wrBurst => mb_plb_M_wrBurst(2), M_rdBurst => mb_plb_M_rdBurst(2), SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(2), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(2), PLB_wrPrim => mb_plb_PLB_wrPrim(2), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(2), Sl_SSize => mb_plb_Sl_SSize(4 to 5), Sl_wait => mb_plb_Sl_wait(2), Sl_rearbitrate => mb_plb_Sl_rearbitrate(2), Sl_wrDAck => mb_plb_Sl_wrDAck(2), Sl_wrComp => mb_plb_Sl_wrComp(2), Sl_wrBTerm => mb_plb_Sl_wrBTerm(2), Sl_rdDBus => mb_plb_Sl_rdDBus(128 to 191), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(8 to 11), Sl_rdDAck => mb_plb_Sl_rdDAck(2), Sl_rdComp => mb_plb_Sl_rdComp(2), Sl_rdBTerm => mb_plb_Sl_rdBTerm(2), Sl_MBusy => mb_plb_Sl_MBusy(12 to 17), Sl_MWrErr => mb_plb_Sl_MWrErr(12 to 17), Sl_MRdErr => mb_plb_Sl_MRdErr(12 to 17), Sl_MIRQ => mb_plb_Sl_MIRQ(12 to 17), REFCLK => PCIe_Diff_Clk, Bridge_Clk => open, RXN => pgassign3(0 to 0), RXP => pgassign4(0 to 0), TXN => pgassign5(0 to 0), TXP => pgassign6(0 to 0), IP2INTC_Irpt => PCIe_Bridge_IP2INTC_Irpt, MSI_request => net_gnd0 ); xps_central_dma_1 : system_xps_central_dma_1_wrapper port map ( SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(3), MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(3), SPLB_ABus => mb_plb_PLB_ABus, SPLB_BE => mb_plb_PLB_BE, SPLB_UABus => mb_plb_PLB_UABus, SPLB_PAValid => mb_plb_PLB_PAValid, SPLB_SAValid => mb_plb_PLB_SAValid, SPLB_rdPrim => mb_plb_PLB_rdPrim(3), SPLB_wrPrim => mb_plb_PLB_wrPrim(3), SPLB_masterID => mb_plb_PLB_masterID, SPLB_abort => mb_plb_PLB_abort, SPLB_busLock => mb_plb_PLB_busLock, SPLB_RNW => mb_plb_PLB_RNW, SPLB_MSize => mb_plb_PLB_MSize, SPLB_size => mb_plb_PLB_size, SPLB_type => mb_plb_PLB_type, SPLB_lockErr => mb_plb_PLB_lockErr, SPLB_wrDBus => mb_plb_PLB_wrDBus, SPLB_wrBurst => mb_plb_PLB_wrBurst, SPLB_rdBurst => mb_plb_PLB_rdBurst, SPLB_wrPendReq => mb_plb_PLB_wrPendReq, SPLB_rdPendReq => mb_plb_PLB_rdPendReq, SPLB_wrPendPri => mb_plb_PLB_wrPendPri, SPLB_rdPendPri => mb_plb_PLB_rdPendPri, SPLB_reqPri => mb_plb_PLB_reqPri, SPLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(3), Sl_SSize => mb_plb_Sl_SSize(6 to 7), Sl_wait => mb_plb_Sl_wait(3), Sl_rearbitrate => mb_plb_Sl_rearbitrate(3), Sl_wrDAck => mb_plb_Sl_wrDAck(3), Sl_wrComp => mb_plb_Sl_wrComp(3), Sl_wrBTerm => mb_plb_Sl_wrBTerm(3), Sl_rdDBus => mb_plb_Sl_rdDBus(192 to 255), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(12 to 15), Sl_rdDAck => mb_plb_Sl_rdDAck(3), Sl_rdComp => mb_plb_Sl_rdComp(3), Sl_rdBTerm => mb_plb_Sl_rdBTerm(3), Sl_MBusy => mb_plb_Sl_MBusy(18 to 23), Sl_MWrErr => mb_plb_Sl_MWrErr(18 to 23), Sl_MRdErr => mb_plb_Sl_MRdErr(18 to 23), Sl_MIRQ => mb_plb_Sl_MIRQ(18 to 23), IP2INTC_Irpt => xps_central_dma_1_IP2INTC_Irpt, MPLB_MAddrAck => mb_plb_PLB_MAddrAck(3), MPLB_MSSize => mb_plb_PLB_MSSize(6 to 7), MPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(3), MPLB_MTimeout => mb_plb_PLB_MTimeout(3), MPLB_MBusy => mb_plb_PLB_MBusy(3), MPLB_MRdErr => mb_plb_PLB_MRdErr(3), MPLB_MWrErr => mb_plb_PLB_MWrErr(3), MPLB_MIRQ => mb_plb_PLB_MIRQ(3), MPLB_MRdDBus => mb_plb_PLB_MRdDBus(192 to 255), MPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(12 to 15), MPLB_MRdDAck => mb_plb_PLB_MRdDAck(3), MPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(3), MPLB_MWrDAck => mb_plb_PLB_MWrDAck(3), MPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(3), M_request => mb_plb_M_request(3), M_priority => mb_plb_M_priority(6 to 7), M_busLock => mb_plb_M_busLock(3), M_RNW => mb_plb_M_RNW(3), M_BE => mb_plb_M_BE(24 to 31), M_MSize => mb_plb_M_MSize(6 to 7), M_size => mb_plb_M_size(12 to 15), M_type => mb_plb_M_type(9 to 11), M_TAttribute => mb_plb_M_TAttribute(48 to 63), M_lockErr => mb_plb_M_lockErr(3), M_abort => mb_plb_M_ABort(3), M_UABus => mb_plb_M_UABus(96 to 127), M_ABus => mb_plb_M_ABus(96 to 127), M_wrDBus => mb_plb_M_wrDBus(192 to 255), M_wrBurst => mb_plb_M_wrBurst(3), M_rdBurst => mb_plb_M_rdBurst(3) ); clock_generator_0 : system_clock_generator_0_wrapper port map ( CLKIN => CLK_S, CLKOUT0 => clk_125_0000MHz90PLL0, CLKOUT1 => clk_125_0000MHzPLL0, CLKOUT2 => clk_200_0000MHz, CLKOUT3 => clk_62_5000MHzPLL0, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, CLKOUT7 => open, CLKOUT8 => open, CLKOUT9 => open, CLKOUT10 => open, CLKOUT11 => open, CLKOUT12 => open, CLKOUT13 => open, CLKOUT14 => open, CLKOUT15 => open, CLKFBIN => SRAM_CLK_FB_s, CLKFBOUT => SRAM_CLK_OUT_s, PSCLK => net_gnd0, PSEN => net_gnd0, PSINCDEC => net_gnd0, PSDONE => open, RST => sys_rst_s, LOCKED => Dcm_all_locked ); mdm_0 : system_mdm_0_wrapper port map ( Interrupt => open, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => net_gnd0, S_AXI_ARESETN => net_gnd0, S_AXI_AWADDR => net_gnd32(0 to 31), S_AXI_AWVALID => net_gnd0, S_AXI_AWREADY => open, S_AXI_WDATA => net_gnd32(0 to 31), S_AXI_WSTRB => net_gnd4(0 to 3), S_AXI_WVALID => net_gnd0, S_AXI_WREADY => open, S_AXI_BRESP => open, S_AXI_BVALID => open, S_AXI_BREADY => net_gnd0, S_AXI_ARADDR => net_gnd32(0 to 31), S_AXI_ARVALID => net_gnd0, S_AXI_ARREADY => open, S_AXI_RDATA => open, S_AXI_RRESP => open, S_AXI_RVALID => open, S_AXI_RREADY => net_gnd0, SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(4), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(4), PLB_wrPrim => mb_plb_PLB_wrPrim(4), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(4), Sl_SSize => mb_plb_Sl_SSize(8 to 9), Sl_wait => mb_plb_Sl_wait(4), Sl_rearbitrate => mb_plb_Sl_rearbitrate(4), Sl_wrDAck => mb_plb_Sl_wrDAck(4), Sl_wrComp => mb_plb_Sl_wrComp(4), Sl_wrBTerm => mb_plb_Sl_wrBTerm(4), Sl_rdDBus => mb_plb_Sl_rdDBus(256 to 319), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(16 to 19), Sl_rdDAck => mb_plb_Sl_rdDAck(4), Sl_rdComp => mb_plb_Sl_rdComp(4), Sl_rdBTerm => mb_plb_Sl_rdBTerm(4), Sl_MBusy => mb_plb_Sl_MBusy(24 to 29), Sl_MWrErr => mb_plb_Sl_MWrErr(24 to 29), Sl_MRdErr => mb_plb_Sl_MRdErr(24 to 29), Sl_MIRQ => mb_plb_Sl_MIRQ(24 to 29), Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk, Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI, Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO, Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En, Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture, Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift, Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update, Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst, Dbg_Clk_1 => open, Dbg_TDI_1 => open, Dbg_TDO_1 => net_gnd0, Dbg_Reg_En_1 => open, Dbg_Capture_1 => open, Dbg_Shift_1 => open, Dbg_Update_1 => open, Dbg_Rst_1 => open, Dbg_Clk_2 => open, Dbg_TDI_2 => open, Dbg_TDO_2 => net_gnd0, Dbg_Reg_En_2 => open, Dbg_Capture_2 => open, Dbg_Shift_2 => open, Dbg_Update_2 => open, Dbg_Rst_2 => open, Dbg_Clk_3 => open, Dbg_TDI_3 => open, Dbg_TDO_3 => net_gnd0, Dbg_Reg_En_3 => open, Dbg_Capture_3 => open, Dbg_Shift_3 => open, Dbg_Update_3 => open, Dbg_Rst_3 => open, Dbg_Clk_4 => open, Dbg_TDI_4 => open, Dbg_TDO_4 => net_gnd0, Dbg_Reg_En_4 => open, Dbg_Capture_4 => open, Dbg_Shift_4 => open, Dbg_Update_4 => open, Dbg_Rst_4 => open, Dbg_Clk_5 => open, Dbg_TDI_5 => open, Dbg_TDO_5 => net_gnd0, Dbg_Reg_En_5 => open, Dbg_Capture_5 => open, Dbg_Shift_5 => open, Dbg_Update_5 => open, Dbg_Rst_5 => open, Dbg_Clk_6 => open, Dbg_TDI_6 => open, Dbg_TDO_6 => net_gnd0, Dbg_Reg_En_6 => open, Dbg_Capture_6 => open, Dbg_Shift_6 => open, Dbg_Update_6 => open, Dbg_Rst_6 => open, Dbg_Clk_7 => open, Dbg_TDI_7 => open, Dbg_TDO_7 => net_gnd0, Dbg_Reg_En_7 => open, Dbg_Capture_7 => open, Dbg_Shift_7 => open, Dbg_Update_7 => open, Dbg_Rst_7 => open, Dbg_Clk_8 => open, Dbg_TDI_8 => open, Dbg_TDO_8 => net_gnd0, Dbg_Reg_En_8 => open, Dbg_Capture_8 => open, Dbg_Shift_8 => open, Dbg_Update_8 => open, Dbg_Rst_8 => open, Dbg_Clk_9 => open, Dbg_TDI_9 => open, Dbg_TDO_9 => net_gnd0, Dbg_Reg_En_9 => open, Dbg_Capture_9 => open, Dbg_Shift_9 => open, Dbg_Update_9 => open, Dbg_Rst_9 => open, Dbg_Clk_10 => open, Dbg_TDI_10 => open, Dbg_TDO_10 => net_gnd0, Dbg_Reg_En_10 => open, Dbg_Capture_10 => open, Dbg_Shift_10 => open, Dbg_Update_10 => open, Dbg_Rst_10 => open, Dbg_Clk_11 => open, Dbg_TDI_11 => open, Dbg_TDO_11 => net_gnd0, Dbg_Reg_En_11 => open, Dbg_Capture_11 => open, Dbg_Shift_11 => open, Dbg_Update_11 => open, Dbg_Rst_11 => open, Dbg_Clk_12 => open, Dbg_TDI_12 => open, Dbg_TDO_12 => net_gnd0, Dbg_Reg_En_12 => open, Dbg_Capture_12 => open, Dbg_Shift_12 => open, Dbg_Update_12 => open, Dbg_Rst_12 => open, Dbg_Clk_13 => open, Dbg_TDI_13 => open, Dbg_TDO_13 => net_gnd0, Dbg_Reg_En_13 => open, Dbg_Capture_13 => open, Dbg_Shift_13 => open, Dbg_Update_13 => open, Dbg_Rst_13 => open, Dbg_Clk_14 => open, Dbg_TDI_14 => open, Dbg_TDO_14 => net_gnd0, Dbg_Reg_En_14 => open, Dbg_Capture_14 => open, Dbg_Shift_14 => open, Dbg_Update_14 => open, Dbg_Rst_14 => open, Dbg_Clk_15 => open, Dbg_TDI_15 => open, Dbg_TDO_15 => net_gnd0, Dbg_Reg_En_15 => open, Dbg_Capture_15 => open, Dbg_Shift_15 => open, Dbg_Update_15 => open, Dbg_Rst_15 => open, Dbg_Clk_16 => open, Dbg_TDI_16 => open, Dbg_TDO_16 => net_gnd0, Dbg_Reg_En_16 => open, Dbg_Capture_16 => open, Dbg_Shift_16 => open, Dbg_Update_16 => open, Dbg_Rst_16 => open, Dbg_Clk_17 => open, Dbg_TDI_17 => open, Dbg_TDO_17 => net_gnd0, Dbg_Reg_En_17 => open, Dbg_Capture_17 => open, Dbg_Shift_17 => open, Dbg_Update_17 => open, Dbg_Rst_17 => open, Dbg_Clk_18 => open, Dbg_TDI_18 => open, Dbg_TDO_18 => net_gnd0, Dbg_Reg_En_18 => open, Dbg_Capture_18 => open, Dbg_Shift_18 => open, Dbg_Update_18 => open, Dbg_Rst_18 => open, Dbg_Clk_19 => open, Dbg_TDI_19 => open, Dbg_TDO_19 => net_gnd0, Dbg_Reg_En_19 => open, Dbg_Capture_19 => open, Dbg_Shift_19 => open, Dbg_Update_19 => open, Dbg_Rst_19 => open, Dbg_Clk_20 => open, Dbg_TDI_20 => open, Dbg_TDO_20 => net_gnd0, Dbg_Reg_En_20 => open, Dbg_Capture_20 => open, Dbg_Shift_20 => open, Dbg_Update_20 => open, Dbg_Rst_20 => open, Dbg_Clk_21 => open, Dbg_TDI_21 => open, Dbg_TDO_21 => net_gnd0, Dbg_Reg_En_21 => open, Dbg_Capture_21 => open, Dbg_Shift_21 => open, Dbg_Update_21 => open, Dbg_Rst_21 => open, Dbg_Clk_22 => open, Dbg_TDI_22 => open, Dbg_TDO_22 => net_gnd0, Dbg_Reg_En_22 => open, Dbg_Capture_22 => open, Dbg_Shift_22 => open, Dbg_Update_22 => open, Dbg_Rst_22 => open, Dbg_Clk_23 => open, Dbg_TDI_23 => open, Dbg_TDO_23 => net_gnd0, Dbg_Reg_En_23 => open, Dbg_Capture_23 => open, Dbg_Shift_23 => open, Dbg_Update_23 => open, Dbg_Rst_23 => open, Dbg_Clk_24 => open, Dbg_TDI_24 => open, Dbg_TDO_24 => net_gnd0, Dbg_Reg_En_24 => open, Dbg_Capture_24 => open, Dbg_Shift_24 => open, Dbg_Update_24 => open, Dbg_Rst_24 => open, Dbg_Clk_25 => open, Dbg_TDI_25 => open, Dbg_TDO_25 => net_gnd0, Dbg_Reg_En_25 => open, Dbg_Capture_25 => open, Dbg_Shift_25 => open, Dbg_Update_25 => open, Dbg_Rst_25 => open, Dbg_Clk_26 => open, Dbg_TDI_26 => open, Dbg_TDO_26 => net_gnd0, Dbg_Reg_En_26 => open, Dbg_Capture_26 => open, Dbg_Shift_26 => open, Dbg_Update_26 => open, Dbg_Rst_26 => open, Dbg_Clk_27 => open, Dbg_TDI_27 => open, Dbg_TDO_27 => net_gnd0, Dbg_Reg_En_27 => open, Dbg_Capture_27 => open, Dbg_Shift_27 => open, Dbg_Update_27 => open, Dbg_Rst_27 => open, Dbg_Clk_28 => open, Dbg_TDI_28 => open, Dbg_TDO_28 => net_gnd0, Dbg_Reg_En_28 => open, Dbg_Capture_28 => open, Dbg_Shift_28 => open, Dbg_Update_28 => open, Dbg_Rst_28 => open, Dbg_Clk_29 => open, Dbg_TDI_29 => open, Dbg_TDO_29 => net_gnd0, Dbg_Reg_En_29 => open, Dbg_Capture_29 => open, Dbg_Shift_29 => open, Dbg_Update_29 => open, Dbg_Rst_29 => open, Dbg_Clk_30 => open, Dbg_TDI_30 => open, Dbg_TDO_30 => net_gnd0, Dbg_Reg_En_30 => open, Dbg_Capture_30 => open, Dbg_Shift_30 => open, Dbg_Update_30 => open, Dbg_Rst_30 => open, Dbg_Clk_31 => open, Dbg_TDI_31 => open, Dbg_TDO_31 => net_gnd0, Dbg_Reg_En_31 => open, Dbg_Capture_31 => open, Dbg_Shift_31 => open, Dbg_Update_31 => open, Dbg_Rst_31 => open, bscan_tdi => open, bscan_reset => open, bscan_shift => open, bscan_update => open, bscan_capture => open, bscan_sel1 => open, bscan_drck1 => open, bscan_tdo1 => net_gnd0, bscan_ext_tdi => net_gnd0, bscan_ext_reset => net_gnd0, bscan_ext_shift => net_gnd0, bscan_ext_update => net_gnd0, bscan_ext_capture => net_gnd0, bscan_ext_sel => net_gnd0, bscan_ext_drck => net_gnd0, bscan_ext_tdo => open, Ext_JTAG_DRCK => open, Ext_JTAG_RESET => open, Ext_JTAG_SEL => open, Ext_JTAG_CAPTURE => open, Ext_JTAG_SHIFT => open, Ext_JTAG_UPDATE => open, Ext_JTAG_TDI => open, Ext_JTAG_TDO => net_gnd0 ); proc_sys_reset_0 : system_proc_sys_reset_0_wrapper port map ( Slowest_sync_clk => clk_125_0000MHzPLL0, Ext_Reset_In => sys_rst_s, Aux_Reset_In => net_gnd0, MB_Debug_Sys_Rst => Debug_SYS_Rst, Core_Reset_Req_0 => net_gnd0, Chip_Reset_Req_0 => net_gnd0, System_Reset_Req_0 => net_gnd0, Core_Reset_Req_1 => net_gnd0, Chip_Reset_Req_1 => net_gnd0, System_Reset_Req_1 => net_gnd0, Dcm_locked => Dcm_all_locked, RstcPPCresetcore_0 => open, RstcPPCresetchip_0 => open, RstcPPCresetsys_0 => open, RstcPPCresetcore_1 => open, RstcPPCresetchip_1 => open, RstcPPCresetsys_1 => open, MB_Reset => mb_reset, Bus_Struct_Reset => sys_bus_reset(0 to 0), Peripheral_Reset => sys_periph_reset(0 to 0), Interconnect_aresetn => open, Peripheral_aresetn => proc_sys_reset_0_Peripheral_aresetn(0 to 0) ); xps_intc_0 : system_xps_intc_0_wrapper port map ( SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(5), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(5), PLB_wrPrim => mb_plb_PLB_wrPrim(5), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(5), Sl_SSize => mb_plb_Sl_SSize(10 to 11), Sl_wait => mb_plb_Sl_wait(5), Sl_rearbitrate => mb_plb_Sl_rearbitrate(5), Sl_wrDAck => mb_plb_Sl_wrDAck(5), Sl_wrComp => mb_plb_Sl_wrComp(5), Sl_rdDBus => mb_plb_Sl_rdDBus(320 to 383), Sl_rdDAck => mb_plb_Sl_rdDAck(5), Sl_rdComp => mb_plb_Sl_rdComp(5), Sl_MBusy => mb_plb_Sl_MBusy(30 to 35), Sl_MWrErr => mb_plb_Sl_MWrErr(30 to 35), Sl_MRdErr => mb_plb_Sl_MRdErr(30 to 35), Sl_wrBTerm => mb_plb_Sl_wrBTerm(5), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(20 to 23), Sl_rdBTerm => mb_plb_Sl_rdBTerm(5), Sl_MIRQ => mb_plb_Sl_MIRQ(30 to 35), Intr => pgassign10, Irq => microblaze_0_Interrupt ); nfa_accept_samples_generic_hw_top_0 : system_nfa_accept_samples_generic_hw_top_0_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(0), indices_M_request => ac0_plb_M_request(0), indices_M_priority => ac0_plb_M_priority(0 to 1), indices_M_busLock => ac0_plb_M_busLock(0), indices_M_RNW => ac0_plb_M_RNW(0), indices_M_BE => ac0_plb_M_BE(0 to 7), indices_M_MSize => ac0_plb_M_MSize(0 to 1), indices_M_size => ac0_plb_M_size(0 to 3), indices_M_type => ac0_plb_M_type(0 to 2), indices_M_TAttribute => ac0_plb_M_TAttribute(0 to 15), indices_M_lockErr => ac0_plb_M_lockErr(0), indices_M_abort => ac0_plb_M_abort(0), indices_M_UABus => ac0_plb_M_UABus(0 to 31), indices_M_ABus => ac0_plb_M_ABus(0 to 31), indices_M_wrDBus => ac0_plb_M_wrDBus(0 to 63), indices_M_wrBurst => ac0_plb_M_wrBurst(0), indices_M_rdBurst => ac0_plb_M_rdBurst(0), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(0), indices_PLB_MSSize => ac0_plb_PLB_MSSize(0 to 1), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(0), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(0), indices_PLB_MBusy => ac0_plb_PLB_MBusy(0), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(0), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(0), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(0), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(0 to 63), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(0 to 3), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(0), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(0), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(0), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(0), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(1), nfa_finals_buckets_M_request => ac0_plb_M_request(1), nfa_finals_buckets_M_priority => ac0_plb_M_priority(2 to 3), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(1), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(1), nfa_finals_buckets_M_BE => ac0_plb_M_BE(8 to 15), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(2 to 3), nfa_finals_buckets_M_size => ac0_plb_M_size(4 to 7), nfa_finals_buckets_M_type => ac0_plb_M_type(3 to 5), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(16 to 31), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(1), nfa_finals_buckets_M_abort => ac0_plb_M_abort(1), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(32 to 63), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(32 to 63), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(64 to 127), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(1), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(1), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(1), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(2 to 3), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(1), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(1), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(1), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(1), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(1), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(1), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(64 to 127), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(4 to 7), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(1), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(1), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(1), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(1), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(2), nfa_forward_buckets_M_request => ac0_plb_M_request(2), nfa_forward_buckets_M_priority => ac0_plb_M_priority(4 to 5), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(2), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(2), nfa_forward_buckets_M_BE => ac0_plb_M_BE(16 to 23), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(4 to 5), nfa_forward_buckets_M_size => ac0_plb_M_size(8 to 11), nfa_forward_buckets_M_type => ac0_plb_M_type(6 to 8), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(32 to 47), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(2), nfa_forward_buckets_M_abort => ac0_plb_M_abort(2), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(64 to 95), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(64 to 95), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(128 to 191), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(2), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(2), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(2), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(4 to 5), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(2), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(2), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(2), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(2), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(2), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(2), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(128 to 191), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(8 to 11), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(2), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(2), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(2), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(2), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(3), nfa_initials_buckets_M_request => ac0_plb_M_request(3), nfa_initials_buckets_M_priority => ac0_plb_M_priority(6 to 7), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(3), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(3), nfa_initials_buckets_M_BE => ac0_plb_M_BE(24 to 31), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(6 to 7), nfa_initials_buckets_M_size => ac0_plb_M_size(12 to 15), nfa_initials_buckets_M_type => ac0_plb_M_type(9 to 11), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(48 to 63), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(3), nfa_initials_buckets_M_abort => ac0_plb_M_abort(3), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(96 to 127), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(96 to 127), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(192 to 255), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(3), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(3), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(3), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(6 to 7), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(3), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(3), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(3), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(3), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(3), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(3), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(192 to 255), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(12 to 15), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(3), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(3), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(3), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(3), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(4), sample_buffer_M_request => ac0_plb_M_request(4), sample_buffer_M_priority => ac0_plb_M_priority(8 to 9), sample_buffer_M_busLock => ac0_plb_M_busLock(4), sample_buffer_M_RNW => ac0_plb_M_RNW(4), sample_buffer_M_BE => ac0_plb_M_BE(32 to 39), sample_buffer_M_MSize => ac0_plb_M_MSize(8 to 9), sample_buffer_M_size => ac0_plb_M_size(16 to 19), sample_buffer_M_type => ac0_plb_M_type(12 to 14), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(64 to 79), sample_buffer_M_lockErr => ac0_plb_M_lockErr(4), sample_buffer_M_abort => ac0_plb_M_abort(4), sample_buffer_M_UABus => ac0_plb_M_UABus(128 to 159), sample_buffer_M_ABus => ac0_plb_M_ABus(128 to 159), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(256 to 319), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(4), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(4), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(4), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(8 to 9), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(4), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(4), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(4), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(4), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(4), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(4), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(256 to 319), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(16 to 19), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(4), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(4), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(4), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(4), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(6), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(6), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(6), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(6), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(12 to 13), splb_slv0_Sl_wait => mb_plb_Sl_wait(6), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(6), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(6), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(6), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(6), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(384 to 447), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(24 to 27), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(6), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(6), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(6), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(36 to 41), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(36 to 41), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(36 to 41), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(36 to 41) ); nfa_accept_samples_generic_hw_top_1 : system_nfa_accept_samples_generic_hw_top_1_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(5), indices_M_request => ac0_plb_M_request(5), indices_M_priority => ac0_plb_M_priority(10 to 11), indices_M_busLock => ac0_plb_M_busLock(5), indices_M_RNW => ac0_plb_M_RNW(5), indices_M_BE => ac0_plb_M_BE(40 to 47), indices_M_MSize => ac0_plb_M_MSize(10 to 11), indices_M_size => ac0_plb_M_size(20 to 23), indices_M_type => ac0_plb_M_type(15 to 17), indices_M_TAttribute => ac0_plb_M_TAttribute(80 to 95), indices_M_lockErr => ac0_plb_M_lockErr(5), indices_M_abort => ac0_plb_M_abort(5), indices_M_UABus => ac0_plb_M_UABus(160 to 191), indices_M_ABus => ac0_plb_M_ABus(160 to 191), indices_M_wrDBus => ac0_plb_M_wrDBus(320 to 383), indices_M_wrBurst => ac0_plb_M_wrBurst(5), indices_M_rdBurst => ac0_plb_M_rdBurst(5), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(5), indices_PLB_MSSize => ac0_plb_PLB_MSSize(10 to 11), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(5), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(5), indices_PLB_MBusy => ac0_plb_PLB_MBusy(5), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(5), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(5), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(5), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(320 to 383), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(20 to 23), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(5), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(5), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(5), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(5), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(6), nfa_finals_buckets_M_request => ac0_plb_M_request(6), nfa_finals_buckets_M_priority => ac0_plb_M_priority(12 to 13), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(6), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(6), nfa_finals_buckets_M_BE => ac0_plb_M_BE(48 to 55), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(12 to 13), nfa_finals_buckets_M_size => ac0_plb_M_size(24 to 27), nfa_finals_buckets_M_type => ac0_plb_M_type(18 to 20), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(96 to 111), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(6), nfa_finals_buckets_M_abort => ac0_plb_M_abort(6), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(192 to 223), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(192 to 223), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(384 to 447), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(6), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(6), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(6), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(12 to 13), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(6), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(6), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(6), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(6), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(6), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(6), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(384 to 447), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(24 to 27), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(6), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(6), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(6), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(6), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(7), nfa_forward_buckets_M_request => ac0_plb_M_request(7), nfa_forward_buckets_M_priority => ac0_plb_M_priority(14 to 15), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(7), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(7), nfa_forward_buckets_M_BE => ac0_plb_M_BE(56 to 63), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(14 to 15), nfa_forward_buckets_M_size => ac0_plb_M_size(28 to 31), nfa_forward_buckets_M_type => ac0_plb_M_type(21 to 23), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(112 to 127), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(7), nfa_forward_buckets_M_abort => ac0_plb_M_abort(7), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(224 to 255), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(224 to 255), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(448 to 511), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(7), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(7), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(7), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(14 to 15), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(7), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(7), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(7), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(7), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(7), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(7), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(448 to 511), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(28 to 31), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(7), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(7), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(7), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(7), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(8), nfa_initials_buckets_M_request => ac0_plb_M_request(8), nfa_initials_buckets_M_priority => ac0_plb_M_priority(16 to 17), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(8), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(8), nfa_initials_buckets_M_BE => ac0_plb_M_BE(64 to 71), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(16 to 17), nfa_initials_buckets_M_size => ac0_plb_M_size(32 to 35), nfa_initials_buckets_M_type => ac0_plb_M_type(24 to 26), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(128 to 143), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(8), nfa_initials_buckets_M_abort => ac0_plb_M_abort(8), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(256 to 287), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(256 to 287), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(512 to 575), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(8), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(8), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(8), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(16 to 17), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(8), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(8), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(8), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(8), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(8), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(8), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(512 to 575), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(32 to 35), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(8), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(8), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(8), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(8), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(9), sample_buffer_M_request => ac0_plb_M_request(9), sample_buffer_M_priority => ac0_plb_M_priority(18 to 19), sample_buffer_M_busLock => ac0_plb_M_busLock(9), sample_buffer_M_RNW => ac0_plb_M_RNW(9), sample_buffer_M_BE => ac0_plb_M_BE(72 to 79), sample_buffer_M_MSize => ac0_plb_M_MSize(18 to 19), sample_buffer_M_size => ac0_plb_M_size(36 to 39), sample_buffer_M_type => ac0_plb_M_type(27 to 29), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(144 to 159), sample_buffer_M_lockErr => ac0_plb_M_lockErr(9), sample_buffer_M_abort => ac0_plb_M_abort(9), sample_buffer_M_UABus => ac0_plb_M_UABus(288 to 319), sample_buffer_M_ABus => ac0_plb_M_ABus(288 to 319), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(576 to 639), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(9), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(9), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(9), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(18 to 19), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(9), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(9), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(9), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(9), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(9), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(9), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(576 to 639), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(36 to 39), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(9), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(9), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(9), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(9), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(7), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(7), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(7), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(7), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(14 to 15), splb_slv0_Sl_wait => mb_plb_Sl_wait(7), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(7), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(7), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(7), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(7), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(448 to 511), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(28 to 31), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(7), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(7), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(7), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(42 to 47), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(42 to 47), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(42 to 47), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(42 to 47) ); nfa_accept_samples_generic_hw_top_2 : system_nfa_accept_samples_generic_hw_top_2_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(10), indices_M_request => ac0_plb_M_request(10), indices_M_priority => ac0_plb_M_priority(20 to 21), indices_M_busLock => ac0_plb_M_busLock(10), indices_M_RNW => ac0_plb_M_RNW(10), indices_M_BE => ac0_plb_M_BE(80 to 87), indices_M_MSize => ac0_plb_M_MSize(20 to 21), indices_M_size => ac0_plb_M_size(40 to 43), indices_M_type => ac0_plb_M_type(30 to 32), indices_M_TAttribute => ac0_plb_M_TAttribute(160 to 175), indices_M_lockErr => ac0_plb_M_lockErr(10), indices_M_abort => ac0_plb_M_abort(10), indices_M_UABus => ac0_plb_M_UABus(320 to 351), indices_M_ABus => ac0_plb_M_ABus(320 to 351), indices_M_wrDBus => ac0_plb_M_wrDBus(640 to 703), indices_M_wrBurst => ac0_plb_M_wrBurst(10), indices_M_rdBurst => ac0_plb_M_rdBurst(10), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(10), indices_PLB_MSSize => ac0_plb_PLB_MSSize(20 to 21), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(10), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(10), indices_PLB_MBusy => ac0_plb_PLB_MBusy(10), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(10), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(10), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(10), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(640 to 703), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(40 to 43), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(10), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(10), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(10), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(10), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(11), nfa_finals_buckets_M_request => ac0_plb_M_request(11), nfa_finals_buckets_M_priority => ac0_plb_M_priority(22 to 23), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(11), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(11), nfa_finals_buckets_M_BE => ac0_plb_M_BE(88 to 95), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(22 to 23), nfa_finals_buckets_M_size => ac0_plb_M_size(44 to 47), nfa_finals_buckets_M_type => ac0_plb_M_type(33 to 35), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(176 to 191), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(11), nfa_finals_buckets_M_abort => ac0_plb_M_abort(11), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(352 to 383), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(352 to 383), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(704 to 767), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(11), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(11), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(11), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(22 to 23), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(11), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(11), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(11), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(11), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(11), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(11), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(704 to 767), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(44 to 47), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(11), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(11), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(11), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(11), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(12), nfa_forward_buckets_M_request => ac0_plb_M_request(12), nfa_forward_buckets_M_priority => ac0_plb_M_priority(24 to 25), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(12), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(12), nfa_forward_buckets_M_BE => ac0_plb_M_BE(96 to 103), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(24 to 25), nfa_forward_buckets_M_size => ac0_plb_M_size(48 to 51), nfa_forward_buckets_M_type => ac0_plb_M_type(36 to 38), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(192 to 207), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(12), nfa_forward_buckets_M_abort => ac0_plb_M_abort(12), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(384 to 415), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(384 to 415), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(768 to 831), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(12), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(12), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(12), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(24 to 25), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(12), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(12), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(12), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(12), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(12), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(12), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(768 to 831), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(48 to 51), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(12), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(12), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(12), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(12), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(13), nfa_initials_buckets_M_request => ac0_plb_M_request(13), nfa_initials_buckets_M_priority => ac0_plb_M_priority(26 to 27), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(13), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(13), nfa_initials_buckets_M_BE => ac0_plb_M_BE(104 to 111), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(26 to 27), nfa_initials_buckets_M_size => ac0_plb_M_size(52 to 55), nfa_initials_buckets_M_type => ac0_plb_M_type(39 to 41), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(208 to 223), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(13), nfa_initials_buckets_M_abort => ac0_plb_M_abort(13), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(416 to 447), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(416 to 447), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(832 to 895), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(13), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(13), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(13), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(26 to 27), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(13), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(13), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(13), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(13), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(13), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(13), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(832 to 895), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(52 to 55), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(13), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(13), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(13), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(13), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(14), sample_buffer_M_request => ac0_plb_M_request(14), sample_buffer_M_priority => ac0_plb_M_priority(28 to 29), sample_buffer_M_busLock => ac0_plb_M_busLock(14), sample_buffer_M_RNW => ac0_plb_M_RNW(14), sample_buffer_M_BE => ac0_plb_M_BE(112 to 119), sample_buffer_M_MSize => ac0_plb_M_MSize(28 to 29), sample_buffer_M_size => ac0_plb_M_size(56 to 59), sample_buffer_M_type => ac0_plb_M_type(42 to 44), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(224 to 239), sample_buffer_M_lockErr => ac0_plb_M_lockErr(14), sample_buffer_M_abort => ac0_plb_M_abort(14), sample_buffer_M_UABus => ac0_plb_M_UABus(448 to 479), sample_buffer_M_ABus => ac0_plb_M_ABus(448 to 479), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(896 to 959), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(14), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(14), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(14), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(28 to 29), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(14), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(14), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(14), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(14), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(14), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(14), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(896 to 959), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(56 to 59), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(14), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(14), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(14), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(14), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(8), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(8), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(8), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(8), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(16 to 17), splb_slv0_Sl_wait => mb_plb_Sl_wait(8), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(8), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(8), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(8), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(8), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(512 to 575), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(32 to 35), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(8), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(8), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(8), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(48 to 53), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(48 to 53), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(48 to 53), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(48 to 53) ); nfa_accept_samples_generic_hw_top_3 : system_nfa_accept_samples_generic_hw_top_3_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(0), indices_M_request => ac1_plb_M_request(0), indices_M_priority => ac1_plb_M_priority(0 to 1), indices_M_busLock => ac1_plb_M_busLock(0), indices_M_RNW => ac1_plb_M_RNW(0), indices_M_BE => ac1_plb_M_BE(0 to 7), indices_M_MSize => ac1_plb_M_MSize(0 to 1), indices_M_size => ac1_plb_M_size(0 to 3), indices_M_type => ac1_plb_M_type(0 to 2), indices_M_TAttribute => ac1_plb_M_TAttribute(0 to 15), indices_M_lockErr => ac1_plb_M_lockErr(0), indices_M_abort => ac1_plb_M_abort(0), indices_M_UABus => ac1_plb_M_UABus(0 to 31), indices_M_ABus => ac1_plb_M_ABus(0 to 31), indices_M_wrDBus => ac1_plb_M_wrDBus(0 to 63), indices_M_wrBurst => ac1_plb_M_wrBurst(0), indices_M_rdBurst => ac1_plb_M_rdBurst(0), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(0), indices_PLB_MSSize => ac1_plb_PLB_MSSize(0 to 1), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(0), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(0), indices_PLB_MBusy => ac1_plb_PLB_MBusy(0), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(0), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(0), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(0), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(0 to 63), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(0 to 3), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(0), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(0), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(0), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(0), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(1), nfa_finals_buckets_M_request => ac1_plb_M_request(1), nfa_finals_buckets_M_priority => ac1_plb_M_priority(2 to 3), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(1), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(1), nfa_finals_buckets_M_BE => ac1_plb_M_BE(8 to 15), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(2 to 3), nfa_finals_buckets_M_size => ac1_plb_M_size(4 to 7), nfa_finals_buckets_M_type => ac1_plb_M_type(3 to 5), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(16 to 31), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(1), nfa_finals_buckets_M_abort => ac1_plb_M_abort(1), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(32 to 63), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(32 to 63), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(64 to 127), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(1), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(1), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(1), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(2 to 3), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(1), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(1), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(1), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(1), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(1), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(1), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(64 to 127), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(4 to 7), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(1), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(1), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(1), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(1), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(2), nfa_forward_buckets_M_request => ac1_plb_M_request(2), nfa_forward_buckets_M_priority => ac1_plb_M_priority(4 to 5), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(2), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(2), nfa_forward_buckets_M_BE => ac1_plb_M_BE(16 to 23), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(4 to 5), nfa_forward_buckets_M_size => ac1_plb_M_size(8 to 11), nfa_forward_buckets_M_type => ac1_plb_M_type(6 to 8), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(32 to 47), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(2), nfa_forward_buckets_M_abort => ac1_plb_M_abort(2), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(64 to 95), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(64 to 95), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(128 to 191), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(2), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(2), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(2), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(4 to 5), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(2), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(2), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(2), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(2), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(2), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(2), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(128 to 191), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(8 to 11), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(2), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(2), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(2), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(2), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(3), nfa_initials_buckets_M_request => ac1_plb_M_request(3), nfa_initials_buckets_M_priority => ac1_plb_M_priority(6 to 7), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(3), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(3), nfa_initials_buckets_M_BE => ac1_plb_M_BE(24 to 31), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(6 to 7), nfa_initials_buckets_M_size => ac1_plb_M_size(12 to 15), nfa_initials_buckets_M_type => ac1_plb_M_type(9 to 11), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(48 to 63), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(3), nfa_initials_buckets_M_abort => ac1_plb_M_abort(3), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(96 to 127), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(96 to 127), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(192 to 255), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(3), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(3), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(3), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(6 to 7), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(3), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(3), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(3), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(3), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(3), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(3), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(192 to 255), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(12 to 15), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(3), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(3), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(3), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(3), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(4), sample_buffer_M_request => ac1_plb_M_request(4), sample_buffer_M_priority => ac1_plb_M_priority(8 to 9), sample_buffer_M_busLock => ac1_plb_M_busLock(4), sample_buffer_M_RNW => ac1_plb_M_RNW(4), sample_buffer_M_BE => ac1_plb_M_BE(32 to 39), sample_buffer_M_MSize => ac1_plb_M_MSize(8 to 9), sample_buffer_M_size => ac1_plb_M_size(16 to 19), sample_buffer_M_type => ac1_plb_M_type(12 to 14), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(64 to 79), sample_buffer_M_lockErr => ac1_plb_M_lockErr(4), sample_buffer_M_abort => ac1_plb_M_abort(4), sample_buffer_M_UABus => ac1_plb_M_UABus(128 to 159), sample_buffer_M_ABus => ac1_plb_M_ABus(128 to 159), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(256 to 319), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(4), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(4), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(4), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(8 to 9), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(4), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(4), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(4), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(4), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(4), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(4), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(256 to 319), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(16 to 19), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(4), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(4), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(4), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(4), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(9), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(9), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(9), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(9), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(18 to 19), splb_slv0_Sl_wait => mb_plb_Sl_wait(9), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(9), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(9), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(9), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(9), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(576 to 639), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(36 to 39), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(9), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(9), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(9), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(54 to 59), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(54 to 59), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(54 to 59), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(54 to 59) ); nfa_accept_samples_generic_hw_top_4 : system_nfa_accept_samples_generic_hw_top_4_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(5), indices_M_request => ac1_plb_M_request(5), indices_M_priority => ac1_plb_M_priority(10 to 11), indices_M_busLock => ac1_plb_M_busLock(5), indices_M_RNW => ac1_plb_M_RNW(5), indices_M_BE => ac1_plb_M_BE(40 to 47), indices_M_MSize => ac1_plb_M_MSize(10 to 11), indices_M_size => ac1_plb_M_size(20 to 23), indices_M_type => ac1_plb_M_type(15 to 17), indices_M_TAttribute => ac1_plb_M_TAttribute(80 to 95), indices_M_lockErr => ac1_plb_M_lockErr(5), indices_M_abort => ac1_plb_M_abort(5), indices_M_UABus => ac1_plb_M_UABus(160 to 191), indices_M_ABus => ac1_plb_M_ABus(160 to 191), indices_M_wrDBus => ac1_plb_M_wrDBus(320 to 383), indices_M_wrBurst => ac1_plb_M_wrBurst(5), indices_M_rdBurst => ac1_plb_M_rdBurst(5), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(5), indices_PLB_MSSize => ac1_plb_PLB_MSSize(10 to 11), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(5), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(5), indices_PLB_MBusy => ac1_plb_PLB_MBusy(5), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(5), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(5), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(5), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(320 to 383), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(20 to 23), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(5), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(5), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(5), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(5), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(6), nfa_finals_buckets_M_request => ac1_plb_M_request(6), nfa_finals_buckets_M_priority => ac1_plb_M_priority(12 to 13), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(6), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(6), nfa_finals_buckets_M_BE => ac1_plb_M_BE(48 to 55), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(12 to 13), nfa_finals_buckets_M_size => ac1_plb_M_size(24 to 27), nfa_finals_buckets_M_type => ac1_plb_M_type(18 to 20), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(96 to 111), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(6), nfa_finals_buckets_M_abort => ac1_plb_M_abort(6), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(192 to 223), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(192 to 223), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(384 to 447), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(6), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(6), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(6), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(12 to 13), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(6), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(6), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(6), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(6), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(6), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(6), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(384 to 447), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(24 to 27), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(6), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(6), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(6), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(6), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(7), nfa_forward_buckets_M_request => ac1_plb_M_request(7), nfa_forward_buckets_M_priority => ac1_plb_M_priority(14 to 15), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(7), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(7), nfa_forward_buckets_M_BE => ac1_plb_M_BE(56 to 63), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(14 to 15), nfa_forward_buckets_M_size => ac1_plb_M_size(28 to 31), nfa_forward_buckets_M_type => ac1_plb_M_type(21 to 23), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(112 to 127), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(7), nfa_forward_buckets_M_abort => ac1_plb_M_abort(7), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(224 to 255), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(224 to 255), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(448 to 511), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(7), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(7), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(7), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(14 to 15), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(7), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(7), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(7), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(7), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(7), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(7), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(448 to 511), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(28 to 31), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(7), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(7), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(7), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(7), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(8), nfa_initials_buckets_M_request => ac1_plb_M_request(8), nfa_initials_buckets_M_priority => ac1_plb_M_priority(16 to 17), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(8), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(8), nfa_initials_buckets_M_BE => ac1_plb_M_BE(64 to 71), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(16 to 17), nfa_initials_buckets_M_size => ac1_plb_M_size(32 to 35), nfa_initials_buckets_M_type => ac1_plb_M_type(24 to 26), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(128 to 143), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(8), nfa_initials_buckets_M_abort => ac1_plb_M_abort(8), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(256 to 287), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(256 to 287), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(512 to 575), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(8), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(8), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(8), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(16 to 17), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(8), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(8), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(8), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(8), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(8), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(8), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(512 to 575), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(32 to 35), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(8), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(8), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(8), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(8), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(9), sample_buffer_M_request => ac1_plb_M_request(9), sample_buffer_M_priority => ac1_plb_M_priority(18 to 19), sample_buffer_M_busLock => ac1_plb_M_busLock(9), sample_buffer_M_RNW => ac1_plb_M_RNW(9), sample_buffer_M_BE => ac1_plb_M_BE(72 to 79), sample_buffer_M_MSize => ac1_plb_M_MSize(18 to 19), sample_buffer_M_size => ac1_plb_M_size(36 to 39), sample_buffer_M_type => ac1_plb_M_type(27 to 29), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(144 to 159), sample_buffer_M_lockErr => ac1_plb_M_lockErr(9), sample_buffer_M_abort => ac1_plb_M_abort(9), sample_buffer_M_UABus => ac1_plb_M_UABus(288 to 319), sample_buffer_M_ABus => ac1_plb_M_ABus(288 to 319), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(576 to 639), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(9), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(9), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(9), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(18 to 19), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(9), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(9), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(9), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(9), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(9), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(9), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(576 to 639), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(36 to 39), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(9), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(9), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(9), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(9), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(10), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(10), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(10), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(10), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(20 to 21), splb_slv0_Sl_wait => mb_plb_Sl_wait(10), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(10), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(10), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(10), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(10), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(640 to 703), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(40 to 43), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(10), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(10), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(10), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(60 to 65), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(60 to 65), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(60 to 65), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(60 to 65) ); ac0_plb : system_ac0_plb_wrapper port map ( PLB_Clk => net_gnd0, SYS_Rst => net_gnd0, PLB_Rst => open, SPLB_Rst => ac0_plb_SPLB_Rst(0 to 0), MPLB_Rst => ac0_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => ac0_plb_M_ABus, M_UABus => ac0_plb_M_UABus, M_BE => ac0_plb_M_BE, M_RNW => ac0_plb_M_RNW, M_abort => ac0_plb_M_abort, M_busLock => ac0_plb_M_busLock, M_TAttribute => ac0_plb_M_TAttribute, M_lockErr => ac0_plb_M_lockErr, M_MSize => ac0_plb_M_MSize, M_priority => ac0_plb_M_priority, M_rdBurst => ac0_plb_M_rdBurst, M_request => ac0_plb_M_request, M_size => ac0_plb_M_size, M_type => ac0_plb_M_type, M_wrBurst => ac0_plb_M_wrBurst, M_wrDBus => ac0_plb_M_wrDBus, Sl_addrAck => ac0_plb_Sl_addrAck(0 to 0), Sl_MRdErr => ac0_plb_Sl_MRdErr, Sl_MWrErr => ac0_plb_Sl_MWrErr, Sl_MBusy => ac0_plb_Sl_MBusy, Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0 to 0), Sl_rdComp => ac0_plb_Sl_rdComp(0 to 0), Sl_rdDAck => ac0_plb_Sl_rdDAck(0 to 0), Sl_rdDBus => ac0_plb_Sl_rdDBus, Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr, Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0 to 0), Sl_SSize => ac0_plb_Sl_SSize, Sl_wait => ac0_plb_Sl_wait(0 to 0), Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0 to 0), Sl_wrComp => ac0_plb_Sl_wrComp(0 to 0), Sl_wrDAck => ac0_plb_Sl_wrDAck(0 to 0), Sl_MIRQ => ac0_plb_Sl_MIRQ, PLB_MIRQ => ac0_plb_PLB_MIRQ, PLB_ABus => ac0_plb_PLB_ABus, PLB_UABus => ac0_plb_PLB_UABus, PLB_BE => ac0_plb_PLB_BE, PLB_MAddrAck => ac0_plb_PLB_MAddrAck, PLB_MTimeout => ac0_plb_PLB_MTimeout, PLB_MBusy => ac0_plb_PLB_MBusy, PLB_MRdErr => ac0_plb_PLB_MRdErr, PLB_MWrErr => ac0_plb_PLB_MWrErr, PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm, PLB_MRdDAck => ac0_plb_PLB_MRdDAck, PLB_MRdDBus => ac0_plb_PLB_MRdDBus, PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr, PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate, PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm, PLB_MWrDAck => ac0_plb_PLB_MWrDAck, PLB_MSSize => ac0_plb_PLB_MSSize, PLB_PAValid => ac0_plb_PLB_PAValid, PLB_RNW => ac0_plb_PLB_RNW, PLB_SAValid => ac0_plb_PLB_SAValid, PLB_abort => ac0_plb_PLB_abort, PLB_busLock => ac0_plb_PLB_busLock, PLB_TAttribute => ac0_plb_PLB_TAttribute, PLB_lockErr => ac0_plb_PLB_lockErr, PLB_masterID => ac0_plb_PLB_masterID, PLB_MSize => ac0_plb_PLB_MSize, PLB_rdPendPri => ac0_plb_PLB_rdPendPri, PLB_wrPendPri => ac0_plb_PLB_wrPendPri, PLB_rdPendReq => ac0_plb_PLB_rdPendReq, PLB_wrPendReq => ac0_plb_PLB_wrPendReq, PLB_rdBurst => ac0_plb_PLB_rdBurst, PLB_rdPrim => ac0_plb_PLB_rdPrim(0 to 0), PLB_reqPri => ac0_plb_PLB_reqPri, PLB_size => ac0_plb_PLB_size, PLB_type => ac0_plb_PLB_type, PLB_wrBurst => ac0_plb_PLB_wrBurst, PLB_wrDBus => ac0_plb_PLB_wrDBus, PLB_wrPrim => ac0_plb_PLB_wrPrim(0 to 0), PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ac0_mb_bridge : system_ac0_mb_bridge_wrapper port map ( SPLB_Clk => net_gnd0, SPLB_Rst => ac0_plb_SPLB_Rst(0), IP2INTC_Irpt => open, PLB_ABus => ac0_plb_PLB_ABus, PLB_UABus => ac0_plb_PLB_UABus, PLB_PAValid => ac0_plb_PLB_PAValid, PLB_SAValid => ac0_plb_PLB_SAValid, PLB_rdPrim => ac0_plb_PLB_rdPrim(0), PLB_wrPrim => ac0_plb_PLB_wrPrim(0), PLB_masterID => ac0_plb_PLB_masterID, PLB_abort => ac0_plb_PLB_abort, PLB_busLock => ac0_plb_PLB_busLock, PLB_RNW => ac0_plb_PLB_RNW, PLB_BE => ac0_plb_PLB_BE, PLB_MSize => ac0_plb_PLB_MSize, PLB_size => ac0_plb_PLB_size, PLB_type => ac0_plb_PLB_type, PLB_lockErr => ac0_plb_PLB_lockErr, PLB_wrDBus => ac0_plb_PLB_wrDBus, PLB_wrBurst => ac0_plb_PLB_wrBurst, PLB_rdBurst => ac0_plb_PLB_rdBurst, PLB_wrPendReq => ac0_plb_PLB_wrPendReq, PLB_rdPendReq => ac0_plb_PLB_rdPendReq, PLB_wrPendPri => ac0_plb_PLB_wrPendPri, PLB_rdPendPri => ac0_plb_PLB_rdPendPri, PLB_reqPri => ac0_plb_PLB_reqPri, PLB_TAttribute => ac0_plb_PLB_TAttribute, Sl_addrAck => ac0_plb_Sl_addrAck(0), Sl_SSize => ac0_plb_Sl_SSize, Sl_wait => ac0_plb_Sl_wait(0), Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0), Sl_wrDAck => ac0_plb_Sl_wrDAck(0), Sl_wrComp => ac0_plb_Sl_wrComp(0), Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0), Sl_rdDBus => ac0_plb_Sl_rdDBus, Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr, Sl_rdDAck => ac0_plb_Sl_rdDAck(0), Sl_rdComp => ac0_plb_Sl_rdComp(0), Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0), Sl_MBusy => ac0_plb_Sl_MBusy, Sl_MWrErr => ac0_plb_Sl_MWrErr, Sl_MRdErr => ac0_plb_Sl_MRdErr, Sl_MIRQ => ac0_plb_Sl_MIRQ, MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(4), M_request => mb_plb_M_request(4), M_priority => mb_plb_M_priority(8 to 9), M_busLock => mb_plb_M_busLock(4), M_RNW => mb_plb_M_RNW(4), M_BE => mb_plb_M_BE(32 to 39), M_MSize => mb_plb_M_MSize(8 to 9), M_size => mb_plb_M_size(16 to 19), M_type => mb_plb_M_type(12 to 14), M_ABus => mb_plb_M_ABus(128 to 159), M_wrBurst => mb_plb_M_wrBurst(4), M_rdBurst => mb_plb_M_rdBurst(4), M_wrDBus => mb_plb_M_wrDBus(256 to 319), PLB_MAddrAck => mb_plb_PLB_MAddrAck(4), PLB_MSSize => mb_plb_PLB_MSSize(8 to 9), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(4), PLB_MTimeout => mb_plb_PLB_MTimeout(4), PLB_MRdErr => mb_plb_PLB_MRdErr(4), PLB_MWrErr => mb_plb_PLB_MWrErr(4), PLB_MRdDBus => mb_plb_PLB_MRdDBus(256 to 319), PLB_MRdDAck => mb_plb_PLB_MRdDAck(4), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(4), PLB_MWrDAck => mb_plb_PLB_MWrDAck(4), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(4), M_TAttribute => mb_plb_M_TAttribute(64 to 79), M_lockErr => mb_plb_M_lockErr(4), M_abort => mb_plb_M_ABort(4), M_UABus => mb_plb_M_UABus(128 to 159), PLB_MBusy => mb_plb_PLB_MBusy(4), PLB_MIRQ => mb_plb_PLB_MIRQ(4), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(16 to 19) ); ac1_plb : system_ac1_plb_wrapper port map ( PLB_Clk => net_gnd0, SYS_Rst => net_gnd0, PLB_Rst => open, SPLB_Rst => ac1_plb_SPLB_Rst(0 to 0), MPLB_Rst => ac1_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => ac1_plb_M_ABus, M_UABus => ac1_plb_M_UABus, M_BE => ac1_plb_M_BE, M_RNW => ac1_plb_M_RNW, M_abort => ac1_plb_M_abort, M_busLock => ac1_plb_M_busLock, M_TAttribute => ac1_plb_M_TAttribute, M_lockErr => ac1_plb_M_lockErr, M_MSize => ac1_plb_M_MSize, M_priority => ac1_plb_M_priority, M_rdBurst => ac1_plb_M_rdBurst, M_request => ac1_plb_M_request, M_size => ac1_plb_M_size, M_type => ac1_plb_M_type, M_wrBurst => ac1_plb_M_wrBurst, M_wrDBus => ac1_plb_M_wrDBus, Sl_addrAck => ac1_plb_Sl_addrAck(0 to 0), Sl_MRdErr => ac1_plb_Sl_MRdErr, Sl_MWrErr => ac1_plb_Sl_MWrErr, Sl_MBusy => ac1_plb_Sl_MBusy, Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0 to 0), Sl_rdComp => ac1_plb_Sl_rdComp(0 to 0), Sl_rdDAck => ac1_plb_Sl_rdDAck(0 to 0), Sl_rdDBus => ac1_plb_Sl_rdDBus, Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr, Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0 to 0), Sl_SSize => ac1_plb_Sl_SSize, Sl_wait => ac1_plb_Sl_wait(0 to 0), Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0 to 0), Sl_wrComp => ac1_plb_Sl_wrComp(0 to 0), Sl_wrDAck => ac1_plb_Sl_wrDAck(0 to 0), Sl_MIRQ => ac1_plb_Sl_MIRQ, PLB_MIRQ => ac1_plb_PLB_MIRQ, PLB_ABus => ac1_plb_PLB_ABus, PLB_UABus => ac1_plb_PLB_UABus, PLB_BE => ac1_plb_PLB_BE, PLB_MAddrAck => ac1_plb_PLB_MAddrAck, PLB_MTimeout => ac1_plb_PLB_MTimeout, PLB_MBusy => ac1_plb_PLB_MBusy, PLB_MRdErr => ac1_plb_PLB_MRdErr, PLB_MWrErr => ac1_plb_PLB_MWrErr, PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm, PLB_MRdDAck => ac1_plb_PLB_MRdDAck, PLB_MRdDBus => ac1_plb_PLB_MRdDBus, PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr, PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate, PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm, PLB_MWrDAck => ac1_plb_PLB_MWrDAck, PLB_MSSize => ac1_plb_PLB_MSSize, PLB_PAValid => ac1_plb_PLB_PAValid, PLB_RNW => ac1_plb_PLB_RNW, PLB_SAValid => ac1_plb_PLB_SAValid, PLB_abort => ac1_plb_PLB_abort, PLB_busLock => ac1_plb_PLB_busLock, PLB_TAttribute => ac1_plb_PLB_TAttribute, PLB_lockErr => ac1_plb_PLB_lockErr, PLB_masterID => ac1_plb_PLB_masterID, PLB_MSize => ac1_plb_PLB_MSize, PLB_rdPendPri => ac1_plb_PLB_rdPendPri, PLB_wrPendPri => ac1_plb_PLB_wrPendPri, PLB_rdPendReq => ac1_plb_PLB_rdPendReq, PLB_wrPendReq => ac1_plb_PLB_wrPendReq, PLB_rdBurst => ac1_plb_PLB_rdBurst, PLB_rdPrim => ac1_plb_PLB_rdPrim(0 to 0), PLB_reqPri => ac1_plb_PLB_reqPri, PLB_size => ac1_plb_PLB_size, PLB_type => ac1_plb_PLB_type, PLB_wrBurst => ac1_plb_PLB_wrBurst, PLB_wrDBus => ac1_plb_PLB_wrDBus, PLB_wrPrim => ac1_plb_PLB_wrPrim(0 to 0), PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ac1_mb_bridge : system_ac1_mb_bridge_wrapper port map ( SPLB_Clk => net_gnd0, SPLB_Rst => ac1_plb_SPLB_Rst(0), IP2INTC_Irpt => open, PLB_ABus => ac1_plb_PLB_ABus, PLB_UABus => ac1_plb_PLB_UABus, PLB_PAValid => ac1_plb_PLB_PAValid, PLB_SAValid => ac1_plb_PLB_SAValid, PLB_rdPrim => ac1_plb_PLB_rdPrim(0), PLB_wrPrim => ac1_plb_PLB_wrPrim(0), PLB_masterID => ac1_plb_PLB_masterID, PLB_abort => ac1_plb_PLB_abort, PLB_busLock => ac1_plb_PLB_busLock, PLB_RNW => ac1_plb_PLB_RNW, PLB_BE => ac1_plb_PLB_BE, PLB_MSize => ac1_plb_PLB_MSize, PLB_size => ac1_plb_PLB_size, PLB_type => ac1_plb_PLB_type, PLB_lockErr => ac1_plb_PLB_lockErr, PLB_wrDBus => ac1_plb_PLB_wrDBus, PLB_wrBurst => ac1_plb_PLB_wrBurst, PLB_rdBurst => ac1_plb_PLB_rdBurst, PLB_wrPendReq => ac1_plb_PLB_wrPendReq, PLB_rdPendReq => ac1_plb_PLB_rdPendReq, PLB_wrPendPri => ac1_plb_PLB_wrPendPri, PLB_rdPendPri => ac1_plb_PLB_rdPendPri, PLB_reqPri => ac1_plb_PLB_reqPri, PLB_TAttribute => ac1_plb_PLB_TAttribute, Sl_addrAck => ac1_plb_Sl_addrAck(0), Sl_SSize => ac1_plb_Sl_SSize, Sl_wait => ac1_plb_Sl_wait(0), Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0), Sl_wrDAck => ac1_plb_Sl_wrDAck(0), Sl_wrComp => ac1_plb_Sl_wrComp(0), Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0), Sl_rdDBus => ac1_plb_Sl_rdDBus, Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr, Sl_rdDAck => ac1_plb_Sl_rdDAck(0), Sl_rdComp => ac1_plb_Sl_rdComp(0), Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0), Sl_MBusy => ac1_plb_Sl_MBusy, Sl_MWrErr => ac1_plb_Sl_MWrErr, Sl_MRdErr => ac1_plb_Sl_MRdErr, Sl_MIRQ => ac1_plb_Sl_MIRQ, MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(5), M_request => mb_plb_M_request(5), M_priority => mb_plb_M_priority(10 to 11), M_busLock => mb_plb_M_busLock(5), M_RNW => mb_plb_M_RNW(5), M_BE => mb_plb_M_BE(40 to 47), M_MSize => mb_plb_M_MSize(10 to 11), M_size => mb_plb_M_size(20 to 23), M_type => mb_plb_M_type(15 to 17), M_ABus => mb_plb_M_ABus(160 to 191), M_wrBurst => mb_plb_M_wrBurst(5), M_rdBurst => mb_plb_M_rdBurst(5), M_wrDBus => mb_plb_M_wrDBus(320 to 383), PLB_MAddrAck => mb_plb_PLB_MAddrAck(5), PLB_MSSize => mb_plb_PLB_MSSize(10 to 11), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(5), PLB_MTimeout => mb_plb_PLB_MTimeout(5), PLB_MRdErr => mb_plb_PLB_MRdErr(5), PLB_MWrErr => mb_plb_PLB_MWrErr(5), PLB_MRdDBus => mb_plb_PLB_MRdDBus(320 to 383), PLB_MRdDAck => mb_plb_PLB_MRdDAck(5), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(5), PLB_MWrDAck => mb_plb_PLB_MWrDAck(5), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(5), M_TAttribute => mb_plb_M_TAttribute(80 to 95), M_lockErr => mb_plb_M_lockErr(5), M_abort => mb_plb_M_ABort(5), M_UABus => mb_plb_M_UABus(160 to 191), PLB_MBusy => mb_plb_PLB_MBusy(5), PLB_MIRQ => mb_plb_PLB_MIRQ(5), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(20 to 23) ); nfa_accept_samples_generic_hw_top_5 : system_nfa_accept_samples_generic_hw_top_5_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(10), indices_M_request => ac1_plb_M_request(10), indices_M_priority => ac1_plb_M_priority(20 to 21), indices_M_busLock => ac1_plb_M_busLock(10), indices_M_RNW => ac1_plb_M_RNW(10), indices_M_BE => ac1_plb_M_BE(80 to 87), indices_M_MSize => ac1_plb_M_MSize(20 to 21), indices_M_size => ac1_plb_M_size(40 to 43), indices_M_type => ac1_plb_M_type(30 to 32), indices_M_TAttribute => ac1_plb_M_TAttribute(160 to 175), indices_M_lockErr => ac1_plb_M_lockErr(10), indices_M_abort => ac1_plb_M_abort(10), indices_M_UABus => ac1_plb_M_UABus(320 to 351), indices_M_ABus => ac1_plb_M_ABus(320 to 351), indices_M_wrDBus => ac1_plb_M_wrDBus(640 to 703), indices_M_wrBurst => ac1_plb_M_wrBurst(10), indices_M_rdBurst => ac1_plb_M_rdBurst(10), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(10), indices_PLB_MSSize => ac1_plb_PLB_MSSize(20 to 21), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(10), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(10), indices_PLB_MBusy => ac1_plb_PLB_MBusy(10), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(10), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(10), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(10), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(640 to 703), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(40 to 43), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(10), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(10), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(10), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(10), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(11), nfa_finals_buckets_M_request => ac1_plb_M_request(11), nfa_finals_buckets_M_priority => ac1_plb_M_priority(22 to 23), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(11), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(11), nfa_finals_buckets_M_BE => ac1_plb_M_BE(88 to 95), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(22 to 23), nfa_finals_buckets_M_size => ac1_plb_M_size(44 to 47), nfa_finals_buckets_M_type => ac1_plb_M_type(33 to 35), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(176 to 191), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(11), nfa_finals_buckets_M_abort => ac1_plb_M_abort(11), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(352 to 383), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(352 to 383), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(704 to 767), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(11), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(11), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(11), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(22 to 23), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(11), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(11), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(11), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(11), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(11), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(11), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(704 to 767), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(44 to 47), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(11), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(11), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(11), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(11), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(12), nfa_forward_buckets_M_request => ac1_plb_M_request(12), nfa_forward_buckets_M_priority => ac1_plb_M_priority(24 to 25), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(12), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(12), nfa_forward_buckets_M_BE => ac1_plb_M_BE(96 to 103), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(24 to 25), nfa_forward_buckets_M_size => ac1_plb_M_size(48 to 51), nfa_forward_buckets_M_type => ac1_plb_M_type(36 to 38), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(192 to 207), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(12), nfa_forward_buckets_M_abort => ac1_plb_M_abort(12), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(384 to 415), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(384 to 415), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(768 to 831), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(12), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(12), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(12), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(24 to 25), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(12), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(12), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(12), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(12), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(12), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(12), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(768 to 831), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(48 to 51), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(12), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(12), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(12), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(12), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(13), nfa_initials_buckets_M_request => ac1_plb_M_request(13), nfa_initials_buckets_M_priority => ac1_plb_M_priority(26 to 27), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(13), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(13), nfa_initials_buckets_M_BE => ac1_plb_M_BE(104 to 111), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(26 to 27), nfa_initials_buckets_M_size => ac1_plb_M_size(52 to 55), nfa_initials_buckets_M_type => ac1_plb_M_type(39 to 41), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(208 to 223), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(13), nfa_initials_buckets_M_abort => ac1_plb_M_abort(13), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(416 to 447), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(416 to 447), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(832 to 895), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(13), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(13), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(13), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(26 to 27), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(13), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(13), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(13), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(13), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(13), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(13), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(832 to 895), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(52 to 55), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(13), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(13), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(13), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(13), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(14), sample_buffer_M_request => ac1_plb_M_request(14), sample_buffer_M_priority => ac1_plb_M_priority(28 to 29), sample_buffer_M_busLock => ac1_plb_M_busLock(14), sample_buffer_M_RNW => ac1_plb_M_RNW(14), sample_buffer_M_BE => ac1_plb_M_BE(112 to 119), sample_buffer_M_MSize => ac1_plb_M_MSize(28 to 29), sample_buffer_M_size => ac1_plb_M_size(56 to 59), sample_buffer_M_type => ac1_plb_M_type(42 to 44), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(224 to 239), sample_buffer_M_lockErr => ac1_plb_M_lockErr(14), sample_buffer_M_abort => ac1_plb_M_abort(14), sample_buffer_M_UABus => ac1_plb_M_UABus(448 to 479), sample_buffer_M_ABus => ac1_plb_M_ABus(448 to 479), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(896 to 959), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(14), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(14), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(14), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(28 to 29), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(14), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(14), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(14), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(14), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(14), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(14), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(896 to 959), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(56 to 59), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(14), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(14), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(14), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(14), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(11), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(11), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(11), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(11), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(22 to 23), splb_slv0_Sl_wait => mb_plb_Sl_wait(11), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(11), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(11), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(11), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(11), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(704 to 767), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(44 to 47), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(11), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(11), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(11), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(66 to 71), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(66 to 71), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(66 to 71), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(66 to 71) ); iobuf_0 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(0), IO => fpga_0_SRAM_Mem_DQ_pin(0), O => fpga_0_SRAM_Mem_DQ_pin_I(0), T => fpga_0_SRAM_Mem_DQ_pin_T(0) ); iobuf_1 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(1), IO => fpga_0_SRAM_Mem_DQ_pin(1), O => fpga_0_SRAM_Mem_DQ_pin_I(1), T => fpga_0_SRAM_Mem_DQ_pin_T(1) ); iobuf_2 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(2), IO => fpga_0_SRAM_Mem_DQ_pin(2), O => fpga_0_SRAM_Mem_DQ_pin_I(2), T => fpga_0_SRAM_Mem_DQ_pin_T(2) ); iobuf_3 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(3), IO => fpga_0_SRAM_Mem_DQ_pin(3), O => fpga_0_SRAM_Mem_DQ_pin_I(3), T => fpga_0_SRAM_Mem_DQ_pin_T(3) ); iobuf_4 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(4), IO => fpga_0_SRAM_Mem_DQ_pin(4), O => fpga_0_SRAM_Mem_DQ_pin_I(4), T => fpga_0_SRAM_Mem_DQ_pin_T(4) ); iobuf_5 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(5), IO => fpga_0_SRAM_Mem_DQ_pin(5), O => fpga_0_SRAM_Mem_DQ_pin_I(5), T => fpga_0_SRAM_Mem_DQ_pin_T(5) ); iobuf_6 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(6), IO => fpga_0_SRAM_Mem_DQ_pin(6), O => fpga_0_SRAM_Mem_DQ_pin_I(6), T => fpga_0_SRAM_Mem_DQ_pin_T(6) ); iobuf_7 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(7), IO => fpga_0_SRAM_Mem_DQ_pin(7), O => fpga_0_SRAM_Mem_DQ_pin_I(7), T => fpga_0_SRAM_Mem_DQ_pin_T(7) ); iobuf_8 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(8), IO => fpga_0_SRAM_Mem_DQ_pin(8), O => fpga_0_SRAM_Mem_DQ_pin_I(8), T => fpga_0_SRAM_Mem_DQ_pin_T(8) ); iobuf_9 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(9), IO => fpga_0_SRAM_Mem_DQ_pin(9), O => fpga_0_SRAM_Mem_DQ_pin_I(9), T => fpga_0_SRAM_Mem_DQ_pin_T(9) ); iobuf_10 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(10), IO => fpga_0_SRAM_Mem_DQ_pin(10), O => fpga_0_SRAM_Mem_DQ_pin_I(10), T => fpga_0_SRAM_Mem_DQ_pin_T(10) ); iobuf_11 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(11), IO => fpga_0_SRAM_Mem_DQ_pin(11), O => fpga_0_SRAM_Mem_DQ_pin_I(11), T => fpga_0_SRAM_Mem_DQ_pin_T(11) ); iobuf_12 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(12), IO => fpga_0_SRAM_Mem_DQ_pin(12), O => fpga_0_SRAM_Mem_DQ_pin_I(12), T => fpga_0_SRAM_Mem_DQ_pin_T(12) ); iobuf_13 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(13), IO => fpga_0_SRAM_Mem_DQ_pin(13), O => fpga_0_SRAM_Mem_DQ_pin_I(13), T => fpga_0_SRAM_Mem_DQ_pin_T(13) ); iobuf_14 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(14), IO => fpga_0_SRAM_Mem_DQ_pin(14), O => fpga_0_SRAM_Mem_DQ_pin_I(14), T => fpga_0_SRAM_Mem_DQ_pin_T(14) ); iobuf_15 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(15), IO => fpga_0_SRAM_Mem_DQ_pin(15), O => fpga_0_SRAM_Mem_DQ_pin_I(15), T => fpga_0_SRAM_Mem_DQ_pin_T(15) ); iobuf_16 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(16), IO => fpga_0_SRAM_Mem_DQ_pin(16), O => fpga_0_SRAM_Mem_DQ_pin_I(16), T => fpga_0_SRAM_Mem_DQ_pin_T(16) ); iobuf_17 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(17), IO => fpga_0_SRAM_Mem_DQ_pin(17), O => fpga_0_SRAM_Mem_DQ_pin_I(17), T => fpga_0_SRAM_Mem_DQ_pin_T(17) ); iobuf_18 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(18), IO => fpga_0_SRAM_Mem_DQ_pin(18), O => fpga_0_SRAM_Mem_DQ_pin_I(18), T => fpga_0_SRAM_Mem_DQ_pin_T(18) ); iobuf_19 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(19), IO => fpga_0_SRAM_Mem_DQ_pin(19), O => fpga_0_SRAM_Mem_DQ_pin_I(19), T => fpga_0_SRAM_Mem_DQ_pin_T(19) ); iobuf_20 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(20), IO => fpga_0_SRAM_Mem_DQ_pin(20), O => fpga_0_SRAM_Mem_DQ_pin_I(20), T => fpga_0_SRAM_Mem_DQ_pin_T(20) ); iobuf_21 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(21), IO => fpga_0_SRAM_Mem_DQ_pin(21), O => fpga_0_SRAM_Mem_DQ_pin_I(21), T => fpga_0_SRAM_Mem_DQ_pin_T(21) ); iobuf_22 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(22), IO => fpga_0_SRAM_Mem_DQ_pin(22), O => fpga_0_SRAM_Mem_DQ_pin_I(22), T => fpga_0_SRAM_Mem_DQ_pin_T(22) ); iobuf_23 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(23), IO => fpga_0_SRAM_Mem_DQ_pin(23), O => fpga_0_SRAM_Mem_DQ_pin_I(23), T => fpga_0_SRAM_Mem_DQ_pin_T(23) ); iobuf_24 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(24), IO => fpga_0_SRAM_Mem_DQ_pin(24), O => fpga_0_SRAM_Mem_DQ_pin_I(24), T => fpga_0_SRAM_Mem_DQ_pin_T(24) ); iobuf_25 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(25), IO => fpga_0_SRAM_Mem_DQ_pin(25), O => fpga_0_SRAM_Mem_DQ_pin_I(25), T => fpga_0_SRAM_Mem_DQ_pin_T(25) ); iobuf_26 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(26), IO => fpga_0_SRAM_Mem_DQ_pin(26), O => fpga_0_SRAM_Mem_DQ_pin_I(26), T => fpga_0_SRAM_Mem_DQ_pin_T(26) ); iobuf_27 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(27), IO => fpga_0_SRAM_Mem_DQ_pin(27), O => fpga_0_SRAM_Mem_DQ_pin_I(27), T => fpga_0_SRAM_Mem_DQ_pin_T(27) ); iobuf_28 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(28), IO => fpga_0_SRAM_Mem_DQ_pin(28), O => fpga_0_SRAM_Mem_DQ_pin_I(28), T => fpga_0_SRAM_Mem_DQ_pin_T(28) ); iobuf_29 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(29), IO => fpga_0_SRAM_Mem_DQ_pin(29), O => fpga_0_SRAM_Mem_DQ_pin_I(29), T => fpga_0_SRAM_Mem_DQ_pin_T(29) ); iobuf_30 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(30), IO => fpga_0_SRAM_Mem_DQ_pin(30), O => fpga_0_SRAM_Mem_DQ_pin_I(30), T => fpga_0_SRAM_Mem_DQ_pin_T(30) ); iobuf_31 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(31), IO => fpga_0_SRAM_Mem_DQ_pin(31), O => fpga_0_SRAM_Mem_DQ_pin_I(31), T => fpga_0_SRAM_Mem_DQ_pin_T(31) ); ibufgds_32 : IBUFGDS port map ( I => fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin, IB => fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin, O => PCIe_Diff_Clk ); end architecture STRUCTURE;	lgpl-3.0	8c7135c90d2d2c08b28a9ed0b610ce51	0.613645	2.849808	false	false	false	false
grwlf/vsim	vhdl_ct/ct00071.vhd	1	51,479	-- NEED RESULT: ARCH00071.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00071 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00071) -- ENT00071_Test_Bench(ARCH00071_Test_Bench) -- -- REVISION HISTORY: -- -- 06-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00071 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_boolean ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P1" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= transport c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; s_boolean <= transport c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_bit ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P2" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= transport c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; s_bit <= transport c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_severity_level ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P3" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= transport c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; s_severity_level <= transport c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_character ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P4" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= transport c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; s_character <= transport c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_st_enum1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P5" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= transport c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1 <= transport c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_integer ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P6" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= transport c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; s_integer <= transport c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process ( s_st_int1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P7" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= transport c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1 <= transport c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process ( s_time ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P8" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= transport c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; s_time <= transport c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process ( s_st_phys1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P9" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= transport c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1 <= transport c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process ( s_real ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P10" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= transport c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; s_real <= transport c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process ( s_st_real1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P11" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= transport c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1 <= transport c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process ( s_st_rec1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P12" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= transport c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1 <= transport c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process ( s_st_rec2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P13" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= transport c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2 <= transport c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process ( s_st_rec3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P14" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= transport c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3 <= transport c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process ( s_st_arr1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P15" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= transport c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 <= transport c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process ( s_st_arr2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P16" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= transport c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 <= transport c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process ( s_st_arr3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P17" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= transport c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 <= transport c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P17 ; -- -- end ARCH00071 ; -- entity ENT00071_Test_Bench is end ENT00071_Test_Bench ; -- architecture ARCH00071_Test_Bench of ENT00071_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00071 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00071_Test_Bench ;	gpl-3.0	3b0bcb3a4741d340a9f48daea3a5549a	0.5098	4.069808	false	true	false	false
grwlf/vsim	vhdl_ct/ct00634.vhd	1	84,966	-- NEED RESULT: ARCH00634.P1: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P2: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P3: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P4: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P5: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P6: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P7: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P8: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P9: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P10: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P11: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P12: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P13: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P14: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P15: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P16: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P17: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00634 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (6) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00634) -- ENT00634_Test_Bench(ARCH00634_Test_Bench) -- -- REVISION HISTORY: -- -- 25-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00634 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- signal s_boolean_1 : boolean := c_boolean_1 ; signal s_bit_1 : bit := c_bit_1 ; signal s_severity_level_1 : severity_level := c_severity_level_1 ; signal s_character_1 : character := c_character_1 ; signal s_st_enum1_1 : st_enum1 := c_st_enum1_1 ; signal s_integer_1 : integer := c_integer_1 ; signal s_st_int1_1 : st_int1 := c_st_int1_1 ; signal s_time_1 : time := c_time_1 ; signal s_st_phys1_1 : st_phys1 := c_st_phys1_1 ; signal s_real_1 : real := c_real_1 ; signal s_st_real1_1 : st_real1 := c_st_real1_1 ; signal s_st_rec1_1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_1 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_1 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_1 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- signal s_boolean_2 : boolean := c_boolean_1 ; signal s_bit_2 : bit := c_bit_1 ; signal s_severity_level_2 : severity_level := c_severity_level_1 ; signal s_character_2 : character := c_character_1 ; signal s_st_enum1_2 : st_enum1 := c_st_enum1_1 ; signal s_integer_2 : integer := c_integer_1 ; signal s_st_int1_2 : st_int1 := c_st_int1_1 ; signal s_time_2 : time := c_time_1 ; signal s_st_phys1_2 : st_phys1 := c_st_phys1_1 ; signal s_real_2 : real := c_real_1 ; signal s_st_real1_2 : st_real1 := c_st_real1_1 ; signal s_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- signal s_boolean_3 : boolean := c_boolean_1 ; signal s_bit_3 : bit := c_bit_1 ; signal s_severity_level_3 : severity_level := c_severity_level_1 ; signal s_character_3 : character := c_character_1 ; signal s_st_enum1_3 : st_enum1 := c_st_enum1_1 ; signal s_integer_3 : integer := c_integer_1 ; signal s_st_int1_3 : st_int1 := c_st_int1_1 ; signal s_time_3 : time := c_time_1 ; signal s_st_phys1_3 : st_phys1 := c_st_phys1_1 ; signal s_real_3 : real := c_real_1 ; signal s_st_real1_3 : st_real1 := c_st_real1_1 ; signal s_st_rec1_3 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_3 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_3 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_3 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 10 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 20 ns ; -- when 1 => correct := s_boolean_1 = c_boolean_2 and s_boolean_2 = c_boolean_2 and s_boolean_3 = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean_1 = c_boolean_1 and s_boolean_2 = c_boolean_1 and s_boolean_3 = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P1" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 10 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 20 ns, arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 30 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 40 ns ; -- when 3 => correct := s_boolean_1 = c_boolean_2 and s_boolean_2 = c_boolean_2 and s_boolean_3 = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 5 ns ; -- when 4 => correct := correct and s_boolean_1 = c_boolean_1 and s_boolean_2 = c_boolean_1 and s_boolean_3 = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_boolean_1'EVENT and s_boolean_2'EVENT and s_boolean_3'EVENT ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 10 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 20 ns ; -- when 1 => correct := s_bit_1 = c_bit_2 and s_bit_2 = c_bit_2 and s_bit_3 = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit_1 = c_bit_1 and s_bit_2 = c_bit_1 and s_bit_3 = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P2" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 10 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 20 ns, arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 30 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 40 ns ; -- when 3 => correct := s_bit_1 = c_bit_2 and s_bit_2 = c_bit_2 and s_bit_3 = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 5 ns ; -- when 4 => correct := correct and s_bit_1 = c_bit_1 and s_bit_2 = c_bit_1 and s_bit_3 = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_bit_1'EVENT and s_bit_2'EVENT and s_bit_3'EVENT ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 10 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 20 ns ; -- when 1 => correct := s_severity_level_1 = c_severity_level_2 and s_severity_level_2 = c_severity_level_2 and s_severity_level_3 = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level_1 = c_severity_level_1 and s_severity_level_2 = c_severity_level_1 and s_severity_level_3 = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P3" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 10 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 20 ns, arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 30 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 40 ns ; -- when 3 => correct := s_severity_level_1 = c_severity_level_2 and s_severity_level_2 = c_severity_level_2 and s_severity_level_3 = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 5 ns ; -- when 4 => correct := correct and s_severity_level_1 = c_severity_level_1 and s_severity_level_2 = c_severity_level_1 and s_severity_level_3 = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_severity_level_1'EVENT and s_severity_level_2'EVENT and s_severity_level_3'EVENT ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 10 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 20 ns ; -- when 1 => correct := s_character_1 = c_character_2 and s_character_2 = c_character_2 and s_character_3 = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character_1 = c_character_1 and s_character_2 = c_character_1 and s_character_3 = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P4" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 10 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 20 ns, arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 30 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 40 ns ; -- when 3 => correct := s_character_1 = c_character_2 and s_character_2 = c_character_2 and s_character_3 = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 5 ns ; -- when 4 => correct := correct and s_character_1 = c_character_1 and s_character_2 = c_character_1 and s_character_3 = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_character_1'EVENT and s_character_2'EVENT and s_character_3'EVENT ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 10 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 20 ns ; -- when 1 => correct := s_st_enum1_1 = c_st_enum1_2 and s_st_enum1_2 = c_st_enum1_2 and s_st_enum1_3 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_1 = c_st_enum1_1 and s_st_enum1_2 = c_st_enum1_1 and s_st_enum1_3 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P5" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 10 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 20 ns, arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 30 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 40 ns ; -- when 3 => correct := s_st_enum1_1 = c_st_enum1_2 and s_st_enum1_2 = c_st_enum1_2 and s_st_enum1_3 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_1 = c_st_enum1_1 and s_st_enum1_2 = c_st_enum1_1 and s_st_enum1_3 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_enum1_1'EVENT and s_st_enum1_2'EVENT and s_st_enum1_3'EVENT ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 10 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 20 ns ; -- when 1 => correct := s_integer_1 = c_integer_2 and s_integer_2 = c_integer_2 and s_integer_3 = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer_1 = c_integer_1 and s_integer_2 = c_integer_1 and s_integer_3 = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P6" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 10 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 20 ns, arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 30 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 40 ns ; -- when 3 => correct := s_integer_1 = c_integer_2 and s_integer_2 = c_integer_2 and s_integer_3 = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 5 ns ; -- when 4 => correct := correct and s_integer_1 = c_integer_1 and s_integer_2 = c_integer_1 and s_integer_3 = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_integer_1'EVENT and s_integer_2'EVENT and s_integer_3'EVENT ; end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 10 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 20 ns ; -- when 1 => correct := s_st_int1_1 = c_st_int1_2 and s_st_int1_2 = c_st_int1_2 and s_st_int1_3 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1_1 = c_st_int1_1 and s_st_int1_2 = c_st_int1_1 and s_st_int1_3 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P7" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 10 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 20 ns, arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 30 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 40 ns ; -- when 3 => correct := s_st_int1_1 = c_st_int1_2 and s_st_int1_2 = c_st_int1_2 and s_st_int1_3 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_int1_1 = c_st_int1_1 and s_st_int1_2 = c_st_int1_1 and s_st_int1_3 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_int1_1'EVENT and s_st_int1_2'EVENT and s_st_int1_3'EVENT ; end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 10 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 20 ns ; -- when 1 => correct := s_time_1 = c_time_2 and s_time_2 = c_time_2 and s_time_3 = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time_1 = c_time_1 and s_time_2 = c_time_1 and s_time_3 = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P8" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 10 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 20 ns, arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 30 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 40 ns ; -- when 3 => correct := s_time_1 = c_time_2 and s_time_2 = c_time_2 and s_time_3 = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 5 ns ; -- when 4 => correct := correct and s_time_1 = c_time_1 and s_time_2 = c_time_1 and s_time_3 = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_time_1'EVENT and s_time_2'EVENT and s_time_3'EVENT ; end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 10 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 20 ns ; -- when 1 => correct := s_st_phys1_1 = c_st_phys1_2 and s_st_phys1_2 = c_st_phys1_2 and s_st_phys1_3 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1_1 = c_st_phys1_1 and s_st_phys1_2 = c_st_phys1_1 and s_st_phys1_3 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P9" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 10 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 20 ns, arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 30 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 40 ns ; -- when 3 => correct := s_st_phys1_1 = c_st_phys1_2 and s_st_phys1_2 = c_st_phys1_2 and s_st_phys1_3 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_phys1_1 = c_st_phys1_1 and s_st_phys1_2 = c_st_phys1_1 and s_st_phys1_3 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_phys1_1'EVENT and s_st_phys1_2'EVENT and s_st_phys1_3'EVENT ; end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 10 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 20 ns ; -- when 1 => correct := s_real_1 = c_real_2 and s_real_2 = c_real_2 and s_real_3 = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real_1 = c_real_1 and s_real_2 = c_real_1 and s_real_3 = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P10" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 10 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 20 ns, arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 30 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 40 ns ; -- when 3 => correct := s_real_1 = c_real_2 and s_real_2 = c_real_2 and s_real_3 = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 5 ns ; -- when 4 => correct := correct and s_real_1 = c_real_1 and s_real_2 = c_real_1 and s_real_3 = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_real_1'EVENT and s_real_2'EVENT and s_real_3'EVENT ; end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 10 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 20 ns ; -- when 1 => correct := s_st_real1_1 = c_st_real1_2 and s_st_real1_2 = c_st_real1_2 and s_st_real1_3 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1_1 = c_st_real1_1 and s_st_real1_2 = c_st_real1_1 and s_st_real1_3 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P11" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 10 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 20 ns, arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 30 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 40 ns ; -- when 3 => correct := s_st_real1_1 = c_st_real1_2 and s_st_real1_2 = c_st_real1_2 and s_st_real1_3 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_real1_1 = c_st_real1_1 and s_st_real1_2 = c_st_real1_1 and s_st_real1_3 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_real1_1'EVENT and s_st_real1_2'EVENT and s_st_real1_3'EVENT ; end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 10 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 20 ns ; -- when 1 => correct := s_st_rec1_1 = c_st_rec1_2 and s_st_rec1_2 = c_st_rec1_2 and s_st_rec1_3 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_1 = c_st_rec1_1 and s_st_rec1_2 = c_st_rec1_1 and s_st_rec1_3 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P12" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 10 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 20 ns, arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 30 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 40 ns ; -- when 3 => correct := s_st_rec1_1 = c_st_rec1_2 and s_st_rec1_2 = c_st_rec1_2 and s_st_rec1_3 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_1 = c_st_rec1_1 and s_st_rec1_2 = c_st_rec1_1 and s_st_rec1_3 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec1_1'EVENT and s_st_rec1_2'EVENT and s_st_rec1_3'EVENT ; end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 10 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 20 ns ; -- when 1 => correct := s_st_rec2_1 = c_st_rec2_2 and s_st_rec2_2 = c_st_rec2_2 and s_st_rec2_3 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_1 = c_st_rec2_1 and s_st_rec2_2 = c_st_rec2_1 and s_st_rec2_3 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P13" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 10 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 20 ns, arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 30 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 40 ns ; -- when 3 => correct := s_st_rec2_1 = c_st_rec2_2 and s_st_rec2_2 = c_st_rec2_2 and s_st_rec2_3 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec2_1 = c_st_rec2_1 and s_st_rec2_2 = c_st_rec2_1 and s_st_rec2_3 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec2_1'EVENT and s_st_rec2_2'EVENT and s_st_rec2_3'EVENT ; end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 10 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 20 ns ; -- when 1 => correct := s_st_rec3_1 = c_st_rec3_2 and s_st_rec3_2 = c_st_rec3_2 and s_st_rec3_3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_1 = c_st_rec3_1 and s_st_rec3_2 = c_st_rec3_1 and s_st_rec3_3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P14" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 10 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 20 ns, arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 30 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 40 ns ; -- when 3 => correct := s_st_rec3_1 = c_st_rec3_2 and s_st_rec3_2 = c_st_rec3_2 and s_st_rec3_3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec3_1 = c_st_rec3_1 and s_st_rec3_2 = c_st_rec3_1 and s_st_rec3_3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec3_1'EVENT and s_st_rec3_2'EVENT and s_st_rec3_3'EVENT ; end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 10 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 20 ns ; -- when 1 => correct := s_st_arr1_1 = c_st_arr1_2 and s_st_arr1_2 = c_st_arr1_2 and s_st_arr1_3 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_1 = c_st_arr1_1 and s_st_arr1_2 = c_st_arr1_1 and s_st_arr1_3 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P15" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 10 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 20 ns, arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 30 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 40 ns ; -- when 3 => correct := s_st_arr1_1 = c_st_arr1_2 and s_st_arr1_2 = c_st_arr1_2 and s_st_arr1_3 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr1_1 = c_st_arr1_1 and s_st_arr1_2 = c_st_arr1_1 and s_st_arr1_3 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr1_1'EVENT and s_st_arr1_2'EVENT and s_st_arr1_3'EVENT ; end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 10 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 20 ns ; -- when 1 => correct := s_st_arr2_1 = c_st_arr2_2 and s_st_arr2_2 = c_st_arr2_2 and s_st_arr2_3 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_1 = c_st_arr2_1 and s_st_arr2_2 = c_st_arr2_1 and s_st_arr2_3 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P16" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 10 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 20 ns, arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 30 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 40 ns ; -- when 3 => correct := s_st_arr2_1 = c_st_arr2_2 and s_st_arr2_2 = c_st_arr2_2 and s_st_arr2_3 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_1 = c_st_arr2_1 and s_st_arr2_2 = c_st_arr2_1 and s_st_arr2_3 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr2_1'EVENT and s_st_arr2_2'EVENT and s_st_arr2_3'EVENT ; end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 10 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 20 ns ; -- when 1 => correct := s_st_arr3_1 = c_st_arr3_2 and s_st_arr3_2 = c_st_arr3_2 and s_st_arr3_3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_1 = c_st_arr3_1 and s_st_arr3_2 = c_st_arr3_1 and s_st_arr3_3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P17" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 10 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 20 ns, arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 30 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 40 ns ; -- when 3 => correct := s_st_arr3_1 = c_st_arr3_2 and s_st_arr3_2 = c_st_arr3_2 and s_st_arr3_3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr3_1 = c_st_arr3_1 and s_st_arr3_2 = c_st_arr3_1 and s_st_arr3_3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr3_1'EVENT and s_st_arr3_2'EVENT and s_st_arr3_3'EVENT ; end process P17 ; -- -- end ARCH00634 ; -- entity ENT00634_Test_Bench is end ENT00634_Test_Bench ; -- architecture ARCH00634_Test_Bench of ENT00634_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00634 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00634_Test_Bench ;	gpl-3.0	a31d2cea095e154a00416d2a889254c0	0.444319	3.854032	false	false	false	false
jairov4/accel-oil	impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_get_finals/_primary.vhd	1	2,755	library verilog; use verilog.vl_types.all; entity nfa_get_finals is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0); ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0); ap_ST_pp0_stg2_fsm_2: vl_logic_vector(0 to 1) := (Hi0, Hi1); ap_ST_pp0_stg3_fsm_3: vl_logic_vector(0 to 1) := (Hi1, Hi1); ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_const_lv32_0 : integer := 0; ap_const_lv32_1 : integer := 1; ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; ap_ce : in vl_logic; nfa_finals_buckets_req_din: out vl_logic; nfa_finals_buckets_req_full_n: in vl_logic; nfa_finals_buckets_req_write: out vl_logic; nfa_finals_buckets_rsp_empty_n: in vl_logic; nfa_finals_buckets_rsp_read: out vl_logic; nfa_finals_buckets_address: out vl_logic_vector(31 downto 0); nfa_finals_buckets_datain: in vl_logic_vector(31 downto 0); nfa_finals_buckets_dataout: out vl_logic_vector(31 downto 0); nfa_finals_buckets_size: out vl_logic_vector(31 downto 0); ap_return_0 : out vl_logic_vector(31 downto 0); ap_return_1 : out vl_logic_vector(31 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg1_fsm_1 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg2_fsm_2 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg3_fsm_3 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end nfa_get_finals;	lgpl-3.0	41a876e40b880a84e5f032333f8ffdc1	0.597096	2.646494	false	false	false	false
MilosSubotic/huffman_coding	RTL/src/rtl/huffman_coding.vhd	1	1,176	------------------------------------------------------------------------------ -- @license MIT -- @brief Huffman coding example. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity huffman_coding is port( i_sw : in std_logic_vector(7 downto 0); o_leds : out std_logic_vector(7 downto 0); on_7_segm_led_disp_a : out std_logic; on_7_segm_led_disp_b : out std_logic; on_7_segm_led_disp_c : out std_logic; on_7_segm_led_disp_d : out std_logic; on_7_segm_led_disp_e : out std_logic; on_7_segm_led_disp_f : out std_logic; on_7_segm_led_disp_g : out std_logic ); end entity huffman_coding; architecture arch_huffman_coding_v1 of huffman_coding is begin on_7_segm_led_disp_a <= i_sw(0); on_7_segm_led_disp_b <= i_sw(1); on_7_segm_led_disp_c <= i_sw(2); on_7_segm_led_disp_d <= i_sw(3); on_7_segm_led_disp_e <= i_sw(4); on_7_segm_led_disp_f <= i_sw(5); on_7_segm_led_disp_g <= i_sw(6); o_leds <= i_sw; end architecture arch_huffman_coding_v1;	mit	7636d16d8a4137b0d0006cfdc33b367f	0.511905	2.60177	false	false	false	false
SamuelLBau/Pool-Shot-Tracking-using-FPGA	examples/sparse_mm/solution1/syn/vhdl/sparse_mm.vhd	1	30,066	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sparse_mm is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; a_address0 : OUT STD_LOGIC_VECTOR (21 downto 0); a_ce0 : OUT STD_LOGIC; a_q0 : IN STD_LOGIC_VECTOR (63 downto 0); a_y : IN STD_LOGIC_VECTOR (31 downto 0); a_x : IN STD_LOGIC_VECTOR (31 downto 0); b_address0 : OUT STD_LOGIC_VECTOR (10 downto 0); b_ce0 : OUT STD_LOGIC; b_q0 : IN STD_LOGIC_VECTOR (31 downto 0); b_y : IN STD_LOGIC_VECTOR (31 downto 0); b_x : IN STD_LOGIC_VECTOR (31 downto 0); c_address0 : OUT STD_LOGIC_VECTOR (10 downto 0); c_ce0 : OUT STD_LOGIC; c_we0 : OUT STD_LOGIC; c_d0 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sparse_mm is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "sparse_mm,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.280000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=462,HLS_SYN_LUT=355}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_34 : BOOLEAN; signal ibx_cast_fu_145_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ibx_cast_reg_258 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_78 : BOOLEAN; signal ibx_1_fu_154_p2 : STD_LOGIC_VECTOR (30 downto 0); signal ibx_1_reg_267 : STD_LOGIC_VECTOR (30 downto 0); signal a_i_1_fu_165_p2 : STD_LOGIC_VECTOR (31 downto 0); signal a_i_1_reg_275 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC; signal ap_sig_bdd_89 : BOOLEAN; signal tmp_1_fu_160_p2 : STD_LOGIC_VECTOR (0 downto 0); signal column_cast_fu_190_p1 : STD_LOGIC_VECTOR (31 downto 0); signal column_cast_reg_289 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC; signal ap_sig_bdd_105 : BOOLEAN; signal value_reg_294 : STD_LOGIC_VECTOR (31 downto 0); signal iay_1_fu_204_p2 : STD_LOGIC_VECTOR (31 downto 0); signal iay_1_reg_299 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_6_fu_176_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_215_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_reg_304 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC; signal ap_sig_bdd_122 : BOOLEAN; signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC; signal ap_sig_bdd_131 : BOOLEAN; signal b_load_reg_314 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC; signal ap_sig_bdd_139 : BOOLEAN; signal grp_fu_228_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_reg_319 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC; signal ap_sig_bdd_148 : BOOLEAN; signal sum_1_fu_232_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC; signal ap_sig_bdd_157 : BOOLEAN; signal grp_fu_210_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_3_reg_329 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC; signal ap_sig_bdd_166 : BOOLEAN; signal ibx_reg_90 : STD_LOGIC_VECTOR (30 downto 0); signal a_i_reg_101 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_149_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC; signal ap_sig_bdd_183 : BOOLEAN; signal iay_reg_114 : STD_LOGIC_VECTOR (31 downto 0); signal sum_reg_129 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_171_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_fu_223_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_4_fu_241_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC; signal ap_sig_bdd_200 : BOOLEAN; signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC; signal ap_sig_bdd_208 : BOOLEAN; signal tmp_fu_149_p1 : STD_LOGIC_VECTOR (31 downto 0); signal column_fu_180_p4 : STD_LOGIC_VECTOR (30 downto 0); signal grp_fu_215_p0 : STD_LOGIC_VECTOR (30 downto 0); signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC; signal ap_sig_bdd_247 : BOOLEAN; signal tmp_9_fu_219_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_237_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_210_ce : STD_LOGIC; signal grp_fu_215_ce : STD_LOGIC; signal grp_fu_228_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0); component sparse_mm_mul_32s_32s_32_3 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sparse_mm_mul_31ns_32s_32_3 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (30 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin sparse_mm_mul_32s_32s_32_3_U1 : component sparse_mm_mul_32s_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => iay_reg_114, din1 => b_x, ce => grp_fu_210_ce, dout => grp_fu_210_p2); sparse_mm_mul_31ns_32s_32_3_U2 : component sparse_mm_mul_31ns_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 31, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_215_p0, din1 => b_x, ce => grp_fu_215_ce, dout => grp_fu_215_p2); sparse_mm_mul_32s_32s_32_3_U3 : component sparse_mm_mul_32s_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => b_load_reg_314, din1 => value_reg_294, ce => grp_fu_228_ce, dout => grp_fu_228_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- a_i_reg_101 assign process. -- a_i_reg_101_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then a_i_reg_101 <= a_i_1_reg_275; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then a_i_reg_101 <= ap_const_lv32_0; end if; end if; end process; -- iay_reg_114 assign process. -- iay_reg_114_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then iay_reg_114 <= iay_reg_114; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then iay_reg_114 <= iay_1_reg_299; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then iay_reg_114 <= ap_const_lv32_0; end if; end if; end process; -- ibx_reg_90 assign process. -- ibx_reg_90_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (tmp_1_fu_160_p2 = ap_const_lv1_0))) then ibx_reg_90 <= ibx_1_reg_267; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ibx_reg_90 <= ap_const_lv31_0; end if; end if; end process; -- sum_reg_129 assign process. -- sum_reg_129_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then sum_reg_129 <= sum_1_fu_232_p2; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then sum_reg_129 <= ap_const_lv32_0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then a_i_1_reg_275 <= a_i_1_fu_165_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then b_load_reg_314 <= b_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then column_cast_reg_289(30 downto 0) <= column_cast_fu_190_p1(30 downto 0); value_reg_294 <= a_q0(63 downto 32); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_6_fu_176_p1)))) then iay_1_reg_299 <= iay_1_fu_204_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then ibx_1_reg_267 <= ibx_1_fu_154_p2; ibx_cast_reg_258(30 downto 0) <= ibx_cast_fu_145_p1(30 downto 0); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then tmp_3_reg_329 <= grp_fu_210_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then tmp_7_reg_319 <= grp_fu_228_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then tmp_8_reg_304 <= grp_fu_215_p2; end if; end if; end process; ibx_cast_reg_258(31) <= '0'; column_cast_reg_289(31) <= '0'; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_160_p2, tmp_6_fu_176_p1, tmp_fu_149_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if ((ap_const_lv1_0 = tmp_fu_149_p2)) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_st3_fsm_2; end if; when ap_ST_st3_fsm_2 => if (not((tmp_1_fu_160_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st4_fsm_3; else ap_NS_fsm <= ap_ST_st2_fsm_1; end if; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => if (not((ap_const_lv1_0 = tmp_6_fu_176_p1))) then ap_NS_fsm <= ap_ST_st16_fsm_15; else ap_NS_fsm <= ap_ST_st7_fsm_6; end if; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st3_fsm_2; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX"; end case; end process; a_address0 <= tmp_2_fu_171_p1(22 - 1 downto 0); -- a_ce0 assign process. -- a_ce0_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st5_fsm_4) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4))) then a_ce0 <= ap_const_logic_1; else a_ce0 <= ap_const_logic_0; end if; end process; a_i_1_fu_165_p2 <= std_logic_vector(unsigned(a_i_reg_101) + unsigned(ap_const_lv32_1)); -- ap_done assign process. -- ap_done_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_105 assign process. -- ap_sig_bdd_105_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; -- ap_sig_bdd_122 assign process. -- ap_sig_bdd_122_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_122 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; -- ap_sig_bdd_131 assign process. -- ap_sig_bdd_131_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_131 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; -- ap_sig_bdd_139 assign process. -- ap_sig_bdd_139_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_139 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; -- ap_sig_bdd_148 assign process. -- ap_sig_bdd_148_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13)); end process; -- ap_sig_bdd_157 assign process. -- ap_sig_bdd_157_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_157 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14)); end process; -- ap_sig_bdd_166 assign process. -- ap_sig_bdd_166_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_166 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16)); end process; -- ap_sig_bdd_183 assign process. -- ap_sig_bdd_183_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_183 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17)); end process; -- ap_sig_bdd_200 assign process. -- ap_sig_bdd_200_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_200 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_208 assign process. -- ap_sig_bdd_208_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_208 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; -- ap_sig_bdd_247 assign process. -- ap_sig_bdd_247_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; -- ap_sig_bdd_34 assign process. -- ap_sig_bdd_34_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_78 assign process. -- ap_sig_bdd_78_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_78 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_89 assign process. -- ap_sig_bdd_89_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_cseq_ST_st10_fsm_9 assign process. -- ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_131) begin if (ap_sig_bdd_131) then ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st11_fsm_10 assign process. -- ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_139) begin if (ap_sig_bdd_139) then ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st14_fsm_13 assign process. -- ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_148) begin if (ap_sig_bdd_148) then ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1; else ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st15_fsm_14 assign process. -- ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_157) begin if (ap_sig_bdd_157) then ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1; else ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st17_fsm_16 assign process. -- ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_166) begin if (ap_sig_bdd_166) then ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st18_fsm_17 assign process. -- ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_183) begin if (ap_sig_bdd_183) then ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1; else ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34) begin if (ap_sig_bdd_34) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_78) begin if (ap_sig_bdd_78) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st3_fsm_2 assign process. -- ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_89) begin if (ap_sig_bdd_89) then ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st4_fsm_3 assign process. -- ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_200) begin if (ap_sig_bdd_200) then ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_4 assign process. -- ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_208) begin if (ap_sig_bdd_208) then ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st6_fsm_5 assign process. -- ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_105) begin if (ap_sig_bdd_105) then ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st7_fsm_6 assign process. -- ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_247) begin if (ap_sig_bdd_247) then ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st9_fsm_8 assign process. -- ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_122) begin if (ap_sig_bdd_122) then ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0; end if; end process; b_address0 <= tmp_s_fu_223_p1(11 - 1 downto 0); -- b_ce0 assign process. -- b_ce0_assign_proc : process(ap_sig_cseq_ST_st10_fsm_9) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then b_ce0 <= ap_const_logic_1; else b_ce0 <= ap_const_logic_0; end if; end process; c_address0 <= tmp_4_fu_241_p1(11 - 1 downto 0); -- c_ce0 assign process. -- c_ce0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then c_ce0 <= ap_const_logic_1; else c_ce0 <= ap_const_logic_0; end if; end process; c_d0 <= sum_reg_129; -- c_we0 assign process. -- c_we0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then c_we0 <= ap_const_logic_1; else c_we0 <= ap_const_logic_0; end if; end process; column_cast_fu_190_p1 <= std_logic_vector(resize(unsigned(column_fu_180_p4),32)); column_fu_180_p4 <= a_q0(31 downto 1); grp_fu_210_ce <= ap_const_logic_1; grp_fu_215_ce <= ap_const_logic_1; grp_fu_215_p0 <= column_cast_reg_289(31 - 1 downto 0); grp_fu_228_ce <= ap_const_logic_1; iay_1_fu_204_p2 <= std_logic_vector(signed(iay_reg_114) + signed(ap_const_lv32_1)); ibx_1_fu_154_p2 <= std_logic_vector(unsigned(ibx_reg_90) + unsigned(ap_const_lv31_1)); ibx_cast_fu_145_p1 <= std_logic_vector(resize(unsigned(ibx_reg_90),32)); sum_1_fu_232_p2 <= std_logic_vector(unsigned(tmp_7_reg_319) + unsigned(sum_reg_129)); tmp_1_fu_160_p2 <= "1" when (unsigned(iay_reg_114) < unsigned(a_y)) else "0"; tmp_2_fu_171_p1 <= std_logic_vector(resize(signed(a_i_reg_101),64)); tmp_4_fu_241_p1 <= std_logic_vector(resize(signed(tmp_5_fu_237_p2),64)); tmp_5_fu_237_p2 <= std_logic_vector(unsigned(tmp_3_reg_329) + unsigned(ibx_cast_reg_258)); tmp_6_fu_176_p1 <= a_q0(1 - 1 downto 0); tmp_9_fu_219_p2 <= std_logic_vector(unsigned(tmp_8_reg_304) + unsigned(ibx_cast_reg_258)); tmp_fu_149_p1 <= b_x; tmp_fu_149_p2 <= "1" when (signed(ibx_cast_fu_145_p1) < signed(tmp_fu_149_p1)) else "0"; tmp_s_fu_223_p1 <= std_logic_vector(resize(unsigned(tmp_9_fu_219_p2),64)); end behav;	gpl-3.0	187253e9206afb9071db2fbd5fe49ec2	0.568416	2.883752	false	false	false	false
grwlf/vsim	vhdl_ct/ct00560.vhd	1	25,718	-- NEED RESULT: ARCH00560: Variable declarations - composite dynamic subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00560 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (12) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00560) -- ENT00560_Test_Bench(ARCH00560_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.test_report ; -- architecture ARCH00560 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is variable correct : boolean := true ; -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- variable va_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable va_st_string_1 : st_string := c_st_string_1 ; variable va_st_rec1_1 : st_rec1 := c_st_rec1_1 ; variable va_st_rec2_1 : st_rec2 := c_st_rec2_1 ; variable va_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable va_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable va_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable va_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and va_st_string_1 = c_st_string_1 ; correct := correct and va_st_rec1_1 = c_st_rec1_1 ; correct := correct and va_st_rec2_1 = c_st_rec2_1 ; correct := correct and va_st_rec3_1 = c_st_rec3_1 ; correct := correct and va_st_arr1_1 = c_st_arr1_1 ; correct := correct and va_st_arr2_1 = c_st_arr2_1 ; correct := correct and va_st_arr3_1 = c_st_arr3_1 ; va_st_bit_vector_1 := c_st_bit_vector_2 ; va_st_string_1 := c_st_string_2 ; va_st_rec1_1 := c_st_rec1_2 ; va_st_rec2_1 := c_st_rec2_2 ; va_st_rec3_1 := c_st_rec3_2 ; va_st_arr1_1 := c_st_arr1_2 ; va_st_arr2_1 := c_st_arr2_2 ; va_st_arr3_1 := c_st_arr3_2 ; correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and va_st_string_1 = c_st_string_2 ; correct := correct and va_st_rec1_1 = c_st_rec1_2 ; correct := correct and va_st_rec2_1 = c_st_rec2_2 ; correct := correct and va_st_rec3_1 = c_st_rec3_2 ; correct := correct and va_st_arr1_1 = c_st_arr1_2 ; correct := correct and va_st_arr2_1 = c_st_arr2_2 ; correct := correct and va_st_arr3_1 = c_st_arr3_2 ; test_report ( "ARCH00560" , "Variable declarations - composite dynamic subtypes" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00560 ; -- entity ENT00560_Test_Bench is end ENT00560_Test_Bench ; -- architecture ARCH00560_Test_Bench of ENT00560_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00560 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00560_Test_Bench ;	gpl-3.0	37d75f805176a5be69861b856e5dad18	0.548099	3.167631	false	false	false	false
grwlf/vsim	vhdl_ct/ct00180.vhd	1	43,554	-- NEED RESULT: ARCH00180.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: P6: Inertial transactions entirely completed failed -- NEED RESULT: P5: Inertial transactions entirely completed failed -- NEED RESULT: P4: Inertial transactions entirely completed failed -- NEED RESULT: P3: Inertial transactions entirely completed failed -- NEED RESULT: P2: Inertial transactions entirely completed failed -- NEED RESULT: P1: Inertial transactions entirely completed failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00180 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- PKG00180 -- PKG00180/BODY -- E00000(ARCH00180) -- ENT00180_Test_Bench(ARCH00180_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00180 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00180 ; -- package body PKG00180 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00180 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00180.all ; architecture ARCH00180 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- begin P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P1" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_r_st_arr1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P2" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_r_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P3" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_r_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- P4 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P4" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P4 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions entirely completed", chk_r_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- P5 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P5" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P5 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions entirely completed", chk_r_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- P6 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P6" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P6 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions entirely completed", chk_r_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- -- end ARCH00180 ; -- entity ENT00180_Test_Bench is end ENT00180_Test_Bench ; -- architecture ARCH00180_Test_Bench of ENT00180_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00180 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00180_Test_Bench ;	gpl-3.0	db12cdeb40b858f120285ef0da3aef90	0.4789	3.395759	false	false	false	false
grwlf/vsim	vhdl_ct/ct00551.vhd	1	25,618	-- NEED RESULT: ARCH00551: Constant declarations - composite globally static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00551 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.1 (7) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00551) -- ENT00551_Test_Bench(ARCH00551_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.test_report ; architecture ARCH00551 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is variable correct : boolean := true ; -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- constant co_bit_vector_1 : bit_vector := c_st_bit_vector_1 ; constant co_string_1 : string := c_st_string_1 ; constant co_t_rec1_1 : t_rec1 := c_st_rec1_1 ; constant co_st_rec1_1 : st_rec1 := c_st_rec1_1 ; constant co_t_rec2_1 : t_rec2 := c_st_rec2_1 ; constant co_st_rec2_1 : st_rec2 := c_st_rec2_1 ; constant co_t_rec3_1 : t_rec3 := c_st_rec3_1 ; constant co_st_rec3_1 : st_rec3 := c_st_rec3_1 ; constant co_t_arr1_1 : t_arr1 := c_st_arr1_1 ; constant co_st_arr1_1 : st_arr1 := c_st_arr1_1 ; constant co_t_arr2_1 : t_arr2 := c_st_arr2_1 ; constant co_st_arr2_1 : st_arr2 := c_st_arr2_1 ; constant co_t_arr3_1 : t_arr3 := c_st_arr3_1 ; constant co_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and co_string_1 = c_st_string_1 ; correct := correct and co_t_rec1_1 = c_t_rec1_1 ; correct := correct and co_st_rec1_1 = c_st_rec1_1 ; correct := correct and co_t_rec2_1 = c_t_rec2_1 ; correct := correct and co_st_rec2_1 = c_st_rec2_1 ; correct := correct and co_t_rec3_1 = c_t_rec3_1 ; correct := correct and co_st_rec3_1 = c_st_rec3_1 ; correct := correct and co_t_arr1_1 = c_t_arr1_1 ; correct := correct and co_st_arr1_1 = c_st_arr1_1 ; correct := correct and co_t_arr2_1 = c_t_arr2_1 ; correct := correct and co_st_arr2_1 = c_st_arr2_1 ; correct := correct and co_t_arr3_1 = c_t_arr3_1 ; correct := correct and co_st_arr3_1 = c_st_arr3_1 ; test_report ( "ARCH00551" , "Constant declarations - composite globally static subtypes" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00551 ; -- entity ENT00551_Test_Bench is end ENT00551_Test_Bench ; -- architecture ARCH00551_Test_Bench of ENT00551_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00551 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00551_Test_Bench ;	gpl-3.0	3dd8caec53fa603fb5abbc212d50d60c	0.546686	3.183151	false	false	false	false
grwlf/vsim	vhdl_ct/ct00558.vhd	1	3,218	-- NEED RESULT: ARCH00558: Variable declarations - composite static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00558 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (10) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00558) -- ENT00558_Test_Bench(ARCH00558_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00558 of E00000 is begin process variable correct : boolean := true ; variable va_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable va_st_string_1 : st_string := c_st_string_1 ; variable va_st_rec1_1 : st_rec1 := c_st_rec1_1 ; variable va_st_rec2_1 : st_rec2 := c_st_rec2_1 ; variable va_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable va_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable va_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable va_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and va_st_string_1 = c_st_string_1 ; correct := correct and va_st_rec1_1 = c_st_rec1_1 ; correct := correct and va_st_rec2_1 = c_st_rec2_1 ; correct := correct and va_st_rec3_1 = c_st_rec3_1 ; correct := correct and va_st_arr1_1 = c_st_arr1_1 ; correct := correct and va_st_arr2_1 = c_st_arr2_1 ; correct := correct and va_st_arr3_1 = c_st_arr3_1 ; va_st_bit_vector_1 := c_st_bit_vector_2 ; va_st_string_1 := c_st_string_2 ; va_st_rec1_1 := c_st_rec1_2 ; va_st_rec2_1 := c_st_rec2_2 ; va_st_rec3_1 := c_st_rec3_2 ; va_st_arr1_1 := c_st_arr1_2 ; va_st_arr2_1 := c_st_arr2_2 ; va_st_arr3_1 := c_st_arr3_2 ; correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and va_st_string_1 = c_st_string_2 ; correct := correct and va_st_rec1_1 = c_st_rec1_2 ; correct := correct and va_st_rec2_1 = c_st_rec2_2 ; correct := correct and va_st_rec3_1 = c_st_rec3_2 ; correct := correct and va_st_arr1_1 = c_st_arr1_2 ; correct := correct and va_st_arr2_1 = c_st_arr2_2 ; correct := correct and va_st_arr3_1 = c_st_arr3_2 ; test_report ( "ARCH00558" , "Variable declarations - composite static subtypes" , correct) ; wait ; end process ; end ARCH00558 ; -- entity ENT00558_Test_Bench is end ENT00558_Test_Bench ; -- architecture ARCH00558_Test_Bench of ENT00558_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00558 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00558_Test_Bench ;	gpl-3.0	857d5805ea6fdc6be3781dc55778dfb0	0.530143	2.909584	false	true	false	false
MrDoomBringer/DSD-Labs	Lab 6/sevenseg_out.vhd	1	6,255	LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY sevenseg_out IS port ( R : IN STD_LOGIC_VECTOR (7 DOWNTO 0); S : IN STD_LOGIC; HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END sevenseg_out; ARCHITECTURE derp OF sevenseg_out IS CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111"; CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111"; CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000"; CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001"; CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100"; CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000"; CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001"; CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010"; CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010"; CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000"; CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000"; CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000"; CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000"; CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011"; CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110"; CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001"; CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110"; CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110"; SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); BEGIN -- Generate a hex display display_hex : PROCESS (R) ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (7 DOWNTO 4); ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (3 DOWNTO 0); BEGIN CASE high_bit IS WHEN "0000" => HEX1_buff_hex <= hex_zer; WHEN "0001" => HEX1_buff_hex <= hex_one; WHEN "0010" => HEX1_buff_hex <= hex_two; WHEN "0011" => HEX1_buff_hex <= hex_thr; WHEN "0100" => HEX1_buff_hex <= hex_fou; WHEN "0101" => HEX1_buff_hex <= hex_fiv; WHEN "0110" => HEX1_buff_hex <= hex_six; WHEN "0111" => HEX1_buff_hex <= hex_sev; WHEN "1000" => HEX1_buff_hex <= hex_eig; WHEN "1001" => HEX1_buff_hex <= hex_nin; WHEN "1010" => HEX1_buff_hex <= hex_0xa; WHEN "1011" => HEX1_buff_hex <= hex_0xb; WHEN "1100" => HEX1_buff_hex <= hex_0xc; WHEN "1101" => HEX1_buff_hex <= hex_0xd; WHEN "1110" => HEX1_buff_hex <= hex_0xe; WHEN "1111" => HEX1_buff_hex <= hex_0xf; WHEN OTHERS => HEX1_buff_hex <= hex_blk; END CASE; CASE low_bit IS WHEN "0000" => HEX2_buff_hex <= hex_zer; WHEN "0001" => HEX2_buff_hex <= hex_one; WHEN "0010" => HEX2_buff_hex <= hex_two; WHEN "0011" => HEX2_buff_hex <= hex_thr; WHEN "0100" => HEX2_buff_hex <= hex_fou; WHEN "0101" => HEX2_buff_hex <= hex_fiv; WHEN "0110" => HEX2_buff_hex <= hex_six; WHEN "0111" => HEX2_buff_hex <= hex_sev; WHEN "1000" => HEX2_buff_hex <= hex_eig; WHEN "1001" => HEX2_buff_hex <= hex_nin; WHEN "1010" => HEX2_buff_hex <= hex_0xa; WHEN "1011" => HEX2_buff_hex <= hex_0xb; WHEN "1100" => HEX2_buff_hex <= hex_0xc; WHEN "1101" => HEX2_buff_hex <= hex_0xd; WHEN "1110" => HEX2_buff_hex <= hex_0xe; WHEN "1111" => HEX2_buff_hex <= hex_0xf; WHEN OTHERS => HEX2_buff_hex <= hex_blk; END CASE; END PROCESS display_hex; -- Generate a decimal display display_dec: PROCESS (R) ALIAS sign_bit : STD_LOGIC IS R (7); VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE r_buff : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN -- Select value to work off of IF (sign_bit='1') THEN HEX0_buff_dec <= hex_neg; r_buff := (NOT(R) + "00000001"); ELSIF (sign_bit='0') THEN HEX0_buff_dec <= hex_blk; r_buff := R; ELSE HEX0_buff_dec <= hex_blk; r_buff := "00000000"; END IF; -- Display higher digit IF (r_buff >= "00001010" AND r_buff < "00010100") THEN -- Within 10-19 HEX1_buff_dec <= hex_one; r_lower := r_buff - "00001010"; ELSIF (r_buff >= "00010100" AND r_buff < "00011110") THEN -- Within 20-29 HEX1_buff_dec <= hex_two; r_lower := r_buff - "00010100"; ELSIF (r_buff >= "00011110" AND r_buff < "00101000") THEN -- Within 30-39 HEX1_buff_dec <= hex_thr; r_lower := r_buff - "00011110"; ELSIF (r_buff >= "00101000" AND r_buff < "00110010") THEN -- Within 40-49 HEX1_buff_dec <= hex_fou; r_lower := r_buff - "00101000"; ELSIF (r_buff >= "00110010" AND r_buff < "00111100") THEN -- Within 50-59 HEX1_buff_dec <= hex_fiv; r_lower := r_buff - "00110010"; ELSIF (r_buff >= "00111100" AND r_buff < "01000110") THEN -- Within 60-69 HEX1_buff_dec <= hex_six; r_lower := r_buff - "00111100"; ELSE -- We can't have any higher values from our ALU, everything else must be zero. HEX1_buff_dec <= hex_zer; r_lower := r_buff; END IF; -- Display lower digit CASE r_lower IS WHEN "00000000" => HEX2_buff_dec <= hex_zer; WHEN "00000001" => HEX2_buff_dec <= hex_one; WHEN "00000010" => HEX2_buff_dec <= hex_two; WHEN "00000011" => HEX2_buff_dec <= hex_thr; WHEN "00000100" => HEX2_buff_dec <= hex_fou; WHEN "00000101" => HEX2_buff_dec <= hex_fiv; WHEN "00000110" => HEX2_buff_dec <= hex_six; WHEN "00000111" => HEX2_buff_dec <= hex_sev; WHEN "00001000" => HEX2_buff_dec <= hex_eig; WHEN "00001001" => HEX2_buff_dec <= hex_nin; WHEN OTHERS => HEX2_buff_dec <= hex_zer; END CASE; END PROCESS display_dec; -- Select display type for output select_display : PROCESS (S, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec) BEGIN IF (s = '0') THEN HEX0 <= hex_blk; HEX1 <= HEX1_buff_hex; HEX2 <= HEX2_buff_hex; ELSIF (s = '1') THEN HEX0 <= HEX0_buff_dec; HEX1 <= HEX1_buff_dec; HEX2 <= HEX2_buff_dec; ELSE HEX0 <= hex_blk; HEX1 <= hex_blk; HEX2 <= hex_blk; END IF; END PROCESS select_display; END derp;	mit	5f3ba47810500edcc0ba800f5131e27e	0.622542	2.645939	false	false	false	false
TWW12/lzw	ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_sim_netlist.vhdl	2	78,687	-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Mar 31 08:57:14 2017 -- Host : Shaun running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_sim_netlist.vhdl -- Design : bram_4096 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_4096_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_wrapper_init is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_02 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_03 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 4, READ_WIDTH_B => 4, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 4, WRITE_WIDTH_B => 4 ) port map ( ADDRARDADDR(13 downto 2) => addra(11 downto 0), ADDRARDADDR(1 downto 0) => B"00", ADDRBWRADDR(13 downto 0) => B"00000000000000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 4) => B"000000000000", DIADI(3 downto 0) => dina(3 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4), DOADO(3 downto 0) => douta(3 downto 0), DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ena, ENBWREN => '0', REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0101010101010101010101010101010100000000000000000000000000000000", INIT_01 => X"0303030303030303030303030303030302020202020202020202020202020202", INIT_02 => X"0505050505050505050505050505050504040404040404040404040404040404", INIT_03 => X"0707070707070707070707070707070706060606060606060606060606060606", INIT_04 => X"0909090909090909090909090909090908080808080808080808080808080808", INIT_05 => X"0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", INIT_06 => X"0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C", INIT_07 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 1) => B"000", DIPADIP(0) => dina(8), DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => douta(7 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => douta(8), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 7) => B"0000000000000000000000000", DIADI(6 downto 0) => dina(6 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6 downto 0) => douta(6 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_4096_blk_mem_gen_prim_width; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_4096_blk_mem_gen_prim_wrapper_init port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), douta(3 downto 0) => douta(3 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(6 downto 0), douta(6 downto 0) => douta(6 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_4096_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_4096_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bram_4096_blk_mem_gen_prim_width port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), douta(3 downto 0) => douta(3 downto 0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(12 downto 4), douta(8 downto 0) => douta(12 downto 4), ena => ena, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized1\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(19 downto 13), douta(6 downto 0) => douta(19 downto 13), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_4096_blk_mem_gen_top; architecture STRUCTURE of bram_4096_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_4096_blk_mem_gen_generic_cstr port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_4096_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_4096_blk_mem_gen_top port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_4096_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_4096_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_4096_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_4096_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_4096_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_4096_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_4096_blk_mem_gen_v8_3_5_synth port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_4096 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_4096 : entity is "bram_4096,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_4096 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_4096; architecture STRUCTURE of bram_4096 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_4096_blk_mem_gen_v8_3_5 port map ( addra(11 downto 0) => addra(11 downto 0), addrb(11 downto 0) => B"000000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;	unlicense	7f0367c77c32b2cad73297582534f371	0.721898	4.060636	false	false	false	false
grwlf/vsim	vhdl_ct/ct00309.vhd	1	24,615	-- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for generically sized types passed -- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for types passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00309 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.2 (1) -- 7.2.2 (2) -- 7.2.2 (6) -- 7.2.2 (9) -- 7.2.2 (10) -- 7.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00309(ARCH00309) -- GENERIC_STANDARD_TYPES(ARCH00309_1) -- ENT00309_Test_Bench(ARCH00309_Test_Bench) -- -- REVISION HISTORY: -- -- 21-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00309 is generic ( i_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; i_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; i_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; i_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; i_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; i_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; i_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; i_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; i_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; i_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; i_st_string_1 : st_string := c_st_string_1 ; i_st_string_2 : st_string := c_st_string_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00309 ; architecture ARCH00309 of ENT00309 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; variable v_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable v_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; variable v_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; variable v_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; variable v_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; variable v_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; variable v_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; variable v_st_string_1 : st_string := c_st_string_1 ; variable v_st_string_2 : st_string := c_st_string_2 ; constant c2_st_bit_vector_1 : boolean := i_st_bit_vector_1 < i_st_bit_vector_2 and i_st_bit_vector_1 <= i_st_bit_vector_2 and i_st_bit_vector_2 <= c_st_bit_vector_2 and i_st_bit_vector_2 >= i_st_bit_vector_1 and i_st_bit_vector_1 >= c_st_bit_vector_1 and i_st_bit_vector_2 > i_st_bit_vector_1 and i_st_bit_vector_1 = c_st_bit_vector_1 and i_st_bit_vector_1 /= i_st_bit_vector_2 and not (i_st_bit_vector_1 = i_st_bit_vector_2) ; constant c2_st_boolean_vector_1 : boolean := i_st_boolean_vector_1 < i_st_boolean_vector_2 and i_st_boolean_vector_1 <= i_st_boolean_vector_2 and i_st_boolean_vector_2 <= c_st_boolean_vector_2 and i_st_boolean_vector_2 >= i_st_boolean_vector_1 and i_st_boolean_vector_1 >= c_st_boolean_vector_1 and i_st_boolean_vector_2 > i_st_boolean_vector_1 and i_st_boolean_vector_1 = c_st_boolean_vector_1 and i_st_boolean_vector_1 /= i_st_boolean_vector_2 and not (i_st_boolean_vector_1 = i_st_boolean_vector_2) ; constant c2_st_enum1_vector_1 : boolean := i_st_enum1_vector_1 < i_st_enum1_vector_2 and i_st_enum1_vector_1 <= i_st_enum1_vector_2 and i_st_enum1_vector_2 <= c_st_enum1_vector_2 and i_st_enum1_vector_2 >= i_st_enum1_vector_1 and i_st_enum1_vector_1 >= c_st_enum1_vector_1 and i_st_enum1_vector_2 > i_st_enum1_vector_1 and i_st_enum1_vector_1 = c_st_enum1_vector_1 and i_st_enum1_vector_1 /= i_st_enum1_vector_2 and not (i_st_enum1_vector_1 = i_st_enum1_vector_2) ; constant c2_st_integer_vector_1 : boolean := i_st_integer_vector_1 < i_st_integer_vector_2 and i_st_integer_vector_1 <= i_st_integer_vector_2 and i_st_integer_vector_2 <= c_st_integer_vector_2 and i_st_integer_vector_2 >= i_st_integer_vector_1 and i_st_integer_vector_1 >= c_st_integer_vector_1 and i_st_integer_vector_2 > i_st_integer_vector_1 and i_st_integer_vector_1 = c_st_integer_vector_1 and i_st_integer_vector_1 /= i_st_integer_vector_2 and not (i_st_integer_vector_1 = i_st_integer_vector_2) ; constant c2_st_severity_level_vector_1 : boolean := i_st_severity_level_vector_1 < i_st_severity_level_vector_2 and i_st_severity_level_vector_1 <= i_st_severity_level_vector_2 and i_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and i_st_severity_level_vector_2 >= i_st_severity_level_vector_1 and i_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and i_st_severity_level_vector_2 > i_st_severity_level_vector_1 and i_st_severity_level_vector_1 = c_st_severity_level_vector_1 and i_st_severity_level_vector_1 /= i_st_severity_level_vector_2 and not (i_st_severity_level_vector_1 = i_st_severity_level_vector_2) ; constant c2_st_string_1 : boolean := i_st_string_1 < i_st_string_2 and i_st_string_1 <= i_st_string_2 and i_st_string_2 <= c_st_string_2 and i_st_string_2 >= i_st_string_1 and i_st_string_1 >= c_st_string_1 and i_st_string_2 > i_st_string_1 and i_st_string_1 = c_st_string_1 and i_st_string_1 /= i_st_string_2 and not (i_st_string_1 = i_st_string_2) ; begin gen_correct := gen_correct and c2_st_bit_vector_1 = true ; gen_correct := gen_correct and c2_st_boolean_vector_1 = true ; gen_correct := gen_correct and c2_st_enum1_vector_1 = true ; gen_correct := gen_correct and c2_st_integer_vector_1 = true ; gen_correct := gen_correct and c2_st_severity_level_vector_1 = true ; gen_correct := gen_correct and c2_st_string_1 = true ; dyn_correct := dyn_correct and v_st_bit_vector_1 < v_st_bit_vector_2 and v_st_bit_vector_1 <= v_st_bit_vector_2 and v_st_bit_vector_2 <= c_st_bit_vector_2 and v_st_bit_vector_2 >= v_st_bit_vector_1 and v_st_bit_vector_1 >= c_st_bit_vector_1 and v_st_bit_vector_2 > v_st_bit_vector_1 and v_st_bit_vector_1 = c_st_bit_vector_1 and v_st_bit_vector_1 /= v_st_bit_vector_2 and not (v_st_bit_vector_1 = v_st_bit_vector_2) ; dyn_correct := dyn_correct and v_st_boolean_vector_1 < v_st_boolean_vector_2 and v_st_boolean_vector_1 <= v_st_boolean_vector_2 and v_st_boolean_vector_2 <= c_st_boolean_vector_2 and v_st_boolean_vector_2 >= v_st_boolean_vector_1 and v_st_boolean_vector_1 >= c_st_boolean_vector_1 and v_st_boolean_vector_2 > v_st_boolean_vector_1 and v_st_boolean_vector_1 = c_st_boolean_vector_1 and v_st_boolean_vector_1 /= v_st_boolean_vector_2 and not (v_st_boolean_vector_1 = v_st_boolean_vector_2) ; dyn_correct := dyn_correct and v_st_enum1_vector_1 < v_st_enum1_vector_2 and v_st_enum1_vector_1 <= v_st_enum1_vector_2 and v_st_enum1_vector_2 <= c_st_enum1_vector_2 and v_st_enum1_vector_2 >= v_st_enum1_vector_1 and v_st_enum1_vector_1 >= c_st_enum1_vector_1 and v_st_enum1_vector_2 > v_st_enum1_vector_1 and v_st_enum1_vector_1 = c_st_enum1_vector_1 and v_st_enum1_vector_1 /= v_st_enum1_vector_2 and not (v_st_enum1_vector_1 = v_st_enum1_vector_2) ; dyn_correct := dyn_correct and v_st_integer_vector_1 < v_st_integer_vector_2 and v_st_integer_vector_1 <= v_st_integer_vector_2 and v_st_integer_vector_2 <= c_st_integer_vector_2 and v_st_integer_vector_2 >= v_st_integer_vector_1 and v_st_integer_vector_1 >= c_st_integer_vector_1 and v_st_integer_vector_2 > v_st_integer_vector_1 and v_st_integer_vector_1 = c_st_integer_vector_1 and v_st_integer_vector_1 /= v_st_integer_vector_2 and not (v_st_integer_vector_1 = v_st_integer_vector_2) ; dyn_correct := dyn_correct and v_st_severity_level_vector_1 < v_st_severity_level_vector_2 and v_st_severity_level_vector_1 <= v_st_severity_level_vector_2 and v_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and v_st_severity_level_vector_2 >= v_st_severity_level_vector_1 and v_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and v_st_severity_level_vector_2 > v_st_severity_level_vector_1 and v_st_severity_level_vector_1 = c_st_severity_level_vector_1 and v_st_severity_level_vector_1 /= v_st_severity_level_vector_2 and not (v_st_severity_level_vector_1 = v_st_severity_level_vector_2) ; dyn_correct := dyn_correct and v_st_string_1 < v_st_string_2 and v_st_string_1 <= v_st_string_2 and v_st_string_2 <= c_st_string_2 and v_st_string_2 >= v_st_string_1 and v_st_string_1 >= c_st_string_1 and v_st_string_2 > v_st_string_1 and v_st_string_1 = c_st_string_1 and v_st_string_1 /= v_st_string_2 and not (v_st_string_1 = v_st_string_2) ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait; end process ; end ARCH00309 ; architecture ARCH00309_1 of GENERIC_STANDARD_TYPES is begin B : block generic ( i_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; i_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; i_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; i_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; i_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; i_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; i_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; i_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; i_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; i_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; i_st_string_1 : st_string := c_st_string_1 ; i_st_string_2 : st_string := c_st_string_2 ) ; begin process variable bool : boolean := true ; variable gen_correct, dyn_correct : boolean := true ; variable v_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable v_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; variable v_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; variable v_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; variable v_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; variable v_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; variable v_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; variable v_st_string_1 : st_string := c_st_string_1 ; variable v_st_string_2 : st_string := c_st_string_2 ; constant c2_st_bit_vector_1 : boolean := i_st_bit_vector_1 < i_st_bit_vector_2 and i_st_bit_vector_1 <= i_st_bit_vector_2 and i_st_bit_vector_2 <= c_st_bit_vector_2 and i_st_bit_vector_2 >= i_st_bit_vector_1 and i_st_bit_vector_1 >= c_st_bit_vector_1 and i_st_bit_vector_2 > i_st_bit_vector_1 and i_st_bit_vector_1 = c_st_bit_vector_1 and i_st_bit_vector_1 /= i_st_bit_vector_2 and not (i_st_bit_vector_1 = i_st_bit_vector_2) ; constant c2_st_boolean_vector_1 : boolean := i_st_boolean_vector_1 < i_st_boolean_vector_2 and i_st_boolean_vector_1 <= i_st_boolean_vector_2 and i_st_boolean_vector_2 <= c_st_boolean_vector_2 and i_st_boolean_vector_2 >= i_st_boolean_vector_1 and i_st_boolean_vector_1 >= c_st_boolean_vector_1 and i_st_boolean_vector_2 > i_st_boolean_vector_1 and i_st_boolean_vector_1 = c_st_boolean_vector_1 and i_st_boolean_vector_1 /= i_st_boolean_vector_2 and not (i_st_boolean_vector_1 = i_st_boolean_vector_2) ; constant c2_st_enum1_vector_1 : boolean := i_st_enum1_vector_1 < i_st_enum1_vector_2 and i_st_enum1_vector_1 <= i_st_enum1_vector_2 and i_st_enum1_vector_2 <= c_st_enum1_vector_2 and i_st_enum1_vector_2 >= i_st_enum1_vector_1 and i_st_enum1_vector_1 >= c_st_enum1_vector_1 and i_st_enum1_vector_2 > i_st_enum1_vector_1 and i_st_enum1_vector_1 = c_st_enum1_vector_1 and i_st_enum1_vector_1 /= i_st_enum1_vector_2 and not (i_st_enum1_vector_1 = i_st_enum1_vector_2) ; constant c2_st_integer_vector_1 : boolean := i_st_integer_vector_1 < i_st_integer_vector_2 and i_st_integer_vector_1 <= i_st_integer_vector_2 and i_st_integer_vector_2 <= c_st_integer_vector_2 and i_st_integer_vector_2 >= i_st_integer_vector_1 and i_st_integer_vector_1 >= c_st_integer_vector_1 and i_st_integer_vector_2 > i_st_integer_vector_1 and i_st_integer_vector_1 = c_st_integer_vector_1 and i_st_integer_vector_1 /= i_st_integer_vector_2 and not (i_st_integer_vector_1 = i_st_integer_vector_2) ; constant c2_st_severity_level_vector_1 : boolean := i_st_severity_level_vector_1 < i_st_severity_level_vector_2 and i_st_severity_level_vector_1 <= i_st_severity_level_vector_2 and i_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and i_st_severity_level_vector_2 >= i_st_severity_level_vector_1 and i_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and i_st_severity_level_vector_2 > i_st_severity_level_vector_1 and i_st_severity_level_vector_1 = c_st_severity_level_vector_1 and i_st_severity_level_vector_1 /= i_st_severity_level_vector_2 and not (i_st_severity_level_vector_1 = i_st_severity_level_vector_2) ; constant c2_st_string_1 : boolean := i_st_string_1 < i_st_string_2 and i_st_string_1 <= i_st_string_2 and i_st_string_2 <= c_st_string_2 and i_st_string_2 >= i_st_string_1 and i_st_string_1 >= c_st_string_1 and i_st_string_2 > i_st_string_1 and i_st_string_1 = c_st_string_1 and i_st_string_1 /= i_st_string_2 and not (i_st_string_1 = i_st_string_2) ; begin dyn_correct := dyn_correct and v_st_bit_vector_1 < v_st_bit_vector_2 and v_st_bit_vector_1 <= v_st_bit_vector_2 and v_st_bit_vector_2 <= c_st_bit_vector_2 and v_st_bit_vector_2 >= v_st_bit_vector_1 and v_st_bit_vector_1 >= c_st_bit_vector_1 and v_st_bit_vector_2 > v_st_bit_vector_1 and v_st_bit_vector_1 = c_st_bit_vector_1 and v_st_bit_vector_1 /= v_st_bit_vector_2 and not (v_st_bit_vector_1 = v_st_bit_vector_2) ; dyn_correct := dyn_correct and v_st_boolean_vector_1 < v_st_boolean_vector_2 and v_st_boolean_vector_1 <= v_st_boolean_vector_2 and v_st_boolean_vector_2 <= c_st_boolean_vector_2 and v_st_boolean_vector_2 >= v_st_boolean_vector_1 and v_st_boolean_vector_1 >= c_st_boolean_vector_1 and v_st_boolean_vector_2 > v_st_boolean_vector_1 and v_st_boolean_vector_1 = c_st_boolean_vector_1 and v_st_boolean_vector_1 /= v_st_boolean_vector_2 and not (v_st_boolean_vector_1 = v_st_boolean_vector_2) ; dyn_correct := dyn_correct and v_st_enum1_vector_1 < v_st_enum1_vector_2 and v_st_enum1_vector_1 <= v_st_enum1_vector_2 and v_st_enum1_vector_2 <= c_st_enum1_vector_2 and v_st_enum1_vector_2 >= v_st_enum1_vector_1 and v_st_enum1_vector_1 >= c_st_enum1_vector_1 and v_st_enum1_vector_2 > v_st_enum1_vector_1 and v_st_enum1_vector_1 = c_st_enum1_vector_1 and v_st_enum1_vector_1 /= v_st_enum1_vector_2 and not (v_st_enum1_vector_1 = v_st_enum1_vector_2) ; dyn_correct := dyn_correct and v_st_integer_vector_1 < v_st_integer_vector_2 and v_st_integer_vector_1 <= v_st_integer_vector_2 and v_st_integer_vector_2 <= c_st_integer_vector_2 and v_st_integer_vector_2 >= v_st_integer_vector_1 and v_st_integer_vector_1 >= c_st_integer_vector_1 and v_st_integer_vector_2 > v_st_integer_vector_1 and v_st_integer_vector_1 = c_st_integer_vector_1 and v_st_integer_vector_1 /= v_st_integer_vector_2 and not (v_st_integer_vector_1 = v_st_integer_vector_2) ; dyn_correct := dyn_correct and v_st_severity_level_vector_1 < v_st_severity_level_vector_2 and v_st_severity_level_vector_1 <= v_st_severity_level_vector_2 and v_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and v_st_severity_level_vector_2 >= v_st_severity_level_vector_1 and v_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and v_st_severity_level_vector_2 > v_st_severity_level_vector_1 and v_st_severity_level_vector_1 = c_st_severity_level_vector_1 and v_st_severity_level_vector_1 /= v_st_severity_level_vector_2 and not (v_st_severity_level_vector_1 = v_st_severity_level_vector_2) ; dyn_correct := dyn_correct and v_st_string_1 < v_st_string_2 and v_st_string_1 <= v_st_string_2 and v_st_string_2 <= c_st_string_2 and v_st_string_2 >= v_st_string_1 and v_st_string_1 >= c_st_string_1 and v_st_string_2 > v_st_string_1 and v_st_string_1 = c_st_string_1 and v_st_string_1 /= v_st_string_2 and not (v_st_string_1 = v_st_string_2) ; if gen_correct and dyn_correct then work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , true ) ; else work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , false ) ; end if ; wait; end process ; end block ; end ARCH00309_1 ; use WORK.STANDARD_TYPES.all ; entity ENT00309_Test_Bench is end ENT00309_Test_Bench ; architecture ARCH00309_Test_Bench of ENT00309_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT end component ; component UUT_1 port ( locally_static_correct, globally_static_correct, dynamic_correct : out boolean ) ; end component ; for CIS2 : UUT_1 use entity WORK.ENT00309 ( ARCH00309 ) ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00309_1 ) ; begin CIS2 : UUT_1 port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; CIS1 : UUT ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for types" , true ) ; end if ; end process ; end block L1 ; end ARCH00309_Test_Bench ;	gpl-3.0	18edeae7454528277a0040e720f0b3fa	0.520455	3.298271	false	false	false	false
progranism/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_fwft_ext_as.vhd	9	12,637	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RvP9zZHkeFP18wLlGgDfVe/DTwIyMP7dhvzgCxp5m3YYL/LPCO9ICc+LBKqhQGhkjW48xpBAGwp3 rBBSE8qK6w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Qh1YkIKhLAJw+T0XBKcVE5CFy7U9clrK+8m4T/x0yjOoagdJeeO9PlbMa8zDeYYoZZutG5tu4t0N sS2pvvQBM2LCvmWTcVG3LWECd1SoSHNd1Q6UbLR4rRzrlUIDN4/JUR9PWghJqqumcUUJxnx5knEi K7afdfP3GWpa+Mc54+8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HhfJKJ7YjkLmM42nTlzlQdDAF0pHVZnxLAjs72tXPKfyr7K5syerWW1IxhILiZNM2A0cNOUuK1B8 3pAH/L4JIt1TVyRIV84DJ8CQly1B9HRzFyS98BKzUfjErddgSfzRoWts821YG5qRykFYzVy0JSNW Ragz33rrmmL7qwMoZDWEs40RddcGX9de4kYYJLuItLwkKCeuM+I1G4CDXKEueQ5u6LQ93N2lQnas nPqBrP8n3BEnbThXBdK1yg3hcWqeBMMV3uoyqi+DrjDYmFIVQeHVKMb7fDMmbeiNu+e1+hNugM7Q zuV0EDd3VBu5V4gC82AsbfxPzRb2dPjR2bGkJA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block r+ZA+Oj7YdWnX06D5ZqZqXmUolmi4IW3cJCjO5tbt4FUt2NRQKFRaPVa/OzCRO98jZcUAZnOrsQs Rep+1VM+AH7vO0AlpTwL2YQWhQIRDtPP4l7hvmAW2QqsKSPWDbymkELktbLs6z2QWa6KZT127iXh ieyHXY4cnV7w42J65Do= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tEVWrDxJT9dKo2YC8zO/ut+oDpg3zkEfgzRECtcSkT6P2lC2McwywkyNOqCk/pmUPQ4bCYcOEOvI jUK+HW4ZZSod7UJE4eE4llpWX07n8fHKwMRVLxvYuhUZ9T0douxC3Lt0fXzC85NJTyJkGimu9KjD 6StBQXytAUuaDDuiaVXVLzHavnShPhHlIbufuZ5VdmuStq9zhYgYirOxIgWll7ywfvt6pWGt6w8p vRlZPnsBCK53+Du8/VX674tC+XGMKo3ahf5CvdS1v1bXUIITFznP1EPny1sPqbe8Z3AmcS4i9zBH 4q/viijyABREqAn303FRoDoAgPOHPMNMgH0nSQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7616) `protect data_block 2jcCW+L/DvZCppgVQq4J4wutN6bK0k6sf58j6Lv8ThwnWKdPBHykU8TGeWX/oWZAwjvz3s87ex1k bw4N3UjDvtfIJZd3xIN1FYC/uWK14Wpia0QJcWqRZp1JtQZsa4gRlgj9wa8mgg/zRb5m72JiU94x SSWVYvuYNxDqJVEWaqcczadPYste5BXE/2QpAyKn/7IzlZCuPa6dIxOCZwq6xAkjZsci4VLJGbmQ oAG3dFsy3DMeFso3O6D9TqLo2YB84+Qjvrfvl8dY/hA6Q30pIvfG7n2NjRkSwX/AEGGdT9QqcfXS VXXZ6EZP1kB95H3HfU8txXxsOK6SqmLOX5F+ZpfXbUpk2XIg0aTDmFTCh1oZpPh7v/HzkFCkRbua HRIhUA2WbVMAQdMtZskmOhC9bwrAZygUHitK5aF+AVwh+dj+eMHDsaNX0UdJ5YE/Vi+dABiLQTLZ UD+DqppmBcCeVc2PWKX3c3T4uj69tXUUi2+S1ry/SZ3QYnErV0m4kPJ7wDOeYRowi5sR+TmHs5WX N9fl/U525IQ1SKefJcGzZY20lKIw22u2U0Q78Bh2nA+rSC2389mIqlr9+V7fRoD5KtIudes+2dpU oB6ISciLiDR+4tDIYvGIKglveO7yTdPvrsIAZLyXeptSD9bRqLeGK/Jdi/Lxs3GVDNkwKFpnHWUH zMvXGQhn6Mn+7dsWlEiI+JWhx8Cx84OPJMPd7aKDVQ4lWr5pJuSikoGDWci4WsOak22ItiaiGVxd IdQoQDDCcTZdw4nYLNuF2Pi5cdCO44aZOwkYc6dRx7Oiovr9nE2B2Ez1EiAU+2g4kqBhJadvq9Od AKtQAmUgRhnmSTdE4mI59hlb5fqw176y/Wf5Eq29RIICCo78oVF78cg77As4ruHyM0HECgatqr/Q jXEK07Rf7MBxCnIn8O/vBoPF5LzpWdNnY3K+K3pVCqLAK/yHI95wk5PehM/1U8YsMwEEvOydgOsZ Ewg2vULvLOOD6pRLRBnv/YyqUrUt6r/W+uKJU58l49TwVuca+C7gnQaMm/f5+zAyb1Dq6qfjIUAA F/1ew6rhvSLCfnybzH8ogDNVGAA+n5EAXM3TW+ZXLMIorvYolagYtQTKoXuv566378DJ9rd7YtQ1 k0f1uLPYdsmwWnHf1PUXgtqbazg/7CyQ5Z1TH9/LbsavboKJhBcmZg/z/iKqKqxDqY/YlnewnpGi grIrQtSfjd3UCA2zYh+sX7j3yqpJBjYTczbtikToJfAvrGvz2fUbOIELJuzu7BgLbJP0JXQpDPnL TpJLn3w51SoMhavMlriwyzUw1vKOJHxR19aXRrw9xcXxsSNOV5E3RVDhJXo1qAr7as41lo1WpTun Xl+XLvvbDVm8EjORRkGR/yLUXd/qyF+SqRmFqi41HnZeD/13h776RLJoLlbq3a3hXVRmQLqxEfCc mdrPpVupdmJePPle+WgJwl07+k83Le1ptMGIvqhzt2Jr291KhwmjnN52iMHHdThJusX+spyLOnfI UftQMGUdYRz8kUFbA8ySA+qEwJ04R+L2Obz16ypAbk8tvSd+FBDjuIlUBFB03d5dzbt5ftvRNDuF NEbeEq4Zs/V3ThL6RjQtGMs9GSs1FTMjIpwgKj9V3BsjxuDzxh4NSjSK8OMFTOtCUp1SrdPbdfmP kQKucCOCcQ6sImTtSwbxxCk1LM24RjfOelWq6P8qL91x1opsNG3iJDPg1UZLTftDoiQgLwubRwiA KGNv3931ePmLSnhBsAidFuvpYBWN6/jIi+3UfIP/fhOZcur6hTAdyC7x46GWZc3P8T2ovd7hW1Zq cfO4/LBrasj5CEInfzB8xkU09aO4/NzmboRi1ni5Ns93GtFKfB4TpyjoAE1beFsMtdHr/Yy7YoZF Rha3YZR+Sw5mg9+k8u8amFOge3Nh9obV5RsiR64zRNAAB8qG0eBwg7m4eC/oy+eSBwGA3hwF+Jpm SOnBRf51kNUTiiccT82rgBX/d//HheB2mwwjjXa/q2YIghTMrileyFWLLmbuWi6fvixYFgwkUw3F XpUj0x0VS84PD/ycCc1TK1o9sglLJDGuQdUdyjoF68rrEkszaVkzgQBGyqS1iKmLwW+l/HM8gn5M C8AqrR1MBk3Grzu7z37esWFCexgj04ZsOJmQSVqij/lTn7akIV9xWhOswVYS9IpUb1u/VaBRUn2v XxgwND1YWGDddlVCT9yeyaQkl26Xal2lQ0lEpt7ap+ujvW6d37OXNKYfYFvXQjtv2YCsR7qdqJE0 fydRm8Yx0DeV1ycivwsHOLDO56D04jUsP42nEIwy1KzdIIGw4Sp9S35hPTdpJg9tLinjJrXXh6lz Mv2NW4bnVV4s68aBJSczcn0o/u6QjRAYaKyz16Kbemy2Gheb9IblySfQGlq1wQaOlK9v7nPc+p2I bDTKS8uwpxvHbkPOto6hjsol5gnEtwzCQEnxq3tkxQDLDmtjxLr4dk4soliG8o8AxmOn2pjRViKf vwLax4S+dZQeWurHBAhCQDlHvVe/oH/CoJreik0CdcCFdQ0sWMAIUUqT9pPCz/dRcFAjpWkcS1cl 3tO+I+gz9wZxPUkBbitQQhhcYbOzAFn5slMyMK6r7SGP9fPuod3hOhvaiUQpUne8PXCsjo+IidDe VuKHXnA2g5neyNcytXcF+pZQdODJUk3QvmqgbEVR85W8SA4kKl30f6m3vbWEqgpN9k7KdoLgYNdr oKnuX4mWnNLcvjY1/9fN0i+f9o1rpfEWH9nGBcvgtDM46uIFTamhSw6QSDBLDVvfJ4DyHa+Qv5pe 7Rhb6tRe/4hdjLvOL6HYD2+EvZMlqs+EY3MDW0tuPl786imA3c32yNp6C4OUxE6Oum+bcot2553s BK6HiyHlk1WRjVCSRH52XIrbBwdbuQzPbiwTWZkWx3U0wpbN4y1TXghxUwu+gELQRua3xNzUwb2T eyvljjTTqyLP1uffHYRhK+Wi7mZjkVJcOFSSMwYNPMiNbrxCUZLNWROEkVdG/3A+TcnyyghufgGa 8qgtwsG/0NbYLTqKp8u1jiTBxPdNdZYu0WSsbhoT9XAeslNvaK69E5Ahgy6UabTX74aNTAuftvnx KsxftpvyCAb61pb4Quueeu3AovJx7QJaR2HG1J7ZP1JkSXRWtkWIiLJ1K1hUEdccUAbegz8qBNrb FNb31mLqvLWu3M8faMXljV3G/c5B7/HrsNNyP6HC2wleINwIPKiCpw965AZU+6Mb2SRVmp8b2KKe gc+RaYvqvMXb8Vdd5b8yb7F7JrgwjRWTuddPc+B+p+Xce0Gmw0s/6Dp32JySDyuoqa/1N5gjgX+6 sm/RW5DPmGxwhzvlKLr3a4k3ka+0BFjh/Sl+KY290r8gvZWVjN743Iypp1JcySAY+DAPsuke/XS1 kMm//TrOo/NqXBhSOxY/JO+9ZAyY8kodCY9gR/kby2Fmbj8LNiPsEm68xpSZ3VePr1CGn9hv5HBp 66ZlQgvSqC9mZGtFcy3/Pm7kvpWy9lwEEzhdgigtxJbz9CxoCJDF16QEbM3DrqUJ8d274ORk4BUn lbpjT8ppFbKFe98+JPRDBWubf5nEfYE92bx+HRL6tV7BVPspK0G3ui75IrzlAks2qghzp4YDbmbR O4mjW5hoOrmFccE+ER80bm7+EOGsWFZkkceZyR/P08PwHRXyGyEjfinTZHv4Rcbb6in3sh63lv+W Oeg+Mxq3608Yy69/O4i6NEk1uo+xAPwi2ZzhL5usNici0OPxdXy5mi3f1ofKlY1M3MsXugit74zY /C/P/bm5tSzkEcIYS4SQG6n0BqDaKDAuTm3qGkMu8Sgpx4wdX+77f6wL2bL3fKyIO95BOxNfWzda 6huflNkOBTRNFzU8Ytq7GuJyzNFJmOQN38b13/Vqvy7f5xpP2e5CoOT0CsGr78iQbW2QFrSlA/dR tmiKHtND5SHoe9OQgHE5xd2KjwbP6GhPIVHh0XAzO4ipCwks/s88wwr4+s5nUvmCUIQGWjCAt6T7 HWRsqbfvhJcGtSRiwwh3dqoOp4o/HFi7DJWJzfL7sinYVUECEfc2kf3Zy1Joh5cseTcLEjwXwVF/ i9FoUSkm7/+qRYORq4R4bHgmZKrOtjaeuyqKLAS2skM7CMVDlsgu4RkkzIgUWzlPFL8OqJ/D7aog SjzQRb0t6eDTBowoDjz9k/P4ZTWhQQpM7lSqS64Pe50RkLtEWXq0d1ihQtopB89R1T7pNY83O5jP iQb3bXJ4l8QAq38/yY6lCmNd7uDHUepn+P1ogwHuSrNtPeS6zEbclAxlctMaUZxX0J4gZlTBHDP+ kuhk6/Xq3O9OFjBSRV3uwNAb16Vtkx4heN9HKRidu+NyApK4l/SaxLbDPweNbcGl5AgBUKYHJx67 od5ubtUyPn1zfDZ/+9o+6Mam2f8eZX3zR04yDK2Bn1RbKrkEOYi+M4IetO4vVRpo3BnxdDOMmgyt M8Jm66UHlyRZl38cv7ypGbXtg7C8MlBgoHjA7Z++K3wQjLR71/Mz8VCwvvIXrmh5+iw3zdn0Gxmp QNBjFwtpBMQ0v1WHlcR6vRF59UR+YJx7nJuQaQSC62sL6bQDgNY4fXLzYL6MBpIBuZojxkyQvaL2 QLhyuEOyqbLMRyPsKb1DFVmgkqJs8b3SHJHhJCWp0OSm9eqHx61BOI/eQncNqGi5mHM34raCChwM MKCwl55zaMxNqac5qcivBkFLU+5YP90n+6Rjne9jvJmgXpsE2jeVmv3yaAcoOIFNLXZtnnXPBElv oHYTU5jreVYgg5aFtbFrrJjZBIY9cDl6GQfaV5qygpC34pdNBq66BCvMgf3zV14YXW1Qdw/0PaoA C4ByIv3mApntVAM6MSZ02S0rJ0OY5fGHDRDPFvrSy/eTdkDu3WN49CJx4xBfvjzwIgxQ18My9VtZ XPToQi4A5Un+P7n0qCHHYhGeOiSzqdoQa88688FN2OIvJY38R473eaTB7a6RP54PVbO4ZFee9Vlx 8jgOmmOIHTaBCAhTsZEJFW+ZRXxnxlxK+ScHGyCvsc/fLEZv3WKfFcO+eY45+zcrcSM+kqTdD2+y 0XoJu09U215jhRBNn11xOlvG2/9QaQqoF7PxfgIF+Z7HXhPth34/1Ampj+ZkFt96OUd3+PcxTKZR n0tgjMLYOe+Vxj11a3erduEkfxmjI1/BIh0XgDoh/YMhUcjEA1TIqkZGBhkiJSAZGO2wPrcRAE/G XlC+h9ADyPZ/HFO9+3JZyUElgpWJp7uP3LnK6BUsaa5aJo967mimc0Il1h9CC9y4ZDxI3tR0LLEP fsG8M0ddvGzUCKtVy9ZQArfD/BIBJTytCKj3JqWlruVF8m5s1C7q4VZEnA8mkIpQt3C75avulq14 dfZQ4VT+X5qpbYrk0fr26RlaUVkoi8gjjjkKK17DwClbctWNuClqYyARzRe+XGEqzzPD2LMvpYB9 dkZK5mbiDcZ5q5TUtZ0JT8YwO1xewBkw0U0TsnPc40Bg3AFBSBfICHoyvXUx/2i4uwCbuZ1rkmKV yJq+IXAzns+Rjrn5cbEpGLPUb5sBl4yzvR47Hw7h2l37kR+WjnQOWszgJR9EhkrSf2e3le69w5a1 y+kV69ZZAngIrxnO7tLGU7DAMZpP2HK1rcNJGHEVeV6Cju9S3De8wLfAoC4xk/u+p0mJBVfgiTZZ F+QJu71hNcjaGjmM7j9+yNiKtJxkv12M789f4JYnTr3/c0MsjGFbpGdg9doIoOACa09JxwmWDnjB XjYMPmEmQ9Pn70cMfljCllX2yIOTMOL/qden1Kr/r5yJLtk/gk/mF3e3DFxOSoz+6noNymev+cff 9DcseFJzE6OIldIQ+LzERegLilWDL7y5Cq/E0ydC9JnOopTycKwEmFlXQ93i3MA/bEyD0MPj+BCb cFLXXzysXUXuvr4DZUpybPsg8CxqVOPLIx80TtX6/37vd2rW4ekW14qeCuku/yP+65IHq/TVC/Cj Vj7/DdF65N76BVLsGDpyBF5M3iCRT7r4YljfMJh50XJmq1fGoM00qWj79DBBSu8ftjnYAM1aR236 mulXHJ2SmlR90UH76HiT7PZlXXnKF6Hw27+D651R+gS1uOoFCslQ9OGyt4x0tnoWSfUHTx9JsOu2 JCEJir/6U+0/4yhiv3qCQ4f2C07eTcRXcDKoz2WPUjTPM1G10wKYlsk1wu0fOQTGxfTXKvfSlRUZ JpkJobML3PFQbVCvjp87iOquOAaercevWvm63OldH8zG6PkE945z4JalO3BMu18jQhtC8MAlyg1w GYr8y5mMKf50nQ6arz/Yw2o4E1xAVazf/qVq8T1PEsz0TEryPOwsPRCgY4VAPAj+jV84kT+Y2tDq ZQmNetcpmFPVP1CByMxWN/BDuGeeiGMLHuVTLn9WATHuEqHsZ1LpaMLrQ47/6qGUp/OsXoXe8RWa Nk31dn9aSH8C8DOfLwO1WFomw14anVsj87QjfPR0r7493P/p0UiKdlMdciJ15OnBKWo7nKlHYtQV ADjjBUqE7/AHU2KtFNiJLEuxIJf3YsE73YSnRkRvw6xay8w2HDt7x3VV+yblvuYa/tOwoBZg0+/B UWFGhnc+JsSyB8ekofCoFWL9+th9bO6GxwBG7rdVFFvii4kfizqpLw07FrolhDRWMHIQPPA7JyR2 b7+hgf9wyg2gzbtRJbyvxuWYbF5ozIt7Zn6/koxNTptHa+EA8qDZeb0FfPSPjv7/GvRp/5Xz6l+z h6oDm92kPpH45ZTKgSV1bezTuW8vhxewANStDXOxTq1XX53HrDsLy5gY4HDs2xERFWu2eA2zmlW/ dg8QI778WGPjg+G13BGZy24xcplZCk350AXq5X4P5d0cIL2JmvonhS4MVyezvKGW5rfmABwNz+sf 7Dz2RaS7ol1anJvEIsUn6qD+onThNZ3di9xJ2ZCEb/+CJ05JMf4kDlLiqlcRe5OQDO2/1iI6htd6 ipHPGnqptn4/KpiX2EgYZx8GURGXaVdnQ7R8G8ddqGny95dRLrg4MOU2dHUI3MX72n1nB6gG0kye 5x+BgbISrtcFmHiJzdnhtHjKJ4nvLf8QOAGlZCImCO+jYYQJO6AcAn6lB3pfAxN6TkgXMswp8w6l NfGoZVp/ET1L5YmdKYIxHmVpyAxyuujm/Py8kr4DxmrSSOCYiD9SwFuqijoawS2RrtenAwTKwVtG fPhGl//TiqYV8tmR1yIp/ZQIsRch6VnvU9ZIIuT06mdz3QBGbXwNLlD/5L6IDv5LF88cITIsjKgB OZSJptDMbDc0xo412ndW7OaFFLDA2R1ehD0G9AbNfDEU9666YHBgd5bETI5WhP1D1ogHabQgi8p+ vWWeePzDo8Me7B0U0SHfpD+34VmiMNCVtJdbuO9EAHbHlwZWer+XSK/YFkwr6mBCGINyiprqmBLj ptXCGCbleiLqLAZ2u+XrBFa3h9iMSg9oN8kqVgEBQ2cAC9criFJSnBGWGkES4YcLJt0LTaf3UNDG 9hIpFe7agmPGZ6uadZjWcvmKYk9EKdQcNThCkggLDEAbMPFSVxMRHpVNS6GORghGz5EYeMwoPGMj z/PZ8y6TAdfk+9kUA5jFepmnf+xrb6isVp9CuYkZtyUaWVg/Np++IovUDvM0e1wGALXmg9BU6Mh6 p0EHNZtM7Wic8T5xXseGXC24RgV+9f9XPhzJGxcU1L4Fqsu/GSv4dKayW/09r5jDVNVilygQFjue RMJtpYRrbsTUFSH1e92EDVlQihnQkleIOCitVFonrfJi8MMHKo2WjqehApZB4fTKNFb2i87pDVG5 ulZLWq6oISzvLHNSNscJvtU+lp/SOCypMY4kNpDbJV7OxL7X9lxwOuMjxgxN+dzfchQV/5lAvIA0 Ymdu4svqA9C1p++AYyuJrPLI3BTaVyqNfu70cV25lSQ+//6PaDOC+h7zfHDNL6DibA6BB+QNYYOy Eg7Sdv2Fl904BigcCBN0t97FenAb4mzugpUJwqeOEXgdKQLsAazkN+jwZ6IK1UzrDOFmKIJ9wXb4 I4qE01km5sQPEMrqAJ00c/aTU3pCzXFu3cIJhO4/q5s2pMe4v0A+o/XQUxTj83K3xJsndKtkbdvK kMGWBI+ZPdI/7awmr/hb4rEoQ9woB1vtlQBfrpbK7iujvt/1rBUzwptUkqVeC0S6wz6R2yMn1CQO 58pS0iMjaIwQpXO3yFIwA6rlY+UYVveuYqeWjIr+AGiI2zxGcMDh5nUIqEN41aBP/5wBmS2fvEfZ P+ukmpQ6WUAEgL8AfTrJd9OXveaNyzxia0/f7mQddohWtouzlsesa5JXF1b1i7WSZLF72CqjcY+T 7kPs7j8BvaUBJRGxuZRZsJ94fkDpnkp1DupQdBJ71BHKTT0cZXCSDON1Wy2fi43eZgGbk3eTzY7d ouIPJ/HdNj6SWxlZ1y4tOXarSvJ4oFSObFy3qxaFEfhRs3HEEZ1bJH2zXtrfXfo0nSKmQKcnFkYa YsEsBqp69EeLzzGq9WKJYaZENvZ0nUK4wqYbjDxa/kfE3QJg0tVVbP++7EontrlggWAqoTgupJCl v/em7+DwY6AzBeARJZgkgd94cCAKpuDeTKOXSyLTgjgTVXC6OFVjiC/NiVl383XALXPfMiAVWmTS CIPfDMuHi+mWbz+ibjreZ6O7yqk4XYFmY2gTnTfbsCmCWY1HBiEiycuzV7Nka3YP0/p+3zsUKfhz KZWXcb6g7AH1JuOb/kj2ReGRwU3bRglImeoNbBY+KBJInVWFaxU2vKhYXjUAhr7306cGvx12uAOe YlDCjXJBvJHDaC5Va91usjE95f4LE15fznn8LDKavOhUp8Vr8NBoOyaM7V5jl4LpJKYUlnpsTh1k 4AKlzwHltc8MY1y1ZpRpLaISYaxGidjB7kYyNc4d+cO9C4r4Dy8hVE8LX/7rnt/JMoRHQO/wzVIG /ubRPRu88MJbzP/N9oYGsy8s+VxmyJo4/nX0ILFdfmUUS1hR2uDzjQB0o+TopNDK8GTx3cfN+VMf UUpSSSOhAR0Mm4uFdZoig1KoJZG2bJThbf4YeeIDih556GoELYeiOvz+W/q7ySGWe3kTioA8ZB8o AedcChGtD2DXTYAjyu64KPpRczdi6zoHujMcQPl1mErZfZ/S+uXA3RHCTPgSbTz35pkSovNvI9YV i8Qyvzv8S5NlJ/9FvXBfSgdZSiCRMFaseMfdq5IJnLoP56cIJBbZ6hi/gDiFRGXufHdvBX8cvLmv J4Jo0enwPaW1Y0jzZhKjuO595EtZEC4JTDMywXaN1h/ZmV9c3xFVBVEP4Lmc6rtEzamG6zswBpX1 M8mwMoL7q+xlRfvVKjAOxdPyyThThRyAdukCkAepnQIjtWyPv03yIAPoR5esQvX/dfrDiPjR9FYS jth9Q4Yx/3hVMljTaMBgRK9uZBN+3T71+BJG8z+eiuTy5ok5Yk6UKW10l6HYMcrLeiZcL/k5YLak OzBSET/V4jtz137N7HIeX2+jW9mY2FdHf2mcKN7lav1CHfwRVGh13IMYekF1hYMFHEBVsfUaMXKd Ex63u8vW4pWSSnuwmLL95MovthUP/qxGonzATwNsMZ2+N5j+usG20Jetox4ANXkNsISlz+8F5r+v V8lGPfWJnu6Jh9Y0+EfJ25HUv+H+OdDUXWmvoF7MsVCAgQSzloyRux7ktXtcNgzqfgMyRolYcqQ3 /7S53ODH5nLt5SJhDIo7XX+oNUmv4qmg1t/YzXYuHa59OfTKGeXHv1BkbQkIhBV3rhE6eVMss6JN GiiRS4TLLZkoy66kW2CPPagAowE6jDdSc/WXQS8mMiVC7TbMmqn9ABdLX8I+CcRRNmxHhHNkvwso ea8jdY1LTuSC5Lp65/pAJ4sw8mrYZJ+hy8oG+xiXVPWN9MzYvY3VctdNgBFoodECBebkSL98q+Bd o2PqMTYpdhW/GrZYE2lE/QMeLuiZkv3dweY3Y7woW9P+yQ56koCaPMcjAm8A8VeIgHdumeFaYu8X 3xoBR/xkVWTNjmO3A1buPxQRz+qh0EAqruYeTw/BDG6rIjSSCuwSV+pIomH1u1L5Rip5ymsrmH6j s0F1hmnIjG+uMN4oqQIMKqKelpYFFLaSgypytcJMmfhq69U= `protect end_protected	gpl-3.0	093f2fd8cd5c5d41004cd41270887e5f	0.927831	1.881346	false	false	false	false
grwlf/vsim	vhdl_ct/pro000028.vhd	1	1,711	-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Scherbinin. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type use work.std_logic_1164_for_tst.all; entity test_generate is generic(N:natural:=8); port ( in_bit : in bit; out_bit : out bit ); end entity test_generate; architecture test_generate_arch of test_generate is signal tst_signal : bit := '0'; signal tst_vector : bit_vector(0 to N-1):=('0','0','0','0','0','0','0','0'); begin tst_signal <= '1'; G2: if (N > 5) generate tst_vector(7) <= '1'; tst_vector(6) <= '1'; end generate G2; validate_g1: process (tst_vector) is variable i : bit; begin i := tst_signal; assert ( ( (tst_vector(6) = '1') and (tst_vector(7) = '1') and i='1' ) or i = '0') report "PRO000028: failure: wrong value." severity ERROR; end process validate_g1; end architecture test_generate_arch; entity ENT00028_Test_Bench is end ENT00028_Test_Bench; architecture ARCH00028_Test_Bench of ENT00028_Test_Bench is signal input, output : bit; begin input <= not input after 10 ns; test_entity: entity work.test_generate port map ( in_bit => input, out_bit => output ); end ARCH00028_Test_Bench ;	gpl-3.0	5bddff71c5d9ae9bafde840a3fc6c772	0.573349	3.32233	false	true	false	false
grwlf/vsim	vhdl_ct/ct00121.vhd	1	32,105	-- NEED RESULT: ARCH00121.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00121 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00121 -- PKG00121/BODY -- ENT00121(ARCH00121) -- ENT00121_Test_Bench(ARCH00121_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00121 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00121 ; -- package body PKG00121 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00121 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00121.all ; entity ENT00121 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_r_st_arr1_vector : inout r_st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_r_st_arr2_vector : inout r_st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_r_st_arr3_vector : inout r_st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_r_st_rec1_vector : inout r_st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_r_st_rec2_vector : inout r_st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_r_st_rec3_vector : inout r_st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- -- end ENT00121 ; -- architecture ARCH00121 of ENT00121 is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_r_st_arr1_vector, counter, correct, savtime, chk_r_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_r_st_arr2_vector, counter, correct, savtime, chk_r_st_arr2_vector ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_r_st_arr3_vector, counter, correct, savtime, chk_r_st_arr3_vector ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_r_st_rec1_vector, counter, correct, savtime, chk_r_st_rec1_vector ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_r_st_rec2_vector, counter, correct, savtime, chk_r_st_rec2_vector ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_r_st_rec3_vector, counter, correct, savtime, chk_r_st_rec3_vector ) ; end process P6 ; -- -- end ARCH00121 ; -- entity ENT00121_Test_Bench is end ENT00121_Test_Bench ; -- architecture ARCH00121_Test_Bench of ENT00121_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00121 ( ARCH00121 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00121_Test_Bench ;	gpl-3.0	40002ca8c1af7c7264c629d8c11a66eb	0.530073	3.350553	false	false	false	false
wsoltys/AtomFpga	src/AtomGodilVideo/src/MINIUART/utils.vhd	1	4,039	------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : utils.vhd -- Author : Philippe CARTON -- ([email protected]) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164 ------------------------------------------------------------------------------- -- Description: VHDL utility file ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- 1.0 Philippe CARTON 19 December 2001 New model -- [email protected] ------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Synchroniser: -- Synchronize an input signal (C1) with an input clock (C). -- The result is the O signal which is synchronous of C, and persist for -- one C clock period. -------------------------------------------------------------------------------- library IEEE,STD; use IEEE.std_logic_1164.all; entity synchroniser is port ( C1 : in std_logic;-- Asynchronous signal C : in std_logic;-- Clock O : out std_logic);-- Synchronised signal end synchroniser; architecture Behaviour of synchroniser is signal C1A : std_logic; signal C1S : std_logic; signal R : std_logic; begin RiseC1A : process(C1,R) begin if Rising_Edge(C1) then C1A <= '1'; end if; if (R = '1') then C1A <= '0'; end if; end process; SyncP : process(C,R) begin if Rising_Edge(C) then if (C1A = '1') then C1S <= '1'; else C1S <= '0'; end if; if (C1S = '1') then R <= '1'; else R <= '0'; end if; end if; if (R = '1') then C1S <= '0'; end if; end process; O <= C1S; end Behaviour; ------------------------------------------------------------------------------- -- Counter -- This counter is a parametrizable clock divider. -- The count value is the generic parameter Count. -- It is CE enabled. (it will count only if CE is high). -- When it overflow, it will emit a pulse on O. -- It can be reseted to 0. ------------------------------------------------------------------------------- library IEEE,STD; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Counter is port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset input CE : in std_logic; -- Chip Enable Count : in std_logic_vector (15 downto 0); -- Count revolution O : out std_logic); -- Output end Counter; architecture Behaviour of Counter is begin counter : process(Clk,Reset) variable Cnt : unsigned (15 downto 0); begin if Reset = '1' then Cnt := unsigned(Count); O <= '0'; elsif Rising_Edge(Clk) then if CE = '1' then if Cnt = 1 then O <= '1'; Cnt := unsigned(Count); else O <= '0'; Cnt := Cnt - 1; end if; else O <= '0'; end if; end if; end process; end Behaviour;	apache-2.0	5f89ee4c61a48031eac992732b9b4b51	0.416192	4.40458	false	false	false	false
jairov4/accel-oil	solution_virtex5/syn/vhdl/sample_iterator_next.vhd	2	14,025	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_req_din : OUT STD_LOGIC; indices_req_full_n : IN STD_LOGIC; indices_req_write : OUT STD_LOGIC; indices_rsp_empty_n : IN STD_LOGIC; indices_rsp_read : OUT STD_LOGIC; indices_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_datain : IN STD_LOGIC_VECTOR (55 downto 0); indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0); indices_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end; architecture behav of sample_iterator_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111"; constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal i_sample_read_reg_147 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_read_reg_153 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_153_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_153_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal indices_samples_load_new5_reg_165 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_7_fu_67_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_cast_fu_91_p1 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_9_fu_94_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_cast_fu_88_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_s_fu_104_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_9_fu_94_p2_temp: signed (17-1 downto 0); signal tmp_s_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_fu_115_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_fu_110_p2 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_index_write_assign_fu_128_p3 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_sample_write_assign_fu_120_p3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_index_read_reg_153_pp0_it1 <= i_index_read_reg_153; ap_reg_ppstg_i_index_read_reg_153_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it1; ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 <= i_sample_read_reg_147; ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_147_pp0_it1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_index_read_reg_153 <= i_index; i_sample_read_reg_147 <= i_sample; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_load_new5_reg_165 <= indices_datain(47 downto 32); end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; agg_result_index_write_assign_fu_128_p3 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it2 when (tmp_s_fu_104_p2(0) = '1') else tmp_2_fu_110_p2; agg_result_sample_write_assign_fu_120_p3 <= tmp_1_fu_115_p2 when (tmp_s_fu_104_p2(0) = '1') else ap_const_lv16_0; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return_0 <= agg_result_index_write_assign_fu_128_p3; ap_return_1 <= agg_result_sample_write_assign_fu_120_p3; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; indices_address <= tmp_7_fu_67_p1(32 - 1 downto 0); indices_dataout <= ap_const_lv56_0; indices_req_din <= ap_const_logic_0; -- indices_req_write assign process. -- indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_req_write <= ap_const_logic_1; else indices_req_write <= ap_const_logic_0; end if; end process; -- indices_rsp_read assign process. -- indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_rsp_read <= ap_const_logic_1; else indices_rsp_read <= ap_const_logic_0; end if; end process; indices_size <= ap_const_lv32_1; tmp_1_fu_115_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2) + unsigned(ap_const_lv16_1)); tmp_2_fu_110_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_index_read_reg_153_pp0_it2) + unsigned(ap_const_lv16_1)); tmp_7_fu_67_p1 <= std_logic_vector(resize(unsigned(i_index),64)); tmp_8_cast_fu_91_p1 <= std_logic_vector(resize(unsigned(indices_samples_load_new5_reg_165),17)); tmp_9_fu_94_p2 <= std_logic_vector(unsigned(tmp_8_cast_fu_91_p1) + unsigned(ap_const_lv17_1FFFF)); tmp_cast_fu_88_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2),18)); tmp_9_fu_94_p2_temp <= signed(tmp_9_fu_94_p2); tmp_s_fu_104_p1 <= std_logic_vector(resize(tmp_9_fu_94_p2_temp,18)); tmp_s_fu_104_p2 <= "1" when (signed(tmp_cast_fu_88_p1) < signed(tmp_s_fu_104_p1)) else "0"; end behav;	lgpl-3.0	b1f8b83a63add65cdca1453f50c077cb	0.606061	2.734984	false	false	false	false
jairov4/accel-oil	solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/sample_buffer_if_ap_fifo.vhd	3	2,817	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sample_buffer_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of sample_buffer_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;	lgpl-3.0	2ae093c6da3dfbc4baa7d4fc5acfa911	0.495918	3.682353	false	false	false	false
grwlf/vsim	vhdl_ct/ct00580.vhd	1	3,924	-- NEED RESULT: ARCH00580: Check involving overloading context rule 1 passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00580 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.5 (1) -- -- DESIGN UNIT ORDERING: -- -- PKG00580 -- PKG00580/BODY -- ENT00580_Test_Bench(ARCH00580_Test_Bench) -- -- REVISION HISTORY: -- -- 20-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- package PKG00580 is type COLOR is (RED, YELLOW, GREEN, BROWN, TAN, WHITE, BLUE) ; type LIGHTS is (RED, YELLOW, GREEN, BROWN, TAN, WHITE, BLUE) ; function F1 (A : COLOR := RED; B : LIGHTS := RED) return COLOR; function F1 (A : LIGHTS := BLUE; B : COLOR := BLUE) return LIGHTS; function "+" ( L,R : COLOR ) return COLOR ; function "+" ( L,R : LIGHTS ) return LIGHTS ; end PKG00580 ; package body PKG00580 is function F1 (A : COLOR := RED; B : LIGHTS := RED) return COLOR is variable RESULT : COLOR := RED; begin if (A /= RED) and (B /= BLUE) then RESULT := COLOR'PRED (A) ; return RESULT ; else return GREEN; end if; end F1; function F1 (A : LIGHTS := BLUE; B : COLOR := BLUE) return LIGHTS is variable RESULT : LIGHTS := RED; begin if (A /= RED) and (B /= BLUE) then RESULT := LIGHTS'PRED (A) ; return RESULT ; else return GREEN; end if; end F1; function "+" ( L,R : COLOR ) return COLOR is begin return COLOR'Val ((COLOR'Pos (L) + COLOR'Pos (R)) mod 7) ; end "+" ; function "+" ( L,R : LIGHTS ) return LIGHTS is begin return LIGHTS'Val (COLOR'Pos (COLOR'Val (LIGHTS'Pos (L)) + COLOR'Val (LIGHTS'Pos (R)) ) ) ; end "+" ; end PKG00580 ; use WORK.STANDARD_TYPES.all ; use WORK.PKG00580.all ; entity ENT00580_Test_Bench is end ENT00580_Test_Bench ; architecture ARCH00580_Test_Bench of ENT00580_Test_Bench is begin L1 : block constant CC1 : COLOR := F1 ; -- set to GREEN constant LC1 : LIGHTS := F1 ; -- set to GREEN constant CC2 : COLOR := F1 (COLOR'(GREEN)) ; -- set to YELLOW constant LC2 : LIGHTS := F1 (LIGHTS'(GREEN)) ; -- set to GREEN constant CC3 : COLOR := F1 (B => BLUE) ; -- set to GREEN constant LC3 : LIGHTS := F1 (B => BLUE) ; -- set to GREEN constant CC4 : COLOR := COLOR'(YELLOW) + COLOR'(GREEN) ; -- set to BRO constant LC4 : LIGHTS := LIGHTS'(YELLOW) + LIGHTS'(GREEN) ; -- set to BRO constant CC5 : COLOR := COLOR'(YELLOW) + BROWN ; -- set to TAN constant LC5 : LIGHTS := LIGHTS'(YELLOW) + BROWN ; -- set to TAN constant CC6 : COLOR := YELLOW + TAN ; -- set to WHITE constant LC6 : LIGHTS := YELLOW + TAN ; -- set to WHITE begin process begin test_report ( "ARCH00580" , "Check involving overloading context rule 1" , (CC1 = GREEN) and (LC1 = GREEN) and (CC2 = YELLOW) and (LC2 = GREEN) and (CC3 = GREEN) and (LC3 = GREEN) and (CC4 = BROWN) and (LC4 = BROWN) and (CC5 = TAN) and (LC5 = TAN) and (CC6 = WHITE) and (LC6 = WHITE) ) ; wait ; end process ; end block L1 ; end ARCH00580_Test_Bench ; --	gpl-3.0	8d7619007d9500070c7b89602947919b	0.47579	3.57377	false	true	false	false
wsoltys/AtomFpga	src/AVR8/Memory/XDM16Kx8.vhd	1	2,069	--********************************************************************************************** -- 16Kx8(16 KB) DM RAM for AVR Core(Xilinx) -- Version 0.2 -- Designed by Ruslan Lepetenok -- Modified 30.07.2005 --******************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For Synplicity Synplify --library virtexe; --use virtexe.components.all; -- Aldec library unisim; use unisim.vcomponents.all; entity XDM16Kx8 is port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(13 downto 0); din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); we : in std_logic ); end XDM16Kx8; architecture RTL of XDM16Kx8 is type RAMBlDOut_Type is array(2(address'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector(2(address'length-9)-1 downto 0); signal cp2n : std_logic; signal gnd : std_logic; begin gnd <= '0'; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0'; end generate ; RAM_Inst:for i in 0 to 2(address'length-9)-1 generate RAM_Byte:component RAMB4_S8 port map( DO => RAMBlDOut(i)(7 downto 0), ADDR => address(8 downto 0), DI => din(7 downto 0), EN => ce, CLK => cp2, WE => WEB(i), RST => gnd ); end generate; -- Output data mux dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9))); end RTL;	apache-2.0	7605d54cbb6046b6502815ab1c95a842	0.444176	3.896422	false	false	false	false
wsoltys/AtomFpga	src/AVR8/Memory/prog_mem_init.vhd	1	69,846	-- VHDL initialization records. -- -- Release 11.1i - Data2MEM L.33, build 1.5.8 Jul 23, 2008 -- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -- -- Command: C:\Users\ZBAND0~1\AppData\Local\Temp\build5746311222132730322.tmp\data2mem.exe -bm bitstreams/custom_bd.bmm -bd out.mem -o h E:\Papilio\Cores\GadgetFactory_Arduino_Timer_Counter\AVR8_SoftCore_TimerCounter_SPI\sources\Memory\prog_mem_init.vhd -- -- Created on 11/24/12 01:13 pm, from: -- -- Map file - bitstreams\custom_bd.bmm -- Data file(s) - out.mem -- -- Address space 'avrmap.rom_code' [0x00000000:0x00003FFF], 16384 bytes in size. -- -- Bus width = 16 bits, bit lane width = 16 bits, number of bus blocks = 8. library ieee; use ieee.std_logic_1164; package prog_mem_init_pkg is -- BRAM 0 in address space [0x00000000:0x000007FF], bit lane [15:0] -- INST PM_Inst/RAM_Word0 LOC = RAMB16_X0Y4; constant PM_Inst_RAM_Word0_INIT_00 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C0098940C"; constant PM_Inst_RAM_Word0_INIT_01 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C"; constant PM_Inst_RAM_Word0_INIT_02 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C1644940C00C7940C1539940C"; constant PM_Inst_RAM_Word0_INIT_03 : bit_vector(0 to 255) := x"000000280022003100340037003A0000005C222A2C3B5D5B2F3F3D2B5E3E3C7C"; constant PM_Inst_RAM_Word0_INIT_04 : bit_vector(0 to 255) := x"010101010101002000210030003300360039000000270023003200350038003B"; constant PM_Inst_RAM_Word0_INIT_05 : bit_vector(0 to 255) := x"0505050505050404040404040404030303030303030302020202020202020101"; constant PM_Inst_RAM_Word0_INIT_06 : bit_vector(0 to 255) := x"2010080402018040201008040201804020100804020106060606060606060505"; constant PM_Inst_RAM_Word0_INIT_07 : bit_vector(0 to 255) := x"0000000000008040201008040201804020100804020180402010080402018040"; constant PM_Inst_RAM_Word0_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000005000001000000000000"; constant PM_Inst_RAM_Word0_INIT_09 : bit_vector(0 to 255) := x"E6A0E011BFCDBFDEE0DFEFCFBE1F241116DD1193000000000000000000000000"; constant PM_Inst_RAM_Word0_INIT_0A : bit_vector(0 to 255) := x"E014BE1BF7C907B131A2F3C89631920D95D8C004BF0B9503EF0FE3F2E1E2E0B0"; constant PM_Inst_RAM_Word0_INIT_0B : bit_vector(0 to 255) := x"1901940E2FEC2FFD9722C005E0D1E3C0E011F7E107B131AB921DC001E0B1E1A2"; constant PM_Inst_RAM_Word0_INIT_0C : bit_vector(0 to 255) := x"9001918DC0042FB92FA82FF72FE60000940C1907940C170E940EF7C107D132CC"; constant PM_Inst_RAM_Word0_INIT_0D : bit_vector(0 to 255) := x"9508E0808385E186F02030672FF92FE895080B991B88F7C840505041F4211980"; constant PM_Inst_RAM_Word0_INIT_0E : bit_vector(0 to 255) := x"E090C002FD22B14DB98D7F8CB18D9A70C0019870F4113066C002FD60E0302F26"; constant PM_Inst_RAM_Word0_INIT_0F : bit_vector(0 to 255) := x"93DF93CF931F930F92FF9508E081B98D2B892B8470812F8295279536E092C001"; constant PM_Inst_RAM_Word0_INIT_10 : bit_vector(0 to 255) := x"C008E081F4113F8FB18FCFFE9B77B8FF94FA24FF2FD72FC61581940E2F172F06"; constant PM_Inst_RAM_Word0_INIT_11 : bit_vector(0 to 255) := x"2FF92FE8950890FF910F911F91CF91DFE080F388077117600B7D1B6C1581940E"; constant PM_Inst_RAM_Word0_INIT_12 : bit_vector(0 to 255) := x"2F84B96F2FB92FA8950815FC940EE06181842FF92FE8950815FC940EE0608184"; constant PM_Inst_RAM_Word0_INIT_13 : bit_vector(0 to 255) := x"96324F3F5F2EB98F8181CFFE9B77B98F8180CFFE9B77E030E0202FF92FE82F95"; constant PM_Inst_RAM_Word0_INIT_14 : bit_vector(0 to 255) := x"B98FEF8FCFFE9B77B98FEF8FCFFE9B77B98FEF8FCFFE9B77F78907383020E082"; constant PM_Inst_RAM_Word0_INIT_15 : bit_vector(0 to 255) := x"2F8A9715938C9615E1819508E081F4113085718F971A938C961AB18FCFFE9B77"; constant PM_Inst_RAM_Word0_INIT_16 : bit_vector(0 to 255) := x"2F172F061581940E2FD92FC893DF93CF931F930F92FF9508E0800125940E2F9B"; constant PM_Inst_RAM_Word0_INIT_17 : bit_vector(0 to 255) := x"B18FCFFE9B77B8FFC00CE08FF0104071526D0B711B601581940EC00994FA24FF"; constant PM_Inst_RAM_Word0_INIT_18 : bit_vector(0 to 255) := x"91CF91DFE0800125940E2F9D2F8C838DE08DC007E081F4113F8EF3813F8F878A"; constant PM_Inst_RAM_Word0_INIT_19 : bit_vector(0 to 255) := x"EF4F8538812FB98FEF8FF0D12388818E2FD92FC893DF93CF950890FF910F911F"; constant PM_Inst_RAM_Word0_INIT_1A : bit_vector(0 to 255) := x"CFFE9B77832F8738F3A84092508197012F932F824F3F5F2FB94FCFFE9B77C003"; constant PM_Inst_RAM_Word0_INIT_1B : bit_vector(0 to 255) := x"2FC893DF93CF931F930F92FF92EF92DF950891CF91DF821E0125940E2F9D2F8C"; constant PM_Inst_RAM_Word0_INIT_1C : bit_vector(0 to 255) := x"E071E26C2F9D2F8C011E940E2F9D2F8C0194940E2F152F042EF32EE22ED62FD9"; constant PM_Inst_RAM_Word0_INIT_1D : bit_vector(0 to 255) := x"95B6C0042E022D8E2D9F2FA02FB1E030E128CFFE9B77B98F64802D8D00FB940E"; constant PM_Inst_RAM_Word0_INIT_1E : bit_vector(0 to 255) := x"F41120DDF75907383F28EF8F40305028CFFE9B77B98FF7D2940A9587959795A7"; constant PM_Inst_RAM_Word0_INIT_1F : bit_vector(0 to 255) := x"CFFE9B77B92FEF2FE090CFFE9B77B98FEF8FC001E887F41116D8E088C006E985"; constant PM_Inst_RAM_Word0_INIT_20 : bit_vector(0 to 255) := x"92DF92CF950890DF90EF90FF910F911F91CF91DF878AF7C15091C002FF87B18F"; constant PM_Inst_RAM_Word0_INIT_21 : bit_vector(0 to 255) := x"055115412ED32EC22F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF"; constant PM_Inst_RAM_Word0_INIT_22 : bit_vector(0 to 255) := x"2F8CF7D1952A1F111F001CFF0CEEE029F0393083858BC03DE182F41105710561"; constant PM_Inst_RAM_Word0_INIT_23 : bit_vector(0 to 255) := x"2D4CEF6E2F9D2F8CC026E084F011238801B8940E2D2E2D3F2F402F51E1682F9D"; constant PM_Inst_RAM_Word0_INIT_24 : bit_vector(0 to 255) := x"2F8CC013E185F411238800FB940EE072E5682F9D2F8CF0F12388012C940E2D5D"; constant PM_Inst_RAM_Word0_INIT_25 : bit_vector(0 to 255) := x"2388B18FCFFE9B77B98FEF8FF439238801B8940EE050E040E030E020E06D2F9D"; constant PM_Inst_RAM_Word0_INIT_26 : bit_vector(0 to 255) := x"90CF90DF90EF90FF910F911F91CF91DFE0800125940E2F9D2F8C838DE184F081"; constant PM_Inst_RAM_Word0_INIT_27 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928FCFF1E0810125940E2F9D2F8C9508"; constant PM_Inst_RAM_Word0_INIT_28 : bit_vector(0 to 255) := x"2F80C081F409051115012E932E822ED72EC62EB52EA42FD92FC893DF93CF931F"; constant PM_Inst_RAM_Word0_INIT_29 : bit_vector(0 to 255) := x"0759174881BB81AA81998188F0712388818EC073F008409250811F930F822F91"; constant PM_Inst_RAM_Word0_INIT_2A : bit_vector(0 to 255) := x"E069F0393083858B82DB82CA82B982A8F538069916888598818FF429077B076A"; constant PM_Inst_RAM_Word0_INIT_2B : bit_vector(0 to 255) := x"238801B8940E2D2A2D3B2D4C2D5DE1612F9D2F8CF7D1956A1CDD1CCC1CBB0CAA"; constant PM_Inst_RAM_Word0_INIT_2C : bit_vector(0 to 255) := x"EF8F838EE081821F8618C03FF40923880165940E2F9D2F8CC046838DE083F019"; constant PM_Inst_RAM_Word0_INIT_2D : bit_vector(0 to 255) := x"2FB12FA0838F8798F3C8059915889601B92FCFFE9B77C004EF2F8598818FB98F"; constant PM_Inst_RAM_Word0_INIT_2E : bit_vector(0 to 255) := x"4F3F5F2FB99F83801FF30FE22DFF2DEEB18FCFFE9B77C00BEF9FE030E0209711"; constant PM_Inst_RAM_Word0_INIT_2F : bit_vector(0 to 255) := x"8589832F87381F310F208538812F938C1DBF0DAEB18FCFFE9B77F390073B172A"; constant PM_Inst_RAM_Word0_INIT_30 : bit_vector(0 to 255) := x"C001E0800125940E2F9D2F8CC0060194940E2F9D2F8CF05840325020F0192388"; constant PM_Inst_RAM_Word0_INIT_31 : bit_vector(0 to 255) := x"92FF92EF9508908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE081"; constant PM_Inst_RAM_Word0_INIT_32 : bit_vector(0 to 255) := x"92BF950890EF90FF910F911F0277940EE012E000E030E0202EF32EE2931F930F"; constant PM_Inst_RAM_Word0_INIT_33 : bit_vector(0 to 255) := x"834C821D821E8619861B2EB62FD92FC893DF93CF931F930F92FF92EF92DF92CF"; constant PM_Inst_RAM_Word0_INIT_34 : bit_vector(0 to 255) := x"15D4940EE060E08C0125940E2F9D2F8C15D4940EE061818C2ED72EC61581940E"; constant PM_Inst_RAM_Word0_INIT_35 : bit_vector(0 to 255) := x"E0809870B98DE58315D4940EE061E08A15D4940EE061E08D15D4940EE061E08B"; constant PM_Inst_RAM_Word0_INIT_36 : bit_vector(0 to 255) := x"097D196C1581940EC009011E940E2F9D2F8CF7D1308A5F8FCFFE9B77B99FEF9F"; constant PM_Inst_RAM_Word0_INIT_37 : bit_vector(0 to 255) := x"878A2F1801B8940EE050E040E030E020E0602F9D2F8CC065E081F01040775D61"; constant PM_Inst_RAM_Word0_INIT_38 : bit_vector(0 to 255) := x"E080C010871BC002FF8201B8940EE050E040E031EA2AE0682F9D2F8CF7513081"; constant PM_Inst_RAM_Word0_INIT_39 : bit_vector(0 to 255) := x"858B878BE082C03DE082F0113A9A879AF7C930845F8FB19FCFFE9B77B92FEF2F"; constant PM_Inst_RAM_Word0_INIT_3A : bit_vector(0 to 255) := x"196C1581940EC0092F17E4702D012CF12CE1C00F2711270024FF24EEF0293082"; constant PM_Inst_RAM_Word0_INIT_3B : bit_vector(0 to 255) := x"2F8C01B8940EE050E040E030E020E3672F9D2F8CC024E088F01040775D61097D"; constant PM_Inst_RAM_Word0_INIT_3C : bit_vector(0 to 255) := x"2F9D2F8CF5313082858BF7112388878A01B8940E2D2E2D3F2F402F51E2692F9D"; constant PM_Inst_RAM_Word0_INIT_3D : bit_vector(0 to 255) := x"E0800125940E2F9D2F8C838DE086F041238801B8940EE050E040E030E020E36A"; constant PM_Inst_RAM_Word0_INIT_3E : bit_vector(0 to 255) := x"CFFE9B77B99FEF9FE080878BE083F4113C807C80B18FCFFE9B77B98FEF8FC01C"; constant PM_Inst_RAM_Word0_INIT_3F : bit_vector(0 to 255) := x"911F91CF91DF00D8940E2D6B2F9D2F8C0125940E2F9D2F8CF7C930835F8FB12F"; -- BRAM 0 in address space [0x00000800:0x00000FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word1 LOC = RAMB16_X0Y8; constant PM_Inst_RAM_Word1_INIT_00 : bit_vector(0 to 255) := x"E220E090E0802FB72FA62FD92FC893DF93CF950890BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word1_INIT_01 : bit_vector(0 to 255) := x"E090E680F019322EC024E040E057F7B90591308B960183201FF90FE82FFB2FEA"; constant PM_Inst_RAM_Word1_INIT_02 : bit_vector(0 to 255) := x"1754F7B923332D3095C896012FF92FE8F1091732C01AE048E05AF131305AC007"; constant PM_Inst_RAM_Word1_INIT_03 : bit_vector(0 to 255) := x"5F4F83201DF10FE42FFB2FEA5220F408318A56812F82F4A0372FF0B03221F0C0"; constant PM_Inst_RAM_Word1_INIT_04 : bit_vector(0 to 255) := x"927F926F950891CF91DF2F89E090C001E091F0193280918CE090F6C923229129"; constant PM_Inst_RAM_Word1_INIT_05 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F"; constant PM_Inst_RAM_Word1_INIT_06 : bit_vector(0 to 255) := x"C07BF40807B707A60795178489BD89AC899B898AC085F4092322812C2F172F06"; constant PM_Inst_RAM_Word1_INIT_07 : bit_vector(0 to 255) := x"8529C06A861C861B861A86198618821F821E821DF4490511050104F114E1C08A"; constant PM_Inst_RAM_Word1_INIT_08 : bit_vector(0 to 255) := x"2E952E842E732E6240504040403050219609E09085858DFB8DEA855C854B853A"; constant PM_Inst_RAM_Word1_INIT_09 : bit_vector(0 to 255) := x"090108F108E194084F5F4F4F4F3F5F2FF7D2940A9467947794879496C0042E08"; constant PM_Inst_RAM_Word1_INIT_0A : bit_vector(0 to 255) := x"1D011CF11CE19408F7D2958A94A794B794C794D6C0042ED12EC02CBF2CAE0911"; constant PM_Inst_RAM_Word1_INIT_0B : bit_vector(0 to 255) := x"838D8DB98DA8899F898EF4490551054105311521F02804D904C804B714A61D11"; constant PM_Inst_RAM_Word1_INIT_0C : bit_vector(0 to 255) := x"2D288D9B8D8A8578816F815E814DC01208D908C808B718A6C01787B883AF839E"; constant PM_Inst_RAM_Word1_INIT_0D : bit_vector(0 to 255) := x"1E9D0E8C2C912E88E085C010F431238808D108C108B108A194080F04940E2D39"; constant PM_Inst_RAM_Word1_INIT_0E : bit_vector(0 to 255) := x"910F911F91CF91DFE080C001E081871C870B86FA86E9F72104D104C104B114A1"; constant PM_Inst_RAM_Word1_INIT_0F : bit_vector(0 to 255) := x"93CFCFE6CF73F00930229508906F907F908F909F90AF90BF90CF90DF90EF90FF"; constant PM_Inst_RAM_Word1_INIT_10 : bit_vector(0 to 255) := x"8989C00AE030E020F41923880CC5940E8998858F857E856D2F462FD92FC893DF"; constant PM_Inst_RAM_Word1_INIT_11 : bit_vector(0 to 255) := x"931F930F950891CF91DF2F932F824F3E5E2CF7E1959A1F330F22E095E0302F28"; constant PM_Inst_RAM_Word1_INIT_12 : bit_vector(0 to 255) := x"E0612F912F80C03DFF878183C043F409238881842FF92FE82F192F0893DF93CF"; constant PM_Inst_RAM_Word1_INIT_13 : bit_vector(0 to 255) := x"8F8C89B589A489938982F440308281842FF12FE0F1B997002FD92FC804FF940E"; constant PM_Inst_RAM_Word1_INIT_14 : bit_vector(0 to 255) := x"27AA2F8A2F9B8DB18DA0899789868F8A8F9B899789862FF12FE08FBF8FAE8F9D"; constant PM_Inst_RAM_Word1_INIT_15 : bit_vector(0 to 255) := x"96482F9D2F8C4F7F5E6A2F7D2F6CF0619730011391F0011291E08B8C8B9D27BB"; constant PM_Inst_RAM_Word1_INIT_16 : bit_vector(0 to 255) := x"91CF91DFE080C0010C64940E8383778F81832FF12FE08B8A8B9B8D998D889509"; constant PM_Inst_RAM_Word1_INIT_17 : bit_vector(0 to 255) := x"950891CF91DFE081821CF0112388051E940E2FD92FC893DF93CF9508910F911F"; constant PM_Inst_RAM_Word1_INIT_18 : bit_vector(0 to 255) := x"D000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F"; constant PM_Inst_RAM_Word1_INIT_19 : bit_vector(0 to 255) := x"C0A1F00930819714918C96142FB92FA82ED72EC62EB52EA42EF92EE8B7DEB7CD"; constant PM_Inst_RAM_Word1_INIT_1A : bit_vector(0 to 255) := x"8483847284612DFF2DEEC097E081F41105B105A19700C0B0C09DFF81918C9613"; constant PM_Inst_RAM_Word1_INIT_1B : bit_vector(0 to 255) := x"918D965A2DBF2DAEC085F4092388044E940E2D4A2D5B2D6C2D7D2D9F2D8E8494"; constant PM_Inst_RAM_Word1_INIT_1C : bit_vector(0 to 255) := x"23880F82940E9759917C916D915D914D9656F49104D104C104B114A1975B919C"; constant PM_Inst_RAM_Word1_INIT_1D : bit_vector(0 to 255) := x"917C916D915D914D96152DBF2DAEC0428E118E108A178A162DFF2DEEC06FF409"; constant PM_Inst_RAM_Word1_INIT_1E : bit_vector(0 to 255) := x"975B91FC91ED965A2DBF2DAEC057F40923880F04940E4F3F5F2F2F3D2F2C9718"; constant PM_Inst_RAM_Word1_INIT_1F : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987817C816B815A8149"; constant PM_Inst_RAM_Word1_INIT_20 : bit_vector(0 to 255) := x"8167815681452DFF2DEEF1B123880F82940E2F9F2F8EF4B0077B076A07591748"; constant PM_Inst_RAM_Word1_INIT_21 : bit_vector(0 to 255) := x"92BD92AD96522DBF2DAEF13123880E5B940EE03FEF2FEF1FEF0F8D938D828570"; constant PM_Inst_RAM_Word1_INIT_22 : bit_vector(0 to 255) := x"2D7DF0912388051E940E2D9F2D8E938C961368809713918C9613975592DC92CD"; constant PM_Inst_RAM_Word1_INIT_23 : bit_vector(0 to 255) := x"044E940E2D9F2D8E2D462D572D682D79F420049D048C047B146A2D4A2D5B2D6C"; constant PM_Inst_RAM_Word1_INIT_24 : bit_vector(0 to 255) := x"90AF90BF90CF90DF90EF90FF910F911F91DF91CF900F900F900F900FE080C001"; constant PM_Inst_RAM_Word1_INIT_25 : bit_vector(0 to 255) := x"F00807B707A60795178489B589A4899389822DFF2DEE9508906F907F908F909F"; constant PM_Inst_RAM_Word1_INIT_26 : bit_vector(0 to 255) := x"92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922FCFDFCF44"; constant PM_Inst_RAM_Word1_INIT_27 : bit_vector(0 to 255) := x"C0EDC0D7FF80818BC0DAF4092388818C2E552E442FD92FC893DF93CF931F930F"; constant PM_Inst_RAM_Word1_INIT_28 : bit_vector(0 to 255) := x"C0BF2C752C641E3D0E2C2C312E27E0752E932E822F372F26085F184E2C5B2C4A"; constant PM_Inst_RAM_Word1_INIT_29 : bit_vector(0 to 255) := x"E0992F152F042EF32EE2818C22B322A22EB6E0612EA6EF6F855C854B853A8529"; constant PM_Inst_RAM_Word1_INIT_2A : bit_vector(0 to 255) := x"1D5F0D4E8D758D648D538D42F44930828DFB8DEAF7D1959A94E794F795079516"; constant PM_Inst_RAM_Word1_INIT_2B : bit_vector(0 to 255) := x"F4490551054105311521F4D920DDF4E904B114A120DE94DA80D4C0411F711F60"; constant PM_Inst_RAM_Word1_INIT_2C : bit_vector(0 to 255) := x"2D222F9F2F8E8578816F815E814DC00D87B883AF839E838D8DB98DA8899F898E"; constant PM_Inst_RAM_Word1_INIT_2D : bit_vector(0 to 255) := x"40704060405050428578816F815E814D8DFB8DEAC080F40923880F04940E2D33"; constant PM_Inst_RAM_Word1_INIT_2E : bit_vector(0 to 255) := x"1F7B1F6A1F590F4889B189A085978586F7D2940A1F771F661F550F44C0048405"; constant PM_Inst_RAM_Word1_INIT_2F : bit_vector(0 to 255) := x"818B2ED92EC8F410059715862CD72CC6099B198AE092E0801D711D611D510D4D"; constant PM_Inst_RAM_Word1_INIT_30 : bit_vector(0 to 255) := x"00FC91B000FB91A000FA919000F99180C080F00906D8E08216C8E080C006FD86"; constant PM_Inst_RAM_Word1_INIT_31 : bit_vector(0 to 255) := x"2CF92CE82D1D2D0C2D3B2D2A0315919003149180C072F409077B076A07591748"; constant PM_Inst_RAM_Word1_INIT_32 : bit_vector(0 to 255) := x"2DA81D5D0D4C2F532F424F3E5E2C2D3B2D2AC0161C9D0C8CF19123880277940E"; constant PM_Inst_RAM_Word1_INIT_33 : bit_vector(0 to 255) := x"E0402D3D2D2C1E9F0E8E0BF31BE2F7D907F517E4938D9181C0022FF32FE22DB9"; constant PM_Inst_RAM_Word1_INIT_34 : bit_vector(0 to 255) := x"1461087D186C87BC87AB879A87891FB51FA41F930F8285BC85AB859A8589E050"; constant PM_Inst_RAM_Word1_INIT_35 : bit_vector(0 to 255) := x"90EF90FF910F911F91CF91DF2F952F84EF5FEF4FC0022D552D44CF3DF0090471"; constant PM_Inst_RAM_Word1_INIT_36 : bit_vector(0 to 255) := x"88CC88BB88AA9508902F903F904F905F906F907F908F909F90AF90BF90CF90DF"; constant PM_Inst_RAM_Word1_INIT_37 : bit_vector(0 to 255) := x"0BA0099F198E2D8A2D9B2DAC2DBDE050E0402F352F24851C850B84FA84E988DD"; constant PM_Inst_RAM_Word1_INIT_38 : bit_vector(0 to 255) := x"23880CC5940EE0402F642F752F862F97CEFCCEF9F40807B507A4079317820BB1"; constant PM_Inst_RAM_Word1_INIT_39 : bit_vector(0 to 255) := x"2ED92EC8B7DEB7CD920F93CF93DF931F930F92FF92EF92DF92CFCFC3CF95F009"; constant PM_Inst_RAM_Word1_INIT_3A : bit_vector(0 to 255) := x"E0414F7F5F6F2F7D2F6C2D9D2D8C8514850384F284E1F080308281842FF92FE8"; constant PM_Inst_RAM_Word1_INIT_3B : bit_vector(0 to 255) := x"90EF90FF910F911F91DF91CF900F2F932F82E030E020F07197010662940EE050"; constant PM_Inst_RAM_Word1_INIT_3C : bit_vector(0 to 255) := x"87B487A3879287811DB11DA1964F85B485A3859285812DFD2DEC950890CF90DF"; constant PM_Inst_RAM_Word1_INIT_3D : bit_vector(0 to 255) := x"F7E195EA1F330F22E0E5E0302F28708F2D8EF7D195FA94E794F795079516E0F5"; constant PM_Inst_RAM_Word1_INIT_3E : bit_vector(0 to 255) := x"2FE6C045F0092388818C2F172F062FD92FC893DF93CF931F930FCFD44F3E5E2C"; constant PM_Inst_RAM_Word1_INIT_3F : bit_vector(0 to 255) := x"0F88E045E0B0E0A08D918D808E198E188A1F8A1E838CE082F4B1318089872FF7"; -- BRAM 0 in address space [0x00001000:0x000017FF], bit lane [15:0] -- INST PM_Inst/RAM_Word2 LOC = RAMB16_X0Y1; constant PM_Inst_RAM_Word2_INIT_00 : bit_vector(0 to 255) := x"2FF72FE6838CE083F5413280C0188BBD8BAC8B9B8B8AF7D1954A1FBB1FAA1F99"; constant PM_Inst_RAM_Word2_INIT_01 : bit_vector(0 to 255) := x"0FE8940E2F912F804F3F5E2E2F3D2F2C8F798F688B5F8B4E8D758D648D538D42"; constant PM_Inst_RAM_Word2_INIT_02 : bit_vector(0 to 255) := x"861E861D861C861B861A86198618821F821E821D838BE0818F0A8F1BF0912388"; constant PM_Inst_RAM_Word2_INIT_03 : bit_vector(0 to 255) := x"2F142FD92FC893DF93CF931F9508910F911F91CF91DFE080C0018A198A18861F"; constant PM_Inst_RAM_Word2_INIT_04 : bit_vector(0 to 255) := x"C057F00974822F84F021718185834FFE5EECF7E1957A1FFF0FEEE075E0F02FE6"; constant PM_Inst_RAM_Word2_INIT_05 : bit_vector(0 to 255) := x"E0A0899589848BB887AF879E878D00FC91B000FB91A000FA919000F991808B69"; constant PM_Inst_RAM_Word2_INIT_06 : bit_vector(0 to 255) := x"8F688B5F8B4E2B7B2B6A2B592B48E0B0E0A08D938D82274427552F792F68E0B0"; constant PM_Inst_RAM_Word2_INIT_07 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A8DB78DA68D958D84F451970070907188E09085838F79"; constant PM_Inst_RAM_Word2_INIT_08 : bit_vector(0 to 255) := x"2F81838CE084F0D123880FE8940E8D9B8D8A4F3F5E2E2F3D2F2CF5219740C00D"; constant PM_Inst_RAM_Word2_INIT_09 : bit_vector(0 to 255) := x"2F9D2F8CC00AE081C002FD16861C861B861A86198618821F821E821D838B708F"; constant PM_Inst_RAM_Word2_INIT_0A : bit_vector(0 to 255) := x"2FD92FC893DF93CF9508911F91CF91DFE080C0010580940EE070E060E050E040"; constant PM_Inst_RAM_Word2_INIT_0B : bit_vector(0 to 255) := x"899F898EF0A123881061940EE070E060E050E0418D9B8D8A4F3F5F2B2F392F28"; constant PM_Inst_RAM_Word2_INIT_0C : bit_vector(0 to 255) := x"6880818B8FB98FA88B9F8B8E85B881AF819E818DF45905B105A197008DB98DA8"; constant PM_Inst_RAM_Word2_INIT_0D : bit_vector(0 to 255) := x"92DF92CF92BF92AF929F928F927F925F924F923F922F950891CF91DFE081838B"; constant PM_Inst_RAM_Word2_INIT_0E : bit_vector(0 to 255) := x"835E2F072F162ED92EC8B7DEB7CDD000D000D00093CF93DF931F930F92FF92EF"; constant PM_Inst_RAM_Word2_INIT_0F : bit_vector(0 to 255) := x"2DFD2DECC1B1C191FF81918C9613C195F00930819714918C96142FB92FA8834D"; constant PM_Inst_RAM_Word2_INIT_10 : bit_vector(0 to 255) := x"940E2D9D2D8CF03907B707A60795178485B485A3859285818975896489538942"; constant PM_Inst_RAM_Word2_INIT_11 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DACC132803E802D2E532E422F302F21C17AF4092388044E"; constant PM_Inst_RAM_Word2_INIT_12 : bit_vector(0 to 255) := x"EF7F2278947A8074F7D1951A9587959795A795B6E0192F822F932FA42FB5975B"; constant PM_Inst_RAM_Word2_INIT_13 : bit_vector(0 to 255) := x"914D96152DBD2DACC053F00904911481C057F0092077229322822E97E0712E87"; constant PM_Inst_RAM_Word2_INIT_14 : bit_vector(0 to 255) := x"97002DA091BC900D919D918D9656F48905710561055115419718917C916D915D"; constant PM_Inst_RAM_Word2_INIT_15 : bit_vector(0 to 255) := x"4F3F5F2F2F3D2F2C2F9F2F8EC03587B083A7839683852DFD2DECF17905B105A1"; constant PM_Inst_RAM_Word2_INIT_16 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DAC815C814B813A8129C12EE050E040F41923880F04940E"; constant PM_Inst_RAM_Word2_INIT_17 : bit_vector(0 to 255) := x"074A07391728E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987975B"; constant PM_Inst_RAM_Word2_INIT_18 : bit_vector(0 to 255) := x"E08087508347833683252DFD2DECC105F439238808AC940E2D9D2D8CF038075B"; constant PM_Inst_RAM_Word2_INIT_19 : bit_vector(0 to 255) := x"975B91FC91ED965A2DBD2DAC2EB92EA8F410059315822CB32CA209991988E092"; constant PM_Inst_RAM_Word2_INIT_1A : bit_vector(0 to 255) := x"C00484051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E9718911C910D90FD90ED9615"; constant PM_Inst_RAM_Word2_INIT_1B : bit_vector(0 to 255) := x"1CF10CE71F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEE"; constant PM_Inst_RAM_Word2_INIT_1C : bit_vector(0 to 255) := x"158E00FC91B000FB91A000FA919000F99180F56906B9E09216A9E0901D111D01"; constant PM_Inst_RAM_Word2_INIT_1D : bit_vector(0 to 255) := x"00FC93B000FB93A000FA939000F99380EFBFEFAFEF9FEF8FF46107B107A0059F"; constant PM_Inst_RAM_Word2_INIT_1E : bit_vector(0 to 255) := x"E0A0C09FF4092388020E940E2D352D242D4E2D5F2F602F710315919003149180"; constant PM_Inst_RAM_Word2_INIT_1F : bit_vector(0 to 255) := x"89A48993898285548543853285212DFD2DECF51104911481C0451E5B0E4AE0B2"; constant PM_Inst_RAM_Word2_INIT_20 : bit_vector(0 to 255) := x"930000FA92F000F992E0C083F40923880C64940EF098075B074A0739172889B5"; constant PM_Inst_RAM_Word2_INIT_21 : bit_vector(0 to 255) := x"0CC5940EE0412D6E2D7F2F802F91C00A0316938060810316918000FC931000FB"; constant PM_Inst_RAM_Word2_INIT_22 : bit_vector(0 to 255) := x"C0022FF32FE22DB52DA41D5B0D4A2F532F424F3E5E2C2D392D28C06BF4092388"; constant PM_Inst_RAM_Word2_INIT_23 : bit_vector(0 to 255) := x"2DECE050E0402D3B2D2A083B182A1E5F0E4E0BF31BE2F7D907F517E49381918D"; constant PM_Inst_RAM_Word2_INIT_24 : bit_vector(0 to 255) := x"96192DBD2DAC87B487A3879287811FB51FA41F930F8285B485A3859285812DFD"; constant PM_Inst_RAM_Word2_INIT_25 : bit_vector(0 to 255) := x"17822DA091BC900D919D918D9652CEC2F00904311421971C915C914D913D912D"; constant PM_Inst_RAM_Word2_INIT_26 : bit_vector(0 to 255) := x"01129180C0128383688081838B558B448B338B222DFD2DECF45007B507A40793"; constant PM_Inst_RAM_Word2_INIT_27 : bit_vector(0 to 255) := x"938C961368809713918C96132DBD2DACF0412B89819E818DF0612B8901139190"; constant PM_Inst_RAM_Word2_INIT_28 : bit_vector(0 to 255) := x"2DACE081C007815E814DF0192388051E940E2D9D2D8CC006FF8381832DFD2DEC"; constant PM_Inst_RAM_Word2_INIT_29 : bit_vector(0 to 255) := x"911F91DF91CFBFCDBE0FBFDE94F8B60F96262F952F84EF5FEF4F938C96122DBD"; constant PM_Inst_RAM_Word2_INIT_2A : bit_vector(0 to 255) := x"FD829508902F903F904F905F907F908F909F90AF90BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word2_INIT_2B : bit_vector(0 to 255) := x"08D5940E2F5B2F4A0BBF1BAE9711F7E92000900D2FBF2FAE2FF72FE6CE62CE4D"; constant PM_Inst_RAM_Word2_INIT_2C : bit_vector(0 to 255) := x"900F08D5940EE050E0414F7F5F6F2F7D2F6C8369B7DEB7CD920F93CF93DF9508"; constant PM_Inst_RAM_Word2_INIT_2D : bit_vector(0 to 255) := x"F409238808AC940E2FD92FC893DF93CF931F930F92FF92EF92DF950891DF91CF"; constant PM_Inst_RAM_Word2_INIT_2E : bit_vector(0 to 255) := x"84051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E8518810F80FE80ED8DFB8DEAC050"; constant PM_Inst_RAM_Word2_INIT_2F : bit_vector(0 to 255) := x"80D41F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEEC004"; constant PM_Inst_RAM_Word2_INIT_30 : bit_vector(0 to 255) := x"0C9F940E1D911D811D710D6D2D6E2D7F2F802F91C00D0911090108F108E19408"; constant PM_Inst_RAM_Word2_INIT_31 : bit_vector(0 to 255) := x"1F441F330F22C0048405E050E040E032E0208DFB8DEAF78920DD94DAF0F92388"; constant PM_Inst_RAM_Word2_INIT_32 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A1FB51FA41F930F8289BD89AC899B898AF7D2940A1F55"; constant PM_Inst_RAM_Word2_INIT_33 : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F950890DF90EF90FF910F911F91CF91DFE080C001"; constant PM_Inst_RAM_Word2_INIT_34 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F972BB7DEB7CD93CF93DF931F930F92FF92EF92DF92CF"; constant PM_Inst_RAM_Word2_INIT_35 : bit_vector(0 to 255) := x"2F1D2F0C2F952F84C0F2F0092388918C96142FB92FA82E822ED72EC62EB92EA8"; constant PM_Inst_RAM_Word2_INIT_36 : bit_vector(0 to 255) := x"965B2DBB2DAA8D938D822DFD2DECC0E5F40923880407940E2F712F604F1F5F0F"; constant PM_Inst_RAM_Word2_INIT_37 : bit_vector(0 to 255) := x"2499971C921C921D921D921D96192DBD2DAC8610821782168215975A938E939C"; constant PM_Inst_RAM_Word2_INIT_38 : bit_vector(0 to 255) := x"9516E085C0C0F40997002FF92FE80793940E2D9D2D8CC0492E792E602F912F80"; constant PM_Inst_RAM_Word2_INIT_39 : bit_vector(0 to 255) := x"2DBB2DAAF4992099F4D93E85F01123888180701F2D1EF7D1958A94E794F79507"; constant PM_Inst_RAM_Word2_INIT_3A : bit_vector(0 to 255) := x"935C934D933D932D961D00FC915000FB914000FA913000F991209751931C9651"; constant PM_Inst_RAM_Word2_INIT_3B : bit_vector(0 to 255) := x"2F2800C9940EE050E04B2F7F2F6E2D972D86C02794932499F4C1238881809750"; constant PM_Inst_RAM_Word2_INIT_3C : bit_vector(0 to 255) := x"2DFD2DEC94932499C07E2F612D9B2D8AC086F409338073802D88F4592B232F39"; constant PM_Inst_RAM_Word2_INIT_3D : bit_vector(0 to 255) := x"71822D88CFA7F408071B070A06F916E889B589A4899389828514850384F284E1"; constant PM_Inst_RAM_Word2_INIT_3E : bit_vector(0 to 255) := x"2DACC05FF4A197002F192F0804FF940EE0612D9B2D8AF0512099C06BF0093182"; constant PM_Inst_RAM_Word2_INIT_3F : bit_vector(0 to 255) := x"8A112DFB2DEAC051F40923880AD3940E2D9D2D8CC058F4093082918C96142DBD"; -- BRAM 0 in address space [0x00001800:0x00001FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word3 LOC = RAMB16_X0Y3; constant PM_Inst_RAM_Word3_INIT_00 : bit_vector(0 to 255) := x"920D9001E08B96312FFD2FEC2FB12FA0F7E9958A921D2FB12FA0E280E011E104"; constant PM_Inst_RAM_Word3_INIT_01 : bit_vector(0 to 255) := x"950996402F912F804F7F5F622F712F60F0499730011391F0011291E0F7E15081"; constant PM_Inst_RAM_Word3_INIT_02 : bit_vector(0 to 255) := x"919C918D96502FB12FA087868797E098E0808B808B912FF12FE0E298E281C00A"; constant PM_Inst_RAM_Word3_INIT_03 : bit_vector(0 to 255) := x"938E939C9657971F919C918D961E9758938E939C96599752938E939C96539751"; constant PM_Inst_RAM_Word3_INIT_04 : bit_vector(0 to 255) := x"962BE080C001083A940E2D4889612DFB2DEA2D9B2D8AF04923880C64940E9756"; constant PM_Inst_RAM_Word3_INIT_05 : bit_vector(0 to 255) := x"909F90AF90BF90CF90DF90EF90FF910F911F91DF91CFBFCDBE0FBFDE94F8B60F"; constant PM_Inst_RAM_Word3_INIT_06 : bit_vector(0 to 255) := x"00FC917000FB916000FA915000F99140F1992388031691809508906F907F908F"; constant PM_Inst_RAM_Word3_INIT_07 : bit_vector(0 to 255) := x"031991600318915003179140F1192388020E940EE031E1240315919003149180"; constant PM_Inst_RAM_Word3_INIT_08 : bit_vector(0 to 255) := x"2388020E940EE031E1240315919003149180F0910571056105511541031A9170"; constant PM_Inst_RAM_Word3_INIT_09 : bit_vector(0 to 255) := x"92EF9508E0809508E08103169210031A9210031992100318921003179210F061"; constant PM_Inst_RAM_Word3_INIT_0A : bit_vector(0 to 255) := x"31E4E0839211E0F1E1E4F0A923880C64940E2F192F082EF72EE6931F930F92FF"; constant PM_Inst_RAM_Word3_INIT_0B : bit_vector(0 to 255) := x"E0810316938060810316918000FC931000FB930000FA92F000F992E0F7D907F8"; constant PM_Inst_RAM_Word3_INIT_0C : bit_vector(0 to 255) := x"91802ED42F192F082EF72EE6931F930F92FF92EF92DF950890EF90FF910F911F"; constant PM_Inst_RAM_Word3_INIT_0D : bit_vector(0 to 255) := x"F0E923880C64940EF0D107B107A0059F158E00FC91B000FB91A000FA919000F9"; constant PM_Inst_RAM_Word3_INIT_0E : bit_vector(0 to 255) := x"00F992E0F0792388031E940EE031E1242D4E2D5F2F602F710315919003149180"; constant PM_Inst_RAM_Word3_INIT_0F : bit_vector(0 to 255) := x"910F911FE080C001E08103169380298D0316918000FC931000FB930000FA92F0"; constant PM_Inst_RAM_Word3_INIT_10 : bit_vector(0 to 255) := x"93DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F950890DF90EF90FF"; constant PM_Inst_RAM_Word3_INIT_11 : bit_vector(0 to 255) := x"F0083045C04124BB24AA24992488F429234403149360031593702F142ED92EC8"; constant PM_Inst_RAM_Word3_INIT_12 : bit_vector(0 to 255) := x"2FFD2FEC9721E0D02FC1C122F40923880CC5940EE040E090E080E070E060C12C"; constant PM_Inst_RAM_Word3_INIT_13 : bit_vector(0 to 255) := x"2B897090778FE09040F15BEE81804FFE54E24FFE5EECF7E1957A1FFF0FEEE074"; constant PM_Inst_RAM_Word3_INIT_14 : bit_vector(0 to 255) := x"0FCCE064C0FFF40805B105A10591368481B381A2819181804FFE53E6C10BF009"; constant PM_Inst_RAM_Word3_INIT_15 : bit_vector(0 to 255) := x"2D9BC0EEF40904B104A10491148180BB80AA809980884FDD52C6F7E1956A1FDD"; constant PM_Inst_RAM_Word3_INIT_16 : bit_vector(0 to 255) := x"F0094092508001209190011F9180C0E4F40923880CC5940EE0402D682D792D8A"; constant PM_Inst_RAM_Word3_INIT_17 : bit_vector(0 to 255) := x"238801219180C0D0F4092B890123919001229180C0D7F409232201249120C0DC"; constant PM_Inst_RAM_Word3_INIT_18 : bit_vector(0 to 255) := x"87452DFD2DEC5F4FC008E070E06186158384012191808B222DFD2DECC0CBF409"; constant PM_Inst_RAM_Word3_INIT_19 : bit_vector(0 to 255) := x"940A1F330F22C0022E042F372F26E090818485452DFD2DECC0B9F00830485041"; constant PM_Inst_RAM_Word3_INIT_1A : bit_vector(0 to 255) := x"01389120C008E050E040F01905311521012B9130012A9120F74107931782F7E2"; constant PM_Inst_RAM_Word3_INIT_1B : bit_vector(0 to 255) := x"012390F0012290E087508347833683252DFD2DEC013B9150013A914001399130"; constant PM_Inst_RAM_Word3_INIT_1C : bit_vector(0 to 255) := x"8F808F9101269190012591808B168B058AF48AE31D1B1D0A1CF90CE8E010E000"; constant PM_Inst_RAM_Word3_INIT_1D : bit_vector(0 to 255) := x"8F848F738F622DFD2DEC1F911F801D7F0D6E18A2940EE090E080E07001249160"; constant PM_Inst_RAM_Word3_INIT_1E : bit_vector(0 to 255) := x"E040952627332F234F3E5021F7E1955A1F330F22E05501269130012591208F95"; constant PM_Inst_RAM_Word3_INIT_1F : bit_vector(0 to 255) := x"E0A0F019970001289190012791808B518B40873787261F591F481F370F26E050"; constant PM_Inst_RAM_Word3_INIT_20 : bit_vector(0 to 255) := x"0AF31AE22CE82CF92D0A2D1B013791B0013691A00135919001349180C008E0B0"; constant PM_Inst_RAM_Word3_INIT_21 : bit_vector(0 to 255) := x"95479556C00484052DFD2DEC1F5B1F4A1F390F282D2E2D3F2F402F510B150B04"; constant PM_Inst_RAM_Word3_INIT_22 : bit_vector(0 to 255) := x"F410075FE0F0074FE0F0073FE0FF3F258754874387328721F7D2940A95279537"; constant PM_Inst_RAM_Word3_INIT_23 : bit_vector(0 to 255) := x"919001409180C011E0818B872DFD2DECE180F430405040404F3F5F25C006E08C"; constant PM_Inst_RAM_Word3_INIT_24 : bit_vector(0 to 255) := x"91CF91DFE080CFEDE2808FB58FA48F938F822DFD2DEC014391B0014291A00141"; constant PM_Inst_RAM_Word3_INIT_25 : bit_vector(0 to 255) := x"928F927F926F925F924F9508908F909F90AF90BF90CF90DF90EF90FF910F911F"; constant PM_Inst_RAM_Word3_INIT_26 : bit_vector(0 to 255) := x"2EE62ED52EC42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F"; constant PM_Inst_RAM_Word3_INIT_27 : bit_vector(0 to 255) := x"960185BC85AB859A8589C077F40805710561055130422E732E622E512E402EF7"; constant PM_Inst_RAM_Word3_INIT_28 : bit_vector(0 to 255) := x"2799F4293180898F895E894D893C892BC06AF40807B707A6079517841DB11DA1"; constant PM_Inst_RAM_Word3_INIT_29 : bit_vector(0 to 255) := x"2E86F7D1951A9567957795879596E0172D6C2D7D2D8E2D9FC00B2D6D2D7E2D8F"; constant PM_Inst_RAM_Word3_INIT_2A : bit_vector(0 to 255) := x"168800FC91B000FB91A000FA919000F991801EB51EA41E930E822EB92EA82E97"; constant PM_Inst_RAM_Word3_INIT_2B : bit_vector(0 to 255) := x"F4513180898FF1A923880CC5940EE0402D682D792D8A2D9BF04906BB06AA0699"; constant PM_Inst_RAM_Word3_INIT_2C : bit_vector(0 to 255) := x"1FFF0FEE70F077EF2DFD2DECC00E824082514FFE5EEC1FFF0FEE70F02DFD2DEC"; constant PM_Inst_RAM_Word3_INIT_2D : bit_vector(0 to 255) := x"F0803082898A0316938060810316918082738262825182404FFE5EEC1FFF0FEE"; constant PM_Inst_RAM_Word3_INIT_2E : bit_vector(0 to 255) := x"031A92B0031992A003189290031792801EBB1EAA1E990E8885B881AF819E818D"; constant PM_Inst_RAM_Word3_INIT_2F : bit_vector(0 to 255) := x"907F908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE080C001E081"; constant PM_Inst_RAM_Word3_INIT_30 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF9508904F905F906F"; constant PM_Inst_RAM_Word3_INIT_31 : bit_vector(0 to 255) := x"F40807B707A6079517841DB11DA1960185BC85AB859A85892ED32EC22F172F06"; constant PM_Inst_RAM_Word3_INIT_32 : bit_vector(0 to 255) := x"2D7F2F802F91C00B2D6F2F702F812799F4293180898F895E894D893C892BC057"; constant PM_Inst_RAM_Word3_INIT_33 : bit_vector(0 to 255) := x"00FA919000F991801F591F481F370F26F7D195EA9567957795879596E0E72D6E"; constant PM_Inst_RAM_Word3_INIT_34 : bit_vector(0 to 255) := x"0CC5940EE0402F622F732F842F95F049075B074A0739172800FC91B000FB91A0"; constant PM_Inst_RAM_Word3_INIT_35 : bit_vector(0 to 255) := x"E0B0E0A0819181804FFE5EEC1FFF0FEE70F02DFF2DEEF4613180898FF1312388"; constant PM_Inst_RAM_Word3_INIT_36 : bit_vector(0 to 255) := x"70BF81B381A2819181804FFE5EEC1FFF0FEE1FFF0FEE70F077EF2DFF2DEEC00F"; constant PM_Inst_RAM_Word3_INIT_37 : bit_vector(0 to 255) := x"90DF90EF90FF910F911F91CF91DFE080C001E08183B383A2839183802DFD2DEC"; constant PM_Inst_RAM_Word3_INIT_38 : bit_vector(0 to 255) := x"B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF950890CF"; constant PM_Inst_RAM_Word3_INIT_39 : bit_vector(0 to 255) := x"83B383A2839183802DFD2DECE0B0E0A0E090E0822F172F062EF52EE42ED92EC8"; constant PM_Inst_RAM_Word3_INIT_3A : bit_vector(0 to 255) := x"23880F04940E2D3B2D2A2D4E2D5F2F602F712D9D2D8C1CB11CA194082EBD2EAC"; constant PM_Inst_RAM_Word3_INIT_3B : bit_vector(0 to 255) := x"80E9F0C923880E5B940EE030E020E010E0002D4E2D5F2F602F712D9D2D8CF139"; constant PM_Inst_RAM_Word3_INIT_3C : bit_vector(0 to 255) := x"E0A0EF9FEF88C004E0BFEFAFEF9FEF88F029318089872DFD2DEC811C810B80FA"; constant PM_Inst_RAM_Word3_INIT_3D : bit_vector(0 to 255) := x"911F91DF91CF900F900F900F900FE080C001E081F278071B070A06F916E8E0B0"; constant PM_Inst_RAM_Word3_INIT_3E : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F925F924F950890AF90BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word3_INIT_3F : bit_vector(0 to 255) := x"835A83492ED92EC8B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF"; -- BRAM 0 in address space [0x00002000:0x000027FF], bit lane [15:0] -- INST PM_Inst/RAM_Word4 LOC = RAMB16_X0Y2; constant PM_Inst_RAM_Word4_INIT_00 : bit_vector(0 to 255) := x"2E9AE0A22C811C511C4194082E5D2E4C2711270024FF24EE2E732E62837C836B"; constant PM_Inst_RAM_Word4_INIT_01 : bit_vector(0 to 255) := x"2DAA2DBBF17123880F04940E2D352D242D9D2D8C817C816B815A81492CB12CA1"; constant PM_Inst_RAM_Word4_INIT_02 : bit_vector(0 to 255) := x"1F1B1F0A1EF90EE8F7D2940A1FBB1FAA1F990F88C00484052DFD2DEC2D882D99"; constant PM_Inst_RAM_Word4_INIT_03 : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987815C814B813A8129"; constant PM_Inst_RAM_Word4_INIT_04 : bit_vector(0 to 255) := x"900F900F900F900FE0818313830282F182E02DF72DE6F268075B074A07391728"; constant PM_Inst_RAM_Word4_INIT_05 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF"; constant PM_Inst_RAM_Word4_INIT_06 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F9508"; constant PM_Inst_RAM_Word4_INIT_07 : bit_vector(0 to 255) := x"876C875B874A2E392E28BFCDBE0FBFDE94F8B60F972FB7DEB7CD93CF93DF931F"; constant PM_Inst_RAM_Word4_INIT_08 : bit_vector(0 to 255) := x"2E912E80F0590531052105111501913C912D911D910D2FB32FA2872E873F877D"; constant PM_Inst_RAM_Word4_INIT_09 : bit_vector(0 to 255) := x"861980B380A2809180802FF92FE8C01186191CB11CA11C911C8194082EB32EA2"; constant PM_Inst_RAM_Word4_INIT_0A : bit_vector(0 to 255) := x"900D919D918D96192DB32DA28799E091F41105B105A1970185BD85AC859B858A"; constant PM_Inst_RAM_Word4_INIT_0B : bit_vector(0 to 255) := x"2466245524442CC82CD92CEA2CFB87B883AF839E838D1DB11DA196012DA091BC"; constant PM_Inst_RAM_Word4_INIT_0C : bit_vector(0 to 255) := x"F008067B066A0659164885B485A3859285812DF32DE24F1F5F0F2F1D2F0C2477"; constant PM_Inst_RAM_Word4_INIT_0D : bit_vector(0 to 255) := x"E0B22CB12CA12C912E88E082F45005BF05AE059D158C85B881AF819E818DC0A8"; constant PM_Inst_RAM_Word4_INIT_0E : bit_vector(0 to 255) := x"F40923880F04940E2F312F202D4C2D5D2D6E2D7F2D932D822CF12CE12CD12ECB"; constant PM_Inst_RAM_Word4_INIT_0F : bit_vector(0 to 255) := x"05B105A197004F5F4F4F4F3F5F2F2D2C2D3D2D4E2D5F81BC81AB819A8189C088"; constant PM_Inst_RAM_Word4_INIT_10 : bit_vector(0 to 255) := x"0739172885BD85AC859B858A095B094A09391928C00D2EB52EA42E932E82F029"; constant PM_Inst_RAM_Word4_INIT_11 : bit_vector(0 to 255) := x"2D932D82CFA71CF11CE11CD11CC194081C711C611C511C419408F059075B074A"; constant PM_Inst_RAM_Word4_INIT_12 : bit_vector(0 to 255) := x"2C6E2C5D2C4CC04CF4E123880E5B940EE03FEF2FEF1FEF0F2D7F2D6E2D5D2D4C"; constant PM_Inst_RAM_Word4_INIT_13 : bit_vector(0 to 255) := x"2D0C2D1D2D2E2D3F2D442D552D662D772D932D82087108610851084194082C7F"; constant PM_Inst_RAM_Word4_INIT_14 : bit_vector(0 to 255) := x"914D85BF85AEF30004BF04AE049D148C2CC42CD52CE62CF7F1A923880E5B940E"; constant PM_Inst_RAM_Word4_INIT_15 : bit_vector(0 to 255) := x"0E5B940E2D082D192D2A2D3B2D932D82F0510571056105511541917C916D915D"; constant PM_Inst_RAM_Word4_INIT_16 : bit_vector(0 to 255) := x"1CB11CA11C911C819408F06123FF85F982B382A28291828085FF85EEF0B92388"; constant PM_Inst_RAM_Word4_INIT_17 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F962FE080C001E081971392BC92AD929D928D2DB32DA2"; constant PM_Inst_RAM_Word4_INIT_18 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF"; constant PM_Inst_RAM_Word4_INIT_19 : bit_vector(0 to 255) := x"9380E0B0E0A0E090E082032692100324921003219210032092109508902F903F"; constant PM_Inst_RAM_Word4_INIT_1A : bit_vector(0 to 255) := x"92100345938003469390E091E081033E9210032A93B0032993A0032893900327"; constant PM_Inst_RAM_Word4_INIT_1B : bit_vector(0 to 255) := x"9380E18A10059380E18910049380E18B95080365921003619380036293900349"; constant PM_Inst_RAM_Word4_INIT_1C : bit_vector(0 to 255) := x"1669940EE070E060E255E840E094E08B20109380E083037E9210037F92101006"; constant PM_Inst_RAM_Word4_INIT_1D : bit_vector(0 to 255) := x"E073E16BE093E287032F940EE14CE061E093E18B1895940EE070E660E094E08B"; constant PM_Inst_RAM_Word4_INIT_1E : bit_vector(0 to 255) := x"E073E267E093E4850D04940EE040E073E16BE093E287F43923880D04940EE041"; constant PM_Inst_RAM_Word4_INIT_1F : bit_vector(0 to 255) := x"E963E094E08BF03123880B3A940EE021E050E848E073E465E093E68107E3940E"; constant PM_Inst_RAM_Word4_INIT_20 : bit_vector(0 to 255) := x"E68120199380037D91800662940EE050E041E073E76DE093E6811895940EE070"; constant PM_Inst_RAM_Word4_INIT_21 : bit_vector(0 to 255) := x"E041E073E76DE093E68120189380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_22 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120179380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_23 : bit_vector(0 to 255) := x"E68120159380037D91800662940EE050E041E073E76DE093E68120169380037D"; constant PM_Inst_RAM_Word4_INIT_24 : bit_vector(0 to 255) := x"E041E073E76DE093E68120149380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_25 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120139380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_26 : bit_vector(0 to 255) := x"E68120219380037D91800662940EE050E041E073E76DE093E68120129380037D"; constant PM_Inst_RAM_Word4_INIT_27 : bit_vector(0 to 255) := x"E041E073E76DE093E68120209380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_28 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201F9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_29 : bit_vector(0 to 255) := x"E681201D9380037D91800662940EE050E041E073E76DE093E681201E9380037D"; constant PM_Inst_RAM_Word4_INIT_2A : bit_vector(0 to 255) := x"E041E073E76DE093E681201C9380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_2B : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201B9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_2C : bit_vector(0 to 255) := x"E68120299380037D91800662940EE050E041E073E76DE093E681201A9380037D"; constant PM_Inst_RAM_Word4_INIT_2D : bit_vector(0 to 255) := x"E041E073E76DE093E68120289380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_2E : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120279380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_2F : bit_vector(0 to 255) := x"E68120259380037D91800662940EE050E041E073E76DE093E68120269380037D"; constant PM_Inst_RAM_Word4_INIT_30 : bit_vector(0 to 255) := x"E041E073E76DE093E68120249380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_31 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120239380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_32 : bit_vector(0 to 255) := x"E68120319380037D91800662940EE050E041E073E76DE093E68120229380037D"; constant PM_Inst_RAM_Word4_INIT_33 : bit_vector(0 to 255) := x"E041E073E76DE093E68120309380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_34 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202F9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_35 : bit_vector(0 to 255) := x"E681202D9380037D91800662940EE050E041E073E76DE093E681202E9380037D"; constant PM_Inst_RAM_Word4_INIT_36 : bit_vector(0 to 255) := x"E041E073E76DE093E681202C9380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_37 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202B9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_38 : bit_vector(0 to 255) := x"E070EA65E094E08BF43031802F18931F95080573940EE093E681202A9380037D"; constant PM_Inst_RAM_Word4_INIT_39 : bit_vector(0 to 255) := x"972BB7DEB7CD93CF93DF9508911F1876940EE050E1402F61E094E08B1757940E"; constant PM_Inst_RAM_Word4_INIT_3A : bit_vector(0 to 255) := x"037E9210037F9210C175F0099706037F9190037E9180BFCDBE0FBFDE94F8B60F"; constant PM_Inst_RAM_Word4_INIT_3B : bit_vector(0 to 255) := x"2F5D2F4CE073E465E093E681F7E15081920D9001E08BE0F0E8E896112FBD2FAC"; constant PM_Inst_RAM_Word4_INIT_3C : bit_vector(0 to 255) := x"940EE093E681201891600AC1940EE093E681201991600B3A940EE5224F5F5F4F"; constant PM_Inst_RAM_Word4_INIT_3D : bit_vector(0 to 255) := x"E681201591600AC1940EE093E681201691600AC1940EE093E681201791600AC1"; constant PM_Inst_RAM_Word4_INIT_3E : bit_vector(0 to 255) := x"91600AC1940EE093E681201391600AC1940EE093E681201491600AC1940EE093"; constant PM_Inst_RAM_Word4_INIT_3F : bit_vector(0 to 255) := x"940EE093E681202091600AC1940EE093E681202191600AC1940EE093E6812012"; -- BRAM 0 in address space [0x00002800:0x00002FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word5 LOC = RAMB16_X0Y7; constant PM_Inst_RAM_Word5_INIT_00 : bit_vector(0 to 255) := x"E681201D91600AC1940EE093E681201E91600AC1940EE093E681201F91600AC1"; constant PM_Inst_RAM_Word5_INIT_01 : bit_vector(0 to 255) := x"91600AC1940EE093E681201B91600AC1940EE093E681201C91600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_02 : bit_vector(0 to 255) := x"940EE093E681202891600AC1940EE093E681202991600AC1940EE093E681201A"; constant PM_Inst_RAM_Word5_INIT_03 : bit_vector(0 to 255) := x"E681202591600AC1940EE093E681202691600AC1940EE093E681202791600AC1"; constant PM_Inst_RAM_Word5_INIT_04 : bit_vector(0 to 255) := x"91600AC1940EE093E681202391600AC1940EE093E681202491600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_05 : bit_vector(0 to 255) := x"940EE093E681203091600AC1940EE093E681203191600AC1940EE093E6812022"; constant PM_Inst_RAM_Word5_INIT_06 : bit_vector(0 to 255) := x"E681202D91600AC1940EE093E681202E91600AC1940EE093E681202F91600AC1"; constant PM_Inst_RAM_Word5_INIT_07 : bit_vector(0 to 255) := x"91600AC1940EE093E681202B91600AC1940EE093E681202C91600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_08 : bit_vector(0 to 255) := x"91801388940E201A91801895940EE070EA67E094E08B0AC1940EE093E681202A"; constant PM_Inst_RAM_Word5_INIT_09 : bit_vector(0 to 255) := x"91801388940E201E91801388940E201D91801388940E201C91801388940E201B"; constant PM_Inst_RAM_Word5_INIT_0A : bit_vector(0 to 255) := x"940EE070EB6CE094E08B1388940E202191801388940E202091801388940E201F"; constant PM_Inst_RAM_Word5_INIT_0B : bit_vector(0 to 255) := x"940E201591801388940E201491801388940E201391801388940E201291801895"; constant PM_Inst_RAM_Word5_INIT_0C : bit_vector(0 to 255) := x"940E201991801388940E201891801388940E201791801388940E201691801388"; constant PM_Inst_RAM_Word5_INIT_0D : bit_vector(0 to 255) := x"91801388940E202B91801388940E202A91801895940EE070ED61E094E08B1388"; constant PM_Inst_RAM_Word5_INIT_0E : bit_vector(0 to 255) := x"91801388940E202F91801388940E202E91801388940E202D91801388940E202C"; constant PM_Inst_RAM_Word5_INIT_0F : bit_vector(0 to 255) := x"940E202291801895940EE070EE65E094E08B1388940E203191801388940E2030"; constant PM_Inst_RAM_Word5_INIT_10 : bit_vector(0 to 255) := x"940E202691801388940E202591801388940E202491801388940E202391801388"; constant PM_Inst_RAM_Word5_INIT_11 : bit_vector(0 to 255) := x"940EE093E6811388940E202991801388940E202891801388940E202791801388"; constant PM_Inst_RAM_Word5_INIT_12 : bit_vector(0 to 255) := x"1591940EE090E080E077ED60037E9380037F93909601037F9190037E91800573"; constant PM_Inst_RAM_Word5_INIT_13 : bit_vector(0 to 255) := x"933F932F2411920FB60F920F921F950891DF91CFBFCDBE0FBFDE94F8B60F962B"; constant PM_Inst_RAM_Word5_INIT_14 : bit_vector(0 to 255) := x"1DA1960103889130038791B0038691A0038591900384918093BF93AF939F938F"; constant PM_Inst_RAM_Word5_INIT_15 : bit_vector(0 to 255) := x"93A00385939003849380038893201DB11DA19601572DF020372D5F2D2F231DB1"; constant PM_Inst_RAM_Word5_INIT_16 : bit_vector(0 to 255) := x"038093801DB11DA19601038391B0038291A00381919003809180038793B00386"; constant PM_Inst_RAM_Word5_INIT_17 : bit_vector(0 to 255) := x"901F900FBE0F900F912F913F918F919F91AF91BF038393B0038293A003819390"; constant PM_Inst_RAM_Word5_INIT_18 : bit_vector(0 to 255) := x"2F952F842F732F62BF8F0387915003869140038591300384912094F8B78F9518"; constant PM_Inst_RAM_Word5_INIT_19 : bit_vector(0 to 255) := x"9160038591500384914094F8B78F2F192F082EF72EE6931F930F92FF92EF9508"; constant PM_Inst_RAM_Word5_INIT_1A : bit_vector(0 to 255) := x"1B84BF2F038791B0038691A0038591900384918094F8B72FBF8F038791700386"; constant PM_Inst_RAM_Word5_INIT_1B : bit_vector(0 to 255) := x"6084B7839478950890EF90FF910F911FF760071B070A06F916E80BB70BA60B95"; constant PM_Inst_RAM_Word5_INIT_1C : bit_vector(0 to 255) := x"BD856082B585BD8F6081B58FBD8E6081B58EBD8E6082B58EBF876081B787BF83"; constant PM_Inst_RAM_Word5_INIT_1D : bit_vector(0 to 255) := x"4F3F56262D9095C82FF92FE84F9F53862F932F82E0302F289508BD856081B585"; constant PM_Inst_RAM_Word5_INIT_1E : bit_vector(0 to 255) := x"95C896312DA095C84FFF59E01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE2"; constant PM_Inst_RAM_Word5_INIT_1F : bit_vector(0 to 255) := x"2F952F84E0502F489508938C2B89918C9508938C23899590918CF42923662DB0"; constant PM_Inst_RAM_Word5_INIT_20 : bit_vector(0 to 255) := x"4F5F56462D9095C82FF92FE84F9F53862F952F842D2095C82FF92FE84F9F5086"; constant PM_Inst_RAM_Word5_INIT_21 : bit_vector(0 to 255) := x"B58FF4213024C004778FB58FF4193023F0B12322F16923332D3095C82FF52FE4"; constant PM_Inst_RAM_Word5_INIT_22 : bit_vector(0 to 255) := x"E0F02FE3BD857D8FB585F4193025C005BF837D8FB783F4213021C00BBD8F7D8F"; constant PM_Inst_RAM_Word5_INIT_23 : bit_vector(0 to 255) := x"9508938C23899590918CF42923662DB095C896312DA095C84FFF58E21FFF0FEE"; constant PM_Inst_RAM_Word5_INIT_24 : bit_vector(0 to 255) := x"91E0B12C93FF93EF939F938F932F2411920FB60F920F921F9508938C2B89918C"; constant PM_Inst_RAM_Word5_INIT_25 : bit_vector(0 to 255) := x"91FF0409939083204FFC57E7E0F0F0311798040A918050E1779F2F9E5FEF0409"; constant PM_Inst_RAM_Word5_INIT_26 : bit_vector(0 to 255) := x"2F242F192F08931F930F92FF92EF9518901F900FBE0F900F912F918F919F91EF"; constant PM_Inst_RAM_Word5_INIT_27 : bit_vector(0 to 255) := x"502118E4940EE090E18EE874E860971590FC90ED96142FB92FA82F572F462F35"; constant PM_Inst_RAM_Word5_INIT_28 : bit_vector(0 to 255) := x"83202DFF2DEE18E4940EE050E040E030E0222F622F732F842F95405040404030"; constant PM_Inst_RAM_Word5_INIT_29 : bit_vector(0 to 255) := x"0F88C002971C900C961C2F952F84E050E0418120971791FC91ED96162FB12FA0"; constant PM_Inst_RAM_Word5_INIT_2A : bit_vector(0 to 255) := x"C002971D900C961D2F952F848120971791FC91ED961683202B28F7E2940A1F99"; constant PM_Inst_RAM_Word5_INIT_2B : bit_vector(0 to 255) := x"1F550F44C002900C961E8180971791FC91ED961683202B28F7E2940A1F990F88"; constant PM_Inst_RAM_Word5_INIT_2C : bit_vector(0 to 255) := x"E090918C852785B185A02FF92FE8950890EF90FF910F911F83802B84F7E2940A"; constant PM_Inst_RAM_Word5_INIT_2D : bit_vector(0 to 255) := x"9390E091E08B950883602DE085F38402CFF6FF80F7E2940A95879595C0022E02"; constant PM_Inst_RAM_Word5_INIT_2E : bit_vector(0 to 255) := x"E28A040F938004109390E090E289040D9380040E9390E093E889040B9380040C"; constant PM_Inst_RAM_Word5_INIT_2F : bit_vector(0 to 255) := x"938004169390E090E28C0413938004149390E090E28B0411938004129390E090"; constant PM_Inst_RAM_Word5_INIT_30 : bit_vector(0 to 255) := x"15BD940E9508041A9380E08504199380E08704189380E08304179380E0840415"; constant PM_Inst_RAM_Word5_INIT_31 : bit_vector(0 to 255) := x"2FA09621C00B2FD72FC62F192F0893DF93CF931F930FCFFD139B940E11B8940E"; constant PM_Inst_RAM_Word5_INIT_32 : bit_vector(0 to 255) := x"910F911F91CF91DFF7912366816895092F912F802DE081F0900191FC91ED2FB1"; constant PM_Inst_RAM_Word5_INIT_33 : bit_vector(0 to 255) := x"2DBF2DAEC0102FD52FC42EF72EE62F192F0893DF93CF931F930F92FF92EF9508"; constant PM_Inst_RAM_Word5_INIT_34 : bit_vector(0 to 255) := x"F7719720972195092F912F802DE081F0900191FC91ED2FB12FA02EFB2EEA916D"; constant PM_Inst_RAM_Word5_INIT_35 : bit_vector(0 to 255) := x"950895092DE081F3800291FC91ED2FB92FA8950890EF90FF910F911F91CF91DF"; constant PM_Inst_RAM_Word5_INIT_36 : bit_vector(0 to 255) := x"931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F"; constant PM_Inst_RAM_Word5_INIT_37 : bit_vector(0 to 255) := x"2EF72EE62ED52EC42E392E28BFCDBE0FBFDE94F8B60F97A0B7DEB7CD93CF93DF"; constant PM_Inst_RAM_Word5_INIT_38 : bit_vector(0 to 255) := x"24992488C06A1821940EE030E020E070E060E050E340F4490571056105511541"; constant PM_Inst_RAM_Word5_INIT_39 : bit_vector(0 to 255) := x"2D6C2D7D2D8E2D9F1D190D081F1D0F0CE010E0012477246624552E4224BB24AA"; constant PM_Inst_RAM_Word5_INIT_3A : bit_vector(0 to 255) := x"2D8E2D9F1CB11CA11C911C81940883602FF12FE018BD940E2D242D352D462D57"; constant PM_Inst_RAM_Word5_INIT_3B : bit_vector(0 to 255) := x"2EFB2EEA2ED92EC82FB52FA42F932F8218BD940E2D242D352D462D572D6C2D7D"; constant PM_Inst_RAM_Word5_INIT_3C : bit_vector(0 to 255) := x"1C6194082E7D2E6C1CF90CE81EFD0EEC2CF12EE8E081F68904F104E104D114C1"; constant PM_Inst_RAM_Word5_INIT_3D : bit_vector(0 to 255) := x"0DEE2DFD2DECC01808D918C82ED92EC809B109A197012D882D992DAA2DBB1C71"; constant PM_Inst_RAM_Word5_INIT_3E : bit_vector(0 to 255) := x"E030E0202D932D822F752F659550FD4727555C49C0015D40F410304A81401DFF"; constant PM_Inst_RAM_Word5_INIT_3F : bit_vector(0 to 255) := x"91DF91CFBFCDBE0FBFDE94F8B60F96A0F729047F146E08F108E194081821940E"; -- BRAM 0 in address space [0x00003000:0x000037FF], bit lane [15:0] -- INST PM_Inst/RAM_Word6 LOC = RAMB16_X0Y5; constant PM_Inst_RAM_Word6_INIT_00 : bit_vector(0 to 255) := x"902F903F904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F"; constant PM_Inst_RAM_Word6_INIT_01 : bit_vector(0 to 255) := x"1760940E950895092F642DE081F0900191FC91EDF441053115212FB92FA89508"; constant PM_Inst_RAM_Word6_INIT_02 : bit_vector(0 to 255) := x"F441053115212F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF9508"; constant PM_Inst_RAM_Word6_INIT_03 : bit_vector(0 to 255) := x"E060E050E24DC010FF77F4C90531302AC01E95092F642DE081F0900181F981E8"; constant PM_Inst_RAM_Word6_INIT_04 : bit_vector(0 to 255) := x"2F712F9D2F8C1D111D011CF11CE194E094F0950095101821940EE030E020E070"; constant PM_Inst_RAM_Word6_INIT_05 : bit_vector(0 to 255) := x"2F08931F930F950890EF90FF910F911F91CF91DF1760940EE02A2D4E2D5F2F60"; constant PM_Inst_RAM_Word6_INIT_06 : bit_vector(0 to 255) := x"E020E070E060E050E04A2F912F801821940EE030E020E070E060E050E04D2F19"; constant PM_Inst_RAM_Word6_INIT_07 : bit_vector(0 to 255) := x"2F352F242F192F08931F930F92FF92EF92DF92CF9508910F911F1821940EE030"; constant PM_Inst_RAM_Word6_INIT_08 : bit_vector(0 to 255) := x"910F911F185D940E2F912F801811940E2D4C2D5D2D6E2D7F24FF24EE24DD2EC6"; constant PM_Inst_RAM_Word6_INIT_09 : bit_vector(0 to 255) := x"911F185D940E2F912F801757940E2F192F08931F930F950890CF90DF90EF90FF"; constant PM_Inst_RAM_Word6_INIT_0A : bit_vector(0 to 255) := x"1F551F441F330F221FF51FE41FB30FA2C004FF6027AA27BB27EE27FF9508910F"; constant PM_Inst_RAM_Word6_INIT_0B : bit_vector(0 to 255) := x"1BAA2E1AE2A195082F6A2F7B2F8E2F9FF77107769700F7899567957795879596"; constant PM_Inst_RAM_Word6_INIT_0C : bit_vector(0 to 255) := x"0BE40BB31BA2F02007F507E407B317A21FFF1FEE1FBB1FAAC00D2FFB2FEA1BBB"; constant PM_Inst_RAM_Word6_INIT_0D : bit_vector(0 to 255) := x"2F6A2F592F482F372F269590958095709560F769941A1F991F881F771F660BF5"; constant PM_Inst_RAM_Word6_INIT_0E : bit_vector(0 to 255) := x"95409550F4381C00D00ADFD2D004FD57D00E26052E09FB9795082F9F2F8E2F7B"; constant PM_Inst_RAM_Word6_INIT_0F : bit_vector(0 to 255) := x"0FEE95084F9F4F8F4F7F9561957095809590F7F695084F5F4F4F4F3F95219530"; constant PM_Inst_RAM_Word6_INIT_10 : bit_vector(0 to 255) := x"6944205241542073692073696854CFFF94F89508920F95C8920F963195C81FFF"; constant PM_Inst_RAM_Word6_INIT_11 : bit_vector(0 to 255) := x"50554B43414200656369766564207265746E756F63206C616E6769732065646F"; constant PM_Inst_RAM_Word6_INIT_12 : bit_vector(0 to 255) := x"632065746972570030005458542E50554B4341422064656E65704F005458542E"; constant PM_Inst_RAM_Word6_INIT_13 : bit_vector(0 to 255) := x"552D3770557265746E756F6320657469725700306E442D376E447265746E756F"; constant PM_Inst_RAM_Word6_INIT_14 : bit_vector(0 to 255) := x"63695420657469725700306E442D376E4472656B636954206574697257003070"; constant PM_Inst_RAM_Word6_INIT_15 : bit_vector(0 to 255) := x"1516C90000000017310AB20AC100000000FFFFFFFF003070552D37705572656B"; constant PM_Inst_RAM_Word6_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000173117"; constant PM_Inst_RAM_Word6_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; -- BRAM 0 in address space [0x00003800:0x00003FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word7 LOC = RAMB16_X0Y6; constant PM_Inst_RAM_Word7_INIT_00 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_01 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_02 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_03 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_04 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_05 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_06 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_07 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_09 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_10 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_11 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_12 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_13 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_14 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_15 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; end prog_mem_init_pkg;	apache-2.0	bd07f99fabd0aae6567298d78217d74c	0.808908	2.441144	false	false	false	false
jairov4/accel-oil	solution_kintex7/sim/vhdl/sample_iterator_next.vhd	1	23,318	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end; architecture behav of sample_iterator_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0); signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_1_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_1_reg_151 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_2_fu_89_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_156 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_fu_95_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_4_reg_162 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_fu_100_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_reg_167 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_cast_12_fu_74_p1 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_cast_fu_83_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_2_fu_89_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_1_reg_151_temp: signed (17-1 downto 0); signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134; ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1; ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2; ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3; ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4; ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5; ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6; ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128; ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1; ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2; ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3; ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4; ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_index_read_reg_134 <= i_index; i_sample_read_reg_128 <= i_sample; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_addr_read_reg_146 <= indices_samples_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then tmp_1_reg_151 <= tmp_1_fu_77_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then tmp_2_reg_156 <= tmp_2_fu_89_p2; tmp_3_reg_167 <= tmp_3_fu_100_p2; tmp_4_reg_162 <= tmp_4_fu_95_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; agg_result_index_write_assign_fu_111_p3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7 when (tmp_2_reg_156(0) = '1') else tmp_4_reg_162; agg_result_sample_write_assign_fu_105_p3 <= tmp_3_reg_167 when (tmp_2_reg_156(0) = '1') else ap_const_lv16_0; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_samples_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return_0 <= agg_result_index_write_assign_fu_111_p3; ap_return_1 <= agg_result_sample_write_assign_fu_105_p3; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; indices_begin_address <= ap_const_lv32_0; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; indices_begin_req_write <= ap_const_logic_0; indices_begin_rsp_read <= ap_const_logic_0; indices_begin_size <= ap_const_lv32_0; indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0); indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_req_write <= ap_const_logic_1; else indices_samples_req_write <= ap_const_logic_0; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_rsp_read <= ap_const_logic_1; else indices_samples_rsp_read <= ap_const_logic_0; end if; end process; indices_samples_size <= ap_const_lv32_1; indices_stride_address <= ap_const_lv32_0; indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; indices_stride_req_write <= ap_const_logic_0; indices_stride_rsp_read <= ap_const_logic_0; indices_stride_size <= ap_const_lv32_0; tmp_1_fu_77_p2 <= std_logic_vector(unsigned(tmp_cast_12_fu_74_p1) + unsigned(ap_const_lv17_1FFFF)); tmp_1_reg_151_temp <= signed(tmp_1_reg_151); tmp_2_fu_89_p1 <= std_logic_vector(resize(tmp_1_reg_151_temp,18)); tmp_2_fu_89_p2 <= "1" when (signed(tmp_cast_fu_83_p1) < signed(tmp_2_fu_89_p1)) else "0"; tmp_3_fu_100_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it6) + unsigned(ap_const_lv16_1)); tmp_4_fu_95_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_index_read_reg_134_pp0_it6) + unsigned(ap_const_lv16_1)); tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64)); tmp_cast_12_fu_74_p1 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17)); tmp_cast_fu_83_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it6),18)); end behav;	lgpl-3.0	f6e0ac9c8907e30740b20f1033f6cc28	0.607899	2.717399	false	false	false	false
jairov4/accel-oil	impl/impl_test_single/hdl/system_proc_sys_reset_0_wrapper.vhd	2	4,214	------------------------------------------------------------------------------- -- system_proc_sys_reset_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library proc_sys_reset_v3_00_a; use proc_sys_reset_v3_00_a.all; entity system_proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); attribute x_core_info : STRING; attribute x_core_info of system_proc_sys_reset_0_wrapper : entity is "proc_sys_reset_v3_00_a"; end system_proc_sys_reset_0_wrapper; architecture STRUCTURE of system_proc_sys_reset_0_wrapper is component proc_sys_reset is generic ( C_EXT_RST_WIDTH : integer; C_AUX_RST_WIDTH : integer; C_EXT_RESET_HIGH : std_logic; C_AUX_RESET_HIGH : std_logic; C_NUM_BUS_RST : integer; C_NUM_PERP_RST : integer; C_NUM_INTERCONNECT_ARESETN : integer; C_NUM_PERP_ARESETN : integer ); port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1); Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1); Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1); Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1) ); end component; begin proc_sys_reset_0 : proc_sys_reset generic map ( C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '1', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) port map ( Slowest_sync_clk => Slowest_sync_clk, Ext_Reset_In => Ext_Reset_In, Aux_Reset_In => Aux_Reset_In, MB_Debug_Sys_Rst => MB_Debug_Sys_Rst, Core_Reset_Req_0 => Core_Reset_Req_0, Chip_Reset_Req_0 => Chip_Reset_Req_0, System_Reset_Req_0 => System_Reset_Req_0, Core_Reset_Req_1 => Core_Reset_Req_1, Chip_Reset_Req_1 => Chip_Reset_Req_1, System_Reset_Req_1 => System_Reset_Req_1, Dcm_locked => Dcm_locked, RstcPPCresetcore_0 => RstcPPCresetcore_0, RstcPPCresetchip_0 => RstcPPCresetchip_0, RstcPPCresetsys_0 => RstcPPCresetsys_0, RstcPPCresetcore_1 => RstcPPCresetcore_1, RstcPPCresetchip_1 => RstcPPCresetchip_1, RstcPPCresetsys_1 => RstcPPCresetsys_1, MB_Reset => MB_Reset, Bus_Struct_Reset => Bus_Struct_Reset, Peripheral_Reset => Peripheral_Reset, Interconnect_aresetn => Interconnect_aresetn, Peripheral_aresetn => Peripheral_aresetn ); end architecture STRUCTURE;	lgpl-3.0	a73f5a5120add593704a0fea0956ff6b	0.616991	3.299922	false	false	false	false
grwlf/vsim	vhdl_ct/ct00459.vhd	1	2,269	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00459 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00459) -- ENT00459_Test_Bench(ARCH00459_Test_Bench) -- -- REVISION HISTORY: -- -- 4-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES ; use WORK.ARITHMETIC.all ; architecture ARCH00459 of E00000 is begin process subtype st_int1 is integer range -100 to 1000 ; subtype st_int2 is integer range 0 downto -100 ; subtype st_phys1 is t_phys range (-2*20) ones to (2*20) ones ; subtype st_phys2 is t_phys range (-2*20) ones to (2*20) ones ; subtype st_real1 is real range 0.0 to 10.0 ; subtype st_real2 is real range -10.0 to -1.0 ; variable v_int1 : st_int1 := 49 ; variable v_int2 : st_int2 := -2 ; variable v_phys1 : st_phys1 := 2 tens ; variable v_phys2 : st_phys2 := 10 ones ; variable v_real1 : st_real1 := 9.0 ; variable v_real2 : st_real2 := -6.0 ; variable bool : boolean := true ; begin bool := bool and v_int1 mod v_int2 = -1 ; bool := bool and v_int1 rem v_int2 = 1 ; bool := bool and v_int1 * v_int2 = -98 ; bool := bool and abs (v_real1 * v_real2 - (-54.0)) < acceptable_error ; -- bool := bool and v_int1 / v_int2 = -24 ; bool := bool and v_phys1 / v_phys2 = 2 ; bool := bool and abs (v_real1 / v_real2 - (-1.5)) < acceptable_error ; STANDARD_TYPES.test_report ( "ARCH00459" , "Operands of multiplying operators may have different" & " subtypes" , bool ) ; wait ; end process ; end ARCH00459 ; entity ENT00459_Test_Bench is end ENT00459_Test_Bench ; architecture ARCH00459_Test_Bench of ENT00459_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00459 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00459_Test_Bench ;	gpl-3.0	bb99b45cb0d9822f2bccf863eec82344	0.539885	3.283647	false	true	false	false
grwlf/vsim	vhdl_ct/ct00498.vhd	1	10,904	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00498 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (7) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00498(ARCH00498) -- ENT00498_Test_Bench(ARCH00498_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00498 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00498 ; -- architecture ARCH00498 of ENT00498 is begin B1 : block procedure p1 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- variable v_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; variable v_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; variable v_bit_vector : st_bit_vector := ( others => '0' ) ; variable v_string : st_string := ( others => 'a' ) ; variable v_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; constant c_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; constant c_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; constant c_bit_vector : st_bit_vector := ( others => '0' ) ; constant c_string : st_string := ( others => 'a' ) ; constant c_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; variable bool : boolean := true; -- begin for i in 1 to 5 loop bool := bool and c_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and c_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and c_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and c_bit_vector = B"00000" ; -- bool := bool and c_string = "aaa" ; -- bool := bool and c_rec_1.f1 = 0 and c_rec_1.f4 = 0 and c_rec_1.f3 = 0 ; -- bool := bool and c_rec_1.f2(1) = false -- and c_rec_1.f2(0) = false and -- c_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in constant declaration" & " (dynamic)" , bool ) ; -- bool := true; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in variable declaration" & " (dynamic)" , bool ) ; end p1 ; -- begin process variable v_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; variable v_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; variable v_bit_vector : st_bit_vector := ( others => '0' ) ; variable v_string : st_string := ( others => 'a' ) ; variable v_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; constant c_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; constant c_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; constant c_bit_vector : st_bit_vector := ( others => '0' ) ; constant c_string : st_string := ( others => 'a' ) ; constant c_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; variable bool : boolean := true; -- begin for i in 1 to 5 loop bool := bool and c_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and c_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and c_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and c_bit_vector = B"00000" ; -- bool := bool and c_string = "aaa" ; -- bool := bool and c_rec_1.f1 = 0 and c_rec_1.f4 = 0 and c_rec_1.f3 = 0 ; -- bool := bool and c_rec_1.f2(1) = false -- and c_rec_1.f2(0) = false and -- c_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in constant declaration" & " (globally static)" , bool ) ; -- bool := true; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in variable declaration" & " (globally static)" , bool ) ; p1 ( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; wait ; end process ; end block B1 ; end ARCH00498 ; -- entity ENT00498_Test_Bench is end ENT00498_Test_Bench ; -- architecture ARCH00498_Test_Bench of ENT00498_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00498 ( ARCH00498 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00498_Test_Bench ;	gpl-3.0	f592d08c8728b63a34294e82b955aa11	0.460932	3.339663	false	false	false	false
grwlf/vsim	vhdl_ct/ct00018.vhd	1	8,897	-- NEED RESULT: ARCH00018: Wait in P1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in P2_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P2_2 did resume passed -- NEED RESULT: ARCH00018: Wait in P3_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P3_2 did resume passed -- NEED RESULT: ARCH00018: Wait in R1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in R1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC2_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC2_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC3_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC3_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC4_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC4_2 did resume passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00018 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.1 (8) -- -- DESIGN UNIT ORDERING: -- -- ENT00018(ARCH00018) -- ENT00018_Test_Bench(ARCH00018_Test_Bench) -- -- REVISION HISTORY: -- -- 26-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00018 is generic ( G1 : Time := 10 ns ) ; port ( P1 : in Time := 10 ns ) ; end ENT00018 ; architecture ARCH00018 of ENT00018 is signal Num_Cycles : Integer := 0 ; signal Dummy_Cond : Boolean := false ; signal P1_1_Did_Resume, P1_2_Did_Resume : Boolean := false ; signal P2_1_Did_Resume, P2_2_Did_Resume : Boolean := false ; signal P3_1_Did_Resume, P3_2_Did_Resume : Boolean := false ; signal R1_1_Did_Resume, R1_2_Did_Resume : Boolean := false ; signal PROC1_1_Did_Resume, PROC1_2_Did_Resume : Boolean := false ; signal PROC2_1_Did_Resume, PROC2_2_Did_Resume : Boolean := false ; signal PROC3_1_Did_Resume, PROC3_2_Did_Resume : Boolean := false ; signal PROC4_1_Did_Resume, PROC4_2_Did_Resume : Boolean := false ; constant Time_To_Wait : Time := 10 ns ; procedure PROC1_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static Resume_Chk <= transport True ; end PROC1_1 ; procedure PROC1_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static Resume_Chk <= transport True ; end PROC1_2 ; procedure PROC2_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static Resume_Chk <= transport True ; end PROC2_1 ; procedure PROC2_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for G1 ; -- Globally Static Resume_Chk <= transport True ; end PROC2_2 ; procedure PROC3_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic Resume_Chk <= transport True ; end PROC3_1 ; procedure PROC3_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for P1 ; -- Dynamic Resume_Chk <= transport True ; end PROC3_2 ; procedure PROC4_1 (Time_To_Wait : Time; Signal Resume_Chk : inout boolean) is begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; Resume_Chk <= transport True ; end PROC4_1 ; procedure PROC4_2 (Time_To_Wait : Time; Signal Resume_Chk : inout boolean) is begin wait until (Num_Cycles = 1000) for Time_To_Wait ; Resume_Chk <= transport True ; end PROC4_2 ; begin Test_Control : process ( Num_Cycles ) begin if Num_Cycles < 9 then Num_Cycles <= transport Num_Cycles + 1 after 1 ns ; elsif Num_Cycles = 9 then -- Verify that in fact, none of the wait statements resumed test_report ( "ARCH00018" , "Wait in P1_1 did resume" , Not P1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P1_2 did resume" , Not P1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P2_1 did resume" , Not P2_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P2_2 did resume" , Not P2_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P3_1 did resume" , Not P3_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P3_2 did resume" , Not P3_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in R1_1 did resume" , Not R1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in R1_2 did resume" , Not R1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC1_1 did resume" , Not PROC1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC1_2 did resume" , Not PROC1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC2_1 did resume" , Not PROC2_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC2_2 did resume" , Not PROC2_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC3_1 did resume" , Not PROC3_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC3_2 did resume" , Not PROC3_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC4_1 did resume" , Not PROC4_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC4_2 did resume" , Not PROC4_2_Did_Resume ) ; end if ; end process Test_Control ; P1_1 : process begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static P1_1_Did_Resume <= transport True ; wait; end process P1_1 ; P1_2 : process begin wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static P1_2_Did_Resume <= transport True ; wait; end process P1_2 ; P2_1 : process begin wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static P2_1_Did_Resume <= transport True ; wait; end process P2_1 ; P2_2 : process begin wait until (Num_Cycles = 1000) for G1 ; -- Globally Static P2_2_Did_Resume <= transport True ; wait; end process P2_2 ; P3_1 : process begin wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic P3_1_Did_Resume <= transport True ; wait; end process P3_1 ; P3_2 : process begin wait until (Num_Cycles = 1000) for P1 ; -- Dynamic P3_2_Did_Resume <= transport True ; wait; end process P3_2 ; Q1_1 : process begin PROC1_1 (PROC1_1_Did_Resume) ; wait; end process Q1_1 ; Q1_2 : process begin PROC1_2 (PROC1_2_Did_Resume) ; wait; end process Q1_2 ; Q2_1 : process begin PROC2_1 (PROC2_1_Did_Resume) ; wait; end process Q2_1 ; Q2_2 : process begin PROC2_2 (PROC2_2_Did_Resume) ; wait; end process Q2_2 ; Q3_1 : process begin PROC3_1 (PROC3_1_Did_Resume) ; wait; end process Q3_1 ; Q3_2 : process begin PROC3_2 (PROC3_2_Did_Resume) ; wait; end process Q3_2 ; Q4_1 : process begin PROC4_1 (Time_To_Wait, PROC4_1_Did_Resume) ; wait; end process Q4_1 ; Q4_2 : process begin PROC4_2 (P1, PROC4_2_Did_Resume) ; wait; end process Q4_2 ; R1_1 : process begin wait on Num_Cycles until Dummy_Cond ; -- No Time R1_1_Did_Resume <= transport True ; wait; end process R1_1 ; R1_2 : process begin wait until (Num_Cycles = 1000) ; -- No Time R1_2_Did_Resume <= transport True ; wait; end process R1_2 ; end ARCH00018 ; entity ENT00018_Test_Bench is end ENT00018_Test_Bench ; architecture ARCH00018_Test_Bench of ENT00018_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00018 ( ARCH00018 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00018_Test_Bench ;	gpl-3.0	f769c560579445752bc82f35311d4c36	0.562886	3.370076	false	true	false	false
dcliche/mdsynth	rtl/src/acia6850.vhd	1	34,541	--===========================================================================-- -- -- -- Synthesizable 6850 compatible ACIA -- -- -- --===========================================================================-- -- -- File name : acia6850.vhd -- -- Entity name : acia6850 -- -- Purpose : Implements a RS232 6850 compatible -- Asynchronous Communications Interface Adapter (ACIA) -- -- Dependencies : ieee.std_logic_1164 -- ieee.numeric_std -- ieee.std_logic_unsigned -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- Origins : miniUART written by Ovidiu Lupas [email protected] -- -- Registers : -- -- IO address + 0 Read - Status Register -- -- Bit[7] - Interrupt Request Flag -- Bit[6] - Receive Parity Error (parity bit does not match) -- Bit[5] - Receive Overrun Error (new character received before last read) -- Bit[4] - Receive Framing Error (bad stop bit) -- Bit[3] - Clear To Send level -- Bit[2] - Data Carrier Detect (lost modem carrier) -- Bit[1] - Transmit Buffer Empty (ready to accept next transmit character) -- Bit[0] - Receive Data Ready (character received) -- -- IO address + 0 Write - Control Register -- -- Bit[7] - Rx Interupt Enable -- 0 - disabled -- 1 - enabled -- Bits[6..5] - Transmit Control -- 0 0 - TX interrupt disabled, RTS asserted -- 0 1 - TX interrupt enabled, RTS asserted -- 1 0 - TX interrupt disabled, RTS cleared -- 1 1 - TX interrupt disabled, RTS asserted, Send Break -- Bits[4..2] - Word Control -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop -- Bits[1..0] - Baud Control -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - Reset -- -- IO address + 1 Read - Receive Data Register -- -- Read when Receive Data Ready bit set -- Read resets Receive Data Ready bit -- -- IO address + 1 Write - Transmit Data Register -- -- Write when Transmit Buffer Empty bit set -- Write resets Transmit Buffer Empty Bit -- -- -- Copyright (C) 2002 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Changes -- -- 0.1 Ovidiu Lupas 2000-01-15 New model -- 1.0 Ovidiu Lupas 2000-01 Synthesis optimizations -- 2.0 Ovidiu Lupas 2000-04 Bugs removed - the RSBusCtrl did not -- process all possible situations -- -- 3.0 John Kent 2002-10 Changed Status bits to match MC6805 -- Added CTS, RTS, Baud rate control & Software Reset -- 3.1 John Kent 2003-01-05 Added Word Format control a'la mc6850 -- 3.2 John Kent 2003-07-19 Latched Data input to UART -- 3.3 John Kent 2004-01-16 Integrated clkunit in rxunit & txunit -- TX / RX Baud Clock now external -- also supports x1 clock and DCD. -- 3.4 John Kent 2005-09-13 Removed LoadCS signal. -- Fixed ReadCS and Read -- in miniuart_DCD_Init process -- 3.5 John Kent 2006-11-28 Cleaned up code. -- -- 4.0 John Kent 2007-02-03 Renamed ACIA6850 -- 4.1 John Kent 2007-02-06 Made software reset synchronous -- 4.2 John Kent 2007-02-25 Changed sensitivity lists -- Rearranged Reset process. -- 4.3 John Kent 2010-06-17 Updated header -- 4.4 John Kent 2010-08-27 Combined with ACIA_RX & ACIA_TX -- Renamed to acia6850 -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; --library unisim; -- use unisim.vcomponents.all; ----------------------------------------------------------------------- -- Entity for ACIA_6850 -- ----------------------------------------------------------------------- entity acia6850 is port ( -- -- CPU Interface signals -- clk : in std_logic; -- System Clock rst : in std_logic; -- Reset input (active high) cs : in std_logic; -- miniUART Chip Select addr : in std_logic; -- Register Select rw : in std_logic; -- Read / Not Write data_in : in std_logic_vector(7 downto 0); -- Data Bus In data_out : out std_logic_vector(7 downto 0); -- Data Bus Out irq : out std_logic; -- Interrupt Request out -- -- RS232 Interface Signals -- RxC : in std_logic; -- Receive Baud Clock TxC : in std_logic; -- Transmit Baud Clock RxD : in std_logic; -- Receive Data TxD : out std_logic; -- Transmit Data DCD_n : in std_logic; -- Data Carrier Detect CTS_n : in std_logic; -- Clear To Send RTS_n : out std_logic -- Request To send ); end acia6850; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for ACIA_6850 Interface registees ------------------------------------------------------------------------------- architecture rtl of acia6850 is type DCD_State_Type is (DCD_State_Idle, DCD_State_Int, DCD_State_Reset); ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- -- -- Reset signals -- signal ac_rst : std_logic; -- Reset (Software & Hardware) signal rx_rst : std_logic; -- Receive Reset (Software & Hardware) signal tx_rst : std_logic; -- Transmit Reset (Software & Hardware) -------------------------------------------------------------------- -- Status Register: StatReg ---------------------------------------------------------------------- -- -- IO address + 0 Read -- -----------+--------+-------+--------+--------+--------+--------+--------+ -- Irq \| PErr \| OErr \| FErr \| CTS \| DCD \| TxRdy \| RxRdy \| -----------+--------+-------+--------+--------+--------+--------+--------+ -- -- Irq - Bit[7] - Interrupt request -- PErr - Bit[6] - Receive Parity error (parity bit does not match) -- OErr - Bit[5] - Receive Overrun error (new character received before last read) -- FErr - Bit[4] - Receive Framing Error (bad stop bit) -- CTS - Bit[3] - Clear To Send level -- DCD - Bit[2] - Data Carrier Detect (lost modem carrier) -- TxRdy - Bit[1] - Transmit Buffer Empty (ready to accept next transmit character) -- RxRdy - Bit[0] - Receive Data Ready (character received) -- signal StatReg : std_logic_vector(7 downto 0) := (others => '0'); -- status register ---------------------------------------------------------------------- -- Control Register: CtrlReg ---------------------------------------------------------------------- -- -- IO address + 0 Write -- -----------+--------+--------+--------+--------+--------+--------+--------+ -- RxIE \|TxCtl(1)\|TxCtl(0)\|WdFmt(2)\|WdFmt(1)\|WdFmt(0)\|BdCtl(1)\|BdCtl(0)\| -----------+--------+--------+--------+--------+--------+--------+--------+ -- RxIEnb - Bit[7] -- 0 - Rx Interrupt disabled -- 1 - Rx Interrupt enabled -- TxCtl - Bits[6..5] -- 0 1 - Tx Interrupt Enable -- 1 0 - RTS high -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop -- BdCtl - Bits[1..0] -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - reset signal CtrlReg : std_logic_vector(7 downto 0) := (others => '0'); -- control register ---------------------------------------------------------------------- -- Receive Register ---------------------------------------------------------------------- -- -- IO address + 1 Read -- signal RxReg : std_logic_vector(7 downto 0) := (others => '0'); ---------------------------------------------------------------------- -- Transmit Register ---------------------------------------------------------------------- -- -- IO address + 1 Write -- signal TxReg : std_logic_vector(7 downto 0) := (others => '0'); signal TxDat : std_logic := '1'; -- Transmit data bit signal TxRdy : std_logic := '0'; -- Transmit buffer empty signal RxRdy : std_logic := '0'; -- Receive Data ready -- signal FErr : std_logic := '0'; -- Frame error signal OErr : std_logic := '0'; -- Output error signal PErr : std_logic := '0'; -- Parity Error -- signal TxIE : std_logic := '0'; -- Transmit interrupt enable signal RxIE : std_logic := '0'; -- Receive interrupt enable -- signal RxRd : std_logic := '0'; -- Read receive buffer signal TxWr : std_logic := '0'; -- Write Transmit buffer signal StRd : std_logic := '0'; -- Read status register -- signal DCDState : DCD_State_Type; -- DCD Reset state sequencer signal DCDDel : std_logic := '0'; -- Delayed DCD_n signal DCDEdge : std_logic := '0'; -- Rising DCD_N Edge Pulse signal DCDInt : std_logic := '0'; -- DCD Interrupt signal BdFmt : std_logic_vector(1 downto 0) := "00"; -- Baud Clock Format signal WdFmt : std_logic_vector(2 downto 0) := "000"; -- Data Word Format ----------------------------------------------------------------------------- -- RX Signals ----------------------------------------------------------------------------- type RxStateType is ( RxState_Wait, RxState_Data, RxState_Parity, RxState_Stop ); signal RxState : RxStateType; -- receive bit state signal RxDatDel0 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatDel1 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatDel2 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatEdge : Std_Logic := '0'; -- Rx Data Edge pulse signal RxClkDel : Std_Logic := '0'; -- Delayed Rx Input Clock signal RxClkEdge : Std_Logic := '0'; -- Rx Input Clock Edge pulse signal RxStart : Std_Logic := '0'; -- Rx Start request signal RxEnable : Std_Logic := '0'; -- Rx Enabled signal RxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Rx Baud Clock Counter signal RxBdClk : Std_Logic := '0'; -- Rx Baud Clock signal RxBdDel : Std_Logic := '0'; -- Delayed Rx Baud Clock signal RxReq : Std_Logic := '0'; -- Rx Data Valid signal RxAck : Std_Logic := '0'; -- Rx Data Valid signal RxParity : Std_Logic := '0'; -- Calculated RX parity bit signal RxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Rx Bit counter signal RxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Shift Register ----------------------------------------------------------------------------- -- TX Signals ----------------------------------------------------------------------------- type TxStateType is ( TxState_Idle, TxState_Start, TxState_Data, TxState_Parity, TxState_Stop ); signal TxState : TxStateType; -- Transmitter state signal TxClkDel : Std_Logic := '0'; -- Delayed Tx Input Clock signal TxClkEdge : Std_Logic := '0'; -- Tx Input Clock Edge pulse signal TxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Tx Baud Clock Counter signal TxBdClk : Std_Logic := '0'; -- Tx Baud Clock signal TxBdDel : Std_Logic := '0'; -- Delayed Tx Baud Clock signal TxReq : std_logic := '0'; -- Request transmit start signal TxAck : std_logic := '0'; -- Acknowledge transmit start signal TxParity : Std_logic := '0'; -- Parity Bit signal TxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Data Bit Counter signal TxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Transmit shift register begin --------------------------------------------------------------- -- ACIA Reset may be hardware or software --------------------------------------------------------------- acia_reset : process( clk, rst, ac_rst, dcd_n ) begin -- -- ACIA reset Synchronous -- Includes software reset -- if falling_edge(clk) then ac_rst <= (CtrlReg(1) and CtrlReg(0)) or rst; end if; -- Receiver reset rx_rst <= ac_rst or DCD_n; -- Transmitter reset tx_rst <= ac_rst; end process; ----------------------------------------------------------------------------- -- Generate Read / Write strobes. ----------------------------------------------------------------------------- acia_read_write : process(clk, ac_rst) begin if falling_edge(clk) then if rst = '1' then CtrlReg(1 downto 0) <= "11"; CtrlReg(7 downto 2) <= (others => '0'); TxReg <= (others => '0'); RxRd <= '0'; TxWr <= '0'; StRd <= '0'; else RxRd <= '0'; TxWr <= '0'; StRd <= '0'; if cs = '1' then if Addr = '0' then -- Control / Status register if rw = '0' then -- write control register CtrlReg <= data_in; else -- read status register StRd <= '1'; end if; else -- Data Register if rw = '0' then -- write transmiter register TxReg <= data_in; TxWr <= '1'; else -- read receiver register RxRd <= '1'; end if; end if; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- ACIA Status Register ----------------------------------------------------------------------------- acia_status : process( clk ) begin if falling_edge( clk ) then StatReg(0) <= RxRdy; -- Receive Data Ready StatReg(1) <= TxRdy and (not CTS_n); -- Transmit Buffer Empty StatReg(2) <= DCDInt; -- Data Carrier Detect StatReg(3) <= CTS_n; -- Clear To Send StatReg(4) <= FErr; -- Framing error StatReg(5) <= OErr; -- Overrun error StatReg(6) <= PErr; -- Parity error StatReg(7) <= (RxIE and RxRdy) or (RxIE and DCDInt) or (TxIE and TxRdy); end if; end process; ----------------------------------------------------------------------------- -- ACIA Transmit Control ----------------------------------------------------------------------------- acia_control : process(CtrlReg, TxDat) begin case CtrlReg(6 downto 5) is when "00" => -- Disable TX Interrupts, Assert RTS TxD <= TxDat; TxIE <= '0'; RTS_n <= '0'; when "01" => -- Enable TX interrupts, Assert RTS TxD <= TxDat; TxIE <= '1'; RTS_n <= '0'; when "10" => -- Disable Tx Interrupts, Clear RTS TxD <= TxDat; TxIE <= '0'; RTS_n <= '1'; when "11" => -- Disable Tx interrupts, Assert RTS, send break TxD <= '0'; TxIE <= '0'; RTS_n <= '0'; when others => null; end case; RxIE <= CtrlReg(7); WdFmt <= CtrlReg(4 downto 2); BdFmt <= CtrlReg(1 downto 0); end process; --------------------------------------------------------------- -- Set Data Output Multiplexer -------------------------------------------------------------- acia_data_mux : process(Addr, RxReg, StatReg) begin if Addr = '1' then data_out <= RxReg; -- read receiver register else data_out <= StatReg; -- read status register end if; end process; irq <= StatReg(7); --------------------------------------------------------------- -- Data Carrier Detect Edge rising edge detect --------------------------------------------------------------- acia_dcd_edge : process( clk, ac_rst ) begin if falling_edge(clk) then if ac_rst = '1' then DCDDel <= '0'; DCDEdge <= '0'; else DCDDel <= DCD_n; DCDEdge <= DCD_n and (not DCDDel); end if; end if; end process; --------------------------------------------------------------- -- Data Carrier Detect Interrupt --------------------------------------------------------------- -- If Data Carrier is lost, an interrupt is generated -- To clear the interrupt, first read the status register -- then read the data receive register acia_dcd_int : process( clk, ac_rst ) begin if falling_edge(clk) then if ac_rst = '1' then DCDInt <= '0'; DCDState <= DCD_State_Idle; else case DCDState is when DCD_State_Idle => -- DCD Edge activates interrupt if DCDEdge = '1' then DCDInt <= '1'; DCDState <= DCD_State_Int; end if; when DCD_State_Int => -- To reset DCD interrupt, -- First read status if StRd = '1' then DCDState <= DCD_State_Reset; end if; when DCD_State_Reset => -- Then read receive register if RxRd = '1' then DCDInt <= '0'; DCDState <= DCD_State_Idle; end if; when others => null; end case; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Clock Edge Detection --------------------------------------------------------------------- -- A rising edge will produce a one clock cycle pulse -- acia_rx_clock_edge : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxClkDel <= '0'; RxClkEdge <= '0'; else RxClkDel <= RxC; RxClkEdge <= (not RxClkDel) and RxC; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Data Edge Detection --------------------------------------------------------------------- -- A falling edge will produce a pulse on RxClk wide -- acia_rx_data_edge : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxDatDel0 <= '0'; RxDatDel1 <= '0'; RxDatDel2 <= '0'; RxDatEdge <= '0'; else RxDatDel0 <= RxD; RxDatDel1 <= RxDatDel0; RxDatDel2 <= RxDatDel1; RxDatEdge <= RxDatDel0 and (not RxD); end if; end if; end process; --------------------------------------------------------------------- -- Receiver Start / Stop --------------------------------------------------------------------- -- Enable the receive clock on detection of a start bit -- Disable the receive clock after a byte is received. -- acia_rx_start_stop : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxEnable <= '0'; RxStart <= '0'; elsif (RxEnable = '0') and (RxDatEdge = '1') then -- Data Edge detected RxStart <= '1'; -- Request Start and RxEnable <= '1'; -- Enable Receive Clock elsif (RxStart = '1') and (RxAck = '1') then -- Data is being received RxStart <= '0'; -- Reset Start Request elsif (RxStart = '0') and (RxAck = '0') then -- Data has now been received RxEnable <= '0'; -- Disable Receiver until next Start Bit end if; end if; end process; --------------------------------------------------------------------- -- Receiver Clock Divider --------------------------------------------------------------------- -- Hold the Rx Clock divider in reset when the receiver is disabled -- Advance the count only on a rising Rx clock edge -- acia_rx_clock_divide : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxClkCnt <= (others => '0'); elsif RxDatEdge = '1' then -- reset on falling data edge RxClkCnt <= (others => '0'); elsif RxClkEdge = '1' then -- increment count on Clock edge RxClkCnt <= RxClkCnt + "000001"; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Baud Clock Selector --------------------------------------------------------------------- -- BdFmt -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - Reset -- acia_rx_baud_clock_select : process( BdFmt, RxC, RxClkCnt ) begin case BdFmt is when "00" => -- Div by 1 RxBdClk <= RxC; when "01" => -- Div by 16 RxBdClk <= RxClkCnt(3); when "10" => -- Div by 64 RxBdClk <= RxClkCnt(5); when others => -- Software Reset RxBdClk <= '0'; end case; end process; --------------------------------------------------------------------- -- Receiver process --------------------------------------------------------------------- -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop acia_rx_receive : process( clk, rst ) begin if falling_edge( clk ) then if rx_rst = '1' then FErr <= '0'; OErr <= '0'; PErr <= '0'; RxShiftReg <= (others => '0'); -- Reset Shift register RxReg <= (others => '0'); RxParity <= '0'; -- reset Parity bit RxAck <= '0'; -- Receiving data RxBitCount <= (others => '0'); RxState <= RxState_Wait; else RxBdDel <= RxBdClk; if RxBdDel = '0' and RxBdClk = '1' then case RxState is when RxState_Wait => RxShiftReg <= (others => '0'); -- Reset Shift register RxParity <= '0'; -- Reset Parity bit if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data bits RxBitCount <= "110"; else -- WdFmt(2) = '1' => 8 data bits RxBitCount <= "111"; end if; if RxDatDel2 = '0' then -- look for start bit RxState <= RxState_Data; -- if low, start reading data end if; when RxState_Data => -- Receiving data bits RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1); RxParity <= RxParity xor RxDatDel2; RxAck <= '1'; -- Flag receive in progress RxBitCount <= RxBitCount - "001"; if RxBitCount = "000" then if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data RxState <= RxState_Parity; -- 7 bits always has parity elsif WdFmt(1) = '0' then -- WdFmt(2) = '1' => 8 data RxState <= RxState_Stop; -- WdFmt(1) = '0' => no parity PErr <= '0'; -- Reset Parity Error else RxState <= RxState_Parity; -- WdFmt(1) = '1' => 8 data + parity end if; end if; when RxState_Parity => -- Receive Parity bit if WdFmt(2) = '0' then -- if 7 data bits, shift parity into MSB RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1); -- 7 data + parity end if; if RxParity = (RxDatDel2 xor WdFmt(0)) then PErr <= '1'; -- If parity not the same flag error else PErr <= '0'; end if; RxState <= RxState_Stop; when RxState_Stop => -- stop bit (Only one required for RX) RxAck <= '0'; -- Flag Receive Complete RxReg <= RxShiftReg; if RxDatDel2 = '1' then -- stop bit expected FErr <= '0'; -- yes, no framing error else FErr <= '1'; -- no, framing error end if; if RxRdy = '1' then -- Has previous data been read ? OErr <= '1'; -- no, overrun error else OErr <= '0'; -- yes, no over run error end if; RxState <= RxState_Wait; when others => RxAck <= '0'; -- Flag Receive Complete RxState <= RxState_Wait; end case; end if; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Read process --------------------------------------------------------------------- acia_rx_read : process( clk, rst, RxRdy ) begin if falling_edge(clk) then if rx_rst = '1' then RxRdy <= '0'; RxReq <= '0'; elsif RxRd = '1' then -- Data was read, RxRdy <= '0'; -- Reset receive full RxReq <= '1'; -- Request more data elsif RxReq = '1' and RxAck = '1' then -- Data is being received RxReq <= '0'; -- reset receive request elsif RxReq = '0' and RxAck = '0' then -- Data now received RxRdy <= '1'; -- Flag RxRdy and read Shift Register end if; end if; end process; --------------------------------------------------------------------- -- Transmit Clock Edge Detection -- A falling edge will produce a one clock cycle pulse --------------------------------------------------------------------- acia_tx_clock_edge : process( Clk, tx_rst ) begin if falling_edge(clk) then if tx_rst = '1' then TxClkDel <= '0'; TxClkEdge <= '0'; else TxClkDel <= TxC; TxClkEdge <= TxClkDel and (not TxC); end if; end if; end process; --------------------------------------------------------------------- -- Transmit Clock Divider -- Advance the count only on an input clock pulse --------------------------------------------------------------------- acia_tx_clock_divide : process( clk, tx_rst ) begin if falling_edge(clk) then if tx_rst = '1' then TxClkCnt <= (others=>'0'); elsif TxClkEdge = '1' then TxClkCnt <= TxClkCnt + "000001"; end if; end if; end process; --------------------------------------------------------------------- -- Transmit Baud Clock Selector --------------------------------------------------------------------- acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC ) begin -- BdFmt -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - reset case BdFmt is when "00" => -- Div by 1 TxBdClk <= TxC; when "01" => -- Div by 16 TxBdClk <= TxClkCnt(3); when "10" => -- Div by 64 TxBdClk <= TxClkCnt(5); when others => -- Software reset TxBdClk <= '0'; end case; end process; ----------------------------------------------------------------------------- -- Implements the Tx unit ----------------------------------------------------------------------------- -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop acia_tx_transmit : process( clk, tx_rst) begin if falling_edge(clk) then if tx_rst = '1' then TxDat <= '1'; TxShiftReg <= (others=>'0'); TxParity <= '0'; TxBitCount <= (others=>'0'); TxAck <= '0'; TxState <= TxState_Idle; else TxBdDel <= TxBdClk; -- On rising edge of baud clock, run the state machine if TxBdDel = '0' and TxBdClk = '1' then case TxState is when TxState_Idle => TxDat <= '1'; if TxReq = '1' then TxShiftReg <= TxReg; -- Load Shift reg with Tx Data TxAck <= '1'; TxState <= TxState_Start; end if; when TxState_Start => TxDat <= '0'; -- Start bit TxParity <= '0'; if WdFmt(2) = '0' then TxBitCount <= "110"; -- 7 data + parity else TxBitCount <= "111"; -- 8 data end if; TxState <= TxState_Data; when TxState_Data => TxDat <= TxShiftReg(0); TxShiftReg <= '1' & TxShiftReg(7 downto 1); TxParity <= TxParity xor TxShiftReg(0); TxBitCount <= TxBitCount - "001"; if TxBitCount = "000" then if (WdFmt(2) = '1') and (WdFmt(1) = '0') then if WdFmt(0) = '0' then -- 8 data bits TxState <= TxState_Stop; -- 2 stops else TxAck <= '0'; TxState <= TxState_Idle; -- 1 stop end if; else TxState <= TxState_Parity; -- parity end if; end if; when TxState_Parity => -- 7/8 data + parity bit if WdFmt(0) = '0' then TxDat <= not(TxParity); -- even parity else TxDat <= TxParity; -- odd parity end if; if WdFmt(1) = '0' then TxState <= TxState_Stop; -- 2 stops else TxAck <= '0'; TxState <= TxState_Idle; -- 1 stop end if; when TxState_Stop => -- first of two stop bits TxDat <= '1'; TxAck <= '0'; TxState <= TxState_Idle; end case; end if; end if; end if; end process; --------------------------------------------------------------------- -- Transmitter Write process --------------------------------------------------------------------- acia_tx_write : process( clk, tx_rst, TxWr, TxReq, TxAck ) begin if falling_edge(clk) then if tx_rst = '1' then TxRdy <= '0'; TxReq <= '0'; elsif TxWr = '1' then -- Data was read, TxRdy <= '0'; -- Reset transmit empty TxReq <= '1'; -- Request data transmit elsif TxReq = '1' and TxAck = '1' then -- Data is being transmitted TxReq <= '0'; -- reset transmit request elsif TxReq = '0' and TxAck = '0' then -- Data transmitted TxRdy <= '1'; -- Flag TxRdy end if; end if; end process; end rtl;	gpl-3.0	a9561e0aa141e988999052e298368f6e	0.425929	4.365647	false	false	false	false
Given-Jiang/Binarization	Binarization_dspbuilder/hdl/Binarization_GN.vhd	2	10,406	-- Binarization_GN.vhd -- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Binarization_GN is port ( Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire Clock : in std_logic := '0'; -- Clock.clk aclr : in std_logic := '0'; -- .reset_n Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire Avalon_MM_Slave_write : in std_logic := '0'; -- Avalon_MM_Slave_write.wire Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire Avalon_ST_Source_endofpacket : out std_logic -- Avalon_ST_Source_endofpacket.wire ); end entity Binarization_GN; architecture rtl of Binarization_GN is component alt_dspbuilder_clock_GNF343OQUJ is port ( aclr : in std_logic := 'X'; -- reset aclr_n : in std_logic := 'X'; -- reset_n aclr_out : out std_logic; -- reset clock : in std_logic := 'X'; -- clk clock_out : out std_logic -- clk ); end component alt_dspbuilder_clock_GNF343OQUJ; component alt_dspbuilder_port_GNOC3SGKQJ is port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_port_GNOC3SGKQJ; component alt_dspbuilder_port_GN37ALZBS4 is port ( input : in std_logic := 'X'; -- wire output : out std_logic -- wire ); end component alt_dspbuilder_port_GN37ALZBS4; component Binarization_GN_Binarization_Binarization_Module is port ( Clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset data_out : out std_logic_vector(23 downto 0); -- wire addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire eop : in std_logic := 'X'; -- wire sop : in std_logic := 'X'; -- wire writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire write : in std_logic := 'X' -- wire ); end component Binarization_GN_Binarization_Binarization_Module; component alt_dspbuilder_port_GN6TDLHAW6 is port ( input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_port_GN6TDLHAW6; component alt_dspbuilder_port_GNEPKLLZKY is port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_port_GNEPKLLZKY; signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Binarization_Binarization_Module_0:sop] signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Binarization_Binarization_Module_0:eop] signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Binarization_Binarization_Module_0:addr signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Binarization_Binarization_Module_0:write signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Binarization_Binarization_Module_0:writedata signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Binarization_Binarization_Module_0:data_in signal binarization_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Binarization_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Binarization_Binarization_Module_0:aclr signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Binarization_Binarization_Module_0:Clock begin clock_0 : component alt_dspbuilder_clock_GNF343OQUJ port map ( clock_out => clock_0_clock_output_clk, -- clock_output.clk aclr_out => clock_0_clock_output_reset, -- .reset clock => Clock, -- clock.clk aclr_n => aclr -- .reset_n ); avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => Avalon_ST_Sink_data, -- input.wire output => avalon_st_sink_data_0_output_wire -- output.wire ); avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_endofpacket, -- input.wire output => avalon_st_sink_endofpacket_0_output_wire -- output.wire ); binarization_binarization_module_0 : component Binarization_GN_Binarization_Binarization_Module port map ( Clock => clock_0_clock_output_clk, -- Clock.clk aclr => clock_0_clock_output_reset, -- .reset data_out => binarization_binarization_module_0_data_out_wire, -- data_out.wire addr => avalon_mm_slave_address_0_output_wire, -- addr.wire eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire write => avalon_mm_slave_write_0_output_wire -- write.wire ); avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6 port map ( input => Avalon_MM_Slave_address, -- input.wire output => avalon_mm_slave_address_0_output_wire -- output.wire ); avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY port map ( input => Avalon_MM_Slave_writedata, -- input.wire output => avalon_mm_slave_writedata_0_output_wire -- output.wire ); avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_valid_0_output_wire, -- input.wire output => Avalon_ST_Source_valid -- output.wire ); avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_valid, -- input.wire output => avalon_st_sink_valid_0_output_wire -- output.wire ); avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire output => Avalon_ST_Source_endofpacket -- output.wire ); avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire output => Avalon_ST_Source_startofpacket -- output.wire ); avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Source_ready, -- input.wire output => avalon_st_source_ready_0_output_wire -- output.wire ); avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_MM_Slave_write, -- input.wire output => avalon_mm_slave_write_0_output_wire -- output.wire ); avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_source_ready_0_output_wire, -- input.wire output => Avalon_ST_Sink_ready -- output.wire ); avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_startofpacket, -- input.wire output => avalon_st_sink_startofpacket_0_output_wire -- output.wire ); avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => binarization_binarization_module_0_data_out_wire, -- input.wire output => Avalon_ST_Source_data -- output.wire ); end architecture rtl; -- of Binarization_GN	mit	11c452a355bc98d653e043a80606e2f7	0.581588	3.428666	false	false	false	false
TWW12/lzw	final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/sim/design_1_rst_ps7_0_100M_0.vhd	3	5,851	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 10 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_10; USE proc_sys_reset_v5_0_10.proc_sys_reset; ENTITY design_1_rst_ps7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END design_1_rst_ps7_0_100M_0; ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END design_1_rst_ps7_0_100M_0_arch;	unlicense	86cf7cdd302d8c9087f1458fad4afbbc	0.705691	3.541768	false	false	false	false
grwlf/vsim	vhdl_ct/ct00546.vhd	1	2,484	-- NEED RESULT: ARCH00546: Architectural library name visibility test failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00546 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.3 (11) -- 10.3 (13) -- -- DESIGN UNIT ORDERING: -- -- ENT00546(ARCH00546) -- ENT00546_Test_Bench(ARCH00546_Test_Bench) -- CONF00546 -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- 19-JAN-1987 - replaced selected name WORK.ARCH00546 with simple -- name ARCH00546 -- -- NOTES: -- -- self-checking -- -- entity ENT00546 is generic ( G : Integer := 0 ) ; port ( P1 : in Boolean ; P2 : out Boolean ) ; end ENT00546 ; -- architecture ARCH00546 of ENT00546 is begin process (P1) begin P2 <= transport Not P1 ; end process ; end ARCH00546 ; -- entity ENT00546_Test_Bench is end ENT00546_Test_Bench ; -- use WORK.STANDARD_TYPES.all ; architecture ARCH00546_Test_Bench of ENT00546_Test_Bench is signal S1, S2 : boolean := false ; signal S3 : boolean := true ; component Comp1 generic ( G : Integer := 0 ) ; port ( P1 : in boolean ; P2 : out boolean ) ; end component ; for CIS1 : Comp1 use entity WORK.ENT00546 ( ARCH00546 ); -- reference in binding indication component Comp2 port ( P1 : in boolean ; P2 : out boolean ) ; end component ; begin CIS1 : Comp1 generic map ( open ) port map ( S1, S2 ) ; Blk : block begin CIS1 : Comp2 port map ( S2, S3 ) ; end block Blk ; process begin wait for 10 ns ; test_report ( "ARCH00546" , "Architectural library name visibility test" , (Not S1) and S2 and (Not S3) ) ; wait ; end process ; end ARCH00546_Test_Bench ; -- configuration CONF00546 of WORK.ENT00546_Test_Bench is for ARCH00546_Test_Bench -- reference in a configuration for Blk for CIS1 : Comp2 use entity WORK.ENT00546 ( ARCH00546 ) -- reference in a binding indication generic map ( G => open ) port map ( P1, P2 ) ; end for ; end for ; end for ; end CONF00546 ; --	gpl-3.0	28581012b36d9f460849eee5c9471e39	0.531804	3.388813	false	true	false	false
wsoltys/AtomFpga	src/AtomGodilVideo/src/MINIUART/Txunit.vhd	1	3,291	------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : Txunit.vhd -- Author : Philippe CARTON -- ([email protected]) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164 ------------------------------------------------------------------------------- -- Description: Txunit is a parallel to serial unit transmitter. ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity TxUnit is port ( Clk : in std_logic; -- Clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input LoadA : in std_logic; -- Asynchronous Load TxD : out std_logic; -- RS-232 data output Busy : out std_logic; -- Tx Busy DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit end TxUnit; architecture Behaviour of TxUnit is component synchroniser port ( C1 : in std_logic; -- Asynchronous signal C : in std_logic; -- Clock O : out Std_logic);-- Synchronised signal end component; signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer signal TReg : std_logic_vector(7 downto 0); -- transmit register signal TBufL : std_logic; -- Buffer loaded signal LoadS : std_logic; -- Synchronised load signal begin -- Synchronise Load on Clk SyncLoad : Synchroniser port map (LoadA, Clk, LoadS); Busy <= LoadS or TBufL; -- Tx process TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL) variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame begin if Reset = '1' then TBufL <= '0'; BitPos := 0; TxD <= '1'; elsif Rising_Edge(Clk) then if LoadS = '1' then TBuff <= DataI; TBufL <= '1'; end if; if Enable = '1' then case BitPos is when 0 => -- idle or stop bit TxD <= '1'; if TBufL = '1' then -- start transmit. next is start bit TReg <= TBuff; TBufL <= '0'; BitPos := 1; end if; when 1 => -- Start bit TxD <= '0'; BitPos := 2; when others => TxD <= TReg(BitPos-2); -- Serialisation of TReg BitPos := BitPos + 1; end case; if BitPos = 10 then -- bit8. next is stop bit BitPos := 0; end if; end if; end if; end process; end Behaviour;	apache-2.0	86bd78425a7c2e5f7b53c529193e111b	0.463993	4.251938	false	false	false	false
jairov4/accel-oil	solution_kintex7/syn/vhdl/nfa_accept_sample.vhd	1	61,739	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_sample is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); empty : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of nfa_accept_sample is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal reg_374 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_reg_577 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_reg_582 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_s_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_597 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0); signal i_1_reg_601 : STD_LOGIC_VECTOR (15 downto 0); signal sample_addr_1_reg_606 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_17_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_i_reg_612 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_rec_reg_616 : STD_LOGIC_VECTOR (31 downto 0); signal sym_reg_621 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_1_i_reg_626 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_368_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal r_bit_reg_630 : STD_LOGIC_VECTOR (4 downto 0); signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 : STD_LOGIC_VECTOR (1 downto 0); signal j_bucket_index1_ph_cast_fu_436_p1 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_ph_cast_fu_440_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_7_i_cast_fu_444_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_i_cast_reg_650 : STD_LOGIC_VECTOR (13 downto 0); signal j_end_phi_fu_312_p4 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p2 : STD_LOGIC_VECTOR (5 downto 0); signal state_reg_665 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p2 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_6_i_reg_680 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_482_p2 : STD_LOGIC_VECTOR (13 downto 0); signal offset_i_reg_685 : STD_LOGIC_VECTOR (13 downto 0); signal j_bit_reg_701 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_index_reg_706 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_reg_711 : STD_LOGIC_VECTOR (31 downto 0); signal p_s_reg_716 : STD_LOGIC_VECTOR (0 downto 0); signal next_buckets_0_1_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_1_reg_721 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_1_fu_544_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_reg_731 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_1_reg_736 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_reg_741 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_fu_563_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_fu_568_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_756 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_p_read : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_r_bit : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_start : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_done : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_idle : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_ready : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_start : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_done : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_idle : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_ready : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_ce : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_ap_ce : STD_LOGIC; signal i_reg_134 : STD_LOGIC_VECTOR (15 downto 0); signal any_phi_fu_324_p4 : STD_LOGIC_VECTOR (0 downto 0); signal p_01_rec_reg_146 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_reg_158 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_reg_168 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_178 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_0_lcssa4_i_reg_190 : STD_LOGIC_VECTOR (0 downto 0); signal j_bucket1_ph_reg_203 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_ph_reg_216 : STD_LOGIC_VECTOR (1 downto 0); signal j_bit1_ph_reg_227 : STD_LOGIC_VECTOR (4 downto 0); signal j_end_ph_reg_238 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_buckets_1_3_reg_252 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_3_reg_265 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket1_reg_278 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_reg_289 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_reg_299 : STD_LOGIC_VECTOR (7 downto 0); signal j_end_reg_309 : STD_LOGIC_VECTOR (0 downto 0); signal any_reg_319 : STD_LOGIC_VECTOR (0 downto 0); signal p_0_reg_332 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_nfa_get_finals_fu_362_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_fu_392_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_4_i_cast_fu_493_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_i_cast_fu_511_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_402_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_402_p1 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_447_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p0 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_463_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_476_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_482_p0 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_482_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_4_i_fu_486_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_8_i_fu_504_p3 : STD_LOGIC_VECTOR (14 downto 0); signal grp_fu_392_ce : STD_LOGIC; signal grp_fu_402_ce : STD_LOGIC; signal grp_fu_414_ce : STD_LOGIC; signal grp_fu_463_ce : STD_LOGIC; signal grp_fu_476_ce : STD_LOGIC; signal grp_fu_482_ce : STD_LOGIC; signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal grp_fu_476_p00 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_476_p10 : STD_LOGIC_VECTOR (13 downto 0); component bitset_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_get_initials IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_get_finals IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (15 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (5 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (5 downto 0) ); end component; component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (7 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (13 downto 0); din1 : IN STD_LOGIC_VECTOR (13 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; begin grp_bitset_next_fu_344 : component bitset_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, p_read => grp_bitset_next_fu_344_p_read, r_bit => grp_bitset_next_fu_344_r_bit, r_bucket_index => grp_bitset_next_fu_344_r_bucket_index, r_bucket => grp_bitset_next_fu_344_r_bucket, ap_return_0 => grp_bitset_next_fu_344_ap_return_0, ap_return_1 => grp_bitset_next_fu_344_ap_return_1, ap_return_2 => grp_bitset_next_fu_344_ap_return_2, ap_return_3 => grp_bitset_next_fu_344_ap_return_3, ap_ce => grp_bitset_next_fu_344_ap_ce); grp_nfa_get_initials_fu_356 : component nfa_get_initials port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_initials_fu_356_ap_start, ap_done => grp_nfa_get_initials_fu_356_ap_done, ap_idle => grp_nfa_get_initials_fu_356_ap_idle, ap_ready => grp_nfa_get_initials_fu_356_ap_ready, nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_get_initials_fu_356_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_get_initials_fu_356_nfa_initials_buckets_size, ap_ce => grp_nfa_get_initials_fu_356_ap_ce, ap_return_0 => grp_nfa_get_initials_fu_356_ap_return_0, ap_return_1 => grp_nfa_get_initials_fu_356_ap_return_1); grp_nfa_get_finals_fu_362 : component nfa_get_finals port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_finals_fu_362_ap_start, ap_done => grp_nfa_get_finals_fu_362_ap_done, ap_idle => grp_nfa_get_finals_fu_362_ap_idle, ap_ready => grp_nfa_get_finals_fu_362_ap_ready, nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_get_finals_fu_362_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_get_finals_fu_362_nfa_finals_buckets_size, ap_ce => grp_nfa_get_finals_fu_362_ap_ce, ap_return_0 => grp_nfa_get_finals_fu_362_ap_return_0, ap_return_1 => grp_nfa_get_finals_fu_362_ap_return_1); grp_p_bsf32_hw_fu_368 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_368_bus_r, ap_return => grp_p_bsf32_hw_fu_368_ap_return, ap_ce => grp_p_bsf32_hw_fu_368_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 17, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_392_p0, din1 => grp_fu_392_p1, ce => grp_fu_392_ce, dout => grp_fu_392_p2); nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 generic map ( ID => 18, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 16, dout_WIDTH => 16) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_402_p0, din1 => grp_fu_402_p1, ce => grp_fu_402_ce, dout => grp_fu_402_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 19, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_414_p0, din1 => grp_fu_414_p1, ce => grp_fu_414_ce, dout => grp_fu_414_p2); nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 generic map ( ID => 20, NUM_STAGE => 2, din0_WIDTH => 6, din1_WIDTH => 6, dout_WIDTH => 6) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_463_p0, din1 => grp_fu_463_p1, ce => grp_fu_463_ce, dout => grp_fu_463_p2); nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 generic map ( ID => 21, NUM_STAGE => 4, din0_WIDTH => 8, din1_WIDTH => 6, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_476_p0, din1 => grp_fu_476_p1, ce => grp_fu_476_ce, dout => grp_fu_476_p2); nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 generic map ( ID => 22, NUM_STAGE => 4, din0_WIDTH => 14, din1_WIDTH => 14, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_482_p0, din1 => grp_fu_482_p1, ce => grp_fu_482_ce, dout => grp_fu_482_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_return_preg assign process. -- ap_return_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_return_preg <= ap_const_lv1_0; else if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_return_preg <= p_0_reg_332; end if; end if; end if; end process; -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st12_fsm_11 = ap_NS_fsm) and (ap_ST_st11_fsm_10 = ap_CS_fsm) and (tmp_s_reg_597 = ap_const_lv1_0))) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_362_ap_ready)) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- agg_result_bucket_index_0_lcssa4_i_reg_190 assign process. -- agg_result_bucket_index_0_lcssa4_i_reg_190_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0; end if; end if; end process; -- any_reg_319 assign process. -- any_reg_319_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_1; end if; end if; end process; -- bus_assign_reg_178 assign process. -- bus_assign_reg_178_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_1_reg_158; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_0_reg_168; end if; end if; end process; -- i_reg_134 assign process. -- i_reg_134_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then i_reg_134 <= i_1_reg_601; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then i_reg_134 <= ap_const_lv16_0; end if; end if; end process; -- j_bit1_reg_299 assign process. -- j_bit1_reg_299_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit_reg_701; end if; end if; end process; -- j_bucket1_ph_reg_203 assign process. -- j_bucket1_ph_reg_203_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket1_ph_reg_203 <= bus_assign_reg_178; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket1_ph_reg_203 <= ap_const_lv32_0; end if; end if; end process; -- j_bucket1_reg_278 assign process. -- j_bucket1_reg_278_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket1_ph_reg_203; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket_reg_711; end if; end if; end process; -- j_bucket_index1_ph_reg_216 assign process. -- j_bucket_index1_ph_reg_216_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket_index1_ph_reg_216 <= ap_const_lv2_2; end if; end if; end process; -- j_bucket_index1_reg_289 assign process. -- j_bucket_index1_reg_289_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index_reg_706; end if; end if; end process; -- j_end_ph_reg_238 assign process. -- j_end_ph_reg_238_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_end_ph_reg_238 <= ap_const_lv1_0; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_end_ph_reg_238 <= ap_const_lv1_1; end if; end if; end process; -- j_end_reg_309 assign process. -- j_end_reg_309_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_end_reg_309 <= j_end_ph_reg_238; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_end_reg_309 <= p_s_reg_716; end if; end if; end process; -- next_buckets_0_reg_168 assign process. -- next_buckets_0_reg_168_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_0_reg_168 <= current_buckets_0_reg_577; end if; end if; end process; -- next_buckets_1_reg_158 assign process. -- next_buckets_1_reg_158_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_1_reg_158 <= current_buckets_1_reg_582; end if; end if; end process; -- p_01_rec_reg_146 assign process. -- p_01_rec_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then p_01_rec_reg_146 <= p_rec_reg_616; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then p_01_rec_reg_146 <= ap_const_lv32_0; end if; end if; end process; -- p_0_reg_332 assign process. -- p_0_reg_332_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then p_0_reg_332 <= ap_const_lv1_0; elsif ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then p_0_reg_332 <= tmp_2_reg_756; end if; end if; end process; -- tmp_buckets_0_3_reg_265 assign process. -- tmp_buckets_0_3_reg_265_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= ap_const_lv32_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721; end if; end if; end process; -- tmp_buckets_1_3_reg_252 assign process. -- tmp_buckets_1_3_reg_252_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= ap_const_lv32_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2; current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0; current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then i_1_reg_601 <= grp_fu_402_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bit1_ph_reg_227 <= r_bit_reg_630; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then j_bit_reg_701 <= grp_bitset_next_fu_344_ap_return_0; j_bucket_index_reg_706 <= grp_bitset_next_fu_344_ap_return_1; j_bucket_reg_711 <= grp_bitset_next_fu_344_ap_return_2; p_s_reg_716 <= grp_bitset_next_fu_344_ap_return_3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm))) then next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then offset_i_reg_685 <= grp_fu_482_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then p_rec_reg_616 <= grp_fu_414_p2; sym_reg_621 <= sample_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then reg_374 <= nfa_forward_buckets_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then sample_addr_1_reg_606 <= grp_fu_392_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then state_reg_665 <= grp_fu_463_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then tmp_17_1_i_reg_626 <= tmp_17_1_i_fu_426_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then tmp_17_i_reg_612 <= tmp_17_i_fu_420_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then tmp_1_reg_751 <= tmp_1_fu_568_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then tmp_2_reg_756 <= tmp_2_fu_572_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then tmp_6_i_reg_680 <= grp_fu_476_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_7_i_cast_reg_650(0) <= tmp_7_i_cast_fu_444_p1(0); tmp_7_i_cast_reg_650(1) <= tmp_7_i_cast_fu_444_p1(1); tmp_7_i_cast_reg_650(2) <= tmp_7_i_cast_fu_444_p1(2); tmp_7_i_cast_reg_650(3) <= tmp_7_i_cast_fu_444_p1(3); tmp_7_i_cast_reg_650(4) <= tmp_7_i_cast_fu_444_p1(4); tmp_7_i_cast_reg_650(5) <= tmp_7_i_cast_fu_444_p1(5); tmp_7_i_cast_reg_650(6) <= tmp_7_i_cast_fu_444_p1(6); tmp_7_i_cast_reg_650(7) <= tmp_7_i_cast_fu_444_p1(7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0; tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then tmp_s_reg_597 <= tmp_s_fu_397_p2; end if; end if; end process; tmp_7_i_cast_reg_650(13 downto 8) <= "000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_597 , tmp_17_i_reg_612 , tmp_17_1_i_reg_626 , j_end_phi_fu_312_p4 , any_phi_fu_324_p4) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => if ((tmp_s_reg_597 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st39_fsm_38; else ap_NS_fsm <= ap_ST_st13_fsm_12; end if; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st21_fsm_20; elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st20_fsm_19; else ap_NS_fsm <= ap_ST_st19_fsm_18; end if; when ap_ST_st20_fsm_19 => if (not((tmp_17_1_i_reg_626 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st24_fsm_23; else ap_NS_fsm <= ap_ST_st21_fsm_20; end if; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => if ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then ap_NS_fsm <= ap_ST_st5_fsm_4; elsif ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then ap_NS_fsm <= ap_ST_st45_fsm_44; else ap_NS_fsm <= ap_ST_st26_fsm_25; end if; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st37_fsm_36; else ap_NS_fsm <= ap_ST_st36_fsm_35; end if; when ap_ST_st37_fsm_36 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st38_fsm_37; else ap_NS_fsm <= ap_ST_st37_fsm_36; end if; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st43_fsm_42; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st44_fsm_43; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190),2)); any_phi_fu_324_p4 <= any_reg_319; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st45_fsm_44 = ap_CS_fsm))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_return assign process. -- ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_332, ap_return_preg) begin if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_return <= p_0_reg_332; else ap_return <= ap_return_preg; end if; end process; current_buckets_0_1_fu_558_p2 <= (next_buckets_0_reg_168 and tmp_buckets_0_reg_731); current_buckets_1_1_fu_563_p2 <= (next_buckets_1_reg_158 and tmp_buckets_1_reg_736); -- grp_bitset_next_fu_344_ap_ce assign process. -- grp_bitset_next_fu_344_ap_ce_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, j_end_phi_fu_312_p4) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st25_fsm_24 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_312_p4)) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then grp_bitset_next_fu_344_ap_ce <= ap_const_logic_1; else grp_bitset_next_fu_344_ap_ce <= ap_const_logic_0; end if; end process; grp_bitset_next_fu_344_p_read <= next_buckets_1_reg_158; grp_bitset_next_fu_344_r_bit <= j_bit1_reg_299; grp_bitset_next_fu_344_r_bucket <= j_bucket1_reg_278; grp_bitset_next_fu_344_r_bucket_index <= j_bucket_index1_reg_289; grp_fu_392_ce <= ap_const_logic_1; grp_fu_392_p0 <= p_01_rec_reg_146; grp_fu_392_p1 <= empty; grp_fu_402_ce <= ap_const_logic_1; grp_fu_402_p0 <= i_reg_134; grp_fu_402_p1 <= ap_const_lv16_1; -- grp_fu_414_ce assign process. -- grp_fu_414_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_597) begin if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((tmp_s_reg_597 = ap_const_lv1_0))) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm))) then grp_fu_414_ce <= ap_const_logic_1; else grp_fu_414_ce <= ap_const_logic_0; end if; end process; grp_fu_414_p0 <= p_01_rec_reg_146; grp_fu_414_p1 <= ap_const_lv32_1; grp_fu_463_ce <= ap_const_logic_1; grp_fu_463_p0 <= (tmp_5_fu_447_p1 & ap_const_lv5_0); grp_fu_463_p1 <= j_bit1_reg_299(6 - 1 downto 0); grp_fu_476_ce <= ap_const_logic_1; grp_fu_476_p0 <= grp_fu_476_p00(8 - 1 downto 0); grp_fu_476_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14)); grp_fu_476_p1 <= grp_fu_476_p10(6 - 1 downto 0); grp_fu_476_p10 <= std_logic_vector(resize(unsigned(state_reg_665),14)); grp_fu_482_ce <= ap_const_logic_1; grp_fu_482_p0 <= tmp_6_i_reg_680; grp_fu_482_p1 <= tmp_7_i_cast_reg_650; grp_nfa_get_finals_fu_362_ap_ce <= ap_const_logic_1; grp_nfa_get_finals_fu_362_ap_start <= grp_nfa_get_finals_fu_362_ap_start_ap_start_reg; grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_get_initials_fu_356_ap_ce <= ap_const_logic_1; -- grp_nfa_get_initials_fu_356_ap_start assign process. -- grp_nfa_get_initials_fu_356_ap_start_assign_proc : process(ap_start, ap_CS_fsm) begin if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_1; else grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_0; end if; end process; grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; -- grp_p_bsf32_hw_fu_368_ap_ce assign process. -- grp_p_bsf32_hw_fu_368_ap_ce_assign_proc : process(ap_CS_fsm) begin if (((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_0; end if; end process; grp_p_bsf32_hw_fu_368_bus_r <= bus_assign_reg_178; j_bit1_ph_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_227),8)); j_bucket_index1_ph_cast_fu_436_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_216),8)); j_end_phi_fu_312_p4 <= j_end_reg_309; next_buckets_0_1_fu_538_p2 <= (tmp_buckets_0_3_reg_265 or reg_374); next_buckets_1_1_fu_544_p2 <= (tmp_buckets_1_3_reg_252 or reg_374); nfa_finals_buckets_address <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_size; -- nfa_forward_buckets_address assign process. -- nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, tmp_4_i_cast_fu_493_p1, tmp_8_i_cast_fu_511_p1) begin if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then nfa_forward_buckets_address <= tmp_8_i_cast_fu_511_p1; elsif ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then nfa_forward_buckets_address <= tmp_4_i_cast_fu_493_p1; else nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_forward_buckets_dataout <= ap_const_lv32_0; nfa_forward_buckets_req_din <= ap_const_logic_0; -- nfa_forward_buckets_req_write assign process. -- nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then nfa_forward_buckets_req_write <= ap_const_logic_1; else nfa_forward_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_forward_buckets_rsp_read assign process. -- nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then nfa_forward_buckets_rsp_read <= ap_const_logic_1; else nfa_forward_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_forward_buckets_size <= ap_const_lv32_1; nfa_initials_buckets_address <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_size; sample_address <= sample_addr_1_reg_606; sample_dataout <= ap_const_lv8_0; sample_req_din <= ap_const_logic_0; -- sample_req_write assign process. -- sample_req_write_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then sample_req_write <= ap_const_logic_1; else sample_req_write <= ap_const_logic_0; end if; end process; -- sample_rsp_read assign process. -- sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n) begin if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then sample_rsp_read <= ap_const_logic_1; else sample_rsp_read <= ap_const_logic_0; end if; end process; sample_size <= ap_const_lv32_1; tmp_17_1_i_fu_426_p2 <= "1" when (next_buckets_1_reg_158 = ap_const_lv32_0) else "0"; tmp_17_i_fu_420_p2 <= "1" when (next_buckets_0_reg_168 = ap_const_lv32_0) else "0"; tmp_1_fu_568_p2 <= (current_buckets_1_1_reg_746 or current_buckets_0_1_reg_741); tmp_2_fu_572_p2 <= "0" when (tmp_1_reg_751 = ap_const_lv32_0) else "1"; tmp_4_i_cast_fu_493_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_486_p3),32)); tmp_4_i_fu_486_p3 <= (offset_i_reg_685 & ap_const_lv1_0); tmp_5_fu_447_p1 <= j_bucket_index1_reg_289(1 - 1 downto 0); tmp_7_i_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(sym_reg_621),14)); tmp_8_i_cast_fu_511_p1 <= std_logic_vector(resize(unsigned(tmp_8_i_fu_504_p3),32)); tmp_8_i_fu_504_p3 <= (offset_i_reg_685 & ap_const_lv1_1); tmp_s_fu_397_p2 <= "1" when (unsigned(i_reg_134) < unsigned(length_r)) else "0"; end behav;	lgpl-3.0	4af02bf1ea3790bf448598a1780ac021	0.579488	2.764103	false	false	false	false
jairov4/accel-oil	impl/impl_test_pcie/hdl/system_clock_generator_0_wrapper.vhd	1	3,263	------------------------------------------------------------------------------- -- system_clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_03_a; use clock_generator_0_v4_03_a.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_clock_generator_0_wrapper : entity is "clock_generator_v4_03_a"; end system_clock_generator_0_wrapper; architecture STRUCTURE of system_clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "virtex5", C_DEVICE => "5vlx50t", C_PACKAGE => "ff1136", C_SPEEDGRADE => "-1" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;	lgpl-3.0	94f5ef2ff125e819d8d5a454e755cf45	0.57585	3.637681	false	false	false	false
jairov4/accel-oil	impl/impl_test_pcie/simulation/behavioral/system_ac1_plb_wrapper.vhd	1	14,574	------------------------------------------------------------------------------- -- system_ac1_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end system_ac1_plb_wrapper; architecture STRUCTURE of system_ac1_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERSC_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERSC_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin ac1_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 15, C_PLBV46_NUM_SLAVES => 1, C_PLBV46_MID_WIDTH => 4, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;	lgpl-3.0	2e22b972707dbfb2d46e9ba2d0caf8ef	0.611157	3.041954	false	false	false	false
wsoltys/AtomFpga	src/AtomGodilVideo/src/DCM/DCMSID1.vhd	1	2,037	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity DCMSID1 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end DCMSID1; architecture BEHAVIORAL of DCMSID1 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, CLKFX_DIVIDE => 12, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 65.1, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => CLK2X_OUT, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;	apache-2.0	56c424e6dae00a525802dfae58d64b2c	0.405989	4.306554	false	false	false	false
jairov4/accel-oil	solution_spartan3/impl/vhdl/nfa_accept_samples_generic_hw.vhd	1	92,188	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_req_din : OUT STD_LOGIC; sample_buffer_req_full_n : IN STD_LOGIC; sample_buffer_req_write : OUT STD_LOGIC; sample_buffer_rsp_empty_n : IN STD_LOGIC; sample_buffer_rsp_read : OUT STD_LOGIC; sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_size : IN STD_LOGIC_VECTOR (15 downto 0); begin_index : IN STD_LOGIC_VECTOR (15 downto 0); begin_sample : IN STD_LOGIC_VECTOR (15 downto 0); end_index : IN STD_LOGIC_VECTOR (15 downto 0); end_sample : IN STD_LOGIC_VECTOR (15 downto 0); stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0); accept : IN STD_LOGIC_VECTOR (0 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_accept_samples_generic_hw is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc3s200avq100-5,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.449000,HLS_SYN_LAT=154790016,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100"; constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (5 downto 0) := "101101"; constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (5 downto 0) := "101110"; constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (5 downto 0) := "101111"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_315 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_reg_320 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_fu_240_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_reg_325 : STD_LOGIC_VECTOR (0 downto 0); signal c_load_reg_329 : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_return : STD_LOGIC_VECTOR (31 downto 0); signal offset_reg_335 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal r_reg_340 : STD_LOGIC_VECTOR (0 downto 0); signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC; signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_345 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_251_p2 : STD_LOGIC_VECTOR (31 downto 0); signal c_1_reg_349 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_tmp_14 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_start : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_done : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_idle : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_ready : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_ce : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_length : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_start : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_done : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_idle : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_ready : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_ap_ce : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0); signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0); signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_sample_iterator_next_fu_211_ap_start_ap_start_reg : STD_LOGIC := '0'; signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_ce : STD_LOGIC; component nfa_accept_sample IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component sample_iterator_get_offset IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sample_iterator_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_nfa_accept_sample_fu_178 : component nfa_accept_sample port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_accept_sample_fu_178_ap_start, ap_done => grp_nfa_accept_sample_fu_178_ap_done, ap_idle => grp_nfa_accept_sample_fu_178_ap_idle, ap_ready => grp_nfa_accept_sample_fu_178_ap_ready, nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size, nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size, nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din, nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n, nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write, nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n, nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read, nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address, nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain, nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout, nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size, nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols, sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din, sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n, sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write, sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n, sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read, sample_address => grp_nfa_accept_sample_fu_178_sample_address, sample_datain => grp_nfa_accept_sample_fu_178_sample_datain, sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout, sample_size => grp_nfa_accept_sample_fu_178_sample_size, tmp_14 => grp_nfa_accept_sample_fu_178_tmp_14, length_r => grp_nfa_accept_sample_fu_178_length_r, ap_return => grp_nfa_accept_sample_fu_178_ap_return); grp_sample_iterator_get_offset_fu_194 : component sample_iterator_get_offset port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_get_offset_fu_194_ap_start, ap_done => grp_sample_iterator_get_offset_fu_194_ap_done, ap_idle => grp_sample_iterator_get_offset_fu_194_ap_idle, ap_ready => grp_sample_iterator_get_offset_fu_194_ap_ready, indices_stride_req_din => grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_get_offset_fu_194_indices_stride_address, indices_stride_datain => grp_sample_iterator_get_offset_fu_194_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, indices_stride_size => grp_sample_iterator_get_offset_fu_194_indices_stride_size, indices_begin_req_din => grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_get_offset_fu_194_indices_begin_address, indices_begin_datain => grp_sample_iterator_get_offset_fu_194_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, indices_begin_size => grp_sample_iterator_get_offset_fu_194_indices_begin_size, ap_ce => grp_sample_iterator_get_offset_fu_194_ap_ce, i_index => grp_sample_iterator_get_offset_fu_194_i_index, i_sample => grp_sample_iterator_get_offset_fu_194_i_sample, indices_samples_req_din => grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_get_offset_fu_194_indices_samples_address, indices_samples_datain => grp_sample_iterator_get_offset_fu_194_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, indices_samples_size => grp_sample_iterator_get_offset_fu_194_indices_samples_size, sample_buffer_size => grp_sample_iterator_get_offset_fu_194_sample_buffer_size, sample_length => grp_sample_iterator_get_offset_fu_194_sample_length, ap_return => grp_sample_iterator_get_offset_fu_194_ap_return); grp_sample_iterator_next_fu_211 : component sample_iterator_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_next_fu_211_ap_start, ap_done => grp_sample_iterator_next_fu_211_ap_done, ap_idle => grp_sample_iterator_next_fu_211_ap_idle, ap_ready => grp_sample_iterator_next_fu_211_ap_ready, indices_samples_req_din => grp_sample_iterator_next_fu_211_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_next_fu_211_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_next_fu_211_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_next_fu_211_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_next_fu_211_indices_samples_address, indices_samples_datain => grp_sample_iterator_next_fu_211_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_next_fu_211_indices_samples_dataout, indices_samples_size => grp_sample_iterator_next_fu_211_indices_samples_size, ap_ce => grp_sample_iterator_next_fu_211_ap_ce, indices_begin_req_din => grp_sample_iterator_next_fu_211_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_next_fu_211_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_next_fu_211_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_next_fu_211_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_next_fu_211_indices_begin_address, indices_begin_datain => grp_sample_iterator_next_fu_211_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_next_fu_211_indices_begin_dataout, indices_begin_size => grp_sample_iterator_next_fu_211_indices_begin_size, indices_stride_req_din => grp_sample_iterator_next_fu_211_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_next_fu_211_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_next_fu_211_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_next_fu_211_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_next_fu_211_indices_stride_address, indices_stride_datain => grp_sample_iterator_next_fu_211_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_next_fu_211_indices_stride_dataout, indices_stride_size => grp_sample_iterator_next_fu_211_indices_stride_size, i_index => grp_sample_iterator_next_fu_211_i_index, i_sample => grp_sample_iterator_next_fu_211_i_sample, ap_return_0 => grp_sample_iterator_next_fu_211_ap_return_0, ap_return_1 => grp_sample_iterator_next_fu_211_ap_return_1); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 38, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_251_p0, din1 => grp_fu_251_p1, ce => grp_fu_251_ce, dout => grp_fu_251_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; else if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg assign process. -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_240_p2 = ap_const_lv1_0))) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_194_ap_ready)) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg assign process. -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st36_fsm_35 = ap_NS_fsm) and ((ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm)))) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_211_ap_ready)) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- c_fu_94 assign process. -- c_fu_94_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and (or_cond_reg_345 = ap_const_lv1_0))) then c_fu_94 <= c_1_reg_349; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then c_fu_94 <= ap_const_lv32_0; end if; end if; end process; -- i_index_reg_146 assign process. -- i_index_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st47_fsm_46 = ap_CS_fsm)) then i_index_reg_146 <= grp_sample_iterator_next_fu_211_ap_return_0; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_index_reg_146 <= begin_index; end if; end if; end process; -- i_sample_reg_156 assign process. -- i_sample_reg_156_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st47_fsm_46 = ap_CS_fsm)) then i_sample_reg_156 <= grp_sample_iterator_next_fu_211_ap_return_1; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_sample_reg_156 <= begin_sample; end if; end if; end process; -- p_0_reg_166 assign process. -- p_0_reg_166_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st28_fsm_27 = ap_CS_fsm) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then p_0_reg_166 <= ap_const_lv32_1; elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_325 = ap_const_lv1_0)))) then p_0_reg_166 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then c_1_reg_349 <= grp_fu_251_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then c_load_reg_329 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then offset_reg_335 <= grp_sample_iterator_get_offset_fu_194_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st28_fsm_27 = ap_CS_fsm)) then or_cond_reg_345 <= or_cond_fu_247_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st27_fsm_26 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then r_reg_340 <= grp_nfa_accept_sample_fu_178_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then tmp_i_10_reg_320 <= tmp_i_10_fu_235_p2; tmp_i_reg_315 <= tmp_i_fu_230_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then tmp_i_11_reg_325 <= tmp_i_11_fu_240_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , tmp_i_11_reg_325 , grp_nfa_accept_sample_fu_178_ap_done , or_cond_fu_247_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => if (not((tmp_i_11_reg_325 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st48_fsm_47; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done))) then ap_NS_fsm <= ap_ST_st28_fsm_27; else ap_NS_fsm <= ap_ST_st27_fsm_26; end if; when ap_ST_st28_fsm_27 => if ((not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st48_fsm_47; elsif (((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st29_fsm_28; else ap_NS_fsm <= ap_ST_st36_fsm_35; end if; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st43_fsm_42; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st44_fsm_43; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => ap_NS_fsm <= ap_ST_st46_fsm_45; when ap_ST_st46_fsm_45 => ap_NS_fsm <= ap_ST_st47_fsm_46; when ap_ST_st47_fsm_46 => ap_NS_fsm <= ap_ST_st2_fsm_1; when ap_ST_st48_fsm_47 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= p_0_reg_166; grp_fu_251_ce <= ap_const_logic_1; grp_fu_251_p0 <= c_load_reg_329; grp_fu_251_p1 <= ap_const_lv32_1; grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg; grp_nfa_accept_sample_fu_178_length_r <= sample_length; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols; grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain; grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n; grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n; grp_nfa_accept_sample_fu_178_tmp_14 <= offset_reg_335; grp_sample_iterator_get_offset_fu_194_ap_ce <= ap_const_logic_1; grp_sample_iterator_get_offset_fu_194_ap_start <= grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg; grp_sample_iterator_get_offset_fu_194_i_index <= i_index_reg_146; grp_sample_iterator_get_offset_fu_194_i_sample <= i_sample_reg_156; grp_sample_iterator_get_offset_fu_194_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_sample_buffer_size <= sample_buffer_length; grp_sample_iterator_get_offset_fu_194_sample_length <= sample_length; grp_sample_iterator_next_fu_211_ap_ce <= ap_const_logic_1; grp_sample_iterator_next_fu_211_ap_start <= grp_sample_iterator_next_fu_211_ap_start_ap_start_reg; grp_sample_iterator_next_fu_211_i_index <= i_index_reg_146; grp_sample_iterator_next_fu_211_i_sample <= i_sample_reg_156; grp_sample_iterator_next_fu_211_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_next_fu_211_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_next_fu_211_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_next_fu_211_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; -- indices_begin_address assign process. -- indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_address, grp_sample_iterator_next_fu_211_indices_begin_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_next_fu_211_indices_begin_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_get_offset_fu_194_indices_begin_address; else indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_dataout assign process. -- indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, grp_sample_iterator_next_fu_211_indices_begin_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_next_fu_211_indices_begin_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_get_offset_fu_194_indices_begin_dataout; else indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_req_din assign process. -- indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, grp_sample_iterator_next_fu_211_indices_begin_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_next_fu_211_indices_begin_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_din; else indices_begin_req_din <= 'X'; end if; end process; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, grp_sample_iterator_next_fu_211_indices_begin_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_next_fu_211_indices_begin_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_write; else indices_begin_req_write <= 'X'; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, grp_sample_iterator_next_fu_211_indices_begin_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_next_fu_211_indices_begin_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read; else indices_begin_rsp_read <= 'X'; end if; end process; -- indices_begin_size assign process. -- indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_size, grp_sample_iterator_next_fu_211_indices_begin_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_next_fu_211_indices_begin_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_get_offset_fu_194_indices_begin_size; else indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_address assign process. -- indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_address, grp_sample_iterator_next_fu_211_indices_samples_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_next_fu_211_indices_samples_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_get_offset_fu_194_indices_samples_address; else indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_dataout assign process. -- indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, grp_sample_iterator_next_fu_211_indices_samples_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_next_fu_211_indices_samples_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_get_offset_fu_194_indices_samples_dataout; else indices_samples_dataout <= "XXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_req_din assign process. -- indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, grp_sample_iterator_next_fu_211_indices_samples_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_next_fu_211_indices_samples_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_din; else indices_samples_req_din <= 'X'; end if; end process; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, grp_sample_iterator_next_fu_211_indices_samples_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_next_fu_211_indices_samples_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_write; else indices_samples_req_write <= 'X'; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, grp_sample_iterator_next_fu_211_indices_samples_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_next_fu_211_indices_samples_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read; else indices_samples_rsp_read <= 'X'; end if; end process; -- indices_samples_size assign process. -- indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_size, grp_sample_iterator_next_fu_211_indices_samples_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_next_fu_211_indices_samples_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_get_offset_fu_194_indices_samples_size; else indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_address assign process. -- indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_address, grp_sample_iterator_next_fu_211_indices_stride_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_next_fu_211_indices_stride_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_get_offset_fu_194_indices_stride_address; else indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_dataout assign process. -- indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, grp_sample_iterator_next_fu_211_indices_stride_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_next_fu_211_indices_stride_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_get_offset_fu_194_indices_stride_dataout; else indices_stride_dataout <= "XXXXXXXX"; end if; end process; -- indices_stride_req_din assign process. -- indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, grp_sample_iterator_next_fu_211_indices_stride_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_next_fu_211_indices_stride_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_din; else indices_stride_req_din <= 'X'; end if; end process; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, grp_sample_iterator_next_fu_211_indices_stride_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_next_fu_211_indices_stride_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_write; else indices_stride_req_write <= 'X'; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, grp_sample_iterator_next_fu_211_indices_stride_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_next_fu_211_indices_stride_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read; else indices_stride_rsp_read <= 'X'; end if; end process; -- indices_stride_size assign process. -- indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_size, grp_sample_iterator_next_fu_211_indices_stride_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_next_fu_211_indices_stride_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_get_offset_fu_194_indices_stride_size; else indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size; nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address; nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout; nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din; nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write; nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read; nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size; nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size; or_cond_fu_247_p2 <= (r_reg_340 xor accept); sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address; sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout; sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din; sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write; sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read; sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size; stop_on_first_read_read_fu_104_p2 <= stop_on_first; tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0"; tmp_i_11_fu_240_p2 <= (tmp_i_reg_315 and tmp_i_10_reg_320); tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0"; end behav;	lgpl-3.0	9001108ec1c639fbaf3680f82f61aaf8	0.640376	2.593557	false	false	false	false
wsoltys/AtomFpga	src/Atomic_top_papilio.vhd	1	9,115	-------------------------------------------------------------------------------- -- Copyright (c) 2009 Alan Daly. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : Atomic_top.vhf -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: Atomic_top --Device: spartan3E library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity Atomic_top_papilio is port (clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERST : in std_logic; red : out std_logic_vector (2 downto 0); green : out std_logic_vector (2 downto 0); blue : out std_logic_vector (2 downto 0); vsync : out std_logic; hsync : out std_logic; audiol : out std_logic; audioR : out std_logic; SDMISO : in std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; RxD : in std_logic; TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic; LED3 : out std_logic; LED4 : out std_logic ); end Atomic_top_papilio; architecture behavioral of Atomic_top_papilio is component dcm4 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component dcm5 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component RAM_2K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (10 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component RAM_8K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (12 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component InternalROM port ( CLK : in std_logic; ADDR : in std_logic_vector(16 downto 0); DATA : out std_logic_vector(7 downto 0) ); end component; component fpgautils port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component Atomic_core generic ( CImplSDDOS : boolean; CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; MainClockSpeed : integer; DefaultBaud : integer ); port ( clk_vga : in std_logic; clk_16M00 : in std_logic; clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERSTn : in std_logic; IRSTn : out std_logic; SDMISO : in std_logic; red : out std_logic_vector(2 downto 0); green : out std_logic_vector(2 downto 0); blue : out std_logic_vector(2 downto 0); vsync : out std_logic; hsync : out std_logic; RamCE : out std_logic; RomCE : out std_logic; Phi2 : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (16 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0); audiol : out std_logic; audioR : out std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; uart_RxD : in std_logic; uart_TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic ); end component; signal clk_vga : std_logic; signal clk_16M00 : std_logic; signal ERSTn : std_logic; signal RamCE : std_logic; signal RomCE : std_logic; signal RomCE1 : std_logic; signal RomCE2 : std_logic; signal RamCE1 : std_logic; signal RamCE2 : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector (16 downto 0); signal ExternDin : std_logic_vector (7 downto 0); signal ExternDout: std_logic_vector (7 downto 0); signal RamDout1 : std_logic_vector (7 downto 0); signal RamDout2 : std_logic_vector (7 downto 0); signal RomDout1 : std_logic_vector (7 downto 0); signal RomDout2 : std_logic_vector (7 downto 0); begin inst_dcm4 : dcm4 port map( CLKIN_IN => clk_32M00, CLK0_OUT => clk_vga, CLK0_OUT1 => open, CLK2X_OUT => open); inst_dcm5 : dcm5 port map( CLKIN_IN => clk_32M00, CLK0_OUT => clk_16M00, CLK0_OUT1 => open, CLK2X_OUT => open); ram_0000_07ff : RAM_2K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE1, addr_uP => ExternA (10 downto 0), D_uP => ExternDin, Q_uP => RamDout1 ); ram_2000_3fff : RAM_8K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE2, addr_uP => ExternA (12 downto 0), D_uP => ExternDin, Q_uP => RamDout2 ); rom_c000_ffff : InternalROM port map( CLK => clk_16M00, ADDR => ExternA, DATA => RomDout1 ); rom_a000 : fpgautils port map( CLK => clk_16M00, ADDR => ExternA(11 downto 0), DATA => RomDout2 ); RamCE1 <= '1' when RamCE = '1' and ExternA(14 downto 11) = "0000" else '0'; RamCE2 <= '1' when RamCE = '1' and ExternA(14 downto 13) = "01" else '0'; RomCE1 <= '1' when RomCE = '1' and ExternA(15 downto 14) = "11" else '0'; RomCE2 <= '1' when RomCE = '1' and ExternA(15 downto 12) = "1010" else '0'; ExternDout(7 downto 0) <= RamDout1 when RamCE1 = '1' else RamDout2 when RamCE2 = '1' else RomDout1 when RomCE1 = '1' else RomDout2 when RomCE2 = '1' else "11110001"; ERSTn <= not ERST; inst_Atomic_core : Atomic_core generic map ( CImplSDDOS => true, CImplGraphicsExt => true, CImplSoftChar => false, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, MainClockSpeed => 16000000, DefaultBaud => 115200 ) port map( clk_vga => clk_vga, clk_16M00 => clk_16M00, clk_32M00 => clk_32M00, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_mouse_clk => ps2_mouse_clk, ps2_mouse_data => ps2_mouse_data, ERSTn => ERSTn, red => red, green => green, blue => blue, vsync => vsync, hsync => hsync, Phi2 => open, RamCE => RamCE, RomCE => RomCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout=> ExternDout, audiol => audiol, audioR => audioR, SDMISO => SDMISO, SDSS => SDSS, SDCLK => SDCLK, SDMOSI => SDMOSI, uart_RxD => RxD, uart_TxD => TxD, LED1 => LED1, LED2 => LED2 ); LED3 <= '0'; LED4 <= '0'; end behavioral;	apache-2.0	99ad0e800dab96145c1b184b6e6c0b89	0.451454	3.643086	false	false	false	false
jairov4/accel-oil	solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/sample_buffer_if_ap_fifo.vhd	2	2,831	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sample_buffer_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC := '1'; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC := '1'; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of sample_buffer_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;	lgpl-3.0	3507e094a5f76efd4b35a193bb707c7f	0.494172	3.671855	false	false	false	false
wsoltys/AtomFpga	src/AVR8/CommonPacks/std_library.vhd	1	10,374	-- *************************************************************************************** -- Standard libraries -- Version 0.2 -- Modified 02.12.2006 -- Designed by Ruslan Lepetenok -- ************************************************************************************* library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package std_library is type log2array_type is array(0 to 1024) of integer; constant fn_log2 : log2array_type := ( 0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, others => 10); constant fn_log2x : log2array_type := ( 0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, others => 10); -- ***************************************************************************** function fn_det_x(d : std_logic_vector) return boolean; function fn_det_x(d : std_logic) return boolean; function fn_xor_vect(vect : std_logic_vector) return std_logic; function fn_or_vect(vect : std_logic_vector) return std_logic; function fn_and_vect(vect : std_logic_vector) return std_logic; function fn_to_integer(vect : std_logic_vector) return integer; function fn_to_integer(d : std_logic) return integer; function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector; function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector; function fn_to_std_logic(b : boolean) return std_logic; function fn_dcd(vect : std_logic_vector) return std_logic_vector; function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic; function "+" (vect : std_logic_vector; int : integer) return std_logic_vector; function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector; function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector; function "-" (vect : std_logic_vector; int : integer) return std_logic_vector; function "-" (int : integer; vect : std_logic_vector) return std_logic_vector; function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector; function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector; end std_library; package body std_library is function fn_det_x(d : std_logic_vector) return boolean is variable result : boolean; begin result := FALSE; -- pragma translate_off result := is_x(d); -- pragma translate_on return (result); end fn_det_x; function fn_det_x(d : std_logic) return boolean is variable result : boolean; begin result := FALSE; -- pragma translate_off result := is_x(d); -- pragma translate_on return (result); end fn_det_x; function fn_xor_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '0'; for i in vect'range loop temp := temp xor vect(i); end loop; return(temp); end fn_xor_vect; function fn_or_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '0'; for i in vect'range loop temp := temp or vect(i); end loop; return(temp); end fn_or_vect; function fn_and_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '1'; for i in vect'range loop temp := temp and vect(i); end loop; return(temp); end fn_and_vect; function fn_to_integer(vect : std_logic_vector) return integer is begin if (not fn_det_x(vect)) then return(to_integer(unsigned(vect))); else return(0); end if; end fn_to_integer; function fn_to_integer(d : std_logic) return integer is begin if (not fn_det_x(d)) then if (d = '1') then return(1); else return(0); end if; else return(0); end if; end fn_to_integer; function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is variable temp : std_logic_vector(width-1 downto 0); begin temp := std_logic_vector(to_unsigned(int, width)); return(temp); end fn_to_std_logic_vector; function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is variable temp : std_logic_vector(width-1 downto 0); begin temp := std_logic_vector(to_signed(int, width)); return(temp); end fn_to_std_logic_vector_signed; function fn_to_std_logic(b : boolean) return std_logic is begin if (b) then return('1'); else return('0'); end if; end fn_to_std_logic; function fn_dcd(vect : std_logic_vector) return std_logic_vector is variable result : std_logic_vector((2vect'length)-1 downto 0); variable i : integer range result'range; begin result := (others => '0'); i := 0; if (not fn_det_x(vect)) then i := to_integer(unsigned(vect)); end if; result(i) := '1'; return(result); end fn_dcd; function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is variable result : std_logic_vector(vect'length-1 downto 0); variable i : integer range result'range; begin result := vect; i := 0; if (not fn_det_x(sel)) then i := to_integer(unsigned(sel)); end if; return(result(i)); end fn_mux; -- >>>> function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is variable tmp_a : std_logic_vector(vect_a'length-1 downto 0); variable tmp_b : std_logic_vector(vect_b'length-1 downto 0); begin if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b))); -- pragma translate_off else tmp_a := (others =>'X'); tmp_b := (others =>'X'); if (tmp_a'length > tmp_b'length) then return(tmp_a); else return(tmp_b); end if; -- pragma translate_on end if; end "+"; function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(unsigned(vect) + int)); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "+"; function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is variable tmp_a : std_logic_vector(vect'length-1 downto 0); variable tmp_b : std_logic_vector(0 downto 0); begin tmp_b(0) := d; if (not (fn_det_x(vect) or fn_det_x(d))) then return(std_logic_vector(unsigned(vect) + unsigned(tmp_b))); -- pragma translate_off else tmp_b := (others =>'X'); return(tmp_b); -- pragma translate_on end if; end "+"; function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is variable tmp_a : std_logic_vector(vect_a'length-1 downto 0); variable tmp_b : std_logic_vector(vect_b'length-1 downto 0); begin if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b))); -- pragma translate_off else tmp_a := (others =>'X'); tmp_b := (others =>'X'); if (tmp_a'length > tmp_b'length) then return(tmp_a); else return(tmp_b); end if; -- pragma translate_on end if; end "-"; function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(unsigned(vect) - int)); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "-"; function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(int - unsigned(vect))); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "-"; function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is variable tmp_a : std_logic_vector(vect'length-1 downto 0); variable tmp_b : std_logic_vector(0 downto 0); begin tmp_b(0) := d; if (not (fn_det_x(vect) or fn_det_x(d))) then return(std_logic_vector(unsigned(vect) - unsigned(tmp_b))); -- pragma translate_off else tmp_a := (others =>'X'); return(tmp_a); -- pragma translate_on end if; end "-"; end std_library;	apache-2.0	d57c3c833d710d8be334341d1bcc2cbd	0.600733	2.175755	false	false	false	false
jairov4/accel-oil	impl/impl_test_pcie/simulation/behavioral/system_mdm_0_wrapper.vhd	1	38,992	------------------------------------------------------------------------------- -- system_mdm_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library mdm_v2_10_a; use mdm_v2_10_a.all; entity system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end system_mdm_0_wrapper; architecture STRUCTURE of system_mdm_0_wrapper is component mdm is generic ( C_FAMILY : STRING; C_JTAG_CHAIN : INTEGER; C_INTERCONNECT : INTEGER; C_BASEADDR : STD_LOGIC_VECTOR; C_HIGHADDR : STD_LOGIC_VECTOR; C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_MB_DBG_PORTS : INTEGER; C_USE_UART : INTEGER; C_USE_BSCAN : integer; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; begin mdm_0 : mdm generic map ( C_FAMILY => "virtex5", C_JTAG_CHAIN => 2, C_INTERCONNECT => 1, C_BASEADDR => X"84400000", C_HIGHADDR => X"8440ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 64, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 3, C_SPLB_NUM_MASTERS => 6, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 1, C_MB_DBG_PORTS => 1, C_USE_UART => 1, C_USE_BSCAN => 0, C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32 ) port map ( Interrupt => Interrupt, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Dbg_Clk_0 => Dbg_Clk_0, Dbg_TDI_0 => Dbg_TDI_0, Dbg_TDO_0 => Dbg_TDO_0, Dbg_Reg_En_0 => Dbg_Reg_En_0, Dbg_Capture_0 => Dbg_Capture_0, Dbg_Shift_0 => Dbg_Shift_0, Dbg_Update_0 => Dbg_Update_0, Dbg_Rst_0 => Dbg_Rst_0, Dbg_Clk_1 => Dbg_Clk_1, Dbg_TDI_1 => Dbg_TDI_1, Dbg_TDO_1 => Dbg_TDO_1, Dbg_Reg_En_1 => Dbg_Reg_En_1, Dbg_Capture_1 => Dbg_Capture_1, Dbg_Shift_1 => Dbg_Shift_1, Dbg_Update_1 => Dbg_Update_1, Dbg_Rst_1 => Dbg_Rst_1, Dbg_Clk_2 => Dbg_Clk_2, Dbg_TDI_2 => Dbg_TDI_2, Dbg_TDO_2 => Dbg_TDO_2, Dbg_Reg_En_2 => Dbg_Reg_En_2, Dbg_Capture_2 => Dbg_Capture_2, Dbg_Shift_2 => Dbg_Shift_2, Dbg_Update_2 => Dbg_Update_2, Dbg_Rst_2 => Dbg_Rst_2, Dbg_Clk_3 => Dbg_Clk_3, Dbg_TDI_3 => Dbg_TDI_3, Dbg_TDO_3 => Dbg_TDO_3, Dbg_Reg_En_3 => Dbg_Reg_En_3, Dbg_Capture_3 => Dbg_Capture_3, Dbg_Shift_3 => Dbg_Shift_3, Dbg_Update_3 => Dbg_Update_3, Dbg_Rst_3 => Dbg_Rst_3, Dbg_Clk_4 => Dbg_Clk_4, Dbg_TDI_4 => Dbg_TDI_4, Dbg_TDO_4 => Dbg_TDO_4, Dbg_Reg_En_4 => Dbg_Reg_En_4, Dbg_Capture_4 => Dbg_Capture_4, Dbg_Shift_4 => Dbg_Shift_4, Dbg_Update_4 => Dbg_Update_4, Dbg_Rst_4 => Dbg_Rst_4, Dbg_Clk_5 => Dbg_Clk_5, Dbg_TDI_5 => Dbg_TDI_5, Dbg_TDO_5 => Dbg_TDO_5, Dbg_Reg_En_5 => Dbg_Reg_En_5, Dbg_Capture_5 => Dbg_Capture_5, Dbg_Shift_5 => Dbg_Shift_5, Dbg_Update_5 => Dbg_Update_5, Dbg_Rst_5 => Dbg_Rst_5, Dbg_Clk_6 => Dbg_Clk_6, Dbg_TDI_6 => Dbg_TDI_6, Dbg_TDO_6 => Dbg_TDO_6, Dbg_Reg_En_6 => Dbg_Reg_En_6, Dbg_Capture_6 => Dbg_Capture_6, Dbg_Shift_6 => Dbg_Shift_6, Dbg_Update_6 => Dbg_Update_6, Dbg_Rst_6 => Dbg_Rst_6, Dbg_Clk_7 => Dbg_Clk_7, Dbg_TDI_7 => Dbg_TDI_7, Dbg_TDO_7 => Dbg_TDO_7, Dbg_Reg_En_7 => Dbg_Reg_En_7, Dbg_Capture_7 => Dbg_Capture_7, Dbg_Shift_7 => Dbg_Shift_7, Dbg_Update_7 => Dbg_Update_7, Dbg_Rst_7 => Dbg_Rst_7, Dbg_Clk_8 => Dbg_Clk_8, Dbg_TDI_8 => Dbg_TDI_8, Dbg_TDO_8 => Dbg_TDO_8, Dbg_Reg_En_8 => Dbg_Reg_En_8, Dbg_Capture_8 => Dbg_Capture_8, Dbg_Shift_8 => Dbg_Shift_8, Dbg_Update_8 => Dbg_Update_8, Dbg_Rst_8 => Dbg_Rst_8, Dbg_Clk_9 => Dbg_Clk_9, Dbg_TDI_9 => Dbg_TDI_9, Dbg_TDO_9 => Dbg_TDO_9, Dbg_Reg_En_9 => Dbg_Reg_En_9, Dbg_Capture_9 => Dbg_Capture_9, Dbg_Shift_9 => Dbg_Shift_9, Dbg_Update_9 => Dbg_Update_9, Dbg_Rst_9 => Dbg_Rst_9, Dbg_Clk_10 => Dbg_Clk_10, Dbg_TDI_10 => Dbg_TDI_10, Dbg_TDO_10 => Dbg_TDO_10, Dbg_Reg_En_10 => Dbg_Reg_En_10, Dbg_Capture_10 => Dbg_Capture_10, Dbg_Shift_10 => Dbg_Shift_10, Dbg_Update_10 => Dbg_Update_10, Dbg_Rst_10 => Dbg_Rst_10, Dbg_Clk_11 => Dbg_Clk_11, Dbg_TDI_11 => Dbg_TDI_11, Dbg_TDO_11 => Dbg_TDO_11, Dbg_Reg_En_11 => Dbg_Reg_En_11, Dbg_Capture_11 => Dbg_Capture_11, Dbg_Shift_11 => Dbg_Shift_11, Dbg_Update_11 => Dbg_Update_11, Dbg_Rst_11 => Dbg_Rst_11, Dbg_Clk_12 => Dbg_Clk_12, Dbg_TDI_12 => Dbg_TDI_12, Dbg_TDO_12 => Dbg_TDO_12, Dbg_Reg_En_12 => Dbg_Reg_En_12, Dbg_Capture_12 => Dbg_Capture_12, Dbg_Shift_12 => Dbg_Shift_12, Dbg_Update_12 => Dbg_Update_12, Dbg_Rst_12 => Dbg_Rst_12, Dbg_Clk_13 => Dbg_Clk_13, Dbg_TDI_13 => Dbg_TDI_13, Dbg_TDO_13 => Dbg_TDO_13, Dbg_Reg_En_13 => Dbg_Reg_En_13, Dbg_Capture_13 => Dbg_Capture_13, Dbg_Shift_13 => Dbg_Shift_13, Dbg_Update_13 => Dbg_Update_13, Dbg_Rst_13 => Dbg_Rst_13, Dbg_Clk_14 => Dbg_Clk_14, Dbg_TDI_14 => Dbg_TDI_14, Dbg_TDO_14 => Dbg_TDO_14, Dbg_Reg_En_14 => Dbg_Reg_En_14, Dbg_Capture_14 => Dbg_Capture_14, Dbg_Shift_14 => Dbg_Shift_14, Dbg_Update_14 => Dbg_Update_14, Dbg_Rst_14 => Dbg_Rst_14, Dbg_Clk_15 => Dbg_Clk_15, Dbg_TDI_15 => Dbg_TDI_15, Dbg_TDO_15 => Dbg_TDO_15, Dbg_Reg_En_15 => Dbg_Reg_En_15, Dbg_Capture_15 => Dbg_Capture_15, Dbg_Shift_15 => Dbg_Shift_15, Dbg_Update_15 => Dbg_Update_15, Dbg_Rst_15 => Dbg_Rst_15, Dbg_Clk_16 => Dbg_Clk_16, Dbg_TDI_16 => Dbg_TDI_16, Dbg_TDO_16 => Dbg_TDO_16, Dbg_Reg_En_16 => Dbg_Reg_En_16, Dbg_Capture_16 => Dbg_Capture_16, Dbg_Shift_16 => Dbg_Shift_16, Dbg_Update_16 => Dbg_Update_16, Dbg_Rst_16 => Dbg_Rst_16, Dbg_Clk_17 => Dbg_Clk_17, Dbg_TDI_17 => Dbg_TDI_17, Dbg_TDO_17 => Dbg_TDO_17, Dbg_Reg_En_17 => Dbg_Reg_En_17, Dbg_Capture_17 => Dbg_Capture_17, Dbg_Shift_17 => Dbg_Shift_17, Dbg_Update_17 => Dbg_Update_17, Dbg_Rst_17 => Dbg_Rst_17, Dbg_Clk_18 => Dbg_Clk_18, Dbg_TDI_18 => Dbg_TDI_18, Dbg_TDO_18 => Dbg_TDO_18, Dbg_Reg_En_18 => Dbg_Reg_En_18, Dbg_Capture_18 => Dbg_Capture_18, Dbg_Shift_18 => Dbg_Shift_18, Dbg_Update_18 => Dbg_Update_18, Dbg_Rst_18 => Dbg_Rst_18, Dbg_Clk_19 => Dbg_Clk_19, Dbg_TDI_19 => Dbg_TDI_19, Dbg_TDO_19 => Dbg_TDO_19, Dbg_Reg_En_19 => Dbg_Reg_En_19, Dbg_Capture_19 => Dbg_Capture_19, Dbg_Shift_19 => Dbg_Shift_19, Dbg_Update_19 => Dbg_Update_19, Dbg_Rst_19 => Dbg_Rst_19, Dbg_Clk_20 => Dbg_Clk_20, Dbg_TDI_20 => Dbg_TDI_20, Dbg_TDO_20 => Dbg_TDO_20, Dbg_Reg_En_20 => Dbg_Reg_En_20, Dbg_Capture_20 => Dbg_Capture_20, Dbg_Shift_20 => Dbg_Shift_20, Dbg_Update_20 => Dbg_Update_20, Dbg_Rst_20 => Dbg_Rst_20, Dbg_Clk_21 => Dbg_Clk_21, Dbg_TDI_21 => Dbg_TDI_21, Dbg_TDO_21 => Dbg_TDO_21, Dbg_Reg_En_21 => Dbg_Reg_En_21, Dbg_Capture_21 => Dbg_Capture_21, Dbg_Shift_21 => Dbg_Shift_21, Dbg_Update_21 => Dbg_Update_21, Dbg_Rst_21 => Dbg_Rst_21, Dbg_Clk_22 => Dbg_Clk_22, Dbg_TDI_22 => Dbg_TDI_22, Dbg_TDO_22 => Dbg_TDO_22, Dbg_Reg_En_22 => Dbg_Reg_En_22, Dbg_Capture_22 => Dbg_Capture_22, Dbg_Shift_22 => Dbg_Shift_22, Dbg_Update_22 => Dbg_Update_22, Dbg_Rst_22 => Dbg_Rst_22, Dbg_Clk_23 => Dbg_Clk_23, Dbg_TDI_23 => Dbg_TDI_23, Dbg_TDO_23 => Dbg_TDO_23, Dbg_Reg_En_23 => Dbg_Reg_En_23, Dbg_Capture_23 => Dbg_Capture_23, Dbg_Shift_23 => Dbg_Shift_23, Dbg_Update_23 => Dbg_Update_23, Dbg_Rst_23 => Dbg_Rst_23, Dbg_Clk_24 => Dbg_Clk_24, Dbg_TDI_24 => Dbg_TDI_24, Dbg_TDO_24 => Dbg_TDO_24, Dbg_Reg_En_24 => Dbg_Reg_En_24, Dbg_Capture_24 => Dbg_Capture_24, Dbg_Shift_24 => Dbg_Shift_24, Dbg_Update_24 => Dbg_Update_24, Dbg_Rst_24 => Dbg_Rst_24, Dbg_Clk_25 => Dbg_Clk_25, Dbg_TDI_25 => Dbg_TDI_25, Dbg_TDO_25 => Dbg_TDO_25, Dbg_Reg_En_25 => Dbg_Reg_En_25, Dbg_Capture_25 => Dbg_Capture_25, Dbg_Shift_25 => Dbg_Shift_25, Dbg_Update_25 => Dbg_Update_25, Dbg_Rst_25 => Dbg_Rst_25, Dbg_Clk_26 => Dbg_Clk_26, Dbg_TDI_26 => Dbg_TDI_26, Dbg_TDO_26 => Dbg_TDO_26, Dbg_Reg_En_26 => Dbg_Reg_En_26, Dbg_Capture_26 => Dbg_Capture_26, Dbg_Shift_26 => Dbg_Shift_26, Dbg_Update_26 => Dbg_Update_26, Dbg_Rst_26 => Dbg_Rst_26, Dbg_Clk_27 => Dbg_Clk_27, Dbg_TDI_27 => Dbg_TDI_27, Dbg_TDO_27 => Dbg_TDO_27, Dbg_Reg_En_27 => Dbg_Reg_En_27, Dbg_Capture_27 => Dbg_Capture_27, Dbg_Shift_27 => Dbg_Shift_27, Dbg_Update_27 => Dbg_Update_27, Dbg_Rst_27 => Dbg_Rst_27, Dbg_Clk_28 => Dbg_Clk_28, Dbg_TDI_28 => Dbg_TDI_28, Dbg_TDO_28 => Dbg_TDO_28, Dbg_Reg_En_28 => Dbg_Reg_En_28, Dbg_Capture_28 => Dbg_Capture_28, Dbg_Shift_28 => Dbg_Shift_28, Dbg_Update_28 => Dbg_Update_28, Dbg_Rst_28 => Dbg_Rst_28, Dbg_Clk_29 => Dbg_Clk_29, Dbg_TDI_29 => Dbg_TDI_29, Dbg_TDO_29 => Dbg_TDO_29, Dbg_Reg_En_29 => Dbg_Reg_En_29, Dbg_Capture_29 => Dbg_Capture_29, Dbg_Shift_29 => Dbg_Shift_29, Dbg_Update_29 => Dbg_Update_29, Dbg_Rst_29 => Dbg_Rst_29, Dbg_Clk_30 => Dbg_Clk_30, Dbg_TDI_30 => Dbg_TDI_30, Dbg_TDO_30 => Dbg_TDO_30, Dbg_Reg_En_30 => Dbg_Reg_En_30, Dbg_Capture_30 => Dbg_Capture_30, Dbg_Shift_30 => Dbg_Shift_30, Dbg_Update_30 => Dbg_Update_30, Dbg_Rst_30 => Dbg_Rst_30, Dbg_Clk_31 => Dbg_Clk_31, Dbg_TDI_31 => Dbg_TDI_31, Dbg_TDO_31 => Dbg_TDO_31, Dbg_Reg_En_31 => Dbg_Reg_En_31, Dbg_Capture_31 => Dbg_Capture_31, Dbg_Shift_31 => Dbg_Shift_31, Dbg_Update_31 => Dbg_Update_31, Dbg_Rst_31 => Dbg_Rst_31, bscan_tdi => bscan_tdi, bscan_reset => bscan_reset, bscan_shift => bscan_shift, bscan_update => bscan_update, bscan_capture => bscan_capture, bscan_sel1 => bscan_sel1, bscan_drck1 => bscan_drck1, bscan_tdo1 => bscan_tdo1, bscan_ext_tdi => bscan_ext_tdi, bscan_ext_reset => bscan_ext_reset, bscan_ext_shift => bscan_ext_shift, bscan_ext_update => bscan_ext_update, bscan_ext_capture => bscan_ext_capture, bscan_ext_sel => bscan_ext_sel, bscan_ext_drck => bscan_ext_drck, bscan_ext_tdo => bscan_ext_tdo, Ext_JTAG_DRCK => Ext_JTAG_DRCK, Ext_JTAG_RESET => Ext_JTAG_RESET, Ext_JTAG_SEL => Ext_JTAG_SEL, Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE, Ext_JTAG_SHIFT => Ext_JTAG_SHIFT, Ext_JTAG_UPDATE => Ext_JTAG_UPDATE, Ext_JTAG_TDI => Ext_JTAG_TDI, Ext_JTAG_TDO => Ext_JTAG_TDO ); end architecture STRUCTURE;	lgpl-3.0	67516c6c77ac3e0a64def9cc33d5773b	0.575528	2.800144	false	false	false	false
jairov4/accel-oil	solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_forward_buckets_if_plb_master_if.vhd	2	37,013	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end entity; architecture rtl of nfa_forward_buckets_if_ap_fifo_uw is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype; signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0); signal internal_empty_n, internal_full_n : STD_LOGIC; signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0); begin mNextInPtr <= mInPtr + 1; if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; use_word <= internal_use_word; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); internal_use_word <= (others => '0'); else if clk'event and clk = '1' then if if_read = '1' and internal_empty_n = '1' then mOutPtr <= mOutPtr + 1; end if; if if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; mInPtr <= mNextInPtr; end if; if (if_read = '1' and if_write = '0') then internal_use_word <= internal_use_word - '1'; elsif (if_read = '0' and if_write = '1') then internal_use_word <= internal_use_word + '1'; end if; end if; end if; end process; process (mInPtr, mOutPtr, mNextInPtr) begin if mInPtr = mOutPtr then internal_empty_n <= '0'; else internal_empty_n <= '1'; end if; if mNextInPtr = mOutPtr then internal_full_n <= '0'; else internal_full_n <= '1'; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3 ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- physical address BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n: out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of PLB_Clk : signal is "Clk"; attribute SIGIS of PLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of nfa_forward_buckets_if_plb_master_if is component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end component; component nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end component; constant PLB_DW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := PLB_DW/8; constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size constant FIFO_ADDR_WIDTH : integer := 5; constant FIFO_DEPTH : integer := 32; -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); -- burst write counter (only push burst data in and ignore all burst write request except the first one) signal req_burst_write: STD_LOGIC; -- whether last request is a burst write signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0); -- write data FIFO (for bus write data) signal wd_fifo_empty_n : STD_LOGIC; signal wd_fifo_pop : STD_LOGIC; signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_full_n : STD_LOGIC; signal wd_fifo_push : STD_LOGIC; signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); -- read data FIFO (for bus read returned data) signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1 signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block signal request, req_nRW: std_logic; signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal pending_rd_req_burst_mode: std_logic; signal pending_rd_req_burst_size: std_logic_vector(3 downto 0); signal pending_wr_req_burst_mode: std_logic; signal pending_wr_req_burst_size: std_logic_vector(3 downto 0); signal pending_read, pending_write: std_logic; signal burst_mode, burst_last : std_logic; signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words --signals for write data mirror signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal conv_counter_comb: std_logic_vector(1 downto 0); signal wr_data_phase : std_logic; signal dataConv_last: std_logic; signal dp_dataConv_last: std_logic; signal dp_dataConv_word_addr: std_logic_vector(1 downto 0); signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64 signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0); signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal dp_PLB_MSSize : std_logic_vector(1 downto 0); --signals for read data mirror signal PLB_MRdDAck_reg : std_logic; signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0); signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0); -- signals with dp_ prefix stand for data phase signals -- signals with req_ prefix stand for request phase signals begin -- interface to user logic BUS_RdData <= rd_fifo_dout; BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n; BUS_rsp_nRW <= '0'; BUS_rsp_empty_n <= rd_fifo_empty_n; -- interface to PLB M_abort <= '0'; M_busLock <= '0'; M_lockErr <= '0'; M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst M_type <= "000"; -- memory trans M_priority <= "00"; M_RNW <= not req_nRW; M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0'; process (PLB_MSSize) begin M_wrBurst <= '0'; if (pending_wr_req_burst_mode = '1' and (pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then M_wrBurst <= '1'; elsif (request = '1' and req_nRW = '1' and pending_write = '0' and burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then M_wrBurst <= '1'; end if; end process; -- write data mirror section process (PLB_MSSize) begin if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then conv_mode_comb <= "10"; -- conv 64:32 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then conv_mode_comb <= "11"; -- conv 128:64 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then conv_mode_comb <= "01"; -- conv 128:32 conv_counter_comb <= "11"; else conv_mode_comb <= "00"; -- do not need conv conv_counter_comb <= "00"; end if; end process; process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE) begin dataConv_last <= '0'; if (burst_mode = '0' or burst_size = "0000") then if (conv_mode_comb = "00") then -- no conv dataConv_last <= '1'; elsif (conv_mode_comb = "10") then -- 64:32 conv if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "11") then -- 128:64 conv if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "01") then -- 128:32 conv if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT3/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "11") then dataConv_last <= '1'; end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_word_addr <= (others => '0'); dp_dataConv_wd_conv_mode <= (others =>'0'); dp_dataConv_wd_burst_counter <= (others => '0'); dp_dataConv_wd_BE <= (others => '0'); dp_dataConv_last <= '0'; wr_data_phase <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then dp_dataConv_wd_BE <= req_BE; dp_dataConv_last <= dataConv_last; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and (PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then wr_data_phase <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0')) then wr_data_phase <= '0'; end if; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then if (PLB_MWrDAck = '0') then -- only AddrAck asserted dp_dataConv_wd_conv_mode <= conv_mode_comb; dp_dataConv_word_addr <= req_address(28 to 29); dp_dataConv_wd_burst_counter <= conv_counter_comb; else -- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle if (dataConv_last = '0') then dp_dataConv_wd_conv_mode <= conv_mode_comb; end if; if (PLB_MSSize = "00") then -- 32 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +1; elsif (PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +2; end if; if (conv_mode_comb /= "00") then -- need conv dp_dataConv_wd_burst_counter <= conv_counter_comb -1; end if; end if; end if; if (wr_data_phase = '1' and PLB_MWrDAck = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then dp_dataConv_wd_conv_mode <= "00"; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if (dp_PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= dp_dataConv_word_addr +2; else dp_dataConv_word_addr <= dp_dataConv_word_addr +1; end if; if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or dp_dataConv_wd_burst_counter /= "00") then if (dp_dataConv_wd_burst_counter = "00") then if (dp_dataConv_wd_conv_mode = "01") then -- 128/32 dp_dataConv_wd_burst_counter <= "11"; elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_wd_burst_counter <= "01"; end if; else dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1; end if; end if; end if; end if; end process; process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE) begin wd_fifo_pop <= '0'; if (PLB_MWrDAck = '1') then if (wr_data_phase = '1') then if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or (dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or dp_dataConv_wd_conv_mode = "00" )then wd_fifo_pop <= '1'; end if; else -- got addrAck and wrDAck at the same cycle if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then wd_fifo_pop <= '1'; elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then wd_fifo_pop <= '1'; end if; end if; end if; end process; process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr) begin wd_fifo_dout_mirror <= wd_fifo_dout; if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert if (C_PLB_DWIDTH = 32) then wd_fifo_dout_mirror <= wd_fifo_dout; elsif (C_PLB_DWIDTH = 64) then if (req_address(29) = '0') then wd_fifo_dout_mirror <= wd_fifo_dout; else wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); end if; elsif (C_PLB_DWIDTH = 128) then case req_address(28 to 29) is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4); when others => null; end case; end if; else -- in data phase wd_fifo_dout_mirror <= wd_fifo_dout; if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or (dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64 wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32 case dp_dataConv_word_addr is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH3/4-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH3/4); when others => null; end case; end if; end if; end process; process(wd_fifo_dout_mirror) variable i: integer; begin for i in 0 to C_PLB_DWIDTH-1 loop M_wrDBus(i) <= wd_fifo_dout_mirror(i); end loop; end process; process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word, pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size) begin M_request <= '0'; if (request = '1') then if (req_nRW = '0' and pending_read = '0') then -- read request if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then M_request <= '1'; elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available M_request <= '1'; end if; elsif (req_nRW = '1' and pending_write = '0') then -- write request if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then M_request <= '1'; elsif (wd_fifo_use_word > burst_size) then M_request <= '1'; end if; end if; end if; end process; M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address; process(req_nRW, burst_mode, burst_size, req_BE) variable i:integer; begin M_BE <= (others => '0'); if (burst_mode = '1') then if (burst_size = "0000") then M_BE <= (others => '1'); -- first single,then burst 16 else M_BE(0 to 3) <= burst_size; -- fixed length burst end if; elsif (req_nRW = '0') then M_BE <= (others => '1'); else for i in 0 to PLB_BYTE_COUNT-1 loop M_BE(i) <= req_BE(i); end loop; end if; end process; -- user req FIFO, for both read request and write request U_req_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_WIDTH, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_push <= BUS_req_push and not req_burst_write; req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size; req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then req_burst_write <= '0'; req_burst_write_counter <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_write <= '1'; req_burst_write_counter <= BUS_size - 1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then req_burst_write_counter <= req_burst_write_counter -1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data req_burst_write <= '0'; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then request <= '0'; req_size <= (others => '0'); req_nRW <= '0'; req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0'); burst_mode <= '0'; burst_size <= (others => '0'); req_fifo_pop <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then req_fifo_pop <= '0'; if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then request <= '1'; if (conv_mode_comb(1) = '1') then -- 2:1 conv req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0'); else -- 128:32 if (req_address(28 to 29) = "00") then req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0'); elsif (req_address(28 to 29) = "01") then req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0'); elsif (req_address(28 to 29) = "10") then req_BE(PLB_BYTE_COUNT3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0'); end if; end if; if (PLB_MSSize = "00") then -- 32 bits slave req_address <= req_address + 4; elsif (PLB_MSSize = "01") then -- 64 slave req_address <= req_address + 8; end if;-- 128 bits slave does not need conversion cycle elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then request <= '1'; -- req next burst section, this will be pending until previous burst finished req_size(0 to 27) <= req_size(0 to 27) - 1; req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1; req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); -- low bits of addr must be reset for possible data_conv modifications of 10 lines above burst_mode <= '1'; burst_size <= "1111"; -- burst 16 words else if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; end if; request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1); req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64); req_address <= req_fifo_dout(63 downto 32); if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); end if; -- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst burst_mode <= req_fifo_empty_n; -- fetched req may be null req -- req of burst 17 will be single + burst 16, please check burst_size also else burst_mode <= '0'; end if; burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_read <= '0'; pending_write <= '0'; dp_PLB_MSSize <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or (pending_rd_req_burst_mode = '0'))) then pending_read <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='0') then pending_read <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or pending_wr_req_burst_mode = '0')) then pending_write <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='1' and (PLB_MWrDAck = '0' or burst_size /= "0000")) then pending_write <= '1'; end if; if (PLB_MAddrAck = '1') then dp_PLB_MSSize <= PLB_MSSize; end if; end if; end process; process(req_size) begin if (req_size(0 to 27) = "000000000000000000000000000") then burst_last <= '1'; -- one request is ok else burst_last <= '0'; end if; end process; -- user write data FIFO, for data of bus write request U_wd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => wd_fifo_empty_n, if_read => wd_fifo_pop, if_dout => wd_fifo_dout, if_full_n => wd_fifo_full_n, if_write => wd_fifo_push, if_din => wd_fifo_din, use_word => wd_fifo_use_word ); wd_fifo_push <= BUS_req_push and BUS_req_nRW; wd_fifo_din <= BUS_WrData; -- returned bus read data fifo U_rd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, if_write => rd_fifo_push, if_din => rd_fifo_din, use_word => rd_fifo_use_word ); process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_rd_conv_mode <= (others =>'0'); dp_dataConv_rd_burst_counter <= (others => '0'); dp_dataConv_rd_burst_counter_reg <= (others => '0'); PLB_MRdDAck_reg <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then dp_dataConv_rd_conv_mode <= conv_mode_comb; dp_dataConv_rd_burst_counter <= conv_counter_comb; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then dp_dataConv_rd_conv_mode <= "00"; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then if (dp_dataConv_rd_burst_counter = "00") then if (dp_dataConv_rd_conv_mode = "01") then -- 128/32 dp_dataConv_rd_burst_counter <= "11"; elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_rd_burst_counter <= "01"; end if; else dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1; end if; end if; dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter; PLB_MRdDAck_reg <= PLB_MRdDAck; end if; end process; rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0'; process(PLB_MRdDBus) variable i: integer; begin -- change to little endian for i in 0 to C_PLB_DWIDTH-1 loop PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i); end loop; end process; process(PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then rd_fifo_din <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1') then case dp_dataConv_rd_conv_mode is when "00" => rd_fifo_din <= PLB_MRdDBus_reverse; when "10" \| "11" => if (dp_dataConv_rd_burst_counter = "00") then rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); else rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); end if; when "01" => case dp_dataConv_rd_burst_counter is when "00" => rd_fifo_din(PLB_DW-1 downto PLB_DW3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "01" => rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "10" => rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "11" => rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when others => null; end case; when others => null; end case; end if; end if; end process; rd_fifo_pop <= BUS_rsp_pop; pending_read_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_rd_req_burst_mode <= '0'; pending_rd_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0') then if (burst_mode = '1' and burst_size /= "0000") then pending_rd_req_burst_mode <= burst_mode; end if; pending_rd_req_burst_size <= burst_size; elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then if (dp_dataConv_rd_burst_counter = "00") then pending_rd_req_burst_size <= pending_rd_req_burst_size - 1; if (pending_rd_req_burst_size = "0000") then pending_rd_req_burst_mode <= '0'; end if; end if; end if; end if; end process; pending_write_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_wr_req_burst_mode <= '0'; pending_wr_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then if (burst_mode = '1' and burst_size /= "0000") then pending_wr_req_burst_mode <= '1'; end if; pending_wr_req_burst_size <= burst_size; if (PLB_MWrDAck = '1') then if (conv_counter_comb = "00") then pending_wr_req_burst_size <= burst_size -1; else pending_wr_req_burst_size <= burst_size; end if; end if; elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then if (dp_dataConv_wd_burst_counter = "00") then pending_wr_req_burst_size <= pending_wr_req_burst_size - 1; if (pending_wr_req_burst_size = "0000") then pending_wr_req_burst_mode <= '0'; end if; end if; end if; end if; end process; end IMP;	lgpl-3.0	3d13ecbd9c9f83c9d75e01710dac4501	0.535001	3.311829	false	false	false	false
jairov4/accel-oil	solution_virtex5_plb/syn/vhdl/nfa_accept_sample_multi_next_buckets.vhd	1	3,201	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nfa_accept_sample_multi_next_buckets_ram is generic( mem_type : string := "block"; dwidth : integer := 64; awidth : integer := 4; mem_size : integer := 16 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of nfa_accept_sample_multi_next_buckets_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_sample_multi_next_buckets is generic ( DataWidth : INTEGER := 64; AddressRange : INTEGER := 16; AddressWidth : INTEGER := 4); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_sample_multi_next_buckets is component nfa_accept_sample_multi_next_buckets_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_sample_multi_next_buckets_ram_U : component nfa_accept_sample_multi_next_buckets_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0); end architecture;	lgpl-3.0	9509007816150f82db7c41a2c328f35c	0.555764	3.521452	false	false	false	false
wsoltys/AtomFpga	src/DCM/dcm4.vhd	1	2,051	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm4 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end dcm4; architecture BEHAVIORAL of dcm4 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, -- 25.175 = 32 * 11 / 14 CLKFX_DIVIDE => 14, CLKFX_MULTIPLY => 11, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;	apache-2.0	d3b01e0f70dd04bba46dfe95885232ec	0.403218	4.29979	false	false	false	false
jairov4/accel-oil	solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_finals_buckets_if_async_fifo.vhd	1	5,827	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_finals_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_finals_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;	lgpl-3.0	9b2ebabfdfd90b59002178d95bfb6c02	0.554144	3.403621	false	false	false	false
jairov4/accel-oil	impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/sample_iterator_get_offset/_primary.vhd	1	2,496	library verilog; use verilog.vl_types.all; entity sample_iterator_get_offset is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_pp0_stg0_fsm_0: vl_logic := Hi0; ap_const_lv32_1 : integer := 1; ap_const_lv32_30: integer := 48; ap_const_lv32_37: integer := 55; ap_const_lv56_0 : vl_logic_vector(0 to 55) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; indices_req_din : out vl_logic; indices_req_full_n: in vl_logic; indices_req_write: out vl_logic; indices_rsp_empty_n: in vl_logic; indices_rsp_read: out vl_logic; indices_address : out vl_logic_vector(31 downto 0); indices_datain : in vl_logic_vector(55 downto 0); indices_dataout : out vl_logic_vector(55 downto 0); indices_size : out vl_logic_vector(31 downto 0); ap_ce : in vl_logic; i_index : in vl_logic_vector(15 downto 0); i_sample : in vl_logic_vector(15 downto 0); sample_buffer_size: in vl_logic_vector(31 downto 0); sample_length : in vl_logic_vector(15 downto 0); ap_return : out vl_logic_vector(31 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_30 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_37 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv56_0 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end sample_iterator_get_offset;	lgpl-3.0	ca5bef7176f29d33beddbcb6a5d57148	0.580929	2.929577	false	false	false	false
takeshineshiro/fpga_fibre_scan	HUCB2P0_150701/usb_core/usb_121pll.vhd	1	18,162	-- megafunction wizard: %Altera PLL v14.0% -- GENERATION: XML -- usb_121pll.vhd -- Generated using ACDS version 14.0 200 at 2015.05.21.11:40:18 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity usb_121pll is port ( refclk : in std_logic := '0'; -- refclk.clk rst : in std_logic := '0'; -- reset.reset outclk_0 : out std_logic; -- outclk0.clk outclk_1 : out std_logic; -- outclk1.clk locked : out std_logic -- locked.export ); end entity usb_121pll; architecture rtl of usb_121pll is component usb_121pll_0002 is port ( refclk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic; -- clk outclk_1 : out std_logic; -- clk locked : out std_logic -- export ); end component usb_121pll_0002; begin usb_121pll_inst : component usb_121pll_0002 port map ( refclk => refclk, -- refclk.clk rst => rst, -- reset.reset outclk_0 => outclk_0, -- outclk0.clk outclk_1 => outclk_1, -- outclk1.clk locked => locked -- locked.export ); end architecture rtl; -- of usb_121pll -- Retrieval info: <?xml version="1.0"?> --<!-- -- Generated by Altera MegaWizard Launcher Utility version 1.0 -- ********************************************************** -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ********************************************************** -- Copyright (C) 1991-2015 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> -- Retrieval info: <instance entity-name="altera_pll" version="14.0" > -- Retrieval info: <generic name="debug_print_output" value="false" /> -- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" /> -- Retrieval info: <generic name="device_family" value="Cyclone V" /> -- Retrieval info: <generic name="device" value="Unknown" /> -- Retrieval info: <generic name="gui_device_speed_grade" value="8" /> -- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" /> -- Retrieval info: <generic name="gui_reference_clock_frequency" value="20.0" /> -- Retrieval info: <generic name="gui_channel_spacing" value="0.0" /> -- Retrieval info: <generic name="gui_operation_mode" value="normal" /> -- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" /> -- Retrieval info: <generic name="gui_fractional_cout" value="32" /> -- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" /> -- Retrieval info: <generic name="gui_use_locked" value="true" /> -- Retrieval info: <generic name="gui_en_adv_params" value="false" /> -- Retrieval info: <generic name="gui_number_of_clocks" value="2" /> -- Retrieval info: <generic name="gui_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_divide_factor_n" value="1" /> -- Retrieval info: <generic name="gui_cascade_counter0" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency0" value="60.0" /> -- Retrieval info: <generic name="gui_divide_factor_c0" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units0" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle0" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter1" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency1" value="60.0" /> -- Retrieval info: <generic name="gui_divide_factor_c1" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units1" value="degrees" /> -- Retrieval info: <generic name="gui_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle1" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter2" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c2" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units2" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle2" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter3" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c3" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units3" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle3" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter4" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c4" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units4" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle4" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter5" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c5" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units5" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle5" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter6" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c6" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units6" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle6" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter7" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c7" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units7" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle7" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter8" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c8" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units8" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle8" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter9" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c9" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units9" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle9" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter10" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c10" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units10" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle10" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter11" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c11" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units11" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle11" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter12" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c12" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units12" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle12" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter13" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c13" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units13" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle13" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter14" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c14" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units14" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle14" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter15" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c15" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units15" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle15" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter16" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c16" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units16" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle16" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter17" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c17" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units17" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle17" value="50" /> -- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" /> -- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" /> -- Retrieval info: <generic name="gui_en_reconf" value="false" /> -- Retrieval info: <generic name="gui_en_dps_ports" value="false" /> -- Retrieval info: <generic name="gui_en_phout_ports" value="false" /> -- Retrieval info: <generic name="gui_phout_division" value="1" /> -- Retrieval info: <generic name="gui_en_lvds_ports" value="false" /> -- Retrieval info: <generic name="gui_mif_generate" value="false" /> -- Retrieval info: <generic name="gui_enable_mif_dps" value="false" /> -- Retrieval info: <generic name="gui_dps_cntr" value="C0" /> -- Retrieval info: <generic name="gui_dps_num" value="1" /> -- Retrieval info: <generic name="gui_dps_dir" value="Positive" /> -- Retrieval info: <generic name="gui_refclk_switch" value="false" /> -- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" /> -- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" /> -- Retrieval info: <generic name="gui_switchover_delay" value="0" /> -- Retrieval info: <generic name="gui_active_clk" value="false" /> -- Retrieval info: <generic name="gui_clk_bad" value="false" /> -- Retrieval info: <generic name="gui_enable_cascade_out" value="false" /> -- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" /> -- Retrieval info: <generic name="gui_enable_cascade_in" value="false" /> -- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" /> -- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" /> -- Retrieval info: </instance> -- IPFS_FILES : usb_121pll.vho -- RELATED_FILES: usb_121pll.vhd, usb_121pll_0002.v	apache-2.0	730e27a773d0c3d6f58dd8cc6677355a	0.672888	3.00248	false	false	false	false
dcliche/mdsynth	rtl/src/sound/lfsr.vhd	1	6,012	------------------------------------------------------------------------------- -- File downloaded from http://www.nandland.com ------------------------------------------------------------------------------- -- Description: -- A LFSR or Linear Feedback Shift Register is a quick and easy -- way to generate pseudo-random data inside of an FPGA. The LFSR can be used -- for things like counters, test patterns, scrambling of data, and others. -- This module creates an LFSR whose width gets set by a generic. The -- o_LFSR_Done will pulse once all combinations of the LFSR are complete. The -- number of clock cycles that it takes o_LFSR_Done to pulse is equal to -- 2^g_Num_Bits-1. For example, setting g_Num_Bits to 5 means that o_LFSR_Done -- will pulse every 2^5-1 = 31 clock cycles. o_LFSR_Data will change on each -- clock cycle that the module is enabled, which can be used if desired. -- -- Generics: -- g_Num_Bits - Set to the integer number of bits wide to create your LFSR. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity lfsr is generic ( g_Num_Bits : integer := 5 ); port ( i_Clk : in std_logic; i_Enable : in std_logic; -- Optional Seed Value i_Seed_DV : in std_logic; i_Seed_Data : in std_logic_vector(g_Num_Bits-1 downto 0); o_LFSR_Data : out std_logic_vector(g_Num_Bits-1 downto 0); o_LFSR_Done : out std_logic ); end entity lfsr; architecture rtl of lfsr is signal r_LFSR : std_logic_vector(g_Num_Bits downto 1) := (others => '0'); signal w_XNOR : std_logic; begin -- Purpose: Load up LFSR with Seed if Data Valid (DV) pulse is detected. -- Othewise just run LFSR when enabled. p_LFSR : process (i_Clk) is begin if rising_edge(i_Clk) then if i_Enable = '1' then if i_Seed_DV = '1' then r_LFSR <= i_Seed_Data; else r_LFSR <= r_LFSR(r_LFSR'left-1 downto 1) & w_XNOR; end if; end if; end if; end process p_LFSR; -- Create Feedback Polynomials. Based on Application Note: -- http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf g_LFSR_3 : if g_Num_Bits = 3 generate w_XNOR <= r_LFSR(3) xnor r_LFSR(2); end generate g_LFSR_3; g_LFSR_4 : if g_Num_Bits = 4 generate w_XNOR <= r_LFSR(4) xnor r_LFSR(3); end generate g_LFSR_4; g_LFSR_5 : if g_Num_Bits = 5 generate w_XNOR <= r_LFSR(5) xnor r_LFSR(3); end generate g_LFSR_5; g_LFSR_6 : if g_Num_Bits = 6 generate w_XNOR <= r_LFSR(6) xnor r_LFSR(5); end generate g_LFSR_6; g_LFSR_7 : if g_Num_Bits = 7 generate w_XNOR <= r_LFSR(7) xnor r_LFSR(6); end generate g_LFSR_7; g_LFSR_8 : if g_Num_Bits = 8 generate w_XNOR <= r_LFSR(8) xnor r_LFSR(6) xnor r_LFSR(5) xnor r_LFSR(4); end generate g_LFSR_8; g_LFSR_9 : if g_Num_Bits = 9 generate w_XNOR <= r_LFSR(9) xnor r_LFSR(5); end generate g_LFSR_9; g_LFSR_10 : if g_Num_Bits = 10 generate w_XNOR <= r_LFSR(10) xnor r_LFSR(7); end generate g_LFSR_10; g_LFSR_11 : if g_Num_Bits = 11 generate w_XNOR <= r_LFSR(11) xnor r_LFSR(9); end generate g_LFSR_11; g_LFSR_12 : if g_Num_Bits = 12 generate w_XNOR <= r_LFSR(12) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1); end generate g_LFSR_12; g_LFSR_13 : if g_Num_Bits = 13 generate w_XNOR <= r_LFSR(13) xnor r_LFSR(4) xnor r_LFSR(3) xnor r_LFSR(1); end generate g_LFSR_13; g_LFSR_14 : if g_Num_Bits = 14 generate w_XNOR <= r_LFSR(14) xnor r_LFSR(5) xnor r_LFSR(3) xnor r_LFSR(1); end generate g_LFSR_14; g_LFSR_15 : if g_Num_Bits = 15 generate w_XNOR <= r_LFSR(15) xnor r_LFSR(14); end generate g_LFSR_15; g_LFSR_16 : if g_Num_Bits = 16 generate w_XNOR <= r_LFSR(16) xnor r_LFSR(15) xnor r_LFSR(13) xnor r_LFSR(4); end generate g_LFSR_16; g_LFSR_17 : if g_Num_Bits = 17 generate w_XNOR <= r_LFSR(17) xnor r_LFSR(14); end generate g_LFSR_17; g_LFSR_18 : if g_Num_Bits = 18 generate w_XNOR <= r_LFSR(18) xnor r_LFSR(11); end generate g_LFSR_18; g_LFSR_19 : if g_Num_Bits = 19 generate w_XNOR <= r_LFSR(19) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_19; g_LFSR_20 : if g_Num_Bits = 20 generate w_XNOR <= r_LFSR(20) xnor r_LFSR(17); end generate g_LFSR_20; g_LFSR_21 : if g_Num_Bits = 21 generate w_XNOR <= r_LFSR(21) xnor r_LFSR(19); end generate g_LFSR_21; g_LFSR_22 : if g_Num_Bits = 22 generate w_XNOR <= r_LFSR(22) xnor r_LFSR(21); end generate g_LFSR_22; g_LFSR_23 : if g_Num_Bits = 23 generate w_XNOR <= r_LFSR(23) xnor r_LFSR(18); end generate g_LFSR_23; g_LFSR_24 : if g_Num_Bits = 24 generate w_XNOR <= r_LFSR(24) xnor r_LFSR(23) xnor r_LFSR(22) xnor r_LFSR(17); end generate g_LFSR_24; g_LFSR_25 : if g_Num_Bits = 25 generate w_XNOR <= r_LFSR(25) xnor r_LFSR(22); end generate g_LFSR_25; g_LFSR_26 : if g_Num_Bits = 26 generate w_XNOR <= r_LFSR(26) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_26; g_LFSR_27 : if g_Num_Bits = 27 generate w_XNOR <= r_LFSR(27) xnor r_LFSR(5) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_27; g_LFSR_28 : if g_Num_Bits = 28 generate w_XNOR <= r_LFSR(28) xnor r_LFSR(25); end generate g_LFSR_28; g_LFSR_29 : if g_Num_Bits = 29 generate w_XNOR <= r_LFSR(29) xnor r_LFSR(27); end generate g_LFSR_29; g_LFSR_30 : if g_Num_Bits = 30 generate w_XNOR <= r_LFSR(30) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1); end generate g_LFSR_30; g_LFSR_31 : if g_Num_Bits = 31 generate w_XNOR <= r_LFSR(31) xnor r_LFSR(28); end generate g_LFSR_31; g_LFSR_32 : if g_Num_Bits = 32 generate w_XNOR <= r_LFSR(32) xnor r_LFSR(22) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_32; o_LFSR_Data <= r_LFSR(r_LFSR'left downto 1); o_LFSR_Done <= '1' when r_LFSR(r_LFSR'left downto 1) = i_Seed_Data else '0'; end architecture rtl;	gpl-3.0	1067162bf4df73e56767e37495d169af	0.601464	2.86969	false	false	false	false
grwlf/vsim	vhdl_ct/ct00379.vhd	1	1,969	-- NEED RESULT: ARCH00379: Elaboration of a block header failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00379 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 12.2 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00379) -- ENT00379_Test_Bench(ARCH00379_Test_Bench) -- -- REVISION HISTORY: -- -- 31-JUL-1987 - initial revision -- 6-APR-1988 - JW: Initial value on block port was not static -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES.all ; architecture ARCH00379 of E00000 is begin B1 : block generic ( g1 : integer ; g2 : integer := 27 ) ; generic map ( g1 => 11 ) ; signal s : bit_vector (1 to 32) ; constant c : bit_vector (g1 to g2) := B"10101010101010101"; -- JW begin B : block -- JW: port ( vec : in bit_vector := s ( g1 to g2 ) ) ; port ( vec : in bit_vector := c ); -- JW constant vec_left : integer := vec'left ; constant vec_right : integer := vec'right ; begin process begin test_report ( "ARCH00379" , "Elaboration of a block header" , (vec_left = 11) and (vec_right = 27) ) ; wait ; end process ; end block B ; end block B1 ; end ARCH00379 ; entity ENT00379_Test_Bench is end ENT00379_Test_Bench ; architecture ARCH00379_Test_Bench of ENT00379_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00379 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00379_Test_Bench ;	gpl-3.0	c6b5c9b25d2e906087b81f2681d7ff81	0.479431	3.4363	false	true	false	false
grwlf/vsim	vhdl_ct/ct00027.vhd	1	3,486	-- NEED RESULT: * An assertion with Report ARCH00027: An assertion with complex string expressions passed and severity of Note should follow -- NEED RESULT: ARCH00027: An assertion with complex string expressions passed -- NEED RESULT: * An assertion with Report ARCH00027: An assertion with complex string expressions passed and severity of Note should follow -- NEED RESULT: ARCH00027: An assertion with complex string expressions passed -- NEED RESULT: * An assertion with Report ARCH00027: An assertion with complex string expressions passed and default severity of Error should follow -- NEED RESULT: * An assertion with Report ARCH00027: An assertion with complex string expressions failed and default severity of Error should follow ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00027 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.2 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00027(ARCH00027) -- ENT00027_Test_Bench(ARCH00027_Test_Bench) -- -- REVISION HISTORY: -- -- 26-JUN-1987 - initial revision -- -- NOTES: -- -- Check that assertion messages match comment messages in output -- use WORK.STANDARD_TYPES.all; entity ENT00027 is generic ( Lowb : Integer := 1 ; Highb : Integer := 12 ) ; port ( msg1 : in string ; msg2 : in string ) ; constant c_msg : string ( 1 to 12 ) := "passedfailed" ; end ENT00027 ; architecture ARCH00027 of ENT00027 is subtype sm_string is string ( Lowb to Highb ) ; constant cc_msg : sm_string := "failedpassed" ; procedure Proc1 ( part1, part2, part3 : in string ) is begin print ( "* An assertion with Report " & part1 & part2 & part3 & " and default severity of Error should follow" ) ; assert false report part1 & part2 & part3; end Proc1 ; signal Dummy : Boolean := false ; begin p1 : process ( Dummy ) begin print ( "* An assertion with Report " & msg1 & msg2 & c_msg(1 to 6) & " and severity of Note should follow" ) ; assert Dummy report msg1 & msg2 & c_msg(1 to 6) severity NOTE ; print ( "*** An assertion with Report " & msg1 & msg2 & cc_msg(7 to Highb) & " and severity of Note should follow" ) ; assert Dummy report msg1 & msg2 & cc_msg(7 to HighB) severity NOTE ; Proc1 ( msg1, msg2, cc_msg(7 to HighB) ) ; Proc1 ( msg1, msg2, cc_msg(1 to 6) ) ; end process p1 ; end ARCH00027 ; entity ENT00027_Test_Bench is end ENT00027_Test_Bench ; architecture ARCH00027_Test_Bench of ENT00027_Test_Bench is begin L1: block component UUT generic ( Lowb : Integer ; Highb : Integer ) ; port ( msg1 : in string ; msg2 : in string ) ; end component ; for CIS1 : UUT use entity WORK.ENT00027 ( ARCH00027 ) ; subtype Name_ST is string (1 to 11) ; signal DU_Name : Name_ST := "ARCH00027: "; subtype Msg_St is string (1 to 45) ; signal msg : Msg_ST := "An assertion with complex string expressions " ; begin CIS1 : UUT generic map ( 1, 12 ) port map ( DU_Name, msg ) ; end block L1 ; end ARCH00027_Test_Bench ;	gpl-3.0	ab593cdf5663f8a06562632142ad48fc	0.592943	3.760518	false	true	false	false
grwlf/vsim	vhdl_ct/ct00295.vhd	1	6,964	-- NEED RESULT: ARCH00295: Bit short circuiting results passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- TEST NAME: -- -- CT00295 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.1 (6) -- 7.2.1 (7) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00295) -- ENT00295_Test_Bench(ARCH00295_Test_Bench) -- -- REVISION HISTORY: -- -- 24-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00295 of E00000 is begin P00295 : process variable vbit : bit; variable bit0 : bit := '0'; variable bit1 : bit := '1'; variable bool : boolean := true ; function do_not_evaluate return bit is begin test_report ( "ARCH00295" , "Bit short circuiting correct" , false ) ; return '0' ; end do_not_evaluate ; begin vbit := bit0 and (do_not_evaluate and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit1 and (bit0 and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit0) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit1 and (bit1 and bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit1) and bit0 ; bool := bool and vbit = '0' ; vbit := bit1 and (bit1 and bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit1) and bit1 ; bool := bool and vbit = '1' ; vbit := bit0 or (bit0 or bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit0) or bit0 ; bool := bool and vbit = '0' ; vbit := bit0 or (bit0 or bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit0) or bit1 ; bool := bool and vbit = '1' ; vbit := bit0 or (bit1 or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit1) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit1 or (do_not_evaluate or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 or do_not_evaluate) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit0 or (bit0 and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit0) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit0 or (bit1 and bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit1) and bit0 ; bool := bool and vbit = '0' ; vbit := bit0 or (bit1 and bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit1) and bit1 ; bool := bool and vbit = '1' ; vbit := bit1 or (do_not_evaluate and do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 or do_not_evaluate) and bit0 ; bool := bool and vbit = '0' ; vbit := (bit1 or do_not_evaluate) and bit1 ; bool := bool and vbit = '1' ; vbit := bit0 and (do_not_evaluate or do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) or bit0 ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) or bit1 ; bool := bool and vbit = '1' ; vbit := bit1 and (bit0 or bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit0) or bit0 ; bool := bool and vbit = '0' ; vbit := bit1 and (bit0 or bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit0) or bit1 ; bool := bool and vbit = '1' ; vbit := bit1 and (bit1 or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit1) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit0 nand (do_not_evaluate nand do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := bit1 nand (bit0 nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit1 nand bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 nand bit1) nand bit0 ; bool := bool and vbit = '1' ; vbit := bit1 nand (bit1 nand bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 nand bit1) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit0 nor bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 nor bit0) nor bit0 ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit0 nor bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 nor bit0) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit1 nor do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit0 nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit1 nand bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 nor bit1) nand bit0 ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit1 nand bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 nor bit1) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit1 nor (do_not_evaluate nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit1 nor do_not_evaluate) nand bit0 ; bool := bool and vbit = '1' ; vbit := (bit1 nor do_not_evaluate) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit0 nand (do_not_evaluate nor do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit0 nand do_not_evaluate) nor bit0 ; bool := bool and vbit = '0' ; vbit := (bit0 nand do_not_evaluate) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit0 nor bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 nand bit0) nor bit0 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit0 nor bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 nand bit0) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit1 nor do_not_evaluate) ; bool := bool and vbit = '1' ; test_report ( "ARCH00295" , "Bit short circuiting results" , bool ) ; wait ; end process P00295 ; end ARCH00295 ; entity ENT00295_Test_Bench is end ENT00295_Test_Bench ; architecture ARCH00295_Test_Bench of ENT00295_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00295 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00295_Test_Bench ;	gpl-3.0	477178724bab90c8468067187dad0585	0.498995	3.115884	false	false	false	false
jairov4/accel-oil	solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_forward_buckets_if.vhd	2	21,283	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if is generic( MPMC_BASE_ADDRESS : std_logic_vector := X"00000000"; USER_DATA_WIDTH : integer := 32; USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width) ); port( --/////////////////////////////////////////////////////////////////////////////// --// MPMC Port Interface - Bus is prefixed with NPI_ NPI_clk : in std_logic; NPI_reset : in std_logic; NPI_Addr : out std_logic_vector(31 downto 0); NPI_AddrReq : out std_logic; NPI_AddrAck : in std_logic; NPI_RNW : out std_logic; NPI_Size : out std_logic_vector(3 downto 0); NPI_WrFIFO_Data : out std_logic_vector(63 downto 0); NPI_WrFIFO_BE : out std_logic_vector(7 downto 0); NPI_WrFIFO_Push : out std_logic; NPI_RdFIFO_Data : in std_logic_vector(63 downto 0); NPI_RdFIFO_Pop : out std_logic; NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0); NPI_WrFIFO_Empty : in std_logic; NPI_WrFIFO_AlmostFull : in std_logic; NPI_WrFIFO_Flush : out std_logic; NPI_RdFIFO_Empty : in std_logic; NPI_RdFIFO_Flush : out std_logic; NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0); NPI_RdModWr : out std_logic; NPI_InitDone : in std_logic; -- signals from user logic ap_clk : in std_logic; ap_reset : in std_logic; USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS USER_size : in std_logic_vector(31 downto 0); -- burst size of word USER_req_nRW : in std_logic; -- req type 0: Read, 1: write USER_req_full_n : out std_logic; -- req Fifo full USER_req_push : in std_logic; -- req Fifo push (new request in) USER_rsp_empty_n: out std_logic; -- return data FIFO empty USER_rsp_pop : in std_logic -- return data FIFO pop ); end entity; architecture arch_nfa_forward_buckets_if OF nfa_forward_buckets_if IS component nfa_forward_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : IN STD_LOGIC; clk_r : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_forward_buckets_if_ap_fifo_af is generic ( DATA_WIDTH : integer := 64; ADDR_WIDTH : integer := 6; DEPTH : integer := 64; ALMOST_FULL_MARGIN : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; constant C_PI_ADDR_WIDTH : integer := 32; constant C_PI_DATA_WIDTH : integer := 64; constant C_PI_BE_WIDTH : integer := 8; constant C_PI_RDWDADDR_WIDTH: integer := 4; constant RSW : integer := 7; -- req size width constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data constant REQ_FIFO_ADDR_WIDTH : integer := 3; constant REQ_FIFO_DEPTH : integer := 8; type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ); signal req_cs, req_ns : req_state_type; type rdata_state_type is (RESET, IDLE, RDATA); signal rdata_cs, rdata_ns : rdata_state_type; -- User interface signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0); signal User_address_local : STD_LOGIC_VECTOR(31 downto 0); -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_dout_req_nRW : STD_LOGIC; signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_reg_en : STD_LOGIC; signal nRW_reg : STD_LOGIC; signal address_reg : STD_LOGIC_VECTOR(31 downto 0); signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0); -- internal request information signal req_nRW : STD_LOGIC; signal req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_WrData_wdAddr : STD_LOGIC; signal req_WrData_reg_en : STD_LOGIC; signal req_WrData_push : STD_LOGIC; signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_valid : STD_LOGIC; -- burst write signal burst_write_reg_en : STD_LOGIC; signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits -- burst read signal burst_read_reg_en : STD_LOGIC; signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0); signal burst_read_wdAddr : STD_LOGIC; -- rsp FIFO constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2) constant RSP_FIFO_ADDR_WIDTH : integer := 2; constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation signal rsp_fifo_empty_n : STD_LOGIC; signal rsp_fifo_pop : STD_LOGIC; signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); signal rsp_fifo_full_n : STD_LOGIC; signal rsp_fifo_push : STD_LOGIC; signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); -- internal rdata pop logic signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC; -- rd FIFO: input: MPMC data out, output: user async fifo signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); -- rd user FIFO: async fifo to user signal rd_user_fifo_empty_n : STD_LOGIC; signal rd_user_fifo_pop : STD_LOGIC; signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_user_fifo_full_n : STD_LOGIC; signal rd_user_fifo_push : STD_LOGIC; signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); begin -- NPI interface NPI_WrFIFO_Flush <= '0'; NPI_RdFIFO_Flush <= '0'; NPI_RdModWr <= '0'; NPI_AddrReq <= req_valid; NPI_Addr <= address_reg; NPI_RNW <= not nRW_reg; NPI_WrFIFO_Push <= req_WrData_push; NPI_WrFIFO_BE <= req_WrData_BE; NPI_RdFIFO_Pop <= rdata_pop; process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data) begin NPI_WrFIFO_Data <= (others => '0'); if (req_WrData_wdAddr = '0') then NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low; else NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data; end if; end process; process (size_reg) begin NPI_Size <= (others => '0'); if (size_reg = "0000100") then --4w NPI_Size <= "0001"; elsif (size_reg = "0001000") then --8w NPI_Size <= "0010"; elsif (size_reg = "0010000") then --16w NPI_Size <= "0011"; elsif (size_reg = "0100000") then --32w NPI_Size <= "0100"; elsif (size_reg = "1000000") then --64w NPI_Size <= "0101"; end if; end process; -- User interface USER_req_full_n <= req_fifo_full_n; USER_rsp_empty_n <= rd_user_fifo_empty_n; USER_RdData <= rd_user_fifo_dout; rd_user_fifo_pop <= USER_rsp_pop; USER_size_local <= User_size(RSW-1 downto 0) when User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW); USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0); USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0'); -- reqest fifo logics req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0); req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData; req_fifo_push <= USER_req_push; U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_async_fifo generic map( DATA_WIDTH => REQ_FIFO_DATA_WIDTH, ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH, DEPTH => REQ_FIFO_DEPTH) port map( clk_w => ap_clk, clk_r => NPI_clk, reset => NPI_reset, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1); req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32); req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW); process(req_fifo_dout) variable i,j: integer; begin -- change byte endian to big endian for i in 0 to USER_DATA_WIDTH/8-1 loop j := USER_DATA_WIDTH/8 -1 -i; req_fifo_dout_wr_data(i8+7 downto i8) <= req_fifo_dout(j8+7 downto j8); end loop; end process; p_req_fifo_out_reg: process (NPI_clk, NPI_reset) variable i,j: integer; begin if (NPI_reset = '1') then nRW_reg <= '0'; address_reg <= (others => '0'); size_reg <= (others => '0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_reg_en = '1') then nRW_reg <= req_fifo_dout_req_nRW; address_reg <= req_fifo_dout_req_address; size_reg <= req_fifo_dout_req_size; end if; end if; end process; -- write and burst write will be controlled by state machine due to MPMC limitation -- read and burst read will have seperate return data phase logic for a pipelined access p_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then req_cs <= req_ns; end if; end process; -- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq -- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW, NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count, req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull) begin req_ns <= FETCH_REQ; req_reg_en <= '0'; req_fifo_pop <= '0'; rsp_fifo_push <= '0'; req_WrData_reg_en <= '0'; burst_write_reg_en <= '0'; req_valid <= '0'; req_WrData_push <= '0'; req_WrData_BE <= "11111111"; case req_cs is when RESET => req_ns <= RESET; if (NPI_InitDone = '1') then req_ns <= FETCH_REQ; end if; when FETCH_REQ => req_ns <= FETCH_REQ; if (req_fifo_empty_n = '1') then if (req_fifo_dout_req_nRW = '1') then req_reg_en <= '1'; req_ns <= REQ; elsif (rsp_fifo_full_n = '1') then req_reg_en <= '1'; req_fifo_pop <= '1'; rsp_fifo_push <= '1'; req_ns <= REQ; end if; end if; when REQ => req_ns <= REQ; if (nRW_reg = '0') then req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then req_valid <= '1'; if (NPI_AddrAck = '1') then req_WrData_reg_en <= '1'; req_ns <= WD_SINGLE; end if; elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then burst_write_reg_en <= '1'; req_ns <= WD_BURST1; end if; when WD_SINGLE => req_ns <= WD_SINGLE; if (NPI_WrFIFO_AlmostFull = '0') then req_WrData_push <= '1'; req_fifo_pop <= '1'; req_ns <= FETCH_REQ; end if; if (req_WrData_wdAddr = '0') then req_WrData_BE <= "00001111"; else req_WrData_BE <= "11110000"; end if; when WD_BURST1 => req_ns <= WD_BURST1; if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; req_WrData_reg_en <= '1'; req_ns <= WD_BURST2; end if; when WD_BURST2 => req_ns <= WD_BURST2; if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then req_fifo_pop <= '1'; req_WrData_push <= '1'; if (burst_write_count /= "000001") then -- not last word req_ns <= WD_BURST1; else req_ns <= WD_BURST_REQ; end if; end if; when WD_BURST_REQ => req_ns <= WD_BURST_REQ; req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_WrData_low <= (others =>'0'); req_WrData_wdAddr <= '0'; burst_write_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_WrData_reg_en = '1') then req_WrData_low <= req_fifo_dout_wr_data; req_WrData_wdAddr <= req_fifo_dout_req_address(2); end if; if (burst_write_reg_en = '1') then burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6); elsif (req_WrData_push = '1') then burst_write_count <= burst_write_count-1; end if; end if; end process; -- below is the response (read data) part U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => RSP_FIFO_DATA_WIDTH, ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH, DEPTH => RSP_FIFO_DEPTH) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rsp_fifo_empty_n, if_read => rsp_fifo_pop, if_dout => rsp_fifo_dout, if_full_n => rsp_fifo_full_n, if_write => rsp_fifo_push, if_din => rsp_fifo_din ); rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size; rsp_fifo_din(0) <= req_fifo_dout_req_address(2); rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_pop_reg1 <= '0'; rdata_pop_reg2 <= '0'; elsif (NPI_clk'event and NPI_clk = '1') then rdata_pop_reg1 <= rdata_pop; rdata_pop_reg2 <= rdata_pop_reg1; end if; end process; process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2) begin if (NPI_RdFIFO_Latency = "00") then rd_fifo_push <= rdata_pop; elsif (NPI_RdFIFO_Latency = "01") then rd_fifo_push <= rdata_pop_reg1; else rd_fifo_push <= rdata_pop_reg2; end if; end process; rd_fifo_din <= NPI_RdFIFO_Data; -- 1. this fifo provide two 64w burst storage -- 2. with almost full signal for MPMC has potential 2 latency from pop to data -- 3. can't replace this fifo with asyn fifo which doesn't support almost_full U_nfa_forward_buckets_if_rd_fifo: component nfa_forward_buckets_if_ap_fifo_af generic map( DATA_WIDTH => C_PI_DATA_WIDTH, ADDR_WIDTH => 6, DEPTH => 64, ALMOST_FULL_MARGIN => 2) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, -- this is almost_full signal if_write => rd_fifo_push, if_din => rd_fifo_din ); process(rd_fifo_dout) variable i,j : integer; begin -- change byte endian to big endian for i in 0 to C_PI_BE_WIDTH-1 loop j := C_PI_BE_WIDTH-1 -i; rd_fifo_dout_endian(i8+7 downto i8) <= rd_fifo_dout(j8+7 downto j8); end loop; end process; p_rdata_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then rdata_cs <= rdata_ns; end if; end process; p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count) begin rdata_ns <= RESET; case rdata_cs is when RESET => if (NPI_InitDone = '1') then rdata_ns <= IDLE; end if; when IDLE => rdata_ns <= IDLE; if (rsp_fifo_empty_n = '1') then rdata_ns <= RDATA; end if; when RDATA => rdata_ns <= RDATA; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then rdata_ns <= IDLE; end if; when others => null; end case; end process; p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count, rd_fifo_empty_n, rd_user_fifo_full_n) begin burst_read_reg_en <= '0'; rd_fifo_pop <= '0'; rd_user_fifo_push <= '0'; rsp_fifo_pop <= '0'; case rdata_cs is when RESET => null; when IDLE => if (rsp_fifo_empty_n = '1') then burst_read_reg_en <= '1'; end if; when RDATA => if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and rd_user_fifo_full_n = '1') then if (burst_read_count(0) = '1') then rd_fifo_pop <= '1'; end if; rd_user_fifo_push <= '1'; end if; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then rsp_fifo_pop <= '1'; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then burst_read_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (burst_read_reg_en = '1') then burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW); burst_read_wdAddr <= rsp_fifo_dout(0); elsif (rd_user_fifo_push = '1') then burst_read_count <= burst_read_count -1; burst_read_wdAddr <= not burst_read_wdAddr; end if; end if; end process; rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH); U_nfa_forward_buckets_if_rd_user_fifo: component nfa_forward_buckets_if_async_fifo generic map( DATA_WIDTH => USER_DATA_WIDTH, ADDR_WIDTH => 3, DEPTH => 8) port map( clk_w => NPI_clk, clk_r => ap_clk, reset => NPI_reset, if_empty_n => rd_user_fifo_empty_n, if_read => rd_user_fifo_pop, if_dout => rd_user_fifo_dout, if_full_n => rd_user_fifo_full_n, if_write => rd_user_fifo_push, if_din => rd_user_fifo_din ); end arch_nfa_forward_buckets_if;	lgpl-3.0	a03da993ab775b87cdf381ff8d0b42e7	0.577033	3.097511	false	false	false	false
grwlf/vsim	vhdl/assign3.1.vhd	1	44,434	-- 500 variable assignments in 2 processes. Assigning a signal. entity main is end entity main ; architecture arch of main is signal clk : integer := 0; constant CYCLES : integer := 1000; begin main: process(clk) --{{{ variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0502 := clk; a0503 := clk; a0504 := clk; a0505 := clk; a0506 := clk; a0507 := clk; a0508 := clk; a0509 := clk; a0510 := clk; a0511 := clk; a0512 := clk; a0513 := clk; a0514 := clk; a0515 := clk; a0516 := clk; a0517 := clk; a0518 := clk; a0519 := clk; a0520 := clk; a0521 := clk; a0522 := clk; a0523 := clk; a0524 := clk; a0525 := clk; a0526 := clk; a0527 := clk; a0528 := clk; a0529 := clk; a0530 := clk; a0531 := clk; a0532 := clk; a0533 := clk; a0534 := clk; a0535 := clk; a0536 := clk; a0537 := clk; a0538 := clk; a0539 := clk; a0540 := clk; a0541 := clk; a0542 := clk; a0543 := clk; a0544 := clk; a0545 := clk; a0546 := clk; a0547 := clk; a0548 := clk; a0549 := clk; a0550 := clk; a0551 := clk; a0552 := clk; a0553 := clk; a0554 := clk; a0555 := clk; a0556 := clk; a0557 := clk; a0558 := clk; a0559 := clk; a0560 := clk; a0561 := clk; a0562 := clk; a0563 := clk; a0564 := clk; a0565 := clk; a0566 := clk; a0567 := clk; a0568 := clk; a0569 := clk; a0570 := clk; a0571 := clk; a0572 := clk; a0573 := clk; a0574 := clk; a0575 := clk; a0576 := clk; a0577 := clk; a0578 := clk; a0579 := clk; a0580 := clk; a0581 := clk; a0582 := clk; a0583 := clk; a0584 := clk; a0585 := clk; a0586 := clk; a0587 := clk; a0588 := clk; a0589 := clk; a0590 := clk; a0591 := clk; a0592 := clk; a0593 := clk; a0594 := clk; a0595 := clk; a0596 := clk; a0597 := clk; a0598 := clk; a0599 := clk; a0600 := clk; a0601 := clk; a0602 := clk; a0603 := clk; a0604 := clk; a0605 := clk; a0606 := clk; a0607 := clk; a0608 := clk; a0609 := clk; a0610 := clk; a0611 := clk; a0612 := clk; a0613 := clk; a0614 := clk; a0615 := clk; a0616 := clk; a0617 := clk; a0618 := clk; a0619 := clk; a0620 := clk; a0621 := clk; a0622 := clk; a0623 := clk; a0624 := clk; a0625 := clk; a0626 := clk; a0627 := clk; a0628 := clk; a0629 := clk; a0630 := clk; a0631 := clk; a0632 := clk; a0633 := clk; a0634 := clk; a0635 := clk; a0636 := clk; a0637 := clk; a0638 := clk; a0639 := clk; a0640 := clk; a0641 := clk; a0642 := clk; a0643 := clk; a0644 := clk; a0645 := clk; a0646 := clk; a0647 := clk; a0648 := clk; a0649 := clk; a0650 := clk; a0651 := clk; a0652 := clk; a0653 := clk; a0654 := clk; a0655 := clk; a0656 := clk; a0657 := clk; a0658 := clk; a0659 := clk; a0660 := clk; a0661 := clk; a0662 := clk; a0663 := clk; a0664 := clk; a0665 := clk; a0666 := clk; a0667 := clk; a0668 := clk; a0669 := clk; a0670 := clk; a0671 := clk; a0672 := clk; a0673 := clk; a0674 := clk; a0675 := clk; a0676 := clk; a0677 := clk; a0678 := clk; a0679 := clk; a0680 := clk; a0681 := clk; a0682 := clk; a0683 := clk; a0684 := clk; a0685 := clk; a0686 := clk; a0687 := clk; a0688 := clk; a0689 := clk; a0690 := clk; a0691 := clk; a0692 := clk; a0693 := clk; a0694 := clk; a0695 := clk; a0696 := clk; a0697 := clk; a0698 := clk; a0699 := clk; a0700 := clk; a0701 := clk; a0702 := clk; a0703 := clk; a0704 := clk; a0705 := clk; a0706 := clk; a0707 := clk; a0708 := clk; a0709 := clk; a0710 := clk; a0711 := clk; a0712 := clk; a0713 := clk; a0714 := clk; a0715 := clk; a0716 := clk; a0717 := clk; a0718 := clk; a0719 := clk; a0720 := clk; a0721 := clk; a0722 := clk; a0723 := clk; a0724 := clk; a0725 := clk; a0726 := clk; a0727 := clk; a0728 := clk; a0729 := clk; a0730 := clk; a0731 := clk; a0732 := clk; a0733 := clk; a0734 := clk; a0735 := clk; a0736 := clk; a0737 := clk; a0738 := clk; a0739 := clk; a0740 := clk; a0741 := clk; a0742 := clk; a0743 := clk; a0744 := clk; a0745 := clk; a0746 := clk; a0747 := clk; a0748 := clk; a0749 := clk; a0750 := clk; a0751 := clk; a0752 := clk; a0753 := clk; a0754 := clk; a0755 := clk; a0756 := clk; a0757 := clk; a0758 := clk; a0759 := clk; a0760 := clk; a0761 := clk; a0762 := clk; a0763 := clk; a0764 := clk; a0765 := clk; a0766 := clk; a0767 := clk; a0768 := clk; a0769 := clk; a0770 := clk; a0771 := clk; a0772 := clk; a0773 := clk; a0774 := clk; a0775 := clk; a0776 := clk; a0777 := clk; a0778 := clk; a0779 := clk; a0780 := clk; a0781 := clk; a0782 := clk; a0783 := clk; a0784 := clk; a0785 := clk; a0786 := clk; a0787 := clk; a0788 := clk; a0789 := clk; a0790 := clk; a0791 := clk; a0792 := clk; a0793 := clk; a0794 := clk; a0795 := clk; a0796 := clk; a0797 := clk; a0798 := clk; a0799 := clk; a0800 := clk; a0801 := clk; a0802 := clk; a0803 := clk; a0804 := clk; a0805 := clk; a0806 := clk; a0807 := clk; a0808 := clk; a0809 := clk; a0810 := clk; a0811 := clk; a0812 := clk; a0813 := clk; a0814 := clk; a0815 := clk; a0816 := clk; a0817 := clk; a0818 := clk; a0819 := clk; a0820 := clk; a0821 := clk; a0822 := clk; a0823 := clk; a0824 := clk; a0825 := clk; a0826 := clk; a0827 := clk; a0828 := clk; a0829 := clk; a0830 := clk; a0831 := clk; a0832 := clk; a0833 := clk; a0834 := clk; a0835 := clk; a0836 := clk; a0837 := clk; a0838 := clk; a0839 := clk; a0840 := clk; a0841 := clk; a0842 := clk; a0843 := clk; a0844 := clk; a0845 := clk; a0846 := clk; a0847 := clk; a0848 := clk; a0849 := clk; a0850 := clk; a0851 := clk; a0852 := clk; a0853 := clk; a0854 := clk; a0855 := clk; a0856 := clk; a0857 := clk; a0858 := clk; a0859 := clk; a0860 := clk; a0861 := clk; a0862 := clk; a0863 := clk; a0864 := clk; a0865 := clk; a0866 := clk; a0867 := clk; a0868 := clk; a0869 := clk; a0870 := clk; a0871 := clk; a0872 := clk; a0873 := clk; a0874 := clk; a0875 := clk; a0876 := clk; a0877 := clk; a0878 := clk; a0879 := clk; a0880 := clk; a0881 := clk; a0882 := clk; a0883 := clk; a0884 := clk; a0885 := clk; a0886 := clk; a0887 := clk; a0888 := clk; a0889 := clk; a0890 := clk; a0891 := clk; a0892 := clk; a0893 := clk; a0894 := clk; a0895 := clk; a0896 := clk; a0897 := clk; a0898 := clk; a0899 := clk; a0900 := clk; a0901 := clk; a0902 := clk; a0903 := clk; a0904 := clk; a0905 := clk; a0906 := clk; a0907 := clk; a0908 := clk; a0909 := clk; a0910 := clk; a0911 := clk; a0912 := clk; a0913 := clk; a0914 := clk; a0915 := clk; a0916 := clk; a0917 := clk; a0918 := clk; a0919 := clk; a0920 := clk; a0921 := clk; a0922 := clk; a0923 := clk; a0924 := clk; a0925 := clk; a0926 := clk; a0927 := clk; a0928 := clk; a0929 := clk; a0930 := clk; a0931 := clk; a0932 := clk; a0933 := clk; a0934 := clk; a0935 := clk; a0936 := clk; a0937 := clk; a0938 := clk; a0939 := clk; a0940 := clk; a0941 := clk; a0942 := clk; a0943 := clk; a0944 := clk; a0945 := clk; a0946 := clk; a0947 := clk; a0948 := clk; a0949 := clk; a0950 := clk; a0951 := clk; a0952 := clk; a0953 := clk; a0954 := clk; a0955 := clk; a0956 := clk; a0957 := clk; a0958 := clk; a0959 := clk; a0960 := clk; a0961 := clk; a0962 := clk; a0963 := clk; a0964 := clk; a0965 := clk; a0966 := clk; a0967 := clk; a0968 := clk; a0969 := clk; a0970 := clk; a0971 := clk; a0972 := clk; a0973 := clk; a0974 := clk; a0975 := clk; a0976 := clk; a0977 := clk; a0978 := clk; a0979 := clk; a0980 := clk; a0981 := clk; a0982 := clk; a0983 := clk; a0984 := clk; a0985 := clk; a0986 := clk; a0987 := clk; a0988 := clk; a0989 := clk; a0990 := clk; a0991 := clk; a0992 := clk; a0993 := clk; a0994 := clk; a0995 := clk; a0996 := clk; a0997 := clk; a0998 := clk; a0999 := clk; a1000 := clk; --}}} end process; main1: process(clk) --{{{ variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0502 := clk; a0503 := clk; a0504 := clk; a0505 := clk; a0506 := clk; a0507 := clk; a0508 := clk; a0509 := clk; a0510 := clk; a0511 := clk; a0512 := clk; a0513 := clk; a0514 := clk; a0515 := clk; a0516 := clk; a0517 := clk; a0518 := clk; a0519 := clk; a0520 := clk; a0521 := clk; a0522 := clk; a0523 := clk; a0524 := clk; a0525 := clk; a0526 := clk; a0527 := clk; a0528 := clk; a0529 := clk; a0530 := clk; a0531 := clk; a0532 := clk; a0533 := clk; a0534 := clk; a0535 := clk; a0536 := clk; a0537 := clk; a0538 := clk; a0539 := clk; a0540 := clk; a0541 := clk; a0542 := clk; a0543 := clk; a0544 := clk; a0545 := clk; a0546 := clk; a0547 := clk; a0548 := clk; a0549 := clk; a0550 := clk; a0551 := clk; a0552 := clk; a0553 := clk; a0554 := clk; a0555 := clk; a0556 := clk; a0557 := clk; a0558 := clk; a0559 := clk; a0560 := clk; a0561 := clk; a0562 := clk; a0563 := clk; a0564 := clk; a0565 := clk; a0566 := clk; a0567 := clk; a0568 := clk; a0569 := clk; a0570 := clk; a0571 := clk; a0572 := clk; a0573 := clk; a0574 := clk; a0575 := clk; a0576 := clk; a0577 := clk; a0578 := clk; a0579 := clk; a0580 := clk; a0581 := clk; a0582 := clk; a0583 := clk; a0584 := clk; a0585 := clk; a0586 := clk; a0587 := clk; a0588 := clk; a0589 := clk; a0590 := clk; a0591 := clk; a0592 := clk; a0593 := clk; a0594 := clk; a0595 := clk; a0596 := clk; a0597 := clk; a0598 := clk; a0599 := clk; a0600 := clk; a0601 := clk; a0602 := clk; a0603 := clk; a0604 := clk; a0605 := clk; a0606 := clk; a0607 := clk; a0608 := clk; a0609 := clk; a0610 := clk; a0611 := clk; a0612 := clk; a0613 := clk; a0614 := clk; a0615 := clk; a0616 := clk; a0617 := clk; a0618 := clk; a0619 := clk; a0620 := clk; a0621 := clk; a0622 := clk; a0623 := clk; a0624 := clk; a0625 := clk; a0626 := clk; a0627 := clk; a0628 := clk; a0629 := clk; a0630 := clk; a0631 := clk; a0632 := clk; a0633 := clk; a0634 := clk; a0635 := clk; a0636 := clk; a0637 := clk; a0638 := clk; a0639 := clk; a0640 := clk; a0641 := clk; a0642 := clk; a0643 := clk; a0644 := clk; a0645 := clk; a0646 := clk; a0647 := clk; a0648 := clk; a0649 := clk; a0650 := clk; a0651 := clk; a0652 := clk; a0653 := clk; a0654 := clk; a0655 := clk; a0656 := clk; a0657 := clk; a0658 := clk; a0659 := clk; a0660 := clk; a0661 := clk; a0662 := clk; a0663 := clk; a0664 := clk; a0665 := clk; a0666 := clk; a0667 := clk; a0668 := clk; a0669 := clk; a0670 := clk; a0671 := clk; a0672 := clk; a0673 := clk; a0674 := clk; a0675 := clk; a0676 := clk; a0677 := clk; a0678 := clk; a0679 := clk; a0680 := clk; a0681 := clk; a0682 := clk; a0683 := clk; a0684 := clk; a0685 := clk; a0686 := clk; a0687 := clk; a0688 := clk; a0689 := clk; a0690 := clk; a0691 := clk; a0692 := clk; a0693 := clk; a0694 := clk; a0695 := clk; a0696 := clk; a0697 := clk; a0698 := clk; a0699 := clk; a0700 := clk; a0701 := clk; a0702 := clk; a0703 := clk; a0704 := clk; a0705 := clk; a0706 := clk; a0707 := clk; a0708 := clk; a0709 := clk; a0710 := clk; a0711 := clk; a0712 := clk; a0713 := clk; a0714 := clk; a0715 := clk; a0716 := clk; a0717 := clk; a0718 := clk; a0719 := clk; a0720 := clk; a0721 := clk; a0722 := clk; a0723 := clk; a0724 := clk; a0725 := clk; a0726 := clk; a0727 := clk; a0728 := clk; a0729 := clk; a0730 := clk; a0731 := clk; a0732 := clk; a0733 := clk; a0734 := clk; a0735 := clk; a0736 := clk; a0737 := clk; a0738 := clk; a0739 := clk; a0740 := clk; a0741 := clk; a0742 := clk; a0743 := clk; a0744 := clk; a0745 := clk; a0746 := clk; a0747 := clk; a0748 := clk; a0749 := clk; a0750 := clk; a0751 := clk; a0752 := clk; a0753 := clk; a0754 := clk; a0755 := clk; a0756 := clk; a0757 := clk; a0758 := clk; a0759 := clk; a0760 := clk; a0761 := clk; a0762 := clk; a0763 := clk; a0764 := clk; a0765 := clk; a0766 := clk; a0767 := clk; a0768 := clk; a0769 := clk; a0770 := clk; a0771 := clk; a0772 := clk; a0773 := clk; a0774 := clk; a0775 := clk; a0776 := clk; a0777 := clk; a0778 := clk; a0779 := clk; a0780 := clk; a0781 := clk; a0782 := clk; a0783 := clk; a0784 := clk; a0785 := clk; a0786 := clk; a0787 := clk; a0788 := clk; a0789 := clk; a0790 := clk; a0791 := clk; a0792 := clk; a0793 := clk; a0794 := clk; a0795 := clk; a0796 := clk; a0797 := clk; a0798 := clk; a0799 := clk; a0800 := clk; a0801 := clk; a0802 := clk; a0803 := clk; a0804 := clk; a0805 := clk; a0806 := clk; a0807 := clk; a0808 := clk; a0809 := clk; a0810 := clk; a0811 := clk; a0812 := clk; a0813 := clk; a0814 := clk; a0815 := clk; a0816 := clk; a0817 := clk; a0818 := clk; a0819 := clk; a0820 := clk; a0821 := clk; a0822 := clk; a0823 := clk; a0824 := clk; a0825 := clk; a0826 := clk; a0827 := clk; a0828 := clk; a0829 := clk; a0830 := clk; a0831 := clk; a0832 := clk; a0833 := clk; a0834 := clk; a0835 := clk; a0836 := clk; a0837 := clk; a0838 := clk; a0839 := clk; a0840 := clk; a0841 := clk; a0842 := clk; a0843 := clk; a0844 := clk; a0845 := clk; a0846 := clk; a0847 := clk; a0848 := clk; a0849 := clk; a0850 := clk; a0851 := clk; a0852 := clk; a0853 := clk; a0854 := clk; a0855 := clk; a0856 := clk; a0857 := clk; a0858 := clk; a0859 := clk; a0860 := clk; a0861 := clk; a0862 := clk; a0863 := clk; a0864 := clk; a0865 := clk; a0866 := clk; a0867 := clk; a0868 := clk; a0869 := clk; a0870 := clk; a0871 := clk; a0872 := clk; a0873 := clk; a0874 := clk; a0875 := clk; a0876 := clk; a0877 := clk; a0878 := clk; a0879 := clk; a0880 := clk; a0881 := clk; a0882 := clk; a0883 := clk; a0884 := clk; a0885 := clk; a0886 := clk; a0887 := clk; a0888 := clk; a0889 := clk; a0890 := clk; a0891 := clk; a0892 := clk; a0893 := clk; a0894 := clk; a0895 := clk; a0896 := clk; a0897 := clk; a0898 := clk; a0899 := clk; a0900 := clk; a0901 := clk; a0902 := clk; a0903 := clk; a0904 := clk; a0905 := clk; a0906 := clk; a0907 := clk; a0908 := clk; a0909 := clk; a0910 := clk; a0911 := clk; a0912 := clk; a0913 := clk; a0914 := clk; a0915 := clk; a0916 := clk; a0917 := clk; a0918 := clk; a0919 := clk; a0920 := clk; a0921 := clk; a0922 := clk; a0923 := clk; a0924 := clk; a0925 := clk; a0926 := clk; a0927 := clk; a0928 := clk; a0929 := clk; a0930 := clk; a0931 := clk; a0932 := clk; a0933 := clk; a0934 := clk; a0935 := clk; a0936 := clk; a0937 := clk; a0938 := clk; a0939 := clk; a0940 := clk; a0941 := clk; a0942 := clk; a0943 := clk; a0944 := clk; a0945 := clk; a0946 := clk; a0947 := clk; a0948 := clk; a0949 := clk; a0950 := clk; a0951 := clk; a0952 := clk; a0953 := clk; a0954 := clk; a0955 := clk; a0956 := clk; a0957 := clk; a0958 := clk; a0959 := clk; a0960 := clk; a0961 := clk; a0962 := clk; a0963 := clk; a0964 := clk; a0965 := clk; a0966 := clk; a0967 := clk; a0968 := clk; a0969 := clk; a0970 := clk; a0971 := clk; a0972 := clk; a0973 := clk; a0974 := clk; a0975 := clk; a0976 := clk; a0977 := clk; a0978 := clk; a0979 := clk; a0980 := clk; a0981 := clk; a0982 := clk; a0983 := clk; a0984 := clk; a0985 := clk; a0986 := clk; a0987 := clk; a0988 := clk; a0989 := clk; a0990 := clk; a0991 := clk; a0992 := clk; a0993 := clk; a0994 := clk; a0995 := clk; a0996 := clk; a0997 := clk; a0998 := clk; a0999 := clk; a1000 := clk; --}}} end process; terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; clk <= (clk+1) after 1 us; end;	gpl-3.0	6c1913ef843634fe476b700dafdbb19e	0.636517	2.729194	false	false	false	false
takeshineshiro/fpga_fibre_scan	HUCB2P0_150701/p2s_dac.vhd	1	897	library ieee; use ieee.std_logic_1164.all; entity p2s_dac is port( a,clk,clr: in std_logic; datain1:in std_logic_vector(15 downto 0); ld,s_data: out std_logic); end p2s_dac; architecture art of p2s_dac is begin process(a,clk,clr) variable I: integer; begin if(clr='1') then I:=0;ld<='0'; elsif( clk'event and clk='1') then if(a='1') then if(I=0) then I:=16; s_data<='0'; else s_data<=datain1(I-1); I:=I-1; ld<='1'; end if; else ld<='0'; end if; end if; end process ; end art;	apache-2.0	3adee115ec36b0157a23fdb7b08196ff	0.354515	4.022422	false	false	false	false
grwlf/vsim	vhdl_ct/ct00489.vhd	1	7,554	-- NEED RESULT: ARCH00489: Aggregates with others choice associated with formal generic (locally static) passed -- NEED RESULT: ARCH00489: Aggregates with others choice associated with formal parameter (locally static) passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00489 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (3) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00489(ARCH00489) -- ENT00489_Test_Bench(ARCH00489_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00489 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; constant r1 : integer := 1 ; constant a11 : boolean := false ; constant a12 : boolean := true ; constant a21 : integer := 1 ; constant a22 : integer := 5 ; constant b11 : integer := 0 ; constant b12 : integer := 0 ; constant b21 : integer := -5 ; constant b22 : integer := -3 ; constant c1 : integer := 0 ; constant c2 : integer := 4 ; constant d1 : integer := 3 ; constant d2 : integer := 5 ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - r1 to r1 ; -- f2 : rec_arr (-r1 to r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-r1 to r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range a11 to a12 ; subtype arange2 is integer range a21 to a22 ; subtype brange1 is integer range b11 to b12 ; subtype brange2 is integer range b21 to b22 ; subtype crange is integer range c1 to c2 ; subtype drange is integer range d1 to d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00489 ; -- architecture ARCH00489 of ENT00489 is begin B1 : block generic ( g_arr_1 : st_arr_1 ; g_time_matrix : st_time_matrix ; g_bit_vector : st_bit_vector ; g_string : st_string ; g_rec_1 : rec_1 ) ; generic map ( ( ( c_rec_1_1, others => c_rec_1_2 ), others => (others => c_rec_1_1) ) , ( st_time_matrix'right(1) => ( st_time_matrix'right(2) => 10 ns, others => 5 fs), others => (brange2'left => 10 ps, others => 15ms) ) , ( 0 => '1', 2 => '1', others => '0' ) , ( 3 => 'a', 4 => 'b', others => '0' ) , -- ( f2 => (r1 => true, others => false ) , ( f3 => 1, others => 0) ) ; -- procedure p1 ( p_arr_1 : st_arr_1 ; p_time_matrix : st_time_matrix ; p_bit_vector : st_bit_vector ; p_string : st_string ; p_rec_1 : rec_1 ) is variable bool : boolean := true ; begin bool := bool and g_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and g_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and g_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and g_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and g_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and g_bit_vector = B"10100" ; -- bool := bool and g_string = "ab0" ; -- bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0 and g_rec_1.f3 = 1 ; -- bool := bool and g_rec_1.f2(1) = true -- and g_rec_1.f2(0) = false and -- g_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00489" , "Aggregates with others choice associated with formal" & " generic (locally static)" , bool ) ; -- bool := true ; bool := bool and p_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and p_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and p_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and p_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and p_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and p_bit_vector = B"10100" ; -- bool := bool and p_string = "ab0" ; -- bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0 and p_rec_1.f3 = 1 ; -- bool := bool and p_rec_1.f2(1) = true -- and p_rec_1.f2(0) = false and -- p_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00489" , "Aggregates with others choice associated with formal" & " parameter (locally static)" , bool ) ; end p1 ; begin process begin p1 ( ( ( c_rec_1_1, others => c_rec_1_2 ), others => (others => c_rec_1_1) ) , ( st_time_matrix'right(1) => ( st_time_matrix'right(2) => 10 ns, others => 5 fs), others => (brange2'left => 10 ps, others => 15ms) ) , ( 0 => '1', 2 => '1', others => '0' ) , ( 3 => 'a', 4 => 'b', others => '0' ) , -- ( f2 => (r1 => true, others => false ) , ( f3 => 1, others => 0) ) ; wait ; end process ; end block B1 ; end ARCH00489 ; -- entity ENT00489_Test_Bench is end ENT00489_Test_Bench ; -- architecture ARCH00489_Test_Bench of ENT00489_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00489 ( ARCH00489 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00489_Test_Bench ;	gpl-3.0	ab9cf63a25938b4bf05220378c6d30da	0.459624	3.317523	false	true	false	false
grwlf/vsim	vhdl_ct/ct00625.vhd	1	5,945	-- NEED RESULT: ARCH00625: Concurrent proc call 1 passed -- NEED RESULT: ARCH00625.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00625: Concurrent proc call 2 passed -- NEED RESULT: ARCH00625: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00625: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00625 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00625(ARCH00625) -- ENT00625_Test_Bench(ARCH00625_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00625 is end ENT00625 ; -- -- architecture ARCH00625 of ENT00625 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_rec3_select : select_type := 1 ; -- signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- procedure P1 (signal s_st_rec3 : in st_rec3 ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_2.f3(lowb,true) after 10 ns, -- c_st_rec3_1.f3(lowb,true) after 20 ns ; -- when 1 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_2.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_1.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_2.f3(lowb,true) after 10 ns , -- c_st_rec3_1.f3(lowb,true) after 20 ns , -- c_st_rec3_2.f3(lowb,true) after 30 ns , -- c_st_rec3_1.f3(lowb,true) after 40 ns ; -- when 3 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_2.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_1.f3(lowb,true) after 5 ns ; -- when 4 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_1.f3(lowb,true) and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00625" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00625" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec3_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_rec3 , st_rec3_select , s_st_rec3_savt , chk_st_rec3 , s_st_rec3_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_rec3_select select s_st_rec3.f3(lowb,true) <= transport c_st_rec3_2.f3(lowb,true) after 10 ns, c_st_rec3_1.f3(lowb,true) after 20 ns when 1, -- c_st_rec3_2.f3(lowb,true) after 10 ns , c_st_rec3_1.f3(lowb,true) after 20 ns , c_st_rec3_2.f3(lowb,true) after 30 ns , c_st_rec3_1.f3(lowb,true) after 40 ns when 2, -- c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ; -- end ARCH00625 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00625_Test_Bench is end ENT00625_Test_Bench ; -- -- architecture ARCH00625_Test_Bench of ENT00625_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00625 ( ARCH00625 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00625_Test_Bench ;	gpl-3.0	2e421ff5c2a9dee1a1ca70583f8e3cf3	0.507485	3.216991	false	true	false	false
grwlf/vsim	vhdl_ct/ct00098.vhd	1	15,031	-- NEED RESULT: ARCH00098.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098.P2: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098.P3: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00098 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00098(ARCH00098) -- ENT00098_Test_Bench(ARCH00098_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00098 is port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- end ENT00098 ; -- architecture ARCH00098 of ENT00098 is begin PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_arr1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P1" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_1(highb) ( st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_arr2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P2" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_arr3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P3" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- -- end ARCH00098 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00098_Test_Bench is signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00098_Test_Bench ; -- architecture ARCH00098_Test_Bench of ENT00098_Test_Bench is begin L1: block component UUT port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00098 ( ARCH00098 ) ; begin CIS1 : UUT port map ( s_st_arr1_vector , s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00098_Test_Bench ;	gpl-3.0	3580077d237c74535aed5ac827aa8f3e	0.505223	3.591637	false	true	false	false
grwlf/vsim	vhdl_ct/ct00408.vhd	1	22,816	-- NEED RESULT: ARCH00408.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00408 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00408(ARCH00408) -- ENT00408_Test_Bench(ARCH00408_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00408 is port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00408 ; -- -- architecture ARCH00408 of ENT00408 is subtype chk_time_type is Time ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_rec2_vector_savt : chk_time_type := 0 ns ; signal s_st_rec3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_rec1_vector_select : select_type := 1 ; signal st_rec2_vector_select : select_type := 1 ; signal st_rec3_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns, -- c_st_rec1_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 4 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 5 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; wait until (not s_st_rec1_vector(lowb).f2'Quiet) and (s_st_rec1_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec1_vector(lowb).f2 <= c_st_rec1_vector_2(lowb).f2 after 10 ns, c_st_rec1_vector_1(lowb).f2 after 20 ns when st_rec1_vector_select = 1 else -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when st_rec1_vector_select = 2 else -- c_st_rec1_vector_1(lowb).f2 after 5 ns when st_rec1_vector_select = 3 else -- c_st_rec1_vector_1(lowb).f2 after 100 ns when st_rec1_vector_select = 4 else -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when st_rec1_vector_select = 5 else -- -- Last transaction above is marked c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_st_rec2_vector_cnt is when 0 => null ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns, -- c_st_rec2_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_vector_select <= transport 2 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; st_rec2_vector_select <= transport 3 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 4 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 5 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_vector_savt <= transport Std.Standard.Now ; chk_st_rec2_vector <= transport s_st_rec2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ; wait until (not s_st_rec2_vector(lowb).f2'Quiet) and (s_st_rec2_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_rec2_vector(lowb).f2 <= c_st_rec2_vector_2(lowb).f2 after 10 ns, c_st_rec2_vector_1(lowb).f2 after 20 ns when st_rec2_vector_select = 1 else -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when st_rec2_vector_select = 2 else -- c_st_rec2_vector_1(lowb).f2 after 5 ns when st_rec2_vector_select = 3 else -- c_st_rec2_vector_1(lowb).f2 after 100 ns when st_rec2_vector_select = 4 else -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when st_rec2_vector_select = 5 else -- -- Last transaction above is marked c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_st_rec3_vector_cnt is when 0 => null ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns, -- c_st_rec3_vector_1(highb).f3 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_vector_select <= transport 2 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; st_rec3_vector_select <= transport 3 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 4 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 100 ns ; -- when 5 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 5 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 6 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 7 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_vector_savt <= transport Std.Standard.Now ; chk_st_rec3_vector <= transport s_st_rec3_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ; wait until (not s_st_rec3_vector(highb).f3'Quiet) and (s_st_rec3_vector_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_rec3_vector(highb).f3 <= c_st_rec3_vector_2(highb).f3 after 10 ns, c_st_rec3_vector_1(highb).f3 after 20 ns when st_rec3_vector_select = 1 else -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when st_rec3_vector_select = 2 else -- c_st_rec3_vector_1(highb).f3 after 5 ns when st_rec3_vector_select = 3 else -- c_st_rec3_vector_1(highb).f3 after 100 ns when st_rec3_vector_select = 4 else -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when st_rec3_vector_select = 5 else -- -- Last transaction above is marked c_st_rec3_vector_1(highb).f3 after 40 ns ; -- end ARCH00408 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00408_Test_Bench is signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- end ENT00408_Test_Bench ; -- -- architecture ARCH00408_Test_Bench of ENT00408_Test_Bench is begin L1: block component UUT port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00408 ( ARCH00408 ) ; begin CIS1 : UUT port map ( s_st_rec1_vector , s_st_rec2_vector , s_st_rec3_vector ) ; end block L1 ; end ARCH00408_Test_Bench ;	gpl-3.0	45ad81bee1f443f64b1d792425f14b0c	0.5103	3.294254	false	false	false	false
jairov4/accel-oil	impl/impl_test_pcie/hdl/system_ac1_plb_wrapper.vhd	1	14,691	------------------------------------------------------------------------------- -- system_ac1_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_ac1_plb_wrapper : entity is "plb_v46_v1_05_a"; end system_ac1_plb_wrapper; architecture STRUCTURE of system_ac1_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERSC_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVESC_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERSC_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin ac1_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 15, C_PLBV46_NUM_SLAVES => 1, C_PLBV46_MID_WIDTH => 4, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;	lgpl-3.0	5d7a89905b39706b2cfcfc3e077b90e5	0.611871	3.039098	false	false	false	false
grwlf/vsim	vhdl_ct/ct00025.vhd	1	7,581	-- NEED RESULT: ENT00025: Associated composite in ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00025 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (4) -- 1.1.1.2 (7) -- -- DESIGN UNIT ORDERING: -- -- ENT00025(ARCH00025) -- ENT00025_Test_Bench(ARCH00025_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00025 is port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; begin end ENT00025 ; -- architecture ARCH00025 of ENT00025 is begin process variable correct : boolean := true ; begin correct := correct and i_bit_vector_1 = c_st_bit_vector_1 and i_bit_vector_2 = c_st_bit_vector_1 ; correct := correct and i_string_1 = c_st_string_1 and i_string_2 = c_st_string_1 ; correct := correct and i_t_rec1_1 = c_st_rec1_1 and i_t_rec1_2 = c_st_rec1_1 ; correct := correct and i_st_rec1_1 = c_st_rec1_1 and i_st_rec1_2 = c_st_rec1_1 ; correct := correct and i_t_rec2_1 = c_st_rec2_1 and i_t_rec2_2 = c_st_rec2_1 ; correct := correct and i_st_rec2_1 = c_st_rec2_1 and i_st_rec2_2 = c_st_rec2_1 ; correct := correct and i_t_rec3_1 = c_st_rec3_1 and i_t_rec3_2 = c_st_rec3_1 ; correct := correct and i_st_rec3_1 = c_st_rec3_1 and i_st_rec3_2 = c_st_rec3_1 ; correct := correct and i_t_arr1_1 = c_st_arr1_1 and i_t_arr1_2 = c_st_arr1_1 ; correct := correct and i_st_arr1_1 = c_st_arr1_1 and i_st_arr1_2 = c_st_arr1_1 ; correct := correct and i_t_arr2_1 = c_st_arr2_1 and i_t_arr2_2 = c_st_arr2_1 ; correct := correct and i_st_arr2_1 = c_st_arr2_1 and i_st_arr2_2 = c_st_arr2_1 ; correct := correct and i_t_arr3_1 = c_st_arr3_1 and i_t_arr3_2 = c_st_arr3_1 ; correct := correct and i_st_arr3_1 = c_st_arr3_1 and i_st_arr3_2 = c_st_arr3_1 ; -- test_report ( "ENT00025" , "Associated composite in ports with static subtypes" , correct) ; wait ; end process ; end ARCH00025 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00025_Test_Bench is end ENT00025_Test_Bench ; -- architecture ARCH00025_Test_Bench of ENT00025_Test_Bench is begin L1: block signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector := c_st_bit_vector_1 ; signal i_string_1, i_string_2 : st_string := c_st_string_1 ; signal i_t_rec1_1, i_t_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_t_rec2_1, i_t_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_t_rec3_1, i_t_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_t_arr1_1, i_t_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_t_arr2_1, i_t_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_t_arr3_1, i_t_arr3_2 : st_arr3 := c_st_arr3_1 ; signal i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- component UUT port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00025 ( ARCH00025 ) ; -- begin CIS1 : UUT port map ( i_bit_vector_1, i_bit_vector_2, i_string_1, i_string_2, i_t_rec1_1, i_t_rec1_2, i_st_rec1_1, i_st_rec1_2, i_t_rec2_1, i_t_rec2_2, i_st_rec2_1, i_st_rec2_2, i_t_rec3_1, i_t_rec3_2, i_st_rec3_1, i_st_rec3_2, i_t_arr1_1, i_t_arr1_2, i_st_arr1_1, i_st_arr1_2, i_t_arr2_1, i_t_arr2_2, i_st_arr2_1, i_st_arr2_2, i_t_arr3_1, i_t_arr3_2, i_st_arr3_1, i_st_arr3_2 ) ; end block L1 ; end ARCH00025_Test_Bench ;	gpl-3.0	4e9dc50f41cbbbc3b11bb394eac75486	0.415908	2.749728	false	false	false	false
grwlf/vsim	vhdl_ct/ct00529.vhd	1	3,403	-- NEED RESULT: ARCH00529: Actual parameter list absent in function calls passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00529 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.3 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00529) -- ENT00529_Test_Bench(ARCH00529_Test_Bench) -- -- REVISION HISTORY: -- -- 17-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00529 of E00000 is type arr_1 is array ( boolean range <> , integer range <> ) of bit ; type arr_2 is array ( integer range <> ) of integer ; type rec_1 is record f1 : boolean ; f2 : integer ; end record ; subtype st_arr_1 is arr_1 ( true downto false , 1 to 4 ) ; subtype st_arr_2 is arr_2 ( -2 to 3 ) ; begin process variable correct : boolean := true ; function f1 return boolean is begin return false ; end f1 ; function f2 return integer is begin return 3 ; end f2 ; function f3 return arr_1 is variable v_st_arr_1 : st_arr_1 ; begin v_st_arr_1(false, 1) := '1' ; v_st_arr_1(false, 2) := '0' ; v_st_arr_1(false, 3) := '1' ; v_st_arr_1(false, 4) := '0' ; v_st_arr_1(true, 1) := '0' ; v_st_arr_1(true, 2) := '1' ; v_st_arr_1(true, 3) := '0' ; v_st_arr_1(true, 4) := '1' ; return v_st_arr_1 ; end f3 ; function f4 return st_arr_1 is begin return ( ( '1' , '0', '1', '0' ), ( '0' , '1', '0', '1' ) ) ; end f4 ; function f5 return st_arr_2 is begin return (-2, -1, 0, 1, 2, 3) ; end f5 ; function f6 return rec_1 is begin return (false, 3) ; end f6 ; begin correct := correct and f3(false, 1) = '1' and f3(false, 2) = '0' and f3(false, 3) = '1' and f3(false, 4) = '0' and f3(true, 1) = '0' and f3(true, 2) = '1' and f3(true, 3) = '0' and f3(true, 4) = '1' ; correct := correct and f4(true, 1) = '1' and f4(true, 2) = '0' and f4(true, 3) = '1' and f4(true, 4) = '0' and f4(false, 1) = '0' and f4(false, 2) = '1' and f4(false, 3) = '0' and f4(false, 4) = '1' ; correct := correct and f5(-2 to 3) = (-2, -1, 0, 1, 2, 3) ; correct := correct and f6.f1 = false and f6.f2 = 3 ; test_report ( "ARCH00529" , "Actual parameter list absent in function calls" , correct and f1 = false and f2 = 3 ) ; wait ; end process ; end ARCH00529 ; -- entity ENT00529_Test_Bench is end ENT00529_Test_Bench ; architecture ARCH00529_Test_Bench of ENT00529_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00529 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00529_Test_Bench ; --	gpl-3.0	89e23f6af5b727a17331748ac4503594	0.458419	3.06853	false	true	false	false
MilosSubotic/huffman_coding	RTL/src/rtl/quasi_tree.vhd	1	3,423	------------------------------------------------------------------------------ -- @license MIT -- @brief Building quasi-tree. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.global.all; entity quasi_tree is port( i_clk : in std_logic; in_rst : in std_logic; i_stage : in t_stage; i_pipe_en : in std_logic; i_sort_sym : in t_sym_array(0 to 15); i_sort_cnt : in t_cnt_array(0 to 15); o_child0 : out t_node_and_cnt; o_child1 : out t_node_and_cnt; o_new_parent : out t_node_and_cnt ); end entity quasi_tree; architecture arch_quasi_tree_v1 of quasi_tree is signal leaves : t_node_and_cnt_array(0 to 15); signal parents : t_node_and_cnt_array(0 to 15); signal parents_end : std_logic_vector(3 downto 0); signal new_parent_node : t_node; signal child0 : t_node_and_cnt; signal child1 : t_node_and_cnt; signal new_parent : t_node_and_cnt; signal next_leaves : t_node_and_cnt_array(0 to 15); signal next_parents : t_node_and_cnt_array(0 to 15); signal leaves_shift : std_logic_vector(1 downto 0); signal parents_shift : std_logic_vector(1 downto 0); signal leaves_shifter : t_node_and_cnt_array(0 to 15); signal parents_shifter : t_node_and_cnt_array(0 to 15); signal push_new_parent : std_logic; signal cmp0 : std_logic; signal cmp1 : std_logic; signal cmp2 : std_logic; begin process(i_clk, in_rst) begin if in_rst = '0' then leaves_node <= (others => ("11111", "11111")); parents_node <= (others => ("11111", "11111")); elsif rising_edge(i_clk) then leaves <= next_leaves; parents <= next_parents; end if; end process; next_leaves <= i_sort_sym when stage_i = 16 else leaves_shifter; ls: for i in 0 to 13 generate with leaves_shift select leaves_shifter(i) <= leaves(i) when "00", leaves(i+1) when "01", leaves(i+2) when others; end generate; with leaves_shift select leaves_shifter(14) <= leaves(14) when "00", leaves(15) when "01", ("11111", "11111") when others; with leaves_shift select leaves_shifter(15) <= leaves(15) when "00", ("11111", "11111") when "01", ("11111", "11111") when others; next_parents <= (others => "11111") when stage_i = 16 else parents_pusher; pp: for i in 0 to 15 generate parents_pusher(i) <= new_parent when parents_end = i and push_new_parent = '1' else parents_shifter; end generate; ps: for i in 0 to 13 generate with parents_shift select parents_shifter(i) <= parents(i) when "00", parents(i+1) when "01", parents(i+2) when others; end generate; with parents_shift select parents_shifter(14) <= parents(14) when "00", parents(15) when "01", ("11111", "11111") when others; with parents_shift select parents_shifter(15) <= parents(15) when "00", ("11111", "11111") when "01", ("11111", "11111") when others; cmp0 <= '1' when leaves(0).cnt < parents(0).cnt else '1'; cmp1 <= '1' when leaves(1).cnt < parents(0).cnt else '1'; cmp2 <= '1' when parents(1).cnt < leaves(0).cnt else '1'; end architecture arch_quasi_tree_v1;	mit	eb91b44d70eac823523ccb445a415be0	0.577564	2.908241	false	false	false	false
TWW12/lzw	ip_repo/axi_compression_1.0/src/dictionary_block_2.vhd	4	5,040	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity dictionary_block_2 is generic( block_num : integer := 0); port ( clk : in std_logic; rst : in std_logic; start_search : in std_logic; search_entry : in std_logic_vector(19 downto 0); halt_search : in std_logic; --Write enable & entries wr_en : in std_logic; wr_addr : in std_logic_vector(10 downto 0); wr_entry : in std_logic_vector(19 downto 0); --Outputs prefix : out std_logic_vector(10 downto 0); entry_found : out std_logic; search_completed : out std_logic); end dictionary_block_2; architecture Behavioral of dictionary_block_2 is component bram_2048_0 is PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); end component; component bram_2048_1 is PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); end component; type state_type is (S_RST,S_GO,S_WAIT,S_SEARCH); signal state : state_type; signal rd_addr : std_logic_vector(11 downto 0); signal addr : std_logic_vector(10 downto 0); signal bram_out : std_logic_vector(19 downto 0); signal full : std_logic; signal rd_addr_delay : std_logic_vector(11 downto 0); signal wr_entry_delay : std_logic_vector(19 downto 0); begin GEN_BLOCK_0: if block_num = 0 generate U_BRAM : bram_2048_0 port map( clka => clk, ena => '1', wea(0) => wr_en, addra => addr, dina => wr_entry_delay, douta => bram_out); end generate GEN_BLOCK_0; GEN_BLOCK_1 : if block_num = 1 generate U_BRAM : bram_2048_1 port map( clka => clk, ena => '1', wea(0) => wr_en, addra => addr, dina => wr_entry_delay, douta => bram_out); end generate GEN_BLOCK_1; with wr_en select addr <= wr_addr when '1', rd_addr(10 downto 0) when others; process(clk,rst) begin if rst = '1' then state <= S_RST; rd_addr <= (rd_addr'range => '0'); entry_found <= '0'; search_completed <= '0'; prefix <= (prefix'range => '0'); wr_entry_delay <= (wr_entry_delay'range => '0'); rd_addr_delay <= (rd_addr_delay'range => '0'); elsif rising_edge(clk) then rd_addr_delay <= rd_addr; wr_entry_delay <= wr_entry; case state is when S_RST => state <= S_GO; --idle until its time to search when S_GO => rd_addr <= (rd_addr'range => '0'); entry_found <= '0'; search_completed <= '0'; prefix <= (prefix'range => '0'); if start_search = '1' then state <= S_WAIT; end if; when S_WAIT => state <= S_SEARCH; when S_SEARCH => rd_addr <= std_logic_vector(unsigned(rd_addr)+to_unsigned(1,12)); --Did we find the entry? if search_entry = bram_out then state <= S_GO; entry_found <= '1'; search_completed <= '1'; prefix <= rd_addr_delay(10 downto 0);--std_logic_vector(unsigned(rd_addr(10 downto 0))-to_unsigned(1,11)); rd_addr <= (others => '0'); end if; --Did we go through the whole dictionary? if start_search = '1' then state <= S_SEARCH; rd_addr <= (others => '0'); elsif halt_search = '1' then state <= S_GO; rd_addr <= (others => '0'); elsif rd_addr = std_logic_vector(unsigned(wr_addr)+to_unsigned(3,12)) then state <= S_GO; rd_addr <= (others => '0'); search_completed <= '1'; end if; end case; end if; end process; end Behavioral;	unlicense	c28bbd5306de6b0a77eeedfc4ffade14	0.44504	4.094232	false	false	false	false
TWW12/lzw	ip_repo/axi_compression_1.0/src/clock_counter.vhd	3	1,794	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clock_counter is Port ( enable : in STD_LOGIC; count : out STD_LOGIC_VECTOR (31 downto 0); done : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC); end clock_counter; architecture Behavioral of clock_counter is type state_type is (RESET,COUNT_CLOCK,COUNT_DONE); signal state : state_type; signal temp_count : std_logic_vector (31 downto 0); begin count <= temp_count; process(clk,rst) begin if rst = '1' then state <= RESET; temp_count <= (temp_count'range => '0'); elsif rising_edge(clk) then case state is when RESET => state <= RESET; if enable = '1' then state <= COUNT_CLOCK; end if; when COUNT_CLOCK => if done = '1' then temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32)); state <= COUNT_DONE; elsif done ='0' then temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32)); state <= COUNT_CLOCK; else temp_count <= temp_count; state <= COUNT_CLOCK; end if; when COUNT_DONE => temp_count <= temp_count; state <= COUNT_DONE; end case; end if; end process; end Behavioral;	unlicense	d4bc33b0a0d6a27b0361df11ea1d4519	0.432553	4.83558	false	false	false	false
jairov4/accel-oil	solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if_async_fifo.vhd	1	5,831	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_initials_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_initials_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;	lgpl-3.0	cd81fa65ca3a197638e589ce0906c032	0.55445	3.405958	false	false	false	false
grwlf/vsim	vhdl_ct/ct00314.vhd	1	5,437	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00314 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (1) -- 7.2.3 (2) -- 7.2.3 (8) -- 7.2.3 (9) -- 7.2.3 (10) -- -- DESIGN UNIT ORDERING: -- -- ENT00314(ARCH00314) -- ENT00314_Test_Bench(ARCH00314_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES ; use WORK.ARITHMETIC.ALL ; entity ENT00314 is generic ( i_int_1 : integer := c_int_1 ; i_int_2 : integer := c_int_2 ; i_t_int_1 : t_int := c_t_int_1 ; i_t_int_2 : t_int := c_t_int_2 ; i_st_int_1 : st_int := c_st_int_1 ; i_st_int_2 : st_int := c_st_int_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00314 ; architecture ARCH00314 of ENT00314 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; -- variable v_int_1, v2_int_1 : integer := c_int_1 ; variable v_int_2, v2_int_2 : integer := c_int_2 ; variable v_t_int_1, v2_t_int_1 : t_int := c_t_int_1 ; variable v_t_int_2, v2_t_int_2 : t_int := c_t_int_2 ; variable v_st_int_1, v2_st_int_1 : st_int := c_st_int_1 ; variable v_st_int_2, v2_st_int_2 : st_int := c_st_int_2 ; -- constant c2_int_1 : integer := (((+i_int_1) + (-i_int_2)) + ((-i_int_1) + (-i_int_2))) - (((+i_int_1) - (-c_int_2)) - ((-c_int_2) - (-i_int_1))) - 28 ; constant c2_t_int_1 : t_int := (((+i_t_int_1) + (-i_t_int_2)) + ((-i_t_int_1) + (-i_t_int_2))) - (((+i_t_int_1) - (-c_t_int_2)) - ((-c_t_int_2) - (-i_t_int_1))) - 5 ; constant c2_st_int_1 : st_int := -(((+i_st_int_1) + (-i_t_int_2)) + ((-i_st_int_1) + (-i_st_int_2))) - (((+i_st_int_1) - (-c_st_int_2)) - ((-c_t_int_2) - (-i_st_int_1))) - 5 ; begin -- -- static expression -- case bool is when ( (((+c_int_1) + (-c_int_2)) + ((-c_int_1) + (-c_int_2))) - (((+c_int_1) - (-c_int_2)) - ((-c_int_2) - (-c_int_1))) - 28 = ans_int1 and (((+c_t_int_1) + (-c_t_int_2)) + ((-c_t_int_1) + (-c_t_int_2))) - (((+c_t_int_1) - (-c_t_int_2)) - ((-c_t_int_2) - (-c_t_int_1))) - 5 = ans_int2 and -(((+c_st_int_1) + (-c_t_int_2)) + ((-c_st_int_1) + (-c_st_int_2))) - (((+c_st_int_1) - (-c_st_int_2)) - ((-c_t_int_2) - (-c_st_int_1))) - 5 = ans_int3 ) => null ; when others => cons_correct := false ; end case ; -- -- generic expression -- gen_correct := c2_int_1 = ans_int1 and c2_t_int_1 = ans_int2 and c2_st_int_1= ans_int3 ; -- -- dynamic expression -- v_int_1 := (((+v2_int_1) + (-v2_int_2)) + ((-v2_int_1) + (-v2_int_2))) - (((+v2_int_1) - (-c_int_2)) - ((-c_int_2) - (-v2_int_1))) - 28 ; v_t_int_1 := (((+v2_t_int_1) + (-v2_t_int_2)) + ((-v2_t_int_1) + (-v2_t_int_2))) - (((+v2_t_int_1) - (-i_t_int_2)) - ((-c_t_int_2) - (-v2_t_int_1))) - 5 ; v_st_int_1 := -(((+v2_st_int_1) + (-v2_t_int_2)) + ((-v2_st_int_1) + (-v2_st_int_2))) - (((+v2_st_int_1) - (-c_st_int_2)) - ((-i_t_int_2) - (-v2_st_int_1))) - 5 ; dyn_correct := true ; dyn_correct := v_int_1 = ans_int1 and v_t_int_1 = ans_int2 and v_st_int_1 = ans_int3 ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait ; end process ; end ARCH00314 ; use WORK.STANDARD_TYPES.all ; entity ENT00314_Test_Bench is end ENT00314_Test_Bench ; architecture ARCH00314_Test_Bench of ENT00314_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end component ; for CIS1 : UUT use entity WORK.ENT00314 ( ARCH00314 ) ; begin CIS1 : UUT port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then WORK.STANDARD_TYPES.test_report ( "ARCH00314" , "+ and - unary and binary operators are correctly" & " predefined for integer types" , true ) ; end if ; end process ; end block L1 ; end ARCH00314_Test_Bench ;	gpl-3.0	21c8d273569c6167f49da55a964194df	0.448225	2.833246	false	true	false	false
jairov4/accel-oil	solution_spartan6/impl/vhdl/p_bsf32_hw.vhd	4	81,430	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity p_bsf32_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end; architecture behav of p_bsf32_hw is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001"; constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010"; constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011"; constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100"; constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101"; constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110"; constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111"; constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000"; constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001"; constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010"; constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011"; constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100"; constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101"; constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110"; constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111"; constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000"; constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001"; constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010"; constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011"; constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100"; constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101"; constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110"; constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111"; constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000"; constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001"; constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010"; constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011"; constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100"; constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101"; constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110"; constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_true : BOOLEAN := true; signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_reg_526 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_530 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_3_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_3_reg_534 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_reg_538 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_reg_542 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_6_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_6_reg_546 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_7_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_7_reg_550 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_reg_554 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_558 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_reg_562 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_566 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_reg_570 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_13_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_13_reg_574 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_14_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_14_reg_578 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_15_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_15_reg_582 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_reg_586 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_reg_590 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_reg_594 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_reg_598 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_20_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_20_reg_602 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_21_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_21_reg_606 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_22_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_22_reg_610 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_reg_614 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_reg_618 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_reg_622 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_reg_626 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_27_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_27_reg_630 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_reg_634 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_reg_638 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_30_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_30_reg_642 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0); signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0); signal ap_sig_bdd_764 : BOOLEAN; signal ap_sig_bdd_178 : BOOLEAN; signal ap_sig_bdd_183 : BOOLEAN; signal ap_sig_bdd_189 : BOOLEAN; signal ap_sig_bdd_196 : BOOLEAN; signal ap_sig_bdd_204 : BOOLEAN; signal ap_sig_bdd_213 : BOOLEAN; signal ap_sig_bdd_223 : BOOLEAN; signal ap_sig_bdd_234 : BOOLEAN; signal ap_sig_bdd_246 : BOOLEAN; signal ap_sig_bdd_259 : BOOLEAN; signal ap_sig_bdd_273 : BOOLEAN; signal ap_sig_bdd_288 : BOOLEAN; signal ap_sig_bdd_304 : BOOLEAN; signal ap_sig_bdd_321 : BOOLEAN; signal ap_sig_bdd_339 : BOOLEAN; signal ap_sig_bdd_358 : BOOLEAN; signal ap_sig_bdd_378 : BOOLEAN; signal ap_sig_bdd_399 : BOOLEAN; signal ap_sig_bdd_421 : BOOLEAN; signal ap_sig_bdd_444 : BOOLEAN; signal ap_sig_bdd_468 : BOOLEAN; signal ap_sig_bdd_493 : BOOLEAN; signal ap_sig_bdd_519 : BOOLEAN; signal ap_sig_bdd_546 : BOOLEAN; signal ap_sig_bdd_574 : BOOLEAN; signal ap_sig_bdd_603 : BOOLEAN; signal ap_sig_bdd_633 : BOOLEAN; signal ap_sig_bdd_664 : BOOLEAN; signal ap_sig_bdd_696 : BOOLEAN; signal ap_sig_bdd_730 : BOOLEAN; begin -- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. -- ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_764) then ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1'; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1); ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2); ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3); ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4); end if; end if; end if; end process; -- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. -- ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_730) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E; elsif (ap_sig_bdd_696) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D; elsif (ap_sig_bdd_664) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C; elsif (ap_sig_bdd_633) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B; elsif (ap_sig_bdd_603) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A; elsif (ap_sig_bdd_574) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19; elsif (ap_sig_bdd_546) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18; elsif (ap_sig_bdd_519) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17; elsif (ap_sig_bdd_493) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16; elsif (ap_sig_bdd_468) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15; elsif (ap_sig_bdd_444) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14; elsif (ap_sig_bdd_421) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13; elsif (ap_sig_bdd_399) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12; elsif (ap_sig_bdd_378) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11; elsif (ap_sig_bdd_358) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10; elsif (ap_sig_bdd_339) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F; elsif (ap_sig_bdd_321) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E; elsif (ap_sig_bdd_304) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D; elsif (ap_sig_bdd_288) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C; elsif (ap_sig_bdd_273) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B; elsif (ap_sig_bdd_259) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A; elsif (ap_sig_bdd_246) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9; elsif (ap_sig_bdd_234) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8; elsif (ap_sig_bdd_223) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7; elsif (ap_sig_bdd_213) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6; elsif (ap_sig_bdd_204) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5; elsif (ap_sig_bdd_196) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4; elsif (ap_sig_bdd_189) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3; elsif (ap_sig_bdd_183) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2; elsif (ap_sig_bdd_178) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1; elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3))) then tmp_10_reg_562 <= bus_r(10 downto 10); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3))) then tmp_11_reg_566 <= bus_r(11 downto 11); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3))) then tmp_12_reg_570 <= bus_r(12 downto 12); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3))) then tmp_13_reg_574 <= bus_r(13 downto 13); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3))) then tmp_14_reg_578 <= bus_r(14 downto 14); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3))) then tmp_15_reg_582 <= bus_r(15 downto 15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3))) then tmp_16_reg_586 <= bus_r(16 downto 16); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3))) then tmp_17_reg_590 <= bus_r(17 downto 17); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3))) then tmp_18_reg_594 <= bus_r(18 downto 18); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3))) then tmp_19_reg_598 <= bus_r(19 downto 19); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then tmp_1_reg_526 <= bus_r(1 downto 1); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3))) then tmp_20_reg_602 <= bus_r(20 downto 20); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3))) then tmp_21_reg_606 <= bus_r(21 downto 21); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3))) then tmp_22_reg_610 <= bus_r(22 downto 22); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3))) then tmp_23_reg_614 <= bus_r(23 downto 23); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3))) then tmp_24_reg_618 <= bus_r(24 downto 24); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3))) then tmp_25_reg_622 <= bus_r(25 downto 25); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3))) then tmp_26_reg_626 <= bus_r(26 downto 26); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3))) then tmp_27_reg_630 <= bus_r(27 downto 27); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3))) then tmp_28_reg_634 <= bus_r(28 downto 28); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3))) then tmp_29_reg_638 <= bus_r(29 downto 29); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0))) then tmp_2_reg_530 <= bus_r(2 downto 2); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3))) then tmp_30_reg_642 <= bus_r(30 downto 30); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3))) then tmp_3_reg_534 <= bus_r(3 downto 3); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3))) then tmp_4_reg_538 <= bus_r(4 downto 4); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3))) then tmp_5_reg_542 <= bus_r(5 downto 5); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3))) then tmp_6_reg_546 <= bus_r(6 downto 6); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3))) then tmp_7_reg_550 <= bus_r(7 downto 7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3))) then tmp_8_reg_554 <= bus_r(8 downto 8); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3))) then tmp_9_reg_558 <= bus_r(9 downto 9); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then tmp_reg_522 <= tmp_fu_278_p1; end if; end if; end process; ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1; ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1; ap_return <= merge_phi_fu_269_p4; -- ap_sig_bdd_178 assign process. -- ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3) begin ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_1_fu_282_p3 = ap_const_lv1_0))); end process; -- ap_sig_bdd_183 assign process. -- ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3) begin ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_290_p3))); end process; -- ap_sig_bdd_189 assign process. -- ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3) begin ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and not((ap_const_lv1_0 = tmp_3_fu_298_p3))); end process; -- ap_sig_bdd_196 assign process. -- ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3) begin ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and not((ap_const_lv1_0 = tmp_4_fu_306_p3))); end process; -- ap_sig_bdd_204 assign process. -- ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3) begin ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and not((ap_const_lv1_0 = tmp_5_fu_314_p3))); end process; -- ap_sig_bdd_213 assign process. -- ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3) begin ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and not((ap_const_lv1_0 = tmp_6_fu_322_p3))); end process; -- ap_sig_bdd_223 assign process. -- ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3) begin ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and not((ap_const_lv1_0 = tmp_7_fu_330_p3))); end process; -- ap_sig_bdd_234 assign process. -- ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3) begin ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and not((ap_const_lv1_0 = tmp_8_fu_338_p3))); end process; -- ap_sig_bdd_246 assign process. -- ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3) begin ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and not((ap_const_lv1_0 = tmp_9_fu_346_p3))); end process; -- ap_sig_bdd_259 assign process. -- ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3) begin ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and not((ap_const_lv1_0 = tmp_10_fu_354_p3))); end process; -- ap_sig_bdd_273 assign process. -- ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3) begin ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and not((ap_const_lv1_0 = tmp_11_fu_362_p3))); end process; -- ap_sig_bdd_288 assign process. -- ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3) begin ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and not((ap_const_lv1_0 = tmp_12_fu_370_p3))); end process; -- ap_sig_bdd_304 assign process. -- ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3) begin ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and not((ap_const_lv1_0 = tmp_13_fu_378_p3))); end process; -- ap_sig_bdd_321 assign process. -- ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3) begin ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and not((ap_const_lv1_0 = tmp_14_fu_386_p3))); end process; -- ap_sig_bdd_339 assign process. -- ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3) begin ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and not((ap_const_lv1_0 = tmp_15_fu_394_p3))); end process; -- ap_sig_bdd_358 assign process. -- ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3) begin ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and not((ap_const_lv1_0 = tmp_16_fu_402_p3))); end process; -- ap_sig_bdd_378 assign process. -- ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3) begin ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and not((ap_const_lv1_0 = tmp_17_fu_410_p3))); end process; -- ap_sig_bdd_399 assign process. -- ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3) begin ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and not((ap_const_lv1_0 = tmp_18_fu_418_p3))); end process; -- ap_sig_bdd_421 assign process. -- ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3) begin ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and not((ap_const_lv1_0 = tmp_19_fu_426_p3))); end process; -- ap_sig_bdd_444 assign process. -- ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3) begin ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and not((ap_const_lv1_0 = tmp_20_fu_434_p3))); end process; -- ap_sig_bdd_468 assign process. -- ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3) begin ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and not((ap_const_lv1_0 = tmp_21_fu_442_p3))); end process; -- ap_sig_bdd_493 assign process. -- ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3) begin ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and not((ap_const_lv1_0 = tmp_22_fu_450_p3))); end process; -- ap_sig_bdd_519 assign process. -- ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3) begin ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and not((ap_const_lv1_0 = tmp_23_fu_458_p3))); end process; -- ap_sig_bdd_546 assign process. -- ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3) begin ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and not((ap_const_lv1_0 = tmp_24_fu_466_p3))); end process; -- ap_sig_bdd_574 assign process. -- ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3) begin ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and not((ap_const_lv1_0 = tmp_25_fu_474_p3))); end process; -- ap_sig_bdd_603 assign process. -- ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3) begin ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and not((ap_const_lv1_0 = tmp_26_fu_482_p3))); end process; -- ap_sig_bdd_633 assign process. -- ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3) begin ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and not((ap_const_lv1_0 = tmp_27_fu_490_p3))); end process; -- ap_sig_bdd_664 assign process. -- ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3) begin ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and not((ap_const_lv1_0 = tmp_28_fu_498_p3))); end process; -- ap_sig_bdd_696 assign process. -- ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3) begin ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and not((ap_const_lv1_0 = tmp_29_fu_506_p3))); end process; -- ap_sig_bdd_730 assign process. -- ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3, tmp_30_fu_514_p3) begin ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3) and not((ap_const_lv1_0 = tmp_30_fu_514_p3))); end process; -- ap_sig_bdd_764 assign process. -- ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3, tmp_30_fu_514_p3) begin ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3) and (ap_const_lv1_0 = tmp_30_fu_514_p3)); end process; -- merge_phi_fu_269_p4 assign process. -- merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_1_reg_526, tmp_2_reg_530, tmp_3_reg_534, tmp_4_reg_538, tmp_5_reg_542, tmp_6_reg_546, tmp_7_reg_550, tmp_8_reg_554, tmp_9_reg_558, tmp_10_reg_562, tmp_11_reg_566, tmp_12_reg_570, tmp_13_reg_574, tmp_14_reg_578, tmp_15_reg_582, tmp_16_reg_586, tmp_17_reg_590, tmp_18_reg_594, tmp_19_reg_598, tmp_20_reg_602, tmp_21_reg_606, tmp_22_reg_610, tmp_23_reg_614, tmp_24_reg_618, tmp_25_reg_622, tmp_26_reg_626, tmp_27_reg_630, tmp_28_reg_634, tmp_29_reg_638, tmp_30_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1) begin if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_1_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_2_reg_530)) or not((ap_const_lv1_0 = tmp_3_reg_534)) or not((ap_const_lv1_0 = tmp_4_reg_538)) or not((ap_const_lv1_0 = tmp_5_reg_542)) or not((ap_const_lv1_0 = tmp_6_reg_546)) or not((ap_const_lv1_0 = tmp_7_reg_550)) or not((ap_const_lv1_0 = tmp_8_reg_554)) or not((ap_const_lv1_0 = tmp_9_reg_558)) or not((ap_const_lv1_0 = tmp_10_reg_562)) or not((ap_const_lv1_0 = tmp_11_reg_566)) or not((ap_const_lv1_0 = tmp_12_reg_570)) or not((ap_const_lv1_0 = tmp_13_reg_574)) or not((ap_const_lv1_0 = tmp_14_reg_578)) or not((ap_const_lv1_0 = tmp_15_reg_582)) or not((ap_const_lv1_0 = tmp_16_reg_586)) or not((ap_const_lv1_0 = tmp_17_reg_590)) or not((ap_const_lv1_0 = tmp_18_reg_594)) or not((ap_const_lv1_0 = tmp_19_reg_598)) or not((ap_const_lv1_0 = tmp_20_reg_602)) or not((ap_const_lv1_0 = tmp_21_reg_606)) or not((ap_const_lv1_0 = tmp_22_reg_610)) or not((ap_const_lv1_0 = tmp_23_reg_614)) or not((ap_const_lv1_0 = tmp_24_reg_618)) or not((ap_const_lv1_0 = tmp_25_reg_622)) or not((ap_const_lv1_0 = tmp_26_reg_626)) or not((ap_const_lv1_0 = tmp_27_reg_630)) or not((ap_const_lv1_0 = tmp_28_reg_634)) or not((ap_const_lv1_0 = tmp_29_reg_638)) or not((ap_const_lv1_0 = tmp_30_reg_642)))) then merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1; else merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1; end if; end process; tmp_10_fu_354_p3 <= bus_r(10 downto 10); tmp_11_fu_362_p3 <= bus_r(11 downto 11); tmp_12_fu_370_p3 <= bus_r(12 downto 12); tmp_13_fu_378_p3 <= bus_r(13 downto 13); tmp_14_fu_386_p3 <= bus_r(14 downto 14); tmp_15_fu_394_p3 <= bus_r(15 downto 15); tmp_16_fu_402_p3 <= bus_r(16 downto 16); tmp_17_fu_410_p3 <= bus_r(17 downto 17); tmp_18_fu_418_p3 <= bus_r(18 downto 18); tmp_19_fu_426_p3 <= bus_r(19 downto 19); tmp_1_fu_282_p3 <= bus_r(1 downto 1); tmp_20_fu_434_p3 <= bus_r(20 downto 20); tmp_21_fu_442_p3 <= bus_r(21 downto 21); tmp_22_fu_450_p3 <= bus_r(22 downto 22); tmp_23_fu_458_p3 <= bus_r(23 downto 23); tmp_24_fu_466_p3 <= bus_r(24 downto 24); tmp_25_fu_474_p3 <= bus_r(25 downto 25); tmp_26_fu_482_p3 <= bus_r(26 downto 26); tmp_27_fu_490_p3 <= bus_r(27 downto 27); tmp_28_fu_498_p3 <= bus_r(28 downto 28); tmp_29_fu_506_p3 <= bus_r(29 downto 29); tmp_2_fu_290_p3 <= bus_r(2 downto 2); tmp_30_fu_514_p3 <= bus_r(30 downto 30); tmp_3_fu_298_p3 <= bus_r(3 downto 3); tmp_4_fu_306_p3 <= bus_r(4 downto 4); tmp_5_fu_314_p3 <= bus_r(5 downto 5); tmp_6_fu_322_p3 <= bus_r(6 downto 6); tmp_7_fu_330_p3 <= bus_r(7 downto 7); tmp_8_fu_338_p3 <= bus_r(8 downto 8); tmp_9_fu_346_p3 <= bus_r(9 downto 9); tmp_fu_278_p1 <= bus_r(1 - 1 downto 0); end behav;	lgpl-3.0	b7a94bb746a66b7320ccdffc3742a15f	0.614552	2.114955	false	false	false	false
jairov4/accel-oil	solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_initials_buckets_if_ap_fifo.vhd	2	2,845	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_initials_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC := '1'; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC := '1'; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of nfa_initials_buckets_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;	lgpl-3.0	ee2d019d8eb19371b2fac493691e3160	0.495958	3.642766	false	false	false	false
grwlf/vsim	vhdl_ct/ct00631.vhd	1	3,742	-- NEED RESULT: ARCH00631: Index constraints passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00631 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 3.2.1.1 (4) -- 3.2.1.1 (5) -- 3.2.1.1 (6) -- 3.2.1.1 (7) -- 3.2.1.1 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00631) -- ENT00631_Test_Bench(ARCH00631_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- 18-JAN-1987 - removed refs to predefined attributes on func calls -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES; use STANDARD_TYPES.all ; architecture ARCH00631 of E00000 is begin P : process constant c : STANDARD_TYPES.t_arr1 := c_st_arr1_1 ; variable v : integer ; attribute a : STANDARD_TYPES.t_arr1 ; attribute a of v : variable is c_st_arr1_1 ; type array_access is access STANDARD_TYPES.t_arr1 ; variable ptr : array_access ; variable low1, high1, left1, right1, low2, high2, left2, right2 : integer := 9999 ; variable st : STANDARD_TYPES.st_arr1 := c_st_arr1_1 ; subtype t_100 is STANDARD_TYPES.t_arr1 (100+st_arr1'left to 100+st_arr1'right) ; variable t : t_100 := c_st_arr1_1 ; procedure proc_with_unconstrained_array ( a : in STANDARD_TYPES.t_arr1 ; lo,hi,lft,rght : out integer ) is begin lo := a'low ; hi := a'high ; lft := a'left ; rght := a'right ; end proc_with_unconstrained_array ; procedure proc_with_constrained_array ( a : in STANDARD_TYPES.st_arr1 ; lo,hi,lft,rght : out integer ) is begin lo := a'low ; hi := a'high ; lft := a'left ; rght := a'right ; end proc_with_constrained_array ; begin proc_with_unconstrained_array ( st, low1, high1, left1, right1 ) ; proc_with_constrained_array ( t, low2, high2, left2, right2 ) ; ptr := new t_arr1(1 to 10) ; test_report ( "ARCH00631" , "Index constraints" , (c'low = st_arr1'low) and -- these test 3.2.1.1 (4) (c'high = st_arr1'high) and (c'left = st_arr1'left) and (c'right = st_arr1'right) and -- (v'a'low = st_arr1'low) and -- these test 3.2.1.1 (5) -- (v'a'high = st_arr1'high) and -- (v'a'left = st_arr1'left) and -- (v'a'right = st_arr1'right) and (ptr.all'low = 1) and -- these test 3.2.1.1 (6) (ptr.all'high = 10) and (ptr.all'left = 1) and (ptr.all'right = 10) and (low1 = st_arr1'low) and -- these test 3.2.1.1 (8) (high1 = st_arr1'high) and (left1 = st_arr1'left) and (right1 = st_arr1'right) and (low2 = st_arr1'low) and -- these test 3.2.1.1 (7) (high2 = st_arr1'high) and (left2 = st_arr1'left) and (right2 = st_arr1'right) ) ; wait ; end process P ; end ARCH00631 ; -- entity ENT00631_Test_Bench is end ENT00631_Test_Bench ; architecture ARCH00631_Test_Bench of ENT00631_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00631 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00631_Test_Bench ; --	gpl-3.0	d9992477999a174278e253c8f3770245	0.495991	3.069729	false	true	false	false
TWW12/lzw	ip_repo/axi_compression_1.0/src/bram_1024_2/synth/bram_1024_2.vhd	4	14,457	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY bram_1024_2 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END bram_1024_2; ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" & "f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" & "PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" & "_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "bram_1024_2.mif", C_INIT_FILE => "bram_1024_2.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 20, C_READ_WIDTH_A => 20, C_WRITE_DEPTH_A => 1024, C_READ_DEPTH_A => 1024, C_ADDRA_WIDTH => 10, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 20, C_READ_WIDTH_B => 20, C_WRITE_DEPTH_B => 1024, C_READ_DEPTH_B => 1024, C_ADDRB_WIDTH => 10, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "1", C_COUNT_18K_BRAM => "0", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END bram_1024_2_arch;	unlicense	e0716f4d3170d600acd22fd66e4a2ce2	0.625372	3.002492	false	false	false	false
grwlf/vsim	vhdl_ct/ct00034.vhd	1	27,414	-- NEED RESULT: ARCH00034.P1: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P2: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P3: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P4: Target of a variable assignment may be a slice passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00034 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00034) -- ENT00034_Test_Bench(ARCH00034_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00034 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P1" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00034.P2" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P3" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_boolean_vector : inout st_boolean_vector ; v_st_bit_vector : inout st_bit_vector ; v_st_severity_level_vector : inout st_severity_level_vector ; v_st_string : inout st_string ; v_st_enum1_vector : inout st_enum1_vector ; v_st_integer_vector : inout st_integer_vector ; v_st_int1_vector : inout st_int1_vector ; v_st_time_vector : inout st_time_vector ; v_st_phys1_vector : inout st_phys1_vector ; v_st_real_vector : inout st_real_vector ; v_st_real1_vector : inout st_real1_vector ; v_st_rec1_vector : inout st_rec1_vector ; v_st_rec2_vector : inout st_rec2_vector ; v_st_rec3_vector : inout st_rec3_vector ; v_st_arr1_vector : inout st_arr1_vector ; v_st_arr2_vector : inout st_arr2_vector ; v_st_arr3_vector : inout st_arr3_vector ) is begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ( v_st_boolean_vector , v_st_bit_vector , v_st_severity_level_vector , v_st_string , v_st_enum1_vector , v_st_integer_vector , v_st_int1_vector , v_st_time_vector , v_st_phys1_vector , v_st_real_vector , v_st_real1_vector , v_st_rec1_vector , v_st_rec2_vector , v_st_rec3_vector , v_st_arr1_vector , v_st_arr2_vector , v_st_arr3_vector ) ; correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P4" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P4 ; -- end ARCH00034 ; -- entity ENT00034_Test_Bench is end ENT00034_Test_Bench ; -- architecture ARCH00034_Test_Bench of ENT00034_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00034 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00034_Test_Bench ;	gpl-3.0	834bfcdf74efbce805a9045c9412b35b	0.514372	3.003945	false	false	false	false
grwlf/vsim	vhdl_ct/ct00218.vhd	1	5,433	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00218 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.1 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00218(ARCH00218) -- ENT00218_Test_Bench(ARCH00218_Test_Bench) -- -- REVISION HISTORY: -- -- 10-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00218 is generic (G : integer) ; port ( s_st_arr1_vector : inout st_arr1_vector ) ; -- constant CG : integer := G+1; attribute attr : integer ; attribute attr of CG : constant is CG+1; -- end ENT00218 ; -- -- architecture ARCH00218 of ENT00218 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_2(1)(1) ; s_st_arr1_vector(2)(1 to 2) <= transport c_st_arr1_vector_2(2)(1 to 2) after 10 ns ; wait until s_st_arr1_vector(2)(1 to 2) = c_st_arr1_vector_2(2)(1 to 2) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(2)(1 to 2) = c_st_arr1_vector_2(2)(1 to 2) )) ; -- when 1 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_1(1)(1) ; s_st_arr1_vector(G)(G-1 to G) <= transport c_st_arr1_vector_2(G)(G-1 to G) after 10 ns ; wait until s_st_arr1_vector(G)(G-1 to G) = c_st_arr1_vector_2(G)(G-1 to G) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(G)(G-1 to G) = c_st_arr1_vector_2(G)(G-1 to G) )) ; -- when 2 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_2(1)(1) ; s_st_arr1_vector(CG)(CG-1 to CG) <= transport c_st_arr1_vector_2(CG)(CG-1 to CG) after 10 ns ; wait until s_st_arr1_vector(CG)(CG-1 to CG) = c_st_arr1_vector_2(CG)(CG-1 to CG) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(CG)(CG-1 to CG) = c_st_arr1_vector_2(CG)(CG-1 to CG) )) ; -- when 3 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_1(1)(1) ; s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) <= transport c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) after 10 ns ; wait until s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) = c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) = c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) )) ; -- when others => wait ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time := 0 ns ; begin Proc1 ( s_st_arr1_vector , counter , correct , savtime , chk_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Wait longest static prefix test completed", chk_st_arr1_vector = 3 ) ; end if ; end process PGEN_CHKP_1 ; -- -- end ARCH00218 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00218_Test_Bench is end ENT00218_Test_Bench ; -- -- architecture ARCH00218_Test_Bench of ENT00218_Test_Bench is begin L1: block signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; -- component UUT generic (G : integer) ; port ( s_st_arr1_vector : inout st_arr1_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00218 ( ARCH00218 ) ; begin CIS1 : UUT generic map (lowb+2) port map ( s_st_arr1_vector ) ; end block L1 ; end ARCH00218_Test_Bench ;	gpl-3.0	6c8378613eb040f7ca4a9f476d51409a	0.492546	3.296723	false	true	false	false
jairov4/accel-oil	solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw_add_64ns_64ns_64_2.vhd	1	7,164	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(63 downto 0); b: in std_logic_vector(63 downto 0); s: out std_logic_vector(63 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is port ( faa : IN STD_LOGIC_VECTOR (32-1 downto 0); fab : IN STD_LOGIC_VECTOR (32-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (32-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (32-1 downto 0); fab : IN STD_LOGIC_VECTOR (32-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (32-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(63 downto 0); signal b_reg : std_logic_vector(63 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(31 downto 0); signal b0_cb : std_logic_vector(31 downto 0); signal a1_cb : std_logic_vector(63 downto 32); signal b1_cb : std_logic_vector(63 downto 32); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(31 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; -- wires for each full adder sum signal fas : std_logic_vector(63 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo0 is array (0 downto 0) of std_logic_vector(31 downto 0); signal s0_ca_rego0 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(63 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(31 downto 0); b0_cb <= b_reg(31 downto 0); a1_cb <= a_reg(63 downto 32); b1_cb <= b_reg(63 downto 32); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(31 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(63 downto 32), facout => faccout1_co1); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(31 downto 0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(31 downto 0) <= s0_ca_rego0(0); s_tmp(63 downto 32) <= fas(63 downto 32); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is generic(N : natural :=32); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is generic(N : natural :=32); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_U : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;	lgpl-3.0	b4c7fe4ed217da6c8362e4b07163573a	0.620324	3.03688	false	false	false	false
jairov4/accel-oil	solution_spartan6/impl/vhdl/sample_iterator_get_offset.vhd	1	42,907	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0'; signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal indices_begin_addr_reg_135 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_147 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_162 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_2_reg_167 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_116_ce : STD_LOGIC; signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_116_p0, din1 => grp_fu_116_p1, ce => grp_fu_116_ce, dout => grp_fu_116_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 1, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_125_p0, din1 => grp_fu_125_p1, ce => grp_fu_125_ce, dout => grp_fu_125_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it10 assign process. -- ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it10 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it11 assign process. -- ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it11 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it12 assign process. -- ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it12 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it13 assign process. -- ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it13 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it14 assign process. -- ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it14 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it15 assign process. -- ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it15 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it16 assign process. -- ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it16 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it17 assign process. -- ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it17 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130; ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1; ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2; ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3; ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0) <= indices_begin_addr_reg_135(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1) <= indices_begin_addr_reg_135(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2) <= indices_begin_addr_reg_135(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3) <= indices_begin_addr_reg_135(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4) <= indices_begin_addr_reg_135(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5) <= indices_begin_addr_reg_135(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6) <= indices_begin_addr_reg_135(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7) <= indices_begin_addr_reg_135(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8) <= indices_begin_addr_reg_135(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9) <= indices_begin_addr_reg_135(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10) <= indices_begin_addr_reg_135(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11) <= indices_begin_addr_reg_135(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12) <= indices_begin_addr_reg_135(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13) <= indices_begin_addr_reg_135(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14) <= indices_begin_addr_reg_135(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15) <= indices_begin_addr_reg_135(15); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_130 <= i_sample; indices_begin_addr_reg_135(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0); indices_begin_addr_reg_135(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1); indices_begin_addr_reg_135(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2); indices_begin_addr_reg_135(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3); indices_begin_addr_reg_135(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4); indices_begin_addr_reg_135(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5); indices_begin_addr_reg_135(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6); indices_begin_addr_reg_135(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7); indices_begin_addr_reg_135(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8); indices_begin_addr_reg_135(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9); indices_begin_addr_reg_135(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10); indices_begin_addr_reg_135(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11); indices_begin_addr_reg_135(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12); indices_begin_addr_reg_135(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13); indices_begin_addr_reg_135(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14); indices_begin_addr_reg_135(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_162 <= indices_begin_datain; tmp_2_reg_167 <= grp_fu_116_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_147 <= indices_stride_datain; end if; end if; end process; indices_begin_addr_reg_135(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it9 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it17, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= grp_fu_125_p2; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_116_ce assign process. -- grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_116_ce <= ap_const_logic_1; else grp_fu_116_ce <= ap_const_logic_0; end if; end process; grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0); grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5),24)); grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0); grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_147),24)); -- grp_fu_125_ce assign process. -- grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_125_ce <= ap_const_logic_1; else grp_fu_125_ce <= ap_const_logic_0; end if; end process; grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_2_reg_167),32)); grp_fu_125_p1 <= indices_begin_addr_read_reg_162; indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0); indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64)); end behav;	lgpl-3.0	f70f775b9fa76f104860b9cbdb8b7ef8	0.616939	2.635403	false	false	false	false
grwlf/vsim	vhdl_ct/ct00354.vhd	1	12,986	-- NEED RESULT: ARCH00354.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00354 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00354(ARCH00354) -- ENT00354_Test_Bench(ARCH00354_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00354 is port ( s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- end ENT00354 ; -- -- architecture ARCH00354 of ENT00354 is subtype chk_time_type is Time ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; -- begin CHG1 : process ( s_st_rec1 ) variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1.f2 <= transport -- c_st_rec1_2.f2 after 10 ns, -- c_st_rec1_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec1.f2 = c_st_rec1_2.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1.f2 = c_st_rec1_1.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1.f2 <= transport -- c_st_rec1_2.f2 after 10 ns , -- c_st_rec1_1.f2 after 20 ns , -- c_st_rec1_2.f2 after 30 ns , -- c_st_rec1_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec1.f2 = c_st_rec1_2.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1.f2 <= transport -- c_st_rec1_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1.f2 = c_st_rec1_1.f2 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec1.f2 <= transport c_st_rec1_2.f2 after 10 ns, c_st_rec1_1.f2 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2.f2 after 10 ns , c_st_rec1_1.f2 after 20 ns , c_st_rec1_2.f2 after 30 ns , c_st_rec1_1.f2 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1.f2 after 5 ns ; -- CHG2 : process ( s_st_rec2 ) variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2.f2 <= transport -- c_st_rec2_2.f2 after 10 ns, -- c_st_rec2_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec2.f2 = c_st_rec2_2.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2.f2 = c_st_rec2_1.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2.f2 <= transport -- c_st_rec2_2.f2 after 10 ns , -- c_st_rec2_1.f2 after 20 ns , -- c_st_rec2_2.f2 after 30 ns , -- c_st_rec2_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec2.f2 = c_st_rec2_2.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2.f2 <= transport -- c_st_rec2_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2.f2 = c_st_rec2_1.f2 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_rec2.f2 <= transport c_st_rec2_2.f2 after 10 ns, c_st_rec2_1.f2 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2.f2 after 10 ns , c_st_rec2_1.f2 after 20 ns , c_st_rec2_2.f2 after 30 ns , c_st_rec2_1.f2 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1.f2 after 5 ns ; -- CHG3 : process ( s_st_rec3 ) variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f2 <= transport -- c_st_rec3_2.f2 after 10 ns, -- c_st_rec3_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec3.f2 = c_st_rec3_2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3.f2 = c_st_rec3_1.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3.f2 <= transport -- c_st_rec3_2.f2 after 10 ns , -- c_st_rec3_1.f2 after 20 ns , -- c_st_rec3_2.f2 after 30 ns , -- c_st_rec3_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec3.f2 = c_st_rec3_2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3.f2 <= transport -- c_st_rec3_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3.f2 = c_st_rec3_1.f2 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_rec3.f2 <= transport c_st_rec3_2.f2 after 10 ns, c_st_rec3_1.f2 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2.f2 after 10 ns , c_st_rec3_1.f2 after 20 ns , c_st_rec3_2.f2 after 30 ns , c_st_rec3_1.f2 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1.f2 after 5 ns ; -- end ARCH00354 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00354_Test_Bench is signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- end ENT00354_Test_Bench ; -- -- architecture ARCH00354_Test_Bench of ENT00354_Test_Bench is begin L1: block component UUT port ( s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00354 ( ARCH00354 ) ; begin CIS1 : UUT port map ( s_st_rec1 , s_st_rec2 , s_st_rec3 ) ; end block L1 ; end ARCH00354_Test_Bench ;	gpl-3.0	1ac5fbe597bd9ac081a43ba0a39e23ab	0.485215	3.321228	false	true	false	false
grwlf/vsim	vhdl/entity1.vhd	1	938	-- Simple entity test, in/out ports entity main is end entity main; entity unit1 is port ( inum : in integer; oled : out integer); end entity unit1; architecture unit1_a of unit1 is signal a : integer := 1; begin oled <= inum + a; end architecture unit1_a; architecture main of main is constant CYCLES : integer := 100; signal clk : integer := 0; signal o1 : integer; signal o2 : integer; signal o : integer; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; end if; end process; u1:entity unit1(unit1_a) port map(inum=>clk, oled=>o1); u2:entity unit1(unit1_a) port map(inum=>clk, oled=>o2); clk <= clk + 1 after 1 us; o <= o1 + o2; reporter : process(o) begin report "o=" & integer'image(o); end process; end architecture main;	gpl-3.0	3ebf7e9f82e22b0c7e05ca065760f4b8	0.607676	3.314488	false	false	false	false
grwlf/vsim	vhdl_ct/ct00030.vhd	1	16,190	-- NEED RESULT: ARCH00030.P1: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P2: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P3: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P4: Target of a variable assignment may be a simple name passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00030 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00030) -- ENT00030_Test_Bench(ARCH00030_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00030 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P1" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00030.P2" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ; correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P3" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( p_boolean : inout boolean ; p_bit : inout bit ; p_severity_level : inout severity_level ; p_character : inout character ; p_st_enum1 : inout st_enum1 ; p_integer : inout integer ; p_st_int1 : inout st_int1 ; p_time : inout time ; p_st_phys1 : inout st_phys1 ; p_real : inout real ; p_st_real1 : inout st_real1 ; p_st_rec1 : inout st_rec1 ; p_st_rec2 : inout st_rec2 ; p_st_rec3 : inout st_rec3 ; p_st_arr1 : inout st_arr1 ; p_st_arr2 : inout st_arr2 ; p_st_arr3 : inout st_arr3 ) is begin p_boolean := c_boolean_2 ; p_bit := c_bit_2 ; p_severity_level := c_severity_level_2 ; p_character := c_character_2 ; p_st_enum1 := c_st_enum1_2 ; p_integer := c_integer_2 ; p_st_int1 := c_st_int1_2 ; p_time := c_time_2 ; p_st_phys1 := c_st_phys1_2 ; p_real := c_real_2 ; p_st_real1 := c_st_real1_2 ; p_st_rec1 := c_st_rec1_2 ; p_st_rec2 := c_st_rec2_2 ; p_st_rec3 := c_st_rec3_2 ; p_st_arr1 := c_st_arr1_2 ; p_st_arr2 := c_st_arr2_2 ; p_st_arr3 := c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ( v_boolean , v_bit , v_severity_level , v_character , v_st_enum1 , v_integer , v_st_int1 , v_time , v_st_phys1 , v_real , v_st_real1 , v_st_rec1 , v_st_rec2 , v_st_rec3 , v_st_arr1 , v_st_arr2 , v_st_arr3 ) ; correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P4" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P4 ; -- end ARCH00030 ; -- entity ENT00030_Test_Bench is end ENT00030_Test_Bench ; -- architecture ARCH00030_Test_Bench of ENT00030_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00030 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00030_Test_Bench ;	gpl-3.0	9498bb0d7d036ec0c1b23baba731be32	0.450154	3.336768	false	false	false	false
grwlf/vsim	vhdl_ct/ct00549.vhd	1	3,106	-- NEED RESULT: ARCH00549: Constant declarations - composite static subtypes failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00549 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00549) -- ENT00549_Test_Bench(ARCH00549_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00549 of E00000 is begin process variable correct : boolean := true ; constant co_bit_vector_1 : bit_vector := c_st_bit_vector_1 ; constant co_string_1 : string := c_st_string_1 ; constant co_t_rec1_1 : t_rec1 := c_st_rec1_1 ; constant co_st_rec1_1 : st_rec1 := c_st_rec1_1 ; constant co_t_rec2_1 : t_rec2 := c_st_rec2_1 ; constant co_st_rec2_1 : st_rec2 := c_st_rec2_1 ; constant co_t_rec3_1 : t_rec3 := c_st_rec3_1 ; constant co_st_rec3_1 : st_rec3 := c_st_rec3_1 ; constant co_t_arr1_1 : t_arr1 := c_st_arr1_1 ; constant co_st_arr1_1 : st_arr1 := c_st_arr1_1 ; constant co_t_arr2_1 : t_arr2 := c_st_arr2_1 ; constant co_st_arr2_1 : st_arr2 := c_st_arr2_1 ; constant co_t_arr3_1 : t_arr3 := c_st_arr3_1 ; constant co_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and co_string_1 = c_st_string_1 ; correct := correct and co_t_rec1_1 = c_t_rec1_1 ; correct := correct and co_st_rec1_1 = c_st_rec1_1 ; correct := correct and co_t_rec2_1 = c_t_rec2_1 ; correct := correct and co_st_rec2_1 = c_st_rec2_1 ; correct := correct and co_t_rec3_1 = c_t_rec3_1 ; correct := correct and co_st_rec3_1 = c_st_rec3_1 ; correct := correct and co_t_arr1_1 = c_t_arr1_1 ; correct := correct and co_st_arr1_1 = c_st_arr1_1 ; correct := correct and co_t_arr2_1 = c_t_arr2_1 ; correct := correct and co_st_arr2_1 = c_st_arr2_1 ; correct := correct and co_t_arr3_1 = c_t_arr3_1 ; correct := correct and co_st_arr3_1 = c_st_arr3_1 ; test_report ( "ARCH00549" , "Constant declarations - composite static subtypes" , correct) ; wait ; end process ; end ARCH00549 ; -- entity ENT00549_Test_Bench is end ENT00549_Test_Bench ; -- architecture ARCH00549_Test_Bench of ENT00549_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00549 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00549_Test_Bench ;	gpl-3.0	eda3aca7a06c9b741070c25e49a55f99	0.515454	2.919173	false	true	false	false
grwlf/vsim	vhdl/entity5.vhd	1	854	entity test is end entity test; entity unit is port ( inum : in integer; oled : out integer); end entity unit; architecture unit_a of unit is subtype oneten is integer range 1 to 10 ; signal a : oneten := 1; begin oled <= inum + a; end architecture unit_a; architecture test_arch of test is subtype onetwo is integer range 1 to 2 ; constant CYCLES : integer := 100; signal clk : integer := 0; signal i : integer := 0; signal o1,o2 : integer; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; u1:entity unit(unit_a) port map(inum=>i, oled=>o1); u2:entity unit(unit_a) port map(inum=>i, oled=>o2); clk <= clk + 1 after 1 us; end architecture test_arch;	gpl-3.0	c0b1693ebaef8f5c30915bd43f88f9b8	0.640515	3.247148	false	true	false	false
jairov4/accel-oil	solution_kintex7/syn/vhdl/sample_iterator_get_offset.vhd	1	35,975	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0'; signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_reg_135 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_145 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_165 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_7_reg_170 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_110_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_ce : STD_LOGIC; signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_110_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_110_p0, din1 => grp_fu_110_p1, ce => grp_fu_110_ce, dout => grp_fu_110_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 1, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_125_p0, din1 => grp_fu_125_p1, ce => grp_fu_125_ce, dout => grp_fu_125_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it10 assign process. -- ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it10 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it11 assign process. -- ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it11 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it12 assign process. -- ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it12 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it13 assign process. -- ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it13 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130; ap_reg_ppstg_tmp_reg_135_pp0_it1(0) <= tmp_reg_135(0); ap_reg_ppstg_tmp_reg_135_pp0_it1(1) <= tmp_reg_135(1); ap_reg_ppstg_tmp_reg_135_pp0_it1(2) <= tmp_reg_135(2); ap_reg_ppstg_tmp_reg_135_pp0_it1(3) <= tmp_reg_135(3); ap_reg_ppstg_tmp_reg_135_pp0_it1(4) <= tmp_reg_135(4); ap_reg_ppstg_tmp_reg_135_pp0_it1(5) <= tmp_reg_135(5); ap_reg_ppstg_tmp_reg_135_pp0_it1(6) <= tmp_reg_135(6); ap_reg_ppstg_tmp_reg_135_pp0_it1(7) <= tmp_reg_135(7); ap_reg_ppstg_tmp_reg_135_pp0_it1(8) <= tmp_reg_135(8); ap_reg_ppstg_tmp_reg_135_pp0_it1(9) <= tmp_reg_135(9); ap_reg_ppstg_tmp_reg_135_pp0_it1(10) <= tmp_reg_135(10); ap_reg_ppstg_tmp_reg_135_pp0_it1(11) <= tmp_reg_135(11); ap_reg_ppstg_tmp_reg_135_pp0_it1(12) <= tmp_reg_135(12); ap_reg_ppstg_tmp_reg_135_pp0_it1(13) <= tmp_reg_135(13); ap_reg_ppstg_tmp_reg_135_pp0_it1(14) <= tmp_reg_135(14); ap_reg_ppstg_tmp_reg_135_pp0_it1(15) <= tmp_reg_135(15); ap_reg_ppstg_tmp_reg_135_pp0_it2(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(0); ap_reg_ppstg_tmp_reg_135_pp0_it2(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(1); ap_reg_ppstg_tmp_reg_135_pp0_it2(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(2); ap_reg_ppstg_tmp_reg_135_pp0_it2(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(3); ap_reg_ppstg_tmp_reg_135_pp0_it2(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(4); ap_reg_ppstg_tmp_reg_135_pp0_it2(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(5); ap_reg_ppstg_tmp_reg_135_pp0_it2(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(6); ap_reg_ppstg_tmp_reg_135_pp0_it2(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(7); ap_reg_ppstg_tmp_reg_135_pp0_it2(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(8); ap_reg_ppstg_tmp_reg_135_pp0_it2(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(9); ap_reg_ppstg_tmp_reg_135_pp0_it2(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(10); ap_reg_ppstg_tmp_reg_135_pp0_it2(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(11); ap_reg_ppstg_tmp_reg_135_pp0_it2(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(12); ap_reg_ppstg_tmp_reg_135_pp0_it2(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(13); ap_reg_ppstg_tmp_reg_135_pp0_it2(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(14); ap_reg_ppstg_tmp_reg_135_pp0_it2(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(15); ap_reg_ppstg_tmp_reg_135_pp0_it3(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(0); ap_reg_ppstg_tmp_reg_135_pp0_it3(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(1); ap_reg_ppstg_tmp_reg_135_pp0_it3(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(2); ap_reg_ppstg_tmp_reg_135_pp0_it3(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(3); ap_reg_ppstg_tmp_reg_135_pp0_it3(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(4); ap_reg_ppstg_tmp_reg_135_pp0_it3(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(5); ap_reg_ppstg_tmp_reg_135_pp0_it3(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(6); ap_reg_ppstg_tmp_reg_135_pp0_it3(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(7); ap_reg_ppstg_tmp_reg_135_pp0_it3(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(8); ap_reg_ppstg_tmp_reg_135_pp0_it3(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(9); ap_reg_ppstg_tmp_reg_135_pp0_it3(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(10); ap_reg_ppstg_tmp_reg_135_pp0_it3(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(11); ap_reg_ppstg_tmp_reg_135_pp0_it3(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(12); ap_reg_ppstg_tmp_reg_135_pp0_it3(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(13); ap_reg_ppstg_tmp_reg_135_pp0_it3(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(14); ap_reg_ppstg_tmp_reg_135_pp0_it3(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_130 <= i_sample; tmp_reg_135(0) <= tmp_fu_93_p1(0); tmp_reg_135(1) <= tmp_fu_93_p1(1); tmp_reg_135(2) <= tmp_fu_93_p1(2); tmp_reg_135(3) <= tmp_fu_93_p1(3); tmp_reg_135(4) <= tmp_fu_93_p1(4); tmp_reg_135(5) <= tmp_fu_93_p1(5); tmp_reg_135(6) <= tmp_fu_93_p1(6); tmp_reg_135(7) <= tmp_fu_93_p1(7); tmp_reg_135(8) <= tmp_fu_93_p1(8); tmp_reg_135(9) <= tmp_fu_93_p1(9); tmp_reg_135(10) <= tmp_fu_93_p1(10); tmp_reg_135(11) <= tmp_fu_93_p1(11); tmp_reg_135(12) <= tmp_fu_93_p1(12); tmp_reg_135(13) <= tmp_fu_93_p1(13); tmp_reg_135(14) <= tmp_fu_93_p1(14); tmp_reg_135(15) <= tmp_fu_93_p1(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_165 <= indices_begin_datain; tmp_7_reg_170 <= grp_fu_110_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_145 <= indices_stride_datain; end if; end if; end process; tmp_reg_135(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it2(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it3(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it5 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it13, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= grp_fu_125_p2; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_110_ce assign process. -- grp_fu_110_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_110_ce <= ap_const_logic_1; else grp_fu_110_ce <= ap_const_logic_0; end if; end process; grp_fu_110_p0 <= grp_fu_110_p00(16 - 1 downto 0); grp_fu_110_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1),24)); grp_fu_110_p1 <= grp_fu_110_p10(8 - 1 downto 0); grp_fu_110_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_145),24)); -- grp_fu_125_ce assign process. -- grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_125_ce <= ap_const_logic_1; else grp_fu_125_ce <= ap_const_logic_0; end if; end process; grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_7_reg_170),32)); grp_fu_125_p1 <= indices_begin_addr_read_reg_165; indices_begin_address <= ap_reg_ppstg_tmp_reg_135_pp0_it3; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1; indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),32)); end behav;	lgpl-3.0	f8ce0d382451392c704eb2e404a4957c	0.607088	2.598786	false	false	false	false
grwlf/vsim	vhdl_ct/pro000012.vhd	1	3,978	-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00009_Test_Bench is end ENT00009_Test_Bench; architecture ARCH00009_Test_Bench of ENT00009_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b2 : byte2 := x"00"; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal ea : enum_array(0 to 3) := (others => a_v); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; signal bit_1, bit_2, bit_3, bit_4 , bit_5, bit_6, bit_7, bit_8 , bit_9, bit_10, bit_11, bit_12 : bit; begin bit_1 <= bv'Transaction; bit_2 <= ra'Transaction; bit_3 <= r'Transaction; bit_4 <= ea'Transaction; bit_5 <= e'Transaction; bit_6 <= I_sa'Transaction; bit_7 <= I_baa'Transaction; bit_8 <= I_saa'Transaction; bit_9 <= b1'Transaction; bit_10 <= b2'Transaction; bit_11 <= clk'Transaction; bit_12 <= clk2'Transaction; clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00009_Test_Bench;	gpl-3.0	0ec03f22e37b08d26f3bb845698b0bd4	0.548014	2.467742	false	false	false	false
Given-Jiang/Binarization	tb_Binarization/reports/Binarization/Binarization_example.vhd	1	2,455	library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity Binarization_example is port( Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0); Avalon_ST_Source_startofpacket : out STD_LOGIC; Avalon_ST_Sink_endofpacket : in STD_LOGIC; Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0); Avalon_ST_Source_valid : out STD_LOGIC; Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0); Avalon_ST_Sink_valid : in STD_LOGIC; Clock : in STD_LOGIC; aclr : in STD_LOGIC; Avalon_ST_Source_ready : in STD_LOGIC; Avalon_MM_Slave_write : in STD_LOGIC; Avalon_ST_Sink_ready : out STD_LOGIC; Avalon_ST_Sink_startofpacket : in STD_LOGIC; Avalon_ST_Source_endofpacket : out STD_LOGIC; Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0)); end entity; architecture rtl of Binarization_example is component Binarization port( Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0); Avalon_ST_Source_startofpacket : out STD_LOGIC; Avalon_ST_Sink_endofpacket : in STD_LOGIC; Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0); Avalon_ST_Source_valid : out STD_LOGIC; Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0); Avalon_ST_Sink_valid : in STD_LOGIC; Clock : in STD_LOGIC; aclr : in STD_LOGIC; Avalon_ST_Source_ready : in STD_LOGIC; Avalon_MM_Slave_write : in STD_LOGIC; Avalon_ST_Sink_ready : out STD_LOGIC; Avalon_ST_Sink_startofpacket : in STD_LOGIC; Avalon_ST_Source_endofpacket : out STD_LOGIC; Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0)); end component; begin Binarization_instance : component Binarization port map( Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Clock => Clock, aclr => aclr, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_data => Avalon_ST_Source_data); end architecture rtl;	mit	182768af9911e3feb515ead5054bb1e3	0.719756	3.042131	false	false	false	false
grwlf/vsim	vhdl_ct/ct00613.vhd	1	49,229	-- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P10: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P10: Transport transactions completed entirely passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00613 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00613(ARCH00613) -- ENT00613_Test_Bench(ARCH00613_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00613 is end ENT00613 ; -- -- architecture ARCH00613 of ENT00613 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; -- signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; -- procedure P1 (signal s_st_boolean_vector : in st_boolean_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns, -- c_st_boolean_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns , -- c_st_boolean_vector_1(lowb) after 20 ns , -- c_st_boolean_vector_2(lowb) after 30 ns , -- c_st_boolean_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_boolean_vector_cnt + 1 ; -- end ; -- procedure P2 (signal s_st_severity_level_vector : in st_severity_level_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns, -- c_st_severity_level_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns , -- c_st_severity_level_vector_1(lowb) after 20 ns , -- c_st_severity_level_vector_2(lowb) after 30 ns , -- c_st_severity_level_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_severity_level_vector_cnt + 1 ; -- end ; -- procedure P3 (signal s_st_string : in st_string ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns, -- c_st_string_1(highb) after 20 ns ; -- when 1 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns , -- c_st_string_1(highb) after 20 ns , -- c_st_string_2(highb) after 30 ns , -- c_st_string_1(highb) after 40 ns ; -- when 3 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_string(highb) <= transport -- c_st_string_1(highb) after 5 ns ; -- when 4 => correct := s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_string_cnt + 1 ; -- end ; -- procedure P4 (signal s_st_enum1_vector : in st_enum1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns, -- c_st_enum1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns , -- c_st_enum1_vector_1(highb) after 20 ns , -- c_st_enum1_vector_2(highb) after 30 ns , -- c_st_enum1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_enum1_vector_cnt + 1 ; -- end ; -- procedure P5 (signal s_st_integer_vector : in st_integer_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns, -- c_st_integer_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns , -- c_st_integer_vector_1(lowb) after 20 ns , -- c_st_integer_vector_2(lowb) after 30 ns , -- c_st_integer_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_integer_vector_cnt + 1 ; -- end ; -- procedure P6 (signal s_st_time_vector : in st_time_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns, -- c_st_time_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns , -- c_st_time_vector_1(lowb) after 20 ns , -- c_st_time_vector_2(lowb) after 30 ns , -- c_st_time_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_time_vector_cnt + 1 ; -- end ; -- procedure P7 (signal s_st_real_vector : in st_real_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns, -- c_st_real_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns , -- c_st_real_vector_1(highb) after 20 ns , -- c_st_real_vector_2(highb) after 30 ns , -- c_st_real_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_real_vector_cnt + 1 ; -- end ; -- procedure P8 (signal s_st_rec1_vector : in st_rec1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns, -- c_st_rec1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns , -- c_st_rec1_vector_1(highb) after 20 ns , -- c_st_rec1_vector_2(highb) after 30 ns , -- c_st_rec1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec1_vector_cnt + 1 ; -- end ; -- procedure P9 (signal s_st_arr2_vector : in st_arr2_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns, -- c_st_arr2_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns , -- c_st_arr2_vector_1(lowb) after 20 ns , -- c_st_arr2_vector_2(lowb) after 30 ns , -- c_st_arr2_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_vector_cnt + 1 ; -- end ; -- procedure P10 (signal s_st_arr2 : in st_arr2 ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns, -- c_st_arr2_1(highb,false) after 20 ns ; -- when 1 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P10" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns , -- c_st_arr2_1(highb,false) after 20 ns , -- c_st_arr2_2(highb,false) after 30 ns , -- c_st_arr2_1(highb,false) after 40 ns ; -- when 3 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_1(highb,false) after 5 ns ; -- when 4 => correct := s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_boolean_vector , st_boolean_vector_select , s_st_boolean_vector_savt , chk_st_boolean_vector , s_st_boolean_vector_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb) <= transport c_st_boolean_vector_2(lowb) after 10 ns, c_st_boolean_vector_1(lowb) after 20 ns when 1, -- c_st_boolean_vector_2(lowb) after 10 ns , c_st_boolean_vector_1(lowb) after 20 ns , c_st_boolean_vector_2(lowb) after 30 ns , c_st_boolean_vector_1(lowb) after 40 ns when 2, -- c_st_boolean_vector_1(lowb) after 5 ns when 3 ; -- CHG2 : P2( s_st_severity_level_vector , st_severity_level_vector_select , s_st_severity_level_vector_savt , chk_st_severity_level_vector , s_st_severity_level_vector_cnt ) ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb) <= transport c_st_severity_level_vector_2(lowb) after 10 ns, c_st_severity_level_vector_1(lowb) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb) after 10 ns , c_st_severity_level_vector_1(lowb) after 20 ns , c_st_severity_level_vector_2(lowb) after 30 ns , c_st_severity_level_vector_1(lowb) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb) after 5 ns when 3 ; -- CHG3 : P3( s_st_string , st_string_select , s_st_string_savt , chk_st_string , s_st_string_cnt ) ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb) <= transport c_st_string_2(highb) after 10 ns, c_st_string_1(highb) after 20 ns when 1, -- c_st_string_2(highb) after 10 ns , c_st_string_1(highb) after 20 ns , c_st_string_2(highb) after 30 ns , c_st_string_1(highb) after 40 ns when 2, -- c_st_string_1(highb) after 5 ns when 3 ; -- CHG4 : P4( s_st_enum1_vector , st_enum1_vector_select , s_st_enum1_vector_savt , chk_st_enum1_vector , s_st_enum1_vector_cnt ) ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb) <= transport c_st_enum1_vector_2(highb) after 10 ns, c_st_enum1_vector_1(highb) after 20 ns when 1, -- c_st_enum1_vector_2(highb) after 10 ns , c_st_enum1_vector_1(highb) after 20 ns , c_st_enum1_vector_2(highb) after 30 ns , c_st_enum1_vector_1(highb) after 40 ns when 2, -- c_st_enum1_vector_1(highb) after 5 ns when 3 ; -- CHG5 : P5( s_st_integer_vector , st_integer_vector_select , s_st_integer_vector_savt , chk_st_integer_vector , s_st_integer_vector_cnt ) ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb) <= transport c_st_integer_vector_2(lowb) after 10 ns, c_st_integer_vector_1(lowb) after 20 ns when 1, -- c_st_integer_vector_2(lowb) after 10 ns , c_st_integer_vector_1(lowb) after 20 ns , c_st_integer_vector_2(lowb) after 30 ns , c_st_integer_vector_1(lowb) after 40 ns when 2, -- c_st_integer_vector_1(lowb) after 5 ns when 3 ; -- CHG6 : P6( s_st_time_vector , st_time_vector_select , s_st_time_vector_savt , chk_st_time_vector , s_st_time_vector_cnt ) ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb) <= transport c_st_time_vector_2(lowb) after 10 ns, c_st_time_vector_1(lowb) after 20 ns when 1, -- c_st_time_vector_2(lowb) after 10 ns , c_st_time_vector_1(lowb) after 20 ns , c_st_time_vector_2(lowb) after 30 ns , c_st_time_vector_1(lowb) after 40 ns when 2, -- c_st_time_vector_1(lowb) after 5 ns when 3 ; -- CHG7 : P7( s_st_real_vector , st_real_vector_select , s_st_real_vector_savt , chk_st_real_vector , s_st_real_vector_cnt ) ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb) <= transport c_st_real_vector_2(highb) after 10 ns, c_st_real_vector_1(highb) after 20 ns when 1, -- c_st_real_vector_2(highb) after 10 ns , c_st_real_vector_1(highb) after 20 ns , c_st_real_vector_2(highb) after 30 ns , c_st_real_vector_1(highb) after 40 ns when 2, -- c_st_real_vector_1(highb) after 5 ns when 3 ; -- CHG8 : P8( s_st_rec1_vector , st_rec1_vector_select , s_st_rec1_vector_savt , chk_st_rec1_vector , s_st_rec1_vector_cnt ) ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb) <= transport c_st_rec1_vector_2(highb) after 10 ns, c_st_rec1_vector_1(highb) after 20 ns when 1, -- c_st_rec1_vector_2(highb) after 10 ns , c_st_rec1_vector_1(highb) after 20 ns , c_st_rec1_vector_2(highb) after 30 ns , c_st_rec1_vector_1(highb) after 40 ns when 2, -- c_st_rec1_vector_1(highb) after 5 ns when 3 ; -- CHG9 : P9( s_st_arr2_vector , st_arr2_vector_select , s_st_arr2_vector_savt , chk_st_arr2_vector , s_st_arr2_vector_cnt ) ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb) <= transport c_st_arr2_vector_2(lowb) after 10 ns, c_st_arr2_vector_1(lowb) after 20 ns when 1, -- c_st_arr2_vector_2(lowb) after 10 ns , c_st_arr2_vector_1(lowb) after 20 ns , c_st_arr2_vector_2(lowb) after 30 ns , c_st_arr2_vector_1(lowb) after 40 ns when 2, -- c_st_arr2_vector_1(lowb) after 5 ns when 3 ; -- CHG10 : P10( s_st_arr2 , st_arr2_select , s_st_arr2_savt , chk_st_arr2 , s_st_arr2_cnt ) ; -- PGEN_CHKP_10 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions completed entirely", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- -- with st_arr2_select select s_st_arr2(highb,false) <= transport c_st_arr2_2(highb,false) after 10 ns, c_st_arr2_1(highb,false) after 20 ns when 1, -- c_st_arr2_2(highb,false) after 10 ns , c_st_arr2_1(highb,false) after 20 ns , c_st_arr2_2(highb,false) after 30 ns , c_st_arr2_1(highb,false) after 40 ns when 2, -- c_st_arr2_1(highb,false) after 5 ns when 3 ; -- end ARCH00613 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00613_Test_Bench is end ENT00613_Test_Bench ; -- -- architecture ARCH00613_Test_Bench of ENT00613_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00613 ( ARCH00613 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00613_Test_Bench ;	gpl-3.0	edd1737484561ec4d3ae61df8ac24acd	0.5266	3.565252	false	true	false	false
jairov4/accel-oil	impl/impl_test_pcie/simulation/behavioral/system_dlmb_cntlr_wrapper.vhd	1	18,331	------------------------------------------------------------------------------- -- system_dlmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v3_10_c; use lmb_bram_if_cntlr_v3_10_c.all; entity system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end system_dlmb_cntlr_wrapper; architecture STRUCTURE of system_dlmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_FAMILY : string; C_MASK : std_logic_vector(0 to 31); C_MASK1 : std_logic_vector(0 to 31); C_MASK2 : std_logic_vector(0 to 31); C_MASK3 : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_ECC : integer; C_INTERCONNECT : integer; C_FAULT_INJECT : integer; C_CE_FAILING_REGISTERS : integer; C_UE_FAILING_REGISTERS : integer; C_ECC_STATUS_REGISTERS : integer; C_ECC_ONOFF_REGISTER : integer; C_ECC_ONOFF_RESET_VALUE : integer; C_CE_COUNTER_WIDTH : integer; C_WRITE_ACCESS : integer; C_NUM_LMB : integer; C_SPLB_CTRL_BASEADDR : std_logic_vector; C_SPLB_CTRL_HIGHADDR : std_logic_vector; C_SPLB_CTRL_AWIDTH : INTEGER; C_SPLB_CTRL_DWIDTH : INTEGER; C_SPLB_CTRL_P2P : INTEGER; C_SPLB_CTRL_MID_WIDTH : INTEGER; C_SPLB_CTRL_NUM_MASTERS : INTEGER; C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER; C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER; C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8C_ECC)/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8C_ECC); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1)); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1)); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; begin dlmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00000fff", C_FAMILY => "virtex5", C_MASK => X"80000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_NUM_LMB => 1, C_SPLB_CTRL_BASEADDR => X"FFFFFFFF", C_SPLB_CTRL_HIGHADDR => X"00000000", C_SPLB_CTRL_AWIDTH => 32, C_SPLB_CTRL_DWIDTH => 32, C_SPLB_CTRL_P2P => 0, C_SPLB_CTRL_MID_WIDTH => 1, C_SPLB_CTRL_NUM_MASTERS => 1, C_SPLB_CTRL_SUPPORT_BURSTS => 0, C_SPLB_CTRL_NATIVE_DWIDTH => 32, C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF", C_S_AXI_CTRL_HIGHADDR => X"00000000", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => LMB1_ABus, LMB1_WriteDBus => LMB1_WriteDBus, LMB1_AddrStrobe => LMB1_AddrStrobe, LMB1_ReadStrobe => LMB1_ReadStrobe, LMB1_WriteStrobe => LMB1_WriteStrobe, LMB1_BE => LMB1_BE, Sl1_DBus => Sl1_DBus, Sl1_Ready => Sl1_Ready, Sl1_Wait => Sl1_Wait, Sl1_UE => Sl1_UE, Sl1_CE => Sl1_CE, LMB2_ABus => LMB2_ABus, LMB2_WriteDBus => LMB2_WriteDBus, LMB2_AddrStrobe => LMB2_AddrStrobe, LMB2_ReadStrobe => LMB2_ReadStrobe, LMB2_WriteStrobe => LMB2_WriteStrobe, LMB2_BE => LMB2_BE, Sl2_DBus => Sl2_DBus, Sl2_Ready => Sl2_Ready, Sl2_Wait => Sl2_Wait, Sl2_UE => Sl2_UE, Sl2_CE => Sl2_CE, LMB3_ABus => LMB3_ABus, LMB3_WriteDBus => LMB3_WriteDBus, LMB3_AddrStrobe => LMB3_AddrStrobe, LMB3_ReadStrobe => LMB3_ReadStrobe, LMB3_WriteStrobe => LMB3_WriteStrobe, LMB3_BE => LMB3_BE, Sl3_DBus => Sl3_DBus, Sl3_Ready => Sl3_Ready, Sl3_Wait => Sl3_Wait, Sl3_UE => Sl3_UE, Sl3_CE => Sl3_CE, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, Interrupt => Interrupt, UE => UE, CE => CE, SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus, SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid, SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID, SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW, SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE, SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size, SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type, SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus, SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck, SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize, SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait, SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate, SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck, SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp, SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus, SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck, SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp, SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy, SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr, SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr, SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus, SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid, SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim, SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim, SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort, SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock, SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize, SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr, SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst, SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst, SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq, SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq, SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri, SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri, SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri, SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute, SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm, SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr, SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm, SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ, S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK, S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN, S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR, S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID, S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY, S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA, S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB, S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID, S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY, S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP, S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID, S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY, S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR, S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID, S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY, S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA, S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP, S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID, S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ); end architecture STRUCTURE;	lgpl-3.0	ec10d3d7ce49d40e892ebe82fa1fc114	0.615078	2.93296	false	false	false	false
grwlf/vsim	vhdl_ct/ct00490.vhd	1	8,474	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00490 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (3) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00490(ARCH00490) -- ENT00490_Test_Bench(ARCH00490_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00490 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00490 ; -- architecture ARCH00490 of ENT00490 is begin B1 : block generic ( g_arr_1 : st_arr_1 ; g_time_matrix : st_time_matrix ; g_bit_vector : st_bit_vector ; g_string : st_string ; g_rec_1 : rec_1 ) ; generic map ( ( others => (others => c_rec_1_1) ) , ( others => (others => 15ms) ) , ( others => '0' ) , ( others => 'a' ) , -- ( f2 => (others => false), others => 0) ) ; ( others => 0) ) ; -- procedure p3 is variable bool : boolean := true ; begin for i in 1 to 5 loop bool := bool and g_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and g_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and g_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and g_bit_vector = B"00000" ; -- bool := bool and g_string = "aaa" ; -- bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0 and g_rec_1.f3 = 0 ; -- bool := bool and g_rec_1.f2(1) = false -- and g_rec_1.f2(0) = false and -- g_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00490" , "Aggregates with others choice associated with formal" & " generic (generic and dynamic)" , bool ) ; -- end p3; procedure p2 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- procedure p1 ( p_arr_1 : st_arr_1 ; p_time_matrix : st_time_matrix ; p_bit_vector : st_bit_vector ; p_string : st_string ; p_rec_1 : rec_1 ) is variable bool : boolean := true ; begin for i in 1 to 5 loop bool := bool and p_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and p_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and p_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and p_bit_vector = B"00000" ; -- bool := bool and p_string = "aaa" ; -- bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0 and p_rec_1.f3 = 0 ; -- bool := bool and p_rec_1.f2(1) = false -- and p_rec_1.f2(0) = false and -- p_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00490" , "Aggregates with others choice associated with formal" & " parameter (generic and dynamic)" , bool ) ; end p1 ; begin p1 ( ( others => (others => c_rec_1_1) ) , ( others => (others => 15ms) ) , ( others => '0' ) , ( others => 'a' ) , -- ( f2 => (others => false), others => 0) ) ; ( others => 0) ) ; p3 ; end p2 ; begin process begin p2( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; wait ; end process ; end block B1 ; end ARCH00490 ; -- entity ENT00490_Test_Bench is end ENT00490_Test_Bench ; -- architecture ARCH00490_Test_Bench of ENT00490_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00490 ( ARCH00490 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00490_Test_Bench ;	gpl-3.0	73f55ae8268fee31919b89937af8be16	0.457753	3.44052	false	false	false	false
MilosSubotic/huffman_coding	RTL/src/sim/huffman_encoder_tb.vhd	1	3,199	------------------------------------------------------------------------------ -- @license MIT ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.global.all; use work.huffman_encoder; entity huffman_encoder_tb is end entity huffman_encoder_tb; architecture arch_huffman_encoder_tb of huffman_encoder_tb is -- Possible values: note, warning, error, failure; constant assert_severity : severity_level := error; file stdout: text open write_mode is "STD_OUTPUT"; procedure println(s: string) is variable l: line; begin write(l, s); writeline(stdout, l); end procedure println; --Inputs signal aclk : std_logic := '0'; signal axi_resetn : std_logic := '0'; signal s_axis_tdata : std_logic_vector(7 downto 0) := (others => '0'); signal s_axis_tvalid : std_logic := '0'; signal s_axis_tlast : std_logic := '0'; signal m_axis_tready : std_logic := '0'; --Outputs signal s_axis_tready : std_logic; signal m_axis_tdata : std_logic_vector(7 downto 0); signal m_axis_tvalid : std_logic; signal m_axis_tlast : std_logic; -- Clock period definitions constant aclk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity huffman_encoder port map ( aclk => aclk, axi_resetn => axi_resetn, s_axis_tdata => s_axis_tdata, s_axis_tvalid => s_axis_tvalid, s_axis_tready => s_axis_tready, s_axis_tlast => s_axis_tlast, m_axis_tdata => m_axis_tdata, m_axis_tvalid => m_axis_tvalid, m_axis_tready => m_axis_tready, m_axis_tlast => m_axis_tlast ); -- Clock process definitions clk_p: process begin aclk <= '0'; wait for aclk_period/2; aclk <= '1'; wait for aclk_period/2; end process; -- Stimulus process axi_master_p: process variable symbol_idx : natural; type t_symbol_batch is array(0 to 15) of std_logic_vector(7 downto 0); constant symbol_batch : t_symbol_batch := ( x"62", x"61", x"62", x"61", x"64", x"65", x"64", x"61", x"64", x"65", x"61", x"64", x"62", x"65", x"65", x"66" ); begin wait for aclk_period2; axi_resetn <= '1'; wait for aclk_period; symbol_idx := 0; while symbol_idx <= 15 loop s_axis_tdata <= symbol_batch(symbol_idx); s_axis_tvalid <= '1'; if symbol_idx = 15 then s_axis_tlast <= '1'; else s_axis_tlast <= '0'; end if; -- If slave is ready then symbols is considered sent, -- and we proceed to next symbol. if s_axis_tready = '1' then symbol_idx := symbol_idx + 1; end if; wait for aclk_period; -- Make pause for 3 clock periods. if symbol_idx mod 8 = 5 then s_axis_tvalid <= '0'; wait for aclk_period3; end if; end loop; s_axis_tvalid <= '0'; s_axis_tlast <= '0'; wait for aclk_period*10; println("--------------------------------------"); println("Testbench done!"); println("--------------------------------------"); wait; end process; end architecture arch_huffman_encoder_tb;	mit	13694de662026fced49ec49e8c44afe5	0.556736	3.08486	false	false	false	false
jairov4/accel-oil	solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.vhd	3	9,502	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(16 downto 0); b: in std_logic_vector(16 downto 0); s: out std_logic_vector(16 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is port ( faa : IN STD_LOGIC_VECTOR (5-1 downto 0); fab : IN STD_LOGIC_VECTOR (5-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (5-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (2-1 downto 0); fab : IN STD_LOGIC_VECTOR (2-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (2-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(16 downto 0); signal b_reg : std_logic_vector(16 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(4 downto 0); signal b0_cb : std_logic_vector(4 downto 0); signal a1_cb : std_logic_vector(9 downto 5); signal b1_cb : std_logic_vector(9 downto 5); signal a2_cb : std_logic_vector(14 downto 10); signal b2_cb : std_logic_vector(14 downto 10); signal a3_cb : std_logic_vector(16 downto 15); signal b3_cb : std_logic_vector(16 downto 15); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; -- wires for each full adder sum signal fas : std_logic_vector(16 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0); signal s0_ca_rego0 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal s1_ca_rego1 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal s2_ca_rego2 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(16 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(4 downto 0); b0_cb <= b_reg(4 downto 0); a1_cb <= a_reg(9 downto 5); b1_cb <= b_reg(9 downto 5); a2_cb <= a_reg(14 downto 10); b2_cb <= b_reg(14 downto 10); a3_cb <= a_reg(16 downto 15); b3_cb <= b_reg(16 downto 15); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(4 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(9 downto 5), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(14 downto 10), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(16 downto 15), facout => faccout3_co3); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(4 downto 0); s1_ca_rego1 (0) <= fas(9 downto 5); s2_ca_rego2 (0) <= fas(14 downto 10); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s1_ca_rego1 (1) <= s1_ca_rego1 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(4 downto 0) <= s0_ca_rego0(2); s_tmp(9 downto 5) <= s1_ca_rego1(1); s_tmp(14 downto 10) <= s2_ca_rego2(0); s_tmp(16 downto 15) <= fas(16 downto 15); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is generic(N : natural :=5); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is generic(N : natural :=2); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;	lgpl-3.0	9ee1d0cac8bbe1c27af5f88eb52b8429	0.608293	2.864637	false	false	false	false
MrDoomBringer/DSD-Labs	Lab 4/name_detector.vhd	1	1,073	LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY name_detector IS PORT ( b6, a, b, c, d, e: IN STD_LOGIC; first_cond, last_cond, first_sel, last_sel: OUT STD_LOGIC); END name_detector; ARCHITECTURE selective_name OF name_detector IS SIGNAL inputs: STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN inputs <= b6 & a & b & c & d & e; WITH inputs SELECT first_sel <= '1' WHEN "100011" \| "100110" \| "101100" \| "101001", '0' WHEN OTHERS; WITH inputs SELECT last_sel <= '1' WHEN "100001" \| "100011" \| "101101" \| "101110" \| "101000" \| "110000", '0' WHEN OTHERS; first_cond <= '1' WHEN inputs = "100011" ELSE '1' WHEN inputs = "100110" ELSE '1' WHEN inputs = "101100" ELSE '1' WHEN inputs = "101001" ELSE '0'; last_cond <= '1' WHEN inputs = "100001" ELSE '1' WHEN inputs = "100011" ELSE '1' WHEN inputs = "101101" ELSE '1' WHEN inputs = "101110" ELSE '1' WHEN inputs = "101000" ELSE '1' WHEN inputs = "110000" ELSE '0'; END selective_name;	mit	200c4b07b220ce34cb1c27771e6cf0c2	0.586207	2.853723	false	false	false	false
wsoltys/AtomFpga	src/AVR8/Memory/XDM32Kx8.vhd	1	2,088	--********************************************************************************************** -- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx) -- Version 0.1 -- Designed by Ruslan Lepetenok -- Modified 29.10.2005 --******************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For Synplicity Synplify --library virtexe; --use virtexe.components.all; -- Aldec library unisim; use unisim.vcomponents.all; entity XDM32Kx8 is port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(14 downto 0); din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); we : in std_logic ); end XDM32Kx8; architecture RTL of XDM32Kx8 is type RAMBlDOut_Type is array(2(address'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector(2(address'length-9)-1 downto 0); signal cp2n : std_logic; signal gnd : std_logic; begin gnd <= '0'; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0'; end generate ; RAM_Inst:for i in 0 to 2(address'length-9)-1 generate RAM_Byte:component RAMB4_S8 port map( DO => RAMBlDOut(i)(7 downto 0), ADDR => address(8 downto 0), DI => din(7 downto 0), EN => ce, CLK => cp2, WE => WEB(i), RST => gnd ); end generate; -- Output data mux dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9))); end RTL;	apache-2.0	2901724ab805feab15c1fe5dc21b37cd	0.440134	3.939623	false	false	false	false
jairov4/accel-oil	impl/impl_test_pcie/simulation/behavioral/system_lmb_bram_wrapper.vhd	1	2,663	------------------------------------------------------------------------------- -- system_lmb_bram_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_elaborate_v1_00_a; use lmb_bram_elaborate_v1_00_a.all; entity system_lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end system_lmb_bram_wrapper; architecture STRUCTURE of system_lmb_bram_wrapper is component lmb_bram_elaborate is generic ( C_MEMSIZE : integer; C_PORT_DWIDTH : integer; C_PORT_AWIDTH : integer; C_NUM_WE : integer; C_FAMILY : string ); port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1) ); end component; begin lmb_bram : lmb_bram_elaborate generic map ( C_MEMSIZE => 16#1000#, C_PORT_DWIDTH => 32, C_PORT_AWIDTH => 32, C_NUM_WE => 4, C_FAMILY => "virtex5" ) port map ( BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, BRAM_Rst_B => BRAM_Rst_B, BRAM_Clk_B => BRAM_Clk_B, BRAM_EN_B => BRAM_EN_B, BRAM_WEN_B => BRAM_WEN_B, BRAM_Addr_B => BRAM_Addr_B, BRAM_Din_B => BRAM_Din_B, BRAM_Dout_B => BRAM_Dout_B ); end architecture STRUCTURE;	lgpl-3.0	f6387af42a506d758fb28df75d920b7c	0.558768	2.910383	false	false	false	false
grwlf/vsim	vhdl_ct/ct00496.vhd	1	10,355	------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00496 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (6) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00496(ARCH00496) -- ENT00496_Test_Bench(ARCH00496_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00496 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00496 ; -- architecture ARCH00496 of ENT00496 is begin B1 : block signal s_arr_1 : st_arr_1 ; signal s_time_matrix : st_time_matrix ; signal s_bit_vector : st_bit_vector ; signal s_string : st_string ; signal s_rec_1 : rec_1 ; signal toggle : boolean := false ; procedure p1 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- variable v_arr_1 : st_arr_1 ; variable v_time_matrix : st_time_matrix ; variable v_bit_vector : st_bit_vector ; variable v_string : st_string ; variable v_rec_1 : rec_1 ; variable bool : boolean := true ; -- begin v_arr_1 := ( others => (others => c_rec_1_1) ) ; v_time_matrix := ( others => (others => 15ms) ) ; v_bit_vector := ( others => '0' ) ; v_string := ( others => 'a' ) ; v_rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in signal assignment" & " (dynamic)" , bool ) ; end p1 ; -- begin process variable v_arr_1 : st_arr_1 ; variable v_time_matrix : st_time_matrix ; variable v_bit_vector : st_bit_vector ; variable v_string : st_string ; variable v_rec_1 : rec_1 ; variable bool : boolean := true ; -- begin s_arr_1 <= ( others => (others => c_rec_1_1) ) ; for i in 2 to 5 loop s_arr_1 (false, i) <= c_rec_1_2; end loop; s_time_matrix <= ( others => (others => 5 fs) ) ; s_time_matrix (0, -3) <= 10 ns; s_bit_vector <= ( others => '0' ) ; s_bit_vector (g_c1) <= '1'; s_bit_vector (g_c1+2) <= '1'; s_string <= "ab0" ; s_rec_1 <= -- ( f2 => (others => false), others => 0) ; ( others => 0) ; s_rec_1.f3 <= 1; toggle <= true ; v_arr_1 := ( others => (others => c_rec_1_1) ) ; v_time_matrix := ( others => (others => 15ms) ) ; v_bit_vector := ( others => '0' ) ; v_string := ( others => 'a' ) ; v_rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in signal assignment" & " (globally static)" , bool ) ; wait ; end process ; process ( toggle ) variable bool : boolean := true ; begin if toggle then bool := bool and s_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and s_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and s_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and s_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and s_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and s_bit_vector = B"10100" ; -- bool := bool and s_string = "ab0" ; -- bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0 and s_rec_1.f3 = 1 ; -- bool := bool and s_rec_1.f2(1) = true -- and s_rec_1.f2(0) = false and -- s_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in variable assignment" & " (globally static)" , bool ) ; end if ; p1 ( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; end process ; end block B1 ; end ARCH00496 ; -- entity ENT00496_Test_Bench is end ENT00496_Test_Bench ; -- architecture ARCH00496_Test_Bench of ENT00496_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00496 ( ARCH00496 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00496_Test_Bench ;	gpl-3.0	66143fca6efd33ce54e0375adc69f93f	0.461709	3.345719	false	false	false	false
grwlf/vsim	vhdl_ct/ct00286.vhd	1	2,562	-- NEED RESULT: ARCH00286: Integer types and predefined integer types passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00286 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 3.1.2 (1) -- 3.1.2 (2) -- 3.1.2 (3) -- 3.1.2.1 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00286) -- ENT00286_Test_Bench(ARCH00286_Test_Bench) -- -- REVISION HISTORY: -- -- 22-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00286 of E00000 is -- these will test 3.1.2 (2) type negative_integers is range -2147483647 to 0 ; type positive_integers is range 0 to +2147483647 ; type all_integers is range -2147483647 to +2147483647 ; -- this tests 3.1.2 (3) type backward_integers is range +2147483647 downto -2147483647 ; -- these will test 3.1.2 (1) type signed_byte is range -128 to +127 ; type signed_nibble is range -8 to +7 ; type signed_something is range signed_nibble'left to signed_byte'right ; begin P : process begin test_report ( "ARCH00286" , "Integer types and predefined integer types" , (negative_integers'left = -2147483647) and (negative_integers'right = 0) and (positive_integers'left = 0) and (positive_integers'right = +2147483647) and (all_integers'left = -2147483647) and (all_integers'right = +2147483647) and (backward_integers'left = +2147483647) and (backward_integers'right = -2147483647) and (signed_byte'left = -128) and (signed_byte'right = +127) and (signed_nibble'left = -8) and (signed_nibble'right = +7) and (signed_something'left = -8) and (signed_something'right = +127) and (integer'left <= -2147483647) and -- test 3.1.2.1 (1) (integer'right >= +2147483647) ) ; wait ; end process P ; end ARCH00286 ; entity ENT00286_Test_Bench is end ENT00286_Test_Bench ; architecture ARCH00286_Test_Bench of ENT00286_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00286 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00286_Test_Bench ;	gpl-3.0	bcd75882b1905557d658b5dc20a72e05	0.556206	3.45749	false	true	false	false
MrDoomBringer/DSD-Labs	Lab 9/vendi.vhd	1	4,597	-- FPGA Clock Circuit for Altera DE-2 board -- Cliff Chapman -- 11/04/2013 -- -- Lab 9 - Digital Systems Design LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY vendi IS PORT ( -- Coins input nickel_in : IN STD_LOGIC; dime_in : IN STD_LOGIC; quarter_in : IN STD_LOGIC; -- User actions dispense : IN STD_LOGIC; coin_return : IN STD_LOGIC; -- Machine data clk : IN STD_LOGIC; rst : IN STD_LOGIC := '1'; -- LED dispense status change_back : OUT STD_LOGIC; red_bull : OUT STD_LOGIC; -- Coin amount displays HEX0_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX1_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END vendi; ARCHITECTURE a OF vendi IS COMPONENT sevenseg_bcd_display PORT ( r : IN STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; SIGNAL coin_val : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Build an enumerated type for the state machine -- This feels like a GREAT way to screw yourself over with -- overloading common names. Maybe that's just me. -- Either way that's why we have the _s hungarian postfix on these. TYPE state_type IS ( idle_s, nickle_s, dime_s, quarter_s , enough_s, excess_s, vend_s, change_s ); -- Register to hold the current state SIGNAL state : state_type; BEGIN -- Display output of current coin value display : sevenseg_bcd_display PORT MAP ( r => coin_val, s => '1', HEX2 => OPEN, HEX1 => HEX1_disp, HEX0 => HEX0_disp ); state_monitor : PROCESS (rst, clk) BEGIN IF (rst = '0') THEN state <= idle_s; ELSIF (rising_edge(clk)) THEN CASE state IS -- IDLE STATE WHEN idle_s => IF (nickel_in = '1') THEN state <= nickle_s; ELSIF (dime_in = '1') THEN state <= dime_s; ELSIF (quarter_in = '1') THEN state <= quarter_s; ELSIF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; -- Coins states WHEN nickle_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; WHEN dime_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; WHEN quarter_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; -- Enough money WHEN enough_s => IF (coin_return = '1') THEN state <= change_s; ELSIF (dispense = '1') THEN state <= vend_s; ELSIF (nickel_in = '1') THEN state <= excess_s; ELSIF (dime_in = '1') THEN state <= excess_s; ELSIF (quarter_in = '1') THEN state <= excess_s; ELSE state <= enough_s; END IF; -- Too much money (Display may overload, can store up to 255 cents) -- TODO: add auto-return dump for values over 2 dollars? WHEN excess_s => IF (coin_return = '1') THEN state <= change_s; ELSIF (dispense = '1') THEN state <= vend_s; -- Coin block again ELSIF (nickel_in = '1') THEN state <= excess_s; ELSIF (dime_in = '1') THEN state <= excess_s; ELSIF (quarter_in = '1') THEN state <= excess_s; ELSE state <= excess_s; END IF; WHEN vend_s => IF (coin_val = "00000000") THEN state <= idle_s; ELSIF (coin_val > "00000000") THEN state <= change_s; END IF; WHEN OTHERS => state <= idle_s; END CASE; END IF; END PROCESS state_monitor; PROCESS (state) BEGIN IF (state = vend_s) THEN red_bull <= '1'; ELSE red_bull <= '0'; END IF; IF (state = change_s) THEN change_back <= '1'; ELSIF (state = excess_s) THEN change_back <= '1'; ELSE change_back <= '0'; END IF; END PROCESS; state_output : PROCESS (state, clk, rst) VARIABLE coin_cnt : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000"; BEGIN IF (rst = '0') THEN coin_cnt := "00000000"; ELSIF (rising_edge(clk) AND rst = '1') THEN CASE state IS WHEN nickle_s => coin_cnt := coin_cnt + "00000101"; WHEN dime_s => coin_cnt := coin_cnt + "00001010"; WHEN quarter_s => coin_cnt := coin_cnt + "00011001"; WHEN vend_s => coin_cnt := coin_cnt - "01001011"; WHEN change_s => coin_cnt := "00000000"; WHEN OTHERS => coin_cnt := coin_cnt; END CASE; ELSE coin_cnt := coin_cnt; END IF; coin_val <= coin_cnt; END PROCESS state_output; END ARCHITECTURE;	mit	f706701c5f0a649294f83c32ea40e09c	0.583206	2.864174	false	false	false	false
grwlf/vsim	vhdl_ct/ct00160.vhd	1	25,015	-- NEED RESULT: ARCH00160.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Inertial transactions entirely completed passed -- NEED RESULT: P2: Inertial transactions entirely completed passed -- NEED RESULT: P1: Inertial transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00160 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- ENT00160(ARCH00160) -- ENT00160_Test_Bench(ARCH00160_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00160 is port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- -- procedure Proc1 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P1" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_1(highb) ( st_arr1'Right) after 100 ns; -- when 5 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 6 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns; -- when 7 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_st_arr2_vector : inout st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P2" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_st_arr3_vector : inout st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P3" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- -- end ENT00160 ; -- architecture ARCH00160 of ENT00160 is begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_st_arr1_vector, counter, correct, savtime, chk_st_arr1_vector ) ; wait until (not s_st_arr1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_st_arr1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_st_arr2_vector, counter, correct, savtime, chk_st_arr2_vector ) ; wait until (not s_st_arr2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_st_arr3_vector, counter, correct, savtime, chk_st_arr3_vector ) ; wait until (not s_st_arr3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- -- end ARCH00160 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00160_Test_Bench is signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00160_Test_Bench ; -- architecture ARCH00160_Test_Bench of ENT00160_Test_Bench is begin L1: block component UUT port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00160 ( ARCH00160 ) ; begin CIS1 : UUT port map ( s_st_arr1_vector , s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00160_Test_Bench ;	gpl-3.0	04f35e81b40a69b948179a8ba3a41eff	0.491585	3.565422	false	false	false	false
grwlf/vsim	vhdl_ct/ct00616.vhd	1	48,823	-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00616 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00616(ARCH00616) -- ENT00616_Test_Bench(ARCH00616_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00616 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; -- end ENT00616 ; -- -- architecture ARCH00616 of ENT00616 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; -- procedure P1 (signal s_st_boolean_vector : in st_boolean_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns, -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_boolean_vector_cnt + 1 ; -- end ; -- procedure P2 (signal s_st_severity_level_vector : in st_severity_level_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_severity_level_vector_cnt + 1 ; -- end ; -- procedure P3 (signal s_st_string : in st_string ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns, -- c_st_string_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_string_cnt + 1 ; -- end ; -- procedure P4 (signal s_st_enum1_vector : in st_enum1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_enum1_vector_cnt + 1 ; -- end ; -- procedure P5 (signal s_st_integer_vector : in st_integer_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns, -- c_st_integer_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_integer_vector_cnt + 1 ; -- end ; -- procedure P6 (signal s_st_time_vector : in st_time_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns, -- c_st_time_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_time_vector_cnt + 1 ; -- end ; -- procedure P7 (signal s_st_real_vector : in st_real_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_real_vector_cnt + 1 ; -- end ; -- procedure P8 (signal s_st_rec1_vector : in st_rec1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec1_vector_cnt + 1 ; -- end ; -- procedure P9 (signal s_st_arr2_vector : in st_arr2_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns, -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_vector_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_boolean_vector , st_boolean_vector_select , s_st_boolean_vector_savt , chk_st_boolean_vector , s_st_boolean_vector_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb to highb-1) <= transport c_st_boolean_vector_2(lowb to highb-1) after 10 ns, c_st_boolean_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG2 : P2( s_st_severity_level_vector , st_severity_level_vector_select , s_st_severity_level_vector_savt , chk_st_severity_level_vector , s_st_severity_level_vector_cnt ) ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb to highb-1) <= transport c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, c_st_severity_level_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG3 : P3( s_st_string , st_string_select , s_st_string_savt , chk_st_string , s_st_string_cnt ) ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb-1 to highb-1) <= transport c_st_string_2(highb-1 to highb-1) after 10 ns, c_st_string_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG4 : P4( s_st_enum1_vector , st_enum1_vector_select , s_st_enum1_vector_savt , chk_st_enum1_vector , s_st_enum1_vector_cnt ) ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb-1 to highb-1) <= transport c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG5 : P5( s_st_integer_vector , st_integer_vector_select , s_st_integer_vector_savt , chk_st_integer_vector , s_st_integer_vector_cnt ) ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb to highb-1) <= transport c_st_integer_vector_2(lowb to highb-1) after 10 ns, c_st_integer_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG6 : P6( s_st_time_vector , st_time_vector_select , s_st_time_vector_savt , chk_st_time_vector , s_st_time_vector_cnt ) ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb to highb-1) <= transport c_st_time_vector_2(lowb to highb-1) after 10 ns, c_st_time_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG7 : P7( s_st_real_vector , st_real_vector_select , s_st_real_vector_savt , chk_st_real_vector , s_st_real_vector_cnt ) ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb-1 to highb-1) <= transport c_st_real_vector_2(highb-1 to highb-1) after 10 ns, c_st_real_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG8 : P8( s_st_rec1_vector , st_rec1_vector_select , s_st_rec1_vector_savt , chk_st_rec1_vector , s_st_rec1_vector_cnt ) ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb-1 to highb-1) <= transport c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG9 : P9( s_st_arr2_vector , st_arr2_vector_select , s_st_arr2_vector_savt , chk_st_arr2_vector , s_st_arr2_vector_cnt ) ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb to highb-1) <= transport c_st_arr2_vector_2(lowb to highb-1) after 10 ns, c_st_arr2_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ; -- end ARCH00616 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00616_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; -- end ENT00616_Test_Bench ; -- -- architecture ARCH00616_Test_Bench of ENT00616_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00616 ( ARCH00616 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector ) ; end block L1 ; end ARCH00616_Test_Bench ;	gpl-3.0	6992b2d913b5fbed0c0ca0c14e908f9e	0.538701	3.452585	false	true	false	false
takeshineshiro/fpga_fibre_scan	HUCB2P0_150701/driver/pll_conf.vhd	1	13,329	--*************************************************************************** -- @Copyright All rights reserved. -- Module name : adc_conf -- Call by : -- Description : Configuration for AD9518-3, read datasheet for reference -- IC : -- Version : A -- Note: : -- -- Author : Weibao Qiu -- Date : 2010.08 -- Update : -- --*************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity pll_conf is port ( I_clk : in std_logic; I_reset_n : in std_logic; O_ADC_ready : out std_logic; O_FPGA_ADC_d : out std_logic; O_FPGA_ADC_clk : out std_logic; O_FPGA_ADC_en : out std_logic; O_FPGA_ADC_reset : out std_logic ); end pll_conf; architecture rtl of pll_conf is component pll_intf is port ( I_clk : in std_logic; I_reset_n : in std_logic; I_ADC_data : in std_logic_vector(23 downto 0); O_ADC_ready : out std_logic; I_ADC_trig : in std_logic; O_FPGA_ADC_d : out std_logic; O_FPGA_ADC_clk : out std_logic; O_FPGA_ADC_en : out std_logic; O_FPGA_ADC_reset : out std_logic ); end component pll_intf; signal S_ADC_trig : std_logic; signal S_adc_cnt : std_logic_vector(4 downto 0); signal S_ADC_data : std_logic_vector(23 downto 0); signal S_ADC_ready : std_logic; signal S_ADC_ready_1buf : std_logic; signal S_ADC_ready_2buf : std_logic; signal S_ADC_ready_3buf : std_logic; signal S_ADC_ready_4buf : std_logic; signal S_data_start : std_logic; signal S_data_finish : std_logic; signal s_delay_cn : std_logic_vector(31 downto 0); signal s_delay_symbol : std_logic; constant C_DATA_NUMBER : std_logic_vector := "10111"; --The total number of data to be setted, plus 1 is the actual amount because of 0 start constant C_N0 : std_logic_vector := "00000"; constant C_N1 : std_logic_vector := "00001"; constant C_N2 : std_logic_vector := "00010"; constant C_N3 : std_logic_vector := "00011"; constant C_N4 : std_logic_vector := "00100"; constant C_N5 : std_logic_vector := "00101"; constant C_N6 : std_logic_vector := "00110"; constant C_N7 : std_logic_vector := "00111"; constant C_N8 : std_logic_vector := "01000"; constant C_N9 : std_logic_vector := "01001"; constant C_N10 : std_logic_vector := "01010"; constant C_N11 : std_logic_vector := "01011"; constant C_N12 : std_logic_vector := "01100"; constant C_N13 : std_logic_vector := "01101"; constant C_N14 : std_logic_vector := "01110"; constant C_N15 : std_logic_vector := "01111"; constant C_N16 : std_logic_vector := "10000"; constant C_N17 : std_logic_vector := "10001"; constant C_N18 : std_logic_vector := "10010"; constant C_N19 : std_logic_vector := "10011"; constant C_N20 : std_logic_vector := "10100"; constant C_N21 : std_logic_vector := "10101"; constant C_N22 : std_logic_vector := "10110"; constant C_N23 : std_logic_vector := "10111"; constant C_N24 : std_logic_vector := "11000"; begin O_ADC_ready <= S_ADC_ready; U0 : pll_intf port map ( I_clk => I_clk , I_reset_n => I_reset_n , I_ADC_data => S_ADC_data , O_ADC_ready => S_ADC_ready , I_ADC_trig => S_ADC_trig , O_FPGA_ADC_d => O_FPGA_ADC_d , O_FPGA_ADC_clk => O_FPGA_ADC_clk , O_FPGA_ADC_en => O_FPGA_ADC_en , O_FPGA_ADC_reset => O_FPGA_ADC_reset ); ------------------- --prepare the sending data ------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_ADC_data <= (others => '0'); S_ADC_trig <= '0'; elsif(I_clk'event and I_clk = '1')then if(S_data_start = '1') and (S_data_finish = '0') then S_ADC_trig <= '1'; case S_adc_cnt is when C_N0 => S_ADC_data <= "0000" & x"000" & "10111101"; --reg 0x000 Serial port configuration --Soft reset, delay when C_N1 => S_ADC_data <= "0000" & x"000" & "10011001"; when C_N2 => S_ADC_data <= "0000" & x"010" & "01111100"; --PLL normal when C_N3 => S_ADC_data <= "0000" & x"018" & "00000111"; --reg 0x018, calibration set when C_N4 => S_ADC_data <= "0000" & x"011" & "00000001"; --reg 0x011 14-bit R divider, Bits[7:0] (LSB) when C_N5 => S_ADC_data <= "0000" & x"014" & "00011110"; --reg 0x014 B counter Bits[7:0] (LSB) --S_ADC_data <= "0000" & x"014" & "00101101"; when C_N6 => S_ADC_data <= "0000" & x"016" & "00000100"; --reg 0x016 PLL Control 1, DM mode, divide by 8 --S_ADC_data <= "0000" & x"016" & "00000011"; when C_N7 => S_ADC_data <= "0000" & x"017" & "10011100"; --set STATUS to monitor the REF1 state, good output high, HL2 light when C_N8 => S_ADC_data <= "0000" & x"01C" & "00000010"; --ref1 power on when C_N9 => -- S_ADC_data <= "0000" & x"0F0" & "00000011"; --reg 0x0F1 output 0, off S_ADC_data <= "0000" & x"0F0" & "00001100"; --reg 0x0F1 output 0, on when C_N10 => S_ADC_data <= "0000" & x"0F1" & "00000011"; --reg 0x0F1 output 1, off when C_N11 => -- S_ADC_data <= "0000" & x"0F2" & "00000011"; --reg 0x0F2 output 2, off S_ADC_data <= "0000" & x"0F2" & "00001100"; --reg 0x0F2 output 2, on when C_N12 => S_ADC_data <= "0000" & x"0F3" & "00000011"; --reg 0x0F3 output 3, off when C_N13 => S_ADC_data <= "0000" & x"0F4" & "00001100"; --reg 0x0F4 output 4, on when C_N14 => S_ADC_data <= "0000" & x"0F5" & "00000011"; --reg 0x0F5 output 5, off when C_N15 => S_ADC_data <= "0000" & x"191" & "00000000"; --reg 0x191 OUTPUT0 use divider, 0+0+2 --S_ADC_data <= "0000" & x"191" & "10000000"; -- Bypass divider --for 600MHz output when C_N16 => S_ADC_data <= "0000" & x"193" & "00000000"; --reg 0x193 OUTPUT1 divide by 2, 0+0+2 --S_ADC_data <= "0000" & x"194" & "10000000"; --194 bypass divider, when C_N17 => S_ADC_data <= "0000" & x"1E0" & "00000011"; --reg 0x1E0, divide by 5 --S_ADC_data <= "0000" & x"1E0" & "00000001"; when C_N18 => S_ADC_data <= "0000" & x"1E1" & "00000010"; --Internal PLL --S_ADC_data <= "0000" & x"1E1" & "00000001"; --External clk when C_N19 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register when C_N20 => S_ADC_data <= "0000" & x"018" & "00000110"; --reg 0x018 when C_N21 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register --Wait for calibration, delay when C_N22 => S_ADC_data <= "0000" & x"018" & "00000111"; --reg 0x018 when C_N23 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register --Wait for calibration finish, delay when C_N24 => S_ADC_data <= "1000" & x"01F" & "00000100"; when others => S_ADC_data <= (others => '0'); end case; else S_ADC_data <= (others => '0'); S_ADC_trig <= '0'; end if; end if; end process; -------------------------------------------------------------------------------------------------- --Control the start of sending data and the delay -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_ADC_ready_1buf <= '0'; S_ADC_ready_2buf <= '0'; S_ADC_ready_3buf <= '0'; S_ADC_ready_4buf <= '0'; S_adc_cnt <= (others => '1'); S_data_start <= '0'; S_data_finish <= '0'; s_delay_cn <= (others => '0'); s_delay_symbol <= '0'; elsif(I_clk'event and I_clk = '1')then if (S_data_finish = '0') then s_delay_cn <= s_delay_cn + '1'; S_ADC_ready_4buf <= S_ADC_ready_3buf; S_ADC_ready_3buf <= S_ADC_ready_2buf; S_ADC_ready_2buf <= S_ADC_ready_1buf; S_ADC_ready_1buf <= S_ADC_ready; if(S_ADC_ready_2buf = '0')and (S_ADC_ready_1buf = '1')then --rising edge0 if (S_adc_cnt = C_DATA_NUMBER)then --Count the number of data to be sent S_data_finish <= '1'; S_adc_cnt <= (others => '0'); elsif(S_adc_cnt = C_N0 or S_adc_cnt = C_N21 or S_adc_cnt = C_N23)then --There is a delay after this value, set 4 means 5 data are sent s_delay_cn <= (others => '0'); s_delay_symbol <= '1'; else S_data_finish <= '0'; S_data_start <= '1'; S_adc_cnt <= S_adc_cnt + '1'; end if; elsif(S_ADC_ready_4buf = '0')and (S_ADC_ready_3buf = '1')then S_data_start <= '0'; elsif(s_delay_symbol = '1' and s_delay_cn = 500000)then --Delay 10ms to wait proper setting S_data_start <= '1'; s_delay_symbol <= '0'; S_adc_cnt <= S_adc_cnt + '1'; elsif(S_data_start = '1' and s_delay_cn = 500002)then --Two cycles for start S_data_start <= '0'; end if; else S_ADC_ready_1buf <= '0'; S_ADC_ready_2buf <= '0'; S_ADC_ready_3buf <= '0'; S_ADC_ready_4buf <= '0'; S_adc_cnt <= (others => '0'); end if; end if; end process; end rtl;	apache-2.0	1db61d12e1793547494edbbe0b6dce2d	0.370095	3.892815	false	false	false	false
grwlf/vsim	vhdl_ct/pro000019.vhd	1	4,233	-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00016_Test_Bench is end ENT00016_Test_Bench; architecture ARCH00016_Test_Bench of ENT00016_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); signal I_saa_lv : std_array_array; subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b1_lv : byte; signal b2 : byte2 := x"00"; signal b2_lv : byte2; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); signal I_baa_lv : bit_array_array; type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; signal I_sa_lv : std_array; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal e_lv : enum; signal ea : enum_array(0 to 3) := (others => a_v); signal ea_lv : enum_array(0 to 3); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal r_lv : rec; signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal ra_lv : rec_array(0 to 3); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal bv_lv : bit_vector(15 downto 0); signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; signal clk_lv : std_ulogic; signal clk2_lv : std_ulogic; begin clk_lv <= clk'Last_value; clk2_lv <= clk2'Last_value; bv_lv <= bv'Last_value; ra_lv <= ra'Last_value; r_lv <= r'Last_value; ea_lv <= ea'Last_value; e_lv <= e'Last_value; I_sa_lv <= I_sa'Last_value; I_baa_lv <= I_baa'Last_value; I_saa_lv <= I_saa'Last_value; b1_lv <= b1'Last_value; b2_lv <= b2'Last_value; clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00016_Test_Bench ;	gpl-3.0	d8df33bb6ec8ddaa4d237514b1cf23f9	0.551854	2.435558	false	false	false	false
jairov4/accel-oil	solution_spartan6/impl/vhdl/nfa_get_finals.vhd	4	14,969	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_get_finals is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_get_finals is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal nfa_finals_buckets_read_reg_63 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_136 : BOOLEAN; signal ap_sig_bdd_67 : BOOLEAN; signal ap_sig_bdd_135 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it0_preg assign process. -- ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then ap_reg_ppiten_pp0_it0_preg <= ap_start; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then nfa_finals_buckets_read_reg_63 <= nfa_finals_buckets_datain; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it2 , ap_reg_ppiten_pp0_it3 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; end if; when ap_ST_pp0_stg1_fsm_1 => if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; end if; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg) begin if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then ap_reg_ppiten_pp0_it0 <= ap_start; else ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg; end if; end process; ap_return_0 <= nfa_finals_buckets_read_reg_63; ap_return_1 <= nfa_finals_buckets_datain; -- ap_sig_bdd_135 assign process. -- ap_sig_bdd_135_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce) begin ap_sig_bdd_135 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_136 assign process. -- ap_sig_bdd_136_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_136 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))); end process; -- ap_sig_bdd_67 assign process. -- ap_sig_bdd_67_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_67 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_address assign process. -- nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_136, ap_sig_bdd_67, ap_sig_bdd_135) begin if (ap_sig_bdd_135) then if (ap_sig_bdd_67) then nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0); elsif (ap_sig_bdd_136) then nfa_finals_buckets_address <= ap_const_lv32_0; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_dataout <= ap_const_lv32_0; nfa_finals_buckets_req_din <= ap_const_logic_0; -- nfa_finals_buckets_req_write assign process. -- nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_req_write <= ap_const_logic_1; else nfa_finals_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_rsp_read assign process. -- nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_rsp_read <= ap_const_logic_1; else nfa_finals_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_finals_buckets_size <= ap_const_lv32_1; end behav;	lgpl-3.0	d0e6bbcd60cfed50cf91043ac210dcb5	0.595497	2.69275	false	false	false	false
wsoltys/AtomFpga	src/AtomGodilVideo/src/mouse/ps2interface.vhd	1	32,429	------------------------------------------------------------------------ -- ps2interface.vhd ------------------------------------------------------------------------ -- Author : Ulrich Zoltn -- Copyright 2006 Digilent, Inc. ------------------------------------------------------------------------ -- Software version : Xilinx ISE 7.1.04i -- WebPack -- Device : 3s200ft256-4 ------------------------------------------------------------------------ -- This file contains the implementation of a generic bidirectional -- ps/2 interface. ------------------------------------------------------------------------ -- Behavioral description ------------------------------------------------------------------------ -- Please read the following article on the web for understanding how -- the ps/2 protocol works. -- http://www.computer-engineering.org/ps2protocol/ -- This module implements a generic bidirectional ps/2 interface. It can -- be used with any ps/2 compatible device. It offers its clients a -- convenient way to exchange data with the device. The interface -- transparently wraps the byte to be sent into a ps/2 frame, generates -- parity for byte and sends the frame one bit at a time to the device. -- Similarly, when receiving data from the ps2 device, the interface -- receives the frame, checks for parity, and extract the usefull data -- and forwards it to the client. If an error occurs during receiving -- or sending a byte, the client is informed by settings the err output -- line high. This way, the client can resend the data or can issue -- a resend command to the device. -- The physical ps/2 interface uses 4 lines -- For the 6-pin connector pins are assigned as follows: -- 1 - Data -- 2 - Not Implemented -- 3 - Ground -- 4 - Vcc (+5V) -- 5 - Clock -- 6 - Not Implemented -- The clock line carries the device generated clock which has a -- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle -- it is placed in high impedance. The clock is only generated when -- device is sending or receiving data. -- The Data and Clock lines are both open-collector with pullup -- resistors to Vcc. An "open-collector" interface has two possible -- states: low('0') or high impedance('Z'). -- When device wants to send a byte, it pulls the clock line low and the -- host(i.e. this interfaces) recognizes that the device is sending data -- When the host wants to send data, it maeks a request to send. This -- is done by holding the clock line low for at least 100us, then with -- the clock line low, the data line is brought low. Next the clock line -- is released (placed in high impedance). The devices begins generating -- clock signal on clock line. -- When receiving data, bits are read from the data line (ps2_data) on -- the falling edge of the clock (ps2_clk). When sending data, the -- device reads the bits from the data line on the rising edge of the -- clock. -- A frame for sending a byte is comprised of 11 bits as shown bellow: -- bits 10 9 8 7 6 5 4 3 2 1 0 -- ------------------------------------------------------------- -- \| STOP\| PAR \| D7 \| D6 \| D5 \| D4 \| D3 \| D2 \| D1 \| D0 \| START \| -- ------------------------------------------------------------- -- STOP - stop bit, always '1' -- PAR - parity bit, odd parity for the 8 data bits. -- - select in such way that the number of bits of '1' in the data -- - bits together with parity bit is odd. -- D0-7 - data bits. -- START - start bit, always '0' -- -- Frame is sent bit by bit starting with the least significant bit -- (starting bit) and is received the same way. This is done, when -- receiving, by shifting the frame register to the left when a bit -- is available and placing the bit on data line on the most significant -- bit. This way the first bit sent will reach the least significant bit -- of the frame when all the bits have been received. When sending data -- the least significant bit of the frame is placed on the data line -- and the frame is shifted to the right when another bit needs to be -- sent. During the request to send, when releasing the clock line, -- the device reads the data line and interprets the data on it as the -- first bit of the frame. Data line is low at that time, at this is the -- way the start bit('0') is sent. Because of this, when sending, only -- 10 shifts of the frame will be made. -- While the interface is sending or receiving data, the busy output -- signal goes high. When interface is idle, busy is low. -- After sending all the bits in the frame, the device must acknowledge -- the data sent. This is done by the host releasing and data line -- (clock line is already released) after the last bit is sent. The -- devices brings the data line and the clock line low, in this order, -- to acknowledge the data. If data line is high when clock line goes -- low after last bit, the device did not acknowledge the data and -- err output is set. -- A FSM is used to manage the transitions the set all the command -- signals. States that begin with "rx_" are used to receive data -- from device and states begining with "tx_" are used to send data -- to the device. -- For the parity bit, a ROM holds the parity bit for all possible -- data (256 possible values, since 8 bits of data). The ROM has -- dimensions 256x1bit. For obtaining the parity bit of a value, -- the bit at the data value address is read. Ex: to find the parity -- bit of 174, the bit at address 174 is read. -- For generating the necessary delay, counters are used. For example, -- to generate the 100us delay a 14 bit counter is used that has the -- upper limit for counting 10000. The interface is designed to run -- at 100MHz. Thus, 10000x10ns = 100us. ----------------------------------------------------------------------- -- If using the interface at different frequency than 100MHz, adjusting -- the delay counters is necessary!!! ----------------------------------------------------------------------- -- Clock line(ps2_clk) and data line(ps2_data) are passed through a -- debouncer for the transitions of the clock and data to be clean. -- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized -- value of the clock and data line to the system clock(clk). ------------------------------------------------------------------------ -- Port definitions ------------------------------------------------------------------------ -- ps2_clk - inout pin, clock line of the ps/2 interface -- ps2_data - inout pin, clock line of the ps/2 interface -- clk - input pin, system clock signal -- rst - input pin, system reset signal -- tx_data - input pin, 8 bits, from client -- - data to be sent to the device -- write - input pin, from client -- - should be active for one clock period when then -- - client wants to send data to the device and -- - data to be sent is valid on tx_data -- rx_data - output pin, 8 bits, to client -- - data received from device -- read - output pin, to client -- - active for one clock period when new data is -- - available from device -- busy - output pin, to client -- - active while sending or receiving data. -- err - output pin, to client -- - active for one clock period when an error occurred -- - during sending or receiving. ------------------------------------------------------------------------ -- Revision History: -- 09/18/2006(UlrichZ): created ------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- simulation library library UNISIM; --use UNISIM.VComponents.all; -- the ps2interface entity declaration -- read above for behavioral description and port definitions. entity ps2interface is generic ( MainClockSpeed : integer ); port( ps2_clk : inout std_logic; ps2_data : inout std_logic; clk : in std_logic; rst : in std_logic; tx_data : in std_logic_vector(7 downto 0); write : in std_logic; rx_data : out std_logic_vector(7 downto 0); read : out std_logic; busy : out std_logic; err : out std_logic ); -- forces the extraction of distributed ram for -- the parityrom memory. -- please remove if block ram is preffered. attribute rom_extract : string; attribute rom_extract of ps2interface: entity is "yes"; attribute rom_style : string; attribute rom_style of ps2interface: entity is "distributed"; end ps2interface; architecture Behavioral of ps2interface is ------------------------------------------------------------------------ -- CONSTANTS ------------------------------------------------------------------------ -- Values are valid for a 49.152MHz clk. Please adjust for other -- frequencies if necessary! -- upper limit for 100us delay counter. -- 4915 * 20.34ns = 100us --constant DELAY_100US : std_logic_vector(13 downto 0):= "01001100110011"; constant DELAY_100US : std_logic_vector(13 downto 0):= std_logic_vector(to_unsigned(MainClockSpeed * 100 / 1000000, 14)); -- upper limit for 20us delay counter. -- 983 * 20.34ns = 20us -- constant DELAY_20US : std_logic_vector(10 downto 0) := "01111010111"; constant DELAY_20US : std_logic_vector(10 downto 0) := std_logic_vector(to_unsigned(MainClockSpeed * 20 / 1000000, 11)); -- upper limit for 63clk delay counter. constant DELAY_63CLK : std_logic_vector(5 downto 0) := "111111"; -- 63 clock periods -- delay from debouncing ps2_clk and ps2_data signals constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111"; -- number of bits in a frame constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11 -- parity bit position in frame constant PARITY_BIT: positive := 9; -- (odd) parity bit ROM -- Used instead of logic because this way speed is far greater -- 256x1bit rom -- If the odd parity bit for a 8 bits number, x, is needed -- the bit at address x is the parity bit. type ROM is array(0 to 255) of std_logic; constant parityrom : ROM := ( '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1' ); ------------------------------------------------------------------------ -- SIGNALS ------------------------------------------------------------------------ -- 14 bits counter -- max value DELAY_100US -- used to wait 100us signal delay_100us_count: std_logic_vector(13 downto 0) := (others => '0'); -- 11 bits counter -- max value DELAY_20US -- used to wait 20us signal delay_20us_count: std_logic_vector(10 downto 0) := (others => '0'); -- 11 bits counter -- max value DELAY_63CLK -- used to wait 63 clock periods signal delay_63clk_count: std_logic_vector(5 downto 0) := (others => '0'); -- done signal for the couters above -- when a counter reaches max value,the corresponding done signal is set signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic; -- enable signal for 100us delay counter signal delay_100us_counter_enable: std_logic := '0'; -- enable signal for 20us delay counter signal delay_20us_counter_enable : std_logic := '0'; -- enable signal for 63clk delay counter signal delay_63clk_counter_enable: std_logic := '0'; -- synchronzed input for ps2_clk and ps2_data signal ps2_clk_s,ps2_data_s: std_logic := '1'; -- control the output of ps2_clk and ps2_data -- if 1 then corresponding signal (ps2_clk or ps2_data) is -- put in high impedance ('Z'). signal ps2_clk_h,ps2_data_h: std_logic := '1'; -- states of the FSM for controlling the communcation with the device -- states that begin with "rx_" are used when receiving data -- states that begin with "tx_" are used when transmiting data type fsm_state is ( idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready, tx_force_clk_l,tx_bring_data_down,tx_release_clk, tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h, tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack, tx_error_no_ack ); -- the signal that holds the current state of the FSM -- implicitly state is idle. signal state: fsm_state := idle; -- register that holds the frame received or the one to be sent. -- Its contents are shifted in from the bus one bit at a time -- from left to right when receiving data and are shifted on the -- bus (ps2_data) one bit at a time to the right when sending data signal frame: std_logic_vector(10 downto 0) := (others => '0'); -- how many bits have been sent or received. signal bit_count: std_logic_vector(3 downto 0) := (others => '0'); -- when active the bit counter is reset. signal reset_bit_count: std_logic := '0'; -- when active the contents of the frame is shifted to the right -- and the most significant bit of frame is loaded with ps2_data. signal shift_frame: std_logic := '0'; -- parity of the byte that was received from the device. -- must match the parity bit received, else error occurred. signal rx_parity: std_logic := '0'; -- parity bit that is sent with the frame, representing the -- odd parity of the byte currently being sent signal tx_parity: std_logic := '0'; -- when active, frame is loaded with the start bit, data on -- tx_data, parity bit (tx_parity) and stop bit -- this frame will be sent to the device. signal load_tx_data: std_logic := '0'; -- when active bits 8 downto 1 from frame are loaded into -- rx_data register. This is the byte received from the device. signal load_rx_data: std_logic := '0'; -- intermediary signals used to debounce the inputs ps2_clk and ps2_data signal ps2_clk_clean,ps2_data_clean: std_logic := '1'; -- debounce counter for the ps2_clk input and the ps2_data input. signal clk_count,data_count: std_logic_vector(3 downto 0); -- last value on ps2_clk and ps2_data. signal clk_inter,data_inter: std_logic := '1'; begin --------------------------------------------------------------------- -- FLAGS and PS2 CLOCK AND DATA LINES --------------------------------------------------------------------- -- clean ps2_clk signal (debounce) -- note that this introduces a delay in ps2_clk of -- DEBOUNCE_DELAY clocks process(clk) begin if(rising_edge(clk)) then -- if the current bit on ps2_clk is different -- from the last value, then reset counter -- and retain value if(ps2_clk /= clk_inter) then clk_inter <= ps2_clk; clk_count <= (others => '0'); -- if counter reached upper limit, then -- the signal is clean elsif(clk_count = DEBOUNCE_DELAY) then ps2_clk_clean <= clk_inter; -- ps2_clk did not change, but counter did not -- reach limit. Increment counter else clk_count <= clk_count + 1; end if; end if; end process; -- clean ps2_data signal (debounce) -- note that this introduces a delay in ps2_data of -- DEBOUNCE_DELAY clocks process(clk) begin if(rising_edge(clk)) then -- if the current bit on ps2_data is different -- from the last value, then reset counter -- and retain value if(ps2_data /= data_inter) then data_inter <= ps2_data; data_count <= (others => '0'); -- if counter reached upper limit, then -- the signal is clean elsif(data_count = DEBOUNCE_DELAY) then ps2_data_clean <= data_inter; -- ps2_data did not change, but counter did not -- reach limit. Increment counter else data_count <= data_count + 1; end if; end if; end process; -- Synchronize ps2 entries ps2_clk_s <= ps2_clk_clean when rising_edge(clk); ps2_data_s <= ps2_data_clean when rising_edge(clk); -- Assign parity from frame bits 8 downto 1, this is the parity -- that should be received inside the frame on PARITY_BIT position rx_parity <= parityrom(conv_integer(frame(8 downto 1))) when rising_edge(clk); -- The parity for the data to be sent tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk); -- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line -- ('Z' = +5Vcc because of pull-ups) ps2_clk <= 'Z' when ps2_clk_h = '1' else '0'; -- Force ps2_data to '0' if ps2_data_h = '0', else release the line -- ('Z' = +5Vcc because of pull-ups) ps2_data <= 'Z' when ps2_data_h = '1' else '0'; -- Control busy flag. Interface is not busy while in idle state. busy <= '0' when state = idle else '1'; -- reset the bit counter when in idle state. reset_bit_count <= '1' when state = idle else '0'; -- Control shifting of the frame -- When receiving from device, data is read -- on the falling edge of ps2_clk -- When sending to device, data is read by device -- on the rising edge of ps2_clk shift_frame <= '1' when state = rx_down_edge or state = tx_clk_l else '0'; --------------------------------------------------------------------- -- FINITE STATE MACHINE --------------------------------------------------------------------- -- For the current state establish next state -- and give necessary commands manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write,tx_data, bit_count,rx_parity,frame,delay_100us_done, delay_20us_done,delay_63clk_done) begin -- if reset occurs, go to idle state. if(rst = '1') then state <= idle; elsif(rising_edge(clk)) then -- default values for these signals -- ensures signals are reset to default value -- when coditions for their activation are no -- longer applied (transition to other state, -- where signal should not be active) -- Idle value for ps2_clk and ps2_data is 'Z' ps2_clk_h <= '1'; ps2_data_h <= '1'; load_tx_data <= '0'; load_rx_data <= '0'; read <= '0'; err <= '0'; case state is -- wait for the device to begin a transmission -- by pulling the clock line low and go to state -- rx_down_edge or, if write is high, the -- client of this interface wants to send a byte -- to the device and a transition is made to state -- tx_force_clk_l when idle => if(ps2_clk_s = '0') then state <= rx_down_edge; elsif(write = '1') then state <= tx_force_clk_l; else state <= idle; end if; -- ps2_clk is high, check if all the bits have been read -- if, last bit read, check parity, and if parity ok -- load received data into rx_data. -- else if more bits left, then wait for the ps2_clk to -- go low when rx_clk_h => if(bit_count = NUMBITS) then if(not (rx_parity = frame(PARITY_BIT))) then state <= rx_error_parity; else load_rx_data <= '1'; state <= rx_data_ready; end if; elsif(ps2_clk_s = '0') then state <= rx_down_edge; else state <= rx_clk_h; end if; -- data must be read into frame in this state -- the ps2_clk just transitioned from high to low when rx_down_edge => state <= rx_clk_l; -- ps2_clk line is low, wait for it to go high when rx_clk_l => if(ps2_clk_s = '1') then state <= rx_clk_h; else state <= rx_clk_l; end if; -- parity bit received is invalid -- signal error and go back to idle. when rx_error_parity => err <= '1'; state <= idle; -- parity bit received was good -- set read signal for the client to know -- a new byte was received and is available on rx_data when rx_data_ready => read <= '1'; state <= idle; -- the client wishes to transmit a byte to the device -- this is done by holding ps2_clk down for at least 100us -- bringing down ps2_data, wait 20us and then releasing -- the ps2_clk. -- This constitutes a request to send command. -- In this state, the ps2_clk line is held down and -- the counter for waiting 100us is eanbled. -- when the counter reached upper limit, transition -- to tx_bring_data_down when tx_force_clk_l => load_tx_data <= '1'; ps2_clk_h <= '0'; if(delay_100us_done = '1') then state <= tx_bring_data_down; else state <= tx_force_clk_l; end if; -- with the ps2_clk line low bring ps2_data low -- wait for 20us and then go to tx_release_clk when tx_bring_data_down => -- keep clock line low ps2_clk_h <= '0'; -- set data line low -- when clock is released in the next state -- the device will read bit 0 on data line -- and this bit represents the start bit. ps2_data_h <= '0'; -- start bit = '0' if(delay_20us_done = '1') then state <= tx_release_clk; else state <= tx_bring_data_down; end if; -- release the ps2_clk line -- keep holding data line low when tx_release_clk => ps2_clk_h <= '1'; -- must maintain data low, -- otherwise will be released by default value ps2_data_h <= '0'; state <= tx_first_wait_down_edge; -- state is necessary because the clock signal -- is not released instantaneously and, because of debounce, -- delay is even greater. -- Wait 63 clock periods for the clock line to release -- then if clock is low then go to tx_clk_l -- else wait until ps2_clk goes low. when tx_first_wait_down_edge => ps2_data_h <= '0'; if(delay_63clk_done = '1') then if(ps2_clk_s = '0') then state <= tx_clk_l; else state <= tx_first_wait_down_edge; end if; else state <= tx_first_wait_down_edge; end if; -- place the least significant bit from frame -- on the data line -- During this state the frame is shifted one -- bit to the right when tx_clk_l => ps2_data_h <= frame(0); state <= tx_wait_up_edge; -- wait for the clock to go high -- this is the edge on which the device reads the data -- on ps2_data. -- keep holding ps2_data on frame(0) because else -- will be released by default value. -- Check if sent the last bit and if so, release data line -- and go to state that wait for acknowledge when tx_wait_up_edge => ps2_data_h <= frame(0); -- NUMBITS - 1 because first (start bit = 0) bit was read -- when the clock line was released in the request to -- send command (see tx_bring_data_down state). if(bit_count = NUMBITS-1) then ps2_data_h <= '1'; state <= tx_wait_up_edge_before_ack; -- if more bits to send, wait for the up edge -- of ps2_clk elsif(ps2_clk_s = '1') then state <= tx_clk_h; else state <= tx_wait_up_edge; end if; -- ps2_clk is released, wait for down edge -- and go to tx_clk_l when arrived when tx_clk_h => ps2_data_h <= frame(0); if(ps2_clk_s = '0') then state <= tx_clk_l; else state <= tx_clk_h; end if; -- release ps2_data and wait for rising edge of ps2_clk -- once this occurs, transition to tx_wait_ack when tx_wait_up_edge_before_ack => ps2_data_h <= '1'; if(ps2_clk_s = '1') then state <= tx_wait_ack; else state <= tx_wait_up_edge_before_ack; end if; -- wait for the falling edge of the clock line -- if data line is low when this occurs, the -- ack is received -- else if data line is high, the device did not -- acknowledge the transimission when tx_wait_ack => if(ps2_clk_s = '0') then if(ps2_data_s = '0') then -- acknowledge received state <= tx_received_ack; else -- acknowledge not received state <= tx_error_no_ack; end if; else state <= tx_wait_ack; end if; -- wait for ps2_clk to be released together with ps2_data -- (bus to be idle) and go back to idle state when tx_received_ack => if(ps2_clk_s = '1' and ps2_data_s = '1') then state <= idle; else state <= tx_received_ack; end if; -- wait for ps2_clk to be released together with ps2_data -- (bus to be idle) and go back to idle state -- signal error for not receiving ack when tx_error_no_ack => if(ps2_clk_s = '1' and ps2_data_s = '1') then err <= '1'; state <= idle; else state <= tx_error_no_ack; end if; -- if invalid transition occurred, signal error and -- go back to idle state when others => err <= '1'; state <= idle; end case; end if; end process manage_fsm; --------------------------------------------------------------------- -- DELAY COUNTERS --------------------------------------------------------------------- -- Enable the 100us counter only when state is tx_force_clk_l delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0'; -- Counter for a 100us delay -- after done counting, done signal remains active until -- enable counter is reset. delay_100us_counter: process(clk) begin if(rising_edge(clk)) then if(delay_100us_counter_enable = '1') then if(delay_100us_count = (DELAY_100US)) then delay_100us_count <= delay_100us_count; delay_100us_done <= '1'; else delay_100us_count <= delay_100us_count + 1; delay_100us_done <= '0'; end if; else delay_100us_count <= (others => '0'); delay_100us_done <= '0'; end if; end if; end process delay_100us_counter; -- Enable the 20us counter only when state is tx_bring_data_down delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0'; -- Counter for a 20us delay -- after done counting, done signal remains active until -- enable counter is reset. delay_20us_counter: process(clk) begin if(rising_edge(clk)) then if(delay_20us_counter_enable = '1') then if(delay_20us_count = (DELAY_20US)) then delay_20us_count <= delay_20us_count; delay_20us_done <= '1'; else delay_20us_count <= delay_20us_count + 1; delay_20us_done <= '0'; end if; else delay_20us_count <= (others => '0'); delay_20us_done <= '0'; end if; end if; end process delay_20us_counter; -- Enable the 63clk counter only when state is tx_first_wait_down_edge delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0'; -- Counter for a 63 clock periods delay -- after done counting, done signal remains active until -- enable counter is reset. delay_63clk_counter: process(clk) begin if(rising_edge(clk)) then if(delay_63clk_counter_enable = '1') then if(delay_63clk_count = (DELAY_63CLK)) then delay_63clk_count <= delay_63clk_count; delay_63clk_done <= '1'; else delay_63clk_count <= delay_63clk_count + 1; delay_63clk_done <= '0'; end if; else delay_63clk_count <= (others => '0'); delay_63clk_done <= '0'; end if; end if; end process delay_63clk_counter; --------------------------------------------------------------------- -- BIT COUNTER AND FRAME SHIFTING LOGIC --------------------------------------------------------------------- -- counts the number of bits shifted into the frame -- or out of the frame. bit_counter: process(clk) begin if(rising_edge(clk)) then if(reset_bit_count = '1') then bit_count <= (others => '0'); elsif(shift_frame = '1') then bit_count <= bit_count + 1; end if; end if; end process bit_counter; -- shifts frame with one bit to right when shift_frame is acitve -- and loads data into frame from tx_data then load_tx_data is high load_tx_data_into_frame: process(clk) begin if(rising_edge(clk)) then if(load_tx_data = '1') then frame(8 downto 1) <= tx_data; -- byte to send frame(0) <= '0'; -- start bit frame(10) <= '1'; -- stop bit frame(9) <= tx_parity; -- parity bit elsif(shift_frame = '1') then -- shift right 1 bit frame(9 downto 0) <= frame(10 downto 1); -- shift in from the ps2_data line frame(10) <= ps2_data_s; end if; end if; end process load_tx_data_into_frame; -- Loads data from frame into rx_data output when data is ready do_load_rx_data: process(clk) begin if(rising_edge(clk)) then if(load_rx_data = '1') then rx_data <= frame(8 downto 1); end if; end if; end process do_load_rx_data; end Behavioral;	apache-2.0	ed12585bba5504711afad7b97d9f6c44	0.539517	3.957169	false	false	false	false
grwlf/vsim	vhdl_ct/ct00107.vhd	1	11,994	-- NEED RESULT: ARCH00107.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00107 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00107) -- ENT00107_Test_Bench(ARCH00107_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00107 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_rec1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns, c_st_rec1_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P1" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns , c_st_rec1_vector_1(highb).f2 after 20 ns , c_st_rec1_vector_2(highb).f2 after 30 ns , c_st_rec1_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_rec2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns, c_st_rec2_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P2" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns , c_st_rec2_vector_1(highb).f2 after 20 ns , c_st_rec2_vector_2(highb).f2 after 30 ns , c_st_rec2_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_rec3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns, c_st_rec3_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P3" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns , c_st_rec3_vector_1(highb).f2 after 20 ns , c_st_rec3_vector_2(highb).f2 after 30 ns , c_st_rec3_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- -- end ARCH00107 ; -- entity ENT00107_Test_Bench is end ENT00107_Test_Bench ; -- architecture ARCH00107_Test_Bench of ENT00107_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00107 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00107_Test_Bench ;	gpl-3.0	aba916ef8864d61a85d80dca36a1f69c	0.5341	3.676885	false	true	false	false

jairov4/accel-oil

impl/impl_test_pcie/simulation/behavioral/system.vhd

1

472,102

------------------------------------------------------------------------------- -- system.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic; fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0); fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0); fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0); fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0); fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30); fpga_0_SRAM_Mem_CEN_pin : out std_logic; fpga_0_SRAM_Mem_OEN_pin : out std_logic; fpga_0_SRAM_Mem_WEN_pin : out std_logic; fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3); fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic; fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31); fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic; fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic; fpga_0_PCIe_Bridge_RXN_pin : in std_logic; fpga_0_PCIe_Bridge_RXP_pin : in std_logic; fpga_0_PCIe_Bridge_TXN_pin : out std_logic; fpga_0_PCIe_Bridge_TXP_pin : out std_logic; fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic; fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic; fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic ); end system; architecture STRUCTURE of system is component system_microblaze_0_wrapper is port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; INTERRUPT_ADDRESS : in std_logic_vector(0 to 31); INTERRUPT_ACK : out std_logic_vector(0 to 1); EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; WAKEUP : in std_logic_vector(0 to 1); SLEEP : out std_logic; DBG_WAKEUP : out std_logic; LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095); LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095); LOCKSTEP_OUT : out std_logic_vector(0 to 4095); INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to 7); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to 63); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to 63); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to 7); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to 63); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to 63); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector(0 downto 0); M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector(31 downto 0); M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector(0 downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector(0 downto 0); M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector(0 downto 0); M_AXI_IP_RDATA : in std_logic_vector(31 downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector(0 downto 0); M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector(31 downto 0); M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector(0 downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector(0 downto 0); M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector(0 downto 0); M_AXI_DP_RDATA : in std_logic_vector(31 downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector(0 downto 0); M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_IC_WDATA : out std_logic_vector(31 downto 0); M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_WUSER : out std_logic_vector(0 downto 0); M_AXI_IC_BID : in std_logic_vector(0 downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_BUSER : in std_logic_vector(0 downto 0); M_AXI_IC_WACK : out std_logic; M_AXI_IC_ARID : out std_logic_vector(0 downto 0); M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_IC_RID : in std_logic_vector(0 downto 0); M_AXI_IC_RDATA : in std_logic_vector(31 downto 0); M_AXI_IC_RRESP : in std_logic_vector(1 downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_IC_RUSER : in std_logic_vector(0 downto 0); M_AXI_IC_RACK : out std_logic; M_AXI_IC_ACVALID : in std_logic; M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_IC_ACREADY : out std_logic; M_AXI_IC_CRREADY : in std_logic; M_AXI_IC_CRVALID : out std_logic; M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_IC_CDVALID : out std_logic; M_AXI_IC_CDREADY : in std_logic; M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_IC_CDLAST : out std_logic; M_AXI_DC_AWID : out std_logic_vector(0 downto 0); M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_DC_WDATA : out std_logic_vector(31 downto 0); M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_WUSER : out std_logic_vector(0 downto 0); M_AXI_DC_BID : in std_logic_vector(0 downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_BUSER : in std_logic_vector(0 downto 0); M_AXI_DC_WACK : out std_logic; M_AXI_DC_ARID : out std_logic_vector(0 downto 0); M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_DC_RID : in std_logic_vector(0 downto 0); M_AXI_DC_RDATA : in std_logic_vector(31 downto 0); M_AXI_DC_RRESP : in std_logic_vector(1 downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; M_AXI_DC_RUSER : in std_logic_vector(0 downto 0); M_AXI_DC_RACK : out std_logic; M_AXI_DC_ACVALID : in std_logic; M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_DC_ACREADY : out std_logic; M_AXI_DC_CRREADY : in std_logic; M_AXI_DC_CRVALID : out std_logic; M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_DC_CDVALID : out std_logic; M_AXI_DC_CDREADY : in std_logic; M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_DC_CDLAST : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to 31); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to 31); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to 31); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to 31); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to 31); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to 31); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to 31); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to 31); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to 31); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to 31); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to 31); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to 31); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to 31); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to 31); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to 31); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to 31); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to 31); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to 31); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to 31); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to 31); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to 31); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to 31); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to 31); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to 31); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to 31); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to 31); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to 31); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to 31); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to 31); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to 31); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to 31); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to 31); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(31 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(31 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(31 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(31 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(31 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(31 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(31 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(31 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(31 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(31 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(31 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(31 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(31 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(31 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(31 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(31 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(31 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(31 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(31 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(31 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(31 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(31 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(31 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(31 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(31 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(31 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(31 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(31 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(31 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(31 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(31 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(31 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end component; component system_mb_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 11); MPLB_Rst : out std_logic_vector(0 to 5); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 191); M_UABus : in std_logic_vector(0 to 191); M_BE : in std_logic_vector(0 to 47); M_RNW : in std_logic_vector(0 to 5); M_abort : in std_logic_vector(0 to 5); M_busLock : in std_logic_vector(0 to 5); M_TAttribute : in std_logic_vector(0 to 95); M_lockErr : in std_logic_vector(0 to 5); M_MSize : in std_logic_vector(0 to 11); M_priority : in std_logic_vector(0 to 11); M_rdBurst : in std_logic_vector(0 to 5); M_request : in std_logic_vector(0 to 5); M_size : in std_logic_vector(0 to 23); M_type : in std_logic_vector(0 to 17); M_wrBurst : in std_logic_vector(0 to 5); M_wrDBus : in std_logic_vector(0 to 383); Sl_addrAck : in std_logic_vector(0 to 11); Sl_MRdErr : in std_logic_vector(0 to 71); Sl_MWrErr : in std_logic_vector(0 to 71); Sl_MBusy : in std_logic_vector(0 to 71); Sl_rdBTerm : in std_logic_vector(0 to 11); Sl_rdComp : in std_logic_vector(0 to 11); Sl_rdDAck : in std_logic_vector(0 to 11); Sl_rdDBus : in std_logic_vector(0 to 767); Sl_rdWdAddr : in std_logic_vector(0 to 47); Sl_rearbitrate : in std_logic_vector(0 to 11); Sl_SSize : in std_logic_vector(0 to 23); Sl_wait : in std_logic_vector(0 to 11); Sl_wrBTerm : in std_logic_vector(0 to 11); Sl_wrComp : in std_logic_vector(0 to 11); Sl_wrDAck : in std_logic_vector(0 to 11); Sl_MIRQ : in std_logic_vector(0 to 71); PLB_MIRQ : out std_logic_vector(0 to 5); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 5); PLB_MTimeout : out std_logic_vector(0 to 5); PLB_MBusy : out std_logic_vector(0 to 5); PLB_MRdErr : out std_logic_vector(0 to 5); PLB_MWrErr : out std_logic_vector(0 to 5); PLB_MRdBTerm : out std_logic_vector(0 to 5); PLB_MRdDAck : out std_logic_vector(0 to 5); PLB_MRdDBus : out std_logic_vector(0 to 383); PLB_MRdWdAddr : out std_logic_vector(0 to 23); PLB_MRearbitrate : out std_logic_vector(0 to 5); PLB_MWrBTerm : out std_logic_vector(0 to 5); PLB_MWrDAck : out std_logic_vector(0 to 5); PLB_MSSize : out std_logic_vector(0 to 11); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 2); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 11); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 11); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 5); PLB_SMWrErr : out std_logic_vector(0 to 5); PLB_SMBusy : out std_logic_vector(0 to 5); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ilmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_wrapper is port ( LMB_Clk : in std_logic; SYS_Rst : in std_logic; LMB_Rst : out std_logic; M_ABus : in std_logic_vector(0 to 31); M_ReadStrobe : in std_logic; M_WriteStrobe : in std_logic; M_AddrStrobe : in std_logic; M_DBus : in std_logic_vector(0 to 31); M_BE : in std_logic_vector(0 to 3); Sl_DBus : in std_logic_vector(0 to 31); Sl_Ready : in std_logic_vector(0 to 0); Sl_Wait : in std_logic_vector(0 to 0); Sl_UE : in std_logic_vector(0 to 0); Sl_CE : in std_logic_vector(0 to 0); LMB_ABus : out std_logic_vector(0 to 31); LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_AddrStrobe : out std_logic; LMB_ReadDBus : out std_logic_vector(0 to 31); LMB_WriteDBus : out std_logic_vector(0 to 31); LMB_Ready : out std_logic; LMB_Wait : out std_logic; LMB_UE : out std_logic; LMB_CE : out std_logic; LMB_BE : out std_logic_vector(0 to 3) ); end component; component system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_ilmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; component system_lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end component; component system_ddr2_sdram_wrapper is port ( FSL0_M_Clk : in std_logic; FSL0_M_Write : in std_logic; FSL0_M_Data : in std_logic_vector(0 to 31); FSL0_M_Control : in std_logic; FSL0_M_Full : out std_logic; FSL0_S_Clk : in std_logic; FSL0_S_Read : in std_logic; FSL0_S_Data : out std_logic_vector(0 to 31); FSL0_S_Control : out std_logic; FSL0_S_Exists : out std_logic; FSL0_B_M_Clk : in std_logic; FSL0_B_M_Write : in std_logic; FSL0_B_M_Data : in std_logic_vector(0 to 31); FSL0_B_M_Control : in std_logic; FSL0_B_M_Full : out std_logic; FSL0_B_S_Clk : in std_logic; FSL0_B_S_Read : in std_logic; FSL0_B_S_Data : out std_logic_vector(0 to 31); FSL0_B_S_Control : out std_logic; FSL0_B_S_Exists : out std_logic; SPLB0_Clk : in std_logic; SPLB0_Rst : in std_logic; SPLB0_PLB_ABus : in std_logic_vector(0 to 31); SPLB0_PLB_PAValid : in std_logic; SPLB0_PLB_SAValid : in std_logic; SPLB0_PLB_masterID : in std_logic_vector(0 to 2); SPLB0_PLB_RNW : in std_logic; SPLB0_PLB_BE : in std_logic_vector(0 to 7); SPLB0_PLB_UABus : in std_logic_vector(0 to 31); SPLB0_PLB_rdPrim : in std_logic; SPLB0_PLB_wrPrim : in std_logic; SPLB0_PLB_abort : in std_logic; SPLB0_PLB_busLock : in std_logic; SPLB0_PLB_MSize : in std_logic_vector(0 to 1); SPLB0_PLB_size : in std_logic_vector(0 to 3); SPLB0_PLB_type : in std_logic_vector(0 to 2); SPLB0_PLB_lockErr : in std_logic; SPLB0_PLB_wrPendReq : in std_logic; SPLB0_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB0_PLB_rdPendReq : in std_logic; SPLB0_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB0_PLB_reqPri : in std_logic_vector(0 to 1); SPLB0_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB0_PLB_rdBurst : in std_logic; SPLB0_PLB_wrBurst : in std_logic; SPLB0_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB0_Sl_addrAck : out std_logic; SPLB0_Sl_SSize : out std_logic_vector(0 to 1); SPLB0_Sl_wait : out std_logic; SPLB0_Sl_rearbitrate : out std_logic; SPLB0_Sl_wrDAck : out std_logic; SPLB0_Sl_wrComp : out std_logic; SPLB0_Sl_wrBTerm : out std_logic; SPLB0_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB0_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB0_Sl_rdDAck : out std_logic; SPLB0_Sl_rdComp : out std_logic; SPLB0_Sl_rdBTerm : out std_logic; SPLB0_Sl_MBusy : out std_logic_vector(0 to 5); SPLB0_Sl_MRdErr : out std_logic_vector(0 to 5); SPLB0_Sl_MWrErr : out std_logic_vector(0 to 5); SPLB0_Sl_MIRQ : out std_logic_vector(0 to 5); SDMA0_Clk : in std_logic; SDMA0_Rx_IntOut : out std_logic; SDMA0_Tx_IntOut : out std_logic; SDMA0_RstOut : out std_logic; SDMA0_TX_D : out std_logic_vector(0 to 31); SDMA0_TX_Rem : out std_logic_vector(0 to 3); SDMA0_TX_SOF : out std_logic; SDMA0_TX_EOF : out std_logic; SDMA0_TX_SOP : out std_logic; SDMA0_TX_EOP : out std_logic; SDMA0_TX_Src_Rdy : out std_logic; SDMA0_TX_Dst_Rdy : in std_logic; SDMA0_RX_D : in std_logic_vector(0 to 31); SDMA0_RX_Rem : in std_logic_vector(0 to 3); SDMA0_RX_SOF : in std_logic; SDMA0_RX_EOF : in std_logic; SDMA0_RX_SOP : in std_logic; SDMA0_RX_EOP : in std_logic; SDMA0_RX_Src_Rdy : in std_logic; SDMA0_RX_Dst_Rdy : out std_logic; SDMA_CTRL0_Clk : in std_logic; SDMA_CTRL0_Rst : in std_logic; SDMA_CTRL0_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL0_PLB_PAValid : in std_logic; SDMA_CTRL0_PLB_SAValid : in std_logic; SDMA_CTRL0_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL0_PLB_RNW : in std_logic; SDMA_CTRL0_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL0_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL0_PLB_rdPrim : in std_logic; SDMA_CTRL0_PLB_wrPrim : in std_logic; SDMA_CTRL0_PLB_abort : in std_logic; SDMA_CTRL0_PLB_busLock : in std_logic; SDMA_CTRL0_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL0_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL0_PLB_lockErr : in std_logic; SDMA_CTRL0_PLB_wrPendReq : in std_logic; SDMA_CTRL0_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_rdPendReq : in std_logic; SDMA_CTRL0_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL0_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL0_PLB_rdBurst : in std_logic; SDMA_CTRL0_PLB_wrBurst : in std_logic; SDMA_CTRL0_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL0_Sl_addrAck : out std_logic; SDMA_CTRL0_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL0_Sl_wait : out std_logic; SDMA_CTRL0_Sl_rearbitrate : out std_logic; SDMA_CTRL0_Sl_wrDAck : out std_logic; SDMA_CTRL0_Sl_wrComp : out std_logic; SDMA_CTRL0_Sl_wrBTerm : out std_logic; SDMA_CTRL0_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL0_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL0_Sl_rdDAck : out std_logic; SDMA_CTRL0_Sl_rdComp : out std_logic; SDMA_CTRL0_Sl_rdBTerm : out std_logic; SDMA_CTRL0_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL0_Sl_MIRQ : out std_logic_vector(0 to 0); PIM0_Addr : in std_logic_vector(31 downto 0); PIM0_AddrReq : in std_logic; PIM0_AddrAck : out std_logic; PIM0_RNW : in std_logic; PIM0_Size : in std_logic_vector(3 downto 0); PIM0_RdModWr : in std_logic; PIM0_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM0_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM0_WrFIFO_Push : in std_logic; PIM0_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM0_RdFIFO_Pop : in std_logic; PIM0_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM0_WrFIFO_Empty : out std_logic; PIM0_WrFIFO_AlmostFull : out std_logic; PIM0_WrFIFO_Flush : in std_logic; PIM0_RdFIFO_Empty : out std_logic; PIM0_RdFIFO_Flush : in std_logic; PIM0_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM0_InitDone : out std_logic; PPC440MC0_MIMCReadNotWrite : in std_logic; PPC440MC0_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC0_MIMCAddressValid : in std_logic; PPC440MC0_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC0_MIMCWriteDataValid : in std_logic; PPC440MC0_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC0_MIMCBankConflict : in std_logic; PPC440MC0_MIMCRowConflict : in std_logic; PPC440MC0_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC0_MCMIReadDataValid : out std_logic; PPC440MC0_MCMIReadDataErr : out std_logic; PPC440MC0_MCMIAddrReadyToAccept : out std_logic; VFBC0_Cmd_Clk : in std_logic; VFBC0_Cmd_Reset : in std_logic; VFBC0_Cmd_Data : in std_logic_vector(31 downto 0); VFBC0_Cmd_Write : in std_logic; VFBC0_Cmd_End : in std_logic; VFBC0_Cmd_Full : out std_logic; VFBC0_Cmd_Almost_Full : out std_logic; VFBC0_Cmd_Idle : out std_logic; VFBC0_Wd_Clk : in std_logic; VFBC0_Wd_Reset : in std_logic; VFBC0_Wd_Write : in std_logic; VFBC0_Wd_End_Burst : in std_logic; VFBC0_Wd_Flush : in std_logic; VFBC0_Wd_Data : in std_logic_vector(31 downto 0); VFBC0_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC0_Wd_Full : out std_logic; VFBC0_Wd_Almost_Full : out std_logic; VFBC0_Rd_Clk : in std_logic; VFBC0_Rd_Reset : in std_logic; VFBC0_Rd_Read : in std_logic; VFBC0_Rd_End_Burst : in std_logic; VFBC0_Rd_Flush : in std_logic; VFBC0_Rd_Data : out std_logic_vector(31 downto 0); VFBC0_Rd_Empty : out std_logic; VFBC0_Rd_Almost_Empty : out std_logic; MCB0_cmd_clk : in std_logic; MCB0_cmd_en : in std_logic; MCB0_cmd_instr : in std_logic_vector(2 downto 0); MCB0_cmd_bl : in std_logic_vector(5 downto 0); MCB0_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB0_cmd_empty : out std_logic; MCB0_cmd_full : out std_logic; MCB0_wr_clk : in std_logic; MCB0_wr_en : in std_logic; MCB0_wr_mask : in std_logic_vector(7 downto 0); MCB0_wr_data : in std_logic_vector(63 downto 0); MCB0_wr_full : out std_logic; MCB0_wr_empty : out std_logic; MCB0_wr_count : out std_logic_vector(6 downto 0); MCB0_wr_underrun : out std_logic; MCB0_wr_error : out std_logic; MCB0_rd_clk : in std_logic; MCB0_rd_en : in std_logic; MCB0_rd_data : out std_logic_vector(63 downto 0); MCB0_rd_full : out std_logic; MCB0_rd_empty : out std_logic; MCB0_rd_count : out std_logic_vector(6 downto 0); MCB0_rd_overflow : out std_logic; MCB0_rd_error : out std_logic; FSL1_M_Clk : in std_logic; FSL1_M_Write : in std_logic; FSL1_M_Data : in std_logic_vector(0 to 31); FSL1_M_Control : in std_logic; FSL1_M_Full : out std_logic; FSL1_S_Clk : in std_logic; FSL1_S_Read : in std_logic; FSL1_S_Data : out std_logic_vector(0 to 31); FSL1_S_Control : out std_logic; FSL1_S_Exists : out std_logic; FSL1_B_M_Clk : in std_logic; FSL1_B_M_Write : in std_logic; FSL1_B_M_Data : in std_logic_vector(0 to 31); FSL1_B_M_Control : in std_logic; FSL1_B_M_Full : out std_logic; FSL1_B_S_Clk : in std_logic; FSL1_B_S_Read : in std_logic; FSL1_B_S_Data : out std_logic_vector(0 to 31); FSL1_B_S_Control : out std_logic; FSL1_B_S_Exists : out std_logic; SPLB1_Clk : in std_logic; SPLB1_Rst : in std_logic; SPLB1_PLB_ABus : in std_logic_vector(0 to 31); SPLB1_PLB_PAValid : in std_logic; SPLB1_PLB_SAValid : in std_logic; SPLB1_PLB_masterID : in std_logic_vector(0 to 0); SPLB1_PLB_RNW : in std_logic; SPLB1_PLB_BE : in std_logic_vector(0 to 7); SPLB1_PLB_UABus : in std_logic_vector(0 to 31); SPLB1_PLB_rdPrim : in std_logic; SPLB1_PLB_wrPrim : in std_logic; SPLB1_PLB_abort : in std_logic; SPLB1_PLB_busLock : in std_logic; SPLB1_PLB_MSize : in std_logic_vector(0 to 1); SPLB1_PLB_size : in std_logic_vector(0 to 3); SPLB1_PLB_type : in std_logic_vector(0 to 2); SPLB1_PLB_lockErr : in std_logic; SPLB1_PLB_wrPendReq : in std_logic; SPLB1_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB1_PLB_rdPendReq : in std_logic; SPLB1_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB1_PLB_reqPri : in std_logic_vector(0 to 1); SPLB1_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB1_PLB_rdBurst : in std_logic; SPLB1_PLB_wrBurst : in std_logic; SPLB1_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB1_Sl_addrAck : out std_logic; SPLB1_Sl_SSize : out std_logic_vector(0 to 1); SPLB1_Sl_wait : out std_logic; SPLB1_Sl_rearbitrate : out std_logic; SPLB1_Sl_wrDAck : out std_logic; SPLB1_Sl_wrComp : out std_logic; SPLB1_Sl_wrBTerm : out std_logic; SPLB1_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB1_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB1_Sl_rdDAck : out std_logic; SPLB1_Sl_rdComp : out std_logic; SPLB1_Sl_rdBTerm : out std_logic; SPLB1_Sl_MBusy : out std_logic_vector(0 to 0); SPLB1_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB1_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB1_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA1_Clk : in std_logic; SDMA1_Rx_IntOut : out std_logic; SDMA1_Tx_IntOut : out std_logic; SDMA1_RstOut : out std_logic; SDMA1_TX_D : out std_logic_vector(0 to 31); SDMA1_TX_Rem : out std_logic_vector(0 to 3); SDMA1_TX_SOF : out std_logic; SDMA1_TX_EOF : out std_logic; SDMA1_TX_SOP : out std_logic; SDMA1_TX_EOP : out std_logic; SDMA1_TX_Src_Rdy : out std_logic; SDMA1_TX_Dst_Rdy : in std_logic; SDMA1_RX_D : in std_logic_vector(0 to 31); SDMA1_RX_Rem : in std_logic_vector(0 to 3); SDMA1_RX_SOF : in std_logic; SDMA1_RX_EOF : in std_logic; SDMA1_RX_SOP : in std_logic; SDMA1_RX_EOP : in std_logic; SDMA1_RX_Src_Rdy : in std_logic; SDMA1_RX_Dst_Rdy : out std_logic; SDMA_CTRL1_Clk : in std_logic; SDMA_CTRL1_Rst : in std_logic; SDMA_CTRL1_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL1_PLB_PAValid : in std_logic; SDMA_CTRL1_PLB_SAValid : in std_logic; SDMA_CTRL1_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL1_PLB_RNW : in std_logic; SDMA_CTRL1_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL1_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL1_PLB_rdPrim : in std_logic; SDMA_CTRL1_PLB_wrPrim : in std_logic; SDMA_CTRL1_PLB_abort : in std_logic; SDMA_CTRL1_PLB_busLock : in std_logic; SDMA_CTRL1_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL1_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL1_PLB_lockErr : in std_logic; SDMA_CTRL1_PLB_wrPendReq : in std_logic; SDMA_CTRL1_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_rdPendReq : in std_logic; SDMA_CTRL1_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL1_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL1_PLB_rdBurst : in std_logic; SDMA_CTRL1_PLB_wrBurst : in std_logic; SDMA_CTRL1_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL1_Sl_addrAck : out std_logic; SDMA_CTRL1_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL1_Sl_wait : out std_logic; SDMA_CTRL1_Sl_rearbitrate : out std_logic; SDMA_CTRL1_Sl_wrDAck : out std_logic; SDMA_CTRL1_Sl_wrComp : out std_logic; SDMA_CTRL1_Sl_wrBTerm : out std_logic; SDMA_CTRL1_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL1_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL1_Sl_rdDAck : out std_logic; SDMA_CTRL1_Sl_rdComp : out std_logic; SDMA_CTRL1_Sl_rdBTerm : out std_logic; SDMA_CTRL1_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL1_Sl_MIRQ : out std_logic_vector(0 to 0); PIM1_Addr : in std_logic_vector(31 downto 0); PIM1_AddrReq : in std_logic; PIM1_AddrAck : out std_logic; PIM1_RNW : in std_logic; PIM1_Size : in std_logic_vector(3 downto 0); PIM1_RdModWr : in std_logic; PIM1_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM1_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM1_WrFIFO_Push : in std_logic; PIM1_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM1_RdFIFO_Pop : in std_logic; PIM1_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM1_WrFIFO_Empty : out std_logic; PIM1_WrFIFO_AlmostFull : out std_logic; PIM1_WrFIFO_Flush : in std_logic; PIM1_RdFIFO_Empty : out std_logic; PIM1_RdFIFO_Flush : in std_logic; PIM1_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM1_InitDone : out std_logic; PPC440MC1_MIMCReadNotWrite : in std_logic; PPC440MC1_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC1_MIMCAddressValid : in std_logic; PPC440MC1_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC1_MIMCWriteDataValid : in std_logic; PPC440MC1_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC1_MIMCBankConflict : in std_logic; PPC440MC1_MIMCRowConflict : in std_logic; PPC440MC1_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC1_MCMIReadDataValid : out std_logic; PPC440MC1_MCMIReadDataErr : out std_logic; PPC440MC1_MCMIAddrReadyToAccept : out std_logic; VFBC1_Cmd_Clk : in std_logic; VFBC1_Cmd_Reset : in std_logic; VFBC1_Cmd_Data : in std_logic_vector(31 downto 0); VFBC1_Cmd_Write : in std_logic; VFBC1_Cmd_End : in std_logic; VFBC1_Cmd_Full : out std_logic; VFBC1_Cmd_Almost_Full : out std_logic; VFBC1_Cmd_Idle : out std_logic; VFBC1_Wd_Clk : in std_logic; VFBC1_Wd_Reset : in std_logic; VFBC1_Wd_Write : in std_logic; VFBC1_Wd_End_Burst : in std_logic; VFBC1_Wd_Flush : in std_logic; VFBC1_Wd_Data : in std_logic_vector(31 downto 0); VFBC1_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC1_Wd_Full : out std_logic; VFBC1_Wd_Almost_Full : out std_logic; VFBC1_Rd_Clk : in std_logic; VFBC1_Rd_Reset : in std_logic; VFBC1_Rd_Read : in std_logic; VFBC1_Rd_End_Burst : in std_logic; VFBC1_Rd_Flush : in std_logic; VFBC1_Rd_Data : out std_logic_vector(31 downto 0); VFBC1_Rd_Empty : out std_logic; VFBC1_Rd_Almost_Empty : out std_logic; MCB1_cmd_clk : in std_logic; MCB1_cmd_en : in std_logic; MCB1_cmd_instr : in std_logic_vector(2 downto 0); MCB1_cmd_bl : in std_logic_vector(5 downto 0); MCB1_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB1_cmd_empty : out std_logic; MCB1_cmd_full : out std_logic; MCB1_wr_clk : in std_logic; MCB1_wr_en : in std_logic; MCB1_wr_mask : in std_logic_vector(7 downto 0); MCB1_wr_data : in std_logic_vector(63 downto 0); MCB1_wr_full : out std_logic; MCB1_wr_empty : out std_logic; MCB1_wr_count : out std_logic_vector(6 downto 0); MCB1_wr_underrun : out std_logic; MCB1_wr_error : out std_logic; MCB1_rd_clk : in std_logic; MCB1_rd_en : in std_logic; MCB1_rd_data : out std_logic_vector(63 downto 0); MCB1_rd_full : out std_logic; MCB1_rd_empty : out std_logic; MCB1_rd_count : out std_logic_vector(6 downto 0); MCB1_rd_overflow : out std_logic; MCB1_rd_error : out std_logic; FSL2_M_Clk : in std_logic; FSL2_M_Write : in std_logic; FSL2_M_Data : in std_logic_vector(0 to 31); FSL2_M_Control : in std_logic; FSL2_M_Full : out std_logic; FSL2_S_Clk : in std_logic; FSL2_S_Read : in std_logic; FSL2_S_Data : out std_logic_vector(0 to 31); FSL2_S_Control : out std_logic; FSL2_S_Exists : out std_logic; FSL2_B_M_Clk : in std_logic; FSL2_B_M_Write : in std_logic; FSL2_B_M_Data : in std_logic_vector(0 to 31); FSL2_B_M_Control : in std_logic; FSL2_B_M_Full : out std_logic; FSL2_B_S_Clk : in std_logic; FSL2_B_S_Read : in std_logic; FSL2_B_S_Data : out std_logic_vector(0 to 31); FSL2_B_S_Control : out std_logic; FSL2_B_S_Exists : out std_logic; SPLB2_Clk : in std_logic; SPLB2_Rst : in std_logic; SPLB2_PLB_ABus : in std_logic_vector(0 to 31); SPLB2_PLB_PAValid : in std_logic; SPLB2_PLB_SAValid : in std_logic; SPLB2_PLB_masterID : in std_logic_vector(0 to 0); SPLB2_PLB_RNW : in std_logic; SPLB2_PLB_BE : in std_logic_vector(0 to 7); SPLB2_PLB_UABus : in std_logic_vector(0 to 31); SPLB2_PLB_rdPrim : in std_logic; SPLB2_PLB_wrPrim : in std_logic; SPLB2_PLB_abort : in std_logic; SPLB2_PLB_busLock : in std_logic; SPLB2_PLB_MSize : in std_logic_vector(0 to 1); SPLB2_PLB_size : in std_logic_vector(0 to 3); SPLB2_PLB_type : in std_logic_vector(0 to 2); SPLB2_PLB_lockErr : in std_logic; SPLB2_PLB_wrPendReq : in std_logic; SPLB2_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB2_PLB_rdPendReq : in std_logic; SPLB2_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB2_PLB_reqPri : in std_logic_vector(0 to 1); SPLB2_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB2_PLB_rdBurst : in std_logic; SPLB2_PLB_wrBurst : in std_logic; SPLB2_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB2_Sl_addrAck : out std_logic; SPLB2_Sl_SSize : out std_logic_vector(0 to 1); SPLB2_Sl_wait : out std_logic; SPLB2_Sl_rearbitrate : out std_logic; SPLB2_Sl_wrDAck : out std_logic; SPLB2_Sl_wrComp : out std_logic; SPLB2_Sl_wrBTerm : out std_logic; SPLB2_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB2_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB2_Sl_rdDAck : out std_logic; SPLB2_Sl_rdComp : out std_logic; SPLB2_Sl_rdBTerm : out std_logic; SPLB2_Sl_MBusy : out std_logic_vector(0 to 0); SPLB2_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB2_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB2_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA2_Clk : in std_logic; SDMA2_Rx_IntOut : out std_logic; SDMA2_Tx_IntOut : out std_logic; SDMA2_RstOut : out std_logic; SDMA2_TX_D : out std_logic_vector(0 to 31); SDMA2_TX_Rem : out std_logic_vector(0 to 3); SDMA2_TX_SOF : out std_logic; SDMA2_TX_EOF : out std_logic; SDMA2_TX_SOP : out std_logic; SDMA2_TX_EOP : out std_logic; SDMA2_TX_Src_Rdy : out std_logic; SDMA2_TX_Dst_Rdy : in std_logic; SDMA2_RX_D : in std_logic_vector(0 to 31); SDMA2_RX_Rem : in std_logic_vector(0 to 3); SDMA2_RX_SOF : in std_logic; SDMA2_RX_EOF : in std_logic; SDMA2_RX_SOP : in std_logic; SDMA2_RX_EOP : in std_logic; SDMA2_RX_Src_Rdy : in std_logic; SDMA2_RX_Dst_Rdy : out std_logic; SDMA_CTRL2_Clk : in std_logic; SDMA_CTRL2_Rst : in std_logic; SDMA_CTRL2_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL2_PLB_PAValid : in std_logic; SDMA_CTRL2_PLB_SAValid : in std_logic; SDMA_CTRL2_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL2_PLB_RNW : in std_logic; SDMA_CTRL2_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL2_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL2_PLB_rdPrim : in std_logic; SDMA_CTRL2_PLB_wrPrim : in std_logic; SDMA_CTRL2_PLB_abort : in std_logic; SDMA_CTRL2_PLB_busLock : in std_logic; SDMA_CTRL2_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL2_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL2_PLB_lockErr : in std_logic; SDMA_CTRL2_PLB_wrPendReq : in std_logic; SDMA_CTRL2_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_rdPendReq : in std_logic; SDMA_CTRL2_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL2_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL2_PLB_rdBurst : in std_logic; SDMA_CTRL2_PLB_wrBurst : in std_logic; SDMA_CTRL2_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL2_Sl_addrAck : out std_logic; SDMA_CTRL2_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL2_Sl_wait : out std_logic; SDMA_CTRL2_Sl_rearbitrate : out std_logic; SDMA_CTRL2_Sl_wrDAck : out std_logic; SDMA_CTRL2_Sl_wrComp : out std_logic; SDMA_CTRL2_Sl_wrBTerm : out std_logic; SDMA_CTRL2_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL2_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL2_Sl_rdDAck : out std_logic; SDMA_CTRL2_Sl_rdComp : out std_logic; SDMA_CTRL2_Sl_rdBTerm : out std_logic; SDMA_CTRL2_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL2_Sl_MIRQ : out std_logic_vector(0 to 0); PIM2_Addr : in std_logic_vector(31 downto 0); PIM2_AddrReq : in std_logic; PIM2_AddrAck : out std_logic; PIM2_RNW : in std_logic; PIM2_Size : in std_logic_vector(3 downto 0); PIM2_RdModWr : in std_logic; PIM2_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM2_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM2_WrFIFO_Push : in std_logic; PIM2_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM2_RdFIFO_Pop : in std_logic; PIM2_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM2_WrFIFO_Empty : out std_logic; PIM2_WrFIFO_AlmostFull : out std_logic; PIM2_WrFIFO_Flush : in std_logic; PIM2_RdFIFO_Empty : out std_logic; PIM2_RdFIFO_Flush : in std_logic; PIM2_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM2_InitDone : out std_logic; PPC440MC2_MIMCReadNotWrite : in std_logic; PPC440MC2_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC2_MIMCAddressValid : in std_logic; PPC440MC2_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC2_MIMCWriteDataValid : in std_logic; PPC440MC2_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC2_MIMCBankConflict : in std_logic; PPC440MC2_MIMCRowConflict : in std_logic; PPC440MC2_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC2_MCMIReadDataValid : out std_logic; PPC440MC2_MCMIReadDataErr : out std_logic; PPC440MC2_MCMIAddrReadyToAccept : out std_logic; VFBC2_Cmd_Clk : in std_logic; VFBC2_Cmd_Reset : in std_logic; VFBC2_Cmd_Data : in std_logic_vector(31 downto 0); VFBC2_Cmd_Write : in std_logic; VFBC2_Cmd_End : in std_logic; VFBC2_Cmd_Full : out std_logic; VFBC2_Cmd_Almost_Full : out std_logic; VFBC2_Cmd_Idle : out std_logic; VFBC2_Wd_Clk : in std_logic; VFBC2_Wd_Reset : in std_logic; VFBC2_Wd_Write : in std_logic; VFBC2_Wd_End_Burst : in std_logic; VFBC2_Wd_Flush : in std_logic; VFBC2_Wd_Data : in std_logic_vector(31 downto 0); VFBC2_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC2_Wd_Full : out std_logic; VFBC2_Wd_Almost_Full : out std_logic; VFBC2_Rd_Clk : in std_logic; VFBC2_Rd_Reset : in std_logic; VFBC2_Rd_Read : in std_logic; VFBC2_Rd_End_Burst : in std_logic; VFBC2_Rd_Flush : in std_logic; VFBC2_Rd_Data : out std_logic_vector(31 downto 0); VFBC2_Rd_Empty : out std_logic; VFBC2_Rd_Almost_Empty : out std_logic; MCB2_cmd_clk : in std_logic; MCB2_cmd_en : in std_logic; MCB2_cmd_instr : in std_logic_vector(2 downto 0); MCB2_cmd_bl : in std_logic_vector(5 downto 0); MCB2_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB2_cmd_empty : out std_logic; MCB2_cmd_full : out std_logic; MCB2_wr_clk : in std_logic; MCB2_wr_en : in std_logic; MCB2_wr_mask : in std_logic_vector(7 downto 0); MCB2_wr_data : in std_logic_vector(63 downto 0); MCB2_wr_full : out std_logic; MCB2_wr_empty : out std_logic; MCB2_wr_count : out std_logic_vector(6 downto 0); MCB2_wr_underrun : out std_logic; MCB2_wr_error : out std_logic; MCB2_rd_clk : in std_logic; MCB2_rd_en : in std_logic; MCB2_rd_data : out std_logic_vector(63 downto 0); MCB2_rd_full : out std_logic; MCB2_rd_empty : out std_logic; MCB2_rd_count : out std_logic_vector(6 downto 0); MCB2_rd_overflow : out std_logic; MCB2_rd_error : out std_logic; FSL3_M_Clk : in std_logic; FSL3_M_Write : in std_logic; FSL3_M_Data : in std_logic_vector(0 to 31); FSL3_M_Control : in std_logic; FSL3_M_Full : out std_logic; FSL3_S_Clk : in std_logic; FSL3_S_Read : in std_logic; FSL3_S_Data : out std_logic_vector(0 to 31); FSL3_S_Control : out std_logic; FSL3_S_Exists : out std_logic; FSL3_B_M_Clk : in std_logic; FSL3_B_M_Write : in std_logic; FSL3_B_M_Data : in std_logic_vector(0 to 31); FSL3_B_M_Control : in std_logic; FSL3_B_M_Full : out std_logic; FSL3_B_S_Clk : in std_logic; FSL3_B_S_Read : in std_logic; FSL3_B_S_Data : out std_logic_vector(0 to 31); FSL3_B_S_Control : out std_logic; FSL3_B_S_Exists : out std_logic; SPLB3_Clk : in std_logic; SPLB3_Rst : in std_logic; SPLB3_PLB_ABus : in std_logic_vector(0 to 31); SPLB3_PLB_PAValid : in std_logic; SPLB3_PLB_SAValid : in std_logic; SPLB3_PLB_masterID : in std_logic_vector(0 to 0); SPLB3_PLB_RNW : in std_logic; SPLB3_PLB_BE : in std_logic_vector(0 to 7); SPLB3_PLB_UABus : in std_logic_vector(0 to 31); SPLB3_PLB_rdPrim : in std_logic; SPLB3_PLB_wrPrim : in std_logic; SPLB3_PLB_abort : in std_logic; SPLB3_PLB_busLock : in std_logic; SPLB3_PLB_MSize : in std_logic_vector(0 to 1); SPLB3_PLB_size : in std_logic_vector(0 to 3); SPLB3_PLB_type : in std_logic_vector(0 to 2); SPLB3_PLB_lockErr : in std_logic; SPLB3_PLB_wrPendReq : in std_logic; SPLB3_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB3_PLB_rdPendReq : in std_logic; SPLB3_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB3_PLB_reqPri : in std_logic_vector(0 to 1); SPLB3_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB3_PLB_rdBurst : in std_logic; SPLB3_PLB_wrBurst : in std_logic; SPLB3_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB3_Sl_addrAck : out std_logic; SPLB3_Sl_SSize : out std_logic_vector(0 to 1); SPLB3_Sl_wait : out std_logic; SPLB3_Sl_rearbitrate : out std_logic; SPLB3_Sl_wrDAck : out std_logic; SPLB3_Sl_wrComp : out std_logic; SPLB3_Sl_wrBTerm : out std_logic; SPLB3_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB3_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB3_Sl_rdDAck : out std_logic; SPLB3_Sl_rdComp : out std_logic; SPLB3_Sl_rdBTerm : out std_logic; SPLB3_Sl_MBusy : out std_logic_vector(0 to 0); SPLB3_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB3_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB3_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA3_Clk : in std_logic; SDMA3_Rx_IntOut : out std_logic; SDMA3_Tx_IntOut : out std_logic; SDMA3_RstOut : out std_logic; SDMA3_TX_D : out std_logic_vector(0 to 31); SDMA3_TX_Rem : out std_logic_vector(0 to 3); SDMA3_TX_SOF : out std_logic; SDMA3_TX_EOF : out std_logic; SDMA3_TX_SOP : out std_logic; SDMA3_TX_EOP : out std_logic; SDMA3_TX_Src_Rdy : out std_logic; SDMA3_TX_Dst_Rdy : in std_logic; SDMA3_RX_D : in std_logic_vector(0 to 31); SDMA3_RX_Rem : in std_logic_vector(0 to 3); SDMA3_RX_SOF : in std_logic; SDMA3_RX_EOF : in std_logic; SDMA3_RX_SOP : in std_logic; SDMA3_RX_EOP : in std_logic; SDMA3_RX_Src_Rdy : in std_logic; SDMA3_RX_Dst_Rdy : out std_logic; SDMA_CTRL3_Clk : in std_logic; SDMA_CTRL3_Rst : in std_logic; SDMA_CTRL3_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL3_PLB_PAValid : in std_logic; SDMA_CTRL3_PLB_SAValid : in std_logic; SDMA_CTRL3_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL3_PLB_RNW : in std_logic; SDMA_CTRL3_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL3_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL3_PLB_rdPrim : in std_logic; SDMA_CTRL3_PLB_wrPrim : in std_logic; SDMA_CTRL3_PLB_abort : in std_logic; SDMA_CTRL3_PLB_busLock : in std_logic; SDMA_CTRL3_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL3_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL3_PLB_lockErr : in std_logic; SDMA_CTRL3_PLB_wrPendReq : in std_logic; SDMA_CTRL3_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_rdPendReq : in std_logic; SDMA_CTRL3_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL3_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL3_PLB_rdBurst : in std_logic; SDMA_CTRL3_PLB_wrBurst : in std_logic; SDMA_CTRL3_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL3_Sl_addrAck : out std_logic; SDMA_CTRL3_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL3_Sl_wait : out std_logic; SDMA_CTRL3_Sl_rearbitrate : out std_logic; SDMA_CTRL3_Sl_wrDAck : out std_logic; SDMA_CTRL3_Sl_wrComp : out std_logic; SDMA_CTRL3_Sl_wrBTerm : out std_logic; SDMA_CTRL3_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL3_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL3_Sl_rdDAck : out std_logic; SDMA_CTRL3_Sl_rdComp : out std_logic; SDMA_CTRL3_Sl_rdBTerm : out std_logic; SDMA_CTRL3_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL3_Sl_MIRQ : out std_logic_vector(0 to 0); PIM3_Addr : in std_logic_vector(31 downto 0); PIM3_AddrReq : in std_logic; PIM3_AddrAck : out std_logic; PIM3_RNW : in std_logic; PIM3_Size : in std_logic_vector(3 downto 0); PIM3_RdModWr : in std_logic; PIM3_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM3_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM3_WrFIFO_Push : in std_logic; PIM3_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM3_RdFIFO_Pop : in std_logic; PIM3_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM3_WrFIFO_Empty : out std_logic; PIM3_WrFIFO_AlmostFull : out std_logic; PIM3_WrFIFO_Flush : in std_logic; PIM3_RdFIFO_Empty : out std_logic; PIM3_RdFIFO_Flush : in std_logic; PIM3_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM3_InitDone : out std_logic; PPC440MC3_MIMCReadNotWrite : in std_logic; PPC440MC3_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC3_MIMCAddressValid : in std_logic; PPC440MC3_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC3_MIMCWriteDataValid : in std_logic; PPC440MC3_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC3_MIMCBankConflict : in std_logic; PPC440MC3_MIMCRowConflict : in std_logic; PPC440MC3_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC3_MCMIReadDataValid : out std_logic; PPC440MC3_MCMIReadDataErr : out std_logic; PPC440MC3_MCMIAddrReadyToAccept : out std_logic; VFBC3_Cmd_Clk : in std_logic; VFBC3_Cmd_Reset : in std_logic; VFBC3_Cmd_Data : in std_logic_vector(31 downto 0); VFBC3_Cmd_Write : in std_logic; VFBC3_Cmd_End : in std_logic; VFBC3_Cmd_Full : out std_logic; VFBC3_Cmd_Almost_Full : out std_logic; VFBC3_Cmd_Idle : out std_logic; VFBC3_Wd_Clk : in std_logic; VFBC3_Wd_Reset : in std_logic; VFBC3_Wd_Write : in std_logic; VFBC3_Wd_End_Burst : in std_logic; VFBC3_Wd_Flush : in std_logic; VFBC3_Wd_Data : in std_logic_vector(31 downto 0); VFBC3_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC3_Wd_Full : out std_logic; VFBC3_Wd_Almost_Full : out std_logic; VFBC3_Rd_Clk : in std_logic; VFBC3_Rd_Reset : in std_logic; VFBC3_Rd_Read : in std_logic; VFBC3_Rd_End_Burst : in std_logic; VFBC3_Rd_Flush : in std_logic; VFBC3_Rd_Data : out std_logic_vector(31 downto 0); VFBC3_Rd_Empty : out std_logic; VFBC3_Rd_Almost_Empty : out std_logic; MCB3_cmd_clk : in std_logic; MCB3_cmd_en : in std_logic; MCB3_cmd_instr : in std_logic_vector(2 downto 0); MCB3_cmd_bl : in std_logic_vector(5 downto 0); MCB3_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB3_cmd_empty : out std_logic; MCB3_cmd_full : out std_logic; MCB3_wr_clk : in std_logic; MCB3_wr_en : in std_logic; MCB3_wr_mask : in std_logic_vector(7 downto 0); MCB3_wr_data : in std_logic_vector(63 downto 0); MCB3_wr_full : out std_logic; MCB3_wr_empty : out std_logic; MCB3_wr_count : out std_logic_vector(6 downto 0); MCB3_wr_underrun : out std_logic; MCB3_wr_error : out std_logic; MCB3_rd_clk : in std_logic; MCB3_rd_en : in std_logic; MCB3_rd_data : out std_logic_vector(63 downto 0); MCB3_rd_full : out std_logic; MCB3_rd_empty : out std_logic; MCB3_rd_count : out std_logic_vector(6 downto 0); MCB3_rd_overflow : out std_logic; MCB3_rd_error : out std_logic; FSL4_M_Clk : in std_logic; FSL4_M_Write : in std_logic; FSL4_M_Data : in std_logic_vector(0 to 31); FSL4_M_Control : in std_logic; FSL4_M_Full : out std_logic; FSL4_S_Clk : in std_logic; FSL4_S_Read : in std_logic; FSL4_S_Data : out std_logic_vector(0 to 31); FSL4_S_Control : out std_logic; FSL4_S_Exists : out std_logic; FSL4_B_M_Clk : in std_logic; FSL4_B_M_Write : in std_logic; FSL4_B_M_Data : in std_logic_vector(0 to 31); FSL4_B_M_Control : in std_logic; FSL4_B_M_Full : out std_logic; FSL4_B_S_Clk : in std_logic; FSL4_B_S_Read : in std_logic; FSL4_B_S_Data : out std_logic_vector(0 to 31); FSL4_B_S_Control : out std_logic; FSL4_B_S_Exists : out std_logic; SPLB4_Clk : in std_logic; SPLB4_Rst : in std_logic; SPLB4_PLB_ABus : in std_logic_vector(0 to 31); SPLB4_PLB_PAValid : in std_logic; SPLB4_PLB_SAValid : in std_logic; SPLB4_PLB_masterID : in std_logic_vector(0 to 0); SPLB4_PLB_RNW : in std_logic; SPLB4_PLB_BE : in std_logic_vector(0 to 7); SPLB4_PLB_UABus : in std_logic_vector(0 to 31); SPLB4_PLB_rdPrim : in std_logic; SPLB4_PLB_wrPrim : in std_logic; SPLB4_PLB_abort : in std_logic; SPLB4_PLB_busLock : in std_logic; SPLB4_PLB_MSize : in std_logic_vector(0 to 1); SPLB4_PLB_size : in std_logic_vector(0 to 3); SPLB4_PLB_type : in std_logic_vector(0 to 2); SPLB4_PLB_lockErr : in std_logic; SPLB4_PLB_wrPendReq : in std_logic; SPLB4_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB4_PLB_rdPendReq : in std_logic; SPLB4_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB4_PLB_reqPri : in std_logic_vector(0 to 1); SPLB4_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB4_PLB_rdBurst : in std_logic; SPLB4_PLB_wrBurst : in std_logic; SPLB4_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB4_Sl_addrAck : out std_logic; SPLB4_Sl_SSize : out std_logic_vector(0 to 1); SPLB4_Sl_wait : out std_logic; SPLB4_Sl_rearbitrate : out std_logic; SPLB4_Sl_wrDAck : out std_logic; SPLB4_Sl_wrComp : out std_logic; SPLB4_Sl_wrBTerm : out std_logic; SPLB4_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB4_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB4_Sl_rdDAck : out std_logic; SPLB4_Sl_rdComp : out std_logic; SPLB4_Sl_rdBTerm : out std_logic; SPLB4_Sl_MBusy : out std_logic_vector(0 to 0); SPLB4_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB4_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB4_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA4_Clk : in std_logic; SDMA4_Rx_IntOut : out std_logic; SDMA4_Tx_IntOut : out std_logic; SDMA4_RstOut : out std_logic; SDMA4_TX_D : out std_logic_vector(0 to 31); SDMA4_TX_Rem : out std_logic_vector(0 to 3); SDMA4_TX_SOF : out std_logic; SDMA4_TX_EOF : out std_logic; SDMA4_TX_SOP : out std_logic; SDMA4_TX_EOP : out std_logic; SDMA4_TX_Src_Rdy : out std_logic; SDMA4_TX_Dst_Rdy : in std_logic; SDMA4_RX_D : in std_logic_vector(0 to 31); SDMA4_RX_Rem : in std_logic_vector(0 to 3); SDMA4_RX_SOF : in std_logic; SDMA4_RX_EOF : in std_logic; SDMA4_RX_SOP : in std_logic; SDMA4_RX_EOP : in std_logic; SDMA4_RX_Src_Rdy : in std_logic; SDMA4_RX_Dst_Rdy : out std_logic; SDMA_CTRL4_Clk : in std_logic; SDMA_CTRL4_Rst : in std_logic; SDMA_CTRL4_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL4_PLB_PAValid : in std_logic; SDMA_CTRL4_PLB_SAValid : in std_logic; SDMA_CTRL4_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL4_PLB_RNW : in std_logic; SDMA_CTRL4_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL4_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL4_PLB_rdPrim : in std_logic; SDMA_CTRL4_PLB_wrPrim : in std_logic; SDMA_CTRL4_PLB_abort : in std_logic; SDMA_CTRL4_PLB_busLock : in std_logic; SDMA_CTRL4_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL4_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL4_PLB_lockErr : in std_logic; SDMA_CTRL4_PLB_wrPendReq : in std_logic; SDMA_CTRL4_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_rdPendReq : in std_logic; SDMA_CTRL4_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL4_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL4_PLB_rdBurst : in std_logic; SDMA_CTRL4_PLB_wrBurst : in std_logic; SDMA_CTRL4_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL4_Sl_addrAck : out std_logic; SDMA_CTRL4_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL4_Sl_wait : out std_logic; SDMA_CTRL4_Sl_rearbitrate : out std_logic; SDMA_CTRL4_Sl_wrDAck : out std_logic; SDMA_CTRL4_Sl_wrComp : out std_logic; SDMA_CTRL4_Sl_wrBTerm : out std_logic; SDMA_CTRL4_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL4_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL4_Sl_rdDAck : out std_logic; SDMA_CTRL4_Sl_rdComp : out std_logic; SDMA_CTRL4_Sl_rdBTerm : out std_logic; SDMA_CTRL4_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL4_Sl_MIRQ : out std_logic_vector(0 to 0); PIM4_Addr : in std_logic_vector(31 downto 0); PIM4_AddrReq : in std_logic; PIM4_AddrAck : out std_logic; PIM4_RNW : in std_logic; PIM4_Size : in std_logic_vector(3 downto 0); PIM4_RdModWr : in std_logic; PIM4_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM4_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM4_WrFIFO_Push : in std_logic; PIM4_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM4_RdFIFO_Pop : in std_logic; PIM4_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM4_WrFIFO_Empty : out std_logic; PIM4_WrFIFO_AlmostFull : out std_logic; PIM4_WrFIFO_Flush : in std_logic; PIM4_RdFIFO_Empty : out std_logic; PIM4_RdFIFO_Flush : in std_logic; PIM4_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM4_InitDone : out std_logic; PPC440MC4_MIMCReadNotWrite : in std_logic; PPC440MC4_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC4_MIMCAddressValid : in std_logic; PPC440MC4_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC4_MIMCWriteDataValid : in std_logic; PPC440MC4_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC4_MIMCBankConflict : in std_logic; PPC440MC4_MIMCRowConflict : in std_logic; PPC440MC4_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC4_MCMIReadDataValid : out std_logic; PPC440MC4_MCMIReadDataErr : out std_logic; PPC440MC4_MCMIAddrReadyToAccept : out std_logic; VFBC4_Cmd_Clk : in std_logic; VFBC4_Cmd_Reset : in std_logic; VFBC4_Cmd_Data : in std_logic_vector(31 downto 0); VFBC4_Cmd_Write : in std_logic; VFBC4_Cmd_End : in std_logic; VFBC4_Cmd_Full : out std_logic; VFBC4_Cmd_Almost_Full : out std_logic; VFBC4_Cmd_Idle : out std_logic; VFBC4_Wd_Clk : in std_logic; VFBC4_Wd_Reset : in std_logic; VFBC4_Wd_Write : in std_logic; VFBC4_Wd_End_Burst : in std_logic; VFBC4_Wd_Flush : in std_logic; VFBC4_Wd_Data : in std_logic_vector(31 downto 0); VFBC4_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC4_Wd_Full : out std_logic; VFBC4_Wd_Almost_Full : out std_logic; VFBC4_Rd_Clk : in std_logic; VFBC4_Rd_Reset : in std_logic; VFBC4_Rd_Read : in std_logic; VFBC4_Rd_End_Burst : in std_logic; VFBC4_Rd_Flush : in std_logic; VFBC4_Rd_Data : out std_logic_vector(31 downto 0); VFBC4_Rd_Empty : out std_logic; VFBC4_Rd_Almost_Empty : out std_logic; MCB4_cmd_clk : in std_logic; MCB4_cmd_en : in std_logic; MCB4_cmd_instr : in std_logic_vector(2 downto 0); MCB4_cmd_bl : in std_logic_vector(5 downto 0); MCB4_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB4_cmd_empty : out std_logic; MCB4_cmd_full : out std_logic; MCB4_wr_clk : in std_logic; MCB4_wr_en : in std_logic; MCB4_wr_mask : in std_logic_vector(7 downto 0); MCB4_wr_data : in std_logic_vector(63 downto 0); MCB4_wr_full : out std_logic; MCB4_wr_empty : out std_logic; MCB4_wr_count : out std_logic_vector(6 downto 0); MCB4_wr_underrun : out std_logic; MCB4_wr_error : out std_logic; MCB4_rd_clk : in std_logic; MCB4_rd_en : in std_logic; MCB4_rd_data : out std_logic_vector(63 downto 0); MCB4_rd_full : out std_logic; MCB4_rd_empty : out std_logic; MCB4_rd_count : out std_logic_vector(6 downto 0); MCB4_rd_overflow : out std_logic; MCB4_rd_error : out std_logic; FSL5_M_Clk : in std_logic; FSL5_M_Write : in std_logic; FSL5_M_Data : in std_logic_vector(0 to 31); FSL5_M_Control : in std_logic; FSL5_M_Full : out std_logic; FSL5_S_Clk : in std_logic; FSL5_S_Read : in std_logic; FSL5_S_Data : out std_logic_vector(0 to 31); FSL5_S_Control : out std_logic; FSL5_S_Exists : out std_logic; FSL5_B_M_Clk : in std_logic; FSL5_B_M_Write : in std_logic; FSL5_B_M_Data : in std_logic_vector(0 to 31); FSL5_B_M_Control : in std_logic; FSL5_B_M_Full : out std_logic; FSL5_B_S_Clk : in std_logic; FSL5_B_S_Read : in std_logic; FSL5_B_S_Data : out std_logic_vector(0 to 31); FSL5_B_S_Control : out std_logic; FSL5_B_S_Exists : out std_logic; SPLB5_Clk : in std_logic; SPLB5_Rst : in std_logic; SPLB5_PLB_ABus : in std_logic_vector(0 to 31); SPLB5_PLB_PAValid : in std_logic; SPLB5_PLB_SAValid : in std_logic; SPLB5_PLB_masterID : in std_logic_vector(0 to 0); SPLB5_PLB_RNW : in std_logic; SPLB5_PLB_BE : in std_logic_vector(0 to 7); SPLB5_PLB_UABus : in std_logic_vector(0 to 31); SPLB5_PLB_rdPrim : in std_logic; SPLB5_PLB_wrPrim : in std_logic; SPLB5_PLB_abort : in std_logic; SPLB5_PLB_busLock : in std_logic; SPLB5_PLB_MSize : in std_logic_vector(0 to 1); SPLB5_PLB_size : in std_logic_vector(0 to 3); SPLB5_PLB_type : in std_logic_vector(0 to 2); SPLB5_PLB_lockErr : in std_logic; SPLB5_PLB_wrPendReq : in std_logic; SPLB5_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB5_PLB_rdPendReq : in std_logic; SPLB5_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB5_PLB_reqPri : in std_logic_vector(0 to 1); SPLB5_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB5_PLB_rdBurst : in std_logic; SPLB5_PLB_wrBurst : in std_logic; SPLB5_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB5_Sl_addrAck : out std_logic; SPLB5_Sl_SSize : out std_logic_vector(0 to 1); SPLB5_Sl_wait : out std_logic; SPLB5_Sl_rearbitrate : out std_logic; SPLB5_Sl_wrDAck : out std_logic; SPLB5_Sl_wrComp : out std_logic; SPLB5_Sl_wrBTerm : out std_logic; SPLB5_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB5_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB5_Sl_rdDAck : out std_logic; SPLB5_Sl_rdComp : out std_logic; SPLB5_Sl_rdBTerm : out std_logic; SPLB5_Sl_MBusy : out std_logic_vector(0 to 0); SPLB5_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB5_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB5_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA5_Clk : in std_logic; SDMA5_Rx_IntOut : out std_logic; SDMA5_Tx_IntOut : out std_logic; SDMA5_RstOut : out std_logic; SDMA5_TX_D : out std_logic_vector(0 to 31); SDMA5_TX_Rem : out std_logic_vector(0 to 3); SDMA5_TX_SOF : out std_logic; SDMA5_TX_EOF : out std_logic; SDMA5_TX_SOP : out std_logic; SDMA5_TX_EOP : out std_logic; SDMA5_TX_Src_Rdy : out std_logic; SDMA5_TX_Dst_Rdy : in std_logic; SDMA5_RX_D : in std_logic_vector(0 to 31); SDMA5_RX_Rem : in std_logic_vector(0 to 3); SDMA5_RX_SOF : in std_logic; SDMA5_RX_EOF : in std_logic; SDMA5_RX_SOP : in std_logic; SDMA5_RX_EOP : in std_logic; SDMA5_RX_Src_Rdy : in std_logic; SDMA5_RX_Dst_Rdy : out std_logic; SDMA_CTRL5_Clk : in std_logic; SDMA_CTRL5_Rst : in std_logic; SDMA_CTRL5_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL5_PLB_PAValid : in std_logic; SDMA_CTRL5_PLB_SAValid : in std_logic; SDMA_CTRL5_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL5_PLB_RNW : in std_logic; SDMA_CTRL5_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL5_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL5_PLB_rdPrim : in std_logic; SDMA_CTRL5_PLB_wrPrim : in std_logic; SDMA_CTRL5_PLB_abort : in std_logic; SDMA_CTRL5_PLB_busLock : in std_logic; SDMA_CTRL5_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL5_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL5_PLB_lockErr : in std_logic; SDMA_CTRL5_PLB_wrPendReq : in std_logic; SDMA_CTRL5_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_rdPendReq : in std_logic; SDMA_CTRL5_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL5_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL5_PLB_rdBurst : in std_logic; SDMA_CTRL5_PLB_wrBurst : in std_logic; SDMA_CTRL5_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL5_Sl_addrAck : out std_logic; SDMA_CTRL5_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL5_Sl_wait : out std_logic; SDMA_CTRL5_Sl_rearbitrate : out std_logic; SDMA_CTRL5_Sl_wrDAck : out std_logic; SDMA_CTRL5_Sl_wrComp : out std_logic; SDMA_CTRL5_Sl_wrBTerm : out std_logic; SDMA_CTRL5_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL5_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL5_Sl_rdDAck : out std_logic; SDMA_CTRL5_Sl_rdComp : out std_logic; SDMA_CTRL5_Sl_rdBTerm : out std_logic; SDMA_CTRL5_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL5_Sl_MIRQ : out std_logic_vector(0 to 0); PIM5_Addr : in std_logic_vector(31 downto 0); PIM5_AddrReq : in std_logic; PIM5_AddrAck : out std_logic; PIM5_RNW : in std_logic; PIM5_Size : in std_logic_vector(3 downto 0); PIM5_RdModWr : in std_logic; PIM5_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM5_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM5_WrFIFO_Push : in std_logic; PIM5_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM5_RdFIFO_Pop : in std_logic; PIM5_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM5_WrFIFO_Empty : out std_logic; PIM5_WrFIFO_AlmostFull : out std_logic; PIM5_WrFIFO_Flush : in std_logic; PIM5_RdFIFO_Empty : out std_logic; PIM5_RdFIFO_Flush : in std_logic; PIM5_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM5_InitDone : out std_logic; PPC440MC5_MIMCReadNotWrite : in std_logic; PPC440MC5_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC5_MIMCAddressValid : in std_logic; PPC440MC5_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC5_MIMCWriteDataValid : in std_logic; PPC440MC5_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC5_MIMCBankConflict : in std_logic; PPC440MC5_MIMCRowConflict : in std_logic; PPC440MC5_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC5_MCMIReadDataValid : out std_logic; PPC440MC5_MCMIReadDataErr : out std_logic; PPC440MC5_MCMIAddrReadyToAccept : out std_logic; VFBC5_Cmd_Clk : in std_logic; VFBC5_Cmd_Reset : in std_logic; VFBC5_Cmd_Data : in std_logic_vector(31 downto 0); VFBC5_Cmd_Write : in std_logic; VFBC5_Cmd_End : in std_logic; VFBC5_Cmd_Full : out std_logic; VFBC5_Cmd_Almost_Full : out std_logic; VFBC5_Cmd_Idle : out std_logic; VFBC5_Wd_Clk : in std_logic; VFBC5_Wd_Reset : in std_logic; VFBC5_Wd_Write : in std_logic; VFBC5_Wd_End_Burst : in std_logic; VFBC5_Wd_Flush : in std_logic; VFBC5_Wd_Data : in std_logic_vector(31 downto 0); VFBC5_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC5_Wd_Full : out std_logic; VFBC5_Wd_Almost_Full : out std_logic; VFBC5_Rd_Clk : in std_logic; VFBC5_Rd_Reset : in std_logic; VFBC5_Rd_Read : in std_logic; VFBC5_Rd_End_Burst : in std_logic; VFBC5_Rd_Flush : in std_logic; VFBC5_Rd_Data : out std_logic_vector(31 downto 0); VFBC5_Rd_Empty : out std_logic; VFBC5_Rd_Almost_Empty : out std_logic; MCB5_cmd_clk : in std_logic; MCB5_cmd_en : in std_logic; MCB5_cmd_instr : in std_logic_vector(2 downto 0); MCB5_cmd_bl : in std_logic_vector(5 downto 0); MCB5_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB5_cmd_empty : out std_logic; MCB5_cmd_full : out std_logic; MCB5_wr_clk : in std_logic; MCB5_wr_en : in std_logic; MCB5_wr_mask : in std_logic_vector(7 downto 0); MCB5_wr_data : in std_logic_vector(63 downto 0); MCB5_wr_full : out std_logic; MCB5_wr_empty : out std_logic; MCB5_wr_count : out std_logic_vector(6 downto 0); MCB5_wr_underrun : out std_logic; MCB5_wr_error : out std_logic; MCB5_rd_clk : in std_logic; MCB5_rd_en : in std_logic; MCB5_rd_data : out std_logic_vector(63 downto 0); MCB5_rd_full : out std_logic; MCB5_rd_empty : out std_logic; MCB5_rd_count : out std_logic_vector(6 downto 0); MCB5_rd_overflow : out std_logic; MCB5_rd_error : out std_logic; FSL6_M_Clk : in std_logic; FSL6_M_Write : in std_logic; FSL6_M_Data : in std_logic_vector(0 to 31); FSL6_M_Control : in std_logic; FSL6_M_Full : out std_logic; FSL6_S_Clk : in std_logic; FSL6_S_Read : in std_logic; FSL6_S_Data : out std_logic_vector(0 to 31); FSL6_S_Control : out std_logic; FSL6_S_Exists : out std_logic; FSL6_B_M_Clk : in std_logic; FSL6_B_M_Write : in std_logic; FSL6_B_M_Data : in std_logic_vector(0 to 31); FSL6_B_M_Control : in std_logic; FSL6_B_M_Full : out std_logic; FSL6_B_S_Clk : in std_logic; FSL6_B_S_Read : in std_logic; FSL6_B_S_Data : out std_logic_vector(0 to 31); FSL6_B_S_Control : out std_logic; FSL6_B_S_Exists : out std_logic; SPLB6_Clk : in std_logic; SPLB6_Rst : in std_logic; SPLB6_PLB_ABus : in std_logic_vector(0 to 31); SPLB6_PLB_PAValid : in std_logic; SPLB6_PLB_SAValid : in std_logic; SPLB6_PLB_masterID : in std_logic_vector(0 to 0); SPLB6_PLB_RNW : in std_logic; SPLB6_PLB_BE : in std_logic_vector(0 to 7); SPLB6_PLB_UABus : in std_logic_vector(0 to 31); SPLB6_PLB_rdPrim : in std_logic; SPLB6_PLB_wrPrim : in std_logic; SPLB6_PLB_abort : in std_logic; SPLB6_PLB_busLock : in std_logic; SPLB6_PLB_MSize : in std_logic_vector(0 to 1); SPLB6_PLB_size : in std_logic_vector(0 to 3); SPLB6_PLB_type : in std_logic_vector(0 to 2); SPLB6_PLB_lockErr : in std_logic; SPLB6_PLB_wrPendReq : in std_logic; SPLB6_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB6_PLB_rdPendReq : in std_logic; SPLB6_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB6_PLB_reqPri : in std_logic_vector(0 to 1); SPLB6_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB6_PLB_rdBurst : in std_logic; SPLB6_PLB_wrBurst : in std_logic; SPLB6_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB6_Sl_addrAck : out std_logic; SPLB6_Sl_SSize : out std_logic_vector(0 to 1); SPLB6_Sl_wait : out std_logic; SPLB6_Sl_rearbitrate : out std_logic; SPLB6_Sl_wrDAck : out std_logic; SPLB6_Sl_wrComp : out std_logic; SPLB6_Sl_wrBTerm : out std_logic; SPLB6_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB6_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB6_Sl_rdDAck : out std_logic; SPLB6_Sl_rdComp : out std_logic; SPLB6_Sl_rdBTerm : out std_logic; SPLB6_Sl_MBusy : out std_logic_vector(0 to 0); SPLB6_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB6_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB6_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA6_Clk : in std_logic; SDMA6_Rx_IntOut : out std_logic; SDMA6_Tx_IntOut : out std_logic; SDMA6_RstOut : out std_logic; SDMA6_TX_D : out std_logic_vector(0 to 31); SDMA6_TX_Rem : out std_logic_vector(0 to 3); SDMA6_TX_SOF : out std_logic; SDMA6_TX_EOF : out std_logic; SDMA6_TX_SOP : out std_logic; SDMA6_TX_EOP : out std_logic; SDMA6_TX_Src_Rdy : out std_logic; SDMA6_TX_Dst_Rdy : in std_logic; SDMA6_RX_D : in std_logic_vector(0 to 31); SDMA6_RX_Rem : in std_logic_vector(0 to 3); SDMA6_RX_SOF : in std_logic; SDMA6_RX_EOF : in std_logic; SDMA6_RX_SOP : in std_logic; SDMA6_RX_EOP : in std_logic; SDMA6_RX_Src_Rdy : in std_logic; SDMA6_RX_Dst_Rdy : out std_logic; SDMA_CTRL6_Clk : in std_logic; SDMA_CTRL6_Rst : in std_logic; SDMA_CTRL6_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL6_PLB_PAValid : in std_logic; SDMA_CTRL6_PLB_SAValid : in std_logic; SDMA_CTRL6_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL6_PLB_RNW : in std_logic; SDMA_CTRL6_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL6_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL6_PLB_rdPrim : in std_logic; SDMA_CTRL6_PLB_wrPrim : in std_logic; SDMA_CTRL6_PLB_abort : in std_logic; SDMA_CTRL6_PLB_busLock : in std_logic; SDMA_CTRL6_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL6_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL6_PLB_lockErr : in std_logic; SDMA_CTRL6_PLB_wrPendReq : in std_logic; SDMA_CTRL6_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_rdPendReq : in std_logic; SDMA_CTRL6_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL6_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL6_PLB_rdBurst : in std_logic; SDMA_CTRL6_PLB_wrBurst : in std_logic; SDMA_CTRL6_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL6_Sl_addrAck : out std_logic; SDMA_CTRL6_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL6_Sl_wait : out std_logic; SDMA_CTRL6_Sl_rearbitrate : out std_logic; SDMA_CTRL6_Sl_wrDAck : out std_logic; SDMA_CTRL6_Sl_wrComp : out std_logic; SDMA_CTRL6_Sl_wrBTerm : out std_logic; SDMA_CTRL6_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL6_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL6_Sl_rdDAck : out std_logic; SDMA_CTRL6_Sl_rdComp : out std_logic; SDMA_CTRL6_Sl_rdBTerm : out std_logic; SDMA_CTRL6_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL6_Sl_MIRQ : out std_logic_vector(0 to 0); PIM6_Addr : in std_logic_vector(31 downto 0); PIM6_AddrReq : in std_logic; PIM6_AddrAck : out std_logic; PIM6_RNW : in std_logic; PIM6_Size : in std_logic_vector(3 downto 0); PIM6_RdModWr : in std_logic; PIM6_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM6_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM6_WrFIFO_Push : in std_logic; PIM6_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM6_RdFIFO_Pop : in std_logic; PIM6_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM6_WrFIFO_Empty : out std_logic; PIM6_WrFIFO_AlmostFull : out std_logic; PIM6_WrFIFO_Flush : in std_logic; PIM6_RdFIFO_Empty : out std_logic; PIM6_RdFIFO_Flush : in std_logic; PIM6_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM6_InitDone : out std_logic; PPC440MC6_MIMCReadNotWrite : in std_logic; PPC440MC6_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC6_MIMCAddressValid : in std_logic; PPC440MC6_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC6_MIMCWriteDataValid : in std_logic; PPC440MC6_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC6_MIMCBankConflict : in std_logic; PPC440MC6_MIMCRowConflict : in std_logic; PPC440MC6_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC6_MCMIReadDataValid : out std_logic; PPC440MC6_MCMIReadDataErr : out std_logic; PPC440MC6_MCMIAddrReadyToAccept : out std_logic; VFBC6_Cmd_Clk : in std_logic; VFBC6_Cmd_Reset : in std_logic; VFBC6_Cmd_Data : in std_logic_vector(31 downto 0); VFBC6_Cmd_Write : in std_logic; VFBC6_Cmd_End : in std_logic; VFBC6_Cmd_Full : out std_logic; VFBC6_Cmd_Almost_Full : out std_logic; VFBC6_Cmd_Idle : out std_logic; VFBC6_Wd_Clk : in std_logic; VFBC6_Wd_Reset : in std_logic; VFBC6_Wd_Write : in std_logic; VFBC6_Wd_End_Burst : in std_logic; VFBC6_Wd_Flush : in std_logic; VFBC6_Wd_Data : in std_logic_vector(31 downto 0); VFBC6_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC6_Wd_Full : out std_logic; VFBC6_Wd_Almost_Full : out std_logic; VFBC6_Rd_Clk : in std_logic; VFBC6_Rd_Reset : in std_logic; VFBC6_Rd_Read : in std_logic; VFBC6_Rd_End_Burst : in std_logic; VFBC6_Rd_Flush : in std_logic; VFBC6_Rd_Data : out std_logic_vector(31 downto 0); VFBC6_Rd_Empty : out std_logic; VFBC6_Rd_Almost_Empty : out std_logic; MCB6_cmd_clk : in std_logic; MCB6_cmd_en : in std_logic; MCB6_cmd_instr : in std_logic_vector(2 downto 0); MCB6_cmd_bl : in std_logic_vector(5 downto 0); MCB6_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB6_cmd_empty : out std_logic; MCB6_cmd_full : out std_logic; MCB6_wr_clk : in std_logic; MCB6_wr_en : in std_logic; MCB6_wr_mask : in std_logic_vector(7 downto 0); MCB6_wr_data : in std_logic_vector(63 downto 0); MCB6_wr_full : out std_logic; MCB6_wr_empty : out std_logic; MCB6_wr_count : out std_logic_vector(6 downto 0); MCB6_wr_underrun : out std_logic; MCB6_wr_error : out std_logic; MCB6_rd_clk : in std_logic; MCB6_rd_en : in std_logic; MCB6_rd_data : out std_logic_vector(63 downto 0); MCB6_rd_full : out std_logic; MCB6_rd_empty : out std_logic; MCB6_rd_count : out std_logic_vector(6 downto 0); MCB6_rd_overflow : out std_logic; MCB6_rd_error : out std_logic; FSL7_M_Clk : in std_logic; FSL7_M_Write : in std_logic; FSL7_M_Data : in std_logic_vector(0 to 31); FSL7_M_Control : in std_logic; FSL7_M_Full : out std_logic; FSL7_S_Clk : in std_logic; FSL7_S_Read : in std_logic; FSL7_S_Data : out std_logic_vector(0 to 31); FSL7_S_Control : out std_logic; FSL7_S_Exists : out std_logic; FSL7_B_M_Clk : in std_logic; FSL7_B_M_Write : in std_logic; FSL7_B_M_Data : in std_logic_vector(0 to 31); FSL7_B_M_Control : in std_logic; FSL7_B_M_Full : out std_logic; FSL7_B_S_Clk : in std_logic; FSL7_B_S_Read : in std_logic; FSL7_B_S_Data : out std_logic_vector(0 to 31); FSL7_B_S_Control : out std_logic; FSL7_B_S_Exists : out std_logic; SPLB7_Clk : in std_logic; SPLB7_Rst : in std_logic; SPLB7_PLB_ABus : in std_logic_vector(0 to 31); SPLB7_PLB_PAValid : in std_logic; SPLB7_PLB_SAValid : in std_logic; SPLB7_PLB_masterID : in std_logic_vector(0 to 0); SPLB7_PLB_RNW : in std_logic; SPLB7_PLB_BE : in std_logic_vector(0 to 7); SPLB7_PLB_UABus : in std_logic_vector(0 to 31); SPLB7_PLB_rdPrim : in std_logic; SPLB7_PLB_wrPrim : in std_logic; SPLB7_PLB_abort : in std_logic; SPLB7_PLB_busLock : in std_logic; SPLB7_PLB_MSize : in std_logic_vector(0 to 1); SPLB7_PLB_size : in std_logic_vector(0 to 3); SPLB7_PLB_type : in std_logic_vector(0 to 2); SPLB7_PLB_lockErr : in std_logic; SPLB7_PLB_wrPendReq : in std_logic; SPLB7_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB7_PLB_rdPendReq : in std_logic; SPLB7_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB7_PLB_reqPri : in std_logic_vector(0 to 1); SPLB7_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB7_PLB_rdBurst : in std_logic; SPLB7_PLB_wrBurst : in std_logic; SPLB7_PLB_wrDBus : in std_logic_vector(0 to 63); SPLB7_Sl_addrAck : out std_logic; SPLB7_Sl_SSize : out std_logic_vector(0 to 1); SPLB7_Sl_wait : out std_logic; SPLB7_Sl_rearbitrate : out std_logic; SPLB7_Sl_wrDAck : out std_logic; SPLB7_Sl_wrComp : out std_logic; SPLB7_Sl_wrBTerm : out std_logic; SPLB7_Sl_rdDBus : out std_logic_vector(0 to 63); SPLB7_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB7_Sl_rdDAck : out std_logic; SPLB7_Sl_rdComp : out std_logic; SPLB7_Sl_rdBTerm : out std_logic; SPLB7_Sl_MBusy : out std_logic_vector(0 to 0); SPLB7_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB7_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB7_Sl_MIRQ : out std_logic_vector(0 to 0); SDMA7_Clk : in std_logic; SDMA7_Rx_IntOut : out std_logic; SDMA7_Tx_IntOut : out std_logic; SDMA7_RstOut : out std_logic; SDMA7_TX_D : out std_logic_vector(0 to 31); SDMA7_TX_Rem : out std_logic_vector(0 to 3); SDMA7_TX_SOF : out std_logic; SDMA7_TX_EOF : out std_logic; SDMA7_TX_SOP : out std_logic; SDMA7_TX_EOP : out std_logic; SDMA7_TX_Src_Rdy : out std_logic; SDMA7_TX_Dst_Rdy : in std_logic; SDMA7_RX_D : in std_logic_vector(0 to 31); SDMA7_RX_Rem : in std_logic_vector(0 to 3); SDMA7_RX_SOF : in std_logic; SDMA7_RX_EOF : in std_logic; SDMA7_RX_SOP : in std_logic; SDMA7_RX_EOP : in std_logic; SDMA7_RX_Src_Rdy : in std_logic; SDMA7_RX_Dst_Rdy : out std_logic; SDMA_CTRL7_Clk : in std_logic; SDMA_CTRL7_Rst : in std_logic; SDMA_CTRL7_PLB_ABus : in std_logic_vector(0 to 31); SDMA_CTRL7_PLB_PAValid : in std_logic; SDMA_CTRL7_PLB_SAValid : in std_logic; SDMA_CTRL7_PLB_masterID : in std_logic_vector(0 to 0); SDMA_CTRL7_PLB_RNW : in std_logic; SDMA_CTRL7_PLB_BE : in std_logic_vector(0 to 7); SDMA_CTRL7_PLB_UABus : in std_logic_vector(0 to 31); SDMA_CTRL7_PLB_rdPrim : in std_logic; SDMA_CTRL7_PLB_wrPrim : in std_logic; SDMA_CTRL7_PLB_abort : in std_logic; SDMA_CTRL7_PLB_busLock : in std_logic; SDMA_CTRL7_PLB_MSize : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_size : in std_logic_vector(0 to 3); SDMA_CTRL7_PLB_type : in std_logic_vector(0 to 2); SDMA_CTRL7_PLB_lockErr : in std_logic; SDMA_CTRL7_PLB_wrPendReq : in std_logic; SDMA_CTRL7_PLB_wrPendPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_rdPendReq : in std_logic; SDMA_CTRL7_PLB_rdPendPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_reqPri : in std_logic_vector(0 to 1); SDMA_CTRL7_PLB_TAttribute : in std_logic_vector(0 to 15); SDMA_CTRL7_PLB_rdBurst : in std_logic; SDMA_CTRL7_PLB_wrBurst : in std_logic; SDMA_CTRL7_PLB_wrDBus : in std_logic_vector(0 to 63); SDMA_CTRL7_Sl_addrAck : out std_logic; SDMA_CTRL7_Sl_SSize : out std_logic_vector(0 to 1); SDMA_CTRL7_Sl_wait : out std_logic; SDMA_CTRL7_Sl_rearbitrate : out std_logic; SDMA_CTRL7_Sl_wrDAck : out std_logic; SDMA_CTRL7_Sl_wrComp : out std_logic; SDMA_CTRL7_Sl_wrBTerm : out std_logic; SDMA_CTRL7_Sl_rdDBus : out std_logic_vector(0 to 63); SDMA_CTRL7_Sl_rdWdAddr : out std_logic_vector(0 to 3); SDMA_CTRL7_Sl_rdDAck : out std_logic; SDMA_CTRL7_Sl_rdComp : out std_logic; SDMA_CTRL7_Sl_rdBTerm : out std_logic; SDMA_CTRL7_Sl_MBusy : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MRdErr : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MWrErr : out std_logic_vector(0 to 0); SDMA_CTRL7_Sl_MIRQ : out std_logic_vector(0 to 0); PIM7_Addr : in std_logic_vector(31 downto 0); PIM7_AddrReq : in std_logic; PIM7_AddrAck : out std_logic; PIM7_RNW : in std_logic; PIM7_Size : in std_logic_vector(3 downto 0); PIM7_RdModWr : in std_logic; PIM7_WrFIFO_Data : in std_logic_vector(63 downto 0); PIM7_WrFIFO_BE : in std_logic_vector(7 downto 0); PIM7_WrFIFO_Push : in std_logic; PIM7_RdFIFO_Data : out std_logic_vector(63 downto 0); PIM7_RdFIFO_Pop : in std_logic; PIM7_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0); PIM7_WrFIFO_Empty : out std_logic; PIM7_WrFIFO_AlmostFull : out std_logic; PIM7_WrFIFO_Flush : in std_logic; PIM7_RdFIFO_Empty : out std_logic; PIM7_RdFIFO_Flush : in std_logic; PIM7_RdFIFO_Latency : out std_logic_vector(1 downto 0); PIM7_InitDone : out std_logic; PPC440MC7_MIMCReadNotWrite : in std_logic; PPC440MC7_MIMCAddress : in std_logic_vector(0 to 35); PPC440MC7_MIMCAddressValid : in std_logic; PPC440MC7_MIMCWriteData : in std_logic_vector(0 to 127); PPC440MC7_MIMCWriteDataValid : in std_logic; PPC440MC7_MIMCByteEnable : in std_logic_vector(0 to 15); PPC440MC7_MIMCBankConflict : in std_logic; PPC440MC7_MIMCRowConflict : in std_logic; PPC440MC7_MCMIReadData : out std_logic_vector(0 to 127); PPC440MC7_MCMIReadDataValid : out std_logic; PPC440MC7_MCMIReadDataErr : out std_logic; PPC440MC7_MCMIAddrReadyToAccept : out std_logic; VFBC7_Cmd_Clk : in std_logic; VFBC7_Cmd_Reset : in std_logic; VFBC7_Cmd_Data : in std_logic_vector(31 downto 0); VFBC7_Cmd_Write : in std_logic; VFBC7_Cmd_End : in std_logic; VFBC7_Cmd_Full : out std_logic; VFBC7_Cmd_Almost_Full : out std_logic; VFBC7_Cmd_Idle : out std_logic; VFBC7_Wd_Clk : in std_logic; VFBC7_Wd_Reset : in std_logic; VFBC7_Wd_Write : in std_logic; VFBC7_Wd_End_Burst : in std_logic; VFBC7_Wd_Flush : in std_logic; VFBC7_Wd_Data : in std_logic_vector(31 downto 0); VFBC7_Wd_Data_BE : in std_logic_vector(3 downto 0); VFBC7_Wd_Full : out std_logic; VFBC7_Wd_Almost_Full : out std_logic; VFBC7_Rd_Clk : in std_logic; VFBC7_Rd_Reset : in std_logic; VFBC7_Rd_Read : in std_logic; VFBC7_Rd_End_Burst : in std_logic; VFBC7_Rd_Flush : in std_logic; VFBC7_Rd_Data : out std_logic_vector(31 downto 0); VFBC7_Rd_Empty : out std_logic; VFBC7_Rd_Almost_Empty : out std_logic; MCB7_cmd_clk : in std_logic; MCB7_cmd_en : in std_logic; MCB7_cmd_instr : in std_logic_vector(2 downto 0); MCB7_cmd_bl : in std_logic_vector(5 downto 0); MCB7_cmd_byte_addr : in std_logic_vector(29 downto 0); MCB7_cmd_empty : out std_logic; MCB7_cmd_full : out std_logic; MCB7_wr_clk : in std_logic; MCB7_wr_en : in std_logic; MCB7_wr_mask : in std_logic_vector(7 downto 0); MCB7_wr_data : in std_logic_vector(63 downto 0); MCB7_wr_full : out std_logic; MCB7_wr_empty : out std_logic; MCB7_wr_count : out std_logic_vector(6 downto 0); MCB7_wr_underrun : out std_logic; MCB7_wr_error : out std_logic; MCB7_rd_clk : in std_logic; MCB7_rd_en : in std_logic; MCB7_rd_data : out std_logic_vector(63 downto 0); MCB7_rd_full : out std_logic; MCB7_rd_empty : out std_logic; MCB7_rd_count : out std_logic_vector(6 downto 0); MCB7_rd_overflow : out std_logic; MCB7_rd_error : out std_logic; MPMC_CTRL_Clk : in std_logic; MPMC_CTRL_Rst : in std_logic; MPMC_CTRL_PLB_ABus : in std_logic_vector(0 to 31); MPMC_CTRL_PLB_PAValid : in std_logic; MPMC_CTRL_PLB_SAValid : in std_logic; MPMC_CTRL_PLB_masterID : in std_logic_vector(0 to 0); MPMC_CTRL_PLB_RNW : in std_logic; MPMC_CTRL_PLB_BE : in std_logic_vector(0 to 7); MPMC_CTRL_PLB_UABus : in std_logic_vector(0 to 31); MPMC_CTRL_PLB_rdPrim : in std_logic; MPMC_CTRL_PLB_wrPrim : in std_logic; MPMC_CTRL_PLB_abort : in std_logic; MPMC_CTRL_PLB_busLock : in std_logic; MPMC_CTRL_PLB_MSize : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_size : in std_logic_vector(0 to 3); MPMC_CTRL_PLB_type : in std_logic_vector(0 to 2); MPMC_CTRL_PLB_lockErr : in std_logic; MPMC_CTRL_PLB_wrPendReq : in std_logic; MPMC_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_rdPendReq : in std_logic; MPMC_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); MPMC_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); MPMC_CTRL_PLB_rdBurst : in std_logic; MPMC_CTRL_PLB_wrBurst : in std_logic; MPMC_CTRL_PLB_wrDBus : in std_logic_vector(0 to 63); MPMC_CTRL_Sl_addrAck : out std_logic; MPMC_CTRL_Sl_SSize : out std_logic_vector(0 to 1); MPMC_CTRL_Sl_wait : out std_logic; MPMC_CTRL_Sl_rearbitrate : out std_logic; MPMC_CTRL_Sl_wrDAck : out std_logic; MPMC_CTRL_Sl_wrComp : out std_logic; MPMC_CTRL_Sl_wrBTerm : out std_logic; MPMC_CTRL_Sl_rdDBus : out std_logic_vector(0 to 63); MPMC_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); MPMC_CTRL_Sl_rdDAck : out std_logic; MPMC_CTRL_Sl_rdComp : out std_logic; MPMC_CTRL_Sl_rdBTerm : out std_logic; MPMC_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); MPMC_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); MPMC_Clk0 : in std_logic; MPMC_Clk0_DIV2 : in std_logic; MPMC_Clk90 : in std_logic; MPMC_Clk_200MHz : in std_logic; MPMC_Rst : in std_logic; MPMC_Clk_Mem : in std_logic; MPMC_Clk_Mem_2x : in std_logic; MPMC_Clk_Mem_2x_180 : in std_logic; MPMC_Clk_Mem_2x_CE0 : in std_logic; MPMC_Clk_Mem_2x_CE90 : in std_logic; MPMC_Clk_Rd_Base : in std_logic; MPMC_Clk_Mem_2x_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_180_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_CE0_bufpll_o : out std_logic; MPMC_Clk_Mem_2x_CE90_bufpll_o : out std_logic; MPMC_PLL_Lock_bufpll_o : out std_logic; MPMC_PLL_Lock : in std_logic; MPMC_Idelayctrl_Rdy_I : in std_logic; MPMC_Idelayctrl_Rdy_O : out std_logic; MPMC_InitDone : out std_logic; MPMC_ECC_Intr : out std_logic; MPMC_DCM_PSEN : out std_logic; MPMC_DCM_PSINCDEC : out std_logic; MPMC_DCM_PSDONE : in std_logic; MPMC_MCB_DRP_Clk : in std_logic; SDRAM_Clk : out std_logic_vector(1 downto 0); SDRAM_CE : out std_logic_vector(1 downto 0); SDRAM_CS_n : out std_logic_vector(1 downto 0); SDRAM_RAS_n : out std_logic; SDRAM_CAS_n : out std_logic; SDRAM_WE_n : out std_logic; SDRAM_BankAddr : out std_logic_vector(1 downto 0); SDRAM_Addr : out std_logic_vector(12 downto 0); SDRAM_DQ : inout std_logic_vector(63 downto 0); SDRAM_DM : out std_logic_vector(7 downto 0); DDR_Clk : out std_logic_vector(1 downto 0); DDR_Clk_n : out std_logic_vector(1 downto 0); DDR_CE : out std_logic_vector(1 downto 0); DDR_CS_n : out std_logic_vector(1 downto 0); DDR_RAS_n : out std_logic; DDR_CAS_n : out std_logic; DDR_WE_n : out std_logic; DDR_BankAddr : out std_logic_vector(1 downto 0); DDR_Addr : out std_logic_vector(12 downto 0); DDR_DQ : inout std_logic_vector(63 downto 0); DDR_DM : out std_logic_vector(7 downto 0); DDR_DQS : inout std_logic_vector(7 downto 0); DDR_DQS_Div_O : out std_logic; DDR_DQS_Div_I : in std_logic; DDR2_Clk : out std_logic_vector(1 downto 0); DDR2_Clk_n : out std_logic_vector(1 downto 0); DDR2_CE : out std_logic_vector(1 downto 0); DDR2_CS_n : out std_logic_vector(1 downto 0); DDR2_ODT : out std_logic_vector(1 downto 0); DDR2_RAS_n : out std_logic; DDR2_CAS_n : out std_logic; DDR2_WE_n : out std_logic; DDR2_BankAddr : out std_logic_vector(1 downto 0); DDR2_Addr : out std_logic_vector(12 downto 0); DDR2_DQ : inout std_logic_vector(63 downto 0); DDR2_DM : out std_logic_vector(7 downto 0); DDR2_DQS : inout std_logic_vector(7 downto 0); DDR2_DQS_n : inout std_logic_vector(7 downto 0); DDR2_DQS_Div_O : out std_logic; DDR2_DQS_Div_I : in std_logic; DDR3_Clk : out std_logic_vector(1 downto 0); DDR3_Clk_n : out std_logic_vector(1 downto 0); DDR3_CE : out std_logic_vector(1 downto 0); DDR3_CS_n : out std_logic_vector(1 downto 0); DDR3_ODT : out std_logic_vector(1 downto 0); DDR3_RAS_n : out std_logic; DDR3_CAS_n : out std_logic; DDR3_WE_n : out std_logic; DDR3_BankAddr : out std_logic_vector(1 downto 0); DDR3_Addr : out std_logic_vector(12 downto 0); DDR3_DQ : inout std_logic_vector(63 downto 0); DDR3_DM : out std_logic_vector(7 downto 0); DDR3_Reset_n : out std_logic; DDR3_DQS : inout std_logic_vector(7 downto 0); DDR3_DQS_n : inout std_logic_vector(7 downto 0); mcbx_dram_addr : out std_logic_vector(12 downto 0); mcbx_dram_ba : out std_logic_vector(1 downto 0); mcbx_dram_ras_n : out std_logic; mcbx_dram_cas_n : out std_logic; mcbx_dram_we_n : out std_logic; mcbx_dram_cke : out std_logic; mcbx_dram_clk : out std_logic; mcbx_dram_clk_n : out std_logic; mcbx_dram_dq : inout std_logic_vector(63 downto 0); mcbx_dram_dqs : inout std_logic; mcbx_dram_dqs_n : inout std_logic; mcbx_dram_udqs : inout std_logic; mcbx_dram_udqs_n : inout std_logic; mcbx_dram_udm : out std_logic; mcbx_dram_ldm : out std_logic; mcbx_dram_odt : out std_logic; mcbx_dram_ddr3_rst : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic; calib_recal : in std_logic; rzq : inout std_logic; zio : inout std_logic ); end component; component system_sram_wrapper is port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to 31); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to 31); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to 31); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to 31); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to 31); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to 31); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to 31); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to 31); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Mem_DQ_I : in std_logic_vector(0 to 31); Mem_DQ_O : out std_logic_vector(0 to 31); Mem_DQ_T : out std_logic_vector(0 to 31); Mem_A : out std_logic_vector(0 to 31); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to 0); Mem_OEN : out std_logic_vector(0 to 0); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to 3); Mem_BEN : out std_logic_vector(0 to 3); Mem_CE : out std_logic_vector(0 to 0); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end component; component system_pcie_bridge_wrapper is port ( MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; PLB_MTimeout : in std_logic; PLB_MIRQ : in std_logic; PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MBusy : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MWrDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrBTerm : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_buslock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_lockErr : out std_logic; M_abort : out std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_UABus : out std_logic_vector(0 to 31); M_ABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to 63); M_wrBurst : out std_logic; M_rdBurst : out std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); REFCLK : in std_logic; Bridge_Clk : out std_logic; RXN : in std_logic_vector(0 to 0); RXP : in std_logic_vector(0 to 0); TXN : out std_logic_vector(0 to 0); TXP : out std_logic_vector(0 to 0); IP2INTC_Irpt : out std_logic; MSI_request : in std_logic ); end component; component system_xps_central_dma_1_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; SPLB_ABus : in std_logic_vector(0 to 31); SPLB_BE : in std_logic_vector(0 to 7); SPLB_UABus : in std_logic_vector(0 to 31); SPLB_PAValid : in std_logic; SPLB_SAValid : in std_logic; SPLB_rdPrim : in std_logic; SPLB_wrPrim : in std_logic; SPLB_masterID : in std_logic_vector(0 to 2); SPLB_abort : in std_logic; SPLB_busLock : in std_logic; SPLB_RNW : in std_logic; SPLB_MSize : in std_logic_vector(0 to 1); SPLB_size : in std_logic_vector(0 to 3); SPLB_type : in std_logic_vector(0 to 2); SPLB_lockErr : in std_logic; SPLB_wrDBus : in std_logic_vector(0 to 63); SPLB_wrBurst : in std_logic; SPLB_rdBurst : in std_logic; SPLB_wrPendReq : in std_logic; SPLB_rdPendReq : in std_logic; SPLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_reqPri : in std_logic_vector(0 to 1); SPLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); IP2INTC_Irpt : out std_logic; MPLB_MAddrAck : in std_logic; MPLB_MSSize : in std_logic_vector(0 to 1); MPLB_MRearbitrate : in std_logic; MPLB_MTimeout : in std_logic; MPLB_MBusy : in std_logic; MPLB_MRdErr : in std_logic; MPLB_MWrErr : in std_logic; MPLB_MIRQ : in std_logic; MPLB_MRdDBus : in std_logic_vector(0 to 63); MPLB_MRdWdAddr : in std_logic_vector(0 to 3); MPLB_MRdDAck : in std_logic; MPLB_MRdBTerm : in std_logic; MPLB_MWrDAck : in std_logic; MPLB_MWrBTerm : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); M_ABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to 63); M_wrBurst : out std_logic; M_rdBurst : out std_logic ); end component; component system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; component system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; component system_proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); end component; component system_xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 63); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 5); Intr : in std_logic_vector(1 downto 0); Irq : out std_logic ); end component; component system_nfa_accept_samples_generic_hw_top_0_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_1_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_2_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_3_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_nfa_accept_samples_generic_hw_top_4_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component system_ac0_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ac0_mb_bridge_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; IP2INTC_Irpt : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 3); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 14); Sl_MWrErr : out std_logic_vector(0 to 14); Sl_MRdErr : out std_logic_vector(0 to 14); Sl_MIRQ : out std_logic_vector(0 to 14); MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_ABus : out std_logic_vector(0 to 31); M_wrBurst : out std_logic; M_rdBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to 63); PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); PLB_MBusy : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdWdAddr : in std_logic_vector(0 to 3) ); end component; component system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; component system_ac1_mb_bridge_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; IP2INTC_Irpt : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 3); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 14); Sl_MWrErr : out std_logic_vector(0 to 14); Sl_MRdErr : out std_logic_vector(0 to 14); Sl_MIRQ : out std_logic_vector(0 to 14); MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to 7); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_ABus : out std_logic_vector(0 to 31); M_wrBurst : out std_logic; M_rdBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to 63); PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to 63); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_UABus : out std_logic_vector(0 to 31); PLB_MBusy : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdWdAddr : in std_logic_vector(0 to 3) ); end component; component system_nfa_accept_samples_generic_hw_top_5_wrapper is port ( aclk : in std_logic; aresetn : in std_logic; indices_MPLB_Clk : in std_logic; indices_MPLB_Rst : in std_logic; indices_M_request : out std_logic; indices_M_priority : out std_logic_vector(0 to 1); indices_M_busLock : out std_logic; indices_M_RNW : out std_logic; indices_M_BE : out std_logic_vector(0 to 7); indices_M_MSize : out std_logic_vector(0 to 1); indices_M_size : out std_logic_vector(0 to 3); indices_M_type : out std_logic_vector(0 to 2); indices_M_TAttribute : out std_logic_vector(0 to 15); indices_M_lockErr : out std_logic; indices_M_abort : out std_logic; indices_M_UABus : out std_logic_vector(0 to 31); indices_M_ABus : out std_logic_vector(0 to 31); indices_M_wrDBus : out std_logic_vector(0 to 63); indices_M_wrBurst : out std_logic; indices_M_rdBurst : out std_logic; indices_PLB_MAddrAck : in std_logic; indices_PLB_MSSize : in std_logic_vector(0 to 1); indices_PLB_MRearbitrate : in std_logic; indices_PLB_MTimeout : in std_logic; indices_PLB_MBusy : in std_logic; indices_PLB_MRdErr : in std_logic; indices_PLB_MWrErr : in std_logic; indices_PLB_MIRQ : in std_logic; indices_PLB_MRdDBus : in std_logic_vector(0 to 63); indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3); indices_PLB_MRdDAck : in std_logic; indices_PLB_MRdBTerm : in std_logic; indices_PLB_MWrDAck : in std_logic; indices_PLB_MWrBTerm : in std_logic; nfa_finals_buckets_MPLB_Clk : in std_logic; nfa_finals_buckets_MPLB_Rst : in std_logic; nfa_finals_buckets_M_request : out std_logic; nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1); nfa_finals_buckets_M_busLock : out std_logic; nfa_finals_buckets_M_RNW : out std_logic; nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7); nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_finals_buckets_M_size : out std_logic_vector(0 to 3); nfa_finals_buckets_M_type : out std_logic_vector(0 to 2); nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_finals_buckets_M_lockErr : out std_logic; nfa_finals_buckets_M_abort : out std_logic; nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_finals_buckets_M_wrBurst : out std_logic; nfa_finals_buckets_M_rdBurst : out std_logic; nfa_finals_buckets_PLB_MAddrAck : in std_logic; nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_finals_buckets_PLB_MRearbitrate : in std_logic; nfa_finals_buckets_PLB_MTimeout : in std_logic; nfa_finals_buckets_PLB_MBusy : in std_logic; nfa_finals_buckets_PLB_MRdErr : in std_logic; nfa_finals_buckets_PLB_MWrErr : in std_logic; nfa_finals_buckets_PLB_MIRQ : in std_logic; nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_finals_buckets_PLB_MRdDAck : in std_logic; nfa_finals_buckets_PLB_MRdBTerm : in std_logic; nfa_finals_buckets_PLB_MWrDAck : in std_logic; nfa_finals_buckets_PLB_MWrBTerm : in std_logic; nfa_forward_buckets_MPLB_Clk : in std_logic; nfa_forward_buckets_MPLB_Rst : in std_logic; nfa_forward_buckets_M_request : out std_logic; nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1); nfa_forward_buckets_M_busLock : out std_logic; nfa_forward_buckets_M_RNW : out std_logic; nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7); nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_forward_buckets_M_size : out std_logic_vector(0 to 3); nfa_forward_buckets_M_type : out std_logic_vector(0 to 2); nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_forward_buckets_M_lockErr : out std_logic; nfa_forward_buckets_M_abort : out std_logic; nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_forward_buckets_M_wrBurst : out std_logic; nfa_forward_buckets_M_rdBurst : out std_logic; nfa_forward_buckets_PLB_MAddrAck : in std_logic; nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_forward_buckets_PLB_MRearbitrate : in std_logic; nfa_forward_buckets_PLB_MTimeout : in std_logic; nfa_forward_buckets_PLB_MBusy : in std_logic; nfa_forward_buckets_PLB_MRdErr : in std_logic; nfa_forward_buckets_PLB_MWrErr : in std_logic; nfa_forward_buckets_PLB_MIRQ : in std_logic; nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_forward_buckets_PLB_MRdDAck : in std_logic; nfa_forward_buckets_PLB_MRdBTerm : in std_logic; nfa_forward_buckets_PLB_MWrDAck : in std_logic; nfa_forward_buckets_PLB_MWrBTerm : in std_logic; nfa_initials_buckets_MPLB_Clk : in std_logic; nfa_initials_buckets_MPLB_Rst : in std_logic; nfa_initials_buckets_M_request : out std_logic; nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1); nfa_initials_buckets_M_busLock : out std_logic; nfa_initials_buckets_M_RNW : out std_logic; nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7); nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1); nfa_initials_buckets_M_size : out std_logic_vector(0 to 3); nfa_initials_buckets_M_type : out std_logic_vector(0 to 2); nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15); nfa_initials_buckets_M_lockErr : out std_logic; nfa_initials_buckets_M_abort : out std_logic; nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31); nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63); nfa_initials_buckets_M_wrBurst : out std_logic; nfa_initials_buckets_M_rdBurst : out std_logic; nfa_initials_buckets_PLB_MAddrAck : in std_logic; nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1); nfa_initials_buckets_PLB_MRearbitrate : in std_logic; nfa_initials_buckets_PLB_MTimeout : in std_logic; nfa_initials_buckets_PLB_MBusy : in std_logic; nfa_initials_buckets_PLB_MRdErr : in std_logic; nfa_initials_buckets_PLB_MWrErr : in std_logic; nfa_initials_buckets_PLB_MIRQ : in std_logic; nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63); nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3); nfa_initials_buckets_PLB_MRdDAck : in std_logic; nfa_initials_buckets_PLB_MRdBTerm : in std_logic; nfa_initials_buckets_PLB_MWrDAck : in std_logic; nfa_initials_buckets_PLB_MWrBTerm : in std_logic; sample_buffer_MPLB_Clk : in std_logic; sample_buffer_MPLB_Rst : in std_logic; sample_buffer_M_request : out std_logic; sample_buffer_M_priority : out std_logic_vector(0 to 1); sample_buffer_M_busLock : out std_logic; sample_buffer_M_RNW : out std_logic; sample_buffer_M_BE : out std_logic_vector(0 to 7); sample_buffer_M_MSize : out std_logic_vector(0 to 1); sample_buffer_M_size : out std_logic_vector(0 to 3); sample_buffer_M_type : out std_logic_vector(0 to 2); sample_buffer_M_TAttribute : out std_logic_vector(0 to 15); sample_buffer_M_lockErr : out std_logic; sample_buffer_M_abort : out std_logic; sample_buffer_M_UABus : out std_logic_vector(0 to 31); sample_buffer_M_ABus : out std_logic_vector(0 to 31); sample_buffer_M_wrDBus : out std_logic_vector(0 to 63); sample_buffer_M_wrBurst : out std_logic; sample_buffer_M_rdBurst : out std_logic; sample_buffer_PLB_MAddrAck : in std_logic; sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1); sample_buffer_PLB_MRearbitrate : in std_logic; sample_buffer_PLB_MTimeout : in std_logic; sample_buffer_PLB_MBusy : in std_logic; sample_buffer_PLB_MRdErr : in std_logic; sample_buffer_PLB_MWrErr : in std_logic; sample_buffer_PLB_MIRQ : in std_logic; sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63); sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3); sample_buffer_PLB_MRdDAck : in std_logic; sample_buffer_PLB_MRdBTerm : in std_logic; sample_buffer_PLB_MWrDAck : in std_logic; sample_buffer_PLB_MWrBTerm : in std_logic; splb_slv0_SPLB_Clk : in std_logic; splb_slv0_SPLB_Rst : in std_logic; splb_slv0_PLB_ABus : in std_logic_vector(0 to 31); splb_slv0_PLB_UABus : in std_logic_vector(0 to 31); splb_slv0_PLB_PAValid : in std_logic; splb_slv0_PLB_SAValid : in std_logic; splb_slv0_PLB_rdPrim : in std_logic; splb_slv0_PLB_wrPrim : in std_logic; splb_slv0_PLB_masterID : in std_logic_vector(0 to 2); splb_slv0_PLB_abort : in std_logic; splb_slv0_PLB_busLock : in std_logic; splb_slv0_PLB_RNW : in std_logic; splb_slv0_PLB_BE : in std_logic_vector(0 to 7); splb_slv0_PLB_MSize : in std_logic_vector(0 to 1); splb_slv0_PLB_size : in std_logic_vector(0 to 3); splb_slv0_PLB_type : in std_logic_vector(0 to 2); splb_slv0_PLB_lockErr : in std_logic; splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63); splb_slv0_PLB_wrBurst : in std_logic; splb_slv0_PLB_rdBurst : in std_logic; splb_slv0_PLB_wrPendReq : in std_logic; splb_slv0_PLB_rdPendReq : in std_logic; splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1); splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1); splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15); splb_slv0_Sl_addrAck : out std_logic; splb_slv0_Sl_SSize : out std_logic_vector(0 to 1); splb_slv0_Sl_wait : out std_logic; splb_slv0_Sl_rearbitrate : out std_logic; splb_slv0_Sl_wrDAck : out std_logic; splb_slv0_Sl_wrComp : out std_logic; splb_slv0_Sl_wrBTerm : out std_logic; splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63); splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3); splb_slv0_Sl_rdDAck : out std_logic; splb_slv0_Sl_rdComp : out std_logic; splb_slv0_Sl_rdBTerm : out std_logic; splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5); splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5); splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5) ); end component; component IOBUF is port ( I : in std_logic; IO : inout std_logic; O : out std_logic; T : in std_logic ); end component; component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- Internal signals signal CLK_S : std_logic; signal Dcm_all_locked : std_logic; signal Debug_SYS_Rst : std_logic; signal Ext_BRK : std_logic; signal Ext_NM_BRK : std_logic; signal PCIe_Bridge_IP2INTC_Irpt : std_logic; signal PCIe_Diff_Clk : std_logic; signal SRAM_CLK_FB_s : std_logic; signal SRAM_CLK_OUT_s : std_logic; signal ac0_plb_MPLB_Rst : std_logic_vector(0 to 14); signal ac0_plb_M_ABus : std_logic_vector(0 to 479); signal ac0_plb_M_BE : std_logic_vector(0 to 119); signal ac0_plb_M_MSize : std_logic_vector(0 to 29); signal ac0_plb_M_RNW : std_logic_vector(0 to 14); signal ac0_plb_M_TAttribute : std_logic_vector(0 to 239); signal ac0_plb_M_UABus : std_logic_vector(0 to 479); signal ac0_plb_M_abort : std_logic_vector(0 to 14); signal ac0_plb_M_busLock : std_logic_vector(0 to 14); signal ac0_plb_M_lockErr : std_logic_vector(0 to 14); signal ac0_plb_M_priority : std_logic_vector(0 to 29); signal ac0_plb_M_rdBurst : std_logic_vector(0 to 14); signal ac0_plb_M_request : std_logic_vector(0 to 14); signal ac0_plb_M_size : std_logic_vector(0 to 59); signal ac0_plb_M_type : std_logic_vector(0 to 44); signal ac0_plb_M_wrBurst : std_logic_vector(0 to 14); signal ac0_plb_M_wrDBus : std_logic_vector(0 to 959); signal ac0_plb_PLB_ABus : std_logic_vector(0 to 31); signal ac0_plb_PLB_BE : std_logic_vector(0 to 7); signal ac0_plb_PLB_MAddrAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MBusy : std_logic_vector(0 to 14); signal ac0_plb_PLB_MIRQ : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdBTerm : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdDAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdDBus : std_logic_vector(0 to 959); signal ac0_plb_PLB_MRdErr : std_logic_vector(0 to 14); signal ac0_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59); signal ac0_plb_PLB_MRearbitrate : std_logic_vector(0 to 14); signal ac0_plb_PLB_MSSize : std_logic_vector(0 to 29); signal ac0_plb_PLB_MSize : std_logic_vector(0 to 1); signal ac0_plb_PLB_MTimeout : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrBTerm : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrDAck : std_logic_vector(0 to 14); signal ac0_plb_PLB_MWrErr : std_logic_vector(0 to 14); signal ac0_plb_PLB_PAValid : std_logic; signal ac0_plb_PLB_RNW : std_logic; signal ac0_plb_PLB_SAValid : std_logic; signal ac0_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal ac0_plb_PLB_UABus : std_logic_vector(0 to 31); signal ac0_plb_PLB_abort : std_logic; signal ac0_plb_PLB_busLock : std_logic; signal ac0_plb_PLB_lockErr : std_logic; signal ac0_plb_PLB_masterID : std_logic_vector(0 to 3); signal ac0_plb_PLB_rdBurst : std_logic; signal ac0_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_rdPendReq : std_logic; signal ac0_plb_PLB_rdPrim : std_logic_vector(0 to 0); signal ac0_plb_PLB_reqPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_size : std_logic_vector(0 to 3); signal ac0_plb_PLB_type : std_logic_vector(0 to 2); signal ac0_plb_PLB_wrBurst : std_logic; signal ac0_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal ac0_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal ac0_plb_PLB_wrPendReq : std_logic; signal ac0_plb_PLB_wrPrim : std_logic_vector(0 to 0); signal ac0_plb_SPLB_Rst : std_logic_vector(0 to 0); signal ac0_plb_Sl_MBusy : std_logic_vector(0 to 14); signal ac0_plb_Sl_MIRQ : std_logic_vector(0 to 14); signal ac0_plb_Sl_MRdErr : std_logic_vector(0 to 14); signal ac0_plb_Sl_MWrErr : std_logic_vector(0 to 14); signal ac0_plb_Sl_SSize : std_logic_vector(0 to 1); signal ac0_plb_Sl_addrAck : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdBTerm : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdComp : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdDAck : std_logic_vector(0 to 0); signal ac0_plb_Sl_rdDBus : std_logic_vector(0 to 63); signal ac0_plb_Sl_rdWdAddr : std_logic_vector(0 to 3); signal ac0_plb_Sl_rearbitrate : std_logic_vector(0 to 0); signal ac0_plb_Sl_wait : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrBTerm : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrComp : std_logic_vector(0 to 0); signal ac0_plb_Sl_wrDAck : std_logic_vector(0 to 0); signal ac1_plb_MPLB_Rst : std_logic_vector(0 to 14); signal ac1_plb_M_ABus : std_logic_vector(0 to 479); signal ac1_plb_M_BE : std_logic_vector(0 to 119); signal ac1_plb_M_MSize : std_logic_vector(0 to 29); signal ac1_plb_M_RNW : std_logic_vector(0 to 14); signal ac1_plb_M_TAttribute : std_logic_vector(0 to 239); signal ac1_plb_M_UABus : std_logic_vector(0 to 479); signal ac1_plb_M_abort : std_logic_vector(0 to 14); signal ac1_plb_M_busLock : std_logic_vector(0 to 14); signal ac1_plb_M_lockErr : std_logic_vector(0 to 14); signal ac1_plb_M_priority : std_logic_vector(0 to 29); signal ac1_plb_M_rdBurst : std_logic_vector(0 to 14); signal ac1_plb_M_request : std_logic_vector(0 to 14); signal ac1_plb_M_size : std_logic_vector(0 to 59); signal ac1_plb_M_type : std_logic_vector(0 to 44); signal ac1_plb_M_wrBurst : std_logic_vector(0 to 14); signal ac1_plb_M_wrDBus : std_logic_vector(0 to 959); signal ac1_plb_PLB_ABus : std_logic_vector(0 to 31); signal ac1_plb_PLB_BE : std_logic_vector(0 to 7); signal ac1_plb_PLB_MAddrAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MBusy : std_logic_vector(0 to 14); signal ac1_plb_PLB_MIRQ : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdBTerm : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdDAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdDBus : std_logic_vector(0 to 959); signal ac1_plb_PLB_MRdErr : std_logic_vector(0 to 14); signal ac1_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59); signal ac1_plb_PLB_MRearbitrate : std_logic_vector(0 to 14); signal ac1_plb_PLB_MSSize : std_logic_vector(0 to 29); signal ac1_plb_PLB_MSize : std_logic_vector(0 to 1); signal ac1_plb_PLB_MTimeout : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrBTerm : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrDAck : std_logic_vector(0 to 14); signal ac1_plb_PLB_MWrErr : std_logic_vector(0 to 14); signal ac1_plb_PLB_PAValid : std_logic; signal ac1_plb_PLB_RNW : std_logic; signal ac1_plb_PLB_SAValid : std_logic; signal ac1_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal ac1_plb_PLB_UABus : std_logic_vector(0 to 31); signal ac1_plb_PLB_abort : std_logic; signal ac1_plb_PLB_busLock : std_logic; signal ac1_plb_PLB_lockErr : std_logic; signal ac1_plb_PLB_masterID : std_logic_vector(0 to 3); signal ac1_plb_PLB_rdBurst : std_logic; signal ac1_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_rdPendReq : std_logic; signal ac1_plb_PLB_rdPrim : std_logic_vector(0 to 0); signal ac1_plb_PLB_reqPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_size : std_logic_vector(0 to 3); signal ac1_plb_PLB_type : std_logic_vector(0 to 2); signal ac1_plb_PLB_wrBurst : std_logic; signal ac1_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal ac1_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal ac1_plb_PLB_wrPendReq : std_logic; signal ac1_plb_PLB_wrPrim : std_logic_vector(0 to 0); signal ac1_plb_SPLB_Rst : std_logic_vector(0 to 0); signal ac1_plb_Sl_MBusy : std_logic_vector(0 to 14); signal ac1_plb_Sl_MIRQ : std_logic_vector(0 to 14); signal ac1_plb_Sl_MRdErr : std_logic_vector(0 to 14); signal ac1_plb_Sl_MWrErr : std_logic_vector(0 to 14); signal ac1_plb_Sl_SSize : std_logic_vector(0 to 1); signal ac1_plb_Sl_addrAck : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdBTerm : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdComp : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdDAck : std_logic_vector(0 to 0); signal ac1_plb_Sl_rdDBus : std_logic_vector(0 to 63); signal ac1_plb_Sl_rdWdAddr : std_logic_vector(0 to 3); signal ac1_plb_Sl_rearbitrate : std_logic_vector(0 to 0); signal ac1_plb_Sl_wait : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrBTerm : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrComp : std_logic_vector(0 to 0); signal ac1_plb_Sl_wrDAck : std_logic_vector(0 to 0); signal clk_62_5000MHzPLL0 : std_logic; signal clk_125_0000MHz90PLL0 : std_logic; signal clk_125_0000MHzPLL0 : std_logic; signal clk_200_0000MHz : std_logic; signal dlmb_LMB_ABus : std_logic_vector(0 to 31); signal dlmb_LMB_AddrStrobe : std_logic; signal dlmb_LMB_BE : std_logic_vector(0 to 3); signal dlmb_LMB_CE : std_logic; signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal dlmb_LMB_ReadStrobe : std_logic; signal dlmb_LMB_Ready : std_logic; signal dlmb_LMB_Rst : std_logic; signal dlmb_LMB_UE : std_logic; signal dlmb_LMB_Wait : std_logic; signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal dlmb_LMB_WriteStrobe : std_logic; signal dlmb_M_ABus : std_logic_vector(0 to 31); signal dlmb_M_AddrStrobe : std_logic; signal dlmb_M_BE : std_logic_vector(0 to 3); signal dlmb_M_DBus : std_logic_vector(0 to 31); signal dlmb_M_ReadStrobe : std_logic; signal dlmb_M_WriteStrobe : std_logic; signal dlmb_Sl_CE : std_logic_vector(0 to 0); signal dlmb_Sl_DBus : std_logic_vector(0 to 31); signal dlmb_Sl_Ready : std_logic_vector(0 to 0); signal dlmb_Sl_UE : std_logic_vector(0 to 0); signal dlmb_Sl_Wait : std_logic_vector(0 to 0); signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Clk : std_logic; signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31); signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal dlmb_port_BRAM_EN : std_logic; signal dlmb_port_BRAM_Rst : std_logic; signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat : std_logic_vector(7 to 30); signal fpga_0_SRAM_Mem_DQ_pin_I : std_logic_vector(0 to 31); signal fpga_0_SRAM_Mem_DQ_pin_O : std_logic_vector(0 to 31); signal fpga_0_SRAM_Mem_DQ_pin_T : std_logic_vector(0 to 31); signal ilmb_LMB_ABus : std_logic_vector(0 to 31); signal ilmb_LMB_AddrStrobe : std_logic; signal ilmb_LMB_BE : std_logic_vector(0 to 3); signal ilmb_LMB_CE : std_logic; signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31); signal ilmb_LMB_ReadStrobe : std_logic; signal ilmb_LMB_Ready : std_logic; signal ilmb_LMB_Rst : std_logic; signal ilmb_LMB_UE : std_logic; signal ilmb_LMB_Wait : std_logic; signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31); signal ilmb_LMB_WriteStrobe : std_logic; signal ilmb_M_ABus : std_logic_vector(0 to 31); signal ilmb_M_AddrStrobe : std_logic; signal ilmb_M_ReadStrobe : std_logic; signal ilmb_Sl_CE : std_logic_vector(0 to 0); signal ilmb_Sl_DBus : std_logic_vector(0 to 31); signal ilmb_Sl_Ready : std_logic_vector(0 to 0); signal ilmb_Sl_UE : std_logic_vector(0 to 0); signal ilmb_Sl_Wait : std_logic_vector(0 to 0); signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Clk : std_logic; signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31); signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31); signal ilmb_port_BRAM_EN : std_logic; signal ilmb_port_BRAM_Rst : std_logic; signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3); signal mb_plb_MPLB_Rst : std_logic_vector(0 to 5); signal mb_plb_M_ABort : std_logic_vector(0 to 5); signal mb_plb_M_ABus : std_logic_vector(0 to 191); signal mb_plb_M_BE : std_logic_vector(0 to 47); signal mb_plb_M_MSize : std_logic_vector(0 to 11); signal mb_plb_M_RNW : std_logic_vector(0 to 5); signal mb_plb_M_TAttribute : std_logic_vector(0 to 95); signal mb_plb_M_UABus : std_logic_vector(0 to 191); signal mb_plb_M_busLock : std_logic_vector(0 to 5); signal mb_plb_M_lockErr : std_logic_vector(0 to 5); signal mb_plb_M_priority : std_logic_vector(0 to 11); signal mb_plb_M_rdBurst : std_logic_vector(0 to 5); signal mb_plb_M_request : std_logic_vector(0 to 5); signal mb_plb_M_size : std_logic_vector(0 to 23); signal mb_plb_M_type : std_logic_vector(0 to 17); signal mb_plb_M_wrBurst : std_logic_vector(0 to 5); signal mb_plb_M_wrDBus : std_logic_vector(0 to 383); signal mb_plb_PLB_ABus : std_logic_vector(0 to 31); signal mb_plb_PLB_BE : std_logic_vector(0 to 7); signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MBusy : std_logic_vector(0 to 5); signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 383); signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 5); signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 23); signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 5); signal mb_plb_PLB_MSSize : std_logic_vector(0 to 11); signal mb_plb_PLB_MSize : std_logic_vector(0 to 1); signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 5); signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 5); signal mb_plb_PLB_PAValid : std_logic; signal mb_plb_PLB_RNW : std_logic; signal mb_plb_PLB_SAValid : std_logic; signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15); signal mb_plb_PLB_UABus : std_logic_vector(0 to 31); signal mb_plb_PLB_abort : std_logic; signal mb_plb_PLB_busLock : std_logic; signal mb_plb_PLB_lockErr : std_logic; signal mb_plb_PLB_masterID : std_logic_vector(0 to 2); signal mb_plb_PLB_rdBurst : std_logic; signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_rdPendReq : std_logic; signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 11); signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1); signal mb_plb_PLB_size : std_logic_vector(0 to 3); signal mb_plb_PLB_type : std_logic_vector(0 to 2); signal mb_plb_PLB_wrBurst : std_logic; signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 63); signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1); signal mb_plb_PLB_wrPendReq : std_logic; signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 11); signal mb_plb_SPLB_Rst : std_logic_vector(0 to 11); signal mb_plb_Sl_MBusy : std_logic_vector(0 to 71); signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 71); signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 71); signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 71); signal mb_plb_Sl_SSize : std_logic_vector(0 to 23); signal mb_plb_Sl_addrAck : std_logic_vector(0 to 11); signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 11); signal mb_plb_Sl_rdComp : std_logic_vector(0 to 11); signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 11); signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 767); signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 47); signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 11); signal mb_plb_Sl_wait : std_logic_vector(0 to 11); signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 11); signal mb_plb_Sl_wrComp : std_logic_vector(0 to 11); signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 11); signal mb_reset : std_logic; signal microblaze_0_Interrupt : std_logic; signal microblaze_0_mdm_bus_Dbg_Capture : std_logic; signal microblaze_0_mdm_bus_Dbg_Clk : std_logic; signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7); signal microblaze_0_mdm_bus_Dbg_Shift : std_logic; signal microblaze_0_mdm_bus_Dbg_TDI : std_logic; signal microblaze_0_mdm_bus_Dbg_TDO : std_logic; signal microblaze_0_mdm_bus_Dbg_Update : std_logic; signal microblaze_0_mdm_bus_Debug_Rst : std_logic; signal net_gnd0 : std_logic; signal net_gnd1 : std_logic_vector(0 downto 0); signal net_gnd2 : std_logic_vector(0 to 1); signal net_gnd3 : std_logic_vector(2 downto 0); signal net_gnd4 : std_logic_vector(0 to 3); signal net_gnd6 : std_logic_vector(5 downto 0); signal net_gnd8 : std_logic_vector(0 to 7); signal net_gnd10 : std_logic_vector(0 to 9); signal net_gnd16 : std_logic_vector(0 to 15); signal net_gnd30 : std_logic_vector(29 downto 0); signal net_gnd32 : std_logic_vector(0 to 31); signal net_gnd36 : std_logic_vector(0 to 35); signal net_gnd64 : std_logic_vector(0 to 63); signal net_gnd128 : std_logic_vector(0 to 127); signal net_gnd4096 : std_logic_vector(0 to 4095); signal net_vcc0 : std_logic; signal net_vcc4 : std_logic_vector(0 to 3); signal pgassign1 : std_logic_vector(0 to 0); signal pgassign2 : std_logic_vector(0 to 0); signal pgassign3 : std_logic_vector(0 to 0); signal pgassign4 : std_logic_vector(0 to 0); signal pgassign5 : std_logic_vector(0 to 0); signal pgassign6 : std_logic_vector(0 to 0); signal pgassign7 : std_logic_vector(0 to 6); signal pgassign8 : std_logic_vector(0 to 0); signal pgassign9 : std_logic_vector(0 to 31); signal pgassign10 : std_logic_vector(1 downto 0); signal proc_sys_reset_0_Peripheral_aresetn : std_logic_vector(0 to 0); signal sys_bus_reset : std_logic_vector(0 to 0); signal sys_periph_reset : std_logic_vector(0 to 0); signal sys_rst_s : std_logic; signal xps_central_dma_1_IP2INTC_Irpt : std_logic; begin -- Internal assignments fpga_0_SRAM_Mem_A_pin <= fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat; fpga_0_SRAM_ZBT_CLK_OUT_pin <= SRAM_CLK_OUT_s; SRAM_CLK_FB_s <= fpga_0_SRAM_ZBT_CLK_FB_pin; CLK_S <= fpga_0_clk_1_sys_clk_pin; sys_rst_s <= fpga_0_rst_1_sys_rst_pin; pgassign7(0 to 6) <= B"0000000"; pgassign8(0 to 0) <= B"0"; fpga_0_SRAM_Mem_CEN_pin <= pgassign1(0); fpga_0_SRAM_Mem_OEN_pin <= pgassign2(0); pgassign3(0) <= fpga_0_PCIe_Bridge_RXN_pin; pgassign4(0) <= fpga_0_PCIe_Bridge_RXP_pin; fpga_0_PCIe_Bridge_TXN_pin <= pgassign5(0); fpga_0_PCIe_Bridge_TXP_pin <= pgassign6(0); fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat(7 to 30) <= pgassign9(7 to 30); pgassign10(1) <= PCIe_Bridge_IP2INTC_Irpt; pgassign10(0) <= xps_central_dma_1_IP2INTC_Irpt; net_gnd0 <= '0'; net_gnd1(0 downto 0) <= B"0"; net_gnd10(0 to 9) <= B"0000000000"; net_gnd128(0 to 127) <= B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; net_gnd16(0 to 15) <= B"0000000000000000"; net_gnd2(0 to 1) <= B"00"; net_gnd3(2 downto 0) <= B"000"; net_gnd30(29 downto 0) <= B"000000000000000000000000000000"; net_gnd32(0 to 31) <= B"00000000000000000000000000000000"; net_gnd36(0 to 35) <= B"000000000000000000000000000000000000"; net_gnd4(0 to 3) <= B"0000"; net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; net_gnd6(5 downto 0) <= B"000000"; net_gnd64(0 to 63) <= B"0000000000000000000000000000000000000000000000000000000000000000"; net_gnd8(0 to 7) <= B"00000000"; net_vcc0 <= '1'; net_vcc4(0 to 3) <= B"1111"; microblaze_0 : system_microblaze_0_wrapper port map ( CLK => clk_125_0000MHzPLL0, RESET => dlmb_LMB_Rst, MB_RESET => mb_reset, INTERRUPT => microblaze_0_Interrupt, INTERRUPT_ADDRESS => net_gnd32, INTERRUPT_ACK => open, EXT_BRK => Ext_BRK, EXT_NM_BRK => Ext_NM_BRK, DBG_STOP => net_gnd0, MB_Halted => open, MB_Error => open, WAKEUP => net_gnd2, SLEEP => open, DBG_WAKEUP => open, LOCKSTEP_MASTER_OUT => open, LOCKSTEP_SLAVE_IN => net_gnd4096, LOCKSTEP_OUT => open, INSTR => ilmb_LMB_ReadDBus, IREADY => ilmb_LMB_Ready, IWAIT => ilmb_LMB_Wait, ICE => ilmb_LMB_CE, IUE => ilmb_LMB_UE, INSTR_ADDR => ilmb_M_ABus, IFETCH => ilmb_M_ReadStrobe, I_AS => ilmb_M_AddrStrobe, IPLB_M_ABort => mb_plb_M_ABort(1), IPLB_M_ABus => mb_plb_M_ABus(32 to 63), IPLB_M_UABus => mb_plb_M_UABus(32 to 63), IPLB_M_BE => mb_plb_M_BE(8 to 15), IPLB_M_busLock => mb_plb_M_busLock(1), IPLB_M_lockErr => mb_plb_M_lockErr(1), IPLB_M_MSize => mb_plb_M_MSize(2 to 3), IPLB_M_priority => mb_plb_M_priority(2 to 3), IPLB_M_rdBurst => mb_plb_M_rdBurst(1), IPLB_M_request => mb_plb_M_request(1), IPLB_M_RNW => mb_plb_M_RNW(1), IPLB_M_size => mb_plb_M_size(4 to 7), IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31), IPLB_M_type => mb_plb_M_type(3 to 5), IPLB_M_wrBurst => mb_plb_M_wrBurst(1), IPLB_M_wrDBus => mb_plb_M_wrDBus(64 to 127), IPLB_MBusy => mb_plb_PLB_MBusy(1), IPLB_MRdErr => mb_plb_PLB_MRdErr(1), IPLB_MWrErr => mb_plb_PLB_MWrErr(1), IPLB_MIRQ => mb_plb_PLB_MIRQ(1), IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1), IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1), IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1), IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1), IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1), IPLB_MRdDBus => mb_plb_PLB_MRdDBus(64 to 127), IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7), IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1), IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3), IPLB_MTimeout => mb_plb_PLB_MTimeout(1), DATA_READ => dlmb_LMB_ReadDBus, DREADY => dlmb_LMB_Ready, DWAIT => dlmb_LMB_Wait, DCE => dlmb_LMB_CE, DUE => dlmb_LMB_UE, DATA_WRITE => dlmb_M_DBus, DATA_ADDR => dlmb_M_ABus, D_AS => dlmb_M_AddrStrobe, READ_STROBE => dlmb_M_ReadStrobe, WRITE_STROBE => dlmb_M_WriteStrobe, BYTE_ENABLE => dlmb_M_BE, DPLB_M_ABort => mb_plb_M_ABort(0), DPLB_M_ABus => mb_plb_M_ABus(0 to 31), DPLB_M_UABus => mb_plb_M_UABus(0 to 31), DPLB_M_BE => mb_plb_M_BE(0 to 7), DPLB_M_busLock => mb_plb_M_busLock(0), DPLB_M_lockErr => mb_plb_M_lockErr(0), DPLB_M_MSize => mb_plb_M_MSize(0 to 1), DPLB_M_priority => mb_plb_M_priority(0 to 1), DPLB_M_rdBurst => mb_plb_M_rdBurst(0), DPLB_M_request => mb_plb_M_request(0), DPLB_M_RNW => mb_plb_M_RNW(0), DPLB_M_size => mb_plb_M_size(0 to 3), DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15), DPLB_M_type => mb_plb_M_type(0 to 2), DPLB_M_wrBurst => mb_plb_M_wrBurst(0), DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 63), DPLB_MBusy => mb_plb_PLB_MBusy(0), DPLB_MRdErr => mb_plb_PLB_MRdErr(0), DPLB_MWrErr => mb_plb_PLB_MWrErr(0), DPLB_MIRQ => mb_plb_PLB_MIRQ(0), DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0), DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0), DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0), DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0), DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0), DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 63), DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3), DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0), DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1), DPLB_MTimeout => mb_plb_PLB_MTimeout(0), M_AXI_IP_AWID => open, M_AXI_IP_AWADDR => open, M_AXI_IP_AWLEN => open, M_AXI_IP_AWSIZE => open, M_AXI_IP_AWBURST => open, M_AXI_IP_AWLOCK => open, M_AXI_IP_AWCACHE => open, M_AXI_IP_AWPROT => open, M_AXI_IP_AWQOS => open, M_AXI_IP_AWVALID => open, M_AXI_IP_AWREADY => net_gnd0, M_AXI_IP_WDATA => open, M_AXI_IP_WSTRB => open, M_AXI_IP_WLAST => open, M_AXI_IP_WVALID => open, M_AXI_IP_WREADY => net_gnd0, M_AXI_IP_BID => net_gnd1(0 downto 0), M_AXI_IP_BRESP => net_gnd2(0 to 1), M_AXI_IP_BVALID => net_gnd0, M_AXI_IP_BREADY => open, M_AXI_IP_ARID => open, M_AXI_IP_ARADDR => open, M_AXI_IP_ARLEN => open, M_AXI_IP_ARSIZE => open, M_AXI_IP_ARBURST => open, M_AXI_IP_ARLOCK => open, M_AXI_IP_ARCACHE => open, M_AXI_IP_ARPROT => open, M_AXI_IP_ARQOS => open, M_AXI_IP_ARVALID => open, M_AXI_IP_ARREADY => net_gnd0, M_AXI_IP_RID => net_gnd1(0 downto 0), M_AXI_IP_RDATA => net_gnd32(0 to 31), M_AXI_IP_RRESP => net_gnd2(0 to 1), M_AXI_IP_RLAST => net_gnd0, M_AXI_IP_RVALID => net_gnd0, M_AXI_IP_RREADY => open, M_AXI_DP_AWID => open, M_AXI_DP_AWADDR => open, M_AXI_DP_AWLEN => open, M_AXI_DP_AWSIZE => open, M_AXI_DP_AWBURST => open, M_AXI_DP_AWLOCK => open, M_AXI_DP_AWCACHE => open, M_AXI_DP_AWPROT => open, M_AXI_DP_AWQOS => open, M_AXI_DP_AWVALID => open, M_AXI_DP_AWREADY => net_gnd0, M_AXI_DP_WDATA => open, M_AXI_DP_WSTRB => open, M_AXI_DP_WLAST => open, M_AXI_DP_WVALID => open, M_AXI_DP_WREADY => net_gnd0, M_AXI_DP_BID => net_gnd1(0 downto 0), M_AXI_DP_BRESP => net_gnd2(0 to 1), M_AXI_DP_BVALID => net_gnd0, M_AXI_DP_BREADY => open, M_AXI_DP_ARID => open, M_AXI_DP_ARADDR => open, M_AXI_DP_ARLEN => open, M_AXI_DP_ARSIZE => open, M_AXI_DP_ARBURST => open, M_AXI_DP_ARLOCK => open, M_AXI_DP_ARCACHE => open, M_AXI_DP_ARPROT => open, M_AXI_DP_ARQOS => open, M_AXI_DP_ARVALID => open, M_AXI_DP_ARREADY => net_gnd0, M_AXI_DP_RID => net_gnd1(0 downto 0), M_AXI_DP_RDATA => net_gnd32(0 to 31), M_AXI_DP_RRESP => net_gnd2(0 to 1), M_AXI_DP_RLAST => net_gnd0, M_AXI_DP_RVALID => net_gnd0, M_AXI_DP_RREADY => open, M_AXI_IC_AWID => open, M_AXI_IC_AWADDR => open, M_AXI_IC_AWLEN => open, M_AXI_IC_AWSIZE => open, M_AXI_IC_AWBURST => open, M_AXI_IC_AWLOCK => open, M_AXI_IC_AWCACHE => open, M_AXI_IC_AWPROT => open, M_AXI_IC_AWQOS => open, M_AXI_IC_AWVALID => open, M_AXI_IC_AWREADY => net_gnd0, M_AXI_IC_AWUSER => open, M_AXI_IC_AWDOMAIN => open, M_AXI_IC_AWSNOOP => open, M_AXI_IC_AWBAR => open, M_AXI_IC_WDATA => open, M_AXI_IC_WSTRB => open, M_AXI_IC_WLAST => open, M_AXI_IC_WVALID => open, M_AXI_IC_WREADY => net_gnd0, M_AXI_IC_WUSER => open, M_AXI_IC_BID => net_gnd1(0 downto 0), M_AXI_IC_BRESP => net_gnd2(0 to 1), M_AXI_IC_BVALID => net_gnd0, M_AXI_IC_BREADY => open, M_AXI_IC_BUSER => net_gnd1(0 downto 0), M_AXI_IC_WACK => open, M_AXI_IC_ARID => open, M_AXI_IC_ARADDR => open, M_AXI_IC_ARLEN => open, M_AXI_IC_ARSIZE => open, M_AXI_IC_ARBURST => open, M_AXI_IC_ARLOCK => open, M_AXI_IC_ARCACHE => open, M_AXI_IC_ARPROT => open, M_AXI_IC_ARQOS => open, M_AXI_IC_ARVALID => open, M_AXI_IC_ARREADY => net_gnd0, M_AXI_IC_ARUSER => open, M_AXI_IC_ARDOMAIN => open, M_AXI_IC_ARSNOOP => open, M_AXI_IC_ARBAR => open, M_AXI_IC_RID => net_gnd1(0 downto 0), M_AXI_IC_RDATA => net_gnd32(0 to 31), M_AXI_IC_RRESP => net_gnd2(0 to 1), M_AXI_IC_RLAST => net_gnd0, M_AXI_IC_RVALID => net_gnd0, M_AXI_IC_RREADY => open, M_AXI_IC_RUSER => net_gnd1(0 downto 0), M_AXI_IC_RACK => open, M_AXI_IC_ACVALID => net_gnd0, M_AXI_IC_ACADDR => net_gnd32(0 to 31), M_AXI_IC_ACSNOOP => net_gnd4(0 to 3), M_AXI_IC_ACPROT => net_gnd3, M_AXI_IC_ACREADY => open, M_AXI_IC_CRREADY => net_gnd0, M_AXI_IC_CRVALID => open, M_AXI_IC_CRRESP => open, M_AXI_IC_CDVALID => open, M_AXI_IC_CDREADY => net_gnd0, M_AXI_IC_CDDATA => open, M_AXI_IC_CDLAST => open, M_AXI_DC_AWID => open, M_AXI_DC_AWADDR => open, M_AXI_DC_AWLEN => open, M_AXI_DC_AWSIZE => open, M_AXI_DC_AWBURST => open, M_AXI_DC_AWLOCK => open, M_AXI_DC_AWCACHE => open, M_AXI_DC_AWPROT => open, M_AXI_DC_AWQOS => open, M_AXI_DC_AWVALID => open, M_AXI_DC_AWREADY => net_gnd0, M_AXI_DC_AWUSER => open, M_AXI_DC_AWDOMAIN => open, M_AXI_DC_AWSNOOP => open, M_AXI_DC_AWBAR => open, M_AXI_DC_WDATA => open, M_AXI_DC_WSTRB => open, M_AXI_DC_WLAST => open, M_AXI_DC_WVALID => open, M_AXI_DC_WREADY => net_gnd0, M_AXI_DC_WUSER => open, M_AXI_DC_BID => net_gnd1(0 downto 0), M_AXI_DC_BRESP => net_gnd2(0 to 1), M_AXI_DC_BVALID => net_gnd0, M_AXI_DC_BREADY => open, M_AXI_DC_BUSER => net_gnd1(0 downto 0), M_AXI_DC_WACK => open, M_AXI_DC_ARID => open, M_AXI_DC_ARADDR => open, M_AXI_DC_ARLEN => open, M_AXI_DC_ARSIZE => open, M_AXI_DC_ARBURST => open, M_AXI_DC_ARLOCK => open, M_AXI_DC_ARCACHE => open, M_AXI_DC_ARPROT => open, M_AXI_DC_ARQOS => open, M_AXI_DC_ARVALID => open, M_AXI_DC_ARREADY => net_gnd0, M_AXI_DC_ARUSER => open, M_AXI_DC_ARDOMAIN => open, M_AXI_DC_ARSNOOP => open, M_AXI_DC_ARBAR => open, M_AXI_DC_RID => net_gnd1(0 downto 0), M_AXI_DC_RDATA => net_gnd32(0 to 31), M_AXI_DC_RRESP => net_gnd2(0 to 1), M_AXI_DC_RLAST => net_gnd0, M_AXI_DC_RVALID => net_gnd0, M_AXI_DC_RREADY => open, M_AXI_DC_RUSER => net_gnd1(0 downto 0), M_AXI_DC_RACK => open, M_AXI_DC_ACVALID => net_gnd0, M_AXI_DC_ACADDR => net_gnd32(0 to 31), M_AXI_DC_ACSNOOP => net_gnd4(0 to 3), M_AXI_DC_ACPROT => net_gnd3, M_AXI_DC_ACREADY => open, M_AXI_DC_CRREADY => net_gnd0, M_AXI_DC_CRVALID => open, M_AXI_DC_CRRESP => open, M_AXI_DC_CDVALID => open, M_AXI_DC_CDREADY => net_gnd0, M_AXI_DC_CDDATA => open, M_AXI_DC_CDLAST => open, DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk, DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI, DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO, DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En, DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift, DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture, DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update, DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst, Trace_Instruction => open, Trace_Valid_Instr => open, Trace_PC => open, Trace_Reg_Write => open, Trace_Reg_Addr => open, Trace_MSR_Reg => open, Trace_PID_Reg => open, Trace_New_Reg_Value => open, Trace_Exception_Taken => open, Trace_Exception_Kind => open, Trace_Jump_Taken => open, Trace_Delay_Slot => open, Trace_Data_Address => open, Trace_Data_Access => open, Trace_Data_Read => open, Trace_Data_Write => open, Trace_Data_Write_Value => open, Trace_Data_Byte_Enable => open, Trace_DCache_Req => open, Trace_DCache_Hit => open, Trace_DCache_Rdy => open, Trace_DCache_Read => open, Trace_ICache_Req => open, Trace_ICache_Hit => open, Trace_ICache_Rdy => open, Trace_OF_PipeRun => open, Trace_EX_PipeRun => open, Trace_MEM_PipeRun => open, Trace_MB_Halted => open, Trace_Jump_Hit => open, FSL0_S_CLK => open, FSL0_S_READ => open, FSL0_S_DATA => net_gnd32, FSL0_S_CONTROL => net_gnd0, FSL0_S_EXISTS => net_gnd0, FSL0_M_CLK => open, FSL0_M_WRITE => open, FSL0_M_DATA => open, FSL0_M_CONTROL => open, FSL0_M_FULL => net_gnd0, FSL1_S_CLK => open, FSL1_S_READ => open, FSL1_S_DATA => net_gnd32, FSL1_S_CONTROL => net_gnd0, FSL1_S_EXISTS => net_gnd0, FSL1_M_CLK => open, FSL1_M_WRITE => open, FSL1_M_DATA => open, FSL1_M_CONTROL => open, FSL1_M_FULL => net_gnd0, FSL2_S_CLK => open, FSL2_S_READ => open, FSL2_S_DATA => net_gnd32, FSL2_S_CONTROL => net_gnd0, FSL2_S_EXISTS => net_gnd0, FSL2_M_CLK => open, FSL2_M_WRITE => open, FSL2_M_DATA => open, FSL2_M_CONTROL => open, FSL2_M_FULL => net_gnd0, FSL3_S_CLK => open, FSL3_S_READ => open, FSL3_S_DATA => net_gnd32, FSL3_S_CONTROL => net_gnd0, FSL3_S_EXISTS => net_gnd0, FSL3_M_CLK => open, FSL3_M_WRITE => open, FSL3_M_DATA => open, FSL3_M_CONTROL => open, FSL3_M_FULL => net_gnd0, FSL4_S_CLK => open, FSL4_S_READ => open, FSL4_S_DATA => net_gnd32, FSL4_S_CONTROL => net_gnd0, FSL4_S_EXISTS => net_gnd0, FSL4_M_CLK => open, FSL4_M_WRITE => open, FSL4_M_DATA => open, FSL4_M_CONTROL => open, FSL4_M_FULL => net_gnd0, FSL5_S_CLK => open, FSL5_S_READ => open, FSL5_S_DATA => net_gnd32, FSL5_S_CONTROL => net_gnd0, FSL5_S_EXISTS => net_gnd0, FSL5_M_CLK => open, FSL5_M_WRITE => open, FSL5_M_DATA => open, FSL5_M_CONTROL => open, FSL5_M_FULL => net_gnd0, FSL6_S_CLK => open, FSL6_S_READ => open, FSL6_S_DATA => net_gnd32, FSL6_S_CONTROL => net_gnd0, FSL6_S_EXISTS => net_gnd0, FSL6_M_CLK => open, FSL6_M_WRITE => open, FSL6_M_DATA => open, FSL6_M_CONTROL => open, FSL6_M_FULL => net_gnd0, FSL7_S_CLK => open, FSL7_S_READ => open, FSL7_S_DATA => net_gnd32, FSL7_S_CONTROL => net_gnd0, FSL7_S_EXISTS => net_gnd0, FSL7_M_CLK => open, FSL7_M_WRITE => open, FSL7_M_DATA => open, FSL7_M_CONTROL => open, FSL7_M_FULL => net_gnd0, FSL8_S_CLK => open, FSL8_S_READ => open, FSL8_S_DATA => net_gnd32, FSL8_S_CONTROL => net_gnd0, FSL8_S_EXISTS => net_gnd0, FSL8_M_CLK => open, FSL8_M_WRITE => open, FSL8_M_DATA => open, FSL8_M_CONTROL => open, FSL8_M_FULL => net_gnd0, FSL9_S_CLK => open, FSL9_S_READ => open, FSL9_S_DATA => net_gnd32, FSL9_S_CONTROL => net_gnd0, FSL9_S_EXISTS => net_gnd0, FSL9_M_CLK => open, FSL9_M_WRITE => open, FSL9_M_DATA => open, FSL9_M_CONTROL => open, FSL9_M_FULL => net_gnd0, FSL10_S_CLK => open, FSL10_S_READ => open, FSL10_S_DATA => net_gnd32, FSL10_S_CONTROL => net_gnd0, FSL10_S_EXISTS => net_gnd0, FSL10_M_CLK => open, FSL10_M_WRITE => open, FSL10_M_DATA => open, FSL10_M_CONTROL => open, FSL10_M_FULL => net_gnd0, FSL11_S_CLK => open, FSL11_S_READ => open, FSL11_S_DATA => net_gnd32, FSL11_S_CONTROL => net_gnd0, FSL11_S_EXISTS => net_gnd0, FSL11_M_CLK => open, FSL11_M_WRITE => open, FSL11_M_DATA => open, FSL11_M_CONTROL => open, FSL11_M_FULL => net_gnd0, FSL12_S_CLK => open, FSL12_S_READ => open, FSL12_S_DATA => net_gnd32, FSL12_S_CONTROL => net_gnd0, FSL12_S_EXISTS => net_gnd0, FSL12_M_CLK => open, FSL12_M_WRITE => open, FSL12_M_DATA => open, FSL12_M_CONTROL => open, FSL12_M_FULL => net_gnd0, FSL13_S_CLK => open, FSL13_S_READ => open, FSL13_S_DATA => net_gnd32, FSL13_S_CONTROL => net_gnd0, FSL13_S_EXISTS => net_gnd0, FSL13_M_CLK => open, FSL13_M_WRITE => open, FSL13_M_DATA => open, FSL13_M_CONTROL => open, FSL13_M_FULL => net_gnd0, FSL14_S_CLK => open, FSL14_S_READ => open, FSL14_S_DATA => net_gnd32, FSL14_S_CONTROL => net_gnd0, FSL14_S_EXISTS => net_gnd0, FSL14_M_CLK => open, FSL14_M_WRITE => open, FSL14_M_DATA => open, FSL14_M_CONTROL => open, FSL14_M_FULL => net_gnd0, FSL15_S_CLK => open, FSL15_S_READ => open, FSL15_S_DATA => net_gnd32, FSL15_S_CONTROL => net_gnd0, FSL15_S_EXISTS => net_gnd0, FSL15_M_CLK => open, FSL15_M_WRITE => open, FSL15_M_DATA => open, FSL15_M_CONTROL => open, FSL15_M_FULL => net_gnd0, M0_AXIS_TLAST => open, M0_AXIS_TDATA => open, M0_AXIS_TVALID => open, M0_AXIS_TREADY => net_gnd0, S0_AXIS_TLAST => net_gnd0, S0_AXIS_TDATA => net_gnd32(0 to 31), S0_AXIS_TVALID => net_gnd0, S0_AXIS_TREADY => open, M1_AXIS_TLAST => open, M1_AXIS_TDATA => open, M1_AXIS_TVALID => open, M1_AXIS_TREADY => net_gnd0, S1_AXIS_TLAST => net_gnd0, S1_AXIS_TDATA => net_gnd32(0 to 31), S1_AXIS_TVALID => net_gnd0, S1_AXIS_TREADY => open, M2_AXIS_TLAST => open, M2_AXIS_TDATA => open, M2_AXIS_TVALID => open, M2_AXIS_TREADY => net_gnd0, S2_AXIS_TLAST => net_gnd0, S2_AXIS_TDATA => net_gnd32(0 to 31), S2_AXIS_TVALID => net_gnd0, S2_AXIS_TREADY => open, M3_AXIS_TLAST => open, M3_AXIS_TDATA => open, M3_AXIS_TVALID => open, M3_AXIS_TREADY => net_gnd0, S3_AXIS_TLAST => net_gnd0, S3_AXIS_TDATA => net_gnd32(0 to 31), S3_AXIS_TVALID => net_gnd0, S3_AXIS_TREADY => open, M4_AXIS_TLAST => open, M4_AXIS_TDATA => open, M4_AXIS_TVALID => open, M4_AXIS_TREADY => net_gnd0, S4_AXIS_TLAST => net_gnd0, S4_AXIS_TDATA => net_gnd32(0 to 31), S4_AXIS_TVALID => net_gnd0, S4_AXIS_TREADY => open, M5_AXIS_TLAST => open, M5_AXIS_TDATA => open, M5_AXIS_TVALID => open, M5_AXIS_TREADY => net_gnd0, S5_AXIS_TLAST => net_gnd0, S5_AXIS_TDATA => net_gnd32(0 to 31), S5_AXIS_TVALID => net_gnd0, S5_AXIS_TREADY => open, M6_AXIS_TLAST => open, M6_AXIS_TDATA => open, M6_AXIS_TVALID => open, M6_AXIS_TREADY => net_gnd0, S6_AXIS_TLAST => net_gnd0, S6_AXIS_TDATA => net_gnd32(0 to 31), S6_AXIS_TVALID => net_gnd0, S6_AXIS_TREADY => open, M7_AXIS_TLAST => open, M7_AXIS_TDATA => open, M7_AXIS_TVALID => open, M7_AXIS_TREADY => net_gnd0, S7_AXIS_TLAST => net_gnd0, S7_AXIS_TDATA => net_gnd32(0 to 31), S7_AXIS_TVALID => net_gnd0, S7_AXIS_TREADY => open, M8_AXIS_TLAST => open, M8_AXIS_TDATA => open, M8_AXIS_TVALID => open, M8_AXIS_TREADY => net_gnd0, S8_AXIS_TLAST => net_gnd0, S8_AXIS_TDATA => net_gnd32(0 to 31), S8_AXIS_TVALID => net_gnd0, S8_AXIS_TREADY => open, M9_AXIS_TLAST => open, M9_AXIS_TDATA => open, M9_AXIS_TVALID => open, M9_AXIS_TREADY => net_gnd0, S9_AXIS_TLAST => net_gnd0, S9_AXIS_TDATA => net_gnd32(0 to 31), S9_AXIS_TVALID => net_gnd0, S9_AXIS_TREADY => open, M10_AXIS_TLAST => open, M10_AXIS_TDATA => open, M10_AXIS_TVALID => open, M10_AXIS_TREADY => net_gnd0, S10_AXIS_TLAST => net_gnd0, S10_AXIS_TDATA => net_gnd32(0 to 31), S10_AXIS_TVALID => net_gnd0, S10_AXIS_TREADY => open, M11_AXIS_TLAST => open, M11_AXIS_TDATA => open, M11_AXIS_TVALID => open, M11_AXIS_TREADY => net_gnd0, S11_AXIS_TLAST => net_gnd0, S11_AXIS_TDATA => net_gnd32(0 to 31), S11_AXIS_TVALID => net_gnd0, S11_AXIS_TREADY => open, M12_AXIS_TLAST => open, M12_AXIS_TDATA => open, M12_AXIS_TVALID => open, M12_AXIS_TREADY => net_gnd0, S12_AXIS_TLAST => net_gnd0, S12_AXIS_TDATA => net_gnd32(0 to 31), S12_AXIS_TVALID => net_gnd0, S12_AXIS_TREADY => open, M13_AXIS_TLAST => open, M13_AXIS_TDATA => open, M13_AXIS_TVALID => open, M13_AXIS_TREADY => net_gnd0, S13_AXIS_TLAST => net_gnd0, S13_AXIS_TDATA => net_gnd32(0 to 31), S13_AXIS_TVALID => net_gnd0, S13_AXIS_TREADY => open, M14_AXIS_TLAST => open, M14_AXIS_TDATA => open, M14_AXIS_TVALID => open, M14_AXIS_TREADY => net_gnd0, S14_AXIS_TLAST => net_gnd0, S14_AXIS_TDATA => net_gnd32(0 to 31), S14_AXIS_TVALID => net_gnd0, S14_AXIS_TREADY => open, M15_AXIS_TLAST => open, M15_AXIS_TDATA => open, M15_AXIS_TVALID => open, M15_AXIS_TREADY => net_gnd0, S15_AXIS_TLAST => net_gnd0, S15_AXIS_TDATA => net_gnd32(0 to 31), S15_AXIS_TVALID => net_gnd0, S15_AXIS_TREADY => open, ICACHE_FSL_IN_CLK => open, ICACHE_FSL_IN_READ => open, ICACHE_FSL_IN_DATA => net_gnd32, ICACHE_FSL_IN_CONTROL => net_gnd0, ICACHE_FSL_IN_EXISTS => net_gnd0, ICACHE_FSL_OUT_CLK => open, ICACHE_FSL_OUT_WRITE => open, ICACHE_FSL_OUT_DATA => open, ICACHE_FSL_OUT_CONTROL => open, ICACHE_FSL_OUT_FULL => net_gnd0, DCACHE_FSL_IN_CLK => open, DCACHE_FSL_IN_READ => open, DCACHE_FSL_IN_DATA => net_gnd32, DCACHE_FSL_IN_CONTROL => net_gnd0, DCACHE_FSL_IN_EXISTS => net_gnd0, DCACHE_FSL_OUT_CLK => open, DCACHE_FSL_OUT_WRITE => open, DCACHE_FSL_OUT_DATA => open, DCACHE_FSL_OUT_CONTROL => open, DCACHE_FSL_OUT_FULL => net_gnd0 ); mb_plb : system_mb_plb_wrapper port map ( PLB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), PLB_Rst => open, SPLB_Rst => mb_plb_SPLB_Rst, MPLB_Rst => mb_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => mb_plb_M_ABus, M_UABus => mb_plb_M_UABus, M_BE => mb_plb_M_BE, M_RNW => mb_plb_M_RNW, M_abort => mb_plb_M_ABort, M_busLock => mb_plb_M_busLock, M_TAttribute => mb_plb_M_TAttribute, M_lockErr => mb_plb_M_lockErr, M_MSize => mb_plb_M_MSize, M_priority => mb_plb_M_priority, M_rdBurst => mb_plb_M_rdBurst, M_request => mb_plb_M_request, M_size => mb_plb_M_size, M_type => mb_plb_M_type, M_wrBurst => mb_plb_M_wrBurst, M_wrDBus => mb_plb_M_wrDBus, Sl_addrAck => mb_plb_Sl_addrAck, Sl_MRdErr => mb_plb_Sl_MRdErr, Sl_MWrErr => mb_plb_Sl_MWrErr, Sl_MBusy => mb_plb_Sl_MBusy, Sl_rdBTerm => mb_plb_Sl_rdBTerm, Sl_rdComp => mb_plb_Sl_rdComp, Sl_rdDAck => mb_plb_Sl_rdDAck, Sl_rdDBus => mb_plb_Sl_rdDBus, Sl_rdWdAddr => mb_plb_Sl_rdWdAddr, Sl_rearbitrate => mb_plb_Sl_rearbitrate, Sl_SSize => mb_plb_Sl_SSize, Sl_wait => mb_plb_Sl_wait, Sl_wrBTerm => mb_plb_Sl_wrBTerm, Sl_wrComp => mb_plb_Sl_wrComp, Sl_wrDAck => mb_plb_Sl_wrDAck, Sl_MIRQ => mb_plb_Sl_MIRQ, PLB_MIRQ => mb_plb_PLB_MIRQ, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_BE => mb_plb_PLB_BE, PLB_MAddrAck => mb_plb_PLB_MAddrAck, PLB_MTimeout => mb_plb_PLB_MTimeout, PLB_MBusy => mb_plb_PLB_MBusy, PLB_MRdErr => mb_plb_PLB_MRdErr, PLB_MWrErr => mb_plb_PLB_MWrErr, PLB_MRdBTerm => mb_plb_PLB_MRdBTerm, PLB_MRdDAck => mb_plb_PLB_MRdDAck, PLB_MRdDBus => mb_plb_PLB_MRdDBus, PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr, PLB_MRearbitrate => mb_plb_PLB_MRearbitrate, PLB_MWrBTerm => mb_plb_PLB_MWrBTerm, PLB_MWrDAck => mb_plb_PLB_MWrDAck, PLB_MSSize => mb_plb_PLB_MSSize, PLB_PAValid => mb_plb_PLB_PAValid, PLB_RNW => mb_plb_PLB_RNW, PLB_SAValid => mb_plb_PLB_SAValid, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_TAttribute => mb_plb_PLB_TAttribute, PLB_lockErr => mb_plb_PLB_lockErr, PLB_masterID => mb_plb_PLB_masterID, PLB_MSize => mb_plb_PLB_MSize, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_rdPrim => mb_plb_PLB_rdPrim, PLB_reqPri => mb_plb_PLB_reqPri, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrPrim => mb_plb_PLB_wrPrim, PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ilmb : system_ilmb_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), LMB_Rst => ilmb_LMB_Rst, M_ABus => ilmb_M_ABus, M_ReadStrobe => ilmb_M_ReadStrobe, M_WriteStrobe => net_gnd0, M_AddrStrobe => ilmb_M_AddrStrobe, M_DBus => net_gnd32, M_BE => net_gnd4, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0 to 0), Sl_Wait => ilmb_Sl_Wait(0 to 0), Sl_UE => ilmb_Sl_UE(0 to 0), Sl_CE => ilmb_Sl_CE(0 to 0), LMB_ABus => ilmb_LMB_ABus, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadDBus => ilmb_LMB_ReadDBus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_Ready => ilmb_LMB_Ready, LMB_Wait => ilmb_LMB_Wait, LMB_UE => ilmb_LMB_UE, LMB_CE => ilmb_LMB_CE, LMB_BE => ilmb_LMB_BE ); dlmb : system_dlmb_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, SYS_Rst => sys_bus_reset(0), LMB_Rst => dlmb_LMB_Rst, M_ABus => dlmb_M_ABus, M_ReadStrobe => dlmb_M_ReadStrobe, M_WriteStrobe => dlmb_M_WriteStrobe, M_AddrStrobe => dlmb_M_AddrStrobe, M_DBus => dlmb_M_DBus, M_BE => dlmb_M_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0 to 0), Sl_Wait => dlmb_Sl_Wait(0 to 0), Sl_UE => dlmb_Sl_UE(0 to 0), Sl_CE => dlmb_Sl_CE(0 to 0), LMB_ABus => dlmb_LMB_ABus, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadDBus => dlmb_LMB_ReadDBus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_Ready => dlmb_LMB_Ready, LMB_Wait => dlmb_LMB_Wait, LMB_UE => dlmb_LMB_UE, LMB_CE => dlmb_LMB_CE, LMB_BE => dlmb_LMB_BE ); dlmb_cntlr : system_dlmb_cntlr_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, LMB_Rst => dlmb_LMB_Rst, LMB_ABus => dlmb_LMB_ABus, LMB_WriteDBus => dlmb_LMB_WriteDBus, LMB_AddrStrobe => dlmb_LMB_AddrStrobe, LMB_ReadStrobe => dlmb_LMB_ReadStrobe, LMB_WriteStrobe => dlmb_LMB_WriteStrobe, LMB_BE => dlmb_LMB_BE, Sl_DBus => dlmb_Sl_DBus, Sl_Ready => dlmb_Sl_Ready(0), Sl_Wait => dlmb_Sl_Wait(0), Sl_UE => dlmb_Sl_UE(0), Sl_CE => dlmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => dlmb_port_BRAM_Rst, BRAM_Clk_A => dlmb_port_BRAM_Clk, BRAM_EN_A => dlmb_port_BRAM_EN, BRAM_WEN_A => dlmb_port_BRAM_WEN, BRAM_Addr_A => dlmb_port_BRAM_Addr, BRAM_Din_A => dlmb_port_BRAM_Din, BRAM_Dout_A => dlmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); ilmb_cntlr : system_ilmb_cntlr_wrapper port map ( LMB_Clk => clk_125_0000MHzPLL0, LMB_Rst => ilmb_LMB_Rst, LMB_ABus => ilmb_LMB_ABus, LMB_WriteDBus => ilmb_LMB_WriteDBus, LMB_AddrStrobe => ilmb_LMB_AddrStrobe, LMB_ReadStrobe => ilmb_LMB_ReadStrobe, LMB_WriteStrobe => ilmb_LMB_WriteStrobe, LMB_BE => ilmb_LMB_BE, Sl_DBus => ilmb_Sl_DBus, Sl_Ready => ilmb_Sl_Ready(0), Sl_Wait => ilmb_Sl_Wait(0), Sl_UE => ilmb_Sl_UE(0), Sl_CE => ilmb_Sl_CE(0), LMB1_ABus => net_gnd32, LMB1_WriteDBus => net_gnd32, LMB1_AddrStrobe => net_gnd0, LMB1_ReadStrobe => net_gnd0, LMB1_WriteStrobe => net_gnd0, LMB1_BE => net_gnd4, Sl1_DBus => open, Sl1_Ready => open, Sl1_Wait => open, Sl1_UE => open, Sl1_CE => open, LMB2_ABus => net_gnd32, LMB2_WriteDBus => net_gnd32, LMB2_AddrStrobe => net_gnd0, LMB2_ReadStrobe => net_gnd0, LMB2_WriteStrobe => net_gnd0, LMB2_BE => net_gnd4, Sl2_DBus => open, Sl2_Ready => open, Sl2_Wait => open, Sl2_UE => open, Sl2_CE => open, LMB3_ABus => net_gnd32, LMB3_WriteDBus => net_gnd32, LMB3_AddrStrobe => net_gnd0, LMB3_ReadStrobe => net_gnd0, LMB3_WriteStrobe => net_gnd0, LMB3_BE => net_gnd4, Sl3_DBus => open, Sl3_Ready => open, Sl3_Wait => open, Sl3_UE => open, Sl3_CE => open, BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, Interrupt => open, UE => open, CE => open, SPLB_CTRL_PLB_ABus => net_gnd32, SPLB_CTRL_PLB_PAValid => net_gnd0, SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0), SPLB_CTRL_PLB_RNW => net_gnd0, SPLB_CTRL_PLB_BE => net_gnd4, SPLB_CTRL_PLB_size => net_gnd4, SPLB_CTRL_PLB_type => net_gnd3(2 downto 0), SPLB_CTRL_PLB_wrDBus => net_gnd32, SPLB_CTRL_Sl_addrAck => open, SPLB_CTRL_Sl_SSize => open, SPLB_CTRL_Sl_wait => open, SPLB_CTRL_Sl_rearbitrate => open, SPLB_CTRL_Sl_wrDAck => open, SPLB_CTRL_Sl_wrComp => open, SPLB_CTRL_Sl_rdDBus => open, SPLB_CTRL_Sl_rdDAck => open, SPLB_CTRL_Sl_rdComp => open, SPLB_CTRL_Sl_MBusy => open, SPLB_CTRL_Sl_MWrErr => open, SPLB_CTRL_Sl_MRdErr => open, SPLB_CTRL_PLB_UABus => net_gnd32, SPLB_CTRL_PLB_SAValid => net_gnd0, SPLB_CTRL_PLB_rdPrim => net_gnd0, SPLB_CTRL_PLB_wrPrim => net_gnd0, SPLB_CTRL_PLB_abort => net_gnd0, SPLB_CTRL_PLB_busLock => net_gnd0, SPLB_CTRL_PLB_MSize => net_gnd2, SPLB_CTRL_PLB_lockErr => net_gnd0, SPLB_CTRL_PLB_wrBurst => net_gnd0, SPLB_CTRL_PLB_rdBurst => net_gnd0, SPLB_CTRL_PLB_wrPendReq => net_gnd0, SPLB_CTRL_PLB_rdPendReq => net_gnd0, SPLB_CTRL_PLB_wrPendPri => net_gnd2, SPLB_CTRL_PLB_rdPendPri => net_gnd2, SPLB_CTRL_PLB_reqPri => net_gnd2, SPLB_CTRL_PLB_TAttribute => net_gnd16, SPLB_CTRL_Sl_wrBTerm => open, SPLB_CTRL_Sl_rdWdAddr => open, SPLB_CTRL_Sl_rdBTerm => open, SPLB_CTRL_Sl_MIRQ => open, S_AXI_CTRL_ACLK => net_vcc0, S_AXI_CTRL_ARESETN => net_gnd0, S_AXI_CTRL_AWADDR => net_gnd32(0 to 31), S_AXI_CTRL_AWVALID => net_gnd0, S_AXI_CTRL_AWREADY => open, S_AXI_CTRL_WDATA => net_gnd32(0 to 31), S_AXI_CTRL_WSTRB => net_gnd4(0 to 3), S_AXI_CTRL_WVALID => net_gnd0, S_AXI_CTRL_WREADY => open, S_AXI_CTRL_BRESP => open, S_AXI_CTRL_BVALID => open, S_AXI_CTRL_BREADY => net_gnd0, S_AXI_CTRL_ARADDR => net_gnd32(0 to 31), S_AXI_CTRL_ARVALID => net_gnd0, S_AXI_CTRL_ARREADY => open, S_AXI_CTRL_RDATA => open, S_AXI_CTRL_RRESP => open, S_AXI_CTRL_RVALID => open, S_AXI_CTRL_RREADY => net_gnd0 ); lmb_bram : system_lmb_bram_wrapper port map ( BRAM_Rst_A => ilmb_port_BRAM_Rst, BRAM_Clk_A => ilmb_port_BRAM_Clk, BRAM_EN_A => ilmb_port_BRAM_EN, BRAM_WEN_A => ilmb_port_BRAM_WEN, BRAM_Addr_A => ilmb_port_BRAM_Addr, BRAM_Din_A => ilmb_port_BRAM_Din, BRAM_Dout_A => ilmb_port_BRAM_Dout, BRAM_Rst_B => dlmb_port_BRAM_Rst, BRAM_Clk_B => dlmb_port_BRAM_Clk, BRAM_EN_B => dlmb_port_BRAM_EN, BRAM_WEN_B => dlmb_port_BRAM_WEN, BRAM_Addr_B => dlmb_port_BRAM_Addr, BRAM_Din_B => dlmb_port_BRAM_Din, BRAM_Dout_B => dlmb_port_BRAM_Dout ); DDR2_SDRAM : system_ddr2_sdram_wrapper port map ( FSL0_M_Clk => net_vcc0, FSL0_M_Write => net_gnd0, FSL0_M_Data => net_gnd32, FSL0_M_Control => net_gnd0, FSL0_M_Full => open, FSL0_S_Clk => net_gnd0, FSL0_S_Read => net_gnd0, FSL0_S_Data => open, FSL0_S_Control => open, FSL0_S_Exists => open, FSL0_B_M_Clk => net_vcc0, FSL0_B_M_Write => net_gnd0, FSL0_B_M_Data => net_gnd32, FSL0_B_M_Control => net_gnd0, FSL0_B_M_Full => open, FSL0_B_S_Clk => net_gnd0, FSL0_B_S_Read => net_gnd0, FSL0_B_S_Data => open, FSL0_B_S_Control => open, FSL0_B_S_Exists => open, SPLB0_Clk => clk_125_0000MHzPLL0, SPLB0_Rst => mb_plb_SPLB_Rst(0), SPLB0_PLB_ABus => mb_plb_PLB_ABus, SPLB0_PLB_PAValid => mb_plb_PLB_PAValid, SPLB0_PLB_SAValid => mb_plb_PLB_SAValid, SPLB0_PLB_masterID => mb_plb_PLB_masterID, SPLB0_PLB_RNW => mb_plb_PLB_RNW, SPLB0_PLB_BE => mb_plb_PLB_BE, SPLB0_PLB_UABus => mb_plb_PLB_UABus, SPLB0_PLB_rdPrim => mb_plb_PLB_rdPrim(0), SPLB0_PLB_wrPrim => mb_plb_PLB_wrPrim(0), SPLB0_PLB_abort => mb_plb_PLB_abort, SPLB0_PLB_busLock => mb_plb_PLB_busLock, SPLB0_PLB_MSize => mb_plb_PLB_MSize, SPLB0_PLB_size => mb_plb_PLB_size, SPLB0_PLB_type => mb_plb_PLB_type, SPLB0_PLB_lockErr => mb_plb_PLB_lockErr, SPLB0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, SPLB0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, SPLB0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, SPLB0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, SPLB0_PLB_reqPri => mb_plb_PLB_reqPri, SPLB0_PLB_TAttribute => mb_plb_PLB_TAttribute, SPLB0_PLB_rdBurst => mb_plb_PLB_rdBurst, SPLB0_PLB_wrBurst => mb_plb_PLB_wrBurst, SPLB0_PLB_wrDBus => mb_plb_PLB_wrDBus, SPLB0_Sl_addrAck => mb_plb_Sl_addrAck(0), SPLB0_Sl_SSize => mb_plb_Sl_SSize(0 to 1), SPLB0_Sl_wait => mb_plb_Sl_wait(0), SPLB0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(0), SPLB0_Sl_wrDAck => mb_plb_Sl_wrDAck(0), SPLB0_Sl_wrComp => mb_plb_Sl_wrComp(0), SPLB0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(0), SPLB0_Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 63), SPLB0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3), SPLB0_Sl_rdDAck => mb_plb_Sl_rdDAck(0), SPLB0_Sl_rdComp => mb_plb_Sl_rdComp(0), SPLB0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(0), SPLB0_Sl_MBusy => mb_plb_Sl_MBusy(0 to 5), SPLB0_Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 5), SPLB0_Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 5), SPLB0_Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 5), SDMA0_Clk => net_gnd0, SDMA0_Rx_IntOut => open, SDMA0_Tx_IntOut => open, SDMA0_RstOut => open, SDMA0_TX_D => open, SDMA0_TX_Rem => open, SDMA0_TX_SOF => open, SDMA0_TX_EOF => open, SDMA0_TX_SOP => open, SDMA0_TX_EOP => open, SDMA0_TX_Src_Rdy => open, SDMA0_TX_Dst_Rdy => net_vcc0, SDMA0_RX_D => net_gnd32, SDMA0_RX_Rem => net_vcc4, SDMA0_RX_SOF => net_vcc0, SDMA0_RX_EOF => net_vcc0, SDMA0_RX_SOP => net_vcc0, SDMA0_RX_EOP => net_vcc0, SDMA0_RX_Src_Rdy => net_vcc0, SDMA0_RX_Dst_Rdy => open, SDMA_CTRL0_Clk => net_vcc0, SDMA_CTRL0_Rst => net_gnd0, SDMA_CTRL0_PLB_ABus => net_gnd32, SDMA_CTRL0_PLB_PAValid => net_gnd0, SDMA_CTRL0_PLB_SAValid => net_gnd0, SDMA_CTRL0_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL0_PLB_RNW => net_gnd0, SDMA_CTRL0_PLB_BE => net_gnd8, SDMA_CTRL0_PLB_UABus => net_gnd32, SDMA_CTRL0_PLB_rdPrim => net_gnd0, SDMA_CTRL0_PLB_wrPrim => net_gnd0, SDMA_CTRL0_PLB_abort => net_gnd0, SDMA_CTRL0_PLB_busLock => net_gnd0, SDMA_CTRL0_PLB_MSize => net_gnd2, SDMA_CTRL0_PLB_size => net_gnd4, SDMA_CTRL0_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL0_PLB_lockErr => net_gnd0, SDMA_CTRL0_PLB_wrPendReq => net_gnd0, SDMA_CTRL0_PLB_wrPendPri => net_gnd2, SDMA_CTRL0_PLB_rdPendReq => net_gnd0, SDMA_CTRL0_PLB_rdPendPri => net_gnd2, SDMA_CTRL0_PLB_reqPri => net_gnd2, SDMA_CTRL0_PLB_TAttribute => net_gnd16, SDMA_CTRL0_PLB_rdBurst => net_gnd0, SDMA_CTRL0_PLB_wrBurst => net_gnd0, SDMA_CTRL0_PLB_wrDBus => net_gnd64, SDMA_CTRL0_Sl_addrAck => open, SDMA_CTRL0_Sl_SSize => open, SDMA_CTRL0_Sl_wait => open, SDMA_CTRL0_Sl_rearbitrate => open, SDMA_CTRL0_Sl_wrDAck => open, SDMA_CTRL0_Sl_wrComp => open, SDMA_CTRL0_Sl_wrBTerm => open, SDMA_CTRL0_Sl_rdDBus => open, SDMA_CTRL0_Sl_rdWdAddr => open, SDMA_CTRL0_Sl_rdDAck => open, SDMA_CTRL0_Sl_rdComp => open, SDMA_CTRL0_Sl_rdBTerm => open, SDMA_CTRL0_Sl_MBusy => open, SDMA_CTRL0_Sl_MRdErr => open, SDMA_CTRL0_Sl_MWrErr => open, SDMA_CTRL0_Sl_MIRQ => open, PIM0_Addr => net_gnd32(0 to 31), PIM0_AddrReq => net_gnd0, PIM0_AddrAck => open, PIM0_RNW => net_gnd0, PIM0_Size => net_gnd4(0 to 3), PIM0_RdModWr => net_gnd0, PIM0_WrFIFO_Data => net_gnd64(0 to 63), PIM0_WrFIFO_BE => net_gnd8(0 to 7), PIM0_WrFIFO_Push => net_gnd0, PIM0_RdFIFO_Data => open, PIM0_RdFIFO_Pop => net_gnd0, PIM0_RdFIFO_RdWdAddr => open, PIM0_WrFIFO_Empty => open, PIM0_WrFIFO_AlmostFull => open, PIM0_WrFIFO_Flush => net_gnd0, PIM0_RdFIFO_Empty => open, PIM0_RdFIFO_Flush => net_gnd0, PIM0_RdFIFO_Latency => open, PIM0_InitDone => open, PPC440MC0_MIMCReadNotWrite => net_gnd0, PPC440MC0_MIMCAddress => net_gnd36, PPC440MC0_MIMCAddressValid => net_gnd0, PPC440MC0_MIMCWriteData => net_gnd128, PPC440MC0_MIMCWriteDataValid => net_gnd0, PPC440MC0_MIMCByteEnable => net_gnd16, PPC440MC0_MIMCBankConflict => net_gnd0, PPC440MC0_MIMCRowConflict => net_gnd0, PPC440MC0_MCMIReadData => open, PPC440MC0_MCMIReadDataValid => open, PPC440MC0_MCMIReadDataErr => open, PPC440MC0_MCMIAddrReadyToAccept => open, VFBC0_Cmd_Clk => net_gnd0, VFBC0_Cmd_Reset => net_gnd0, VFBC0_Cmd_Data => net_gnd32(0 to 31), VFBC0_Cmd_Write => net_gnd0, VFBC0_Cmd_End => net_gnd0, VFBC0_Cmd_Full => open, VFBC0_Cmd_Almost_Full => open, VFBC0_Cmd_Idle => open, VFBC0_Wd_Clk => net_gnd0, VFBC0_Wd_Reset => net_gnd0, VFBC0_Wd_Write => net_gnd0, VFBC0_Wd_End_Burst => net_gnd0, VFBC0_Wd_Flush => net_gnd0, VFBC0_Wd_Data => net_gnd32(0 to 31), VFBC0_Wd_Data_BE => net_gnd4(0 to 3), VFBC0_Wd_Full => open, VFBC0_Wd_Almost_Full => open, VFBC0_Rd_Clk => net_gnd0, VFBC0_Rd_Reset => net_gnd0, VFBC0_Rd_Read => net_gnd0, VFBC0_Rd_End_Burst => net_gnd0, VFBC0_Rd_Flush => net_gnd0, VFBC0_Rd_Data => open, VFBC0_Rd_Empty => open, VFBC0_Rd_Almost_Empty => open, MCB0_cmd_clk => net_gnd0, MCB0_cmd_en => net_gnd0, MCB0_cmd_instr => net_gnd3, MCB0_cmd_bl => net_gnd6, MCB0_cmd_byte_addr => net_gnd30, MCB0_cmd_empty => open, MCB0_cmd_full => open, MCB0_wr_clk => net_gnd0, MCB0_wr_en => net_gnd0, MCB0_wr_mask => net_gnd8(0 to 7), MCB0_wr_data => net_gnd64(0 to 63), MCB0_wr_full => open, MCB0_wr_empty => open, MCB0_wr_count => open, MCB0_wr_underrun => open, MCB0_wr_error => open, MCB0_rd_clk => net_gnd0, MCB0_rd_en => net_gnd0, MCB0_rd_data => open, MCB0_rd_full => open, MCB0_rd_empty => open, MCB0_rd_count => open, MCB0_rd_overflow => open, MCB0_rd_error => open, FSL1_M_Clk => net_vcc0, FSL1_M_Write => net_gnd0, FSL1_M_Data => net_gnd32, FSL1_M_Control => net_gnd0, FSL1_M_Full => open, FSL1_S_Clk => net_gnd0, FSL1_S_Read => net_gnd0, FSL1_S_Data => open, FSL1_S_Control => open, FSL1_S_Exists => open, FSL1_B_M_Clk => net_vcc0, FSL1_B_M_Write => net_gnd0, FSL1_B_M_Data => net_gnd32, FSL1_B_M_Control => net_gnd0, FSL1_B_M_Full => open, FSL1_B_S_Clk => net_gnd0, FSL1_B_S_Read => net_gnd0, FSL1_B_S_Data => open, FSL1_B_S_Control => open, FSL1_B_S_Exists => open, SPLB1_Clk => net_vcc0, SPLB1_Rst => net_gnd0, SPLB1_PLB_ABus => net_gnd32, SPLB1_PLB_PAValid => net_gnd0, SPLB1_PLB_SAValid => net_gnd0, SPLB1_PLB_masterID => net_gnd1(0 downto 0), SPLB1_PLB_RNW => net_gnd0, SPLB1_PLB_BE => net_gnd8, SPLB1_PLB_UABus => net_gnd32, SPLB1_PLB_rdPrim => net_gnd0, SPLB1_PLB_wrPrim => net_gnd0, SPLB1_PLB_abort => net_gnd0, SPLB1_PLB_busLock => net_gnd0, SPLB1_PLB_MSize => net_gnd2, SPLB1_PLB_size => net_gnd4, SPLB1_PLB_type => net_gnd3(2 downto 0), SPLB1_PLB_lockErr => net_gnd0, SPLB1_PLB_wrPendReq => net_gnd0, SPLB1_PLB_wrPendPri => net_gnd2, SPLB1_PLB_rdPendReq => net_gnd0, SPLB1_PLB_rdPendPri => net_gnd2, SPLB1_PLB_reqPri => net_gnd2, SPLB1_PLB_TAttribute => net_gnd16, SPLB1_PLB_rdBurst => net_gnd0, SPLB1_PLB_wrBurst => net_gnd0, SPLB1_PLB_wrDBus => net_gnd64, SPLB1_Sl_addrAck => open, SPLB1_Sl_SSize => open, SPLB1_Sl_wait => open, SPLB1_Sl_rearbitrate => open, SPLB1_Sl_wrDAck => open, SPLB1_Sl_wrComp => open, SPLB1_Sl_wrBTerm => open, SPLB1_Sl_rdDBus => open, SPLB1_Sl_rdWdAddr => open, SPLB1_Sl_rdDAck => open, SPLB1_Sl_rdComp => open, SPLB1_Sl_rdBTerm => open, SPLB1_Sl_MBusy => open, SPLB1_Sl_MRdErr => open, SPLB1_Sl_MWrErr => open, SPLB1_Sl_MIRQ => open, SDMA1_Clk => net_gnd0, SDMA1_Rx_IntOut => open, SDMA1_Tx_IntOut => open, SDMA1_RstOut => open, SDMA1_TX_D => open, SDMA1_TX_Rem => open, SDMA1_TX_SOF => open, SDMA1_TX_EOF => open, SDMA1_TX_SOP => open, SDMA1_TX_EOP => open, SDMA1_TX_Src_Rdy => open, SDMA1_TX_Dst_Rdy => net_vcc0, SDMA1_RX_D => net_gnd32, SDMA1_RX_Rem => net_vcc4, SDMA1_RX_SOF => net_vcc0, SDMA1_RX_EOF => net_vcc0, SDMA1_RX_SOP => net_vcc0, SDMA1_RX_EOP => net_vcc0, SDMA1_RX_Src_Rdy => net_vcc0, SDMA1_RX_Dst_Rdy => open, SDMA_CTRL1_Clk => net_vcc0, SDMA_CTRL1_Rst => net_gnd0, SDMA_CTRL1_PLB_ABus => net_gnd32, SDMA_CTRL1_PLB_PAValid => net_gnd0, SDMA_CTRL1_PLB_SAValid => net_gnd0, SDMA_CTRL1_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL1_PLB_RNW => net_gnd0, SDMA_CTRL1_PLB_BE => net_gnd8, SDMA_CTRL1_PLB_UABus => net_gnd32, SDMA_CTRL1_PLB_rdPrim => net_gnd0, SDMA_CTRL1_PLB_wrPrim => net_gnd0, SDMA_CTRL1_PLB_abort => net_gnd0, SDMA_CTRL1_PLB_busLock => net_gnd0, SDMA_CTRL1_PLB_MSize => net_gnd2, SDMA_CTRL1_PLB_size => net_gnd4, SDMA_CTRL1_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL1_PLB_lockErr => net_gnd0, SDMA_CTRL1_PLB_wrPendReq => net_gnd0, SDMA_CTRL1_PLB_wrPendPri => net_gnd2, SDMA_CTRL1_PLB_rdPendReq => net_gnd0, SDMA_CTRL1_PLB_rdPendPri => net_gnd2, SDMA_CTRL1_PLB_reqPri => net_gnd2, SDMA_CTRL1_PLB_TAttribute => net_gnd16, SDMA_CTRL1_PLB_rdBurst => net_gnd0, SDMA_CTRL1_PLB_wrBurst => net_gnd0, SDMA_CTRL1_PLB_wrDBus => net_gnd64, SDMA_CTRL1_Sl_addrAck => open, SDMA_CTRL1_Sl_SSize => open, SDMA_CTRL1_Sl_wait => open, SDMA_CTRL1_Sl_rearbitrate => open, SDMA_CTRL1_Sl_wrDAck => open, SDMA_CTRL1_Sl_wrComp => open, SDMA_CTRL1_Sl_wrBTerm => open, SDMA_CTRL1_Sl_rdDBus => open, SDMA_CTRL1_Sl_rdWdAddr => open, SDMA_CTRL1_Sl_rdDAck => open, SDMA_CTRL1_Sl_rdComp => open, SDMA_CTRL1_Sl_rdBTerm => open, SDMA_CTRL1_Sl_MBusy => open, SDMA_CTRL1_Sl_MRdErr => open, SDMA_CTRL1_Sl_MWrErr => open, SDMA_CTRL1_Sl_MIRQ => open, PIM1_Addr => net_gnd32(0 to 31), PIM1_AddrReq => net_gnd0, PIM1_AddrAck => open, PIM1_RNW => net_gnd0, PIM1_Size => net_gnd4(0 to 3), PIM1_RdModWr => net_gnd0, PIM1_WrFIFO_Data => net_gnd64(0 to 63), PIM1_WrFIFO_BE => net_gnd8(0 to 7), PIM1_WrFIFO_Push => net_gnd0, PIM1_RdFIFO_Data => open, PIM1_RdFIFO_Pop => net_gnd0, PIM1_RdFIFO_RdWdAddr => open, PIM1_WrFIFO_Empty => open, PIM1_WrFIFO_AlmostFull => open, PIM1_WrFIFO_Flush => net_gnd0, PIM1_RdFIFO_Empty => open, PIM1_RdFIFO_Flush => net_gnd0, PIM1_RdFIFO_Latency => open, PIM1_InitDone => open, PPC440MC1_MIMCReadNotWrite => net_gnd0, PPC440MC1_MIMCAddress => net_gnd36, PPC440MC1_MIMCAddressValid => net_gnd0, PPC440MC1_MIMCWriteData => net_gnd128, PPC440MC1_MIMCWriteDataValid => net_gnd0, PPC440MC1_MIMCByteEnable => net_gnd16, PPC440MC1_MIMCBankConflict => net_gnd0, PPC440MC1_MIMCRowConflict => net_gnd0, PPC440MC1_MCMIReadData => open, PPC440MC1_MCMIReadDataValid => open, PPC440MC1_MCMIReadDataErr => open, PPC440MC1_MCMIAddrReadyToAccept => open, VFBC1_Cmd_Clk => net_gnd0, VFBC1_Cmd_Reset => net_gnd0, VFBC1_Cmd_Data => net_gnd32(0 to 31), VFBC1_Cmd_Write => net_gnd0, VFBC1_Cmd_End => net_gnd0, VFBC1_Cmd_Full => open, VFBC1_Cmd_Almost_Full => open, VFBC1_Cmd_Idle => open, VFBC1_Wd_Clk => net_gnd0, VFBC1_Wd_Reset => net_gnd0, VFBC1_Wd_Write => net_gnd0, VFBC1_Wd_End_Burst => net_gnd0, VFBC1_Wd_Flush => net_gnd0, VFBC1_Wd_Data => net_gnd32(0 to 31), VFBC1_Wd_Data_BE => net_gnd4(0 to 3), VFBC1_Wd_Full => open, VFBC1_Wd_Almost_Full => open, VFBC1_Rd_Clk => net_gnd0, VFBC1_Rd_Reset => net_gnd0, VFBC1_Rd_Read => net_gnd0, VFBC1_Rd_End_Burst => net_gnd0, VFBC1_Rd_Flush => net_gnd0, VFBC1_Rd_Data => open, VFBC1_Rd_Empty => open, VFBC1_Rd_Almost_Empty => open, MCB1_cmd_clk => net_gnd0, MCB1_cmd_en => net_gnd0, MCB1_cmd_instr => net_gnd3, MCB1_cmd_bl => net_gnd6, MCB1_cmd_byte_addr => net_gnd30, MCB1_cmd_empty => open, MCB1_cmd_full => open, MCB1_wr_clk => net_gnd0, MCB1_wr_en => net_gnd0, MCB1_wr_mask => net_gnd8(0 to 7), MCB1_wr_data => net_gnd64(0 to 63), MCB1_wr_full => open, MCB1_wr_empty => open, MCB1_wr_count => open, MCB1_wr_underrun => open, MCB1_wr_error => open, MCB1_rd_clk => net_gnd0, MCB1_rd_en => net_gnd0, MCB1_rd_data => open, MCB1_rd_full => open, MCB1_rd_empty => open, MCB1_rd_count => open, MCB1_rd_overflow => open, MCB1_rd_error => open, FSL2_M_Clk => net_vcc0, FSL2_M_Write => net_gnd0, FSL2_M_Data => net_gnd32, FSL2_M_Control => net_gnd0, FSL2_M_Full => open, FSL2_S_Clk => net_gnd0, FSL2_S_Read => net_gnd0, FSL2_S_Data => open, FSL2_S_Control => open, FSL2_S_Exists => open, FSL2_B_M_Clk => net_vcc0, FSL2_B_M_Write => net_gnd0, FSL2_B_M_Data => net_gnd32, FSL2_B_M_Control => net_gnd0, FSL2_B_M_Full => open, FSL2_B_S_Clk => net_gnd0, FSL2_B_S_Read => net_gnd0, FSL2_B_S_Data => open, FSL2_B_S_Control => open, FSL2_B_S_Exists => open, SPLB2_Clk => net_vcc0, SPLB2_Rst => net_gnd0, SPLB2_PLB_ABus => net_gnd32, SPLB2_PLB_PAValid => net_gnd0, SPLB2_PLB_SAValid => net_gnd0, SPLB2_PLB_masterID => net_gnd1(0 downto 0), SPLB2_PLB_RNW => net_gnd0, SPLB2_PLB_BE => net_gnd8, SPLB2_PLB_UABus => net_gnd32, SPLB2_PLB_rdPrim => net_gnd0, SPLB2_PLB_wrPrim => net_gnd0, SPLB2_PLB_abort => net_gnd0, SPLB2_PLB_busLock => net_gnd0, SPLB2_PLB_MSize => net_gnd2, SPLB2_PLB_size => net_gnd4, SPLB2_PLB_type => net_gnd3(2 downto 0), SPLB2_PLB_lockErr => net_gnd0, SPLB2_PLB_wrPendReq => net_gnd0, SPLB2_PLB_wrPendPri => net_gnd2, SPLB2_PLB_rdPendReq => net_gnd0, SPLB2_PLB_rdPendPri => net_gnd2, SPLB2_PLB_reqPri => net_gnd2, SPLB2_PLB_TAttribute => net_gnd16, SPLB2_PLB_rdBurst => net_gnd0, SPLB2_PLB_wrBurst => net_gnd0, SPLB2_PLB_wrDBus => net_gnd64, SPLB2_Sl_addrAck => open, SPLB2_Sl_SSize => open, SPLB2_Sl_wait => open, SPLB2_Sl_rearbitrate => open, SPLB2_Sl_wrDAck => open, SPLB2_Sl_wrComp => open, SPLB2_Sl_wrBTerm => open, SPLB2_Sl_rdDBus => open, SPLB2_Sl_rdWdAddr => open, SPLB2_Sl_rdDAck => open, SPLB2_Sl_rdComp => open, SPLB2_Sl_rdBTerm => open, SPLB2_Sl_MBusy => open, SPLB2_Sl_MRdErr => open, SPLB2_Sl_MWrErr => open, SPLB2_Sl_MIRQ => open, SDMA2_Clk => net_gnd0, SDMA2_Rx_IntOut => open, SDMA2_Tx_IntOut => open, SDMA2_RstOut => open, SDMA2_TX_D => open, SDMA2_TX_Rem => open, SDMA2_TX_SOF => open, SDMA2_TX_EOF => open, SDMA2_TX_SOP => open, SDMA2_TX_EOP => open, SDMA2_TX_Src_Rdy => open, SDMA2_TX_Dst_Rdy => net_vcc0, SDMA2_RX_D => net_gnd32, SDMA2_RX_Rem => net_vcc4, SDMA2_RX_SOF => net_vcc0, SDMA2_RX_EOF => net_vcc0, SDMA2_RX_SOP => net_vcc0, SDMA2_RX_EOP => net_vcc0, SDMA2_RX_Src_Rdy => net_vcc0, SDMA2_RX_Dst_Rdy => open, SDMA_CTRL2_Clk => net_vcc0, SDMA_CTRL2_Rst => net_gnd0, SDMA_CTRL2_PLB_ABus => net_gnd32, SDMA_CTRL2_PLB_PAValid => net_gnd0, SDMA_CTRL2_PLB_SAValid => net_gnd0, SDMA_CTRL2_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL2_PLB_RNW => net_gnd0, SDMA_CTRL2_PLB_BE => net_gnd8, SDMA_CTRL2_PLB_UABus => net_gnd32, SDMA_CTRL2_PLB_rdPrim => net_gnd0, SDMA_CTRL2_PLB_wrPrim => net_gnd0, SDMA_CTRL2_PLB_abort => net_gnd0, SDMA_CTRL2_PLB_busLock => net_gnd0, SDMA_CTRL2_PLB_MSize => net_gnd2, SDMA_CTRL2_PLB_size => net_gnd4, SDMA_CTRL2_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL2_PLB_lockErr => net_gnd0, SDMA_CTRL2_PLB_wrPendReq => net_gnd0, SDMA_CTRL2_PLB_wrPendPri => net_gnd2, SDMA_CTRL2_PLB_rdPendReq => net_gnd0, SDMA_CTRL2_PLB_rdPendPri => net_gnd2, SDMA_CTRL2_PLB_reqPri => net_gnd2, SDMA_CTRL2_PLB_TAttribute => net_gnd16, SDMA_CTRL2_PLB_rdBurst => net_gnd0, SDMA_CTRL2_PLB_wrBurst => net_gnd0, SDMA_CTRL2_PLB_wrDBus => net_gnd64, SDMA_CTRL2_Sl_addrAck => open, SDMA_CTRL2_Sl_SSize => open, SDMA_CTRL2_Sl_wait => open, SDMA_CTRL2_Sl_rearbitrate => open, SDMA_CTRL2_Sl_wrDAck => open, SDMA_CTRL2_Sl_wrComp => open, SDMA_CTRL2_Sl_wrBTerm => open, SDMA_CTRL2_Sl_rdDBus => open, SDMA_CTRL2_Sl_rdWdAddr => open, SDMA_CTRL2_Sl_rdDAck => open, SDMA_CTRL2_Sl_rdComp => open, SDMA_CTRL2_Sl_rdBTerm => open, SDMA_CTRL2_Sl_MBusy => open, SDMA_CTRL2_Sl_MRdErr => open, SDMA_CTRL2_Sl_MWrErr => open, SDMA_CTRL2_Sl_MIRQ => open, PIM2_Addr => net_gnd32(0 to 31), PIM2_AddrReq => net_gnd0, PIM2_AddrAck => open, PIM2_RNW => net_gnd0, PIM2_Size => net_gnd4(0 to 3), PIM2_RdModWr => net_gnd0, PIM2_WrFIFO_Data => net_gnd64(0 to 63), PIM2_WrFIFO_BE => net_gnd8(0 to 7), PIM2_WrFIFO_Push => net_gnd0, PIM2_RdFIFO_Data => open, PIM2_RdFIFO_Pop => net_gnd0, PIM2_RdFIFO_RdWdAddr => open, PIM2_WrFIFO_Empty => open, PIM2_WrFIFO_AlmostFull => open, PIM2_WrFIFO_Flush => net_gnd0, PIM2_RdFIFO_Empty => open, PIM2_RdFIFO_Flush => net_gnd0, PIM2_RdFIFO_Latency => open, PIM2_InitDone => open, PPC440MC2_MIMCReadNotWrite => net_gnd0, PPC440MC2_MIMCAddress => net_gnd36, PPC440MC2_MIMCAddressValid => net_gnd0, PPC440MC2_MIMCWriteData => net_gnd128, PPC440MC2_MIMCWriteDataValid => net_gnd0, PPC440MC2_MIMCByteEnable => net_gnd16, PPC440MC2_MIMCBankConflict => net_gnd0, PPC440MC2_MIMCRowConflict => net_gnd0, PPC440MC2_MCMIReadData => open, PPC440MC2_MCMIReadDataValid => open, PPC440MC2_MCMIReadDataErr => open, PPC440MC2_MCMIAddrReadyToAccept => open, VFBC2_Cmd_Clk => net_gnd0, VFBC2_Cmd_Reset => net_gnd0, VFBC2_Cmd_Data => net_gnd32(0 to 31), VFBC2_Cmd_Write => net_gnd0, VFBC2_Cmd_End => net_gnd0, VFBC2_Cmd_Full => open, VFBC2_Cmd_Almost_Full => open, VFBC2_Cmd_Idle => open, VFBC2_Wd_Clk => net_gnd0, VFBC2_Wd_Reset => net_gnd0, VFBC2_Wd_Write => net_gnd0, VFBC2_Wd_End_Burst => net_gnd0, VFBC2_Wd_Flush => net_gnd0, VFBC2_Wd_Data => net_gnd32(0 to 31), VFBC2_Wd_Data_BE => net_gnd4(0 to 3), VFBC2_Wd_Full => open, VFBC2_Wd_Almost_Full => open, VFBC2_Rd_Clk => net_gnd0, VFBC2_Rd_Reset => net_gnd0, VFBC2_Rd_Read => net_gnd0, VFBC2_Rd_End_Burst => net_gnd0, VFBC2_Rd_Flush => net_gnd0, VFBC2_Rd_Data => open, VFBC2_Rd_Empty => open, VFBC2_Rd_Almost_Empty => open, MCB2_cmd_clk => net_gnd0, MCB2_cmd_en => net_gnd0, MCB2_cmd_instr => net_gnd3, MCB2_cmd_bl => net_gnd6, MCB2_cmd_byte_addr => net_gnd30, MCB2_cmd_empty => open, MCB2_cmd_full => open, MCB2_wr_clk => net_gnd0, MCB2_wr_en => net_gnd0, MCB2_wr_mask => net_gnd8(0 to 7), MCB2_wr_data => net_gnd64(0 to 63), MCB2_wr_full => open, MCB2_wr_empty => open, MCB2_wr_count => open, MCB2_wr_underrun => open, MCB2_wr_error => open, MCB2_rd_clk => net_gnd0, MCB2_rd_en => net_gnd0, MCB2_rd_data => open, MCB2_rd_full => open, MCB2_rd_empty => open, MCB2_rd_count => open, MCB2_rd_overflow => open, MCB2_rd_error => open, FSL3_M_Clk => net_vcc0, FSL3_M_Write => net_gnd0, FSL3_M_Data => net_gnd32, FSL3_M_Control => net_gnd0, FSL3_M_Full => open, FSL3_S_Clk => net_gnd0, FSL3_S_Read => net_gnd0, FSL3_S_Data => open, FSL3_S_Control => open, FSL3_S_Exists => open, FSL3_B_M_Clk => net_vcc0, FSL3_B_M_Write => net_gnd0, FSL3_B_M_Data => net_gnd32, FSL3_B_M_Control => net_gnd0, FSL3_B_M_Full => open, FSL3_B_S_Clk => net_gnd0, FSL3_B_S_Read => net_gnd0, FSL3_B_S_Data => open, FSL3_B_S_Control => open, FSL3_B_S_Exists => open, SPLB3_Clk => net_vcc0, SPLB3_Rst => net_gnd0, SPLB3_PLB_ABus => net_gnd32, SPLB3_PLB_PAValid => net_gnd0, SPLB3_PLB_SAValid => net_gnd0, SPLB3_PLB_masterID => net_gnd1(0 downto 0), SPLB3_PLB_RNW => net_gnd0, SPLB3_PLB_BE => net_gnd8, SPLB3_PLB_UABus => net_gnd32, SPLB3_PLB_rdPrim => net_gnd0, SPLB3_PLB_wrPrim => net_gnd0, SPLB3_PLB_abort => net_gnd0, SPLB3_PLB_busLock => net_gnd0, SPLB3_PLB_MSize => net_gnd2, SPLB3_PLB_size => net_gnd4, SPLB3_PLB_type => net_gnd3(2 downto 0), SPLB3_PLB_lockErr => net_gnd0, SPLB3_PLB_wrPendReq => net_gnd0, SPLB3_PLB_wrPendPri => net_gnd2, SPLB3_PLB_rdPendReq => net_gnd0, SPLB3_PLB_rdPendPri => net_gnd2, SPLB3_PLB_reqPri => net_gnd2, SPLB3_PLB_TAttribute => net_gnd16, SPLB3_PLB_rdBurst => net_gnd0, SPLB3_PLB_wrBurst => net_gnd0, SPLB3_PLB_wrDBus => net_gnd64, SPLB3_Sl_addrAck => open, SPLB3_Sl_SSize => open, SPLB3_Sl_wait => open, SPLB3_Sl_rearbitrate => open, SPLB3_Sl_wrDAck => open, SPLB3_Sl_wrComp => open, SPLB3_Sl_wrBTerm => open, SPLB3_Sl_rdDBus => open, SPLB3_Sl_rdWdAddr => open, SPLB3_Sl_rdDAck => open, SPLB3_Sl_rdComp => open, SPLB3_Sl_rdBTerm => open, SPLB3_Sl_MBusy => open, SPLB3_Sl_MRdErr => open, SPLB3_Sl_MWrErr => open, SPLB3_Sl_MIRQ => open, SDMA3_Clk => net_gnd0, SDMA3_Rx_IntOut => open, SDMA3_Tx_IntOut => open, SDMA3_RstOut => open, SDMA3_TX_D => open, SDMA3_TX_Rem => open, SDMA3_TX_SOF => open, SDMA3_TX_EOF => open, SDMA3_TX_SOP => open, SDMA3_TX_EOP => open, SDMA3_TX_Src_Rdy => open, SDMA3_TX_Dst_Rdy => net_vcc0, SDMA3_RX_D => net_gnd32, SDMA3_RX_Rem => net_vcc4, SDMA3_RX_SOF => net_vcc0, SDMA3_RX_EOF => net_vcc0, SDMA3_RX_SOP => net_vcc0, SDMA3_RX_EOP => net_vcc0, SDMA3_RX_Src_Rdy => net_vcc0, SDMA3_RX_Dst_Rdy => open, SDMA_CTRL3_Clk => net_vcc0, SDMA_CTRL3_Rst => net_gnd0, SDMA_CTRL3_PLB_ABus => net_gnd32, SDMA_CTRL3_PLB_PAValid => net_gnd0, SDMA_CTRL3_PLB_SAValid => net_gnd0, SDMA_CTRL3_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL3_PLB_RNW => net_gnd0, SDMA_CTRL3_PLB_BE => net_gnd8, SDMA_CTRL3_PLB_UABus => net_gnd32, SDMA_CTRL3_PLB_rdPrim => net_gnd0, SDMA_CTRL3_PLB_wrPrim => net_gnd0, SDMA_CTRL3_PLB_abort => net_gnd0, SDMA_CTRL3_PLB_busLock => net_gnd0, SDMA_CTRL3_PLB_MSize => net_gnd2, SDMA_CTRL3_PLB_size => net_gnd4, SDMA_CTRL3_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL3_PLB_lockErr => net_gnd0, SDMA_CTRL3_PLB_wrPendReq => net_gnd0, SDMA_CTRL3_PLB_wrPendPri => net_gnd2, SDMA_CTRL3_PLB_rdPendReq => net_gnd0, SDMA_CTRL3_PLB_rdPendPri => net_gnd2, SDMA_CTRL3_PLB_reqPri => net_gnd2, SDMA_CTRL3_PLB_TAttribute => net_gnd16, SDMA_CTRL3_PLB_rdBurst => net_gnd0, SDMA_CTRL3_PLB_wrBurst => net_gnd0, SDMA_CTRL3_PLB_wrDBus => net_gnd64, SDMA_CTRL3_Sl_addrAck => open, SDMA_CTRL3_Sl_SSize => open, SDMA_CTRL3_Sl_wait => open, SDMA_CTRL3_Sl_rearbitrate => open, SDMA_CTRL3_Sl_wrDAck => open, SDMA_CTRL3_Sl_wrComp => open, SDMA_CTRL3_Sl_wrBTerm => open, SDMA_CTRL3_Sl_rdDBus => open, SDMA_CTRL3_Sl_rdWdAddr => open, SDMA_CTRL3_Sl_rdDAck => open, SDMA_CTRL3_Sl_rdComp => open, SDMA_CTRL3_Sl_rdBTerm => open, SDMA_CTRL3_Sl_MBusy => open, SDMA_CTRL3_Sl_MRdErr => open, SDMA_CTRL3_Sl_MWrErr => open, SDMA_CTRL3_Sl_MIRQ => open, PIM3_Addr => net_gnd32(0 to 31), PIM3_AddrReq => net_gnd0, PIM3_AddrAck => open, PIM3_RNW => net_gnd0, PIM3_Size => net_gnd4(0 to 3), PIM3_RdModWr => net_gnd0, PIM3_WrFIFO_Data => net_gnd64(0 to 63), PIM3_WrFIFO_BE => net_gnd8(0 to 7), PIM3_WrFIFO_Push => net_gnd0, PIM3_RdFIFO_Data => open, PIM3_RdFIFO_Pop => net_gnd0, PIM3_RdFIFO_RdWdAddr => open, PIM3_WrFIFO_Empty => open, PIM3_WrFIFO_AlmostFull => open, PIM3_WrFIFO_Flush => net_gnd0, PIM3_RdFIFO_Empty => open, PIM3_RdFIFO_Flush => net_gnd0, PIM3_RdFIFO_Latency => open, PIM3_InitDone => open, PPC440MC3_MIMCReadNotWrite => net_gnd0, PPC440MC3_MIMCAddress => net_gnd36, PPC440MC3_MIMCAddressValid => net_gnd0, PPC440MC3_MIMCWriteData => net_gnd128, PPC440MC3_MIMCWriteDataValid => net_gnd0, PPC440MC3_MIMCByteEnable => net_gnd16, PPC440MC3_MIMCBankConflict => net_gnd0, PPC440MC3_MIMCRowConflict => net_gnd0, PPC440MC3_MCMIReadData => open, PPC440MC3_MCMIReadDataValid => open, PPC440MC3_MCMIReadDataErr => open, PPC440MC3_MCMIAddrReadyToAccept => open, VFBC3_Cmd_Clk => net_gnd0, VFBC3_Cmd_Reset => net_gnd0, VFBC3_Cmd_Data => net_gnd32(0 to 31), VFBC3_Cmd_Write => net_gnd0, VFBC3_Cmd_End => net_gnd0, VFBC3_Cmd_Full => open, VFBC3_Cmd_Almost_Full => open, VFBC3_Cmd_Idle => open, VFBC3_Wd_Clk => net_gnd0, VFBC3_Wd_Reset => net_gnd0, VFBC3_Wd_Write => net_gnd0, VFBC3_Wd_End_Burst => net_gnd0, VFBC3_Wd_Flush => net_gnd0, VFBC3_Wd_Data => net_gnd32(0 to 31), VFBC3_Wd_Data_BE => net_gnd4(0 to 3), VFBC3_Wd_Full => open, VFBC3_Wd_Almost_Full => open, VFBC3_Rd_Clk => net_gnd0, VFBC3_Rd_Reset => net_gnd0, VFBC3_Rd_Read => net_gnd0, VFBC3_Rd_End_Burst => net_gnd0, VFBC3_Rd_Flush => net_gnd0, VFBC3_Rd_Data => open, VFBC3_Rd_Empty => open, VFBC3_Rd_Almost_Empty => open, MCB3_cmd_clk => net_gnd0, MCB3_cmd_en => net_gnd0, MCB3_cmd_instr => net_gnd3, MCB3_cmd_bl => net_gnd6, MCB3_cmd_byte_addr => net_gnd30, MCB3_cmd_empty => open, MCB3_cmd_full => open, MCB3_wr_clk => net_gnd0, MCB3_wr_en => net_gnd0, MCB3_wr_mask => net_gnd8(0 to 7), MCB3_wr_data => net_gnd64(0 to 63), MCB3_wr_full => open, MCB3_wr_empty => open, MCB3_wr_count => open, MCB3_wr_underrun => open, MCB3_wr_error => open, MCB3_rd_clk => net_gnd0, MCB3_rd_en => net_gnd0, MCB3_rd_data => open, MCB3_rd_full => open, MCB3_rd_empty => open, MCB3_rd_count => open, MCB3_rd_overflow => open, MCB3_rd_error => open, FSL4_M_Clk => net_vcc0, FSL4_M_Write => net_gnd0, FSL4_M_Data => net_gnd32, FSL4_M_Control => net_gnd0, FSL4_M_Full => open, FSL4_S_Clk => net_gnd0, FSL4_S_Read => net_gnd0, FSL4_S_Data => open, FSL4_S_Control => open, FSL4_S_Exists => open, FSL4_B_M_Clk => net_vcc0, FSL4_B_M_Write => net_gnd0, FSL4_B_M_Data => net_gnd32, FSL4_B_M_Control => net_gnd0, FSL4_B_M_Full => open, FSL4_B_S_Clk => net_gnd0, FSL4_B_S_Read => net_gnd0, FSL4_B_S_Data => open, FSL4_B_S_Control => open, FSL4_B_S_Exists => open, SPLB4_Clk => net_vcc0, SPLB4_Rst => net_gnd0, SPLB4_PLB_ABus => net_gnd32, SPLB4_PLB_PAValid => net_gnd0, SPLB4_PLB_SAValid => net_gnd0, SPLB4_PLB_masterID => net_gnd1(0 downto 0), SPLB4_PLB_RNW => net_gnd0, SPLB4_PLB_BE => net_gnd8, SPLB4_PLB_UABus => net_gnd32, SPLB4_PLB_rdPrim => net_gnd0, SPLB4_PLB_wrPrim => net_gnd0, SPLB4_PLB_abort => net_gnd0, SPLB4_PLB_busLock => net_gnd0, SPLB4_PLB_MSize => net_gnd2, SPLB4_PLB_size => net_gnd4, SPLB4_PLB_type => net_gnd3(2 downto 0), SPLB4_PLB_lockErr => net_gnd0, SPLB4_PLB_wrPendReq => net_gnd0, SPLB4_PLB_wrPendPri => net_gnd2, SPLB4_PLB_rdPendReq => net_gnd0, SPLB4_PLB_rdPendPri => net_gnd2, SPLB4_PLB_reqPri => net_gnd2, SPLB4_PLB_TAttribute => net_gnd16, SPLB4_PLB_rdBurst => net_gnd0, SPLB4_PLB_wrBurst => net_gnd0, SPLB4_PLB_wrDBus => net_gnd64, SPLB4_Sl_addrAck => open, SPLB4_Sl_SSize => open, SPLB4_Sl_wait => open, SPLB4_Sl_rearbitrate => open, SPLB4_Sl_wrDAck => open, SPLB4_Sl_wrComp => open, SPLB4_Sl_wrBTerm => open, SPLB4_Sl_rdDBus => open, SPLB4_Sl_rdWdAddr => open, SPLB4_Sl_rdDAck => open, SPLB4_Sl_rdComp => open, SPLB4_Sl_rdBTerm => open, SPLB4_Sl_MBusy => open, SPLB4_Sl_MRdErr => open, SPLB4_Sl_MWrErr => open, SPLB4_Sl_MIRQ => open, SDMA4_Clk => net_gnd0, SDMA4_Rx_IntOut => open, SDMA4_Tx_IntOut => open, SDMA4_RstOut => open, SDMA4_TX_D => open, SDMA4_TX_Rem => open, SDMA4_TX_SOF => open, SDMA4_TX_EOF => open, SDMA4_TX_SOP => open, SDMA4_TX_EOP => open, SDMA4_TX_Src_Rdy => open, SDMA4_TX_Dst_Rdy => net_vcc0, SDMA4_RX_D => net_gnd32, SDMA4_RX_Rem => net_vcc4, SDMA4_RX_SOF => net_vcc0, SDMA4_RX_EOF => net_vcc0, SDMA4_RX_SOP => net_vcc0, SDMA4_RX_EOP => net_vcc0, SDMA4_RX_Src_Rdy => net_vcc0, SDMA4_RX_Dst_Rdy => open, SDMA_CTRL4_Clk => net_vcc0, SDMA_CTRL4_Rst => net_gnd0, SDMA_CTRL4_PLB_ABus => net_gnd32, SDMA_CTRL4_PLB_PAValid => net_gnd0, SDMA_CTRL4_PLB_SAValid => net_gnd0, SDMA_CTRL4_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL4_PLB_RNW => net_gnd0, SDMA_CTRL4_PLB_BE => net_gnd8, SDMA_CTRL4_PLB_UABus => net_gnd32, SDMA_CTRL4_PLB_rdPrim => net_gnd0, SDMA_CTRL4_PLB_wrPrim => net_gnd0, SDMA_CTRL4_PLB_abort => net_gnd0, SDMA_CTRL4_PLB_busLock => net_gnd0, SDMA_CTRL4_PLB_MSize => net_gnd2, SDMA_CTRL4_PLB_size => net_gnd4, SDMA_CTRL4_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL4_PLB_lockErr => net_gnd0, SDMA_CTRL4_PLB_wrPendReq => net_gnd0, SDMA_CTRL4_PLB_wrPendPri => net_gnd2, SDMA_CTRL4_PLB_rdPendReq => net_gnd0, SDMA_CTRL4_PLB_rdPendPri => net_gnd2, SDMA_CTRL4_PLB_reqPri => net_gnd2, SDMA_CTRL4_PLB_TAttribute => net_gnd16, SDMA_CTRL4_PLB_rdBurst => net_gnd0, SDMA_CTRL4_PLB_wrBurst => net_gnd0, SDMA_CTRL4_PLB_wrDBus => net_gnd64, SDMA_CTRL4_Sl_addrAck => open, SDMA_CTRL4_Sl_SSize => open, SDMA_CTRL4_Sl_wait => open, SDMA_CTRL4_Sl_rearbitrate => open, SDMA_CTRL4_Sl_wrDAck => open, SDMA_CTRL4_Sl_wrComp => open, SDMA_CTRL4_Sl_wrBTerm => open, SDMA_CTRL4_Sl_rdDBus => open, SDMA_CTRL4_Sl_rdWdAddr => open, SDMA_CTRL4_Sl_rdDAck => open, SDMA_CTRL4_Sl_rdComp => open, SDMA_CTRL4_Sl_rdBTerm => open, SDMA_CTRL4_Sl_MBusy => open, SDMA_CTRL4_Sl_MRdErr => open, SDMA_CTRL4_Sl_MWrErr => open, SDMA_CTRL4_Sl_MIRQ => open, PIM4_Addr => net_gnd32(0 to 31), PIM4_AddrReq => net_gnd0, PIM4_AddrAck => open, PIM4_RNW => net_gnd0, PIM4_Size => net_gnd4(0 to 3), PIM4_RdModWr => net_gnd0, PIM4_WrFIFO_Data => net_gnd64(0 to 63), PIM4_WrFIFO_BE => net_gnd8(0 to 7), PIM4_WrFIFO_Push => net_gnd0, PIM4_RdFIFO_Data => open, PIM4_RdFIFO_Pop => net_gnd0, PIM4_RdFIFO_RdWdAddr => open, PIM4_WrFIFO_Empty => open, PIM4_WrFIFO_AlmostFull => open, PIM4_WrFIFO_Flush => net_gnd0, PIM4_RdFIFO_Empty => open, PIM4_RdFIFO_Flush => net_gnd0, PIM4_RdFIFO_Latency => open, PIM4_InitDone => open, PPC440MC4_MIMCReadNotWrite => net_gnd0, PPC440MC4_MIMCAddress => net_gnd36, PPC440MC4_MIMCAddressValid => net_gnd0, PPC440MC4_MIMCWriteData => net_gnd128, PPC440MC4_MIMCWriteDataValid => net_gnd0, PPC440MC4_MIMCByteEnable => net_gnd16, PPC440MC4_MIMCBankConflict => net_gnd0, PPC440MC4_MIMCRowConflict => net_gnd0, PPC440MC4_MCMIReadData => open, PPC440MC4_MCMIReadDataValid => open, PPC440MC4_MCMIReadDataErr => open, PPC440MC4_MCMIAddrReadyToAccept => open, VFBC4_Cmd_Clk => net_gnd0, VFBC4_Cmd_Reset => net_gnd0, VFBC4_Cmd_Data => net_gnd32(0 to 31), VFBC4_Cmd_Write => net_gnd0, VFBC4_Cmd_End => net_gnd0, VFBC4_Cmd_Full => open, VFBC4_Cmd_Almost_Full => open, VFBC4_Cmd_Idle => open, VFBC4_Wd_Clk => net_gnd0, VFBC4_Wd_Reset => net_gnd0, VFBC4_Wd_Write => net_gnd0, VFBC4_Wd_End_Burst => net_gnd0, VFBC4_Wd_Flush => net_gnd0, VFBC4_Wd_Data => net_gnd32(0 to 31), VFBC4_Wd_Data_BE => net_gnd4(0 to 3), VFBC4_Wd_Full => open, VFBC4_Wd_Almost_Full => open, VFBC4_Rd_Clk => net_gnd0, VFBC4_Rd_Reset => net_gnd0, VFBC4_Rd_Read => net_gnd0, VFBC4_Rd_End_Burst => net_gnd0, VFBC4_Rd_Flush => net_gnd0, VFBC4_Rd_Data => open, VFBC4_Rd_Empty => open, VFBC4_Rd_Almost_Empty => open, MCB4_cmd_clk => net_gnd0, MCB4_cmd_en => net_gnd0, MCB4_cmd_instr => net_gnd3, MCB4_cmd_bl => net_gnd6, MCB4_cmd_byte_addr => net_gnd30, MCB4_cmd_empty => open, MCB4_cmd_full => open, MCB4_wr_clk => net_gnd0, MCB4_wr_en => net_gnd0, MCB4_wr_mask => net_gnd8(0 to 7), MCB4_wr_data => net_gnd64(0 to 63), MCB4_wr_full => open, MCB4_wr_empty => open, MCB4_wr_count => open, MCB4_wr_underrun => open, MCB4_wr_error => open, MCB4_rd_clk => net_gnd0, MCB4_rd_en => net_gnd0, MCB4_rd_data => open, MCB4_rd_full => open, MCB4_rd_empty => open, MCB4_rd_count => open, MCB4_rd_overflow => open, MCB4_rd_error => open, FSL5_M_Clk => net_vcc0, FSL5_M_Write => net_gnd0, FSL5_M_Data => net_gnd32, FSL5_M_Control => net_gnd0, FSL5_M_Full => open, FSL5_S_Clk => net_gnd0, FSL5_S_Read => net_gnd0, FSL5_S_Data => open, FSL5_S_Control => open, FSL5_S_Exists => open, FSL5_B_M_Clk => net_vcc0, FSL5_B_M_Write => net_gnd0, FSL5_B_M_Data => net_gnd32, FSL5_B_M_Control => net_gnd0, FSL5_B_M_Full => open, FSL5_B_S_Clk => net_gnd0, FSL5_B_S_Read => net_gnd0, FSL5_B_S_Data => open, FSL5_B_S_Control => open, FSL5_B_S_Exists => open, SPLB5_Clk => net_vcc0, SPLB5_Rst => net_gnd0, SPLB5_PLB_ABus => net_gnd32, SPLB5_PLB_PAValid => net_gnd0, SPLB5_PLB_SAValid => net_gnd0, SPLB5_PLB_masterID => net_gnd1(0 downto 0), SPLB5_PLB_RNW => net_gnd0, SPLB5_PLB_BE => net_gnd8, SPLB5_PLB_UABus => net_gnd32, SPLB5_PLB_rdPrim => net_gnd0, SPLB5_PLB_wrPrim => net_gnd0, SPLB5_PLB_abort => net_gnd0, SPLB5_PLB_busLock => net_gnd0, SPLB5_PLB_MSize => net_gnd2, SPLB5_PLB_size => net_gnd4, SPLB5_PLB_type => net_gnd3(2 downto 0), SPLB5_PLB_lockErr => net_gnd0, SPLB5_PLB_wrPendReq => net_gnd0, SPLB5_PLB_wrPendPri => net_gnd2, SPLB5_PLB_rdPendReq => net_gnd0, SPLB5_PLB_rdPendPri => net_gnd2, SPLB5_PLB_reqPri => net_gnd2, SPLB5_PLB_TAttribute => net_gnd16, SPLB5_PLB_rdBurst => net_gnd0, SPLB5_PLB_wrBurst => net_gnd0, SPLB5_PLB_wrDBus => net_gnd64, SPLB5_Sl_addrAck => open, SPLB5_Sl_SSize => open, SPLB5_Sl_wait => open, SPLB5_Sl_rearbitrate => open, SPLB5_Sl_wrDAck => open, SPLB5_Sl_wrComp => open, SPLB5_Sl_wrBTerm => open, SPLB5_Sl_rdDBus => open, SPLB5_Sl_rdWdAddr => open, SPLB5_Sl_rdDAck => open, SPLB5_Sl_rdComp => open, SPLB5_Sl_rdBTerm => open, SPLB5_Sl_MBusy => open, SPLB5_Sl_MRdErr => open, SPLB5_Sl_MWrErr => open, SPLB5_Sl_MIRQ => open, SDMA5_Clk => net_gnd0, SDMA5_Rx_IntOut => open, SDMA5_Tx_IntOut => open, SDMA5_RstOut => open, SDMA5_TX_D => open, SDMA5_TX_Rem => open, SDMA5_TX_SOF => open, SDMA5_TX_EOF => open, SDMA5_TX_SOP => open, SDMA5_TX_EOP => open, SDMA5_TX_Src_Rdy => open, SDMA5_TX_Dst_Rdy => net_vcc0, SDMA5_RX_D => net_gnd32, SDMA5_RX_Rem => net_vcc4, SDMA5_RX_SOF => net_vcc0, SDMA5_RX_EOF => net_vcc0, SDMA5_RX_SOP => net_vcc0, SDMA5_RX_EOP => net_vcc0, SDMA5_RX_Src_Rdy => net_vcc0, SDMA5_RX_Dst_Rdy => open, SDMA_CTRL5_Clk => net_vcc0, SDMA_CTRL5_Rst => net_gnd0, SDMA_CTRL5_PLB_ABus => net_gnd32, SDMA_CTRL5_PLB_PAValid => net_gnd0, SDMA_CTRL5_PLB_SAValid => net_gnd0, SDMA_CTRL5_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL5_PLB_RNW => net_gnd0, SDMA_CTRL5_PLB_BE => net_gnd8, SDMA_CTRL5_PLB_UABus => net_gnd32, SDMA_CTRL5_PLB_rdPrim => net_gnd0, SDMA_CTRL5_PLB_wrPrim => net_gnd0, SDMA_CTRL5_PLB_abort => net_gnd0, SDMA_CTRL5_PLB_busLock => net_gnd0, SDMA_CTRL5_PLB_MSize => net_gnd2, SDMA_CTRL5_PLB_size => net_gnd4, SDMA_CTRL5_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL5_PLB_lockErr => net_gnd0, SDMA_CTRL5_PLB_wrPendReq => net_gnd0, SDMA_CTRL5_PLB_wrPendPri => net_gnd2, SDMA_CTRL5_PLB_rdPendReq => net_gnd0, SDMA_CTRL5_PLB_rdPendPri => net_gnd2, SDMA_CTRL5_PLB_reqPri => net_gnd2, SDMA_CTRL5_PLB_TAttribute => net_gnd16, SDMA_CTRL5_PLB_rdBurst => net_gnd0, SDMA_CTRL5_PLB_wrBurst => net_gnd0, SDMA_CTRL5_PLB_wrDBus => net_gnd64, SDMA_CTRL5_Sl_addrAck => open, SDMA_CTRL5_Sl_SSize => open, SDMA_CTRL5_Sl_wait => open, SDMA_CTRL5_Sl_rearbitrate => open, SDMA_CTRL5_Sl_wrDAck => open, SDMA_CTRL5_Sl_wrComp => open, SDMA_CTRL5_Sl_wrBTerm => open, SDMA_CTRL5_Sl_rdDBus => open, SDMA_CTRL5_Sl_rdWdAddr => open, SDMA_CTRL5_Sl_rdDAck => open, SDMA_CTRL5_Sl_rdComp => open, SDMA_CTRL5_Sl_rdBTerm => open, SDMA_CTRL5_Sl_MBusy => open, SDMA_CTRL5_Sl_MRdErr => open, SDMA_CTRL5_Sl_MWrErr => open, SDMA_CTRL5_Sl_MIRQ => open, PIM5_Addr => net_gnd32(0 to 31), PIM5_AddrReq => net_gnd0, PIM5_AddrAck => open, PIM5_RNW => net_gnd0, PIM5_Size => net_gnd4(0 to 3), PIM5_RdModWr => net_gnd0, PIM5_WrFIFO_Data => net_gnd64(0 to 63), PIM5_WrFIFO_BE => net_gnd8(0 to 7), PIM5_WrFIFO_Push => net_gnd0, PIM5_RdFIFO_Data => open, PIM5_RdFIFO_Pop => net_gnd0, PIM5_RdFIFO_RdWdAddr => open, PIM5_WrFIFO_Empty => open, PIM5_WrFIFO_AlmostFull => open, PIM5_WrFIFO_Flush => net_gnd0, PIM5_RdFIFO_Empty => open, PIM5_RdFIFO_Flush => net_gnd0, PIM5_RdFIFO_Latency => open, PIM5_InitDone => open, PPC440MC5_MIMCReadNotWrite => net_gnd0, PPC440MC5_MIMCAddress => net_gnd36, PPC440MC5_MIMCAddressValid => net_gnd0, PPC440MC5_MIMCWriteData => net_gnd128, PPC440MC5_MIMCWriteDataValid => net_gnd0, PPC440MC5_MIMCByteEnable => net_gnd16, PPC440MC5_MIMCBankConflict => net_gnd0, PPC440MC5_MIMCRowConflict => net_gnd0, PPC440MC5_MCMIReadData => open, PPC440MC5_MCMIReadDataValid => open, PPC440MC5_MCMIReadDataErr => open, PPC440MC5_MCMIAddrReadyToAccept => open, VFBC5_Cmd_Clk => net_gnd0, VFBC5_Cmd_Reset => net_gnd0, VFBC5_Cmd_Data => net_gnd32(0 to 31), VFBC5_Cmd_Write => net_gnd0, VFBC5_Cmd_End => net_gnd0, VFBC5_Cmd_Full => open, VFBC5_Cmd_Almost_Full => open, VFBC5_Cmd_Idle => open, VFBC5_Wd_Clk => net_gnd0, VFBC5_Wd_Reset => net_gnd0, VFBC5_Wd_Write => net_gnd0, VFBC5_Wd_End_Burst => net_gnd0, VFBC5_Wd_Flush => net_gnd0, VFBC5_Wd_Data => net_gnd32(0 to 31), VFBC5_Wd_Data_BE => net_gnd4(0 to 3), VFBC5_Wd_Full => open, VFBC5_Wd_Almost_Full => open, VFBC5_Rd_Clk => net_gnd0, VFBC5_Rd_Reset => net_gnd0, VFBC5_Rd_Read => net_gnd0, VFBC5_Rd_End_Burst => net_gnd0, VFBC5_Rd_Flush => net_gnd0, VFBC5_Rd_Data => open, VFBC5_Rd_Empty => open, VFBC5_Rd_Almost_Empty => open, MCB5_cmd_clk => net_gnd0, MCB5_cmd_en => net_gnd0, MCB5_cmd_instr => net_gnd3, MCB5_cmd_bl => net_gnd6, MCB5_cmd_byte_addr => net_gnd30, MCB5_cmd_empty => open, MCB5_cmd_full => open, MCB5_wr_clk => net_gnd0, MCB5_wr_en => net_gnd0, MCB5_wr_mask => net_gnd8(0 to 7), MCB5_wr_data => net_gnd64(0 to 63), MCB5_wr_full => open, MCB5_wr_empty => open, MCB5_wr_count => open, MCB5_wr_underrun => open, MCB5_wr_error => open, MCB5_rd_clk => net_gnd0, MCB5_rd_en => net_gnd0, MCB5_rd_data => open, MCB5_rd_full => open, MCB5_rd_empty => open, MCB5_rd_count => open, MCB5_rd_overflow => open, MCB5_rd_error => open, FSL6_M_Clk => net_vcc0, FSL6_M_Write => net_gnd0, FSL6_M_Data => net_gnd32, FSL6_M_Control => net_gnd0, FSL6_M_Full => open, FSL6_S_Clk => net_gnd0, FSL6_S_Read => net_gnd0, FSL6_S_Data => open, FSL6_S_Control => open, FSL6_S_Exists => open, FSL6_B_M_Clk => net_vcc0, FSL6_B_M_Write => net_gnd0, FSL6_B_M_Data => net_gnd32, FSL6_B_M_Control => net_gnd0, FSL6_B_M_Full => open, FSL6_B_S_Clk => net_gnd0, FSL6_B_S_Read => net_gnd0, FSL6_B_S_Data => open, FSL6_B_S_Control => open, FSL6_B_S_Exists => open, SPLB6_Clk => net_vcc0, SPLB6_Rst => net_gnd0, SPLB6_PLB_ABus => net_gnd32, SPLB6_PLB_PAValid => net_gnd0, SPLB6_PLB_SAValid => net_gnd0, SPLB6_PLB_masterID => net_gnd1(0 downto 0), SPLB6_PLB_RNW => net_gnd0, SPLB6_PLB_BE => net_gnd8, SPLB6_PLB_UABus => net_gnd32, SPLB6_PLB_rdPrim => net_gnd0, SPLB6_PLB_wrPrim => net_gnd0, SPLB6_PLB_abort => net_gnd0, SPLB6_PLB_busLock => net_gnd0, SPLB6_PLB_MSize => net_gnd2, SPLB6_PLB_size => net_gnd4, SPLB6_PLB_type => net_gnd3(2 downto 0), SPLB6_PLB_lockErr => net_gnd0, SPLB6_PLB_wrPendReq => net_gnd0, SPLB6_PLB_wrPendPri => net_gnd2, SPLB6_PLB_rdPendReq => net_gnd0, SPLB6_PLB_rdPendPri => net_gnd2, SPLB6_PLB_reqPri => net_gnd2, SPLB6_PLB_TAttribute => net_gnd16, SPLB6_PLB_rdBurst => net_gnd0, SPLB6_PLB_wrBurst => net_gnd0, SPLB6_PLB_wrDBus => net_gnd64, SPLB6_Sl_addrAck => open, SPLB6_Sl_SSize => open, SPLB6_Sl_wait => open, SPLB6_Sl_rearbitrate => open, SPLB6_Sl_wrDAck => open, SPLB6_Sl_wrComp => open, SPLB6_Sl_wrBTerm => open, SPLB6_Sl_rdDBus => open, SPLB6_Sl_rdWdAddr => open, SPLB6_Sl_rdDAck => open, SPLB6_Sl_rdComp => open, SPLB6_Sl_rdBTerm => open, SPLB6_Sl_MBusy => open, SPLB6_Sl_MRdErr => open, SPLB6_Sl_MWrErr => open, SPLB6_Sl_MIRQ => open, SDMA6_Clk => net_gnd0, SDMA6_Rx_IntOut => open, SDMA6_Tx_IntOut => open, SDMA6_RstOut => open, SDMA6_TX_D => open, SDMA6_TX_Rem => open, SDMA6_TX_SOF => open, SDMA6_TX_EOF => open, SDMA6_TX_SOP => open, SDMA6_TX_EOP => open, SDMA6_TX_Src_Rdy => open, SDMA6_TX_Dst_Rdy => net_vcc0, SDMA6_RX_D => net_gnd32, SDMA6_RX_Rem => net_vcc4, SDMA6_RX_SOF => net_vcc0, SDMA6_RX_EOF => net_vcc0, SDMA6_RX_SOP => net_vcc0, SDMA6_RX_EOP => net_vcc0, SDMA6_RX_Src_Rdy => net_vcc0, SDMA6_RX_Dst_Rdy => open, SDMA_CTRL6_Clk => net_vcc0, SDMA_CTRL6_Rst => net_gnd0, SDMA_CTRL6_PLB_ABus => net_gnd32, SDMA_CTRL6_PLB_PAValid => net_gnd0, SDMA_CTRL6_PLB_SAValid => net_gnd0, SDMA_CTRL6_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL6_PLB_RNW => net_gnd0, SDMA_CTRL6_PLB_BE => net_gnd8, SDMA_CTRL6_PLB_UABus => net_gnd32, SDMA_CTRL6_PLB_rdPrim => net_gnd0, SDMA_CTRL6_PLB_wrPrim => net_gnd0, SDMA_CTRL6_PLB_abort => net_gnd0, SDMA_CTRL6_PLB_busLock => net_gnd0, SDMA_CTRL6_PLB_MSize => net_gnd2, SDMA_CTRL6_PLB_size => net_gnd4, SDMA_CTRL6_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL6_PLB_lockErr => net_gnd0, SDMA_CTRL6_PLB_wrPendReq => net_gnd0, SDMA_CTRL6_PLB_wrPendPri => net_gnd2, SDMA_CTRL6_PLB_rdPendReq => net_gnd0, SDMA_CTRL6_PLB_rdPendPri => net_gnd2, SDMA_CTRL6_PLB_reqPri => net_gnd2, SDMA_CTRL6_PLB_TAttribute => net_gnd16, SDMA_CTRL6_PLB_rdBurst => net_gnd0, SDMA_CTRL6_PLB_wrBurst => net_gnd0, SDMA_CTRL6_PLB_wrDBus => net_gnd64, SDMA_CTRL6_Sl_addrAck => open, SDMA_CTRL6_Sl_SSize => open, SDMA_CTRL6_Sl_wait => open, SDMA_CTRL6_Sl_rearbitrate => open, SDMA_CTRL6_Sl_wrDAck => open, SDMA_CTRL6_Sl_wrComp => open, SDMA_CTRL6_Sl_wrBTerm => open, SDMA_CTRL6_Sl_rdDBus => open, SDMA_CTRL6_Sl_rdWdAddr => open, SDMA_CTRL6_Sl_rdDAck => open, SDMA_CTRL6_Sl_rdComp => open, SDMA_CTRL6_Sl_rdBTerm => open, SDMA_CTRL6_Sl_MBusy => open, SDMA_CTRL6_Sl_MRdErr => open, SDMA_CTRL6_Sl_MWrErr => open, SDMA_CTRL6_Sl_MIRQ => open, PIM6_Addr => net_gnd32(0 to 31), PIM6_AddrReq => net_gnd0, PIM6_AddrAck => open, PIM6_RNW => net_gnd0, PIM6_Size => net_gnd4(0 to 3), PIM6_RdModWr => net_gnd0, PIM6_WrFIFO_Data => net_gnd64(0 to 63), PIM6_WrFIFO_BE => net_gnd8(0 to 7), PIM6_WrFIFO_Push => net_gnd0, PIM6_RdFIFO_Data => open, PIM6_RdFIFO_Pop => net_gnd0, PIM6_RdFIFO_RdWdAddr => open, PIM6_WrFIFO_Empty => open, PIM6_WrFIFO_AlmostFull => open, PIM6_WrFIFO_Flush => net_gnd0, PIM6_RdFIFO_Empty => open, PIM6_RdFIFO_Flush => net_gnd0, PIM6_RdFIFO_Latency => open, PIM6_InitDone => open, PPC440MC6_MIMCReadNotWrite => net_gnd0, PPC440MC6_MIMCAddress => net_gnd36, PPC440MC6_MIMCAddressValid => net_gnd0, PPC440MC6_MIMCWriteData => net_gnd128, PPC440MC6_MIMCWriteDataValid => net_gnd0, PPC440MC6_MIMCByteEnable => net_gnd16, PPC440MC6_MIMCBankConflict => net_gnd0, PPC440MC6_MIMCRowConflict => net_gnd0, PPC440MC6_MCMIReadData => open, PPC440MC6_MCMIReadDataValid => open, PPC440MC6_MCMIReadDataErr => open, PPC440MC6_MCMIAddrReadyToAccept => open, VFBC6_Cmd_Clk => net_gnd0, VFBC6_Cmd_Reset => net_gnd0, VFBC6_Cmd_Data => net_gnd32(0 to 31), VFBC6_Cmd_Write => net_gnd0, VFBC6_Cmd_End => net_gnd0, VFBC6_Cmd_Full => open, VFBC6_Cmd_Almost_Full => open, VFBC6_Cmd_Idle => open, VFBC6_Wd_Clk => net_gnd0, VFBC6_Wd_Reset => net_gnd0, VFBC6_Wd_Write => net_gnd0, VFBC6_Wd_End_Burst => net_gnd0, VFBC6_Wd_Flush => net_gnd0, VFBC6_Wd_Data => net_gnd32(0 to 31), VFBC6_Wd_Data_BE => net_gnd4(0 to 3), VFBC6_Wd_Full => open, VFBC6_Wd_Almost_Full => open, VFBC6_Rd_Clk => net_gnd0, VFBC6_Rd_Reset => net_gnd0, VFBC6_Rd_Read => net_gnd0, VFBC6_Rd_End_Burst => net_gnd0, VFBC6_Rd_Flush => net_gnd0, VFBC6_Rd_Data => open, VFBC6_Rd_Empty => open, VFBC6_Rd_Almost_Empty => open, MCB6_cmd_clk => net_gnd0, MCB6_cmd_en => net_gnd0, MCB6_cmd_instr => net_gnd3, MCB6_cmd_bl => net_gnd6, MCB6_cmd_byte_addr => net_gnd30, MCB6_cmd_empty => open, MCB6_cmd_full => open, MCB6_wr_clk => net_gnd0, MCB6_wr_en => net_gnd0, MCB6_wr_mask => net_gnd8(0 to 7), MCB6_wr_data => net_gnd64(0 to 63), MCB6_wr_full => open, MCB6_wr_empty => open, MCB6_wr_count => open, MCB6_wr_underrun => open, MCB6_wr_error => open, MCB6_rd_clk => net_gnd0, MCB6_rd_en => net_gnd0, MCB6_rd_data => open, MCB6_rd_full => open, MCB6_rd_empty => open, MCB6_rd_count => open, MCB6_rd_overflow => open, MCB6_rd_error => open, FSL7_M_Clk => net_vcc0, FSL7_M_Write => net_gnd0, FSL7_M_Data => net_gnd32, FSL7_M_Control => net_gnd0, FSL7_M_Full => open, FSL7_S_Clk => net_gnd0, FSL7_S_Read => net_gnd0, FSL7_S_Data => open, FSL7_S_Control => open, FSL7_S_Exists => open, FSL7_B_M_Clk => net_vcc0, FSL7_B_M_Write => net_gnd0, FSL7_B_M_Data => net_gnd32, FSL7_B_M_Control => net_gnd0, FSL7_B_M_Full => open, FSL7_B_S_Clk => net_gnd0, FSL7_B_S_Read => net_gnd0, FSL7_B_S_Data => open, FSL7_B_S_Control => open, FSL7_B_S_Exists => open, SPLB7_Clk => net_vcc0, SPLB7_Rst => net_gnd0, SPLB7_PLB_ABus => net_gnd32, SPLB7_PLB_PAValid => net_gnd0, SPLB7_PLB_SAValid => net_gnd0, SPLB7_PLB_masterID => net_gnd1(0 downto 0), SPLB7_PLB_RNW => net_gnd0, SPLB7_PLB_BE => net_gnd8, SPLB7_PLB_UABus => net_gnd32, SPLB7_PLB_rdPrim => net_gnd0, SPLB7_PLB_wrPrim => net_gnd0, SPLB7_PLB_abort => net_gnd0, SPLB7_PLB_busLock => net_gnd0, SPLB7_PLB_MSize => net_gnd2, SPLB7_PLB_size => net_gnd4, SPLB7_PLB_type => net_gnd3(2 downto 0), SPLB7_PLB_lockErr => net_gnd0, SPLB7_PLB_wrPendReq => net_gnd0, SPLB7_PLB_wrPendPri => net_gnd2, SPLB7_PLB_rdPendReq => net_gnd0, SPLB7_PLB_rdPendPri => net_gnd2, SPLB7_PLB_reqPri => net_gnd2, SPLB7_PLB_TAttribute => net_gnd16, SPLB7_PLB_rdBurst => net_gnd0, SPLB7_PLB_wrBurst => net_gnd0, SPLB7_PLB_wrDBus => net_gnd64, SPLB7_Sl_addrAck => open, SPLB7_Sl_SSize => open, SPLB7_Sl_wait => open, SPLB7_Sl_rearbitrate => open, SPLB7_Sl_wrDAck => open, SPLB7_Sl_wrComp => open, SPLB7_Sl_wrBTerm => open, SPLB7_Sl_rdDBus => open, SPLB7_Sl_rdWdAddr => open, SPLB7_Sl_rdDAck => open, SPLB7_Sl_rdComp => open, SPLB7_Sl_rdBTerm => open, SPLB7_Sl_MBusy => open, SPLB7_Sl_MRdErr => open, SPLB7_Sl_MWrErr => open, SPLB7_Sl_MIRQ => open, SDMA7_Clk => net_gnd0, SDMA7_Rx_IntOut => open, SDMA7_Tx_IntOut => open, SDMA7_RstOut => open, SDMA7_TX_D => open, SDMA7_TX_Rem => open, SDMA7_TX_SOF => open, SDMA7_TX_EOF => open, SDMA7_TX_SOP => open, SDMA7_TX_EOP => open, SDMA7_TX_Src_Rdy => open, SDMA7_TX_Dst_Rdy => net_vcc0, SDMA7_RX_D => net_gnd32, SDMA7_RX_Rem => net_vcc4, SDMA7_RX_SOF => net_vcc0, SDMA7_RX_EOF => net_vcc0, SDMA7_RX_SOP => net_vcc0, SDMA7_RX_EOP => net_vcc0, SDMA7_RX_Src_Rdy => net_vcc0, SDMA7_RX_Dst_Rdy => open, SDMA_CTRL7_Clk => net_vcc0, SDMA_CTRL7_Rst => net_gnd0, SDMA_CTRL7_PLB_ABus => net_gnd32, SDMA_CTRL7_PLB_PAValid => net_gnd0, SDMA_CTRL7_PLB_SAValid => net_gnd0, SDMA_CTRL7_PLB_masterID => net_gnd1(0 downto 0), SDMA_CTRL7_PLB_RNW => net_gnd0, SDMA_CTRL7_PLB_BE => net_gnd8, SDMA_CTRL7_PLB_UABus => net_gnd32, SDMA_CTRL7_PLB_rdPrim => net_gnd0, SDMA_CTRL7_PLB_wrPrim => net_gnd0, SDMA_CTRL7_PLB_abort => net_gnd0, SDMA_CTRL7_PLB_busLock => net_gnd0, SDMA_CTRL7_PLB_MSize => net_gnd2, SDMA_CTRL7_PLB_size => net_gnd4, SDMA_CTRL7_PLB_type => net_gnd3(2 downto 0), SDMA_CTRL7_PLB_lockErr => net_gnd0, SDMA_CTRL7_PLB_wrPendReq => net_gnd0, SDMA_CTRL7_PLB_wrPendPri => net_gnd2, SDMA_CTRL7_PLB_rdPendReq => net_gnd0, SDMA_CTRL7_PLB_rdPendPri => net_gnd2, SDMA_CTRL7_PLB_reqPri => net_gnd2, SDMA_CTRL7_PLB_TAttribute => net_gnd16, SDMA_CTRL7_PLB_rdBurst => net_gnd0, SDMA_CTRL7_PLB_wrBurst => net_gnd0, SDMA_CTRL7_PLB_wrDBus => net_gnd64, SDMA_CTRL7_Sl_addrAck => open, SDMA_CTRL7_Sl_SSize => open, SDMA_CTRL7_Sl_wait => open, SDMA_CTRL7_Sl_rearbitrate => open, SDMA_CTRL7_Sl_wrDAck => open, SDMA_CTRL7_Sl_wrComp => open, SDMA_CTRL7_Sl_wrBTerm => open, SDMA_CTRL7_Sl_rdDBus => open, SDMA_CTRL7_Sl_rdWdAddr => open, SDMA_CTRL7_Sl_rdDAck => open, SDMA_CTRL7_Sl_rdComp => open, SDMA_CTRL7_Sl_rdBTerm => open, SDMA_CTRL7_Sl_MBusy => open, SDMA_CTRL7_Sl_MRdErr => open, SDMA_CTRL7_Sl_MWrErr => open, SDMA_CTRL7_Sl_MIRQ => open, PIM7_Addr => net_gnd32(0 to 31), PIM7_AddrReq => net_gnd0, PIM7_AddrAck => open, PIM7_RNW => net_gnd0, PIM7_Size => net_gnd4(0 to 3), PIM7_RdModWr => net_gnd0, PIM7_WrFIFO_Data => net_gnd64(0 to 63), PIM7_WrFIFO_BE => net_gnd8(0 to 7), PIM7_WrFIFO_Push => net_gnd0, PIM7_RdFIFO_Data => open, PIM7_RdFIFO_Pop => net_gnd0, PIM7_RdFIFO_RdWdAddr => open, PIM7_WrFIFO_Empty => open, PIM7_WrFIFO_AlmostFull => open, PIM7_WrFIFO_Flush => net_gnd0, PIM7_RdFIFO_Empty => open, PIM7_RdFIFO_Flush => net_gnd0, PIM7_RdFIFO_Latency => open, PIM7_InitDone => open, PPC440MC7_MIMCReadNotWrite => net_gnd0, PPC440MC7_MIMCAddress => net_gnd36, PPC440MC7_MIMCAddressValid => net_gnd0, PPC440MC7_MIMCWriteData => net_gnd128, PPC440MC7_MIMCWriteDataValid => net_gnd0, PPC440MC7_MIMCByteEnable => net_gnd16, PPC440MC7_MIMCBankConflict => net_gnd0, PPC440MC7_MIMCRowConflict => net_gnd0, PPC440MC7_MCMIReadData => open, PPC440MC7_MCMIReadDataValid => open, PPC440MC7_MCMIReadDataErr => open, PPC440MC7_MCMIAddrReadyToAccept => open, VFBC7_Cmd_Clk => net_gnd0, VFBC7_Cmd_Reset => net_gnd0, VFBC7_Cmd_Data => net_gnd32(0 to 31), VFBC7_Cmd_Write => net_gnd0, VFBC7_Cmd_End => net_gnd0, VFBC7_Cmd_Full => open, VFBC7_Cmd_Almost_Full => open, VFBC7_Cmd_Idle => open, VFBC7_Wd_Clk => net_gnd0, VFBC7_Wd_Reset => net_gnd0, VFBC7_Wd_Write => net_gnd0, VFBC7_Wd_End_Burst => net_gnd0, VFBC7_Wd_Flush => net_gnd0, VFBC7_Wd_Data => net_gnd32(0 to 31), VFBC7_Wd_Data_BE => net_gnd4(0 to 3), VFBC7_Wd_Full => open, VFBC7_Wd_Almost_Full => open, VFBC7_Rd_Clk => net_gnd0, VFBC7_Rd_Reset => net_gnd0, VFBC7_Rd_Read => net_gnd0, VFBC7_Rd_End_Burst => net_gnd0, VFBC7_Rd_Flush => net_gnd0, VFBC7_Rd_Data => open, VFBC7_Rd_Empty => open, VFBC7_Rd_Almost_Empty => open, MCB7_cmd_clk => net_gnd0, MCB7_cmd_en => net_gnd0, MCB7_cmd_instr => net_gnd3, MCB7_cmd_bl => net_gnd6, MCB7_cmd_byte_addr => net_gnd30, MCB7_cmd_empty => open, MCB7_cmd_full => open, MCB7_wr_clk => net_gnd0, MCB7_wr_en => net_gnd0, MCB7_wr_mask => net_gnd8(0 to 7), MCB7_wr_data => net_gnd64(0 to 63), MCB7_wr_full => open, MCB7_wr_empty => open, MCB7_wr_count => open, MCB7_wr_underrun => open, MCB7_wr_error => open, MCB7_rd_clk => net_gnd0, MCB7_rd_en => net_gnd0, MCB7_rd_data => open, MCB7_rd_full => open, MCB7_rd_empty => open, MCB7_rd_count => open, MCB7_rd_overflow => open, MCB7_rd_error => open, MPMC_CTRL_Clk => net_vcc0, MPMC_CTRL_Rst => net_gnd0, MPMC_CTRL_PLB_ABus => net_gnd32, MPMC_CTRL_PLB_PAValid => net_gnd0, MPMC_CTRL_PLB_SAValid => net_gnd0, MPMC_CTRL_PLB_masterID => net_gnd1(0 downto 0), MPMC_CTRL_PLB_RNW => net_gnd0, MPMC_CTRL_PLB_BE => net_gnd8, MPMC_CTRL_PLB_UABus => net_gnd32, MPMC_CTRL_PLB_rdPrim => net_gnd0, MPMC_CTRL_PLB_wrPrim => net_gnd0, MPMC_CTRL_PLB_abort => net_gnd0, MPMC_CTRL_PLB_busLock => net_gnd0, MPMC_CTRL_PLB_MSize => net_gnd2, MPMC_CTRL_PLB_size => net_gnd4, MPMC_CTRL_PLB_type => net_gnd3(2 downto 0), MPMC_CTRL_PLB_lockErr => net_gnd0, MPMC_CTRL_PLB_wrPendReq => net_gnd0, MPMC_CTRL_PLB_wrPendPri => net_gnd2, MPMC_CTRL_PLB_rdPendReq => net_gnd0, MPMC_CTRL_PLB_rdPendPri => net_gnd2, MPMC_CTRL_PLB_reqPri => net_gnd2, MPMC_CTRL_PLB_TAttribute => net_gnd16, MPMC_CTRL_PLB_rdBurst => net_gnd0, MPMC_CTRL_PLB_wrBurst => net_gnd0, MPMC_CTRL_PLB_wrDBus => net_gnd64, MPMC_CTRL_Sl_addrAck => open, MPMC_CTRL_Sl_SSize => open, MPMC_CTRL_Sl_wait => open, MPMC_CTRL_Sl_rearbitrate => open, MPMC_CTRL_Sl_wrDAck => open, MPMC_CTRL_Sl_wrComp => open, MPMC_CTRL_Sl_wrBTerm => open, MPMC_CTRL_Sl_rdDBus => open, MPMC_CTRL_Sl_rdWdAddr => open, MPMC_CTRL_Sl_rdDAck => open, MPMC_CTRL_Sl_rdComp => open, MPMC_CTRL_Sl_rdBTerm => open, MPMC_CTRL_Sl_MBusy => open, MPMC_CTRL_Sl_MRdErr => open, MPMC_CTRL_Sl_MWrErr => open, MPMC_CTRL_Sl_MIRQ => open, MPMC_Clk0 => clk_125_0000MHzPLL0, MPMC_Clk0_DIV2 => clk_62_5000MHzPLL0, MPMC_Clk90 => clk_125_0000MHz90PLL0, MPMC_Clk_200MHz => clk_200_0000MHz, MPMC_Rst => sys_periph_reset(0), MPMC_Clk_Mem => net_vcc0, MPMC_Clk_Mem_2x => net_vcc0, MPMC_Clk_Mem_2x_180 => net_vcc0, MPMC_Clk_Mem_2x_CE0 => net_vcc0, MPMC_Clk_Mem_2x_CE90 => net_vcc0, MPMC_Clk_Rd_Base => net_vcc0, MPMC_Clk_Mem_2x_bufpll_o => open, MPMC_Clk_Mem_2x_180_bufpll_o => open, MPMC_Clk_Mem_2x_CE0_bufpll_o => open, MPMC_Clk_Mem_2x_CE90_bufpll_o => open, MPMC_PLL_Lock_bufpll_o => open, MPMC_PLL_Lock => net_gnd0, MPMC_Idelayctrl_Rdy_I => net_vcc0, MPMC_Idelayctrl_Rdy_O => open, MPMC_InitDone => open, MPMC_ECC_Intr => open, MPMC_DCM_PSEN => open, MPMC_DCM_PSINCDEC => open, MPMC_DCM_PSDONE => net_gnd0, MPMC_MCB_DRP_Clk => net_vcc0, SDRAM_Clk => open, SDRAM_CE => open, SDRAM_CS_n => open, SDRAM_RAS_n => open, SDRAM_CAS_n => open, SDRAM_WE_n => open, SDRAM_BankAddr => open, SDRAM_Addr => open, SDRAM_DQ => open, SDRAM_DM => open, DDR_Clk => open, DDR_Clk_n => open, DDR_CE => open, DDR_CS_n => open, DDR_RAS_n => open, DDR_CAS_n => open, DDR_WE_n => open, DDR_BankAddr => open, DDR_Addr => open, DDR_DQ => open, DDR_DM => open, DDR_DQS => open, DDR_DQS_Div_O => open, DDR_DQS_Div_I => net_gnd0, DDR2_Clk => fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DDR2_Clk_n => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin, DDR2_CE => fpga_0_DDR2_SDRAM_DDR2_CE_pin, DDR2_CS_n => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin, DDR2_ODT => fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DDR2_RAS_n => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin, DDR2_CAS_n => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin, DDR2_WE_n => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin, DDR2_BankAddr => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DDR2_Addr => fpga_0_DDR2_SDRAM_DDR2_Addr_pin, DDR2_DQ => fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DDR2_DM => fpga_0_DDR2_SDRAM_DDR2_DM_pin, DDR2_DQS => fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DDR2_DQS_n => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin, DDR2_DQS_Div_O => open, DDR2_DQS_Div_I => net_gnd0, DDR3_Clk => open, DDR3_Clk_n => open, DDR3_CE => open, DDR3_CS_n => open, DDR3_ODT => open, DDR3_RAS_n => open, DDR3_CAS_n => open, DDR3_WE_n => open, DDR3_BankAddr => open, DDR3_Addr => open, DDR3_DQ => open, DDR3_DM => open, DDR3_Reset_n => open, DDR3_DQS => open, DDR3_DQS_n => open, mcbx_dram_addr => open, mcbx_dram_ba => open, mcbx_dram_ras_n => open, mcbx_dram_cas_n => open, mcbx_dram_we_n => open, mcbx_dram_cke => open, mcbx_dram_clk => open, mcbx_dram_clk_n => open, mcbx_dram_dq => open, mcbx_dram_dqs => open, mcbx_dram_dqs_n => open, mcbx_dram_udqs => open, mcbx_dram_udqs_n => open, mcbx_dram_udm => open, mcbx_dram_ldm => open, mcbx_dram_odt => open, mcbx_dram_ddr3_rst => open, selfrefresh_enter => net_gnd0, selfrefresh_mode => open, calib_recal => net_gnd0, rzq => open, zio => open ); SRAM : system_sram_wrapper port map ( MCH_SPLB_Clk => clk_125_0000MHzPLL0, RdClk => clk_125_0000MHzPLL0, MCH_SPLB_Rst => mb_plb_SPLB_Rst(1), MCH0_Access_Control => net_gnd0, MCH0_Access_Data => net_gnd32, MCH0_Access_Write => net_gnd0, MCH0_Access_Full => open, MCH0_ReadData_Control => open, MCH0_ReadData_Data => open, MCH0_ReadData_Read => net_gnd0, MCH0_ReadData_Exists => open, MCH1_Access_Control => net_gnd0, MCH1_Access_Data => net_gnd32, MCH1_Access_Write => net_gnd0, MCH1_Access_Full => open, MCH1_ReadData_Control => open, MCH1_ReadData_Data => open, MCH1_ReadData_Read => net_gnd0, MCH1_ReadData_Exists => open, MCH2_Access_Control => net_gnd0, MCH2_Access_Data => net_gnd32, MCH2_Access_Write => net_gnd0, MCH2_Access_Full => open, MCH2_ReadData_Control => open, MCH2_ReadData_Data => open, MCH2_ReadData_Read => net_gnd0, MCH2_ReadData_Exists => open, MCH3_Access_Control => net_gnd0, MCH3_Access_Data => net_gnd32, MCH3_Access_Write => net_gnd0, MCH3_Access_Full => open, MCH3_ReadData_Control => open, MCH3_ReadData_Data => open, MCH3_ReadData_Read => net_gnd0, MCH3_ReadData_Exists => open, PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(1), PLB_wrPrim => mb_plb_PLB_wrPrim(1), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(1), Sl_SSize => mb_plb_Sl_SSize(2 to 3), Sl_wait => mb_plb_Sl_wait(1), Sl_rearbitrate => mb_plb_Sl_rearbitrate(1), Sl_wrDAck => mb_plb_Sl_wrDAck(1), Sl_wrComp => mb_plb_Sl_wrComp(1), Sl_wrBTerm => mb_plb_Sl_wrBTerm(1), Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 127), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7), Sl_rdDAck => mb_plb_Sl_rdDAck(1), Sl_rdComp => mb_plb_Sl_rdComp(1), Sl_rdBTerm => mb_plb_Sl_rdBTerm(1), Sl_MBusy => mb_plb_Sl_MBusy(6 to 11), Sl_MWrErr => mb_plb_Sl_MWrErr(6 to 11), Sl_MRdErr => mb_plb_Sl_MRdErr(6 to 11), Sl_MIRQ => mb_plb_Sl_MIRQ(6 to 11), Mem_DQ_I => fpga_0_SRAM_Mem_DQ_pin_I, Mem_DQ_O => fpga_0_SRAM_Mem_DQ_pin_O, Mem_DQ_T => fpga_0_SRAM_Mem_DQ_pin_T, Mem_A => pgassign9, Mem_RPN => open, Mem_CEN => pgassign1(0 to 0), Mem_OEN => pgassign2(0 to 0), Mem_WEN => fpga_0_SRAM_Mem_WEN_pin, Mem_QWEN => open, Mem_BEN => fpga_0_SRAM_Mem_BEN_pin, Mem_CE => open, Mem_ADV_LDN => fpga_0_SRAM_Mem_ADV_LDN_pin, Mem_LBON => open, Mem_CKEN => open, Mem_RNW => open ); PCIe_Bridge : system_pcie_bridge_wrapper port map ( MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(2), PLB_MTimeout => mb_plb_PLB_MTimeout(2), PLB_MIRQ => mb_plb_PLB_MIRQ(2), PLB_MAddrAck => mb_plb_PLB_MAddrAck(2), PLB_MSSize => mb_plb_PLB_MSSize(4 to 5), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(2), PLB_MBusy => mb_plb_PLB_MBusy(2), PLB_MRdErr => mb_plb_PLB_MRdErr(2), PLB_MWrErr => mb_plb_PLB_MWrErr(2), PLB_MWrDAck => mb_plb_PLB_MWrDAck(2), PLB_MRdDBus => mb_plb_PLB_MRdDBus(128 to 191), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(8 to 11), PLB_MRdDAck => mb_plb_PLB_MRdDAck(2), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(2), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(2), M_request => mb_plb_M_request(2), M_priority => mb_plb_M_priority(4 to 5), M_buslock => mb_plb_M_busLock(2), M_RNW => mb_plb_M_RNW(2), M_BE => mb_plb_M_BE(16 to 23), M_MSize => mb_plb_M_MSize(4 to 5), M_size => mb_plb_M_size(8 to 11), M_type => mb_plb_M_type(6 to 8), M_lockErr => mb_plb_M_lockErr(2), M_abort => mb_plb_M_ABort(2), M_TAttribute => mb_plb_M_TAttribute(32 to 47), M_UABus => mb_plb_M_UABus(64 to 95), M_ABus => mb_plb_M_ABus(64 to 95), M_wrDBus => mb_plb_M_wrDBus(128 to 191), M_wrBurst => mb_plb_M_wrBurst(2), M_rdBurst => mb_plb_M_rdBurst(2), SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(2), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(2), PLB_wrPrim => mb_plb_PLB_wrPrim(2), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(2), Sl_SSize => mb_plb_Sl_SSize(4 to 5), Sl_wait => mb_plb_Sl_wait(2), Sl_rearbitrate => mb_plb_Sl_rearbitrate(2), Sl_wrDAck => mb_plb_Sl_wrDAck(2), Sl_wrComp => mb_plb_Sl_wrComp(2), Sl_wrBTerm => mb_plb_Sl_wrBTerm(2), Sl_rdDBus => mb_plb_Sl_rdDBus(128 to 191), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(8 to 11), Sl_rdDAck => mb_plb_Sl_rdDAck(2), Sl_rdComp => mb_plb_Sl_rdComp(2), Sl_rdBTerm => mb_plb_Sl_rdBTerm(2), Sl_MBusy => mb_plb_Sl_MBusy(12 to 17), Sl_MWrErr => mb_plb_Sl_MWrErr(12 to 17), Sl_MRdErr => mb_plb_Sl_MRdErr(12 to 17), Sl_MIRQ => mb_plb_Sl_MIRQ(12 to 17), REFCLK => PCIe_Diff_Clk, Bridge_Clk => open, RXN => pgassign3(0 to 0), RXP => pgassign4(0 to 0), TXN => pgassign5(0 to 0), TXP => pgassign6(0 to 0), IP2INTC_Irpt => PCIe_Bridge_IP2INTC_Irpt, MSI_request => net_gnd0 ); xps_central_dma_1 : system_xps_central_dma_1_wrapper port map ( SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(3), MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(3), SPLB_ABus => mb_plb_PLB_ABus, SPLB_BE => mb_plb_PLB_BE, SPLB_UABus => mb_plb_PLB_UABus, SPLB_PAValid => mb_plb_PLB_PAValid, SPLB_SAValid => mb_plb_PLB_SAValid, SPLB_rdPrim => mb_plb_PLB_rdPrim(3), SPLB_wrPrim => mb_plb_PLB_wrPrim(3), SPLB_masterID => mb_plb_PLB_masterID, SPLB_abort => mb_plb_PLB_abort, SPLB_busLock => mb_plb_PLB_busLock, SPLB_RNW => mb_plb_PLB_RNW, SPLB_MSize => mb_plb_PLB_MSize, SPLB_size => mb_plb_PLB_size, SPLB_type => mb_plb_PLB_type, SPLB_lockErr => mb_plb_PLB_lockErr, SPLB_wrDBus => mb_plb_PLB_wrDBus, SPLB_wrBurst => mb_plb_PLB_wrBurst, SPLB_rdBurst => mb_plb_PLB_rdBurst, SPLB_wrPendReq => mb_plb_PLB_wrPendReq, SPLB_rdPendReq => mb_plb_PLB_rdPendReq, SPLB_wrPendPri => mb_plb_PLB_wrPendPri, SPLB_rdPendPri => mb_plb_PLB_rdPendPri, SPLB_reqPri => mb_plb_PLB_reqPri, SPLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(3), Sl_SSize => mb_plb_Sl_SSize(6 to 7), Sl_wait => mb_plb_Sl_wait(3), Sl_rearbitrate => mb_plb_Sl_rearbitrate(3), Sl_wrDAck => mb_plb_Sl_wrDAck(3), Sl_wrComp => mb_plb_Sl_wrComp(3), Sl_wrBTerm => mb_plb_Sl_wrBTerm(3), Sl_rdDBus => mb_plb_Sl_rdDBus(192 to 255), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(12 to 15), Sl_rdDAck => mb_plb_Sl_rdDAck(3), Sl_rdComp => mb_plb_Sl_rdComp(3), Sl_rdBTerm => mb_plb_Sl_rdBTerm(3), Sl_MBusy => mb_plb_Sl_MBusy(18 to 23), Sl_MWrErr => mb_plb_Sl_MWrErr(18 to 23), Sl_MRdErr => mb_plb_Sl_MRdErr(18 to 23), Sl_MIRQ => mb_plb_Sl_MIRQ(18 to 23), IP2INTC_Irpt => xps_central_dma_1_IP2INTC_Irpt, MPLB_MAddrAck => mb_plb_PLB_MAddrAck(3), MPLB_MSSize => mb_plb_PLB_MSSize(6 to 7), MPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(3), MPLB_MTimeout => mb_plb_PLB_MTimeout(3), MPLB_MBusy => mb_plb_PLB_MBusy(3), MPLB_MRdErr => mb_plb_PLB_MRdErr(3), MPLB_MWrErr => mb_plb_PLB_MWrErr(3), MPLB_MIRQ => mb_plb_PLB_MIRQ(3), MPLB_MRdDBus => mb_plb_PLB_MRdDBus(192 to 255), MPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(12 to 15), MPLB_MRdDAck => mb_plb_PLB_MRdDAck(3), MPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(3), MPLB_MWrDAck => mb_plb_PLB_MWrDAck(3), MPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(3), M_request => mb_plb_M_request(3), M_priority => mb_plb_M_priority(6 to 7), M_busLock => mb_plb_M_busLock(3), M_RNW => mb_plb_M_RNW(3), M_BE => mb_plb_M_BE(24 to 31), M_MSize => mb_plb_M_MSize(6 to 7), M_size => mb_plb_M_size(12 to 15), M_type => mb_plb_M_type(9 to 11), M_TAttribute => mb_plb_M_TAttribute(48 to 63), M_lockErr => mb_plb_M_lockErr(3), M_abort => mb_plb_M_ABort(3), M_UABus => mb_plb_M_UABus(96 to 127), M_ABus => mb_plb_M_ABus(96 to 127), M_wrDBus => mb_plb_M_wrDBus(192 to 255), M_wrBurst => mb_plb_M_wrBurst(3), M_rdBurst => mb_plb_M_rdBurst(3) ); clock_generator_0 : system_clock_generator_0_wrapper port map ( CLKIN => CLK_S, CLKOUT0 => clk_125_0000MHz90PLL0, CLKOUT1 => clk_125_0000MHzPLL0, CLKOUT2 => clk_200_0000MHz, CLKOUT3 => clk_62_5000MHzPLL0, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, CLKOUT7 => open, CLKOUT8 => open, CLKOUT9 => open, CLKOUT10 => open, CLKOUT11 => open, CLKOUT12 => open, CLKOUT13 => open, CLKOUT14 => open, CLKOUT15 => open, CLKFBIN => SRAM_CLK_FB_s, CLKFBOUT => SRAM_CLK_OUT_s, PSCLK => net_gnd0, PSEN => net_gnd0, PSINCDEC => net_gnd0, PSDONE => open, RST => sys_rst_s, LOCKED => Dcm_all_locked ); mdm_0 : system_mdm_0_wrapper port map ( Interrupt => open, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => net_gnd0, S_AXI_ARESETN => net_gnd0, S_AXI_AWADDR => net_gnd32(0 to 31), S_AXI_AWVALID => net_gnd0, S_AXI_AWREADY => open, S_AXI_WDATA => net_gnd32(0 to 31), S_AXI_WSTRB => net_gnd4(0 to 3), S_AXI_WVALID => net_gnd0, S_AXI_WREADY => open, S_AXI_BRESP => open, S_AXI_BVALID => open, S_AXI_BREADY => net_gnd0, S_AXI_ARADDR => net_gnd32(0 to 31), S_AXI_ARVALID => net_gnd0, S_AXI_ARREADY => open, S_AXI_RDATA => open, S_AXI_RRESP => open, S_AXI_RVALID => open, S_AXI_RREADY => net_gnd0, SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(4), PLB_ABus => mb_plb_PLB_ABus, PLB_UABus => mb_plb_PLB_UABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(4), PLB_wrPrim => mb_plb_PLB_wrPrim(4), PLB_masterID => mb_plb_PLB_masterID, PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_MSize => mb_plb_PLB_MSize, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(4), Sl_SSize => mb_plb_Sl_SSize(8 to 9), Sl_wait => mb_plb_Sl_wait(4), Sl_rearbitrate => mb_plb_Sl_rearbitrate(4), Sl_wrDAck => mb_plb_Sl_wrDAck(4), Sl_wrComp => mb_plb_Sl_wrComp(4), Sl_wrBTerm => mb_plb_Sl_wrBTerm(4), Sl_rdDBus => mb_plb_Sl_rdDBus(256 to 319), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(16 to 19), Sl_rdDAck => mb_plb_Sl_rdDAck(4), Sl_rdComp => mb_plb_Sl_rdComp(4), Sl_rdBTerm => mb_plb_Sl_rdBTerm(4), Sl_MBusy => mb_plb_Sl_MBusy(24 to 29), Sl_MWrErr => mb_plb_Sl_MWrErr(24 to 29), Sl_MRdErr => mb_plb_Sl_MRdErr(24 to 29), Sl_MIRQ => mb_plb_Sl_MIRQ(24 to 29), Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk, Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI, Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO, Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En, Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture, Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift, Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update, Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst, Dbg_Clk_1 => open, Dbg_TDI_1 => open, Dbg_TDO_1 => net_gnd0, Dbg_Reg_En_1 => open, Dbg_Capture_1 => open, Dbg_Shift_1 => open, Dbg_Update_1 => open, Dbg_Rst_1 => open, Dbg_Clk_2 => open, Dbg_TDI_2 => open, Dbg_TDO_2 => net_gnd0, Dbg_Reg_En_2 => open, Dbg_Capture_2 => open, Dbg_Shift_2 => open, Dbg_Update_2 => open, Dbg_Rst_2 => open, Dbg_Clk_3 => open, Dbg_TDI_3 => open, Dbg_TDO_3 => net_gnd0, Dbg_Reg_En_3 => open, Dbg_Capture_3 => open, Dbg_Shift_3 => open, Dbg_Update_3 => open, Dbg_Rst_3 => open, Dbg_Clk_4 => open, Dbg_TDI_4 => open, Dbg_TDO_4 => net_gnd0, Dbg_Reg_En_4 => open, Dbg_Capture_4 => open, Dbg_Shift_4 => open, Dbg_Update_4 => open, Dbg_Rst_4 => open, Dbg_Clk_5 => open, Dbg_TDI_5 => open, Dbg_TDO_5 => net_gnd0, Dbg_Reg_En_5 => open, Dbg_Capture_5 => open, Dbg_Shift_5 => open, Dbg_Update_5 => open, Dbg_Rst_5 => open, Dbg_Clk_6 => open, Dbg_TDI_6 => open, Dbg_TDO_6 => net_gnd0, Dbg_Reg_En_6 => open, Dbg_Capture_6 => open, Dbg_Shift_6 => open, Dbg_Update_6 => open, Dbg_Rst_6 => open, Dbg_Clk_7 => open, Dbg_TDI_7 => open, Dbg_TDO_7 => net_gnd0, Dbg_Reg_En_7 => open, Dbg_Capture_7 => open, Dbg_Shift_7 => open, Dbg_Update_7 => open, Dbg_Rst_7 => open, Dbg_Clk_8 => open, Dbg_TDI_8 => open, Dbg_TDO_8 => net_gnd0, Dbg_Reg_En_8 => open, Dbg_Capture_8 => open, Dbg_Shift_8 => open, Dbg_Update_8 => open, Dbg_Rst_8 => open, Dbg_Clk_9 => open, Dbg_TDI_9 => open, Dbg_TDO_9 => net_gnd0, Dbg_Reg_En_9 => open, Dbg_Capture_9 => open, Dbg_Shift_9 => open, Dbg_Update_9 => open, Dbg_Rst_9 => open, Dbg_Clk_10 => open, Dbg_TDI_10 => open, Dbg_TDO_10 => net_gnd0, Dbg_Reg_En_10 => open, Dbg_Capture_10 => open, Dbg_Shift_10 => open, Dbg_Update_10 => open, Dbg_Rst_10 => open, Dbg_Clk_11 => open, Dbg_TDI_11 => open, Dbg_TDO_11 => net_gnd0, Dbg_Reg_En_11 => open, Dbg_Capture_11 => open, Dbg_Shift_11 => open, Dbg_Update_11 => open, Dbg_Rst_11 => open, Dbg_Clk_12 => open, Dbg_TDI_12 => open, Dbg_TDO_12 => net_gnd0, Dbg_Reg_En_12 => open, Dbg_Capture_12 => open, Dbg_Shift_12 => open, Dbg_Update_12 => open, Dbg_Rst_12 => open, Dbg_Clk_13 => open, Dbg_TDI_13 => open, Dbg_TDO_13 => net_gnd0, Dbg_Reg_En_13 => open, Dbg_Capture_13 => open, Dbg_Shift_13 => open, Dbg_Update_13 => open, Dbg_Rst_13 => open, Dbg_Clk_14 => open, Dbg_TDI_14 => open, Dbg_TDO_14 => net_gnd0, Dbg_Reg_En_14 => open, Dbg_Capture_14 => open, Dbg_Shift_14 => open, Dbg_Update_14 => open, Dbg_Rst_14 => open, Dbg_Clk_15 => open, Dbg_TDI_15 => open, Dbg_TDO_15 => net_gnd0, Dbg_Reg_En_15 => open, Dbg_Capture_15 => open, Dbg_Shift_15 => open, Dbg_Update_15 => open, Dbg_Rst_15 => open, Dbg_Clk_16 => open, Dbg_TDI_16 => open, Dbg_TDO_16 => net_gnd0, Dbg_Reg_En_16 => open, Dbg_Capture_16 => open, Dbg_Shift_16 => open, Dbg_Update_16 => open, Dbg_Rst_16 => open, Dbg_Clk_17 => open, Dbg_TDI_17 => open, Dbg_TDO_17 => net_gnd0, Dbg_Reg_En_17 => open, Dbg_Capture_17 => open, Dbg_Shift_17 => open, Dbg_Update_17 => open, Dbg_Rst_17 => open, Dbg_Clk_18 => open, Dbg_TDI_18 => open, Dbg_TDO_18 => net_gnd0, Dbg_Reg_En_18 => open, Dbg_Capture_18 => open, Dbg_Shift_18 => open, Dbg_Update_18 => open, Dbg_Rst_18 => open, Dbg_Clk_19 => open, Dbg_TDI_19 => open, Dbg_TDO_19 => net_gnd0, Dbg_Reg_En_19 => open, Dbg_Capture_19 => open, Dbg_Shift_19 => open, Dbg_Update_19 => open, Dbg_Rst_19 => open, Dbg_Clk_20 => open, Dbg_TDI_20 => open, Dbg_TDO_20 => net_gnd0, Dbg_Reg_En_20 => open, Dbg_Capture_20 => open, Dbg_Shift_20 => open, Dbg_Update_20 => open, Dbg_Rst_20 => open, Dbg_Clk_21 => open, Dbg_TDI_21 => open, Dbg_TDO_21 => net_gnd0, Dbg_Reg_En_21 => open, Dbg_Capture_21 => open, Dbg_Shift_21 => open, Dbg_Update_21 => open, Dbg_Rst_21 => open, Dbg_Clk_22 => open, Dbg_TDI_22 => open, Dbg_TDO_22 => net_gnd0, Dbg_Reg_En_22 => open, Dbg_Capture_22 => open, Dbg_Shift_22 => open, Dbg_Update_22 => open, Dbg_Rst_22 => open, Dbg_Clk_23 => open, Dbg_TDI_23 => open, Dbg_TDO_23 => net_gnd0, Dbg_Reg_En_23 => open, Dbg_Capture_23 => open, Dbg_Shift_23 => open, Dbg_Update_23 => open, Dbg_Rst_23 => open, Dbg_Clk_24 => open, Dbg_TDI_24 => open, Dbg_TDO_24 => net_gnd0, Dbg_Reg_En_24 => open, Dbg_Capture_24 => open, Dbg_Shift_24 => open, Dbg_Update_24 => open, Dbg_Rst_24 => open, Dbg_Clk_25 => open, Dbg_TDI_25 => open, Dbg_TDO_25 => net_gnd0, Dbg_Reg_En_25 => open, Dbg_Capture_25 => open, Dbg_Shift_25 => open, Dbg_Update_25 => open, Dbg_Rst_25 => open, Dbg_Clk_26 => open, Dbg_TDI_26 => open, Dbg_TDO_26 => net_gnd0, Dbg_Reg_En_26 => open, Dbg_Capture_26 => open, Dbg_Shift_26 => open, Dbg_Update_26 => open, Dbg_Rst_26 => open, Dbg_Clk_27 => open, Dbg_TDI_27 => open, Dbg_TDO_27 => net_gnd0, Dbg_Reg_En_27 => open, Dbg_Capture_27 => open, Dbg_Shift_27 => open, Dbg_Update_27 => open, Dbg_Rst_27 => open, Dbg_Clk_28 => open, Dbg_TDI_28 => open, Dbg_TDO_28 => net_gnd0, Dbg_Reg_En_28 => open, Dbg_Capture_28 => open, Dbg_Shift_28 => open, Dbg_Update_28 => open, Dbg_Rst_28 => open, Dbg_Clk_29 => open, Dbg_TDI_29 => open, Dbg_TDO_29 => net_gnd0, Dbg_Reg_En_29 => open, Dbg_Capture_29 => open, Dbg_Shift_29 => open, Dbg_Update_29 => open, Dbg_Rst_29 => open, Dbg_Clk_30 => open, Dbg_TDI_30 => open, Dbg_TDO_30 => net_gnd0, Dbg_Reg_En_30 => open, Dbg_Capture_30 => open, Dbg_Shift_30 => open, Dbg_Update_30 => open, Dbg_Rst_30 => open, Dbg_Clk_31 => open, Dbg_TDI_31 => open, Dbg_TDO_31 => net_gnd0, Dbg_Reg_En_31 => open, Dbg_Capture_31 => open, Dbg_Shift_31 => open, Dbg_Update_31 => open, Dbg_Rst_31 => open, bscan_tdi => open, bscan_reset => open, bscan_shift => open, bscan_update => open, bscan_capture => open, bscan_sel1 => open, bscan_drck1 => open, bscan_tdo1 => net_gnd0, bscan_ext_tdi => net_gnd0, bscan_ext_reset => net_gnd0, bscan_ext_shift => net_gnd0, bscan_ext_update => net_gnd0, bscan_ext_capture => net_gnd0, bscan_ext_sel => net_gnd0, bscan_ext_drck => net_gnd0, bscan_ext_tdo => open, Ext_JTAG_DRCK => open, Ext_JTAG_RESET => open, Ext_JTAG_SEL => open, Ext_JTAG_CAPTURE => open, Ext_JTAG_SHIFT => open, Ext_JTAG_UPDATE => open, Ext_JTAG_TDI => open, Ext_JTAG_TDO => net_gnd0 ); proc_sys_reset_0 : system_proc_sys_reset_0_wrapper port map ( Slowest_sync_clk => clk_125_0000MHzPLL0, Ext_Reset_In => sys_rst_s, Aux_Reset_In => net_gnd0, MB_Debug_Sys_Rst => Debug_SYS_Rst, Core_Reset_Req_0 => net_gnd0, Chip_Reset_Req_0 => net_gnd0, System_Reset_Req_0 => net_gnd0, Core_Reset_Req_1 => net_gnd0, Chip_Reset_Req_1 => net_gnd0, System_Reset_Req_1 => net_gnd0, Dcm_locked => Dcm_all_locked, RstcPPCresetcore_0 => open, RstcPPCresetchip_0 => open, RstcPPCresetsys_0 => open, RstcPPCresetcore_1 => open, RstcPPCresetchip_1 => open, RstcPPCresetsys_1 => open, MB_Reset => mb_reset, Bus_Struct_Reset => sys_bus_reset(0 to 0), Peripheral_Reset => sys_periph_reset(0 to 0), Interconnect_aresetn => open, Peripheral_aresetn => proc_sys_reset_0_Peripheral_aresetn(0 to 0) ); xps_intc_0 : system_xps_intc_0_wrapper port map ( SPLB_Clk => clk_125_0000MHzPLL0, SPLB_Rst => mb_plb_SPLB_Rst(5), PLB_ABus => mb_plb_PLB_ABus, PLB_PAValid => mb_plb_PLB_PAValid, PLB_masterID => mb_plb_PLB_masterID, PLB_RNW => mb_plb_PLB_RNW, PLB_BE => mb_plb_PLB_BE, PLB_size => mb_plb_PLB_size, PLB_type => mb_plb_PLB_type, PLB_wrDBus => mb_plb_PLB_wrDBus, PLB_UABus => mb_plb_PLB_UABus, PLB_SAValid => mb_plb_PLB_SAValid, PLB_rdPrim => mb_plb_PLB_rdPrim(5), PLB_wrPrim => mb_plb_PLB_wrPrim(5), PLB_abort => mb_plb_PLB_abort, PLB_busLock => mb_plb_PLB_busLock, PLB_MSize => mb_plb_PLB_MSize, PLB_lockErr => mb_plb_PLB_lockErr, PLB_wrBurst => mb_plb_PLB_wrBurst, PLB_rdBurst => mb_plb_PLB_rdBurst, PLB_wrPendReq => mb_plb_PLB_wrPendReq, PLB_rdPendReq => mb_plb_PLB_rdPendReq, PLB_wrPendPri => mb_plb_PLB_wrPendPri, PLB_rdPendPri => mb_plb_PLB_rdPendPri, PLB_reqPri => mb_plb_PLB_reqPri, PLB_TAttribute => mb_plb_PLB_TAttribute, Sl_addrAck => mb_plb_Sl_addrAck(5), Sl_SSize => mb_plb_Sl_SSize(10 to 11), Sl_wait => mb_plb_Sl_wait(5), Sl_rearbitrate => mb_plb_Sl_rearbitrate(5), Sl_wrDAck => mb_plb_Sl_wrDAck(5), Sl_wrComp => mb_plb_Sl_wrComp(5), Sl_rdDBus => mb_plb_Sl_rdDBus(320 to 383), Sl_rdDAck => mb_plb_Sl_rdDAck(5), Sl_rdComp => mb_plb_Sl_rdComp(5), Sl_MBusy => mb_plb_Sl_MBusy(30 to 35), Sl_MWrErr => mb_plb_Sl_MWrErr(30 to 35), Sl_MRdErr => mb_plb_Sl_MRdErr(30 to 35), Sl_wrBTerm => mb_plb_Sl_wrBTerm(5), Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(20 to 23), Sl_rdBTerm => mb_plb_Sl_rdBTerm(5), Sl_MIRQ => mb_plb_Sl_MIRQ(30 to 35), Intr => pgassign10, Irq => microblaze_0_Interrupt ); nfa_accept_samples_generic_hw_top_0 : system_nfa_accept_samples_generic_hw_top_0_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(0), indices_M_request => ac0_plb_M_request(0), indices_M_priority => ac0_plb_M_priority(0 to 1), indices_M_busLock => ac0_plb_M_busLock(0), indices_M_RNW => ac0_plb_M_RNW(0), indices_M_BE => ac0_plb_M_BE(0 to 7), indices_M_MSize => ac0_plb_M_MSize(0 to 1), indices_M_size => ac0_plb_M_size(0 to 3), indices_M_type => ac0_plb_M_type(0 to 2), indices_M_TAttribute => ac0_plb_M_TAttribute(0 to 15), indices_M_lockErr => ac0_plb_M_lockErr(0), indices_M_abort => ac0_plb_M_abort(0), indices_M_UABus => ac0_plb_M_UABus(0 to 31), indices_M_ABus => ac0_plb_M_ABus(0 to 31), indices_M_wrDBus => ac0_plb_M_wrDBus(0 to 63), indices_M_wrBurst => ac0_plb_M_wrBurst(0), indices_M_rdBurst => ac0_plb_M_rdBurst(0), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(0), indices_PLB_MSSize => ac0_plb_PLB_MSSize(0 to 1), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(0), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(0), indices_PLB_MBusy => ac0_plb_PLB_MBusy(0), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(0), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(0), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(0), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(0 to 63), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(0 to 3), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(0), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(0), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(0), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(0), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(1), nfa_finals_buckets_M_request => ac0_plb_M_request(1), nfa_finals_buckets_M_priority => ac0_plb_M_priority(2 to 3), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(1), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(1), nfa_finals_buckets_M_BE => ac0_plb_M_BE(8 to 15), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(2 to 3), nfa_finals_buckets_M_size => ac0_plb_M_size(4 to 7), nfa_finals_buckets_M_type => ac0_plb_M_type(3 to 5), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(16 to 31), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(1), nfa_finals_buckets_M_abort => ac0_plb_M_abort(1), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(32 to 63), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(32 to 63), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(64 to 127), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(1), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(1), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(1), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(2 to 3), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(1), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(1), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(1), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(1), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(1), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(1), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(64 to 127), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(4 to 7), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(1), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(1), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(1), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(1), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(2), nfa_forward_buckets_M_request => ac0_plb_M_request(2), nfa_forward_buckets_M_priority => ac0_plb_M_priority(4 to 5), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(2), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(2), nfa_forward_buckets_M_BE => ac0_plb_M_BE(16 to 23), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(4 to 5), nfa_forward_buckets_M_size => ac0_plb_M_size(8 to 11), nfa_forward_buckets_M_type => ac0_plb_M_type(6 to 8), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(32 to 47), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(2), nfa_forward_buckets_M_abort => ac0_plb_M_abort(2), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(64 to 95), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(64 to 95), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(128 to 191), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(2), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(2), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(2), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(4 to 5), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(2), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(2), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(2), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(2), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(2), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(2), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(128 to 191), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(8 to 11), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(2), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(2), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(2), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(2), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(3), nfa_initials_buckets_M_request => ac0_plb_M_request(3), nfa_initials_buckets_M_priority => ac0_plb_M_priority(6 to 7), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(3), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(3), nfa_initials_buckets_M_BE => ac0_plb_M_BE(24 to 31), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(6 to 7), nfa_initials_buckets_M_size => ac0_plb_M_size(12 to 15), nfa_initials_buckets_M_type => ac0_plb_M_type(9 to 11), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(48 to 63), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(3), nfa_initials_buckets_M_abort => ac0_plb_M_abort(3), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(96 to 127), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(96 to 127), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(192 to 255), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(3), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(3), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(3), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(6 to 7), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(3), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(3), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(3), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(3), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(3), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(3), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(192 to 255), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(12 to 15), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(3), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(3), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(3), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(3), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(4), sample_buffer_M_request => ac0_plb_M_request(4), sample_buffer_M_priority => ac0_plb_M_priority(8 to 9), sample_buffer_M_busLock => ac0_plb_M_busLock(4), sample_buffer_M_RNW => ac0_plb_M_RNW(4), sample_buffer_M_BE => ac0_plb_M_BE(32 to 39), sample_buffer_M_MSize => ac0_plb_M_MSize(8 to 9), sample_buffer_M_size => ac0_plb_M_size(16 to 19), sample_buffer_M_type => ac0_plb_M_type(12 to 14), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(64 to 79), sample_buffer_M_lockErr => ac0_plb_M_lockErr(4), sample_buffer_M_abort => ac0_plb_M_abort(4), sample_buffer_M_UABus => ac0_plb_M_UABus(128 to 159), sample_buffer_M_ABus => ac0_plb_M_ABus(128 to 159), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(256 to 319), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(4), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(4), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(4), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(8 to 9), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(4), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(4), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(4), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(4), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(4), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(4), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(256 to 319), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(16 to 19), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(4), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(4), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(4), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(4), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(6), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(6), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(6), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(6), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(12 to 13), splb_slv0_Sl_wait => mb_plb_Sl_wait(6), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(6), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(6), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(6), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(6), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(384 to 447), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(24 to 27), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(6), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(6), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(6), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(36 to 41), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(36 to 41), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(36 to 41), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(36 to 41) ); nfa_accept_samples_generic_hw_top_1 : system_nfa_accept_samples_generic_hw_top_1_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(5), indices_M_request => ac0_plb_M_request(5), indices_M_priority => ac0_plb_M_priority(10 to 11), indices_M_busLock => ac0_plb_M_busLock(5), indices_M_RNW => ac0_plb_M_RNW(5), indices_M_BE => ac0_plb_M_BE(40 to 47), indices_M_MSize => ac0_plb_M_MSize(10 to 11), indices_M_size => ac0_plb_M_size(20 to 23), indices_M_type => ac0_plb_M_type(15 to 17), indices_M_TAttribute => ac0_plb_M_TAttribute(80 to 95), indices_M_lockErr => ac0_plb_M_lockErr(5), indices_M_abort => ac0_plb_M_abort(5), indices_M_UABus => ac0_plb_M_UABus(160 to 191), indices_M_ABus => ac0_plb_M_ABus(160 to 191), indices_M_wrDBus => ac0_plb_M_wrDBus(320 to 383), indices_M_wrBurst => ac0_plb_M_wrBurst(5), indices_M_rdBurst => ac0_plb_M_rdBurst(5), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(5), indices_PLB_MSSize => ac0_plb_PLB_MSSize(10 to 11), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(5), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(5), indices_PLB_MBusy => ac0_plb_PLB_MBusy(5), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(5), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(5), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(5), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(320 to 383), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(20 to 23), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(5), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(5), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(5), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(5), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(6), nfa_finals_buckets_M_request => ac0_plb_M_request(6), nfa_finals_buckets_M_priority => ac0_plb_M_priority(12 to 13), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(6), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(6), nfa_finals_buckets_M_BE => ac0_plb_M_BE(48 to 55), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(12 to 13), nfa_finals_buckets_M_size => ac0_plb_M_size(24 to 27), nfa_finals_buckets_M_type => ac0_plb_M_type(18 to 20), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(96 to 111), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(6), nfa_finals_buckets_M_abort => ac0_plb_M_abort(6), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(192 to 223), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(192 to 223), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(384 to 447), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(6), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(6), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(6), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(12 to 13), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(6), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(6), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(6), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(6), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(6), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(6), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(384 to 447), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(24 to 27), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(6), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(6), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(6), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(6), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(7), nfa_forward_buckets_M_request => ac0_plb_M_request(7), nfa_forward_buckets_M_priority => ac0_plb_M_priority(14 to 15), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(7), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(7), nfa_forward_buckets_M_BE => ac0_plb_M_BE(56 to 63), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(14 to 15), nfa_forward_buckets_M_size => ac0_plb_M_size(28 to 31), nfa_forward_buckets_M_type => ac0_plb_M_type(21 to 23), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(112 to 127), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(7), nfa_forward_buckets_M_abort => ac0_plb_M_abort(7), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(224 to 255), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(224 to 255), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(448 to 511), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(7), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(7), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(7), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(14 to 15), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(7), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(7), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(7), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(7), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(7), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(7), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(448 to 511), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(28 to 31), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(7), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(7), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(7), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(7), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(8), nfa_initials_buckets_M_request => ac0_plb_M_request(8), nfa_initials_buckets_M_priority => ac0_plb_M_priority(16 to 17), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(8), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(8), nfa_initials_buckets_M_BE => ac0_plb_M_BE(64 to 71), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(16 to 17), nfa_initials_buckets_M_size => ac0_plb_M_size(32 to 35), nfa_initials_buckets_M_type => ac0_plb_M_type(24 to 26), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(128 to 143), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(8), nfa_initials_buckets_M_abort => ac0_plb_M_abort(8), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(256 to 287), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(256 to 287), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(512 to 575), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(8), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(8), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(8), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(16 to 17), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(8), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(8), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(8), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(8), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(8), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(8), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(512 to 575), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(32 to 35), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(8), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(8), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(8), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(8), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(9), sample_buffer_M_request => ac0_plb_M_request(9), sample_buffer_M_priority => ac0_plb_M_priority(18 to 19), sample_buffer_M_busLock => ac0_plb_M_busLock(9), sample_buffer_M_RNW => ac0_plb_M_RNW(9), sample_buffer_M_BE => ac0_plb_M_BE(72 to 79), sample_buffer_M_MSize => ac0_plb_M_MSize(18 to 19), sample_buffer_M_size => ac0_plb_M_size(36 to 39), sample_buffer_M_type => ac0_plb_M_type(27 to 29), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(144 to 159), sample_buffer_M_lockErr => ac0_plb_M_lockErr(9), sample_buffer_M_abort => ac0_plb_M_abort(9), sample_buffer_M_UABus => ac0_plb_M_UABus(288 to 319), sample_buffer_M_ABus => ac0_plb_M_ABus(288 to 319), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(576 to 639), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(9), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(9), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(9), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(18 to 19), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(9), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(9), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(9), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(9), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(9), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(9), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(576 to 639), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(36 to 39), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(9), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(9), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(9), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(9), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(7), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(7), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(7), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(7), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(14 to 15), splb_slv0_Sl_wait => mb_plb_Sl_wait(7), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(7), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(7), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(7), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(7), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(448 to 511), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(28 to 31), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(7), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(7), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(7), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(42 to 47), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(42 to 47), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(42 to 47), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(42 to 47) ); nfa_accept_samples_generic_hw_top_2 : system_nfa_accept_samples_generic_hw_top_2_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac0_plb_MPLB_Rst(10), indices_M_request => ac0_plb_M_request(10), indices_M_priority => ac0_plb_M_priority(20 to 21), indices_M_busLock => ac0_plb_M_busLock(10), indices_M_RNW => ac0_plb_M_RNW(10), indices_M_BE => ac0_plb_M_BE(80 to 87), indices_M_MSize => ac0_plb_M_MSize(20 to 21), indices_M_size => ac0_plb_M_size(40 to 43), indices_M_type => ac0_plb_M_type(30 to 32), indices_M_TAttribute => ac0_plb_M_TAttribute(160 to 175), indices_M_lockErr => ac0_plb_M_lockErr(10), indices_M_abort => ac0_plb_M_abort(10), indices_M_UABus => ac0_plb_M_UABus(320 to 351), indices_M_ABus => ac0_plb_M_ABus(320 to 351), indices_M_wrDBus => ac0_plb_M_wrDBus(640 to 703), indices_M_wrBurst => ac0_plb_M_wrBurst(10), indices_M_rdBurst => ac0_plb_M_rdBurst(10), indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(10), indices_PLB_MSSize => ac0_plb_PLB_MSSize(20 to 21), indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(10), indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(10), indices_PLB_MBusy => ac0_plb_PLB_MBusy(10), indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(10), indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(10), indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(10), indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(640 to 703), indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(40 to 43), indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(10), indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(10), indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(10), indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(10), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(11), nfa_finals_buckets_M_request => ac0_plb_M_request(11), nfa_finals_buckets_M_priority => ac0_plb_M_priority(22 to 23), nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(11), nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(11), nfa_finals_buckets_M_BE => ac0_plb_M_BE(88 to 95), nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(22 to 23), nfa_finals_buckets_M_size => ac0_plb_M_size(44 to 47), nfa_finals_buckets_M_type => ac0_plb_M_type(33 to 35), nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(176 to 191), nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(11), nfa_finals_buckets_M_abort => ac0_plb_M_abort(11), nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(352 to 383), nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(352 to 383), nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(704 to 767), nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(11), nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(11), nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(11), nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(22 to 23), nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(11), nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(11), nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(11), nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(11), nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(11), nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(11), nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(704 to 767), nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(44 to 47), nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(11), nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(11), nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(11), nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(11), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(12), nfa_forward_buckets_M_request => ac0_plb_M_request(12), nfa_forward_buckets_M_priority => ac0_plb_M_priority(24 to 25), nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(12), nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(12), nfa_forward_buckets_M_BE => ac0_plb_M_BE(96 to 103), nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(24 to 25), nfa_forward_buckets_M_size => ac0_plb_M_size(48 to 51), nfa_forward_buckets_M_type => ac0_plb_M_type(36 to 38), nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(192 to 207), nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(12), nfa_forward_buckets_M_abort => ac0_plb_M_abort(12), nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(384 to 415), nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(384 to 415), nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(768 to 831), nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(12), nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(12), nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(12), nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(24 to 25), nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(12), nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(12), nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(12), nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(12), nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(12), nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(12), nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(768 to 831), nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(48 to 51), nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(12), nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(12), nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(12), nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(12), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(13), nfa_initials_buckets_M_request => ac0_plb_M_request(13), nfa_initials_buckets_M_priority => ac0_plb_M_priority(26 to 27), nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(13), nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(13), nfa_initials_buckets_M_BE => ac0_plb_M_BE(104 to 111), nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(26 to 27), nfa_initials_buckets_M_size => ac0_plb_M_size(52 to 55), nfa_initials_buckets_M_type => ac0_plb_M_type(39 to 41), nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(208 to 223), nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(13), nfa_initials_buckets_M_abort => ac0_plb_M_abort(13), nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(416 to 447), nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(416 to 447), nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(832 to 895), nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(13), nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(13), nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(13), nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(26 to 27), nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(13), nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(13), nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(13), nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(13), nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(13), nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(13), nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(832 to 895), nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(52 to 55), nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(13), nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(13), nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(13), nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(13), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(14), sample_buffer_M_request => ac0_plb_M_request(14), sample_buffer_M_priority => ac0_plb_M_priority(28 to 29), sample_buffer_M_busLock => ac0_plb_M_busLock(14), sample_buffer_M_RNW => ac0_plb_M_RNW(14), sample_buffer_M_BE => ac0_plb_M_BE(112 to 119), sample_buffer_M_MSize => ac0_plb_M_MSize(28 to 29), sample_buffer_M_size => ac0_plb_M_size(56 to 59), sample_buffer_M_type => ac0_plb_M_type(42 to 44), sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(224 to 239), sample_buffer_M_lockErr => ac0_plb_M_lockErr(14), sample_buffer_M_abort => ac0_plb_M_abort(14), sample_buffer_M_UABus => ac0_plb_M_UABus(448 to 479), sample_buffer_M_ABus => ac0_plb_M_ABus(448 to 479), sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(896 to 959), sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(14), sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(14), sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(14), sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(28 to 29), sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(14), sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(14), sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(14), sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(14), sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(14), sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(14), sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(896 to 959), sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(56 to 59), sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(14), sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(14), sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(14), sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(14), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(8), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(8), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(8), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(8), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(16 to 17), splb_slv0_Sl_wait => mb_plb_Sl_wait(8), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(8), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(8), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(8), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(8), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(512 to 575), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(32 to 35), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(8), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(8), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(8), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(48 to 53), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(48 to 53), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(48 to 53), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(48 to 53) ); nfa_accept_samples_generic_hw_top_3 : system_nfa_accept_samples_generic_hw_top_3_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(0), indices_M_request => ac1_plb_M_request(0), indices_M_priority => ac1_plb_M_priority(0 to 1), indices_M_busLock => ac1_plb_M_busLock(0), indices_M_RNW => ac1_plb_M_RNW(0), indices_M_BE => ac1_plb_M_BE(0 to 7), indices_M_MSize => ac1_plb_M_MSize(0 to 1), indices_M_size => ac1_plb_M_size(0 to 3), indices_M_type => ac1_plb_M_type(0 to 2), indices_M_TAttribute => ac1_plb_M_TAttribute(0 to 15), indices_M_lockErr => ac1_plb_M_lockErr(0), indices_M_abort => ac1_plb_M_abort(0), indices_M_UABus => ac1_plb_M_UABus(0 to 31), indices_M_ABus => ac1_plb_M_ABus(0 to 31), indices_M_wrDBus => ac1_plb_M_wrDBus(0 to 63), indices_M_wrBurst => ac1_plb_M_wrBurst(0), indices_M_rdBurst => ac1_plb_M_rdBurst(0), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(0), indices_PLB_MSSize => ac1_plb_PLB_MSSize(0 to 1), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(0), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(0), indices_PLB_MBusy => ac1_plb_PLB_MBusy(0), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(0), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(0), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(0), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(0 to 63), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(0 to 3), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(0), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(0), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(0), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(0), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(1), nfa_finals_buckets_M_request => ac1_plb_M_request(1), nfa_finals_buckets_M_priority => ac1_plb_M_priority(2 to 3), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(1), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(1), nfa_finals_buckets_M_BE => ac1_plb_M_BE(8 to 15), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(2 to 3), nfa_finals_buckets_M_size => ac1_plb_M_size(4 to 7), nfa_finals_buckets_M_type => ac1_plb_M_type(3 to 5), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(16 to 31), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(1), nfa_finals_buckets_M_abort => ac1_plb_M_abort(1), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(32 to 63), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(32 to 63), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(64 to 127), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(1), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(1), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(1), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(2 to 3), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(1), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(1), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(1), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(1), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(1), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(1), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(64 to 127), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(4 to 7), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(1), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(1), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(1), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(1), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(2), nfa_forward_buckets_M_request => ac1_plb_M_request(2), nfa_forward_buckets_M_priority => ac1_plb_M_priority(4 to 5), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(2), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(2), nfa_forward_buckets_M_BE => ac1_plb_M_BE(16 to 23), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(4 to 5), nfa_forward_buckets_M_size => ac1_plb_M_size(8 to 11), nfa_forward_buckets_M_type => ac1_plb_M_type(6 to 8), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(32 to 47), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(2), nfa_forward_buckets_M_abort => ac1_plb_M_abort(2), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(64 to 95), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(64 to 95), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(128 to 191), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(2), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(2), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(2), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(4 to 5), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(2), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(2), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(2), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(2), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(2), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(2), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(128 to 191), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(8 to 11), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(2), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(2), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(2), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(2), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(3), nfa_initials_buckets_M_request => ac1_plb_M_request(3), nfa_initials_buckets_M_priority => ac1_plb_M_priority(6 to 7), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(3), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(3), nfa_initials_buckets_M_BE => ac1_plb_M_BE(24 to 31), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(6 to 7), nfa_initials_buckets_M_size => ac1_plb_M_size(12 to 15), nfa_initials_buckets_M_type => ac1_plb_M_type(9 to 11), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(48 to 63), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(3), nfa_initials_buckets_M_abort => ac1_plb_M_abort(3), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(96 to 127), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(96 to 127), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(192 to 255), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(3), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(3), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(3), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(6 to 7), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(3), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(3), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(3), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(3), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(3), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(3), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(192 to 255), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(12 to 15), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(3), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(3), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(3), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(3), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(4), sample_buffer_M_request => ac1_plb_M_request(4), sample_buffer_M_priority => ac1_plb_M_priority(8 to 9), sample_buffer_M_busLock => ac1_plb_M_busLock(4), sample_buffer_M_RNW => ac1_plb_M_RNW(4), sample_buffer_M_BE => ac1_plb_M_BE(32 to 39), sample_buffer_M_MSize => ac1_plb_M_MSize(8 to 9), sample_buffer_M_size => ac1_plb_M_size(16 to 19), sample_buffer_M_type => ac1_plb_M_type(12 to 14), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(64 to 79), sample_buffer_M_lockErr => ac1_plb_M_lockErr(4), sample_buffer_M_abort => ac1_plb_M_abort(4), sample_buffer_M_UABus => ac1_plb_M_UABus(128 to 159), sample_buffer_M_ABus => ac1_plb_M_ABus(128 to 159), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(256 to 319), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(4), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(4), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(4), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(8 to 9), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(4), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(4), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(4), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(4), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(4), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(4), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(256 to 319), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(16 to 19), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(4), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(4), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(4), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(4), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(9), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(9), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(9), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(9), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(18 to 19), splb_slv0_Sl_wait => mb_plb_Sl_wait(9), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(9), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(9), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(9), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(9), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(576 to 639), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(36 to 39), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(9), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(9), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(9), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(54 to 59), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(54 to 59), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(54 to 59), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(54 to 59) ); nfa_accept_samples_generic_hw_top_4 : system_nfa_accept_samples_generic_hw_top_4_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(5), indices_M_request => ac1_plb_M_request(5), indices_M_priority => ac1_plb_M_priority(10 to 11), indices_M_busLock => ac1_plb_M_busLock(5), indices_M_RNW => ac1_plb_M_RNW(5), indices_M_BE => ac1_plb_M_BE(40 to 47), indices_M_MSize => ac1_plb_M_MSize(10 to 11), indices_M_size => ac1_plb_M_size(20 to 23), indices_M_type => ac1_plb_M_type(15 to 17), indices_M_TAttribute => ac1_plb_M_TAttribute(80 to 95), indices_M_lockErr => ac1_plb_M_lockErr(5), indices_M_abort => ac1_plb_M_abort(5), indices_M_UABus => ac1_plb_M_UABus(160 to 191), indices_M_ABus => ac1_plb_M_ABus(160 to 191), indices_M_wrDBus => ac1_plb_M_wrDBus(320 to 383), indices_M_wrBurst => ac1_plb_M_wrBurst(5), indices_M_rdBurst => ac1_plb_M_rdBurst(5), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(5), indices_PLB_MSSize => ac1_plb_PLB_MSSize(10 to 11), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(5), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(5), indices_PLB_MBusy => ac1_plb_PLB_MBusy(5), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(5), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(5), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(5), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(320 to 383), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(20 to 23), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(5), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(5), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(5), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(5), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(6), nfa_finals_buckets_M_request => ac1_plb_M_request(6), nfa_finals_buckets_M_priority => ac1_plb_M_priority(12 to 13), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(6), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(6), nfa_finals_buckets_M_BE => ac1_plb_M_BE(48 to 55), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(12 to 13), nfa_finals_buckets_M_size => ac1_plb_M_size(24 to 27), nfa_finals_buckets_M_type => ac1_plb_M_type(18 to 20), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(96 to 111), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(6), nfa_finals_buckets_M_abort => ac1_plb_M_abort(6), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(192 to 223), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(192 to 223), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(384 to 447), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(6), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(6), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(6), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(12 to 13), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(6), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(6), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(6), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(6), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(6), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(6), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(384 to 447), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(24 to 27), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(6), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(6), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(6), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(6), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(7), nfa_forward_buckets_M_request => ac1_plb_M_request(7), nfa_forward_buckets_M_priority => ac1_plb_M_priority(14 to 15), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(7), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(7), nfa_forward_buckets_M_BE => ac1_plb_M_BE(56 to 63), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(14 to 15), nfa_forward_buckets_M_size => ac1_plb_M_size(28 to 31), nfa_forward_buckets_M_type => ac1_plb_M_type(21 to 23), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(112 to 127), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(7), nfa_forward_buckets_M_abort => ac1_plb_M_abort(7), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(224 to 255), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(224 to 255), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(448 to 511), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(7), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(7), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(7), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(14 to 15), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(7), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(7), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(7), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(7), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(7), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(7), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(448 to 511), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(28 to 31), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(7), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(7), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(7), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(7), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(8), nfa_initials_buckets_M_request => ac1_plb_M_request(8), nfa_initials_buckets_M_priority => ac1_plb_M_priority(16 to 17), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(8), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(8), nfa_initials_buckets_M_BE => ac1_plb_M_BE(64 to 71), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(16 to 17), nfa_initials_buckets_M_size => ac1_plb_M_size(32 to 35), nfa_initials_buckets_M_type => ac1_plb_M_type(24 to 26), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(128 to 143), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(8), nfa_initials_buckets_M_abort => ac1_plb_M_abort(8), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(256 to 287), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(256 to 287), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(512 to 575), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(8), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(8), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(8), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(16 to 17), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(8), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(8), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(8), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(8), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(8), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(8), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(512 to 575), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(32 to 35), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(8), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(8), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(8), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(8), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(9), sample_buffer_M_request => ac1_plb_M_request(9), sample_buffer_M_priority => ac1_plb_M_priority(18 to 19), sample_buffer_M_busLock => ac1_plb_M_busLock(9), sample_buffer_M_RNW => ac1_plb_M_RNW(9), sample_buffer_M_BE => ac1_plb_M_BE(72 to 79), sample_buffer_M_MSize => ac1_plb_M_MSize(18 to 19), sample_buffer_M_size => ac1_plb_M_size(36 to 39), sample_buffer_M_type => ac1_plb_M_type(27 to 29), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(144 to 159), sample_buffer_M_lockErr => ac1_plb_M_lockErr(9), sample_buffer_M_abort => ac1_plb_M_abort(9), sample_buffer_M_UABus => ac1_plb_M_UABus(288 to 319), sample_buffer_M_ABus => ac1_plb_M_ABus(288 to 319), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(576 to 639), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(9), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(9), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(9), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(18 to 19), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(9), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(9), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(9), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(9), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(9), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(9), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(576 to 639), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(36 to 39), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(9), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(9), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(9), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(9), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(10), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(10), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(10), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(10), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(20 to 21), splb_slv0_Sl_wait => mb_plb_Sl_wait(10), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(10), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(10), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(10), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(10), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(640 to 703), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(40 to 43), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(10), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(10), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(10), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(60 to 65), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(60 to 65), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(60 to 65), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(60 to 65) ); ac0_plb : system_ac0_plb_wrapper port map ( PLB_Clk => net_gnd0, SYS_Rst => net_gnd0, PLB_Rst => open, SPLB_Rst => ac0_plb_SPLB_Rst(0 to 0), MPLB_Rst => ac0_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => ac0_plb_M_ABus, M_UABus => ac0_plb_M_UABus, M_BE => ac0_plb_M_BE, M_RNW => ac0_plb_M_RNW, M_abort => ac0_plb_M_abort, M_busLock => ac0_plb_M_busLock, M_TAttribute => ac0_plb_M_TAttribute, M_lockErr => ac0_plb_M_lockErr, M_MSize => ac0_plb_M_MSize, M_priority => ac0_plb_M_priority, M_rdBurst => ac0_plb_M_rdBurst, M_request => ac0_plb_M_request, M_size => ac0_plb_M_size, M_type => ac0_plb_M_type, M_wrBurst => ac0_plb_M_wrBurst, M_wrDBus => ac0_plb_M_wrDBus, Sl_addrAck => ac0_plb_Sl_addrAck(0 to 0), Sl_MRdErr => ac0_plb_Sl_MRdErr, Sl_MWrErr => ac0_plb_Sl_MWrErr, Sl_MBusy => ac0_plb_Sl_MBusy, Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0 to 0), Sl_rdComp => ac0_plb_Sl_rdComp(0 to 0), Sl_rdDAck => ac0_plb_Sl_rdDAck(0 to 0), Sl_rdDBus => ac0_plb_Sl_rdDBus, Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr, Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0 to 0), Sl_SSize => ac0_plb_Sl_SSize, Sl_wait => ac0_plb_Sl_wait(0 to 0), Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0 to 0), Sl_wrComp => ac0_plb_Sl_wrComp(0 to 0), Sl_wrDAck => ac0_plb_Sl_wrDAck(0 to 0), Sl_MIRQ => ac0_plb_Sl_MIRQ, PLB_MIRQ => ac0_plb_PLB_MIRQ, PLB_ABus => ac0_plb_PLB_ABus, PLB_UABus => ac0_plb_PLB_UABus, PLB_BE => ac0_plb_PLB_BE, PLB_MAddrAck => ac0_plb_PLB_MAddrAck, PLB_MTimeout => ac0_plb_PLB_MTimeout, PLB_MBusy => ac0_plb_PLB_MBusy, PLB_MRdErr => ac0_plb_PLB_MRdErr, PLB_MWrErr => ac0_plb_PLB_MWrErr, PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm, PLB_MRdDAck => ac0_plb_PLB_MRdDAck, PLB_MRdDBus => ac0_plb_PLB_MRdDBus, PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr, PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate, PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm, PLB_MWrDAck => ac0_plb_PLB_MWrDAck, PLB_MSSize => ac0_plb_PLB_MSSize, PLB_PAValid => ac0_plb_PLB_PAValid, PLB_RNW => ac0_plb_PLB_RNW, PLB_SAValid => ac0_plb_PLB_SAValid, PLB_abort => ac0_plb_PLB_abort, PLB_busLock => ac0_plb_PLB_busLock, PLB_TAttribute => ac0_plb_PLB_TAttribute, PLB_lockErr => ac0_plb_PLB_lockErr, PLB_masterID => ac0_plb_PLB_masterID, PLB_MSize => ac0_plb_PLB_MSize, PLB_rdPendPri => ac0_plb_PLB_rdPendPri, PLB_wrPendPri => ac0_plb_PLB_wrPendPri, PLB_rdPendReq => ac0_plb_PLB_rdPendReq, PLB_wrPendReq => ac0_plb_PLB_wrPendReq, PLB_rdBurst => ac0_plb_PLB_rdBurst, PLB_rdPrim => ac0_plb_PLB_rdPrim(0 to 0), PLB_reqPri => ac0_plb_PLB_reqPri, PLB_size => ac0_plb_PLB_size, PLB_type => ac0_plb_PLB_type, PLB_wrBurst => ac0_plb_PLB_wrBurst, PLB_wrDBus => ac0_plb_PLB_wrDBus, PLB_wrPrim => ac0_plb_PLB_wrPrim(0 to 0), PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ac0_mb_bridge : system_ac0_mb_bridge_wrapper port map ( SPLB_Clk => net_gnd0, SPLB_Rst => ac0_plb_SPLB_Rst(0), IP2INTC_Irpt => open, PLB_ABus => ac0_plb_PLB_ABus, PLB_UABus => ac0_plb_PLB_UABus, PLB_PAValid => ac0_plb_PLB_PAValid, PLB_SAValid => ac0_plb_PLB_SAValid, PLB_rdPrim => ac0_plb_PLB_rdPrim(0), PLB_wrPrim => ac0_plb_PLB_wrPrim(0), PLB_masterID => ac0_plb_PLB_masterID, PLB_abort => ac0_plb_PLB_abort, PLB_busLock => ac0_plb_PLB_busLock, PLB_RNW => ac0_plb_PLB_RNW, PLB_BE => ac0_plb_PLB_BE, PLB_MSize => ac0_plb_PLB_MSize, PLB_size => ac0_plb_PLB_size, PLB_type => ac0_plb_PLB_type, PLB_lockErr => ac0_plb_PLB_lockErr, PLB_wrDBus => ac0_plb_PLB_wrDBus, PLB_wrBurst => ac0_plb_PLB_wrBurst, PLB_rdBurst => ac0_plb_PLB_rdBurst, PLB_wrPendReq => ac0_plb_PLB_wrPendReq, PLB_rdPendReq => ac0_plb_PLB_rdPendReq, PLB_wrPendPri => ac0_plb_PLB_wrPendPri, PLB_rdPendPri => ac0_plb_PLB_rdPendPri, PLB_reqPri => ac0_plb_PLB_reqPri, PLB_TAttribute => ac0_plb_PLB_TAttribute, Sl_addrAck => ac0_plb_Sl_addrAck(0), Sl_SSize => ac0_plb_Sl_SSize, Sl_wait => ac0_plb_Sl_wait(0), Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0), Sl_wrDAck => ac0_plb_Sl_wrDAck(0), Sl_wrComp => ac0_plb_Sl_wrComp(0), Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0), Sl_rdDBus => ac0_plb_Sl_rdDBus, Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr, Sl_rdDAck => ac0_plb_Sl_rdDAck(0), Sl_rdComp => ac0_plb_Sl_rdComp(0), Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0), Sl_MBusy => ac0_plb_Sl_MBusy, Sl_MWrErr => ac0_plb_Sl_MWrErr, Sl_MRdErr => ac0_plb_Sl_MRdErr, Sl_MIRQ => ac0_plb_Sl_MIRQ, MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(4), M_request => mb_plb_M_request(4), M_priority => mb_plb_M_priority(8 to 9), M_busLock => mb_plb_M_busLock(4), M_RNW => mb_plb_M_RNW(4), M_BE => mb_plb_M_BE(32 to 39), M_MSize => mb_plb_M_MSize(8 to 9), M_size => mb_plb_M_size(16 to 19), M_type => mb_plb_M_type(12 to 14), M_ABus => mb_plb_M_ABus(128 to 159), M_wrBurst => mb_plb_M_wrBurst(4), M_rdBurst => mb_plb_M_rdBurst(4), M_wrDBus => mb_plb_M_wrDBus(256 to 319), PLB_MAddrAck => mb_plb_PLB_MAddrAck(4), PLB_MSSize => mb_plb_PLB_MSSize(8 to 9), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(4), PLB_MTimeout => mb_plb_PLB_MTimeout(4), PLB_MRdErr => mb_plb_PLB_MRdErr(4), PLB_MWrErr => mb_plb_PLB_MWrErr(4), PLB_MRdDBus => mb_plb_PLB_MRdDBus(256 to 319), PLB_MRdDAck => mb_plb_PLB_MRdDAck(4), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(4), PLB_MWrDAck => mb_plb_PLB_MWrDAck(4), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(4), M_TAttribute => mb_plb_M_TAttribute(64 to 79), M_lockErr => mb_plb_M_lockErr(4), M_abort => mb_plb_M_ABort(4), M_UABus => mb_plb_M_UABus(128 to 159), PLB_MBusy => mb_plb_PLB_MBusy(4), PLB_MIRQ => mb_plb_PLB_MIRQ(4), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(16 to 19) ); ac1_plb : system_ac1_plb_wrapper port map ( PLB_Clk => net_gnd0, SYS_Rst => net_gnd0, PLB_Rst => open, SPLB_Rst => ac1_plb_SPLB_Rst(0 to 0), MPLB_Rst => ac1_plb_MPLB_Rst, PLB_dcrAck => open, PLB_dcrDBus => open, DCR_ABus => net_gnd10, DCR_DBus => net_gnd32, DCR_Read => net_gnd0, DCR_Write => net_gnd0, M_ABus => ac1_plb_M_ABus, M_UABus => ac1_plb_M_UABus, M_BE => ac1_plb_M_BE, M_RNW => ac1_plb_M_RNW, M_abort => ac1_plb_M_abort, M_busLock => ac1_plb_M_busLock, M_TAttribute => ac1_plb_M_TAttribute, M_lockErr => ac1_plb_M_lockErr, M_MSize => ac1_plb_M_MSize, M_priority => ac1_plb_M_priority, M_rdBurst => ac1_plb_M_rdBurst, M_request => ac1_plb_M_request, M_size => ac1_plb_M_size, M_type => ac1_plb_M_type, M_wrBurst => ac1_plb_M_wrBurst, M_wrDBus => ac1_plb_M_wrDBus, Sl_addrAck => ac1_plb_Sl_addrAck(0 to 0), Sl_MRdErr => ac1_plb_Sl_MRdErr, Sl_MWrErr => ac1_plb_Sl_MWrErr, Sl_MBusy => ac1_plb_Sl_MBusy, Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0 to 0), Sl_rdComp => ac1_plb_Sl_rdComp(0 to 0), Sl_rdDAck => ac1_plb_Sl_rdDAck(0 to 0), Sl_rdDBus => ac1_plb_Sl_rdDBus, Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr, Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0 to 0), Sl_SSize => ac1_plb_Sl_SSize, Sl_wait => ac1_plb_Sl_wait(0 to 0), Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0 to 0), Sl_wrComp => ac1_plb_Sl_wrComp(0 to 0), Sl_wrDAck => ac1_plb_Sl_wrDAck(0 to 0), Sl_MIRQ => ac1_plb_Sl_MIRQ, PLB_MIRQ => ac1_plb_PLB_MIRQ, PLB_ABus => ac1_plb_PLB_ABus, PLB_UABus => ac1_plb_PLB_UABus, PLB_BE => ac1_plb_PLB_BE, PLB_MAddrAck => ac1_plb_PLB_MAddrAck, PLB_MTimeout => ac1_plb_PLB_MTimeout, PLB_MBusy => ac1_plb_PLB_MBusy, PLB_MRdErr => ac1_plb_PLB_MRdErr, PLB_MWrErr => ac1_plb_PLB_MWrErr, PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm, PLB_MRdDAck => ac1_plb_PLB_MRdDAck, PLB_MRdDBus => ac1_plb_PLB_MRdDBus, PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr, PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate, PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm, PLB_MWrDAck => ac1_plb_PLB_MWrDAck, PLB_MSSize => ac1_plb_PLB_MSSize, PLB_PAValid => ac1_plb_PLB_PAValid, PLB_RNW => ac1_plb_PLB_RNW, PLB_SAValid => ac1_plb_PLB_SAValid, PLB_abort => ac1_plb_PLB_abort, PLB_busLock => ac1_plb_PLB_busLock, PLB_TAttribute => ac1_plb_PLB_TAttribute, PLB_lockErr => ac1_plb_PLB_lockErr, PLB_masterID => ac1_plb_PLB_masterID, PLB_MSize => ac1_plb_PLB_MSize, PLB_rdPendPri => ac1_plb_PLB_rdPendPri, PLB_wrPendPri => ac1_plb_PLB_wrPendPri, PLB_rdPendReq => ac1_plb_PLB_rdPendReq, PLB_wrPendReq => ac1_plb_PLB_wrPendReq, PLB_rdBurst => ac1_plb_PLB_rdBurst, PLB_rdPrim => ac1_plb_PLB_rdPrim(0 to 0), PLB_reqPri => ac1_plb_PLB_reqPri, PLB_size => ac1_plb_PLB_size, PLB_type => ac1_plb_PLB_type, PLB_wrBurst => ac1_plb_PLB_wrBurst, PLB_wrDBus => ac1_plb_PLB_wrDBus, PLB_wrPrim => ac1_plb_PLB_wrPrim(0 to 0), PLB_SaddrAck => open, PLB_SMRdErr => open, PLB_SMWrErr => open, PLB_SMBusy => open, PLB_SrdBTerm => open, PLB_SrdComp => open, PLB_SrdDAck => open, PLB_SrdDBus => open, PLB_SrdWdAddr => open, PLB_Srearbitrate => open, PLB_Sssize => open, PLB_Swait => open, PLB_SwrBTerm => open, PLB_SwrComp => open, PLB_SwrDAck => open, Bus_Error_Det => open ); ac1_mb_bridge : system_ac1_mb_bridge_wrapper port map ( SPLB_Clk => net_gnd0, SPLB_Rst => ac1_plb_SPLB_Rst(0), IP2INTC_Irpt => open, PLB_ABus => ac1_plb_PLB_ABus, PLB_UABus => ac1_plb_PLB_UABus, PLB_PAValid => ac1_plb_PLB_PAValid, PLB_SAValid => ac1_plb_PLB_SAValid, PLB_rdPrim => ac1_plb_PLB_rdPrim(0), PLB_wrPrim => ac1_plb_PLB_wrPrim(0), PLB_masterID => ac1_plb_PLB_masterID, PLB_abort => ac1_plb_PLB_abort, PLB_busLock => ac1_plb_PLB_busLock, PLB_RNW => ac1_plb_PLB_RNW, PLB_BE => ac1_plb_PLB_BE, PLB_MSize => ac1_plb_PLB_MSize, PLB_size => ac1_plb_PLB_size, PLB_type => ac1_plb_PLB_type, PLB_lockErr => ac1_plb_PLB_lockErr, PLB_wrDBus => ac1_plb_PLB_wrDBus, PLB_wrBurst => ac1_plb_PLB_wrBurst, PLB_rdBurst => ac1_plb_PLB_rdBurst, PLB_wrPendReq => ac1_plb_PLB_wrPendReq, PLB_rdPendReq => ac1_plb_PLB_rdPendReq, PLB_wrPendPri => ac1_plb_PLB_wrPendPri, PLB_rdPendPri => ac1_plb_PLB_rdPendPri, PLB_reqPri => ac1_plb_PLB_reqPri, PLB_TAttribute => ac1_plb_PLB_TAttribute, Sl_addrAck => ac1_plb_Sl_addrAck(0), Sl_SSize => ac1_plb_Sl_SSize, Sl_wait => ac1_plb_Sl_wait(0), Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0), Sl_wrDAck => ac1_plb_Sl_wrDAck(0), Sl_wrComp => ac1_plb_Sl_wrComp(0), Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0), Sl_rdDBus => ac1_plb_Sl_rdDBus, Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr, Sl_rdDAck => ac1_plb_Sl_rdDAck(0), Sl_rdComp => ac1_plb_Sl_rdComp(0), Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0), Sl_MBusy => ac1_plb_Sl_MBusy, Sl_MWrErr => ac1_plb_Sl_MWrErr, Sl_MRdErr => ac1_plb_Sl_MRdErr, Sl_MIRQ => ac1_plb_Sl_MIRQ, MPLB_Clk => clk_125_0000MHzPLL0, MPLB_Rst => mb_plb_MPLB_Rst(5), M_request => mb_plb_M_request(5), M_priority => mb_plb_M_priority(10 to 11), M_busLock => mb_plb_M_busLock(5), M_RNW => mb_plb_M_RNW(5), M_BE => mb_plb_M_BE(40 to 47), M_MSize => mb_plb_M_MSize(10 to 11), M_size => mb_plb_M_size(20 to 23), M_type => mb_plb_M_type(15 to 17), M_ABus => mb_plb_M_ABus(160 to 191), M_wrBurst => mb_plb_M_wrBurst(5), M_rdBurst => mb_plb_M_rdBurst(5), M_wrDBus => mb_plb_M_wrDBus(320 to 383), PLB_MAddrAck => mb_plb_PLB_MAddrAck(5), PLB_MSSize => mb_plb_PLB_MSSize(10 to 11), PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(5), PLB_MTimeout => mb_plb_PLB_MTimeout(5), PLB_MRdErr => mb_plb_PLB_MRdErr(5), PLB_MWrErr => mb_plb_PLB_MWrErr(5), PLB_MRdDBus => mb_plb_PLB_MRdDBus(320 to 383), PLB_MRdDAck => mb_plb_PLB_MRdDAck(5), PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(5), PLB_MWrDAck => mb_plb_PLB_MWrDAck(5), PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(5), M_TAttribute => mb_plb_M_TAttribute(80 to 95), M_lockErr => mb_plb_M_lockErr(5), M_abort => mb_plb_M_ABort(5), M_UABus => mb_plb_M_UABus(160 to 191), PLB_MBusy => mb_plb_PLB_MBusy(5), PLB_MIRQ => mb_plb_PLB_MIRQ(5), PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(20 to 23) ); nfa_accept_samples_generic_hw_top_5 : system_nfa_accept_samples_generic_hw_top_5_wrapper port map ( aclk => clk_125_0000MHzPLL0, aresetn => proc_sys_reset_0_Peripheral_aresetn(0), indices_MPLB_Clk => net_gnd0, indices_MPLB_Rst => ac1_plb_MPLB_Rst(10), indices_M_request => ac1_plb_M_request(10), indices_M_priority => ac1_plb_M_priority(20 to 21), indices_M_busLock => ac1_plb_M_busLock(10), indices_M_RNW => ac1_plb_M_RNW(10), indices_M_BE => ac1_plb_M_BE(80 to 87), indices_M_MSize => ac1_plb_M_MSize(20 to 21), indices_M_size => ac1_plb_M_size(40 to 43), indices_M_type => ac1_plb_M_type(30 to 32), indices_M_TAttribute => ac1_plb_M_TAttribute(160 to 175), indices_M_lockErr => ac1_plb_M_lockErr(10), indices_M_abort => ac1_plb_M_abort(10), indices_M_UABus => ac1_plb_M_UABus(320 to 351), indices_M_ABus => ac1_plb_M_ABus(320 to 351), indices_M_wrDBus => ac1_plb_M_wrDBus(640 to 703), indices_M_wrBurst => ac1_plb_M_wrBurst(10), indices_M_rdBurst => ac1_plb_M_rdBurst(10), indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(10), indices_PLB_MSSize => ac1_plb_PLB_MSSize(20 to 21), indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(10), indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(10), indices_PLB_MBusy => ac1_plb_PLB_MBusy(10), indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(10), indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(10), indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(10), indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(640 to 703), indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(40 to 43), indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(10), indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(10), indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(10), indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(10), nfa_finals_buckets_MPLB_Clk => net_gnd0, nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(11), nfa_finals_buckets_M_request => ac1_plb_M_request(11), nfa_finals_buckets_M_priority => ac1_plb_M_priority(22 to 23), nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(11), nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(11), nfa_finals_buckets_M_BE => ac1_plb_M_BE(88 to 95), nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(22 to 23), nfa_finals_buckets_M_size => ac1_plb_M_size(44 to 47), nfa_finals_buckets_M_type => ac1_plb_M_type(33 to 35), nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(176 to 191), nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(11), nfa_finals_buckets_M_abort => ac1_plb_M_abort(11), nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(352 to 383), nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(352 to 383), nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(704 to 767), nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(11), nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(11), nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(11), nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(22 to 23), nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(11), nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(11), nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(11), nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(11), nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(11), nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(11), nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(704 to 767), nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(44 to 47), nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(11), nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(11), nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(11), nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(11), nfa_forward_buckets_MPLB_Clk => net_gnd0, nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(12), nfa_forward_buckets_M_request => ac1_plb_M_request(12), nfa_forward_buckets_M_priority => ac1_plb_M_priority(24 to 25), nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(12), nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(12), nfa_forward_buckets_M_BE => ac1_plb_M_BE(96 to 103), nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(24 to 25), nfa_forward_buckets_M_size => ac1_plb_M_size(48 to 51), nfa_forward_buckets_M_type => ac1_plb_M_type(36 to 38), nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(192 to 207), nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(12), nfa_forward_buckets_M_abort => ac1_plb_M_abort(12), nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(384 to 415), nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(384 to 415), nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(768 to 831), nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(12), nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(12), nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(12), nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(24 to 25), nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(12), nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(12), nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(12), nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(12), nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(12), nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(12), nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(768 to 831), nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(48 to 51), nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(12), nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(12), nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(12), nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(12), nfa_initials_buckets_MPLB_Clk => net_gnd0, nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(13), nfa_initials_buckets_M_request => ac1_plb_M_request(13), nfa_initials_buckets_M_priority => ac1_plb_M_priority(26 to 27), nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(13), nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(13), nfa_initials_buckets_M_BE => ac1_plb_M_BE(104 to 111), nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(26 to 27), nfa_initials_buckets_M_size => ac1_plb_M_size(52 to 55), nfa_initials_buckets_M_type => ac1_plb_M_type(39 to 41), nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(208 to 223), nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(13), nfa_initials_buckets_M_abort => ac1_plb_M_abort(13), nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(416 to 447), nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(416 to 447), nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(832 to 895), nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(13), nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(13), nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(13), nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(26 to 27), nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(13), nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(13), nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(13), nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(13), nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(13), nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(13), nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(832 to 895), nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(52 to 55), nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(13), nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(13), nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(13), nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(13), sample_buffer_MPLB_Clk => net_gnd0, sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(14), sample_buffer_M_request => ac1_plb_M_request(14), sample_buffer_M_priority => ac1_plb_M_priority(28 to 29), sample_buffer_M_busLock => ac1_plb_M_busLock(14), sample_buffer_M_RNW => ac1_plb_M_RNW(14), sample_buffer_M_BE => ac1_plb_M_BE(112 to 119), sample_buffer_M_MSize => ac1_plb_M_MSize(28 to 29), sample_buffer_M_size => ac1_plb_M_size(56 to 59), sample_buffer_M_type => ac1_plb_M_type(42 to 44), sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(224 to 239), sample_buffer_M_lockErr => ac1_plb_M_lockErr(14), sample_buffer_M_abort => ac1_plb_M_abort(14), sample_buffer_M_UABus => ac1_plb_M_UABus(448 to 479), sample_buffer_M_ABus => ac1_plb_M_ABus(448 to 479), sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(896 to 959), sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(14), sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(14), sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(14), sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(28 to 29), sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(14), sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(14), sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(14), sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(14), sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(14), sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(14), sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(896 to 959), sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(56 to 59), sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(14), sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(14), sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(14), sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(14), splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0, splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(11), splb_slv0_PLB_ABus => mb_plb_PLB_ABus, splb_slv0_PLB_UABus => mb_plb_PLB_UABus, splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid, splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid, splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(11), splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(11), splb_slv0_PLB_masterID => mb_plb_PLB_masterID, splb_slv0_PLB_abort => mb_plb_PLB_abort, splb_slv0_PLB_busLock => mb_plb_PLB_busLock, splb_slv0_PLB_RNW => mb_plb_PLB_RNW, splb_slv0_PLB_BE => mb_plb_PLB_BE, splb_slv0_PLB_MSize => mb_plb_PLB_MSize, splb_slv0_PLB_size => mb_plb_PLB_size, splb_slv0_PLB_type => mb_plb_PLB_type, splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr, splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus, splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst, splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst, splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq, splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq, splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri, splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri, splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri, splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute, splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(11), splb_slv0_Sl_SSize => mb_plb_Sl_SSize(22 to 23), splb_slv0_Sl_wait => mb_plb_Sl_wait(11), splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(11), splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(11), splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(11), splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(11), splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(704 to 767), splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(44 to 47), splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(11), splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(11), splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(11), splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(66 to 71), splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(66 to 71), splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(66 to 71), splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(66 to 71) ); iobuf_0 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(0), IO => fpga_0_SRAM_Mem_DQ_pin(0), O => fpga_0_SRAM_Mem_DQ_pin_I(0), T => fpga_0_SRAM_Mem_DQ_pin_T(0) ); iobuf_1 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(1), IO => fpga_0_SRAM_Mem_DQ_pin(1), O => fpga_0_SRAM_Mem_DQ_pin_I(1), T => fpga_0_SRAM_Mem_DQ_pin_T(1) ); iobuf_2 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(2), IO => fpga_0_SRAM_Mem_DQ_pin(2), O => fpga_0_SRAM_Mem_DQ_pin_I(2), T => fpga_0_SRAM_Mem_DQ_pin_T(2) ); iobuf_3 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(3), IO => fpga_0_SRAM_Mem_DQ_pin(3), O => fpga_0_SRAM_Mem_DQ_pin_I(3), T => fpga_0_SRAM_Mem_DQ_pin_T(3) ); iobuf_4 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(4), IO => fpga_0_SRAM_Mem_DQ_pin(4), O => fpga_0_SRAM_Mem_DQ_pin_I(4), T => fpga_0_SRAM_Mem_DQ_pin_T(4) ); iobuf_5 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(5), IO => fpga_0_SRAM_Mem_DQ_pin(5), O => fpga_0_SRAM_Mem_DQ_pin_I(5), T => fpga_0_SRAM_Mem_DQ_pin_T(5) ); iobuf_6 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(6), IO => fpga_0_SRAM_Mem_DQ_pin(6), O => fpga_0_SRAM_Mem_DQ_pin_I(6), T => fpga_0_SRAM_Mem_DQ_pin_T(6) ); iobuf_7 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(7), IO => fpga_0_SRAM_Mem_DQ_pin(7), O => fpga_0_SRAM_Mem_DQ_pin_I(7), T => fpga_0_SRAM_Mem_DQ_pin_T(7) ); iobuf_8 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(8), IO => fpga_0_SRAM_Mem_DQ_pin(8), O => fpga_0_SRAM_Mem_DQ_pin_I(8), T => fpga_0_SRAM_Mem_DQ_pin_T(8) ); iobuf_9 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(9), IO => fpga_0_SRAM_Mem_DQ_pin(9), O => fpga_0_SRAM_Mem_DQ_pin_I(9), T => fpga_0_SRAM_Mem_DQ_pin_T(9) ); iobuf_10 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(10), IO => fpga_0_SRAM_Mem_DQ_pin(10), O => fpga_0_SRAM_Mem_DQ_pin_I(10), T => fpga_0_SRAM_Mem_DQ_pin_T(10) ); iobuf_11 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(11), IO => fpga_0_SRAM_Mem_DQ_pin(11), O => fpga_0_SRAM_Mem_DQ_pin_I(11), T => fpga_0_SRAM_Mem_DQ_pin_T(11) ); iobuf_12 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(12), IO => fpga_0_SRAM_Mem_DQ_pin(12), O => fpga_0_SRAM_Mem_DQ_pin_I(12), T => fpga_0_SRAM_Mem_DQ_pin_T(12) ); iobuf_13 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(13), IO => fpga_0_SRAM_Mem_DQ_pin(13), O => fpga_0_SRAM_Mem_DQ_pin_I(13), T => fpga_0_SRAM_Mem_DQ_pin_T(13) ); iobuf_14 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(14), IO => fpga_0_SRAM_Mem_DQ_pin(14), O => fpga_0_SRAM_Mem_DQ_pin_I(14), T => fpga_0_SRAM_Mem_DQ_pin_T(14) ); iobuf_15 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(15), IO => fpga_0_SRAM_Mem_DQ_pin(15), O => fpga_0_SRAM_Mem_DQ_pin_I(15), T => fpga_0_SRAM_Mem_DQ_pin_T(15) ); iobuf_16 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(16), IO => fpga_0_SRAM_Mem_DQ_pin(16), O => fpga_0_SRAM_Mem_DQ_pin_I(16), T => fpga_0_SRAM_Mem_DQ_pin_T(16) ); iobuf_17 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(17), IO => fpga_0_SRAM_Mem_DQ_pin(17), O => fpga_0_SRAM_Mem_DQ_pin_I(17), T => fpga_0_SRAM_Mem_DQ_pin_T(17) ); iobuf_18 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(18), IO => fpga_0_SRAM_Mem_DQ_pin(18), O => fpga_0_SRAM_Mem_DQ_pin_I(18), T => fpga_0_SRAM_Mem_DQ_pin_T(18) ); iobuf_19 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(19), IO => fpga_0_SRAM_Mem_DQ_pin(19), O => fpga_0_SRAM_Mem_DQ_pin_I(19), T => fpga_0_SRAM_Mem_DQ_pin_T(19) ); iobuf_20 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(20), IO => fpga_0_SRAM_Mem_DQ_pin(20), O => fpga_0_SRAM_Mem_DQ_pin_I(20), T => fpga_0_SRAM_Mem_DQ_pin_T(20) ); iobuf_21 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(21), IO => fpga_0_SRAM_Mem_DQ_pin(21), O => fpga_0_SRAM_Mem_DQ_pin_I(21), T => fpga_0_SRAM_Mem_DQ_pin_T(21) ); iobuf_22 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(22), IO => fpga_0_SRAM_Mem_DQ_pin(22), O => fpga_0_SRAM_Mem_DQ_pin_I(22), T => fpga_0_SRAM_Mem_DQ_pin_T(22) ); iobuf_23 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(23), IO => fpga_0_SRAM_Mem_DQ_pin(23), O => fpga_0_SRAM_Mem_DQ_pin_I(23), T => fpga_0_SRAM_Mem_DQ_pin_T(23) ); iobuf_24 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(24), IO => fpga_0_SRAM_Mem_DQ_pin(24), O => fpga_0_SRAM_Mem_DQ_pin_I(24), T => fpga_0_SRAM_Mem_DQ_pin_T(24) ); iobuf_25 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(25), IO => fpga_0_SRAM_Mem_DQ_pin(25), O => fpga_0_SRAM_Mem_DQ_pin_I(25), T => fpga_0_SRAM_Mem_DQ_pin_T(25) ); iobuf_26 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(26), IO => fpga_0_SRAM_Mem_DQ_pin(26), O => fpga_0_SRAM_Mem_DQ_pin_I(26), T => fpga_0_SRAM_Mem_DQ_pin_T(26) ); iobuf_27 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(27), IO => fpga_0_SRAM_Mem_DQ_pin(27), O => fpga_0_SRAM_Mem_DQ_pin_I(27), T => fpga_0_SRAM_Mem_DQ_pin_T(27) ); iobuf_28 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(28), IO => fpga_0_SRAM_Mem_DQ_pin(28), O => fpga_0_SRAM_Mem_DQ_pin_I(28), T => fpga_0_SRAM_Mem_DQ_pin_T(28) ); iobuf_29 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(29), IO => fpga_0_SRAM_Mem_DQ_pin(29), O => fpga_0_SRAM_Mem_DQ_pin_I(29), T => fpga_0_SRAM_Mem_DQ_pin_T(29) ); iobuf_30 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(30), IO => fpga_0_SRAM_Mem_DQ_pin(30), O => fpga_0_SRAM_Mem_DQ_pin_I(30), T => fpga_0_SRAM_Mem_DQ_pin_T(30) ); iobuf_31 : IOBUF port map ( I => fpga_0_SRAM_Mem_DQ_pin_O(31), IO => fpga_0_SRAM_Mem_DQ_pin(31), O => fpga_0_SRAM_Mem_DQ_pin_I(31), T => fpga_0_SRAM_Mem_DQ_pin_T(31) ); ibufgds_32 : IBUFGDS port map ( I => fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin, IB => fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin, O => PCIe_Diff_Clk ); end architecture STRUCTURE;

lgpl-3.0

8c7135c90d2d2c08b28a9ed0b610ce51

0.613645

2.849808

false

grwlf/vsim

vhdl_ct/ct00071.vhd

1

51,479

-- NEED RESULT: ARCH00071.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00071 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00071) -- ENT00071_Test_Bench(ARCH00071_Test_Bench) -- -- REVISION HISTORY: -- -- 06-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00071 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_boolean ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P1" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= transport c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; s_boolean <= transport c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_bit ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P2" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= transport c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; s_bit <= transport c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_severity_level ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P3" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= transport c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; s_severity_level <= transport c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_character ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P4" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= transport c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; s_character <= transport c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_st_enum1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P5" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= transport c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1 <= transport c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_integer ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P6" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= transport c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; s_integer <= transport c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process ( s_st_int1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P7" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= transport c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1 <= transport c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process ( s_time ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P8" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= transport c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; s_time <= transport c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process ( s_st_phys1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P9" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= transport c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1 <= transport c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process ( s_real ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P10" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= transport c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; s_real <= transport c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process ( s_st_real1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P11" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= transport c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1 <= transport c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process ( s_st_rec1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P12" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= transport c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1 <= transport c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process ( s_st_rec2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P13" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= transport c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2 <= transport c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process ( s_st_rec3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P14" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= transport c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3 <= transport c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process ( s_st_arr1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P15" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= transport c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 <= transport c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process ( s_st_arr2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P16" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= transport c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 <= transport c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process ( s_st_arr3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P17" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= transport c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 <= transport c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P17 ; -- -- end ARCH00071 ; -- entity ENT00071_Test_Bench is end ENT00071_Test_Bench ; -- architecture ARCH00071_Test_Bench of ENT00071_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00071 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00071_Test_Bench ;

gpl-3.0

3b0bcb3a4741d340a9f48daea3a5549a

0.5098

4.069808

false

true

false

grwlf/vsim

vhdl_ct/ct00634.vhd

1

84,966

-- NEED RESULT: ARCH00634.P1: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P2: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P3: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P4: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P5: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P6: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P7: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P8: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P9: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P10: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P11: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P12: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P13: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P14: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P15: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P16: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634.P17: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: ARCH00634: Old transactions were removed on signal asg with aggregate of simple names on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00634 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (6) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00634) -- ENT00634_Test_Bench(ARCH00634_Test_Bench) -- -- REVISION HISTORY: -- -- 25-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00634 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- type arr_boolean is array (integer range -1 downto - 3 ) of boolean ; type arr_bit is array (integer range -1 downto - 3 ) of bit ; type arr_severity_level is array (integer range -1 downto - 3 ) of severity_level ; type arr_character is array (integer range -1 downto - 3 ) of character ; type arr_st_enum1 is array (integer range -1 downto - 3 ) of st_enum1 ; type arr_integer is array (integer range -1 downto - 3 ) of integer ; type arr_st_int1 is array (integer range -1 downto - 3 ) of st_int1 ; type arr_time is array (integer range -1 downto - 3 ) of time ; type arr_st_phys1 is array (integer range -1 downto - 3 ) of st_phys1 ; type arr_real is array (integer range -1 downto - 3 ) of real ; type arr_st_real1 is array (integer range -1 downto - 3 ) of st_real1 ; type arr_st_rec1 is array (integer range -1 downto - 3 ) of st_rec1 ; type arr_st_rec2 is array (integer range -1 downto - 3 ) of st_rec2 ; type arr_st_rec3 is array (integer range -1 downto - 3 ) of st_rec3 ; type arr_st_arr1 is array (integer range -1 downto - 3 ) of st_arr1 ; type arr_st_arr2 is array (integer range -1 downto - 3 ) of st_arr2 ; type arr_st_arr3 is array (integer range -1 downto - 3 ) of st_arr3 ; -- signal s_boolean_1 : boolean := c_boolean_1 ; signal s_bit_1 : bit := c_bit_1 ; signal s_severity_level_1 : severity_level := c_severity_level_1 ; signal s_character_1 : character := c_character_1 ; signal s_st_enum1_1 : st_enum1 := c_st_enum1_1 ; signal s_integer_1 : integer := c_integer_1 ; signal s_st_int1_1 : st_int1 := c_st_int1_1 ; signal s_time_1 : time := c_time_1 ; signal s_st_phys1_1 : st_phys1 := c_st_phys1_1 ; signal s_real_1 : real := c_real_1 ; signal s_st_real1_1 : st_real1 := c_st_real1_1 ; signal s_st_rec1_1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_1 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_1 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_1 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_1 : st_arr3 := c_st_arr3_1 ; -- signal s_boolean_2 : boolean := c_boolean_1 ; signal s_bit_2 : bit := c_bit_1 ; signal s_severity_level_2 : severity_level := c_severity_level_1 ; signal s_character_2 : character := c_character_1 ; signal s_st_enum1_2 : st_enum1 := c_st_enum1_1 ; signal s_integer_2 : integer := c_integer_1 ; signal s_st_int1_2 : st_int1 := c_st_int1_1 ; signal s_time_2 : time := c_time_1 ; signal s_st_phys1_2 : st_phys1 := c_st_phys1_1 ; signal s_real_2 : real := c_real_1 ; signal s_st_real1_2 : st_real1 := c_st_real1_1 ; signal s_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- signal s_boolean_3 : boolean := c_boolean_1 ; signal s_bit_3 : bit := c_bit_1 ; signal s_severity_level_3 : severity_level := c_severity_level_1 ; signal s_character_3 : character := c_character_1 ; signal s_st_enum1_3 : st_enum1 := c_st_enum1_1 ; signal s_integer_3 : integer := c_integer_1 ; signal s_st_int1_3 : st_int1 := c_st_int1_1 ; signal s_time_3 : time := c_time_1 ; signal s_st_phys1_3 : st_phys1 := c_st_phys1_1 ; signal s_real_3 : real := c_real_1 ; signal s_st_real1_3 : st_real1 := c_st_real1_1 ; signal s_st_rec1_3 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2_3 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3_3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1_3 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2_3 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3_3 : st_arr3 := c_st_arr3_1 ; -- begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 10 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 20 ns ; -- when 1 => correct := s_boolean_1 = c_boolean_2 and s_boolean_2 = c_boolean_2 and s_boolean_3 = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean_1 = c_boolean_1 and s_boolean_2 = c_boolean_1 and s_boolean_3 = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P1" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 10 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 20 ns, arr_boolean ' ( (c_boolean_2, c_boolean_2, c_boolean_2) ) after 30 ns, arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 40 ns ; -- when 3 => correct := s_boolean_1 = c_boolean_2 and s_boolean_2 = c_boolean_2 and s_boolean_3 = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_boolean_1, s_boolean_2, s_boolean_3) <= transport arr_boolean ' ( (c_boolean_1, c_boolean_1, c_boolean_1) ) after 5 ns ; -- when 4 => correct := correct and s_boolean_1 = c_boolean_1 and s_boolean_2 = c_boolean_1 and s_boolean_3 = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_boolean_1'EVENT and s_boolean_2'EVENT and s_boolean_3'EVENT ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 10 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 20 ns ; -- when 1 => correct := s_bit_1 = c_bit_2 and s_bit_2 = c_bit_2 and s_bit_3 = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit_1 = c_bit_1 and s_bit_2 = c_bit_1 and s_bit_3 = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P2" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 10 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 20 ns, arr_bit ' ( (c_bit_2, c_bit_2, c_bit_2) ) after 30 ns, arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 40 ns ; -- when 3 => correct := s_bit_1 = c_bit_2 and s_bit_2 = c_bit_2 and s_bit_3 = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_bit_1, s_bit_2, s_bit_3) <= transport arr_bit ' ( (c_bit_1, c_bit_1, c_bit_1) ) after 5 ns ; -- when 4 => correct := correct and s_bit_1 = c_bit_1 and s_bit_2 = c_bit_1 and s_bit_3 = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_bit_1'EVENT and s_bit_2'EVENT and s_bit_3'EVENT ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 10 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 20 ns ; -- when 1 => correct := s_severity_level_1 = c_severity_level_2 and s_severity_level_2 = c_severity_level_2 and s_severity_level_3 = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level_1 = c_severity_level_1 and s_severity_level_2 = c_severity_level_1 and s_severity_level_3 = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P3" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 10 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 20 ns, arr_severity_level ' ( (c_severity_level_2, c_severity_level_2, c_severity_level_2) ) after 30 ns, arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 40 ns ; -- when 3 => correct := s_severity_level_1 = c_severity_level_2 and s_severity_level_2 = c_severity_level_2 and s_severity_level_3 = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_severity_level_1, s_severity_level_2, s_severity_level_3) <= transport arr_severity_level ' ( (c_severity_level_1, c_severity_level_1, c_severity_level_1) ) after 5 ns ; -- when 4 => correct := correct and s_severity_level_1 = c_severity_level_1 and s_severity_level_2 = c_severity_level_1 and s_severity_level_3 = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_severity_level_1'EVENT and s_severity_level_2'EVENT and s_severity_level_3'EVENT ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 10 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 20 ns ; -- when 1 => correct := s_character_1 = c_character_2 and s_character_2 = c_character_2 and s_character_3 = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character_1 = c_character_1 and s_character_2 = c_character_1 and s_character_3 = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P4" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 10 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 20 ns, arr_character ' ( (c_character_2, c_character_2, c_character_2) ) after 30 ns, arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 40 ns ; -- when 3 => correct := s_character_1 = c_character_2 and s_character_2 = c_character_2 and s_character_3 = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_character_1, s_character_2, s_character_3) <= transport arr_character ' ( (c_character_1, c_character_1, c_character_1) ) after 5 ns ; -- when 4 => correct := correct and s_character_1 = c_character_1 and s_character_2 = c_character_1 and s_character_3 = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_character_1'EVENT and s_character_2'EVENT and s_character_3'EVENT ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 10 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 20 ns ; -- when 1 => correct := s_st_enum1_1 = c_st_enum1_2 and s_st_enum1_2 = c_st_enum1_2 and s_st_enum1_3 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1_1 = c_st_enum1_1 and s_st_enum1_2 = c_st_enum1_1 and s_st_enum1_3 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P5" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 10 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 20 ns, arr_st_enum1 ' ( (c_st_enum1_2, c_st_enum1_2, c_st_enum1_2) ) after 30 ns, arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 40 ns ; -- when 3 => correct := s_st_enum1_1 = c_st_enum1_2 and s_st_enum1_2 = c_st_enum1_2 and s_st_enum1_3 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_enum1_1, s_st_enum1_2, s_st_enum1_3) <= transport arr_st_enum1 ' ( (c_st_enum1_1, c_st_enum1_1, c_st_enum1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_enum1_1 = c_st_enum1_1 and s_st_enum1_2 = c_st_enum1_1 and s_st_enum1_3 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_enum1_1'EVENT and s_st_enum1_2'EVENT and s_st_enum1_3'EVENT ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 10 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 20 ns ; -- when 1 => correct := s_integer_1 = c_integer_2 and s_integer_2 = c_integer_2 and s_integer_3 = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer_1 = c_integer_1 and s_integer_2 = c_integer_1 and s_integer_3 = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P6" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 10 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 20 ns, arr_integer ' ( (c_integer_2, c_integer_2, c_integer_2) ) after 30 ns, arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 40 ns ; -- when 3 => correct := s_integer_1 = c_integer_2 and s_integer_2 = c_integer_2 and s_integer_3 = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_integer_1, s_integer_2, s_integer_3) <= transport arr_integer ' ( (c_integer_1, c_integer_1, c_integer_1) ) after 5 ns ; -- when 4 => correct := correct and s_integer_1 = c_integer_1 and s_integer_2 = c_integer_1 and s_integer_3 = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_integer_1'EVENT and s_integer_2'EVENT and s_integer_3'EVENT ; end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 10 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 20 ns ; -- when 1 => correct := s_st_int1_1 = c_st_int1_2 and s_st_int1_2 = c_st_int1_2 and s_st_int1_3 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1_1 = c_st_int1_1 and s_st_int1_2 = c_st_int1_1 and s_st_int1_3 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P7" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 10 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 20 ns, arr_st_int1 ' ( (c_st_int1_2, c_st_int1_2, c_st_int1_2) ) after 30 ns, arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 40 ns ; -- when 3 => correct := s_st_int1_1 = c_st_int1_2 and s_st_int1_2 = c_st_int1_2 and s_st_int1_3 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_int1_1, s_st_int1_2, s_st_int1_3) <= transport arr_st_int1 ' ( (c_st_int1_1, c_st_int1_1, c_st_int1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_int1_1 = c_st_int1_1 and s_st_int1_2 = c_st_int1_1 and s_st_int1_3 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_int1_1'EVENT and s_st_int1_2'EVENT and s_st_int1_3'EVENT ; end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 10 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 20 ns ; -- when 1 => correct := s_time_1 = c_time_2 and s_time_2 = c_time_2 and s_time_3 = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time_1 = c_time_1 and s_time_2 = c_time_1 and s_time_3 = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P8" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 10 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 20 ns, arr_time ' ( (c_time_2, c_time_2, c_time_2) ) after 30 ns, arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 40 ns ; -- when 3 => correct := s_time_1 = c_time_2 and s_time_2 = c_time_2 and s_time_3 = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_time_1, s_time_2, s_time_3) <= transport arr_time ' ( (c_time_1, c_time_1, c_time_1) ) after 5 ns ; -- when 4 => correct := correct and s_time_1 = c_time_1 and s_time_2 = c_time_1 and s_time_3 = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_time_1'EVENT and s_time_2'EVENT and s_time_3'EVENT ; end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 10 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 20 ns ; -- when 1 => correct := s_st_phys1_1 = c_st_phys1_2 and s_st_phys1_2 = c_st_phys1_2 and s_st_phys1_3 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1_1 = c_st_phys1_1 and s_st_phys1_2 = c_st_phys1_1 and s_st_phys1_3 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P9" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 10 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 20 ns, arr_st_phys1 ' ( (c_st_phys1_2, c_st_phys1_2, c_st_phys1_2) ) after 30 ns, arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 40 ns ; -- when 3 => correct := s_st_phys1_1 = c_st_phys1_2 and s_st_phys1_2 = c_st_phys1_2 and s_st_phys1_3 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_phys1_1, s_st_phys1_2, s_st_phys1_3) <= transport arr_st_phys1 ' ( (c_st_phys1_1, c_st_phys1_1, c_st_phys1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_phys1_1 = c_st_phys1_1 and s_st_phys1_2 = c_st_phys1_1 and s_st_phys1_3 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_phys1_1'EVENT and s_st_phys1_2'EVENT and s_st_phys1_3'EVENT ; end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 10 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 20 ns ; -- when 1 => correct := s_real_1 = c_real_2 and s_real_2 = c_real_2 and s_real_3 = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real_1 = c_real_1 and s_real_2 = c_real_1 and s_real_3 = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P10" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 10 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 20 ns, arr_real ' ( (c_real_2, c_real_2, c_real_2) ) after 30 ns, arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 40 ns ; -- when 3 => correct := s_real_1 = c_real_2 and s_real_2 = c_real_2 and s_real_3 = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_real_1, s_real_2, s_real_3) <= transport arr_real ' ( (c_real_1, c_real_1, c_real_1) ) after 5 ns ; -- when 4 => correct := correct and s_real_1 = c_real_1 and s_real_2 = c_real_1 and s_real_3 = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_real_1'EVENT and s_real_2'EVENT and s_real_3'EVENT ; end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 10 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 20 ns ; -- when 1 => correct := s_st_real1_1 = c_st_real1_2 and s_st_real1_2 = c_st_real1_2 and s_st_real1_3 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1_1 = c_st_real1_1 and s_st_real1_2 = c_st_real1_1 and s_st_real1_3 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P11" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 10 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 20 ns, arr_st_real1 ' ( (c_st_real1_2, c_st_real1_2, c_st_real1_2) ) after 30 ns, arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 40 ns ; -- when 3 => correct := s_st_real1_1 = c_st_real1_2 and s_st_real1_2 = c_st_real1_2 and s_st_real1_3 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_real1_1, s_st_real1_2, s_st_real1_3) <= transport arr_st_real1 ' ( (c_st_real1_1, c_st_real1_1, c_st_real1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_real1_1 = c_st_real1_1 and s_st_real1_2 = c_st_real1_1 and s_st_real1_3 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_real1_1'EVENT and s_st_real1_2'EVENT and s_st_real1_3'EVENT ; end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 10 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 20 ns ; -- when 1 => correct := s_st_rec1_1 = c_st_rec1_2 and s_st_rec1_2 = c_st_rec1_2 and s_st_rec1_3 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_1 = c_st_rec1_1 and s_st_rec1_2 = c_st_rec1_1 and s_st_rec1_3 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P12" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 10 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 20 ns, arr_st_rec1 ' ( (c_st_rec1_2, c_st_rec1_2, c_st_rec1_2) ) after 30 ns, arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 40 ns ; -- when 3 => correct := s_st_rec1_1 = c_st_rec1_2 and s_st_rec1_2 = c_st_rec1_2 and s_st_rec1_3 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec1_1, s_st_rec1_2, s_st_rec1_3) <= transport arr_st_rec1 ' ( (c_st_rec1_1, c_st_rec1_1, c_st_rec1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec1_1 = c_st_rec1_1 and s_st_rec1_2 = c_st_rec1_1 and s_st_rec1_3 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec1_1'EVENT and s_st_rec1_2'EVENT and s_st_rec1_3'EVENT ; end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 10 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 20 ns ; -- when 1 => correct := s_st_rec2_1 = c_st_rec2_2 and s_st_rec2_2 = c_st_rec2_2 and s_st_rec2_3 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_1 = c_st_rec2_1 and s_st_rec2_2 = c_st_rec2_1 and s_st_rec2_3 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P13" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 10 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 20 ns, arr_st_rec2 ' ( (c_st_rec2_2, c_st_rec2_2, c_st_rec2_2) ) after 30 ns, arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 40 ns ; -- when 3 => correct := s_st_rec2_1 = c_st_rec2_2 and s_st_rec2_2 = c_st_rec2_2 and s_st_rec2_3 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec2_1, s_st_rec2_2, s_st_rec2_3) <= transport arr_st_rec2 ' ( (c_st_rec2_1, c_st_rec2_1, c_st_rec2_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec2_1 = c_st_rec2_1 and s_st_rec2_2 = c_st_rec2_1 and s_st_rec2_3 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec2_1'EVENT and s_st_rec2_2'EVENT and s_st_rec2_3'EVENT ; end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 10 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 20 ns ; -- when 1 => correct := s_st_rec3_1 = c_st_rec3_2 and s_st_rec3_2 = c_st_rec3_2 and s_st_rec3_3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_1 = c_st_rec3_1 and s_st_rec3_2 = c_st_rec3_1 and s_st_rec3_3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P14" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 10 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 20 ns, arr_st_rec3 ' ( (c_st_rec3_2, c_st_rec3_2, c_st_rec3_2) ) after 30 ns, arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 40 ns ; -- when 3 => correct := s_st_rec3_1 = c_st_rec3_2 and s_st_rec3_2 = c_st_rec3_2 and s_st_rec3_3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_rec3_1, s_st_rec3_2, s_st_rec3_3) <= transport arr_st_rec3 ' ( (c_st_rec3_1, c_st_rec3_1, c_st_rec3_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_rec3_1 = c_st_rec3_1 and s_st_rec3_2 = c_st_rec3_1 and s_st_rec3_3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_rec3_1'EVENT and s_st_rec3_2'EVENT and s_st_rec3_3'EVENT ; end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 10 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 20 ns ; -- when 1 => correct := s_st_arr1_1 = c_st_arr1_2 and s_st_arr1_2 = c_st_arr1_2 and s_st_arr1_3 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_1 = c_st_arr1_1 and s_st_arr1_2 = c_st_arr1_1 and s_st_arr1_3 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P15" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 10 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 20 ns, arr_st_arr1 ' ( (c_st_arr1_2, c_st_arr1_2, c_st_arr1_2) ) after 30 ns, arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 40 ns ; -- when 3 => correct := s_st_arr1_1 = c_st_arr1_2 and s_st_arr1_2 = c_st_arr1_2 and s_st_arr1_3 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr1_1, s_st_arr1_2, s_st_arr1_3) <= transport arr_st_arr1 ' ( (c_st_arr1_1, c_st_arr1_1, c_st_arr1_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr1_1 = c_st_arr1_1 and s_st_arr1_2 = c_st_arr1_1 and s_st_arr1_3 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr1_1'EVENT and s_st_arr1_2'EVENT and s_st_arr1_3'EVENT ; end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 10 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 20 ns ; -- when 1 => correct := s_st_arr2_1 = c_st_arr2_2 and s_st_arr2_2 = c_st_arr2_2 and s_st_arr2_3 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_1 = c_st_arr2_1 and s_st_arr2_2 = c_st_arr2_1 and s_st_arr2_3 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P16" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 10 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 20 ns, arr_st_arr2 ' ( (c_st_arr2_2, c_st_arr2_2, c_st_arr2_2) ) after 30 ns, arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 40 ns ; -- when 3 => correct := s_st_arr2_1 = c_st_arr2_2 and s_st_arr2_2 = c_st_arr2_2 and s_st_arr2_3 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr2_1, s_st_arr2_2, s_st_arr2_3) <= transport arr_st_arr2 ' ( (c_st_arr2_1, c_st_arr2_1, c_st_arr2_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_1 = c_st_arr2_1 and s_st_arr2_2 = c_st_arr2_1 and s_st_arr2_3 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr2_1'EVENT and s_st_arr2_2'EVENT and s_st_arr2_3'EVENT ; end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 10 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 20 ns ; -- when 1 => correct := s_st_arr3_1 = c_st_arr3_2 and s_st_arr3_2 = c_st_arr3_2 and s_st_arr3_3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_1 = c_st_arr3_1 and s_st_arr3_2 = c_st_arr3_1 and s_st_arr3_3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00634.P17" , "Multi transport transactions occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 10 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 20 ns, arr_st_arr3 ' ( (c_st_arr3_2, c_st_arr3_2, c_st_arr3_2) ) after 30 ns, arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 40 ns ; -- when 3 => correct := s_st_arr3_1 = c_st_arr3_2 and s_st_arr3_2 = c_st_arr3_2 and s_st_arr3_3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; (s_st_arr3_1, s_st_arr3_2, s_st_arr3_3) <= transport arr_st_arr3 ' ( (c_st_arr3_1, c_st_arr3_1, c_st_arr3_1) ) after 5 ns ; -- when 4 => correct := correct and s_st_arr3_1 = c_st_arr3_1 and s_st_arr3_2 = c_st_arr3_1 and s_st_arr3_3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00634" , "One transport transaction occurred on signal " & "asg with aggregate of simple names on LHS", correct ) ; test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00634" , "Old transactions were removed on signal " & "asg with aggregate of simple names on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until s_st_arr3_1'EVENT and s_st_arr3_2'EVENT and s_st_arr3_3'EVENT ; end process P17 ; -- -- end ARCH00634 ; -- entity ENT00634_Test_Bench is end ENT00634_Test_Bench ; -- architecture ARCH00634_Test_Bench of ENT00634_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00634 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00634_Test_Bench ;

gpl-3.0

a31d2cea095e154a00416d2a889254c0

0.444319

3.854032

false

jairov4/accel-oil

impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_get_finals/_primary.vhd

1

2,755

library verilog; use verilog.vl_types.all; entity nfa_get_finals is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0); ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0); ap_ST_pp0_stg2_fsm_2: vl_logic_vector(0 to 1) := (Hi0, Hi1); ap_ST_pp0_stg3_fsm_3: vl_logic_vector(0 to 1) := (Hi1, Hi1); ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_const_lv32_0 : integer := 0; ap_const_lv32_1 : integer := 1; ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; ap_ce : in vl_logic; nfa_finals_buckets_req_din: out vl_logic; nfa_finals_buckets_req_full_n: in vl_logic; nfa_finals_buckets_req_write: out vl_logic; nfa_finals_buckets_rsp_empty_n: in vl_logic; nfa_finals_buckets_rsp_read: out vl_logic; nfa_finals_buckets_address: out vl_logic_vector(31 downto 0); nfa_finals_buckets_datain: in vl_logic_vector(31 downto 0); nfa_finals_buckets_dataout: out vl_logic_vector(31 downto 0); nfa_finals_buckets_size: out vl_logic_vector(31 downto 0); ap_return_0 : out vl_logic_vector(31 downto 0); ap_return_1 : out vl_logic_vector(31 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg1_fsm_1 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg2_fsm_2 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg3_fsm_3 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end nfa_get_finals;

lgpl-3.0

41a876e40b880a84e5f032333f8ffdc1

0.597096

2.646494

false

MilosSubotic/huffman_coding

RTL/src/rtl/huffman_coding.vhd

1

1,176

------------------------------------------------------------------------------ -- @license MIT -- @brief Huffman coding example. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity huffman_coding is port( i_sw : in std_logic_vector(7 downto 0); o_leds : out std_logic_vector(7 downto 0); on_7_segm_led_disp_a : out std_logic; on_7_segm_led_disp_b : out std_logic; on_7_segm_led_disp_c : out std_logic; on_7_segm_led_disp_d : out std_logic; on_7_segm_led_disp_e : out std_logic; on_7_segm_led_disp_f : out std_logic; on_7_segm_led_disp_g : out std_logic ); end entity huffman_coding; architecture arch_huffman_coding_v1 of huffman_coding is begin on_7_segm_led_disp_a <= i_sw(0); on_7_segm_led_disp_b <= i_sw(1); on_7_segm_led_disp_c <= i_sw(2); on_7_segm_led_disp_d <= i_sw(3); on_7_segm_led_disp_e <= i_sw(4); on_7_segm_led_disp_f <= i_sw(5); on_7_segm_led_disp_g <= i_sw(6); o_leds <= i_sw; end architecture arch_huffman_coding_v1;

mit

7636d16d8a4137b0d0006cfdc33b367f

0.511905

2.60177

false

SamuelLBau/Pool-Shot-Tracking-using-FPGA

examples/sparse_mm/solution1/syn/vhdl/sparse_mm.vhd

1

30,066

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sparse_mm is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; a_address0 : OUT STD_LOGIC_VECTOR (21 downto 0); a_ce0 : OUT STD_LOGIC; a_q0 : IN STD_LOGIC_VECTOR (63 downto 0); a_y : IN STD_LOGIC_VECTOR (31 downto 0); a_x : IN STD_LOGIC_VECTOR (31 downto 0); b_address0 : OUT STD_LOGIC_VECTOR (10 downto 0); b_ce0 : OUT STD_LOGIC; b_q0 : IN STD_LOGIC_VECTOR (31 downto 0); b_y : IN STD_LOGIC_VECTOR (31 downto 0); b_x : IN STD_LOGIC_VECTOR (31 downto 0); c_address0 : OUT STD_LOGIC_VECTOR (10 downto 0); c_ce0 : OUT STD_LOGIC; c_we0 : OUT STD_LOGIC; c_d0 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sparse_mm is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "sparse_mm,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.280000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=462,HLS_SYN_LUT=355}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_34 : BOOLEAN; signal ibx_cast_fu_145_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ibx_cast_reg_258 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_78 : BOOLEAN; signal ibx_1_fu_154_p2 : STD_LOGIC_VECTOR (30 downto 0); signal ibx_1_reg_267 : STD_LOGIC_VECTOR (30 downto 0); signal a_i_1_fu_165_p2 : STD_LOGIC_VECTOR (31 downto 0); signal a_i_1_reg_275 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC; signal ap_sig_bdd_89 : BOOLEAN; signal tmp_1_fu_160_p2 : STD_LOGIC_VECTOR (0 downto 0); signal column_cast_fu_190_p1 : STD_LOGIC_VECTOR (31 downto 0); signal column_cast_reg_289 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC; signal ap_sig_bdd_105 : BOOLEAN; signal value_reg_294 : STD_LOGIC_VECTOR (31 downto 0); signal iay_1_fu_204_p2 : STD_LOGIC_VECTOR (31 downto 0); signal iay_1_reg_299 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_6_fu_176_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_215_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_reg_304 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC; signal ap_sig_bdd_122 : BOOLEAN; signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC; signal ap_sig_bdd_131 : BOOLEAN; signal b_load_reg_314 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC; signal ap_sig_bdd_139 : BOOLEAN; signal grp_fu_228_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_reg_319 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC; signal ap_sig_bdd_148 : BOOLEAN; signal sum_1_fu_232_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC; signal ap_sig_bdd_157 : BOOLEAN; signal grp_fu_210_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_3_reg_329 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC; signal ap_sig_bdd_166 : BOOLEAN; signal ibx_reg_90 : STD_LOGIC_VECTOR (30 downto 0); signal a_i_reg_101 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_149_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC; signal ap_sig_bdd_183 : BOOLEAN; signal iay_reg_114 : STD_LOGIC_VECTOR (31 downto 0); signal sum_reg_129 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_171_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_fu_223_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_4_fu_241_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC; signal ap_sig_bdd_200 : BOOLEAN; signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC; signal ap_sig_bdd_208 : BOOLEAN; signal tmp_fu_149_p1 : STD_LOGIC_VECTOR (31 downto 0); signal column_fu_180_p4 : STD_LOGIC_VECTOR (30 downto 0); signal grp_fu_215_p0 : STD_LOGIC_VECTOR (30 downto 0); signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC; signal ap_sig_bdd_247 : BOOLEAN; signal tmp_9_fu_219_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_237_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_210_ce : STD_LOGIC; signal grp_fu_215_ce : STD_LOGIC; signal grp_fu_228_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0); component sparse_mm_mul_32s_32s_32_3 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sparse_mm_mul_31ns_32s_32_3 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (30 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin sparse_mm_mul_32s_32s_32_3_U1 : component sparse_mm_mul_32s_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => iay_reg_114, din1 => b_x, ce => grp_fu_210_ce, dout => grp_fu_210_p2); sparse_mm_mul_31ns_32s_32_3_U2 : component sparse_mm_mul_31ns_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 31, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_215_p0, din1 => b_x, ce => grp_fu_215_ce, dout => grp_fu_215_p2); sparse_mm_mul_32s_32s_32_3_U3 : component sparse_mm_mul_32s_32s_32_3 generic map ( ID => 1, NUM_STAGE => 3, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => b_load_reg_314, din1 => value_reg_294, ce => grp_fu_228_ce, dout => grp_fu_228_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- a_i_reg_101 assign process. -- a_i_reg_101_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then a_i_reg_101 <= a_i_1_reg_275; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then a_i_reg_101 <= ap_const_lv32_0; end if; end if; end process; -- iay_reg_114 assign process. -- iay_reg_114_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then iay_reg_114 <= iay_reg_114; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then iay_reg_114 <= iay_1_reg_299; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then iay_reg_114 <= ap_const_lv32_0; end if; end if; end process; -- ibx_reg_90 assign process. -- ibx_reg_90_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (tmp_1_fu_160_p2 = ap_const_lv1_0))) then ibx_reg_90 <= ibx_1_reg_267; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then ibx_reg_90 <= ap_const_lv31_0; end if; end if; end process; -- sum_reg_129 assign process. -- sum_reg_129_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then sum_reg_129 <= sum_1_fu_232_p2; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then sum_reg_129 <= ap_const_lv32_0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then a_i_1_reg_275 <= a_i_1_fu_165_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then b_load_reg_314 <= b_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then column_cast_reg_289(30 downto 0) <= column_cast_fu_190_p1(30 downto 0); value_reg_294 <= a_q0(63 downto 32); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_6_fu_176_p1)))) then iay_1_reg_299 <= iay_1_fu_204_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then ibx_1_reg_267 <= ibx_1_fu_154_p2; ibx_cast_reg_258(30 downto 0) <= ibx_cast_fu_145_p1(30 downto 0); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then tmp_3_reg_329 <= grp_fu_210_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then tmp_7_reg_319 <= grp_fu_228_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then tmp_8_reg_304 <= grp_fu_215_p2; end if; end if; end process; ibx_cast_reg_258(31) <= '0'; column_cast_reg_289(31) <= '0'; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_160_p2, tmp_6_fu_176_p1, tmp_fu_149_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if ((ap_const_lv1_0 = tmp_fu_149_p2)) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_st3_fsm_2; end if; when ap_ST_st3_fsm_2 => if (not((tmp_1_fu_160_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st4_fsm_3; else ap_NS_fsm <= ap_ST_st2_fsm_1; end if; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => if (not((ap_const_lv1_0 = tmp_6_fu_176_p1))) then ap_NS_fsm <= ap_ST_st16_fsm_15; else ap_NS_fsm <= ap_ST_st7_fsm_6; end if; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st3_fsm_2; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX"; end case; end process; a_address0 <= tmp_2_fu_171_p1(22 - 1 downto 0); -- a_ce0 assign process. -- a_ce0_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st5_fsm_4) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4))) then a_ce0 <= ap_const_logic_1; else a_ce0 <= ap_const_logic_0; end if; end process; a_i_1_fu_165_p2 <= std_logic_vector(unsigned(a_i_reg_101) + unsigned(ap_const_lv32_1)); -- ap_done assign process. -- ap_done_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_105 assign process. -- ap_sig_bdd_105_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; -- ap_sig_bdd_122 assign process. -- ap_sig_bdd_122_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_122 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; -- ap_sig_bdd_131 assign process. -- ap_sig_bdd_131_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_131 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; -- ap_sig_bdd_139 assign process. -- ap_sig_bdd_139_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_139 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; -- ap_sig_bdd_148 assign process. -- ap_sig_bdd_148_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13)); end process; -- ap_sig_bdd_157 assign process. -- ap_sig_bdd_157_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_157 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14)); end process; -- ap_sig_bdd_166 assign process. -- ap_sig_bdd_166_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_166 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16)); end process; -- ap_sig_bdd_183 assign process. -- ap_sig_bdd_183_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_183 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17)); end process; -- ap_sig_bdd_200 assign process. -- ap_sig_bdd_200_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_200 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_208 assign process. -- ap_sig_bdd_208_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_208 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; -- ap_sig_bdd_247 assign process. -- ap_sig_bdd_247_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; -- ap_sig_bdd_34 assign process. -- ap_sig_bdd_34_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_78 assign process. -- ap_sig_bdd_78_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_78 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_89 assign process. -- ap_sig_bdd_89_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_cseq_ST_st10_fsm_9 assign process. -- ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_131) begin if (ap_sig_bdd_131) then ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st11_fsm_10 assign process. -- ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_139) begin if (ap_sig_bdd_139) then ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st14_fsm_13 assign process. -- ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_148) begin if (ap_sig_bdd_148) then ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1; else ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st15_fsm_14 assign process. -- ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_157) begin if (ap_sig_bdd_157) then ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1; else ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st17_fsm_16 assign process. -- ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_166) begin if (ap_sig_bdd_166) then ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st18_fsm_17 assign process. -- ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_183) begin if (ap_sig_bdd_183) then ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1; else ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34) begin if (ap_sig_bdd_34) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_78) begin if (ap_sig_bdd_78) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st3_fsm_2 assign process. -- ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_89) begin if (ap_sig_bdd_89) then ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st4_fsm_3 assign process. -- ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_200) begin if (ap_sig_bdd_200) then ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_4 assign process. -- ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_208) begin if (ap_sig_bdd_208) then ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st6_fsm_5 assign process. -- ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_105) begin if (ap_sig_bdd_105) then ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st7_fsm_6 assign process. -- ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_247) begin if (ap_sig_bdd_247) then ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st9_fsm_8 assign process. -- ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_122) begin if (ap_sig_bdd_122) then ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0; end if; end process; b_address0 <= tmp_s_fu_223_p1(11 - 1 downto 0); -- b_ce0 assign process. -- b_ce0_assign_proc : process(ap_sig_cseq_ST_st10_fsm_9) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then b_ce0 <= ap_const_logic_1; else b_ce0 <= ap_const_logic_0; end if; end process; c_address0 <= tmp_4_fu_241_p1(11 - 1 downto 0); -- c_ce0 assign process. -- c_ce0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then c_ce0 <= ap_const_logic_1; else c_ce0 <= ap_const_logic_0; end if; end process; c_d0 <= sum_reg_129; -- c_we0 assign process. -- c_we0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then c_we0 <= ap_const_logic_1; else c_we0 <= ap_const_logic_0; end if; end process; column_cast_fu_190_p1 <= std_logic_vector(resize(unsigned(column_fu_180_p4),32)); column_fu_180_p4 <= a_q0(31 downto 1); grp_fu_210_ce <= ap_const_logic_1; grp_fu_215_ce <= ap_const_logic_1; grp_fu_215_p0 <= column_cast_reg_289(31 - 1 downto 0); grp_fu_228_ce <= ap_const_logic_1; iay_1_fu_204_p2 <= std_logic_vector(signed(iay_reg_114) + signed(ap_const_lv32_1)); ibx_1_fu_154_p2 <= std_logic_vector(unsigned(ibx_reg_90) + unsigned(ap_const_lv31_1)); ibx_cast_fu_145_p1 <= std_logic_vector(resize(unsigned(ibx_reg_90),32)); sum_1_fu_232_p2 <= std_logic_vector(unsigned(tmp_7_reg_319) + unsigned(sum_reg_129)); tmp_1_fu_160_p2 <= "1" when (unsigned(iay_reg_114) < unsigned(a_y)) else "0"; tmp_2_fu_171_p1 <= std_logic_vector(resize(signed(a_i_reg_101),64)); tmp_4_fu_241_p1 <= std_logic_vector(resize(signed(tmp_5_fu_237_p2),64)); tmp_5_fu_237_p2 <= std_logic_vector(unsigned(tmp_3_reg_329) + unsigned(ibx_cast_reg_258)); tmp_6_fu_176_p1 <= a_q0(1 - 1 downto 0); tmp_9_fu_219_p2 <= std_logic_vector(unsigned(tmp_8_reg_304) + unsigned(ibx_cast_reg_258)); tmp_fu_149_p1 <= b_x; tmp_fu_149_p2 <= "1" when (signed(ibx_cast_fu_145_p1) < signed(tmp_fu_149_p1)) else "0"; tmp_s_fu_223_p1 <= std_logic_vector(resize(unsigned(tmp_9_fu_219_p2),64)); end behav;

gpl-3.0

187253e9206afb9071db2fbd5fe49ec2

0.568416

2.883752

false

grwlf/vsim

vhdl_ct/ct00560.vhd

1

25,718

-- NEED RESULT: ARCH00560: Variable declarations - composite dynamic subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00560 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (12) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00560) -- ENT00560_Test_Bench(ARCH00560_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.test_report ; -- architecture ARCH00560 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is variable correct : boolean := true ; -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- variable va_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable va_st_string_1 : st_string := c_st_string_1 ; variable va_st_rec1_1 : st_rec1 := c_st_rec1_1 ; variable va_st_rec2_1 : st_rec2 := c_st_rec2_1 ; variable va_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable va_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable va_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable va_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and va_st_string_1 = c_st_string_1 ; correct := correct and va_st_rec1_1 = c_st_rec1_1 ; correct := correct and va_st_rec2_1 = c_st_rec2_1 ; correct := correct and va_st_rec3_1 = c_st_rec3_1 ; correct := correct and va_st_arr1_1 = c_st_arr1_1 ; correct := correct and va_st_arr2_1 = c_st_arr2_1 ; correct := correct and va_st_arr3_1 = c_st_arr3_1 ; va_st_bit_vector_1 := c_st_bit_vector_2 ; va_st_string_1 := c_st_string_2 ; va_st_rec1_1 := c_st_rec1_2 ; va_st_rec2_1 := c_st_rec2_2 ; va_st_rec3_1 := c_st_rec3_2 ; va_st_arr1_1 := c_st_arr1_2 ; va_st_arr2_1 := c_st_arr2_2 ; va_st_arr3_1 := c_st_arr3_2 ; correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and va_st_string_1 = c_st_string_2 ; correct := correct and va_st_rec1_1 = c_st_rec1_2 ; correct := correct and va_st_rec2_1 = c_st_rec2_2 ; correct := correct and va_st_rec3_1 = c_st_rec3_2 ; correct := correct and va_st_arr1_1 = c_st_arr1_2 ; correct := correct and va_st_arr2_1 = c_st_arr2_2 ; correct := correct and va_st_arr3_1 = c_st_arr3_2 ; test_report ( "ARCH00560" , "Variable declarations - composite dynamic subtypes" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00560 ; -- entity ENT00560_Test_Bench is end ENT00560_Test_Bench ; -- architecture ARCH00560_Test_Bench of ENT00560_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00560 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00560_Test_Bench ;

gpl-3.0

37d75f805176a5be69861b856e5dad18

0.548099

3.167631

false

grwlf/vsim

vhdl_ct/ct00180.vhd

1

43,554

-- NEED RESULT: ARCH00180.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: ARCH00180: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed -- NEED RESULT: P6: Inertial transactions entirely completed failed -- NEED RESULT: P5: Inertial transactions entirely completed failed -- NEED RESULT: P4: Inertial transactions entirely completed failed -- NEED RESULT: P3: Inertial transactions entirely completed failed -- NEED RESULT: P2: Inertial transactions entirely completed failed -- NEED RESULT: P1: Inertial transactions entirely completed failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00180 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- PKG00180 -- PKG00180/BODY -- E00000(ARCH00180) -- ENT00180_Test_Bench(ARCH00180_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00180 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00180 ; -- package body PKG00180 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00180 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00180.all ; architecture ARCH00180 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- begin P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P1" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_r_st_arr1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P2" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_r_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P3" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_arr3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_r_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- P4 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P4" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P4 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions entirely completed", chk_r_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- P5 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P5" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P5 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions entirely completed", chk_r_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- P6 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180.P6" , "Multi inertial transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 100 ns ; -- when 5 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Old transactions were removed on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 6 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "One inertial transaction occurred on signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 7 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00180" , "Inertial semantics check on a signal " & "asg with slice name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_r_st_rec3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P6 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions entirely completed", chk_r_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- -- end ARCH00180 ; -- entity ENT00180_Test_Bench is end ENT00180_Test_Bench ; -- architecture ARCH00180_Test_Bench of ENT00180_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00180 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00180_Test_Bench ;

gpl-3.0

db12cdeb40b858f120285ef0da3aef90

0.4789

3.395759

false

grwlf/vsim

vhdl_ct/ct00551.vhd

1

25,618

-- NEED RESULT: ARCH00551: Constant declarations - composite globally static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00551 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.1 (7) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00551) -- ENT00551_Test_Bench(ARCH00551_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.test_report ; architecture ARCH00551 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is variable correct : boolean := true ; -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- constant co_bit_vector_1 : bit_vector := c_st_bit_vector_1 ; constant co_string_1 : string := c_st_string_1 ; constant co_t_rec1_1 : t_rec1 := c_st_rec1_1 ; constant co_st_rec1_1 : st_rec1 := c_st_rec1_1 ; constant co_t_rec2_1 : t_rec2 := c_st_rec2_1 ; constant co_st_rec2_1 : st_rec2 := c_st_rec2_1 ; constant co_t_rec3_1 : t_rec3 := c_st_rec3_1 ; constant co_st_rec3_1 : st_rec3 := c_st_rec3_1 ; constant co_t_arr1_1 : t_arr1 := c_st_arr1_1 ; constant co_st_arr1_1 : st_arr1 := c_st_arr1_1 ; constant co_t_arr2_1 : t_arr2 := c_st_arr2_1 ; constant co_st_arr2_1 : st_arr2 := c_st_arr2_1 ; constant co_t_arr3_1 : t_arr3 := c_st_arr3_1 ; constant co_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and co_string_1 = c_st_string_1 ; correct := correct and co_t_rec1_1 = c_t_rec1_1 ; correct := correct and co_st_rec1_1 = c_st_rec1_1 ; correct := correct and co_t_rec2_1 = c_t_rec2_1 ; correct := correct and co_st_rec2_1 = c_st_rec2_1 ; correct := correct and co_t_rec3_1 = c_t_rec3_1 ; correct := correct and co_st_rec3_1 = c_st_rec3_1 ; correct := correct and co_t_arr1_1 = c_t_arr1_1 ; correct := correct and co_st_arr1_1 = c_st_arr1_1 ; correct := correct and co_t_arr2_1 = c_t_arr2_1 ; correct := correct and co_st_arr2_1 = c_st_arr2_1 ; correct := correct and co_t_arr3_1 = c_t_arr3_1 ; correct := correct and co_st_arr3_1 = c_st_arr3_1 ; test_report ( "ARCH00551" , "Constant declarations - composite globally static subtypes" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00551 ; -- entity ENT00551_Test_Bench is end ENT00551_Test_Bench ; -- architecture ARCH00551_Test_Bench of ENT00551_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00551 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00551_Test_Bench ;

gpl-3.0

3dd8caec53fa603fb5abbc212d50d60c

0.546686

3.183151

false

grwlf/vsim

vhdl_ct/ct00558.vhd

1

3,218

-- NEED RESULT: ARCH00558: Variable declarations - composite static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00558 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (10) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00558) -- ENT00558_Test_Bench(ARCH00558_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00558 of E00000 is begin process variable correct : boolean := true ; variable va_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable va_st_string_1 : st_string := c_st_string_1 ; variable va_st_rec1_1 : st_rec1 := c_st_rec1_1 ; variable va_st_rec2_1 : st_rec2 := c_st_rec2_1 ; variable va_st_rec3_1 : st_rec3 := c_st_rec3_1 ; variable va_st_arr1_1 : st_arr1 := c_st_arr1_1 ; variable va_st_arr2_1 : st_arr2 := c_st_arr2_1 ; variable va_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and va_st_string_1 = c_st_string_1 ; correct := correct and va_st_rec1_1 = c_st_rec1_1 ; correct := correct and va_st_rec2_1 = c_st_rec2_1 ; correct := correct and va_st_rec3_1 = c_st_rec3_1 ; correct := correct and va_st_arr1_1 = c_st_arr1_1 ; correct := correct and va_st_arr2_1 = c_st_arr2_1 ; correct := correct and va_st_arr3_1 = c_st_arr3_1 ; va_st_bit_vector_1 := c_st_bit_vector_2 ; va_st_string_1 := c_st_string_2 ; va_st_rec1_1 := c_st_rec1_2 ; va_st_rec2_1 := c_st_rec2_2 ; va_st_rec3_1 := c_st_rec3_2 ; va_st_arr1_1 := c_st_arr1_2 ; va_st_arr2_1 := c_st_arr2_2 ; va_st_arr3_1 := c_st_arr3_2 ; correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ; correct := correct and va_st_string_1 = c_st_string_2 ; correct := correct and va_st_rec1_1 = c_st_rec1_2 ; correct := correct and va_st_rec2_1 = c_st_rec2_2 ; correct := correct and va_st_rec3_1 = c_st_rec3_2 ; correct := correct and va_st_arr1_1 = c_st_arr1_2 ; correct := correct and va_st_arr2_1 = c_st_arr2_2 ; correct := correct and va_st_arr3_1 = c_st_arr3_2 ; test_report ( "ARCH00558" , "Variable declarations - composite static subtypes" , correct) ; wait ; end process ; end ARCH00558 ; -- entity ENT00558_Test_Bench is end ENT00558_Test_Bench ; -- architecture ARCH00558_Test_Bench of ENT00558_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00558 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00558_Test_Bench ;

gpl-3.0

857d5805ea6fdc6be3781dc55778dfb0

0.530143

2.909584

false

true

false

MrDoomBringer/DSD-Labs

Lab 6/sevenseg_out.vhd

1

6,255

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY sevenseg_out IS port ( R : IN STD_LOGIC_VECTOR (7 DOWNTO 0); S : IN STD_LOGIC; HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END sevenseg_out; ARCHITECTURE derp OF sevenseg_out IS CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111"; CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111"; CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000"; CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001"; CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100"; CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000"; CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001"; CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010"; CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010"; CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000"; CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000"; CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000"; CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000"; CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011"; CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110"; CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001"; CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110"; CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110"; SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0); BEGIN -- Generate a hex display display_hex : PROCESS (R) ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (7 DOWNTO 4); ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (3 DOWNTO 0); BEGIN CASE high_bit IS WHEN "0000" => HEX1_buff_hex <= hex_zer; WHEN "0001" => HEX1_buff_hex <= hex_one; WHEN "0010" => HEX1_buff_hex <= hex_two; WHEN "0011" => HEX1_buff_hex <= hex_thr; WHEN "0100" => HEX1_buff_hex <= hex_fou; WHEN "0101" => HEX1_buff_hex <= hex_fiv; WHEN "0110" => HEX1_buff_hex <= hex_six; WHEN "0111" => HEX1_buff_hex <= hex_sev; WHEN "1000" => HEX1_buff_hex <= hex_eig; WHEN "1001" => HEX1_buff_hex <= hex_nin; WHEN "1010" => HEX1_buff_hex <= hex_0xa; WHEN "1011" => HEX1_buff_hex <= hex_0xb; WHEN "1100" => HEX1_buff_hex <= hex_0xc; WHEN "1101" => HEX1_buff_hex <= hex_0xd; WHEN "1110" => HEX1_buff_hex <= hex_0xe; WHEN "1111" => HEX1_buff_hex <= hex_0xf; WHEN OTHERS => HEX1_buff_hex <= hex_blk; END CASE; CASE low_bit IS WHEN "0000" => HEX2_buff_hex <= hex_zer; WHEN "0001" => HEX2_buff_hex <= hex_one; WHEN "0010" => HEX2_buff_hex <= hex_two; WHEN "0011" => HEX2_buff_hex <= hex_thr; WHEN "0100" => HEX2_buff_hex <= hex_fou; WHEN "0101" => HEX2_buff_hex <= hex_fiv; WHEN "0110" => HEX2_buff_hex <= hex_six; WHEN "0111" => HEX2_buff_hex <= hex_sev; WHEN "1000" => HEX2_buff_hex <= hex_eig; WHEN "1001" => HEX2_buff_hex <= hex_nin; WHEN "1010" => HEX2_buff_hex <= hex_0xa; WHEN "1011" => HEX2_buff_hex <= hex_0xb; WHEN "1100" => HEX2_buff_hex <= hex_0xc; WHEN "1101" => HEX2_buff_hex <= hex_0xd; WHEN "1110" => HEX2_buff_hex <= hex_0xe; WHEN "1111" => HEX2_buff_hex <= hex_0xf; WHEN OTHERS => HEX2_buff_hex <= hex_blk; END CASE; END PROCESS display_hex; -- Generate a decimal display display_dec: PROCESS (R) ALIAS sign_bit : STD_LOGIC IS R (7); VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE r_buff : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN -- Select value to work off of IF (sign_bit='1') THEN HEX0_buff_dec <= hex_neg; r_buff := (NOT(R) + "00000001"); ELSIF (sign_bit='0') THEN HEX0_buff_dec <= hex_blk; r_buff := R; ELSE HEX0_buff_dec <= hex_blk; r_buff := "00000000"; END IF; -- Display higher digit IF (r_buff >= "00001010" AND r_buff < "00010100") THEN -- Within 10-19 HEX1_buff_dec <= hex_one; r_lower := r_buff - "00001010"; ELSIF (r_buff >= "00010100" AND r_buff < "00011110") THEN -- Within 20-29 HEX1_buff_dec <= hex_two; r_lower := r_buff - "00010100"; ELSIF (r_buff >= "00011110" AND r_buff < "00101000") THEN -- Within 30-39 HEX1_buff_dec <= hex_thr; r_lower := r_buff - "00011110"; ELSIF (r_buff >= "00101000" AND r_buff < "00110010") THEN -- Within 40-49 HEX1_buff_dec <= hex_fou; r_lower := r_buff - "00101000"; ELSIF (r_buff >= "00110010" AND r_buff < "00111100") THEN -- Within 50-59 HEX1_buff_dec <= hex_fiv; r_lower := r_buff - "00110010"; ELSIF (r_buff >= "00111100" AND r_buff < "01000110") THEN -- Within 60-69 HEX1_buff_dec <= hex_six; r_lower := r_buff - "00111100"; ELSE -- We can't have any higher values from our ALU, everything else must be zero. HEX1_buff_dec <= hex_zer; r_lower := r_buff; END IF; -- Display lower digit CASE r_lower IS WHEN "00000000" => HEX2_buff_dec <= hex_zer; WHEN "00000001" => HEX2_buff_dec <= hex_one; WHEN "00000010" => HEX2_buff_dec <= hex_two; WHEN "00000011" => HEX2_buff_dec <= hex_thr; WHEN "00000100" => HEX2_buff_dec <= hex_fou; WHEN "00000101" => HEX2_buff_dec <= hex_fiv; WHEN "00000110" => HEX2_buff_dec <= hex_six; WHEN "00000111" => HEX2_buff_dec <= hex_sev; WHEN "00001000" => HEX2_buff_dec <= hex_eig; WHEN "00001001" => HEX2_buff_dec <= hex_nin; WHEN OTHERS => HEX2_buff_dec <= hex_zer; END CASE; END PROCESS display_dec; -- Select display type for output select_display : PROCESS (S, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec) BEGIN IF (s = '0') THEN HEX0 <= hex_blk; HEX1 <= HEX1_buff_hex; HEX2 <= HEX2_buff_hex; ELSIF (s = '1') THEN HEX0 <= HEX0_buff_dec; HEX1 <= HEX1_buff_dec; HEX2 <= HEX2_buff_dec; ELSE HEX0 <= hex_blk; HEX1 <= hex_blk; HEX2 <= hex_blk; END IF; END PROCESS select_display; END derp;

mit

5f3ba47810500edcc0ba800f5131e27e

0.622542

2.645939

false

TWW12/lzw

ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_sim_netlist.vhdl

2

78,687

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Mar 31 08:57:14 2017 -- Host : Shaun running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_sim_netlist.vhdl -- Design : bram_4096 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_4096_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_wrapper_init is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_02 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_03 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 4, READ_WIDTH_B => 4, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 4, WRITE_WIDTH_B => 4 ) port map ( ADDRARDADDR(13 downto 2) => addra(11 downto 0), ADDRARDADDR(1 downto 0) => B"00", ADDRBWRADDR(13 downto 0) => B"00000000000000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 4) => B"000000000000", DIADI(3 downto 0) => dina(3 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4), DOADO(3 downto 0) => douta(3 downto 0), DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ena, ENBWREN => '0', REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0101010101010101010101010101010100000000000000000000000000000000", INIT_01 => X"0303030303030303030303030303030302020202020202020202020202020202", INIT_02 => X"0505050505050505050505050505050504040404040404040404040404040404", INIT_03 => X"0707070707070707070707070707070706060606060606060606060606060606", INIT_04 => X"0909090909090909090909090909090908080808080808080808080808080808", INIT_05 => X"0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", INIT_06 => X"0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C", INIT_07 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 1) => B"000", DIPADIP(0) => dina(8), DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => douta(7 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => douta(8), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 7) => B"0000000000000000000000000", DIADI(6 downto 0) => dina(6 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6 downto 0) => douta(6 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_4096_blk_mem_gen_prim_width; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_4096_blk_mem_gen_prim_wrapper_init port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), douta(3 downto 0) => douta(3 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized1\ is port ( douta : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(6 downto 0), douta(6 downto 0) => douta(6 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_4096_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_4096_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bram_4096_blk_mem_gen_prim_width port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), douta(3 downto 0) => douta(3 downto 0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(12 downto 4), douta(8 downto 0) => douta(12 downto 4), ena => ena, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized1\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(19 downto 13), douta(6 downto 0) => douta(19 downto 13), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_4096_blk_mem_gen_top; architecture STRUCTURE of bram_4096_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_4096_blk_mem_gen_generic_cstr port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_4096_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_4096_blk_mem_gen_top port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_4096_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_4096_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_4096_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_4096_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_4096_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_4096_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_4096_blk_mem_gen_v8_3_5_synth port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_4096 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_4096 : entity is "bram_4096,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_4096 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_4096; architecture STRUCTURE of bram_4096 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_4096_blk_mem_gen_v8_3_5 port map ( addra(11 downto 0) => addra(11 downto 0), addrb(11 downto 0) => B"000000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;

unlicense

7f0367c77c32b2cad73297582534f371

0.721898

4.060636

false

grwlf/vsim

vhdl_ct/ct00309.vhd

1

24,615

-- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for generically sized types passed -- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for types passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00309 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.2 (1) -- 7.2.2 (2) -- 7.2.2 (6) -- 7.2.2 (9) -- 7.2.2 (10) -- 7.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00309(ARCH00309) -- GENERIC_STANDARD_TYPES(ARCH00309_1) -- ENT00309_Test_Bench(ARCH00309_Test_Bench) -- -- REVISION HISTORY: -- -- 21-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00309 is generic ( i_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; i_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; i_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; i_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; i_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; i_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; i_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; i_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; i_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; i_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; i_st_string_1 : st_string := c_st_string_1 ; i_st_string_2 : st_string := c_st_string_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00309 ; architecture ARCH00309 of ENT00309 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; variable v_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable v_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; variable v_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; variable v_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; variable v_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; variable v_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; variable v_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; variable v_st_string_1 : st_string := c_st_string_1 ; variable v_st_string_2 : st_string := c_st_string_2 ; constant c2_st_bit_vector_1 : boolean := i_st_bit_vector_1 < i_st_bit_vector_2 and i_st_bit_vector_1 <= i_st_bit_vector_2 and i_st_bit_vector_2 <= c_st_bit_vector_2 and i_st_bit_vector_2 >= i_st_bit_vector_1 and i_st_bit_vector_1 >= c_st_bit_vector_1 and i_st_bit_vector_2 > i_st_bit_vector_1 and i_st_bit_vector_1 = c_st_bit_vector_1 and i_st_bit_vector_1 /= i_st_bit_vector_2 and not (i_st_bit_vector_1 = i_st_bit_vector_2) ; constant c2_st_boolean_vector_1 : boolean := i_st_boolean_vector_1 < i_st_boolean_vector_2 and i_st_boolean_vector_1 <= i_st_boolean_vector_2 and i_st_boolean_vector_2 <= c_st_boolean_vector_2 and i_st_boolean_vector_2 >= i_st_boolean_vector_1 and i_st_boolean_vector_1 >= c_st_boolean_vector_1 and i_st_boolean_vector_2 > i_st_boolean_vector_1 and i_st_boolean_vector_1 = c_st_boolean_vector_1 and i_st_boolean_vector_1 /= i_st_boolean_vector_2 and not (i_st_boolean_vector_1 = i_st_boolean_vector_2) ; constant c2_st_enum1_vector_1 : boolean := i_st_enum1_vector_1 < i_st_enum1_vector_2 and i_st_enum1_vector_1 <= i_st_enum1_vector_2 and i_st_enum1_vector_2 <= c_st_enum1_vector_2 and i_st_enum1_vector_2 >= i_st_enum1_vector_1 and i_st_enum1_vector_1 >= c_st_enum1_vector_1 and i_st_enum1_vector_2 > i_st_enum1_vector_1 and i_st_enum1_vector_1 = c_st_enum1_vector_1 and i_st_enum1_vector_1 /= i_st_enum1_vector_2 and not (i_st_enum1_vector_1 = i_st_enum1_vector_2) ; constant c2_st_integer_vector_1 : boolean := i_st_integer_vector_1 < i_st_integer_vector_2 and i_st_integer_vector_1 <= i_st_integer_vector_2 and i_st_integer_vector_2 <= c_st_integer_vector_2 and i_st_integer_vector_2 >= i_st_integer_vector_1 and i_st_integer_vector_1 >= c_st_integer_vector_1 and i_st_integer_vector_2 > i_st_integer_vector_1 and i_st_integer_vector_1 = c_st_integer_vector_1 and i_st_integer_vector_1 /= i_st_integer_vector_2 and not (i_st_integer_vector_1 = i_st_integer_vector_2) ; constant c2_st_severity_level_vector_1 : boolean := i_st_severity_level_vector_1 < i_st_severity_level_vector_2 and i_st_severity_level_vector_1 <= i_st_severity_level_vector_2 and i_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and i_st_severity_level_vector_2 >= i_st_severity_level_vector_1 and i_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and i_st_severity_level_vector_2 > i_st_severity_level_vector_1 and i_st_severity_level_vector_1 = c_st_severity_level_vector_1 and i_st_severity_level_vector_1 /= i_st_severity_level_vector_2 and not (i_st_severity_level_vector_1 = i_st_severity_level_vector_2) ; constant c2_st_string_1 : boolean := i_st_string_1 < i_st_string_2 and i_st_string_1 <= i_st_string_2 and i_st_string_2 <= c_st_string_2 and i_st_string_2 >= i_st_string_1 and i_st_string_1 >= c_st_string_1 and i_st_string_2 > i_st_string_1 and i_st_string_1 = c_st_string_1 and i_st_string_1 /= i_st_string_2 and not (i_st_string_1 = i_st_string_2) ; begin gen_correct := gen_correct and c2_st_bit_vector_1 = true ; gen_correct := gen_correct and c2_st_boolean_vector_1 = true ; gen_correct := gen_correct and c2_st_enum1_vector_1 = true ; gen_correct := gen_correct and c2_st_integer_vector_1 = true ; gen_correct := gen_correct and c2_st_severity_level_vector_1 = true ; gen_correct := gen_correct and c2_st_string_1 = true ; dyn_correct := dyn_correct and v_st_bit_vector_1 < v_st_bit_vector_2 and v_st_bit_vector_1 <= v_st_bit_vector_2 and v_st_bit_vector_2 <= c_st_bit_vector_2 and v_st_bit_vector_2 >= v_st_bit_vector_1 and v_st_bit_vector_1 >= c_st_bit_vector_1 and v_st_bit_vector_2 > v_st_bit_vector_1 and v_st_bit_vector_1 = c_st_bit_vector_1 and v_st_bit_vector_1 /= v_st_bit_vector_2 and not (v_st_bit_vector_1 = v_st_bit_vector_2) ; dyn_correct := dyn_correct and v_st_boolean_vector_1 < v_st_boolean_vector_2 and v_st_boolean_vector_1 <= v_st_boolean_vector_2 and v_st_boolean_vector_2 <= c_st_boolean_vector_2 and v_st_boolean_vector_2 >= v_st_boolean_vector_1 and v_st_boolean_vector_1 >= c_st_boolean_vector_1 and v_st_boolean_vector_2 > v_st_boolean_vector_1 and v_st_boolean_vector_1 = c_st_boolean_vector_1 and v_st_boolean_vector_1 /= v_st_boolean_vector_2 and not (v_st_boolean_vector_1 = v_st_boolean_vector_2) ; dyn_correct := dyn_correct and v_st_enum1_vector_1 < v_st_enum1_vector_2 and v_st_enum1_vector_1 <= v_st_enum1_vector_2 and v_st_enum1_vector_2 <= c_st_enum1_vector_2 and v_st_enum1_vector_2 >= v_st_enum1_vector_1 and v_st_enum1_vector_1 >= c_st_enum1_vector_1 and v_st_enum1_vector_2 > v_st_enum1_vector_1 and v_st_enum1_vector_1 = c_st_enum1_vector_1 and v_st_enum1_vector_1 /= v_st_enum1_vector_2 and not (v_st_enum1_vector_1 = v_st_enum1_vector_2) ; dyn_correct := dyn_correct and v_st_integer_vector_1 < v_st_integer_vector_2 and v_st_integer_vector_1 <= v_st_integer_vector_2 and v_st_integer_vector_2 <= c_st_integer_vector_2 and v_st_integer_vector_2 >= v_st_integer_vector_1 and v_st_integer_vector_1 >= c_st_integer_vector_1 and v_st_integer_vector_2 > v_st_integer_vector_1 and v_st_integer_vector_1 = c_st_integer_vector_1 and v_st_integer_vector_1 /= v_st_integer_vector_2 and not (v_st_integer_vector_1 = v_st_integer_vector_2) ; dyn_correct := dyn_correct and v_st_severity_level_vector_1 < v_st_severity_level_vector_2 and v_st_severity_level_vector_1 <= v_st_severity_level_vector_2 and v_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and v_st_severity_level_vector_2 >= v_st_severity_level_vector_1 and v_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and v_st_severity_level_vector_2 > v_st_severity_level_vector_1 and v_st_severity_level_vector_1 = c_st_severity_level_vector_1 and v_st_severity_level_vector_1 /= v_st_severity_level_vector_2 and not (v_st_severity_level_vector_1 = v_st_severity_level_vector_2) ; dyn_correct := dyn_correct and v_st_string_1 < v_st_string_2 and v_st_string_1 <= v_st_string_2 and v_st_string_2 <= c_st_string_2 and v_st_string_2 >= v_st_string_1 and v_st_string_1 >= c_st_string_1 and v_st_string_2 > v_st_string_1 and v_st_string_1 = c_st_string_1 and v_st_string_1 /= v_st_string_2 and not (v_st_string_1 = v_st_string_2) ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait; end process ; end ARCH00309 ; architecture ARCH00309_1 of GENERIC_STANDARD_TYPES is begin B : block generic ( i_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; i_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; i_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; i_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; i_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; i_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; i_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; i_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; i_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; i_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; i_st_string_1 : st_string := c_st_string_1 ; i_st_string_2 : st_string := c_st_string_2 ) ; begin process variable bool : boolean := true ; variable gen_correct, dyn_correct : boolean := true ; variable v_st_bit_vector_1 : st_bit_vector := c_st_bit_vector_1 ; variable v_st_bit_vector_2 : st_bit_vector := c_st_bit_vector_2 ; variable v_st_boolean_vector_1 : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_boolean_vector_2 : st_boolean_vector := c_st_boolean_vector_2 ; variable v_st_enum1_vector_1 : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_enum1_vector_2 : st_enum1_vector := c_st_enum1_vector_2 ; variable v_st_integer_vector_1 : st_integer_vector := c_st_integer_vector_1 ; variable v_st_integer_vector_2 : st_integer_vector := c_st_integer_vector_2 ; variable v_st_severity_level_vector_1 : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_severity_level_vector_2 : st_severity_level_vector := c_st_severity_level_vector_2 ; variable v_st_string_1 : st_string := c_st_string_1 ; variable v_st_string_2 : st_string := c_st_string_2 ; constant c2_st_bit_vector_1 : boolean := i_st_bit_vector_1 < i_st_bit_vector_2 and i_st_bit_vector_1 <= i_st_bit_vector_2 and i_st_bit_vector_2 <= c_st_bit_vector_2 and i_st_bit_vector_2 >= i_st_bit_vector_1 and i_st_bit_vector_1 >= c_st_bit_vector_1 and i_st_bit_vector_2 > i_st_bit_vector_1 and i_st_bit_vector_1 = c_st_bit_vector_1 and i_st_bit_vector_1 /= i_st_bit_vector_2 and not (i_st_bit_vector_1 = i_st_bit_vector_2) ; constant c2_st_boolean_vector_1 : boolean := i_st_boolean_vector_1 < i_st_boolean_vector_2 and i_st_boolean_vector_1 <= i_st_boolean_vector_2 and i_st_boolean_vector_2 <= c_st_boolean_vector_2 and i_st_boolean_vector_2 >= i_st_boolean_vector_1 and i_st_boolean_vector_1 >= c_st_boolean_vector_1 and i_st_boolean_vector_2 > i_st_boolean_vector_1 and i_st_boolean_vector_1 = c_st_boolean_vector_1 and i_st_boolean_vector_1 /= i_st_boolean_vector_2 and not (i_st_boolean_vector_1 = i_st_boolean_vector_2) ; constant c2_st_enum1_vector_1 : boolean := i_st_enum1_vector_1 < i_st_enum1_vector_2 and i_st_enum1_vector_1 <= i_st_enum1_vector_2 and i_st_enum1_vector_2 <= c_st_enum1_vector_2 and i_st_enum1_vector_2 >= i_st_enum1_vector_1 and i_st_enum1_vector_1 >= c_st_enum1_vector_1 and i_st_enum1_vector_2 > i_st_enum1_vector_1 and i_st_enum1_vector_1 = c_st_enum1_vector_1 and i_st_enum1_vector_1 /= i_st_enum1_vector_2 and not (i_st_enum1_vector_1 = i_st_enum1_vector_2) ; constant c2_st_integer_vector_1 : boolean := i_st_integer_vector_1 < i_st_integer_vector_2 and i_st_integer_vector_1 <= i_st_integer_vector_2 and i_st_integer_vector_2 <= c_st_integer_vector_2 and i_st_integer_vector_2 >= i_st_integer_vector_1 and i_st_integer_vector_1 >= c_st_integer_vector_1 and i_st_integer_vector_2 > i_st_integer_vector_1 and i_st_integer_vector_1 = c_st_integer_vector_1 and i_st_integer_vector_1 /= i_st_integer_vector_2 and not (i_st_integer_vector_1 = i_st_integer_vector_2) ; constant c2_st_severity_level_vector_1 : boolean := i_st_severity_level_vector_1 < i_st_severity_level_vector_2 and i_st_severity_level_vector_1 <= i_st_severity_level_vector_2 and i_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and i_st_severity_level_vector_2 >= i_st_severity_level_vector_1 and i_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and i_st_severity_level_vector_2 > i_st_severity_level_vector_1 and i_st_severity_level_vector_1 = c_st_severity_level_vector_1 and i_st_severity_level_vector_1 /= i_st_severity_level_vector_2 and not (i_st_severity_level_vector_1 = i_st_severity_level_vector_2) ; constant c2_st_string_1 : boolean := i_st_string_1 < i_st_string_2 and i_st_string_1 <= i_st_string_2 and i_st_string_2 <= c_st_string_2 and i_st_string_2 >= i_st_string_1 and i_st_string_1 >= c_st_string_1 and i_st_string_2 > i_st_string_1 and i_st_string_1 = c_st_string_1 and i_st_string_1 /= i_st_string_2 and not (i_st_string_1 = i_st_string_2) ; begin dyn_correct := dyn_correct and v_st_bit_vector_1 < v_st_bit_vector_2 and v_st_bit_vector_1 <= v_st_bit_vector_2 and v_st_bit_vector_2 <= c_st_bit_vector_2 and v_st_bit_vector_2 >= v_st_bit_vector_1 and v_st_bit_vector_1 >= c_st_bit_vector_1 and v_st_bit_vector_2 > v_st_bit_vector_1 and v_st_bit_vector_1 = c_st_bit_vector_1 and v_st_bit_vector_1 /= v_st_bit_vector_2 and not (v_st_bit_vector_1 = v_st_bit_vector_2) ; dyn_correct := dyn_correct and v_st_boolean_vector_1 < v_st_boolean_vector_2 and v_st_boolean_vector_1 <= v_st_boolean_vector_2 and v_st_boolean_vector_2 <= c_st_boolean_vector_2 and v_st_boolean_vector_2 >= v_st_boolean_vector_1 and v_st_boolean_vector_1 >= c_st_boolean_vector_1 and v_st_boolean_vector_2 > v_st_boolean_vector_1 and v_st_boolean_vector_1 = c_st_boolean_vector_1 and v_st_boolean_vector_1 /= v_st_boolean_vector_2 and not (v_st_boolean_vector_1 = v_st_boolean_vector_2) ; dyn_correct := dyn_correct and v_st_enum1_vector_1 < v_st_enum1_vector_2 and v_st_enum1_vector_1 <= v_st_enum1_vector_2 and v_st_enum1_vector_2 <= c_st_enum1_vector_2 and v_st_enum1_vector_2 >= v_st_enum1_vector_1 and v_st_enum1_vector_1 >= c_st_enum1_vector_1 and v_st_enum1_vector_2 > v_st_enum1_vector_1 and v_st_enum1_vector_1 = c_st_enum1_vector_1 and v_st_enum1_vector_1 /= v_st_enum1_vector_2 and not (v_st_enum1_vector_1 = v_st_enum1_vector_2) ; dyn_correct := dyn_correct and v_st_integer_vector_1 < v_st_integer_vector_2 and v_st_integer_vector_1 <= v_st_integer_vector_2 and v_st_integer_vector_2 <= c_st_integer_vector_2 and v_st_integer_vector_2 >= v_st_integer_vector_1 and v_st_integer_vector_1 >= c_st_integer_vector_1 and v_st_integer_vector_2 > v_st_integer_vector_1 and v_st_integer_vector_1 = c_st_integer_vector_1 and v_st_integer_vector_1 /= v_st_integer_vector_2 and not (v_st_integer_vector_1 = v_st_integer_vector_2) ; dyn_correct := dyn_correct and v_st_severity_level_vector_1 < v_st_severity_level_vector_2 and v_st_severity_level_vector_1 <= v_st_severity_level_vector_2 and v_st_severity_level_vector_2 <= c_st_severity_level_vector_2 and v_st_severity_level_vector_2 >= v_st_severity_level_vector_1 and v_st_severity_level_vector_1 >= c_st_severity_level_vector_1 and v_st_severity_level_vector_2 > v_st_severity_level_vector_1 and v_st_severity_level_vector_1 = c_st_severity_level_vector_1 and v_st_severity_level_vector_1 /= v_st_severity_level_vector_2 and not (v_st_severity_level_vector_1 = v_st_severity_level_vector_2) ; dyn_correct := dyn_correct and v_st_string_1 < v_st_string_2 and v_st_string_1 <= v_st_string_2 and v_st_string_2 <= c_st_string_2 and v_st_string_2 >= v_st_string_1 and v_st_string_1 >= c_st_string_1 and v_st_string_2 > v_st_string_1 and v_st_string_1 = c_st_string_1 and v_st_string_1 /= v_st_string_2 and not (v_st_string_1 = v_st_string_2) ; if gen_correct and dyn_correct then work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , true ) ; else work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , false ) ; end if ; wait; end process ; end block ; end ARCH00309_1 ; use WORK.STANDARD_TYPES.all ; entity ENT00309_Test_Bench is end ENT00309_Test_Bench ; architecture ARCH00309_Test_Bench of ENT00309_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT end component ; component UUT_1 port ( locally_static_correct, globally_static_correct, dynamic_correct : out boolean ) ; end component ; for CIS2 : UUT_1 use entity WORK.ENT00309 ( ARCH00309 ) ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00309_1 ) ; begin CIS2 : UUT_1 port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; CIS1 : UUT ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for types" , true ) ; end if ; end process ; end block L1 ; end ARCH00309_Test_Bench ;

gpl-3.0

18edeae7454528277a0040e720f0b3fa

0.520455

3.298271

false

progranism/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_fwft_ext_as.vhd

9

12,637

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RvP9zZHkeFP18wLlGgDfVe/DTwIyMP7dhvzgCxp5m3YYL/LPCO9ICc+LBKqhQGhkjW48xpBAGwp3 rBBSE8qK6w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Qh1YkIKhLAJw+T0XBKcVE5CFy7U9clrK+8m4T/x0yjOoagdJeeO9PlbMa8zDeYYoZZutG5tu4t0N sS2pvvQBM2LCvmWTcVG3LWECd1SoSHNd1Q6UbLR4rRzrlUIDN4/JUR9PWghJqqumcUUJxnx5knEi K7afdfP3GWpa+Mc54+8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HhfJKJ7YjkLmM42nTlzlQdDAF0pHVZnxLAjs72tXPKfyr7K5syerWW1IxhILiZNM2A0cNOUuK1B8 3pAH/L4JIt1TVyRIV84DJ8CQly1B9HRzFyS98BKzUfjErddgSfzRoWts821YG5qRykFYzVy0JSNW Ragz33rrmmL7qwMoZDWEs40RddcGX9de4kYYJLuItLwkKCeuM+I1G4CDXKEueQ5u6LQ93N2lQnas nPqBrP8n3BEnbThXBdK1yg3hcWqeBMMV3uoyqi+DrjDYmFIVQeHVKMb7fDMmbeiNu+e1+hNugM7Q zuV0EDd3VBu5V4gC82AsbfxPzRb2dPjR2bGkJA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block r+ZA+Oj7YdWnX06D5ZqZqXmUolmi4IW3cJCjO5tbt4FUt2NRQKFRaPVa/OzCRO98jZcUAZnOrsQs Rep+1VM+AH7vO0AlpTwL2YQWhQIRDtPP4l7hvmAW2QqsKSPWDbymkELktbLs6z2QWa6KZT127iXh ieyHXY4cnV7w42J65Do= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tEVWrDxJT9dKo2YC8zO/ut+oDpg3zkEfgzRECtcSkT6P2lC2McwywkyNOqCk/pmUPQ4bCYcOEOvI jUK+HW4ZZSod7UJE4eE4llpWX07n8fHKwMRVLxvYuhUZ9T0douxC3Lt0fXzC85NJTyJkGimu9KjD 6StBQXytAUuaDDuiaVXVLzHavnShPhHlIbufuZ5VdmuStq9zhYgYirOxIgWll7ywfvt6pWGt6w8p vRlZPnsBCK53+Du8/VX674tC+XGMKo3ahf5CvdS1v1bXUIITFznP1EPny1sPqbe8Z3AmcS4i9zBH 4q/viijyABREqAn303FRoDoAgPOHPMNMgH0nSQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7616) `protect data_block 2jcCW+L/DvZCppgVQq4J4wutN6bK0k6sf58j6Lv8ThwnWKdPBHykU8TGeWX/oWZAwjvz3s87ex1k bw4N3UjDvtfIJZd3xIN1FYC/uWK14Wpia0QJcWqRZp1JtQZsa4gRlgj9wa8mgg/zRb5m72JiU94x SSWVYvuYNxDqJVEWaqcczadPYste5BXE/2QpAyKn/7IzlZCuPa6dIxOCZwq6xAkjZsci4VLJGbmQ oAG3dFsy3DMeFso3O6D9TqLo2YB84+Qjvrfvl8dY/hA6Q30pIvfG7n2NjRkSwX/AEGGdT9QqcfXS VXXZ6EZP1kB95H3HfU8txXxsOK6SqmLOX5F+ZpfXbUpk2XIg0aTDmFTCh1oZpPh7v/HzkFCkRbua HRIhUA2WbVMAQdMtZskmOhC9bwrAZygUHitK5aF+AVwh+dj+eMHDsaNX0UdJ5YE/Vi+dABiLQTLZ UD+DqppmBcCeVc2PWKX3c3T4uj69tXUUi2+S1ry/SZ3QYnErV0m4kPJ7wDOeYRowi5sR+TmHs5WX N9fl/U525IQ1SKefJcGzZY20lKIw22u2U0Q78Bh2nA+rSC2389mIqlr9+V7fRoD5KtIudes+2dpU oB6ISciLiDR+4tDIYvGIKglveO7yTdPvrsIAZLyXeptSD9bRqLeGK/Jdi/Lxs3GVDNkwKFpnHWUH zMvXGQhn6Mn+7dsWlEiI+JWhx8Cx84OPJMPd7aKDVQ4lWr5pJuSikoGDWci4WsOak22ItiaiGVxd IdQoQDDCcTZdw4nYLNuF2Pi5cdCO44aZOwkYc6dRx7Oiovr9nE2B2Ez1EiAU+2g4kqBhJadvq9Od AKtQAmUgRhnmSTdE4mI59hlb5fqw176y/Wf5Eq29RIICCo78oVF78cg77As4ruHyM0HECgatqr/Q jXEK07Rf7MBxCnIn8O/vBoPF5LzpWdNnY3K+K3pVCqLAK/yHI95wk5PehM/1U8YsMwEEvOydgOsZ Ewg2vULvLOOD6pRLRBnv/YyqUrUt6r/W+uKJU58l49TwVuca+C7gnQaMm/f5+zAyb1Dq6qfjIUAA F/1ew6rhvSLCfnybzH8ogDNVGAA+n5EAXM3TW+ZXLMIorvYolagYtQTKoXuv566378DJ9rd7YtQ1 k0f1uLPYdsmwWnHf1PUXgtqbazg/7CyQ5Z1TH9/LbsavboKJhBcmZg/z/iKqKqxDqY/YlnewnpGi grIrQtSfjd3UCA2zYh+sX7j3yqpJBjYTczbtikToJfAvrGvz2fUbOIELJuzu7BgLbJP0JXQpDPnL TpJLn3w51SoMhavMlriwyzUw1vKOJHxR19aXRrw9xcXxsSNOV5E3RVDhJXo1qAr7as41lo1WpTun Xl+XLvvbDVm8EjORRkGR/yLUXd/qyF+SqRmFqi41HnZeD/13h776RLJoLlbq3a3hXVRmQLqxEfCc mdrPpVupdmJePPle+WgJwl07+k83Le1ptMGIvqhzt2Jr291KhwmjnN52iMHHdThJusX+spyLOnfI UftQMGUdYRz8kUFbA8ySA+qEwJ04R+L2Obz16ypAbk8tvSd+FBDjuIlUBFB03d5dzbt5ftvRNDuF NEbeEq4Zs/V3ThL6RjQtGMs9GSs1FTMjIpwgKj9V3BsjxuDzxh4NSjSK8OMFTOtCUp1SrdPbdfmP kQKucCOCcQ6sImTtSwbxxCk1LM24RjfOelWq6P8qL91x1opsNG3iJDPg1UZLTftDoiQgLwubRwiA KGNv3931ePmLSnhBsAidFuvpYBWN6/jIi+3UfIP/fhOZcur6hTAdyC7x46GWZc3P8T2ovd7hW1Zq cfO4/LBrasj5CEInfzB8xkU09aO4/NzmboRi1ni5Ns93GtFKfB4TpyjoAE1beFsMtdHr/Yy7YoZF Rha3YZR+Sw5mg9+k8u8amFOge3Nh9obV5RsiR64zRNAAB8qG0eBwg7m4eC/oy+eSBwGA3hwF+Jpm SOnBRf51kNUTiiccT82rgBX/d//HheB2mwwjjXa/q2YIghTMrileyFWLLmbuWi6fvixYFgwkUw3F XpUj0x0VS84PD/ycCc1TK1o9sglLJDGuQdUdyjoF68rrEkszaVkzgQBGyqS1iKmLwW+l/HM8gn5M C8AqrR1MBk3Grzu7z37esWFCexgj04ZsOJmQSVqij/lTn7akIV9xWhOswVYS9IpUb1u/VaBRUn2v XxgwND1YWGDddlVCT9yeyaQkl26Xal2lQ0lEpt7ap+ujvW6d37OXNKYfYFvXQjtv2YCsR7qdqJE0 fydRm8Yx0DeV1ycivwsHOLDO56D04jUsP42nEIwy1KzdIIGw4Sp9S35hPTdpJg9tLinjJrXXh6lz Mv2NW4bnVV4s68aBJSczcn0o/u6QjRAYaKyz16Kbemy2Gheb9IblySfQGlq1wQaOlK9v7nPc+p2I bDTKS8uwpxvHbkPOto6hjsol5gnEtwzCQEnxq3tkxQDLDmtjxLr4dk4soliG8o8AxmOn2pjRViKf vwLax4S+dZQeWurHBAhCQDlHvVe/oH/CoJreik0CdcCFdQ0sWMAIUUqT9pPCz/dRcFAjpWkcS1cl 3tO+I+gz9wZxPUkBbitQQhhcYbOzAFn5slMyMK6r7SGP9fPuod3hOhvaiUQpUne8PXCsjo+IidDe VuKHXnA2g5neyNcytXcF+pZQdODJUk3QvmqgbEVR85W8SA4kKl30f6m3vbWEqgpN9k7KdoLgYNdr oKnuX4mWnNLcvjY1/9fN0i+f9o1rpfEWH9nGBcvgtDM46uIFTamhSw6QSDBLDVvfJ4DyHa+Qv5pe 7Rhb6tRe/4hdjLvOL6HYD2+EvZMlqs+EY3MDW0tuPl786imA3c32yNp6C4OUxE6Oum+bcot2553s BK6HiyHlk1WRjVCSRH52XIrbBwdbuQzPbiwTWZkWx3U0wpbN4y1TXghxUwu+gELQRua3xNzUwb2T eyvljjTTqyLP1uffHYRhK+Wi7mZjkVJcOFSSMwYNPMiNbrxCUZLNWROEkVdG/3A+TcnyyghufgGa 8qgtwsG/0NbYLTqKp8u1jiTBxPdNdZYu0WSsbhoT9XAeslNvaK69E5Ahgy6UabTX74aNTAuftvnx KsxftpvyCAb61pb4Quueeu3AovJx7QJaR2HG1J7ZP1JkSXRWtkWIiLJ1K1hUEdccUAbegz8qBNrb FNb31mLqvLWu3M8faMXljV3G/c5B7/HrsNNyP6HC2wleINwIPKiCpw965AZU+6Mb2SRVmp8b2KKe gc+RaYvqvMXb8Vdd5b8yb7F7JrgwjRWTuddPc+B+p+Xce0Gmw0s/6Dp32JySDyuoqa/1N5gjgX+6 sm/RW5DPmGxwhzvlKLr3a4k3ka+0BFjh/Sl+KY290r8gvZWVjN743Iypp1JcySAY+DAPsuke/XS1 kMm//TrOo/NqXBhSOxY/JO+9ZAyY8kodCY9gR/kby2Fmbj8LNiPsEm68xpSZ3VePr1CGn9hv5HBp 66ZlQgvSqC9mZGtFcy3/Pm7kvpWy9lwEEzhdgigtxJbz9CxoCJDF16QEbM3DrqUJ8d274ORk4BUn lbpjT8ppFbKFe98+JPRDBWubf5nEfYE92bx+HRL6tV7BVPspK0G3ui75IrzlAks2qghzp4YDbmbR O4mjW5hoOrmFccE+ER80bm7+EOGsWFZkkceZyR/P08PwHRXyGyEjfinTZHv4Rcbb6in3sh63lv+W Oeg+Mxq3608Yy69/O4i6NEk1uo+xAPwi2ZzhL5usNici0OPxdXy5mi3f1ofKlY1M3MsXugit74zY /C/P/bm5tSzkEcIYS4SQG6n0BqDaKDAuTm3qGkMu8Sgpx4wdX+77f6wL2bL3fKyIO95BOxNfWzda 6huflNkOBTRNFzU8Ytq7GuJyzNFJmOQN38b13/Vqvy7f5xpP2e5CoOT0CsGr78iQbW2QFrSlA/dR tmiKHtND5SHoe9OQgHE5xd2KjwbP6GhPIVHh0XAzO4ipCwks/s88wwr4+s5nUvmCUIQGWjCAt6T7 HWRsqbfvhJcGtSRiwwh3dqoOp4o/HFi7DJWJzfL7sinYVUECEfc2kf3Zy1Joh5cseTcLEjwXwVF/ i9FoUSkm7/+qRYORq4R4bHgmZKrOtjaeuyqKLAS2skM7CMVDlsgu4RkkzIgUWzlPFL8OqJ/D7aog SjzQRb0t6eDTBowoDjz9k/P4ZTWhQQpM7lSqS64Pe50RkLtEWXq0d1ihQtopB89R1T7pNY83O5jP iQb3bXJ4l8QAq38/yY6lCmNd7uDHUepn+P1ogwHuSrNtPeS6zEbclAxlctMaUZxX0J4gZlTBHDP+ kuhk6/Xq3O9OFjBSRV3uwNAb16Vtkx4heN9HKRidu+NyApK4l/SaxLbDPweNbcGl5AgBUKYHJx67 od5ubtUyPn1zfDZ/+9o+6Mam2f8eZX3zR04yDK2Bn1RbKrkEOYi+M4IetO4vVRpo3BnxdDOMmgyt M8Jm66UHlyRZl38cv7ypGbXtg7C8MlBgoHjA7Z++K3wQjLR71/Mz8VCwvvIXrmh5+iw3zdn0Gxmp QNBjFwtpBMQ0v1WHlcR6vRF59UR+YJx7nJuQaQSC62sL6bQDgNY4fXLzYL6MBpIBuZojxkyQvaL2 QLhyuEOyqbLMRyPsKb1DFVmgkqJs8b3SHJHhJCWp0OSm9eqHx61BOI/eQncNqGi5mHM34raCChwM MKCwl55zaMxNqac5qcivBkFLU+5YP90n+6Rjne9jvJmgXpsE2jeVmv3yaAcoOIFNLXZtnnXPBElv oHYTU5jreVYgg5aFtbFrrJjZBIY9cDl6GQfaV5qygpC34pdNBq66BCvMgf3zV14YXW1Qdw/0PaoA C4ByIv3mApntVAM6MSZ02S0rJ0OY5fGHDRDPFvrSy/eTdkDu3WN49CJx4xBfvjzwIgxQ18My9VtZ XPToQi4A5Un+P7n0qCHHYhGeOiSzqdoQa88688FN2OIvJY38R473eaTB7a6RP54PVbO4ZFee9Vlx 8jgOmmOIHTaBCAhTsZEJFW+ZRXxnxlxK+ScHGyCvsc/fLEZv3WKfFcO+eY45+zcrcSM+kqTdD2+y 0XoJu09U215jhRBNn11xOlvG2/9QaQqoF7PxfgIF+Z7HXhPth34/1Ampj+ZkFt96OUd3+PcxTKZR n0tgjMLYOe+Vxj11a3erduEkfxmjI1/BIh0XgDoh/YMhUcjEA1TIqkZGBhkiJSAZGO2wPrcRAE/G XlC+h9ADyPZ/HFO9+3JZyUElgpWJp7uP3LnK6BUsaa5aJo967mimc0Il1h9CC9y4ZDxI3tR0LLEP fsG8M0ddvGzUCKtVy9ZQArfD/BIBJTytCKj3JqWlruVF8m5s1C7q4VZEnA8mkIpQt3C75avulq14 dfZQ4VT+X5qpbYrk0fr26RlaUVkoi8gjjjkKK17DwClbctWNuClqYyARzRe+XGEqzzPD2LMvpYB9 dkZK5mbiDcZ5q5TUtZ0JT8YwO1xewBkw0U0TsnPc40Bg3AFBSBfICHoyvXUx/2i4uwCbuZ1rkmKV yJq+IXAzns+Rjrn5cbEpGLPUb5sBl4yzvR47Hw7h2l37kR+WjnQOWszgJR9EhkrSf2e3le69w5a1 y+kV69ZZAngIrxnO7tLGU7DAMZpP2HK1rcNJGHEVeV6Cju9S3De8wLfAoC4xk/u+p0mJBVfgiTZZ F+QJu71hNcjaGjmM7j9+yNiKtJxkv12M789f4JYnTr3/c0MsjGFbpGdg9doIoOACa09JxwmWDnjB XjYMPmEmQ9Pn70cMfljCllX2yIOTMOL/qden1Kr/r5yJLtk/gk/mF3e3DFxOSoz+6noNymev+cff 9DcseFJzE6OIldIQ+LzERegLilWDL7y5Cq/E0ydC9JnOopTycKwEmFlXQ93i3MA/bEyD0MPj+BCb cFLXXzysXUXuvr4DZUpybPsg8CxqVOPLIx80TtX6/37vd2rW4ekW14qeCuku/yP+65IHq/TVC/Cj Vj7/DdF65N76BVLsGDpyBF5M3iCRT7r4YljfMJh50XJmq1fGoM00qWj79DBBSu8ftjnYAM1aR236 mulXHJ2SmlR90UH76HiT7PZlXXnKF6Hw27+D651R+gS1uOoFCslQ9OGyt4x0tnoWSfUHTx9JsOu2 JCEJir/6U+0/4yhiv3qCQ4f2C07eTcRXcDKoz2WPUjTPM1G10wKYlsk1wu0fOQTGxfTXKvfSlRUZ JpkJobML3PFQbVCvjp87iOquOAaercevWvm63OldH8zG6PkE945z4JalO3BMu18jQhtC8MAlyg1w GYr8y5mMKf50nQ6arz/Yw2o4E1xAVazf/qVq8T1PEsz0TEryPOwsPRCgY4VAPAj+jV84kT+Y2tDq ZQmNetcpmFPVP1CByMxWN/BDuGeeiGMLHuVTLn9WATHuEqHsZ1LpaMLrQ47/6qGUp/OsXoXe8RWa Nk31dn9aSH8C8DOfLwO1WFomw14anVsj87QjfPR0r7493P/p0UiKdlMdciJ15OnBKWo7nKlHYtQV ADjjBUqE7/AHU2KtFNiJLEuxIJf3YsE73YSnRkRvw6xay8w2HDt7x3VV+yblvuYa/tOwoBZg0+/B UWFGhnc+JsSyB8ekofCoFWL9+th9bO6GxwBG7rdVFFvii4kfizqpLw07FrolhDRWMHIQPPA7JyR2 b7+hgf9wyg2gzbtRJbyvxuWYbF5ozIt7Zn6/koxNTptHa+EA8qDZeb0FfPSPjv7/GvRp/5Xz6l+z h6oDm92kPpH45ZTKgSV1bezTuW8vhxewANStDXOxTq1XX53HrDsLy5gY4HDs2xERFWu2eA2zmlW/ dg8QI778WGPjg+G13BGZy24xcplZCk350AXq5X4P5d0cIL2JmvonhS4MVyezvKGW5rfmABwNz+sf 7Dz2RaS7ol1anJvEIsUn6qD+onThNZ3di9xJ2ZCEb/+CJ05JMf4kDlLiqlcRe5OQDO2/1iI6htd6 ipHPGnqptn4/KpiX2EgYZx8GURGXaVdnQ7R8G8ddqGny95dRLrg4MOU2dHUI3MX72n1nB6gG0kye 5x+BgbISrtcFmHiJzdnhtHjKJ4nvLf8QOAGlZCImCO+jYYQJO6AcAn6lB3pfAxN6TkgXMswp8w6l NfGoZVp/ET1L5YmdKYIxHmVpyAxyuujm/Py8kr4DxmrSSOCYiD9SwFuqijoawS2RrtenAwTKwVtG fPhGl//TiqYV8tmR1yIp/ZQIsRch6VnvU9ZIIuT06mdz3QBGbXwNLlD/5L6IDv5LF88cITIsjKgB OZSJptDMbDc0xo412ndW7OaFFLDA2R1ehD0G9AbNfDEU9666YHBgd5bETI5WhP1D1ogHabQgi8p+ vWWeePzDo8Me7B0U0SHfpD+34VmiMNCVtJdbuO9EAHbHlwZWer+XSK/YFkwr6mBCGINyiprqmBLj ptXCGCbleiLqLAZ2u+XrBFa3h9iMSg9oN8kqVgEBQ2cAC9criFJSnBGWGkES4YcLJt0LTaf3UNDG 9hIpFe7agmPGZ6uadZjWcvmKYk9EKdQcNThCkggLDEAbMPFSVxMRHpVNS6GORghGz5EYeMwoPGMj z/PZ8y6TAdfk+9kUA5jFepmnf+xrb6isVp9CuYkZtyUaWVg/Np++IovUDvM0e1wGALXmg9BU6Mh6 p0EHNZtM7Wic8T5xXseGXC24RgV+9f9XPhzJGxcU1L4Fqsu/GSv4dKayW/09r5jDVNVilygQFjue RMJtpYRrbsTUFSH1e92EDVlQihnQkleIOCitVFonrfJi8MMHKo2WjqehApZB4fTKNFb2i87pDVG5 ulZLWq6oISzvLHNSNscJvtU+lp/SOCypMY4kNpDbJV7OxL7X9lxwOuMjxgxN+dzfchQV/5lAvIA0 Ymdu4svqA9C1p++AYyuJrPLI3BTaVyqNfu70cV25lSQ+//6PaDOC+h7zfHDNL6DibA6BB+QNYYOy Eg7Sdv2Fl904BigcCBN0t97FenAb4mzugpUJwqeOEXgdKQLsAazkN+jwZ6IK1UzrDOFmKIJ9wXb4 I4qE01km5sQPEMrqAJ00c/aTU3pCzXFu3cIJhO4/q5s2pMe4v0A+o/XQUxTj83K3xJsndKtkbdvK kMGWBI+ZPdI/7awmr/hb4rEoQ9woB1vtlQBfrpbK7iujvt/1rBUzwptUkqVeC0S6wz6R2yMn1CQO 58pS0iMjaIwQpXO3yFIwA6rlY+UYVveuYqeWjIr+AGiI2zxGcMDh5nUIqEN41aBP/5wBmS2fvEfZ P+ukmpQ6WUAEgL8AfTrJd9OXveaNyzxia0/f7mQddohWtouzlsesa5JXF1b1i7WSZLF72CqjcY+T 7kPs7j8BvaUBJRGxuZRZsJ94fkDpnkp1DupQdBJ71BHKTT0cZXCSDON1Wy2fi43eZgGbk3eTzY7d ouIPJ/HdNj6SWxlZ1y4tOXarSvJ4oFSObFy3qxaFEfhRs3HEEZ1bJH2zXtrfXfo0nSKmQKcnFkYa YsEsBqp69EeLzzGq9WKJYaZENvZ0nUK4wqYbjDxa/kfE3QJg0tVVbP++7EontrlggWAqoTgupJCl v/em7+DwY6AzBeARJZgkgd94cCAKpuDeTKOXSyLTgjgTVXC6OFVjiC/NiVl383XALXPfMiAVWmTS CIPfDMuHi+mWbz+ibjreZ6O7yqk4XYFmY2gTnTfbsCmCWY1HBiEiycuzV7Nka3YP0/p+3zsUKfhz KZWXcb6g7AH1JuOb/kj2ReGRwU3bRglImeoNbBY+KBJInVWFaxU2vKhYXjUAhr7306cGvx12uAOe YlDCjXJBvJHDaC5Va91usjE95f4LE15fznn8LDKavOhUp8Vr8NBoOyaM7V5jl4LpJKYUlnpsTh1k 4AKlzwHltc8MY1y1ZpRpLaISYaxGidjB7kYyNc4d+cO9C4r4Dy8hVE8LX/7rnt/JMoRHQO/wzVIG /ubRPRu88MJbzP/N9oYGsy8s+VxmyJo4/nX0ILFdfmUUS1hR2uDzjQB0o+TopNDK8GTx3cfN+VMf UUpSSSOhAR0Mm4uFdZoig1KoJZG2bJThbf4YeeIDih556GoELYeiOvz+W/q7ySGWe3kTioA8ZB8o AedcChGtD2DXTYAjyu64KPpRczdi6zoHujMcQPl1mErZfZ/S+uXA3RHCTPgSbTz35pkSovNvI9YV i8Qyvzv8S5NlJ/9FvXBfSgdZSiCRMFaseMfdq5IJnLoP56cIJBbZ6hi/gDiFRGXufHdvBX8cvLmv J4Jo0enwPaW1Y0jzZhKjuO595EtZEC4JTDMywXaN1h/ZmV9c3xFVBVEP4Lmc6rtEzamG6zswBpX1 M8mwMoL7q+xlRfvVKjAOxdPyyThThRyAdukCkAepnQIjtWyPv03yIAPoR5esQvX/dfrDiPjR9FYS jth9Q4Yx/3hVMljTaMBgRK9uZBN+3T71+BJG8z+eiuTy5ok5Yk6UKW10l6HYMcrLeiZcL/k5YLak OzBSET/V4jtz137N7HIeX2+jW9mY2FdHf2mcKN7lav1CHfwRVGh13IMYekF1hYMFHEBVsfUaMXKd Ex63u8vW4pWSSnuwmLL95MovthUP/qxGonzATwNsMZ2+N5j+usG20Jetox4ANXkNsISlz+8F5r+v V8lGPfWJnu6Jh9Y0+EfJ25HUv+H+OdDUXWmvoF7MsVCAgQSzloyRux7ktXtcNgzqfgMyRolYcqQ3 /7S53ODH5nLt5SJhDIo7XX+oNUmv4qmg1t/YzXYuHa59OfTKGeXHv1BkbQkIhBV3rhE6eVMss6JN GiiRS4TLLZkoy66kW2CPPagAowE6jDdSc/WXQS8mMiVC7TbMmqn9ABdLX8I+CcRRNmxHhHNkvwso ea8jdY1LTuSC5Lp65/pAJ4sw8mrYZJ+hy8oG+xiXVPWN9MzYvY3VctdNgBFoodECBebkSL98q+Bd o2PqMTYpdhW/GrZYE2lE/QMeLuiZkv3dweY3Y7woW9P+yQ56koCaPMcjAm8A8VeIgHdumeFaYu8X 3xoBR/xkVWTNjmO3A1buPxQRz+qh0EAqruYeTw/BDG6rIjSSCuwSV+pIomH1u1L5Rip5ymsrmH6j s0F1hmnIjG+uMN4oqQIMKqKelpYFFLaSgypytcJMmfhq69U= `protect end_protected

gpl-3.0

093f2fd8cd5c5d41004cd41270887e5f

0.927831

1.881346

false

grwlf/vsim

vhdl_ct/pro000028.vhd

1

1,711

-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Scherbinin. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type use work.std_logic_1164_for_tst.all; entity test_generate is generic(N:natural:=8); port ( in_bit : in bit; out_bit : out bit ); end entity test_generate; architecture test_generate_arch of test_generate is signal tst_signal : bit := '0'; signal tst_vector : bit_vector(0 to N-1):=('0','0','0','0','0','0','0','0'); begin tst_signal <= '1'; G2: if (N > 5) generate tst_vector(7) <= '1'; tst_vector(6) <= '1'; end generate G2; validate_g1: process (tst_vector) is variable i : bit; begin i := tst_signal; assert ( ( (tst_vector(6) = '1') and (tst_vector(7) = '1') and i='1' ) or i = '0') report "PRO000028: failure: wrong value." severity ERROR; end process validate_g1; end architecture test_generate_arch; entity ENT00028_Test_Bench is end ENT00028_Test_Bench; architecture ARCH00028_Test_Bench of ENT00028_Test_Bench is signal input, output : bit; begin input <= not input after 10 ns; test_entity: entity work.test_generate port map ( in_bit => input, out_bit => output ); end ARCH00028_Test_Bench ;

gpl-3.0

5bddff71c5d9ae9bafde840a3fc6c772

0.573349

3.32233

false

true

false

grwlf/vsim

vhdl_ct/ct00121.vhd

1

32,105

-- NEED RESULT: ARCH00121.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: ARCH00121: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS failed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00121 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- PKG00121 -- PKG00121/BODY -- ENT00121(ARCH00121) -- ENT00121_Test_Bench(ARCH00121_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00121 is type r_st_arr1_vector is record f1 : integer ; f2 : st_arr1_vector ; end record ; function c_r_st_arr1_vector_1 return r_st_arr1_vector ; -- (c_integer_1, c_st_arr1_vector_1) ; function c_r_st_arr1_vector_2 return r_st_arr1_vector ; -- (c_integer_2, c_st_arr1_vector_2) ; -- type r_st_arr2_vector is record f1 : integer ; f2 : st_arr2_vector ; end record ; function c_r_st_arr2_vector_1 return r_st_arr2_vector ; -- (c_integer_1, c_st_arr2_vector_1) ; function c_r_st_arr2_vector_2 return r_st_arr2_vector ; -- (c_integer_2, c_st_arr2_vector_2) ; -- type r_st_arr3_vector is record f1 : integer ; f2 : st_arr3_vector ; end record ; function c_r_st_arr3_vector_1 return r_st_arr3_vector ; -- (c_integer_1, c_st_arr3_vector_1) ; function c_r_st_arr3_vector_2 return r_st_arr3_vector ; -- (c_integer_2, c_st_arr3_vector_2) ; -- type r_st_rec1_vector is record f1 : integer ; f2 : st_rec1_vector ; end record ; function c_r_st_rec1_vector_1 return r_st_rec1_vector ; -- (c_integer_1, c_st_rec1_vector_1) ; function c_r_st_rec1_vector_2 return r_st_rec1_vector ; -- (c_integer_2, c_st_rec1_vector_2) ; -- type r_st_rec2_vector is record f1 : integer ; f2 : st_rec2_vector ; end record ; function c_r_st_rec2_vector_1 return r_st_rec2_vector ; -- (c_integer_1, c_st_rec2_vector_1) ; function c_r_st_rec2_vector_2 return r_st_rec2_vector ; -- (c_integer_2, c_st_rec2_vector_2) ; -- type r_st_rec3_vector is record f1 : integer ; f2 : st_rec3_vector ; end record ; function c_r_st_rec3_vector_1 return r_st_rec3_vector ; -- (c_integer_1, c_st_rec3_vector_1) ; function c_r_st_rec3_vector_2 return r_st_rec3_vector ; -- (c_integer_2, c_st_rec3_vector_2) ; -- -- end PKG00121 ; -- package body PKG00121 is function c_r_st_arr1_vector_1 return r_st_arr1_vector is begin return (c_integer_1, c_st_arr1_vector_1) ; end c_r_st_arr1_vector_1 ; -- function c_r_st_arr1_vector_2 return r_st_arr1_vector is begin return (c_integer_2, c_st_arr1_vector_2) ; end c_r_st_arr1_vector_2 ; -- -- function c_r_st_arr2_vector_1 return r_st_arr2_vector is begin return (c_integer_1, c_st_arr2_vector_1) ; end c_r_st_arr2_vector_1 ; -- function c_r_st_arr2_vector_2 return r_st_arr2_vector is begin return (c_integer_2, c_st_arr2_vector_2) ; end c_r_st_arr2_vector_2 ; -- -- function c_r_st_arr3_vector_1 return r_st_arr3_vector is begin return (c_integer_1, c_st_arr3_vector_1) ; end c_r_st_arr3_vector_1 ; -- function c_r_st_arr3_vector_2 return r_st_arr3_vector is begin return (c_integer_2, c_st_arr3_vector_2) ; end c_r_st_arr3_vector_2 ; -- -- function c_r_st_rec1_vector_1 return r_st_rec1_vector is begin return (c_integer_1, c_st_rec1_vector_1) ; end c_r_st_rec1_vector_1 ; -- function c_r_st_rec1_vector_2 return r_st_rec1_vector is begin return (c_integer_2, c_st_rec1_vector_2) ; end c_r_st_rec1_vector_2 ; -- -- function c_r_st_rec2_vector_1 return r_st_rec2_vector is begin return (c_integer_1, c_st_rec2_vector_1) ; end c_r_st_rec2_vector_1 ; -- function c_r_st_rec2_vector_2 return r_st_rec2_vector is begin return (c_integer_2, c_st_rec2_vector_2) ; end c_r_st_rec2_vector_2 ; -- -- function c_r_st_rec3_vector_1 return r_st_rec3_vector is begin return (c_integer_1, c_st_rec3_vector_1) ; end c_r_st_rec3_vector_1 ; -- function c_r_st_rec3_vector_2 return r_st_rec3_vector is begin return (c_integer_2, c_st_rec3_vector_2) ; end c_r_st_rec3_vector_2 ; -- -- -- end PKG00121 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00121.all ; entity ENT00121 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_arr1_vector : chk_sig_type := -1 ; signal chk_r_st_arr2_vector : chk_sig_type := -1 ; signal chk_r_st_arr3_vector : chk_sig_type := -1 ; signal chk_r_st_rec1_vector : chk_sig_type := -1 ; signal chk_r_st_rec2_vector : chk_sig_type := -1 ; signal chk_r_st_rec3_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_r_st_arr1_vector : inout r_st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P1" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr1_vector.f2 (lowb+1 to highb-1) = c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_r_st_arr2_vector : inout r_st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P2" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr2_vector.f2 (lowb+1 to highb-1) = c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_r_st_arr3_vector : inout r_st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P3" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_arr3_vector.f2 (lowb+1 to highb-1) = c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_r_st_rec1_vector : inout r_st_rec1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec1_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P4" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1_vector.f2 (lowb+1 to highb-1) = c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_r_st_rec2_vector : inout r_st_rec2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec2_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P5" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2_vector.f2 (lowb+1 to highb-1) = c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_r_st_rec3_vector : inout r_st_rec3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec3_vector : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns, c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns ; -- when 1 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00121.P6" , "Multi transport transactions occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 10 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 20 ns , c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) after 30 ns , c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 40 ns ; -- when 3 => correct := s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3_vector.f2 (lowb+1 to highb-1) = c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00121" , "One transport transaction occurred on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00121" , "Old transactions were removed on signal " & "asg with slice name prefixed by a selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- -- end ENT00121 ; -- architecture ARCH00121 of ENT00121 is signal s_r_st_arr1_vector : r_st_arr1_vector := c_r_st_arr1_vector_1 ; signal s_r_st_arr2_vector : r_st_arr2_vector := c_r_st_arr2_vector_1 ; signal s_r_st_arr3_vector : r_st_arr3_vector := c_r_st_arr3_vector_1 ; signal s_r_st_rec1_vector : r_st_rec1_vector := c_r_st_rec1_vector_1 ; signal s_r_st_rec2_vector : r_st_rec2_vector := c_r_st_rec2_vector_1 ; signal s_r_st_rec3_vector : r_st_rec3_vector := c_r_st_rec3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_r_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_r_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_r_st_arr1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_r_st_arr1_vector, counter, correct, savtime, chk_r_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_r_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_r_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_r_st_arr2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_r_st_arr2_vector, counter, correct, savtime, chk_r_st_arr2_vector ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_r_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_r_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_r_st_arr3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_r_st_arr3_vector, counter, correct, savtime, chk_r_st_arr3_vector ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_r_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_r_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_r_st_rec1_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_r_st_rec1_vector, counter, correct, savtime, chk_r_st_rec1_vector ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_r_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_r_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_r_st_rec2_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_r_st_rec2_vector, counter, correct, savtime, chk_r_st_rec2_vector ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_r_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_r_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_r_st_rec3_vector ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_r_st_rec3_vector, counter, correct, savtime, chk_r_st_rec3_vector ) ; end process P6 ; -- -- end ARCH00121 ; -- entity ENT00121_Test_Bench is end ENT00121_Test_Bench ; -- architecture ARCH00121_Test_Bench of ENT00121_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00121 ( ARCH00121 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00121_Test_Bench ;

gpl-3.0

40002ca8c1af7c7264c629d8c11a66eb

0.530073

3.350553

false

wsoltys/AtomFpga

src/AtomGodilVideo/src/MINIUART/utils.vhd

1

4,039

------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : utils.vhd -- Author : Philippe CARTON -- ([email protected]) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164 ------------------------------------------------------------------------------- -- Description: VHDL utility file ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- 1.0 Philippe CARTON 19 December 2001 New model -- [email protected] ------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Synchroniser: -- Synchronize an input signal (C1) with an input clock (C). -- The result is the O signal which is synchronous of C, and persist for -- one C clock period. -------------------------------------------------------------------------------- library IEEE,STD; use IEEE.std_logic_1164.all; entity synchroniser is port ( C1 : in std_logic;-- Asynchronous signal C : in std_logic;-- Clock O : out std_logic);-- Synchronised signal end synchroniser; architecture Behaviour of synchroniser is signal C1A : std_logic; signal C1S : std_logic; signal R : std_logic; begin RiseC1A : process(C1,R) begin if Rising_Edge(C1) then C1A <= '1'; end if; if (R = '1') then C1A <= '0'; end if; end process; SyncP : process(C,R) begin if Rising_Edge(C) then if (C1A = '1') then C1S <= '1'; else C1S <= '0'; end if; if (C1S = '1') then R <= '1'; else R <= '0'; end if; end if; if (R = '1') then C1S <= '0'; end if; end process; O <= C1S; end Behaviour; ------------------------------------------------------------------------------- -- Counter -- This counter is a parametrizable clock divider. -- The count value is the generic parameter Count. -- It is CE enabled. (it will count only if CE is high). -- When it overflow, it will emit a pulse on O. -- It can be reseted to 0. ------------------------------------------------------------------------------- library IEEE,STD; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Counter is port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset input CE : in std_logic; -- Chip Enable Count : in std_logic_vector (15 downto 0); -- Count revolution O : out std_logic); -- Output end Counter; architecture Behaviour of Counter is begin counter : process(Clk,Reset) variable Cnt : unsigned (15 downto 0); begin if Reset = '1' then Cnt := unsigned(Count); O <= '0'; elsif Rising_Edge(Clk) then if CE = '1' then if Cnt = 1 then O <= '1'; Cnt := unsigned(Count); else O <= '0'; Cnt := Cnt - 1; end if; else O <= '0'; end if; end if; end process; end Behaviour;

apache-2.0

5f89ee4c61a48031eac992732b9b4b51

0.416192

4.40458

false

jairov4/accel-oil

solution_virtex5/syn/vhdl/sample_iterator_next.vhd

2

14,025

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_req_din : OUT STD_LOGIC; indices_req_full_n : IN STD_LOGIC; indices_req_write : OUT STD_LOGIC; indices_rsp_empty_n : IN STD_LOGIC; indices_rsp_read : OUT STD_LOGIC; indices_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_datain : IN STD_LOGIC_VECTOR (55 downto 0); indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0); indices_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end; architecture behav of sample_iterator_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111"; constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal i_sample_read_reg_147 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_read_reg_153 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_153_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_153_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal indices_samples_load_new5_reg_165 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_7_fu_67_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_cast_fu_91_p1 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_9_fu_94_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_cast_fu_88_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_s_fu_104_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_9_fu_94_p2_temp: signed (17-1 downto 0); signal tmp_s_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_fu_115_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_fu_110_p2 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_index_write_assign_fu_128_p3 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_sample_write_assign_fu_120_p3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_index_read_reg_153_pp0_it1 <= i_index_read_reg_153; ap_reg_ppstg_i_index_read_reg_153_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it1; ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 <= i_sample_read_reg_147; ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_147_pp0_it1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_index_read_reg_153 <= i_index; i_sample_read_reg_147 <= i_sample; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_load_new5_reg_165 <= indices_datain(47 downto 32); end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; agg_result_index_write_assign_fu_128_p3 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it2 when (tmp_s_fu_104_p2(0) = '1') else tmp_2_fu_110_p2; agg_result_sample_write_assign_fu_120_p3 <= tmp_1_fu_115_p2 when (tmp_s_fu_104_p2(0) = '1') else ap_const_lv16_0; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return_0 <= agg_result_index_write_assign_fu_128_p3; ap_return_1 <= agg_result_sample_write_assign_fu_120_p3; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; indices_address <= tmp_7_fu_67_p1(32 - 1 downto 0); indices_dataout <= ap_const_lv56_0; indices_req_din <= ap_const_logic_0; -- indices_req_write assign process. -- indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_req_write <= ap_const_logic_1; else indices_req_write <= ap_const_logic_0; end if; end process; -- indices_rsp_read assign process. -- indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_rsp_read <= ap_const_logic_1; else indices_rsp_read <= ap_const_logic_0; end if; end process; indices_size <= ap_const_lv32_1; tmp_1_fu_115_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2) + unsigned(ap_const_lv16_1)); tmp_2_fu_110_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_index_read_reg_153_pp0_it2) + unsigned(ap_const_lv16_1)); tmp_7_fu_67_p1 <= std_logic_vector(resize(unsigned(i_index),64)); tmp_8_cast_fu_91_p1 <= std_logic_vector(resize(unsigned(indices_samples_load_new5_reg_165),17)); tmp_9_fu_94_p2 <= std_logic_vector(unsigned(tmp_8_cast_fu_91_p1) + unsigned(ap_const_lv17_1FFFF)); tmp_cast_fu_88_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2),18)); tmp_9_fu_94_p2_temp <= signed(tmp_9_fu_94_p2); tmp_s_fu_104_p1 <= std_logic_vector(resize(tmp_9_fu_94_p2_temp,18)); tmp_s_fu_104_p2 <= "1" when (signed(tmp_cast_fu_88_p1) < signed(tmp_s_fu_104_p1)) else "0"; end behav;

lgpl-3.0

b1f8b83a63add65cdca1453f50c077cb

0.606061

2.734984

false

jairov4/accel-oil

solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/sample_buffer_if_ap_fifo.vhd

3

2,817

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sample_buffer_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of sample_buffer_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;

lgpl-3.0

2ae093c6da3dfbc4baa7d4fc5acfa911

0.495918

3.682353

false

grwlf/vsim

vhdl_ct/ct00580.vhd

1

3,924

-- NEED RESULT: ARCH00580: Check involving overloading context rule 1 passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00580 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.5 (1) -- -- DESIGN UNIT ORDERING: -- -- PKG00580 -- PKG00580/BODY -- ENT00580_Test_Bench(ARCH00580_Test_Bench) -- -- REVISION HISTORY: -- -- 20-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- package PKG00580 is type COLOR is (RED, YELLOW, GREEN, BROWN, TAN, WHITE, BLUE) ; type LIGHTS is (RED, YELLOW, GREEN, BROWN, TAN, WHITE, BLUE) ; function F1 (A : COLOR := RED; B : LIGHTS := RED) return COLOR; function F1 (A : LIGHTS := BLUE; B : COLOR := BLUE) return LIGHTS; function "+" ( L,R : COLOR ) return COLOR ; function "+" ( L,R : LIGHTS ) return LIGHTS ; end PKG00580 ; package body PKG00580 is function F1 (A : COLOR := RED; B : LIGHTS := RED) return COLOR is variable RESULT : COLOR := RED; begin if (A /= RED) and (B /= BLUE) then RESULT := COLOR'PRED (A) ; return RESULT ; else return GREEN; end if; end F1; function F1 (A : LIGHTS := BLUE; B : COLOR := BLUE) return LIGHTS is variable RESULT : LIGHTS := RED; begin if (A /= RED) and (B /= BLUE) then RESULT := LIGHTS'PRED (A) ; return RESULT ; else return GREEN; end if; end F1; function "+" ( L,R : COLOR ) return COLOR is begin return COLOR'Val ((COLOR'Pos (L) + COLOR'Pos (R)) mod 7) ; end "+" ; function "+" ( L,R : LIGHTS ) return LIGHTS is begin return LIGHTS'Val (COLOR'Pos (COLOR'Val (LIGHTS'Pos (L)) + COLOR'Val (LIGHTS'Pos (R)) ) ) ; end "+" ; end PKG00580 ; use WORK.STANDARD_TYPES.all ; use WORK.PKG00580.all ; entity ENT00580_Test_Bench is end ENT00580_Test_Bench ; architecture ARCH00580_Test_Bench of ENT00580_Test_Bench is begin L1 : block constant CC1 : COLOR := F1 ; -- set to GREEN constant LC1 : LIGHTS := F1 ; -- set to GREEN constant CC2 : COLOR := F1 (COLOR'(GREEN)) ; -- set to YELLOW constant LC2 : LIGHTS := F1 (LIGHTS'(GREEN)) ; -- set to GREEN constant CC3 : COLOR := F1 (B => BLUE) ; -- set to GREEN constant LC3 : LIGHTS := F1 (B => BLUE) ; -- set to GREEN constant CC4 : COLOR := COLOR'(YELLOW) + COLOR'(GREEN) ; -- set to BRO constant LC4 : LIGHTS := LIGHTS'(YELLOW) + LIGHTS'(GREEN) ; -- set to BRO constant CC5 : COLOR := COLOR'(YELLOW) + BROWN ; -- set to TAN constant LC5 : LIGHTS := LIGHTS'(YELLOW) + BROWN ; -- set to TAN constant CC6 : COLOR := YELLOW + TAN ; -- set to WHITE constant LC6 : LIGHTS := YELLOW + TAN ; -- set to WHITE begin process begin test_report ( "ARCH00580" , "Check involving overloading context rule 1" , (CC1 = GREEN) and (LC1 = GREEN) and (CC2 = YELLOW) and (LC2 = GREEN) and (CC3 = GREEN) and (LC3 = GREEN) and (CC4 = BROWN) and (LC4 = BROWN) and (CC5 = TAN) and (LC5 = TAN) and (CC6 = WHITE) and (LC6 = WHITE) ) ; wait ; end process ; end block L1 ; end ARCH00580_Test_Bench ; --

gpl-3.0

8d7619007d9500070c7b89602947919b

0.47579

3.57377

false

true

false

wsoltys/AtomFpga

src/AVR8/Memory/XDM16Kx8.vhd

1

2,069

--************************************************************************************************ -- 16Kx8(16 KB) DM RAM for AVR Core(Xilinx) -- Version 0.2 -- Designed by Ruslan Lepetenok -- Modified 30.07.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For Synplicity Synplify --library virtexe; --use virtexe.components.all; -- Aldec library unisim; use unisim.vcomponents.all; entity XDM16Kx8 is port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(13 downto 0); din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); we : in std_logic ); end XDM16Kx8; architecture RTL of XDM16Kx8 is type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0); signal cp2n : std_logic; signal gnd : std_logic; begin gnd <= '0'; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0'; end generate ; RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate RAM_Byte:component RAMB4_S8 port map( DO => RAMBlDOut(i)(7 downto 0), ADDR => address(8 downto 0), DI => din(7 downto 0), EN => ce, CLK => cp2, WE => WEB(i), RST => gnd ); end generate; -- Output data mux dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9))); end RTL;

apache-2.0

7605d54cbb6046b6502815ab1c95a842

0.444176

3.896422

false

wsoltys/AtomFpga

src/AVR8/Memory/prog_mem_init.vhd

1

69,846

-- VHDL initialization records. -- -- Release 11.1i - Data2MEM L.33, build 1.5.8 Jul 23, 2008 -- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -- -- Command: C:\Users\ZBAND0~1\AppData\Local\Temp\build5746311222132730322.tmp\data2mem.exe -bm bitstreams/custom_bd.bmm -bd out.mem -o h E:\Papilio\Cores\GadgetFactory_Arduino_Timer_Counter\AVR8_SoftCore_TimerCounter_SPI\sources\Memory\prog_mem_init.vhd -- -- Created on 11/24/12 01:13 pm, from: -- -- Map file - bitstreams\custom_bd.bmm -- Data file(s) - out.mem -- -- Address space 'avrmap.rom_code' [0x00000000:0x00003FFF], 16384 bytes in size. -- -- Bus width = 16 bits, bit lane width = 16 bits, number of bus blocks = 8. library ieee; use ieee.std_logic_1164; package prog_mem_init_pkg is -- BRAM 0 in address space [0x00000000:0x000007FF], bit lane [15:0] -- INST PM_Inst/RAM_Word0 LOC = RAMB16_X0Y4; constant PM_Inst_RAM_Word0_INIT_00 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C0098940C"; constant PM_Inst_RAM_Word0_INIT_01 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C"; constant PM_Inst_RAM_Word0_INIT_02 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C1644940C00C7940C1539940C"; constant PM_Inst_RAM_Word0_INIT_03 : bit_vector(0 to 255) := x"000000280022003100340037003A0000005C222A2C3B5D5B2F3F3D2B5E3E3C7C"; constant PM_Inst_RAM_Word0_INIT_04 : bit_vector(0 to 255) := x"010101010101002000210030003300360039000000270023003200350038003B"; constant PM_Inst_RAM_Word0_INIT_05 : bit_vector(0 to 255) := x"0505050505050404040404040404030303030303030302020202020202020101"; constant PM_Inst_RAM_Word0_INIT_06 : bit_vector(0 to 255) := x"2010080402018040201008040201804020100804020106060606060606060505"; constant PM_Inst_RAM_Word0_INIT_07 : bit_vector(0 to 255) := x"0000000000008040201008040201804020100804020180402010080402018040"; constant PM_Inst_RAM_Word0_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000005000001000000000000"; constant PM_Inst_RAM_Word0_INIT_09 : bit_vector(0 to 255) := x"E6A0E011BFCDBFDEE0DFEFCFBE1F241116DD1193000000000000000000000000"; constant PM_Inst_RAM_Word0_INIT_0A : bit_vector(0 to 255) := x"E014BE1BF7C907B131A2F3C89631920D95D8C004BF0B9503EF0FE3F2E1E2E0B0"; constant PM_Inst_RAM_Word0_INIT_0B : bit_vector(0 to 255) := x"1901940E2FEC2FFD9722C005E0D1E3C0E011F7E107B131AB921DC001E0B1E1A2"; constant PM_Inst_RAM_Word0_INIT_0C : bit_vector(0 to 255) := x"9001918DC0042FB92FA82FF72FE60000940C1907940C170E940EF7C107D132CC"; constant PM_Inst_RAM_Word0_INIT_0D : bit_vector(0 to 255) := x"9508E0808385E186F02030672FF92FE895080B991B88F7C840505041F4211980"; constant PM_Inst_RAM_Word0_INIT_0E : bit_vector(0 to 255) := x"E090C002FD22B14DB98D7F8CB18D9A70C0019870F4113066C002FD60E0302F26"; constant PM_Inst_RAM_Word0_INIT_0F : bit_vector(0 to 255) := x"93DF93CF931F930F92FF9508E081B98D2B892B8470812F8295279536E092C001"; constant PM_Inst_RAM_Word0_INIT_10 : bit_vector(0 to 255) := x"C008E081F4113F8FB18FCFFE9B77B8FF94FA24FF2FD72FC61581940E2F172F06"; constant PM_Inst_RAM_Word0_INIT_11 : bit_vector(0 to 255) := x"2FF92FE8950890FF910F911F91CF91DFE080F388077117600B7D1B6C1581940E"; constant PM_Inst_RAM_Word0_INIT_12 : bit_vector(0 to 255) := x"2F84B96F2FB92FA8950815FC940EE06181842FF92FE8950815FC940EE0608184"; constant PM_Inst_RAM_Word0_INIT_13 : bit_vector(0 to 255) := x"96324F3F5F2EB98F8181CFFE9B77B98F8180CFFE9B77E030E0202FF92FE82F95"; constant PM_Inst_RAM_Word0_INIT_14 : bit_vector(0 to 255) := x"B98FEF8FCFFE9B77B98FEF8FCFFE9B77B98FEF8FCFFE9B77F78907383020E082"; constant PM_Inst_RAM_Word0_INIT_15 : bit_vector(0 to 255) := x"2F8A9715938C9615E1819508E081F4113085718F971A938C961AB18FCFFE9B77"; constant PM_Inst_RAM_Word0_INIT_16 : bit_vector(0 to 255) := x"2F172F061581940E2FD92FC893DF93CF931F930F92FF9508E0800125940E2F9B"; constant PM_Inst_RAM_Word0_INIT_17 : bit_vector(0 to 255) := x"B18FCFFE9B77B8FFC00CE08FF0104071526D0B711B601581940EC00994FA24FF"; constant PM_Inst_RAM_Word0_INIT_18 : bit_vector(0 to 255) := x"91CF91DFE0800125940E2F9D2F8C838DE08DC007E081F4113F8EF3813F8F878A"; constant PM_Inst_RAM_Word0_INIT_19 : bit_vector(0 to 255) := x"EF4F8538812FB98FEF8FF0D12388818E2FD92FC893DF93CF950890FF910F911F"; constant PM_Inst_RAM_Word0_INIT_1A : bit_vector(0 to 255) := x"CFFE9B77832F8738F3A84092508197012F932F824F3F5F2FB94FCFFE9B77C003"; constant PM_Inst_RAM_Word0_INIT_1B : bit_vector(0 to 255) := x"2FC893DF93CF931F930F92FF92EF92DF950891CF91DF821E0125940E2F9D2F8C"; constant PM_Inst_RAM_Word0_INIT_1C : bit_vector(0 to 255) := x"E071E26C2F9D2F8C011E940E2F9D2F8C0194940E2F152F042EF32EE22ED62FD9"; constant PM_Inst_RAM_Word0_INIT_1D : bit_vector(0 to 255) := x"95B6C0042E022D8E2D9F2FA02FB1E030E128CFFE9B77B98F64802D8D00FB940E"; constant PM_Inst_RAM_Word0_INIT_1E : bit_vector(0 to 255) := x"F41120DDF75907383F28EF8F40305028CFFE9B77B98FF7D2940A9587959795A7"; constant PM_Inst_RAM_Word0_INIT_1F : bit_vector(0 to 255) := x"CFFE9B77B92FEF2FE090CFFE9B77B98FEF8FC001E887F41116D8E088C006E985"; constant PM_Inst_RAM_Word0_INIT_20 : bit_vector(0 to 255) := x"92DF92CF950890DF90EF90FF910F911F91CF91DF878AF7C15091C002FF87B18F"; constant PM_Inst_RAM_Word0_INIT_21 : bit_vector(0 to 255) := x"055115412ED32EC22F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF"; constant PM_Inst_RAM_Word0_INIT_22 : bit_vector(0 to 255) := x"2F8CF7D1952A1F111F001CFF0CEEE029F0393083858BC03DE182F41105710561"; constant PM_Inst_RAM_Word0_INIT_23 : bit_vector(0 to 255) := x"2D4CEF6E2F9D2F8CC026E084F011238801B8940E2D2E2D3F2F402F51E1682F9D"; constant PM_Inst_RAM_Word0_INIT_24 : bit_vector(0 to 255) := x"2F8CC013E185F411238800FB940EE072E5682F9D2F8CF0F12388012C940E2D5D"; constant PM_Inst_RAM_Word0_INIT_25 : bit_vector(0 to 255) := x"2388B18FCFFE9B77B98FEF8FF439238801B8940EE050E040E030E020E06D2F9D"; constant PM_Inst_RAM_Word0_INIT_26 : bit_vector(0 to 255) := x"90CF90DF90EF90FF910F911F91CF91DFE0800125940E2F9D2F8C838DE184F081"; constant PM_Inst_RAM_Word0_INIT_27 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928FCFF1E0810125940E2F9D2F8C9508"; constant PM_Inst_RAM_Word0_INIT_28 : bit_vector(0 to 255) := x"2F80C081F409051115012E932E822ED72EC62EB52EA42FD92FC893DF93CF931F"; constant PM_Inst_RAM_Word0_INIT_29 : bit_vector(0 to 255) := x"0759174881BB81AA81998188F0712388818EC073F008409250811F930F822F91"; constant PM_Inst_RAM_Word0_INIT_2A : bit_vector(0 to 255) := x"E069F0393083858B82DB82CA82B982A8F538069916888598818FF429077B076A"; constant PM_Inst_RAM_Word0_INIT_2B : bit_vector(0 to 255) := x"238801B8940E2D2A2D3B2D4C2D5DE1612F9D2F8CF7D1956A1CDD1CCC1CBB0CAA"; constant PM_Inst_RAM_Word0_INIT_2C : bit_vector(0 to 255) := x"EF8F838EE081821F8618C03FF40923880165940E2F9D2F8CC046838DE083F019"; constant PM_Inst_RAM_Word0_INIT_2D : bit_vector(0 to 255) := x"2FB12FA0838F8798F3C8059915889601B92FCFFE9B77C004EF2F8598818FB98F"; constant PM_Inst_RAM_Word0_INIT_2E : bit_vector(0 to 255) := x"4F3F5F2FB99F83801FF30FE22DFF2DEEB18FCFFE9B77C00BEF9FE030E0209711"; constant PM_Inst_RAM_Word0_INIT_2F : bit_vector(0 to 255) := x"8589832F87381F310F208538812F938C1DBF0DAEB18FCFFE9B77F390073B172A"; constant PM_Inst_RAM_Word0_INIT_30 : bit_vector(0 to 255) := x"C001E0800125940E2F9D2F8CC0060194940E2F9D2F8CF05840325020F0192388"; constant PM_Inst_RAM_Word0_INIT_31 : bit_vector(0 to 255) := x"92FF92EF9508908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE081"; constant PM_Inst_RAM_Word0_INIT_32 : bit_vector(0 to 255) := x"92BF950890EF90FF910F911F0277940EE012E000E030E0202EF32EE2931F930F"; constant PM_Inst_RAM_Word0_INIT_33 : bit_vector(0 to 255) := x"834C821D821E8619861B2EB62FD92FC893DF93CF931F930F92FF92EF92DF92CF"; constant PM_Inst_RAM_Word0_INIT_34 : bit_vector(0 to 255) := x"15D4940EE060E08C0125940E2F9D2F8C15D4940EE061818C2ED72EC61581940E"; constant PM_Inst_RAM_Word0_INIT_35 : bit_vector(0 to 255) := x"E0809870B98DE58315D4940EE061E08A15D4940EE061E08D15D4940EE061E08B"; constant PM_Inst_RAM_Word0_INIT_36 : bit_vector(0 to 255) := x"097D196C1581940EC009011E940E2F9D2F8CF7D1308A5F8FCFFE9B77B99FEF9F"; constant PM_Inst_RAM_Word0_INIT_37 : bit_vector(0 to 255) := x"878A2F1801B8940EE050E040E030E020E0602F9D2F8CC065E081F01040775D61"; constant PM_Inst_RAM_Word0_INIT_38 : bit_vector(0 to 255) := x"E080C010871BC002FF8201B8940EE050E040E031EA2AE0682F9D2F8CF7513081"; constant PM_Inst_RAM_Word0_INIT_39 : bit_vector(0 to 255) := x"858B878BE082C03DE082F0113A9A879AF7C930845F8FB19FCFFE9B77B92FEF2F"; constant PM_Inst_RAM_Word0_INIT_3A : bit_vector(0 to 255) := x"196C1581940EC0092F17E4702D012CF12CE1C00F2711270024FF24EEF0293082"; constant PM_Inst_RAM_Word0_INIT_3B : bit_vector(0 to 255) := x"2F8C01B8940EE050E040E030E020E3672F9D2F8CC024E088F01040775D61097D"; constant PM_Inst_RAM_Word0_INIT_3C : bit_vector(0 to 255) := x"2F9D2F8CF5313082858BF7112388878A01B8940E2D2E2D3F2F402F51E2692F9D"; constant PM_Inst_RAM_Word0_INIT_3D : bit_vector(0 to 255) := x"E0800125940E2F9D2F8C838DE086F041238801B8940EE050E040E030E020E36A"; constant PM_Inst_RAM_Word0_INIT_3E : bit_vector(0 to 255) := x"CFFE9B77B99FEF9FE080878BE083F4113C807C80B18FCFFE9B77B98FEF8FC01C"; constant PM_Inst_RAM_Word0_INIT_3F : bit_vector(0 to 255) := x"911F91CF91DF00D8940E2D6B2F9D2F8C0125940E2F9D2F8CF7C930835F8FB12F"; -- BRAM 0 in address space [0x00000800:0x00000FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word1 LOC = RAMB16_X0Y8; constant PM_Inst_RAM_Word1_INIT_00 : bit_vector(0 to 255) := x"E220E090E0802FB72FA62FD92FC893DF93CF950890BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word1_INIT_01 : bit_vector(0 to 255) := x"E090E680F019322EC024E040E057F7B90591308B960183201FF90FE82FFB2FEA"; constant PM_Inst_RAM_Word1_INIT_02 : bit_vector(0 to 255) := x"1754F7B923332D3095C896012FF92FE8F1091732C01AE048E05AF131305AC007"; constant PM_Inst_RAM_Word1_INIT_03 : bit_vector(0 to 255) := x"5F4F83201DF10FE42FFB2FEA5220F408318A56812F82F4A0372FF0B03221F0C0"; constant PM_Inst_RAM_Word1_INIT_04 : bit_vector(0 to 255) := x"927F926F950891CF91DF2F89E090C001E091F0193280918CE090F6C923229129"; constant PM_Inst_RAM_Word1_INIT_05 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F"; constant PM_Inst_RAM_Word1_INIT_06 : bit_vector(0 to 255) := x"C07BF40807B707A60795178489BD89AC899B898AC085F4092322812C2F172F06"; constant PM_Inst_RAM_Word1_INIT_07 : bit_vector(0 to 255) := x"8529C06A861C861B861A86198618821F821E821DF4490511050104F114E1C08A"; constant PM_Inst_RAM_Word1_INIT_08 : bit_vector(0 to 255) := x"2E952E842E732E6240504040403050219609E09085858DFB8DEA855C854B853A"; constant PM_Inst_RAM_Word1_INIT_09 : bit_vector(0 to 255) := x"090108F108E194084F5F4F4F4F3F5F2FF7D2940A9467947794879496C0042E08"; constant PM_Inst_RAM_Word1_INIT_0A : bit_vector(0 to 255) := x"1D011CF11CE19408F7D2958A94A794B794C794D6C0042ED12EC02CBF2CAE0911"; constant PM_Inst_RAM_Word1_INIT_0B : bit_vector(0 to 255) := x"838D8DB98DA8899F898EF4490551054105311521F02804D904C804B714A61D11"; constant PM_Inst_RAM_Word1_INIT_0C : bit_vector(0 to 255) := x"2D288D9B8D8A8578816F815E814DC01208D908C808B718A6C01787B883AF839E"; constant PM_Inst_RAM_Word1_INIT_0D : bit_vector(0 to 255) := x"1E9D0E8C2C912E88E085C010F431238808D108C108B108A194080F04940E2D39"; constant PM_Inst_RAM_Word1_INIT_0E : bit_vector(0 to 255) := x"910F911F91CF91DFE080C001E081871C870B86FA86E9F72104D104C104B114A1"; constant PM_Inst_RAM_Word1_INIT_0F : bit_vector(0 to 255) := x"93CFCFE6CF73F00930229508906F907F908F909F90AF90BF90CF90DF90EF90FF"; constant PM_Inst_RAM_Word1_INIT_10 : bit_vector(0 to 255) := x"8989C00AE030E020F41923880CC5940E8998858F857E856D2F462FD92FC893DF"; constant PM_Inst_RAM_Word1_INIT_11 : bit_vector(0 to 255) := x"931F930F950891CF91DF2F932F824F3E5E2CF7E1959A1F330F22E095E0302F28"; constant PM_Inst_RAM_Word1_INIT_12 : bit_vector(0 to 255) := x"E0612F912F80C03DFF878183C043F409238881842FF92FE82F192F0893DF93CF"; constant PM_Inst_RAM_Word1_INIT_13 : bit_vector(0 to 255) := x"8F8C89B589A489938982F440308281842FF12FE0F1B997002FD92FC804FF940E"; constant PM_Inst_RAM_Word1_INIT_14 : bit_vector(0 to 255) := x"27AA2F8A2F9B8DB18DA0899789868F8A8F9B899789862FF12FE08FBF8FAE8F9D"; constant PM_Inst_RAM_Word1_INIT_15 : bit_vector(0 to 255) := x"96482F9D2F8C4F7F5E6A2F7D2F6CF0619730011391F0011291E08B8C8B9D27BB"; constant PM_Inst_RAM_Word1_INIT_16 : bit_vector(0 to 255) := x"91CF91DFE080C0010C64940E8383778F81832FF12FE08B8A8B9B8D998D889509"; constant PM_Inst_RAM_Word1_INIT_17 : bit_vector(0 to 255) := x"950891CF91DFE081821CF0112388051E940E2FD92FC893DF93CF9508910F911F"; constant PM_Inst_RAM_Word1_INIT_18 : bit_vector(0 to 255) := x"D000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F"; constant PM_Inst_RAM_Word1_INIT_19 : bit_vector(0 to 255) := x"C0A1F00930819714918C96142FB92FA82ED72EC62EB52EA42EF92EE8B7DEB7CD"; constant PM_Inst_RAM_Word1_INIT_1A : bit_vector(0 to 255) := x"8483847284612DFF2DEEC097E081F41105B105A19700C0B0C09DFF81918C9613"; constant PM_Inst_RAM_Word1_INIT_1B : bit_vector(0 to 255) := x"918D965A2DBF2DAEC085F4092388044E940E2D4A2D5B2D6C2D7D2D9F2D8E8494"; constant PM_Inst_RAM_Word1_INIT_1C : bit_vector(0 to 255) := x"23880F82940E9759917C916D915D914D9656F49104D104C104B114A1975B919C"; constant PM_Inst_RAM_Word1_INIT_1D : bit_vector(0 to 255) := x"917C916D915D914D96152DBF2DAEC0428E118E108A178A162DFF2DEEC06FF409"; constant PM_Inst_RAM_Word1_INIT_1E : bit_vector(0 to 255) := x"975B91FC91ED965A2DBF2DAEC057F40923880F04940E4F3F5F2F2F3D2F2C9718"; constant PM_Inst_RAM_Word1_INIT_1F : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987817C816B815A8149"; constant PM_Inst_RAM_Word1_INIT_20 : bit_vector(0 to 255) := x"8167815681452DFF2DEEF1B123880F82940E2F9F2F8EF4B0077B076A07591748"; constant PM_Inst_RAM_Word1_INIT_21 : bit_vector(0 to 255) := x"92BD92AD96522DBF2DAEF13123880E5B940EE03FEF2FEF1FEF0F8D938D828570"; constant PM_Inst_RAM_Word1_INIT_22 : bit_vector(0 to 255) := x"2D7DF0912388051E940E2D9F2D8E938C961368809713918C9613975592DC92CD"; constant PM_Inst_RAM_Word1_INIT_23 : bit_vector(0 to 255) := x"044E940E2D9F2D8E2D462D572D682D79F420049D048C047B146A2D4A2D5B2D6C"; constant PM_Inst_RAM_Word1_INIT_24 : bit_vector(0 to 255) := x"90AF90BF90CF90DF90EF90FF910F911F91DF91CF900F900F900F900FE080C001"; constant PM_Inst_RAM_Word1_INIT_25 : bit_vector(0 to 255) := x"F00807B707A60795178489B589A4899389822DFF2DEE9508906F907F908F909F"; constant PM_Inst_RAM_Word1_INIT_26 : bit_vector(0 to 255) := x"92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922FCFDFCF44"; constant PM_Inst_RAM_Word1_INIT_27 : bit_vector(0 to 255) := x"C0EDC0D7FF80818BC0DAF4092388818C2E552E442FD92FC893DF93CF931F930F"; constant PM_Inst_RAM_Word1_INIT_28 : bit_vector(0 to 255) := x"C0BF2C752C641E3D0E2C2C312E27E0752E932E822F372F26085F184E2C5B2C4A"; constant PM_Inst_RAM_Word1_INIT_29 : bit_vector(0 to 255) := x"E0992F152F042EF32EE2818C22B322A22EB6E0612EA6EF6F855C854B853A8529"; constant PM_Inst_RAM_Word1_INIT_2A : bit_vector(0 to 255) := x"1D5F0D4E8D758D648D538D42F44930828DFB8DEAF7D1959A94E794F795079516"; constant PM_Inst_RAM_Word1_INIT_2B : bit_vector(0 to 255) := x"F4490551054105311521F4D920DDF4E904B114A120DE94DA80D4C0411F711F60"; constant PM_Inst_RAM_Word1_INIT_2C : bit_vector(0 to 255) := x"2D222F9F2F8E8578816F815E814DC00D87B883AF839E838D8DB98DA8899F898E"; constant PM_Inst_RAM_Word1_INIT_2D : bit_vector(0 to 255) := x"40704060405050428578816F815E814D8DFB8DEAC080F40923880F04940E2D33"; constant PM_Inst_RAM_Word1_INIT_2E : bit_vector(0 to 255) := x"1F7B1F6A1F590F4889B189A085978586F7D2940A1F771F661F550F44C0048405"; constant PM_Inst_RAM_Word1_INIT_2F : bit_vector(0 to 255) := x"818B2ED92EC8F410059715862CD72CC6099B198AE092E0801D711D611D510D4D"; constant PM_Inst_RAM_Word1_INIT_30 : bit_vector(0 to 255) := x"00FC91B000FB91A000FA919000F99180C080F00906D8E08216C8E080C006FD86"; constant PM_Inst_RAM_Word1_INIT_31 : bit_vector(0 to 255) := x"2CF92CE82D1D2D0C2D3B2D2A0315919003149180C072F409077B076A07591748"; constant PM_Inst_RAM_Word1_INIT_32 : bit_vector(0 to 255) := x"2DA81D5D0D4C2F532F424F3E5E2C2D3B2D2AC0161C9D0C8CF19123880277940E"; constant PM_Inst_RAM_Word1_INIT_33 : bit_vector(0 to 255) := x"E0402D3D2D2C1E9F0E8E0BF31BE2F7D907F517E4938D9181C0022FF32FE22DB9"; constant PM_Inst_RAM_Word1_INIT_34 : bit_vector(0 to 255) := x"1461087D186C87BC87AB879A87891FB51FA41F930F8285BC85AB859A8589E050"; constant PM_Inst_RAM_Word1_INIT_35 : bit_vector(0 to 255) := x"90EF90FF910F911F91CF91DF2F952F84EF5FEF4FC0022D552D44CF3DF0090471"; constant PM_Inst_RAM_Word1_INIT_36 : bit_vector(0 to 255) := x"88CC88BB88AA9508902F903F904F905F906F907F908F909F90AF90BF90CF90DF"; constant PM_Inst_RAM_Word1_INIT_37 : bit_vector(0 to 255) := x"0BA0099F198E2D8A2D9B2DAC2DBDE050E0402F352F24851C850B84FA84E988DD"; constant PM_Inst_RAM_Word1_INIT_38 : bit_vector(0 to 255) := x"23880CC5940EE0402F642F752F862F97CEFCCEF9F40807B507A4079317820BB1"; constant PM_Inst_RAM_Word1_INIT_39 : bit_vector(0 to 255) := x"2ED92EC8B7DEB7CD920F93CF93DF931F930F92FF92EF92DF92CFCFC3CF95F009"; constant PM_Inst_RAM_Word1_INIT_3A : bit_vector(0 to 255) := x"E0414F7F5F6F2F7D2F6C2D9D2D8C8514850384F284E1F080308281842FF92FE8"; constant PM_Inst_RAM_Word1_INIT_3B : bit_vector(0 to 255) := x"90EF90FF910F911F91DF91CF900F2F932F82E030E020F07197010662940EE050"; constant PM_Inst_RAM_Word1_INIT_3C : bit_vector(0 to 255) := x"87B487A3879287811DB11DA1964F85B485A3859285812DFD2DEC950890CF90DF"; constant PM_Inst_RAM_Word1_INIT_3D : bit_vector(0 to 255) := x"F7E195EA1F330F22E0E5E0302F28708F2D8EF7D195FA94E794F795079516E0F5"; constant PM_Inst_RAM_Word1_INIT_3E : bit_vector(0 to 255) := x"2FE6C045F0092388818C2F172F062FD92FC893DF93CF931F930FCFD44F3E5E2C"; constant PM_Inst_RAM_Word1_INIT_3F : bit_vector(0 to 255) := x"0F88E045E0B0E0A08D918D808E198E188A1F8A1E838CE082F4B1318089872FF7"; -- BRAM 0 in address space [0x00001000:0x000017FF], bit lane [15:0] -- INST PM_Inst/RAM_Word2 LOC = RAMB16_X0Y1; constant PM_Inst_RAM_Word2_INIT_00 : bit_vector(0 to 255) := x"2FF72FE6838CE083F5413280C0188BBD8BAC8B9B8B8AF7D1954A1FBB1FAA1F99"; constant PM_Inst_RAM_Word2_INIT_01 : bit_vector(0 to 255) := x"0FE8940E2F912F804F3F5E2E2F3D2F2C8F798F688B5F8B4E8D758D648D538D42"; constant PM_Inst_RAM_Word2_INIT_02 : bit_vector(0 to 255) := x"861E861D861C861B861A86198618821F821E821D838BE0818F0A8F1BF0912388"; constant PM_Inst_RAM_Word2_INIT_03 : bit_vector(0 to 255) := x"2F142FD92FC893DF93CF931F9508910F911F91CF91DFE080C0018A198A18861F"; constant PM_Inst_RAM_Word2_INIT_04 : bit_vector(0 to 255) := x"C057F00974822F84F021718185834FFE5EECF7E1957A1FFF0FEEE075E0F02FE6"; constant PM_Inst_RAM_Word2_INIT_05 : bit_vector(0 to 255) := x"E0A0899589848BB887AF879E878D00FC91B000FB91A000FA919000F991808B69"; constant PM_Inst_RAM_Word2_INIT_06 : bit_vector(0 to 255) := x"8F688B5F8B4E2B7B2B6A2B592B48E0B0E0A08D938D82274427552F792F68E0B0"; constant PM_Inst_RAM_Word2_INIT_07 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A8DB78DA68D958D84F451970070907188E09085838F79"; constant PM_Inst_RAM_Word2_INIT_08 : bit_vector(0 to 255) := x"2F81838CE084F0D123880FE8940E8D9B8D8A4F3F5E2E2F3D2F2CF5219740C00D"; constant PM_Inst_RAM_Word2_INIT_09 : bit_vector(0 to 255) := x"2F9D2F8CC00AE081C002FD16861C861B861A86198618821F821E821D838B708F"; constant PM_Inst_RAM_Word2_INIT_0A : bit_vector(0 to 255) := x"2FD92FC893DF93CF9508911F91CF91DFE080C0010580940EE070E060E050E040"; constant PM_Inst_RAM_Word2_INIT_0B : bit_vector(0 to 255) := x"899F898EF0A123881061940EE070E060E050E0418D9B8D8A4F3F5F2B2F392F28"; constant PM_Inst_RAM_Word2_INIT_0C : bit_vector(0 to 255) := x"6880818B8FB98FA88B9F8B8E85B881AF819E818DF45905B105A197008DB98DA8"; constant PM_Inst_RAM_Word2_INIT_0D : bit_vector(0 to 255) := x"92DF92CF92BF92AF929F928F927F925F924F923F922F950891CF91DFE081838B"; constant PM_Inst_RAM_Word2_INIT_0E : bit_vector(0 to 255) := x"835E2F072F162ED92EC8B7DEB7CDD000D000D00093CF93DF931F930F92FF92EF"; constant PM_Inst_RAM_Word2_INIT_0F : bit_vector(0 to 255) := x"2DFD2DECC1B1C191FF81918C9613C195F00930819714918C96142FB92FA8834D"; constant PM_Inst_RAM_Word2_INIT_10 : bit_vector(0 to 255) := x"940E2D9D2D8CF03907B707A60795178485B485A3859285818975896489538942"; constant PM_Inst_RAM_Word2_INIT_11 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DACC132803E802D2E532E422F302F21C17AF4092388044E"; constant PM_Inst_RAM_Word2_INIT_12 : bit_vector(0 to 255) := x"EF7F2278947A8074F7D1951A9587959795A795B6E0192F822F932FA42FB5975B"; constant PM_Inst_RAM_Word2_INIT_13 : bit_vector(0 to 255) := x"914D96152DBD2DACC053F00904911481C057F0092077229322822E97E0712E87"; constant PM_Inst_RAM_Word2_INIT_14 : bit_vector(0 to 255) := x"97002DA091BC900D919D918D9656F48905710561055115419718917C916D915D"; constant PM_Inst_RAM_Word2_INIT_15 : bit_vector(0 to 255) := x"4F3F5F2F2F3D2F2C2F9F2F8EC03587B083A7839683852DFD2DECF17905B105A1"; constant PM_Inst_RAM_Word2_INIT_16 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DAC815C814B813A8129C12EE050E040F41923880F04940E"; constant PM_Inst_RAM_Word2_INIT_17 : bit_vector(0 to 255) := x"074A07391728E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987975B"; constant PM_Inst_RAM_Word2_INIT_18 : bit_vector(0 to 255) := x"E08087508347833683252DFD2DECC105F439238808AC940E2D9D2D8CF038075B"; constant PM_Inst_RAM_Word2_INIT_19 : bit_vector(0 to 255) := x"975B91FC91ED965A2DBD2DAC2EB92EA8F410059315822CB32CA209991988E092"; constant PM_Inst_RAM_Word2_INIT_1A : bit_vector(0 to 255) := x"C00484051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E9718911C910D90FD90ED9615"; constant PM_Inst_RAM_Word2_INIT_1B : bit_vector(0 to 255) := x"1CF10CE71F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEE"; constant PM_Inst_RAM_Word2_INIT_1C : bit_vector(0 to 255) := x"158E00FC91B000FB91A000FA919000F99180F56906B9E09216A9E0901D111D01"; constant PM_Inst_RAM_Word2_INIT_1D : bit_vector(0 to 255) := x"00FC93B000FB93A000FA939000F99380EFBFEFAFEF9FEF8FF46107B107A0059F"; constant PM_Inst_RAM_Word2_INIT_1E : bit_vector(0 to 255) := x"E0A0C09FF4092388020E940E2D352D242D4E2D5F2F602F710315919003149180"; constant PM_Inst_RAM_Word2_INIT_1F : bit_vector(0 to 255) := x"89A48993898285548543853285212DFD2DECF51104911481C0451E5B0E4AE0B2"; constant PM_Inst_RAM_Word2_INIT_20 : bit_vector(0 to 255) := x"930000FA92F000F992E0C083F40923880C64940EF098075B074A0739172889B5"; constant PM_Inst_RAM_Word2_INIT_21 : bit_vector(0 to 255) := x"0CC5940EE0412D6E2D7F2F802F91C00A0316938060810316918000FC931000FB"; constant PM_Inst_RAM_Word2_INIT_22 : bit_vector(0 to 255) := x"C0022FF32FE22DB52DA41D5B0D4A2F532F424F3E5E2C2D392D28C06BF4092388"; constant PM_Inst_RAM_Word2_INIT_23 : bit_vector(0 to 255) := x"2DECE050E0402D3B2D2A083B182A1E5F0E4E0BF31BE2F7D907F517E49381918D"; constant PM_Inst_RAM_Word2_INIT_24 : bit_vector(0 to 255) := x"96192DBD2DAC87B487A3879287811FB51FA41F930F8285B485A3859285812DFD"; constant PM_Inst_RAM_Word2_INIT_25 : bit_vector(0 to 255) := x"17822DA091BC900D919D918D9652CEC2F00904311421971C915C914D913D912D"; constant PM_Inst_RAM_Word2_INIT_26 : bit_vector(0 to 255) := x"01129180C0128383688081838B558B448B338B222DFD2DECF45007B507A40793"; constant PM_Inst_RAM_Word2_INIT_27 : bit_vector(0 to 255) := x"938C961368809713918C96132DBD2DACF0412B89819E818DF0612B8901139190"; constant PM_Inst_RAM_Word2_INIT_28 : bit_vector(0 to 255) := x"2DACE081C007815E814DF0192388051E940E2D9D2D8CC006FF8381832DFD2DEC"; constant PM_Inst_RAM_Word2_INIT_29 : bit_vector(0 to 255) := x"911F91DF91CFBFCDBE0FBFDE94F8B60F96262F952F84EF5FEF4F938C96122DBD"; constant PM_Inst_RAM_Word2_INIT_2A : bit_vector(0 to 255) := x"FD829508902F903F904F905F907F908F909F90AF90BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word2_INIT_2B : bit_vector(0 to 255) := x"08D5940E2F5B2F4A0BBF1BAE9711F7E92000900D2FBF2FAE2FF72FE6CE62CE4D"; constant PM_Inst_RAM_Word2_INIT_2C : bit_vector(0 to 255) := x"900F08D5940EE050E0414F7F5F6F2F7D2F6C8369B7DEB7CD920F93CF93DF9508"; constant PM_Inst_RAM_Word2_INIT_2D : bit_vector(0 to 255) := x"F409238808AC940E2FD92FC893DF93CF931F930F92FF92EF92DF950891DF91CF"; constant PM_Inst_RAM_Word2_INIT_2E : bit_vector(0 to 255) := x"84051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E8518810F80FE80ED8DFB8DEAC050"; constant PM_Inst_RAM_Word2_INIT_2F : bit_vector(0 to 255) := x"80D41F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEEC004"; constant PM_Inst_RAM_Word2_INIT_30 : bit_vector(0 to 255) := x"0C9F940E1D911D811D710D6D2D6E2D7F2F802F91C00D0911090108F108E19408"; constant PM_Inst_RAM_Word2_INIT_31 : bit_vector(0 to 255) := x"1F441F330F22C0048405E050E040E032E0208DFB8DEAF78920DD94DAF0F92388"; constant PM_Inst_RAM_Word2_INIT_32 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A1FB51FA41F930F8289BD89AC899B898AF7D2940A1F55"; constant PM_Inst_RAM_Word2_INIT_33 : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F950890DF90EF90FF910F911F91CF91DFE080C001"; constant PM_Inst_RAM_Word2_INIT_34 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F972BB7DEB7CD93CF93DF931F930F92FF92EF92DF92CF"; constant PM_Inst_RAM_Word2_INIT_35 : bit_vector(0 to 255) := x"2F1D2F0C2F952F84C0F2F0092388918C96142FB92FA82E822ED72EC62EB92EA8"; constant PM_Inst_RAM_Word2_INIT_36 : bit_vector(0 to 255) := x"965B2DBB2DAA8D938D822DFD2DECC0E5F40923880407940E2F712F604F1F5F0F"; constant PM_Inst_RAM_Word2_INIT_37 : bit_vector(0 to 255) := x"2499971C921C921D921D921D96192DBD2DAC8610821782168215975A938E939C"; constant PM_Inst_RAM_Word2_INIT_38 : bit_vector(0 to 255) := x"9516E085C0C0F40997002FF92FE80793940E2D9D2D8CC0492E792E602F912F80"; constant PM_Inst_RAM_Word2_INIT_39 : bit_vector(0 to 255) := x"2DBB2DAAF4992099F4D93E85F01123888180701F2D1EF7D1958A94E794F79507"; constant PM_Inst_RAM_Word2_INIT_3A : bit_vector(0 to 255) := x"935C934D933D932D961D00FC915000FB914000FA913000F991209751931C9651"; constant PM_Inst_RAM_Word2_INIT_3B : bit_vector(0 to 255) := x"2F2800C9940EE050E04B2F7F2F6E2D972D86C02794932499F4C1238881809750"; constant PM_Inst_RAM_Word2_INIT_3C : bit_vector(0 to 255) := x"2DFD2DEC94932499C07E2F612D9B2D8AC086F409338073802D88F4592B232F39"; constant PM_Inst_RAM_Word2_INIT_3D : bit_vector(0 to 255) := x"71822D88CFA7F408071B070A06F916E889B589A4899389828514850384F284E1"; constant PM_Inst_RAM_Word2_INIT_3E : bit_vector(0 to 255) := x"2DACC05FF4A197002F192F0804FF940EE0612D9B2D8AF0512099C06BF0093182"; constant PM_Inst_RAM_Word2_INIT_3F : bit_vector(0 to 255) := x"8A112DFB2DEAC051F40923880AD3940E2D9D2D8CC058F4093082918C96142DBD"; -- BRAM 0 in address space [0x00001800:0x00001FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word3 LOC = RAMB16_X0Y3; constant PM_Inst_RAM_Word3_INIT_00 : bit_vector(0 to 255) := x"920D9001E08B96312FFD2FEC2FB12FA0F7E9958A921D2FB12FA0E280E011E104"; constant PM_Inst_RAM_Word3_INIT_01 : bit_vector(0 to 255) := x"950996402F912F804F7F5F622F712F60F0499730011391F0011291E0F7E15081"; constant PM_Inst_RAM_Word3_INIT_02 : bit_vector(0 to 255) := x"919C918D96502FB12FA087868797E098E0808B808B912FF12FE0E298E281C00A"; constant PM_Inst_RAM_Word3_INIT_03 : bit_vector(0 to 255) := x"938E939C9657971F919C918D961E9758938E939C96599752938E939C96539751"; constant PM_Inst_RAM_Word3_INIT_04 : bit_vector(0 to 255) := x"962BE080C001083A940E2D4889612DFB2DEA2D9B2D8AF04923880C64940E9756"; constant PM_Inst_RAM_Word3_INIT_05 : bit_vector(0 to 255) := x"909F90AF90BF90CF90DF90EF90FF910F911F91DF91CFBFCDBE0FBFDE94F8B60F"; constant PM_Inst_RAM_Word3_INIT_06 : bit_vector(0 to 255) := x"00FC917000FB916000FA915000F99140F1992388031691809508906F907F908F"; constant PM_Inst_RAM_Word3_INIT_07 : bit_vector(0 to 255) := x"031991600318915003179140F1192388020E940EE031E1240315919003149180"; constant PM_Inst_RAM_Word3_INIT_08 : bit_vector(0 to 255) := x"2388020E940EE031E1240315919003149180F0910571056105511541031A9170"; constant PM_Inst_RAM_Word3_INIT_09 : bit_vector(0 to 255) := x"92EF9508E0809508E08103169210031A9210031992100318921003179210F061"; constant PM_Inst_RAM_Word3_INIT_0A : bit_vector(0 to 255) := x"31E4E0839211E0F1E1E4F0A923880C64940E2F192F082EF72EE6931F930F92FF"; constant PM_Inst_RAM_Word3_INIT_0B : bit_vector(0 to 255) := x"E0810316938060810316918000FC931000FB930000FA92F000F992E0F7D907F8"; constant PM_Inst_RAM_Word3_INIT_0C : bit_vector(0 to 255) := x"91802ED42F192F082EF72EE6931F930F92FF92EF92DF950890EF90FF910F911F"; constant PM_Inst_RAM_Word3_INIT_0D : bit_vector(0 to 255) := x"F0E923880C64940EF0D107B107A0059F158E00FC91B000FB91A000FA919000F9"; constant PM_Inst_RAM_Word3_INIT_0E : bit_vector(0 to 255) := x"00F992E0F0792388031E940EE031E1242D4E2D5F2F602F710315919003149180"; constant PM_Inst_RAM_Word3_INIT_0F : bit_vector(0 to 255) := x"910F911FE080C001E08103169380298D0316918000FC931000FB930000FA92F0"; constant PM_Inst_RAM_Word3_INIT_10 : bit_vector(0 to 255) := x"93DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F950890DF90EF90FF"; constant PM_Inst_RAM_Word3_INIT_11 : bit_vector(0 to 255) := x"F0083045C04124BB24AA24992488F429234403149360031593702F142ED92EC8"; constant PM_Inst_RAM_Word3_INIT_12 : bit_vector(0 to 255) := x"2FFD2FEC9721E0D02FC1C122F40923880CC5940EE040E090E080E070E060C12C"; constant PM_Inst_RAM_Word3_INIT_13 : bit_vector(0 to 255) := x"2B897090778FE09040F15BEE81804FFE54E24FFE5EECF7E1957A1FFF0FEEE074"; constant PM_Inst_RAM_Word3_INIT_14 : bit_vector(0 to 255) := x"0FCCE064C0FFF40805B105A10591368481B381A2819181804FFE53E6C10BF009"; constant PM_Inst_RAM_Word3_INIT_15 : bit_vector(0 to 255) := x"2D9BC0EEF40904B104A10491148180BB80AA809980884FDD52C6F7E1956A1FDD"; constant PM_Inst_RAM_Word3_INIT_16 : bit_vector(0 to 255) := x"F0094092508001209190011F9180C0E4F40923880CC5940EE0402D682D792D8A"; constant PM_Inst_RAM_Word3_INIT_17 : bit_vector(0 to 255) := x"238801219180C0D0F4092B890123919001229180C0D7F409232201249120C0DC"; constant PM_Inst_RAM_Word3_INIT_18 : bit_vector(0 to 255) := x"87452DFD2DEC5F4FC008E070E06186158384012191808B222DFD2DECC0CBF409"; constant PM_Inst_RAM_Word3_INIT_19 : bit_vector(0 to 255) := x"940A1F330F22C0022E042F372F26E090818485452DFD2DECC0B9F00830485041"; constant PM_Inst_RAM_Word3_INIT_1A : bit_vector(0 to 255) := x"01389120C008E050E040F01905311521012B9130012A9120F74107931782F7E2"; constant PM_Inst_RAM_Word3_INIT_1B : bit_vector(0 to 255) := x"012390F0012290E087508347833683252DFD2DEC013B9150013A914001399130"; constant PM_Inst_RAM_Word3_INIT_1C : bit_vector(0 to 255) := x"8F808F9101269190012591808B168B058AF48AE31D1B1D0A1CF90CE8E010E000"; constant PM_Inst_RAM_Word3_INIT_1D : bit_vector(0 to 255) := x"8F848F738F622DFD2DEC1F911F801D7F0D6E18A2940EE090E080E07001249160"; constant PM_Inst_RAM_Word3_INIT_1E : bit_vector(0 to 255) := x"E040952627332F234F3E5021F7E1955A1F330F22E05501269130012591208F95"; constant PM_Inst_RAM_Word3_INIT_1F : bit_vector(0 to 255) := x"E0A0F019970001289190012791808B518B40873787261F591F481F370F26E050"; constant PM_Inst_RAM_Word3_INIT_20 : bit_vector(0 to 255) := x"0AF31AE22CE82CF92D0A2D1B013791B0013691A00135919001349180C008E0B0"; constant PM_Inst_RAM_Word3_INIT_21 : bit_vector(0 to 255) := x"95479556C00484052DFD2DEC1F5B1F4A1F390F282D2E2D3F2F402F510B150B04"; constant PM_Inst_RAM_Word3_INIT_22 : bit_vector(0 to 255) := x"F410075FE0F0074FE0F0073FE0FF3F258754874387328721F7D2940A95279537"; constant PM_Inst_RAM_Word3_INIT_23 : bit_vector(0 to 255) := x"919001409180C011E0818B872DFD2DECE180F430405040404F3F5F25C006E08C"; constant PM_Inst_RAM_Word3_INIT_24 : bit_vector(0 to 255) := x"91CF91DFE080CFEDE2808FB58FA48F938F822DFD2DEC014391B0014291A00141"; constant PM_Inst_RAM_Word3_INIT_25 : bit_vector(0 to 255) := x"928F927F926F925F924F9508908F909F90AF90BF90CF90DF90EF90FF910F911F"; constant PM_Inst_RAM_Word3_INIT_26 : bit_vector(0 to 255) := x"2EE62ED52EC42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F"; constant PM_Inst_RAM_Word3_INIT_27 : bit_vector(0 to 255) := x"960185BC85AB859A8589C077F40805710561055130422E732E622E512E402EF7"; constant PM_Inst_RAM_Word3_INIT_28 : bit_vector(0 to 255) := x"2799F4293180898F895E894D893C892BC06AF40807B707A6079517841DB11DA1"; constant PM_Inst_RAM_Word3_INIT_29 : bit_vector(0 to 255) := x"2E86F7D1951A9567957795879596E0172D6C2D7D2D8E2D9FC00B2D6D2D7E2D8F"; constant PM_Inst_RAM_Word3_INIT_2A : bit_vector(0 to 255) := x"168800FC91B000FB91A000FA919000F991801EB51EA41E930E822EB92EA82E97"; constant PM_Inst_RAM_Word3_INIT_2B : bit_vector(0 to 255) := x"F4513180898FF1A923880CC5940EE0402D682D792D8A2D9BF04906BB06AA0699"; constant PM_Inst_RAM_Word3_INIT_2C : bit_vector(0 to 255) := x"1FFF0FEE70F077EF2DFD2DECC00E824082514FFE5EEC1FFF0FEE70F02DFD2DEC"; constant PM_Inst_RAM_Word3_INIT_2D : bit_vector(0 to 255) := x"F0803082898A0316938060810316918082738262825182404FFE5EEC1FFF0FEE"; constant PM_Inst_RAM_Word3_INIT_2E : bit_vector(0 to 255) := x"031A92B0031992A003189290031792801EBB1EAA1E990E8885B881AF819E818D"; constant PM_Inst_RAM_Word3_INIT_2F : bit_vector(0 to 255) := x"907F908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE080C001E081"; constant PM_Inst_RAM_Word3_INIT_30 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF9508904F905F906F"; constant PM_Inst_RAM_Word3_INIT_31 : bit_vector(0 to 255) := x"F40807B707A6079517841DB11DA1960185BC85AB859A85892ED32EC22F172F06"; constant PM_Inst_RAM_Word3_INIT_32 : bit_vector(0 to 255) := x"2D7F2F802F91C00B2D6F2F702F812799F4293180898F895E894D893C892BC057"; constant PM_Inst_RAM_Word3_INIT_33 : bit_vector(0 to 255) := x"00FA919000F991801F591F481F370F26F7D195EA9567957795879596E0E72D6E"; constant PM_Inst_RAM_Word3_INIT_34 : bit_vector(0 to 255) := x"0CC5940EE0402F622F732F842F95F049075B074A0739172800FC91B000FB91A0"; constant PM_Inst_RAM_Word3_INIT_35 : bit_vector(0 to 255) := x"E0B0E0A0819181804FFE5EEC1FFF0FEE70F02DFF2DEEF4613180898FF1312388"; constant PM_Inst_RAM_Word3_INIT_36 : bit_vector(0 to 255) := x"70BF81B381A2819181804FFE5EEC1FFF0FEE1FFF0FEE70F077EF2DFF2DEEC00F"; constant PM_Inst_RAM_Word3_INIT_37 : bit_vector(0 to 255) := x"90DF90EF90FF910F911F91CF91DFE080C001E08183B383A2839183802DFD2DEC"; constant PM_Inst_RAM_Word3_INIT_38 : bit_vector(0 to 255) := x"B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF950890CF"; constant PM_Inst_RAM_Word3_INIT_39 : bit_vector(0 to 255) := x"83B383A2839183802DFD2DECE0B0E0A0E090E0822F172F062EF52EE42ED92EC8"; constant PM_Inst_RAM_Word3_INIT_3A : bit_vector(0 to 255) := x"23880F04940E2D3B2D2A2D4E2D5F2F602F712D9D2D8C1CB11CA194082EBD2EAC"; constant PM_Inst_RAM_Word3_INIT_3B : bit_vector(0 to 255) := x"80E9F0C923880E5B940EE030E020E010E0002D4E2D5F2F602F712D9D2D8CF139"; constant PM_Inst_RAM_Word3_INIT_3C : bit_vector(0 to 255) := x"E0A0EF9FEF88C004E0BFEFAFEF9FEF88F029318089872DFD2DEC811C810B80FA"; constant PM_Inst_RAM_Word3_INIT_3D : bit_vector(0 to 255) := x"911F91DF91CF900F900F900F900FE080C001E081F278071B070A06F916E8E0B0"; constant PM_Inst_RAM_Word3_INIT_3E : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F925F924F950890AF90BF90CF90DF90EF90FF910F"; constant PM_Inst_RAM_Word3_INIT_3F : bit_vector(0 to 255) := x"835A83492ED92EC8B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF"; -- BRAM 0 in address space [0x00002000:0x000027FF], bit lane [15:0] -- INST PM_Inst/RAM_Word4 LOC = RAMB16_X0Y2; constant PM_Inst_RAM_Word4_INIT_00 : bit_vector(0 to 255) := x"2E9AE0A22C811C511C4194082E5D2E4C2711270024FF24EE2E732E62837C836B"; constant PM_Inst_RAM_Word4_INIT_01 : bit_vector(0 to 255) := x"2DAA2DBBF17123880F04940E2D352D242D9D2D8C817C816B815A81492CB12CA1"; constant PM_Inst_RAM_Word4_INIT_02 : bit_vector(0 to 255) := x"1F1B1F0A1EF90EE8F7D2940A1FBB1FAA1F990F88C00484052DFD2DEC2D882D99"; constant PM_Inst_RAM_Word4_INIT_03 : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987815C814B813A8129"; constant PM_Inst_RAM_Word4_INIT_04 : bit_vector(0 to 255) := x"900F900F900F900FE0818313830282F182E02DF72DE6F268075B074A07391728"; constant PM_Inst_RAM_Word4_INIT_05 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF"; constant PM_Inst_RAM_Word4_INIT_06 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F9508"; constant PM_Inst_RAM_Word4_INIT_07 : bit_vector(0 to 255) := x"876C875B874A2E392E28BFCDBE0FBFDE94F8B60F972FB7DEB7CD93CF93DF931F"; constant PM_Inst_RAM_Word4_INIT_08 : bit_vector(0 to 255) := x"2E912E80F0590531052105111501913C912D911D910D2FB32FA2872E873F877D"; constant PM_Inst_RAM_Word4_INIT_09 : bit_vector(0 to 255) := x"861980B380A2809180802FF92FE8C01186191CB11CA11C911C8194082EB32EA2"; constant PM_Inst_RAM_Word4_INIT_0A : bit_vector(0 to 255) := x"900D919D918D96192DB32DA28799E091F41105B105A1970185BD85AC859B858A"; constant PM_Inst_RAM_Word4_INIT_0B : bit_vector(0 to 255) := x"2466245524442CC82CD92CEA2CFB87B883AF839E838D1DB11DA196012DA091BC"; constant PM_Inst_RAM_Word4_INIT_0C : bit_vector(0 to 255) := x"F008067B066A0659164885B485A3859285812DF32DE24F1F5F0F2F1D2F0C2477"; constant PM_Inst_RAM_Word4_INIT_0D : bit_vector(0 to 255) := x"E0B22CB12CA12C912E88E082F45005BF05AE059D158C85B881AF819E818DC0A8"; constant PM_Inst_RAM_Word4_INIT_0E : bit_vector(0 to 255) := x"F40923880F04940E2F312F202D4C2D5D2D6E2D7F2D932D822CF12CE12CD12ECB"; constant PM_Inst_RAM_Word4_INIT_0F : bit_vector(0 to 255) := x"05B105A197004F5F4F4F4F3F5F2F2D2C2D3D2D4E2D5F81BC81AB819A8189C088"; constant PM_Inst_RAM_Word4_INIT_10 : bit_vector(0 to 255) := x"0739172885BD85AC859B858A095B094A09391928C00D2EB52EA42E932E82F029"; constant PM_Inst_RAM_Word4_INIT_11 : bit_vector(0 to 255) := x"2D932D82CFA71CF11CE11CD11CC194081C711C611C511C419408F059075B074A"; constant PM_Inst_RAM_Word4_INIT_12 : bit_vector(0 to 255) := x"2C6E2C5D2C4CC04CF4E123880E5B940EE03FEF2FEF1FEF0F2D7F2D6E2D5D2D4C"; constant PM_Inst_RAM_Word4_INIT_13 : bit_vector(0 to 255) := x"2D0C2D1D2D2E2D3F2D442D552D662D772D932D82087108610851084194082C7F"; constant PM_Inst_RAM_Word4_INIT_14 : bit_vector(0 to 255) := x"914D85BF85AEF30004BF04AE049D148C2CC42CD52CE62CF7F1A923880E5B940E"; constant PM_Inst_RAM_Word4_INIT_15 : bit_vector(0 to 255) := x"0E5B940E2D082D192D2A2D3B2D932D82F0510571056105511541917C916D915D"; constant PM_Inst_RAM_Word4_INIT_16 : bit_vector(0 to 255) := x"1CB11CA11C911C819408F06123FF85F982B382A28291828085FF85EEF0B92388"; constant PM_Inst_RAM_Word4_INIT_17 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F962FE080C001E081971392BC92AD929D928D2DB32DA2"; constant PM_Inst_RAM_Word4_INIT_18 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF"; constant PM_Inst_RAM_Word4_INIT_19 : bit_vector(0 to 255) := x"9380E0B0E0A0E090E082032692100324921003219210032092109508902F903F"; constant PM_Inst_RAM_Word4_INIT_1A : bit_vector(0 to 255) := x"92100345938003469390E091E081033E9210032A93B0032993A0032893900327"; constant PM_Inst_RAM_Word4_INIT_1B : bit_vector(0 to 255) := x"9380E18A10059380E18910049380E18B95080365921003619380036293900349"; constant PM_Inst_RAM_Word4_INIT_1C : bit_vector(0 to 255) := x"1669940EE070E060E255E840E094E08B20109380E083037E9210037F92101006"; constant PM_Inst_RAM_Word4_INIT_1D : bit_vector(0 to 255) := x"E073E16BE093E287032F940EE14CE061E093E18B1895940EE070E660E094E08B"; constant PM_Inst_RAM_Word4_INIT_1E : bit_vector(0 to 255) := x"E073E267E093E4850D04940EE040E073E16BE093E287F43923880D04940EE041"; constant PM_Inst_RAM_Word4_INIT_1F : bit_vector(0 to 255) := x"E963E094E08BF03123880B3A940EE021E050E848E073E465E093E68107E3940E"; constant PM_Inst_RAM_Word4_INIT_20 : bit_vector(0 to 255) := x"E68120199380037D91800662940EE050E041E073E76DE093E6811895940EE070"; constant PM_Inst_RAM_Word4_INIT_21 : bit_vector(0 to 255) := x"E041E073E76DE093E68120189380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_22 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120179380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_23 : bit_vector(0 to 255) := x"E68120159380037D91800662940EE050E041E073E76DE093E68120169380037D"; constant PM_Inst_RAM_Word4_INIT_24 : bit_vector(0 to 255) := x"E041E073E76DE093E68120149380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_25 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120139380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_26 : bit_vector(0 to 255) := x"E68120219380037D91800662940EE050E041E073E76DE093E68120129380037D"; constant PM_Inst_RAM_Word4_INIT_27 : bit_vector(0 to 255) := x"E041E073E76DE093E68120209380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_28 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201F9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_29 : bit_vector(0 to 255) := x"E681201D9380037D91800662940EE050E041E073E76DE093E681201E9380037D"; constant PM_Inst_RAM_Word4_INIT_2A : bit_vector(0 to 255) := x"E041E073E76DE093E681201C9380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_2B : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201B9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_2C : bit_vector(0 to 255) := x"E68120299380037D91800662940EE050E041E073E76DE093E681201A9380037D"; constant PM_Inst_RAM_Word4_INIT_2D : bit_vector(0 to 255) := x"E041E073E76DE093E68120289380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_2E : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120279380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_2F : bit_vector(0 to 255) := x"E68120259380037D91800662940EE050E041E073E76DE093E68120269380037D"; constant PM_Inst_RAM_Word4_INIT_30 : bit_vector(0 to 255) := x"E041E073E76DE093E68120249380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_31 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120239380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_32 : bit_vector(0 to 255) := x"E68120319380037D91800662940EE050E041E073E76DE093E68120229380037D"; constant PM_Inst_RAM_Word4_INIT_33 : bit_vector(0 to 255) := x"E041E073E76DE093E68120309380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_34 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202F9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_35 : bit_vector(0 to 255) := x"E681202D9380037D91800662940EE050E041E073E76DE093E681202E9380037D"; constant PM_Inst_RAM_Word4_INIT_36 : bit_vector(0 to 255) := x"E041E073E76DE093E681202C9380037D91800662940EE050E041E073E76DE093"; constant PM_Inst_RAM_Word4_INIT_37 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202B9380037D91800662940EE050"; constant PM_Inst_RAM_Word4_INIT_38 : bit_vector(0 to 255) := x"E070EA65E094E08BF43031802F18931F95080573940EE093E681202A9380037D"; constant PM_Inst_RAM_Word4_INIT_39 : bit_vector(0 to 255) := x"972BB7DEB7CD93CF93DF9508911F1876940EE050E1402F61E094E08B1757940E"; constant PM_Inst_RAM_Word4_INIT_3A : bit_vector(0 to 255) := x"037E9210037F9210C175F0099706037F9190037E9180BFCDBE0FBFDE94F8B60F"; constant PM_Inst_RAM_Word4_INIT_3B : bit_vector(0 to 255) := x"2F5D2F4CE073E465E093E681F7E15081920D9001E08BE0F0E8E896112FBD2FAC"; constant PM_Inst_RAM_Word4_INIT_3C : bit_vector(0 to 255) := x"940EE093E681201891600AC1940EE093E681201991600B3A940EE5224F5F5F4F"; constant PM_Inst_RAM_Word4_INIT_3D : bit_vector(0 to 255) := x"E681201591600AC1940EE093E681201691600AC1940EE093E681201791600AC1"; constant PM_Inst_RAM_Word4_INIT_3E : bit_vector(0 to 255) := x"91600AC1940EE093E681201391600AC1940EE093E681201491600AC1940EE093"; constant PM_Inst_RAM_Word4_INIT_3F : bit_vector(0 to 255) := x"940EE093E681202091600AC1940EE093E681202191600AC1940EE093E6812012"; -- BRAM 0 in address space [0x00002800:0x00002FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word5 LOC = RAMB16_X0Y7; constant PM_Inst_RAM_Word5_INIT_00 : bit_vector(0 to 255) := x"E681201D91600AC1940EE093E681201E91600AC1940EE093E681201F91600AC1"; constant PM_Inst_RAM_Word5_INIT_01 : bit_vector(0 to 255) := x"91600AC1940EE093E681201B91600AC1940EE093E681201C91600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_02 : bit_vector(0 to 255) := x"940EE093E681202891600AC1940EE093E681202991600AC1940EE093E681201A"; constant PM_Inst_RAM_Word5_INIT_03 : bit_vector(0 to 255) := x"E681202591600AC1940EE093E681202691600AC1940EE093E681202791600AC1"; constant PM_Inst_RAM_Word5_INIT_04 : bit_vector(0 to 255) := x"91600AC1940EE093E681202391600AC1940EE093E681202491600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_05 : bit_vector(0 to 255) := x"940EE093E681203091600AC1940EE093E681203191600AC1940EE093E6812022"; constant PM_Inst_RAM_Word5_INIT_06 : bit_vector(0 to 255) := x"E681202D91600AC1940EE093E681202E91600AC1940EE093E681202F91600AC1"; constant PM_Inst_RAM_Word5_INIT_07 : bit_vector(0 to 255) := x"91600AC1940EE093E681202B91600AC1940EE093E681202C91600AC1940EE093"; constant PM_Inst_RAM_Word5_INIT_08 : bit_vector(0 to 255) := x"91801388940E201A91801895940EE070EA67E094E08B0AC1940EE093E681202A"; constant PM_Inst_RAM_Word5_INIT_09 : bit_vector(0 to 255) := x"91801388940E201E91801388940E201D91801388940E201C91801388940E201B"; constant PM_Inst_RAM_Word5_INIT_0A : bit_vector(0 to 255) := x"940EE070EB6CE094E08B1388940E202191801388940E202091801388940E201F"; constant PM_Inst_RAM_Word5_INIT_0B : bit_vector(0 to 255) := x"940E201591801388940E201491801388940E201391801388940E201291801895"; constant PM_Inst_RAM_Word5_INIT_0C : bit_vector(0 to 255) := x"940E201991801388940E201891801388940E201791801388940E201691801388"; constant PM_Inst_RAM_Word5_INIT_0D : bit_vector(0 to 255) := x"91801388940E202B91801388940E202A91801895940EE070ED61E094E08B1388"; constant PM_Inst_RAM_Word5_INIT_0E : bit_vector(0 to 255) := x"91801388940E202F91801388940E202E91801388940E202D91801388940E202C"; constant PM_Inst_RAM_Word5_INIT_0F : bit_vector(0 to 255) := x"940E202291801895940EE070EE65E094E08B1388940E203191801388940E2030"; constant PM_Inst_RAM_Word5_INIT_10 : bit_vector(0 to 255) := x"940E202691801388940E202591801388940E202491801388940E202391801388"; constant PM_Inst_RAM_Word5_INIT_11 : bit_vector(0 to 255) := x"940EE093E6811388940E202991801388940E202891801388940E202791801388"; constant PM_Inst_RAM_Word5_INIT_12 : bit_vector(0 to 255) := x"1591940EE090E080E077ED60037E9380037F93909601037F9190037E91800573"; constant PM_Inst_RAM_Word5_INIT_13 : bit_vector(0 to 255) := x"933F932F2411920FB60F920F921F950891DF91CFBFCDBE0FBFDE94F8B60F962B"; constant PM_Inst_RAM_Word5_INIT_14 : bit_vector(0 to 255) := x"1DA1960103889130038791B0038691A0038591900384918093BF93AF939F938F"; constant PM_Inst_RAM_Word5_INIT_15 : bit_vector(0 to 255) := x"93A00385939003849380038893201DB11DA19601572DF020372D5F2D2F231DB1"; constant PM_Inst_RAM_Word5_INIT_16 : bit_vector(0 to 255) := x"038093801DB11DA19601038391B0038291A00381919003809180038793B00386"; constant PM_Inst_RAM_Word5_INIT_17 : bit_vector(0 to 255) := x"901F900FBE0F900F912F913F918F919F91AF91BF038393B0038293A003819390"; constant PM_Inst_RAM_Word5_INIT_18 : bit_vector(0 to 255) := x"2F952F842F732F62BF8F0387915003869140038591300384912094F8B78F9518"; constant PM_Inst_RAM_Word5_INIT_19 : bit_vector(0 to 255) := x"9160038591500384914094F8B78F2F192F082EF72EE6931F930F92FF92EF9508"; constant PM_Inst_RAM_Word5_INIT_1A : bit_vector(0 to 255) := x"1B84BF2F038791B0038691A0038591900384918094F8B72FBF8F038791700386"; constant PM_Inst_RAM_Word5_INIT_1B : bit_vector(0 to 255) := x"6084B7839478950890EF90FF910F911FF760071B070A06F916E80BB70BA60B95"; constant PM_Inst_RAM_Word5_INIT_1C : bit_vector(0 to 255) := x"BD856082B585BD8F6081B58FBD8E6081B58EBD8E6082B58EBF876081B787BF83"; constant PM_Inst_RAM_Word5_INIT_1D : bit_vector(0 to 255) := x"4F3F56262D9095C82FF92FE84F9F53862F932F82E0302F289508BD856081B585"; constant PM_Inst_RAM_Word5_INIT_1E : bit_vector(0 to 255) := x"95C896312DA095C84FFF59E01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE2"; constant PM_Inst_RAM_Word5_INIT_1F : bit_vector(0 to 255) := x"2F952F84E0502F489508938C2B89918C9508938C23899590918CF42923662DB0"; constant PM_Inst_RAM_Word5_INIT_20 : bit_vector(0 to 255) := x"4F5F56462D9095C82FF92FE84F9F53862F952F842D2095C82FF92FE84F9F5086"; constant PM_Inst_RAM_Word5_INIT_21 : bit_vector(0 to 255) := x"B58FF4213024C004778FB58FF4193023F0B12322F16923332D3095C82FF52FE4"; constant PM_Inst_RAM_Word5_INIT_22 : bit_vector(0 to 255) := x"E0F02FE3BD857D8FB585F4193025C005BF837D8FB783F4213021C00BBD8F7D8F"; constant PM_Inst_RAM_Word5_INIT_23 : bit_vector(0 to 255) := x"9508938C23899590918CF42923662DB095C896312DA095C84FFF58E21FFF0FEE"; constant PM_Inst_RAM_Word5_INIT_24 : bit_vector(0 to 255) := x"91E0B12C93FF93EF939F938F932F2411920FB60F920F921F9508938C2B89918C"; constant PM_Inst_RAM_Word5_INIT_25 : bit_vector(0 to 255) := x"91FF0409939083204FFC57E7E0F0F0311798040A918050E1779F2F9E5FEF0409"; constant PM_Inst_RAM_Word5_INIT_26 : bit_vector(0 to 255) := x"2F242F192F08931F930F92FF92EF9518901F900FBE0F900F912F918F919F91EF"; constant PM_Inst_RAM_Word5_INIT_27 : bit_vector(0 to 255) := x"502118E4940EE090E18EE874E860971590FC90ED96142FB92FA82F572F462F35"; constant PM_Inst_RAM_Word5_INIT_28 : bit_vector(0 to 255) := x"83202DFF2DEE18E4940EE050E040E030E0222F622F732F842F95405040404030"; constant PM_Inst_RAM_Word5_INIT_29 : bit_vector(0 to 255) := x"0F88C002971C900C961C2F952F84E050E0418120971791FC91ED96162FB12FA0"; constant PM_Inst_RAM_Word5_INIT_2A : bit_vector(0 to 255) := x"C002971D900C961D2F952F848120971791FC91ED961683202B28F7E2940A1F99"; constant PM_Inst_RAM_Word5_INIT_2B : bit_vector(0 to 255) := x"1F550F44C002900C961E8180971791FC91ED961683202B28F7E2940A1F990F88"; constant PM_Inst_RAM_Word5_INIT_2C : bit_vector(0 to 255) := x"E090918C852785B185A02FF92FE8950890EF90FF910F911F83802B84F7E2940A"; constant PM_Inst_RAM_Word5_INIT_2D : bit_vector(0 to 255) := x"9390E091E08B950883602DE085F38402CFF6FF80F7E2940A95879595C0022E02"; constant PM_Inst_RAM_Word5_INIT_2E : bit_vector(0 to 255) := x"E28A040F938004109390E090E289040D9380040E9390E093E889040B9380040C"; constant PM_Inst_RAM_Word5_INIT_2F : bit_vector(0 to 255) := x"938004169390E090E28C0413938004149390E090E28B0411938004129390E090"; constant PM_Inst_RAM_Word5_INIT_30 : bit_vector(0 to 255) := x"15BD940E9508041A9380E08504199380E08704189380E08304179380E0840415"; constant PM_Inst_RAM_Word5_INIT_31 : bit_vector(0 to 255) := x"2FA09621C00B2FD72FC62F192F0893DF93CF931F930FCFFD139B940E11B8940E"; constant PM_Inst_RAM_Word5_INIT_32 : bit_vector(0 to 255) := x"910F911F91CF91DFF7912366816895092F912F802DE081F0900191FC91ED2FB1"; constant PM_Inst_RAM_Word5_INIT_33 : bit_vector(0 to 255) := x"2DBF2DAEC0102FD52FC42EF72EE62F192F0893DF93CF931F930F92FF92EF9508"; constant PM_Inst_RAM_Word5_INIT_34 : bit_vector(0 to 255) := x"F7719720972195092F912F802DE081F0900191FC91ED2FB12FA02EFB2EEA916D"; constant PM_Inst_RAM_Word5_INIT_35 : bit_vector(0 to 255) := x"950895092DE081F3800291FC91ED2FB92FA8950890EF90FF910F911F91CF91DF"; constant PM_Inst_RAM_Word5_INIT_36 : bit_vector(0 to 255) := x"931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F"; constant PM_Inst_RAM_Word5_INIT_37 : bit_vector(0 to 255) := x"2EF72EE62ED52EC42E392E28BFCDBE0FBFDE94F8B60F97A0B7DEB7CD93CF93DF"; constant PM_Inst_RAM_Word5_INIT_38 : bit_vector(0 to 255) := x"24992488C06A1821940EE030E020E070E060E050E340F4490571056105511541"; constant PM_Inst_RAM_Word5_INIT_39 : bit_vector(0 to 255) := x"2D6C2D7D2D8E2D9F1D190D081F1D0F0CE010E0012477246624552E4224BB24AA"; constant PM_Inst_RAM_Word5_INIT_3A : bit_vector(0 to 255) := x"2D8E2D9F1CB11CA11C911C81940883602FF12FE018BD940E2D242D352D462D57"; constant PM_Inst_RAM_Word5_INIT_3B : bit_vector(0 to 255) := x"2EFB2EEA2ED92EC82FB52FA42F932F8218BD940E2D242D352D462D572D6C2D7D"; constant PM_Inst_RAM_Word5_INIT_3C : bit_vector(0 to 255) := x"1C6194082E7D2E6C1CF90CE81EFD0EEC2CF12EE8E081F68904F104E104D114C1"; constant PM_Inst_RAM_Word5_INIT_3D : bit_vector(0 to 255) := x"0DEE2DFD2DECC01808D918C82ED92EC809B109A197012D882D992DAA2DBB1C71"; constant PM_Inst_RAM_Word5_INIT_3E : bit_vector(0 to 255) := x"E030E0202D932D822F752F659550FD4727555C49C0015D40F410304A81401DFF"; constant PM_Inst_RAM_Word5_INIT_3F : bit_vector(0 to 255) := x"91DF91CFBFCDBE0FBFDE94F8B60F96A0F729047F146E08F108E194081821940E"; -- BRAM 0 in address space [0x00003000:0x000037FF], bit lane [15:0] -- INST PM_Inst/RAM_Word6 LOC = RAMB16_X0Y5; constant PM_Inst_RAM_Word6_INIT_00 : bit_vector(0 to 255) := x"902F903F904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F"; constant PM_Inst_RAM_Word6_INIT_01 : bit_vector(0 to 255) := x"1760940E950895092F642DE081F0900191FC91EDF441053115212FB92FA89508"; constant PM_Inst_RAM_Word6_INIT_02 : bit_vector(0 to 255) := x"F441053115212F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF9508"; constant PM_Inst_RAM_Word6_INIT_03 : bit_vector(0 to 255) := x"E060E050E24DC010FF77F4C90531302AC01E95092F642DE081F0900181F981E8"; constant PM_Inst_RAM_Word6_INIT_04 : bit_vector(0 to 255) := x"2F712F9D2F8C1D111D011CF11CE194E094F0950095101821940EE030E020E070"; constant PM_Inst_RAM_Word6_INIT_05 : bit_vector(0 to 255) := x"2F08931F930F950890EF90FF910F911F91CF91DF1760940EE02A2D4E2D5F2F60"; constant PM_Inst_RAM_Word6_INIT_06 : bit_vector(0 to 255) := x"E020E070E060E050E04A2F912F801821940EE030E020E070E060E050E04D2F19"; constant PM_Inst_RAM_Word6_INIT_07 : bit_vector(0 to 255) := x"2F352F242F192F08931F930F92FF92EF92DF92CF9508910F911F1821940EE030"; constant PM_Inst_RAM_Word6_INIT_08 : bit_vector(0 to 255) := x"910F911F185D940E2F912F801811940E2D4C2D5D2D6E2D7F24FF24EE24DD2EC6"; constant PM_Inst_RAM_Word6_INIT_09 : bit_vector(0 to 255) := x"911F185D940E2F912F801757940E2F192F08931F930F950890CF90DF90EF90FF"; constant PM_Inst_RAM_Word6_INIT_0A : bit_vector(0 to 255) := x"1F551F441F330F221FF51FE41FB30FA2C004FF6027AA27BB27EE27FF9508910F"; constant PM_Inst_RAM_Word6_INIT_0B : bit_vector(0 to 255) := x"1BAA2E1AE2A195082F6A2F7B2F8E2F9FF77107769700F7899567957795879596"; constant PM_Inst_RAM_Word6_INIT_0C : bit_vector(0 to 255) := x"0BE40BB31BA2F02007F507E407B317A21FFF1FEE1FBB1FAAC00D2FFB2FEA1BBB"; constant PM_Inst_RAM_Word6_INIT_0D : bit_vector(0 to 255) := x"2F6A2F592F482F372F269590958095709560F769941A1F991F881F771F660BF5"; constant PM_Inst_RAM_Word6_INIT_0E : bit_vector(0 to 255) := x"95409550F4381C00D00ADFD2D004FD57D00E26052E09FB9795082F9F2F8E2F7B"; constant PM_Inst_RAM_Word6_INIT_0F : bit_vector(0 to 255) := x"0FEE95084F9F4F8F4F7F9561957095809590F7F695084F5F4F4F4F3F95219530"; constant PM_Inst_RAM_Word6_INIT_10 : bit_vector(0 to 255) := x"6944205241542073692073696854CFFF94F89508920F95C8920F963195C81FFF"; constant PM_Inst_RAM_Word6_INIT_11 : bit_vector(0 to 255) := x"50554B43414200656369766564207265746E756F63206C616E6769732065646F"; constant PM_Inst_RAM_Word6_INIT_12 : bit_vector(0 to 255) := x"632065746972570030005458542E50554B4341422064656E65704F005458542E"; constant PM_Inst_RAM_Word6_INIT_13 : bit_vector(0 to 255) := x"552D3770557265746E756F6320657469725700306E442D376E447265746E756F"; constant PM_Inst_RAM_Word6_INIT_14 : bit_vector(0 to 255) := x"63695420657469725700306E442D376E4472656B636954206574697257003070"; constant PM_Inst_RAM_Word6_INIT_15 : bit_vector(0 to 255) := x"1516C90000000017310AB20AC100000000FFFFFFFF003070552D37705572656B"; constant PM_Inst_RAM_Word6_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000173117"; constant PM_Inst_RAM_Word6_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word6_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; -- BRAM 0 in address space [0x00003800:0x00003FFF], bit lane [15:0] -- INST PM_Inst/RAM_Word7 LOC = RAMB16_X0Y6; constant PM_Inst_RAM_Word7_INIT_00 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_01 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_02 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_03 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_04 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_05 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_06 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_07 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_09 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_0F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_10 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_11 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_12 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_13 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_14 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_15 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; constant PM_Inst_RAM_Word7_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000"; end prog_mem_init_pkg;

apache-2.0

bd07f99fabd0aae6567298d78217d74c

0.808908

2.441144

false

jairov4/accel-oil

solution_kintex7/sim/vhdl/sample_iterator_next.vhd

1

23,318

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end; architecture behav of sample_iterator_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0); signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_1_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_1_reg_151 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_2_fu_89_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_156 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_fu_95_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_4_reg_162 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_fu_100_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_reg_167 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_cast_12_fu_74_p1 : STD_LOGIC_VECTOR (16 downto 0); signal tmp_cast_fu_83_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_2_fu_89_p1 : STD_LOGIC_VECTOR (17 downto 0); signal tmp_1_reg_151_temp: signed (17-1 downto 0); signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0); signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134; ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1; ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2; ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3; ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4; ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5; ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6; ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128; ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1; ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2; ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3; ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4; ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_index_read_reg_134 <= i_index; i_sample_read_reg_128 <= i_sample; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_addr_read_reg_146 <= indices_samples_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then tmp_1_reg_151 <= tmp_1_fu_77_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then tmp_2_reg_156 <= tmp_2_fu_89_p2; tmp_3_reg_167 <= tmp_3_fu_100_p2; tmp_4_reg_162 <= tmp_4_fu_95_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; agg_result_index_write_assign_fu_111_p3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7 when (tmp_2_reg_156(0) = '1') else tmp_4_reg_162; agg_result_sample_write_assign_fu_105_p3 <= tmp_3_reg_167 when (tmp_2_reg_156(0) = '1') else ap_const_lv16_0; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it8, indices_samples_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it8) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return_0 <= agg_result_index_write_assign_fu_111_p3; ap_return_1 <= agg_result_sample_write_assign_fu_105_p3; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; indices_begin_address <= ap_const_lv32_0; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; indices_begin_req_write <= ap_const_logic_0; indices_begin_rsp_read <= ap_const_logic_0; indices_begin_size <= ap_const_lv32_0; indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0); indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_req_write <= ap_const_logic_1; else indices_samples_req_write <= ap_const_logic_0; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_samples_rsp_read <= ap_const_logic_1; else indices_samples_rsp_read <= ap_const_logic_0; end if; end process; indices_samples_size <= ap_const_lv32_1; indices_stride_address <= ap_const_lv32_0; indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; indices_stride_req_write <= ap_const_logic_0; indices_stride_rsp_read <= ap_const_logic_0; indices_stride_size <= ap_const_lv32_0; tmp_1_fu_77_p2 <= std_logic_vector(unsigned(tmp_cast_12_fu_74_p1) + unsigned(ap_const_lv17_1FFFF)); tmp_1_reg_151_temp <= signed(tmp_1_reg_151); tmp_2_fu_89_p1 <= std_logic_vector(resize(tmp_1_reg_151_temp,18)); tmp_2_fu_89_p2 <= "1" when (signed(tmp_cast_fu_83_p1) < signed(tmp_2_fu_89_p1)) else "0"; tmp_3_fu_100_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it6) + unsigned(ap_const_lv16_1)); tmp_4_fu_95_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_index_read_reg_134_pp0_it6) + unsigned(ap_const_lv16_1)); tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64)); tmp_cast_12_fu_74_p1 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17)); tmp_cast_fu_83_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it6),18)); end behav;

lgpl-3.0

f6e0ac9c8907e30740b20f1033f6cc28

0.607899

2.717399

false

jairov4/accel-oil

impl/impl_test_single/hdl/system_proc_sys_reset_0_wrapper.vhd

2

4,214

------------------------------------------------------------------------------- -- system_proc_sys_reset_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library proc_sys_reset_v3_00_a; use proc_sys_reset_v3_00_a.all; entity system_proc_sys_reset_0_wrapper is port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to 0); Peripheral_Reset : out std_logic_vector(0 to 0); Interconnect_aresetn : out std_logic_vector(0 to 0); Peripheral_aresetn : out std_logic_vector(0 to 0) ); attribute x_core_info : STRING; attribute x_core_info of system_proc_sys_reset_0_wrapper : entity is "proc_sys_reset_v3_00_a"; end system_proc_sys_reset_0_wrapper; architecture STRUCTURE of system_proc_sys_reset_0_wrapper is component proc_sys_reset is generic ( C_EXT_RST_WIDTH : integer; C_AUX_RST_WIDTH : integer; C_EXT_RESET_HIGH : std_logic; C_AUX_RESET_HIGH : std_logic; C_NUM_BUS_RST : integer; C_NUM_PERP_RST : integer; C_NUM_INTERCONNECT_ARESETN : integer; C_NUM_PERP_ARESETN : integer ); port ( Slowest_sync_clk : in std_logic; Ext_Reset_In : in std_logic; Aux_Reset_In : in std_logic; MB_Debug_Sys_Rst : in std_logic; Core_Reset_Req_0 : in std_logic; Chip_Reset_Req_0 : in std_logic; System_Reset_Req_0 : in std_logic; Core_Reset_Req_1 : in std_logic; Chip_Reset_Req_1 : in std_logic; System_Reset_Req_1 : in std_logic; Dcm_locked : in std_logic; RstcPPCresetcore_0 : out std_logic; RstcPPCresetchip_0 : out std_logic; RstcPPCresetsys_0 : out std_logic; RstcPPCresetcore_1 : out std_logic; RstcPPCresetchip_1 : out std_logic; RstcPPCresetsys_1 : out std_logic; MB_Reset : out std_logic; Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1); Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1); Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1); Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1) ); end component; begin proc_sys_reset_0 : proc_sys_reset generic map ( C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '1', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) port map ( Slowest_sync_clk => Slowest_sync_clk, Ext_Reset_In => Ext_Reset_In, Aux_Reset_In => Aux_Reset_In, MB_Debug_Sys_Rst => MB_Debug_Sys_Rst, Core_Reset_Req_0 => Core_Reset_Req_0, Chip_Reset_Req_0 => Chip_Reset_Req_0, System_Reset_Req_0 => System_Reset_Req_0, Core_Reset_Req_1 => Core_Reset_Req_1, Chip_Reset_Req_1 => Chip_Reset_Req_1, System_Reset_Req_1 => System_Reset_Req_1, Dcm_locked => Dcm_locked, RstcPPCresetcore_0 => RstcPPCresetcore_0, RstcPPCresetchip_0 => RstcPPCresetchip_0, RstcPPCresetsys_0 => RstcPPCresetsys_0, RstcPPCresetcore_1 => RstcPPCresetcore_1, RstcPPCresetchip_1 => RstcPPCresetchip_1, RstcPPCresetsys_1 => RstcPPCresetsys_1, MB_Reset => MB_Reset, Bus_Struct_Reset => Bus_Struct_Reset, Peripheral_Reset => Peripheral_Reset, Interconnect_aresetn => Interconnect_aresetn, Peripheral_aresetn => Peripheral_aresetn ); end architecture STRUCTURE;

lgpl-3.0

a73f5a5120add593704a0fea0956ff6b

0.616991

3.299922

false

grwlf/vsim

vhdl_ct/ct00459.vhd

1

2,269

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00459 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00459) -- ENT00459_Test_Bench(ARCH00459_Test_Bench) -- -- REVISION HISTORY: -- -- 4-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES ; use WORK.ARITHMETIC.all ; architecture ARCH00459 of E00000 is begin process subtype st_int1 is integer range -100 to 1000 ; subtype st_int2 is integer range 0 downto -100 ; subtype st_phys1 is t_phys range (-2**20) * ones to (2**20) * ones ; subtype st_phys2 is t_phys range (-2**20) * ones to (2**20) * ones ; subtype st_real1 is real range 0.0 to 10.0 ; subtype st_real2 is real range -10.0 to -1.0 ; variable v_int1 : st_int1 := 49 ; variable v_int2 : st_int2 := -2 ; variable v_phys1 : st_phys1 := 2 tens ; variable v_phys2 : st_phys2 := 10 ones ; variable v_real1 : st_real1 := 9.0 ; variable v_real2 : st_real2 := -6.0 ; variable bool : boolean := true ; begin bool := bool and v_int1 mod v_int2 = -1 ; bool := bool and v_int1 rem v_int2 = 1 ; bool := bool and v_int1 * v_int2 = -98 ; bool := bool and abs (v_real1 * v_real2 - (-54.0)) < acceptable_error ; -- bool := bool and v_int1 / v_int2 = -24 ; bool := bool and v_phys1 / v_phys2 = 2 ; bool := bool and abs (v_real1 / v_real2 - (-1.5)) < acceptable_error ; STANDARD_TYPES.test_report ( "ARCH00459" , "Operands of multiplying operators may have different" & " subtypes" , bool ) ; wait ; end process ; end ARCH00459 ; entity ENT00459_Test_Bench is end ENT00459_Test_Bench ; architecture ARCH00459_Test_Bench of ENT00459_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00459 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00459_Test_Bench ;

gpl-3.0

bb99b45cb0d9822f2bccf863eec82344

0.539885

3.283647

false

true

false

grwlf/vsim

vhdl_ct/ct00498.vhd

1

10,904

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00498 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (7) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00498(ARCH00498) -- ENT00498_Test_Bench(ARCH00498_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00498 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00498 ; -- architecture ARCH00498 of ENT00498 is begin B1 : block procedure p1 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- variable v_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; variable v_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; variable v_bit_vector : st_bit_vector := ( others => '0' ) ; variable v_string : st_string := ( others => 'a' ) ; variable v_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; constant c_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; constant c_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; constant c_bit_vector : st_bit_vector := ( others => '0' ) ; constant c_string : st_string := ( others => 'a' ) ; constant c_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; variable bool : boolean := true; -- begin for i in 1 to 5 loop bool := bool and c_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and c_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and c_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and c_bit_vector = B"00000" ; -- bool := bool and c_string = "aaa" ; -- bool := bool and c_rec_1.f1 = 0 and c_rec_1.f4 = 0 and c_rec_1.f3 = 0 ; -- bool := bool and c_rec_1.f2(1) = false -- and c_rec_1.f2(0) = false and -- c_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in constant declaration" & " (dynamic)" , bool ) ; -- bool := true; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in variable declaration" & " (dynamic)" , bool ) ; end p1 ; -- begin process variable v_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; variable v_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; variable v_bit_vector : st_bit_vector := ( others => '0' ) ; variable v_string : st_string := ( others => 'a' ) ; variable v_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; constant c_arr_1 : st_arr_1 := ( others => (others => c_rec_1_1) ) ; constant c_time_matrix : st_time_matrix := ( others => (others => 15ms) ) ; constant c_bit_vector : st_bit_vector := ( others => '0' ) ; constant c_string : st_string := ( others => 'a' ) ; constant c_rec_1 : rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; variable bool : boolean := true; -- begin for i in 1 to 5 loop bool := bool and c_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and c_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and c_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and c_bit_vector = B"00000" ; -- bool := bool and c_string = "aaa" ; -- bool := bool and c_rec_1.f1 = 0 and c_rec_1.f4 = 0 and c_rec_1.f3 = 0 ; -- bool := bool and c_rec_1.f2(1) = false -- and c_rec_1.f2(0) = false and -- c_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in constant declaration" & " (globally static)" , bool ) ; -- bool := true; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00498" , "Aggregates with others choice in variable declaration" & " (globally static)" , bool ) ; p1 ( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; wait ; end process ; end block B1 ; end ARCH00498 ; -- entity ENT00498_Test_Bench is end ENT00498_Test_Bench ; -- architecture ARCH00498_Test_Bench of ENT00498_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00498 ( ARCH00498 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00498_Test_Bench ;

gpl-3.0

f592d08c8728b63a34294e82b955aa11

0.460932

3.339663

false

grwlf/vsim

vhdl_ct/ct00018.vhd

1

8,897

-- NEED RESULT: ARCH00018: Wait in P1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in P2_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P2_2 did resume passed -- NEED RESULT: ARCH00018: Wait in P3_1 did resume passed -- NEED RESULT: ARCH00018: Wait in P3_2 did resume passed -- NEED RESULT: ARCH00018: Wait in R1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in R1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC1_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC1_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC2_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC2_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC3_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC3_2 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC4_1 did resume passed -- NEED RESULT: ARCH00018: Wait in PROC4_2 did resume passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00018 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.1 (8) -- -- DESIGN UNIT ORDERING: -- -- ENT00018(ARCH00018) -- ENT00018_Test_Bench(ARCH00018_Test_Bench) -- -- REVISION HISTORY: -- -- 26-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00018 is generic ( G1 : Time := 10 ns ) ; port ( P1 : in Time := 10 ns ) ; end ENT00018 ; architecture ARCH00018 of ENT00018 is signal Num_Cycles : Integer := 0 ; signal Dummy_Cond : Boolean := false ; signal P1_1_Did_Resume, P1_2_Did_Resume : Boolean := false ; signal P2_1_Did_Resume, P2_2_Did_Resume : Boolean := false ; signal P3_1_Did_Resume, P3_2_Did_Resume : Boolean := false ; signal R1_1_Did_Resume, R1_2_Did_Resume : Boolean := false ; signal PROC1_1_Did_Resume, PROC1_2_Did_Resume : Boolean := false ; signal PROC2_1_Did_Resume, PROC2_2_Did_Resume : Boolean := false ; signal PROC3_1_Did_Resume, PROC3_2_Did_Resume : Boolean := false ; signal PROC4_1_Did_Resume, PROC4_2_Did_Resume : Boolean := false ; constant Time_To_Wait : Time := 10 ns ; procedure PROC1_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static Resume_Chk <= transport True ; end PROC1_1 ; procedure PROC1_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static Resume_Chk <= transport True ; end PROC1_2 ; procedure PROC2_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static Resume_Chk <= transport True ; end PROC2_1 ; procedure PROC2_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for G1 ; -- Globally Static Resume_Chk <= transport True ; end PROC2_2 ; procedure PROC3_1 ( Signal Resume_Chk : inout boolean ) is begin wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic Resume_Chk <= transport True ; end PROC3_1 ; procedure PROC3_2 ( Signal Resume_Chk : inout boolean ) is begin wait until (Num_Cycles = 1000) for P1 ; -- Dynamic Resume_Chk <= transport True ; end PROC3_2 ; procedure PROC4_1 (Time_To_Wait : Time; Signal Resume_Chk : inout boolean) is begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; Resume_Chk <= transport True ; end PROC4_1 ; procedure PROC4_2 (Time_To_Wait : Time; Signal Resume_Chk : inout boolean) is begin wait until (Num_Cycles = 1000) for Time_To_Wait ; Resume_Chk <= transport True ; end PROC4_2 ; begin Test_Control : process ( Num_Cycles ) begin if Num_Cycles < 9 then Num_Cycles <= transport Num_Cycles + 1 after 1 ns ; elsif Num_Cycles = 9 then -- Verify that in fact, none of the wait statements resumed test_report ( "ARCH00018" , "Wait in P1_1 did resume" , Not P1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P1_2 did resume" , Not P1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P2_1 did resume" , Not P2_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P2_2 did resume" , Not P2_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P3_1 did resume" , Not P3_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in P3_2 did resume" , Not P3_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in R1_1 did resume" , Not R1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in R1_2 did resume" , Not R1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC1_1 did resume" , Not PROC1_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC1_2 did resume" , Not PROC1_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC2_1 did resume" , Not PROC2_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC2_2 did resume" , Not PROC2_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC3_1 did resume" , Not PROC3_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC3_2 did resume" , Not PROC3_2_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC4_1 did resume" , Not PROC4_1_Did_Resume ) ; test_report ( "ARCH00018" , "Wait in PROC4_2 did resume" , Not PROC4_2_Did_Resume ) ; end if ; end process Test_Control ; P1_1 : process begin wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static P1_1_Did_Resume <= transport True ; wait; end process P1_1 ; P1_2 : process begin wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static P1_2_Did_Resume <= transport True ; wait; end process P1_2 ; P2_1 : process begin wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static P2_1_Did_Resume <= transport True ; wait; end process P2_1 ; P2_2 : process begin wait until (Num_Cycles = 1000) for G1 ; -- Globally Static P2_2_Did_Resume <= transport True ; wait; end process P2_2 ; P3_1 : process begin wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic P3_1_Did_Resume <= transport True ; wait; end process P3_1 ; P3_2 : process begin wait until (Num_Cycles = 1000) for P1 ; -- Dynamic P3_2_Did_Resume <= transport True ; wait; end process P3_2 ; Q1_1 : process begin PROC1_1 (PROC1_1_Did_Resume) ; wait; end process Q1_1 ; Q1_2 : process begin PROC1_2 (PROC1_2_Did_Resume) ; wait; end process Q1_2 ; Q2_1 : process begin PROC2_1 (PROC2_1_Did_Resume) ; wait; end process Q2_1 ; Q2_2 : process begin PROC2_2 (PROC2_2_Did_Resume) ; wait; end process Q2_2 ; Q3_1 : process begin PROC3_1 (PROC3_1_Did_Resume) ; wait; end process Q3_1 ; Q3_2 : process begin PROC3_2 (PROC3_2_Did_Resume) ; wait; end process Q3_2 ; Q4_1 : process begin PROC4_1 (Time_To_Wait, PROC4_1_Did_Resume) ; wait; end process Q4_1 ; Q4_2 : process begin PROC4_2 (P1, PROC4_2_Did_Resume) ; wait; end process Q4_2 ; R1_1 : process begin wait on Num_Cycles until Dummy_Cond ; -- No Time R1_1_Did_Resume <= transport True ; wait; end process R1_1 ; R1_2 : process begin wait until (Num_Cycles = 1000) ; -- No Time R1_2_Did_Resume <= transport True ; wait; end process R1_2 ; end ARCH00018 ; entity ENT00018_Test_Bench is end ENT00018_Test_Bench ; architecture ARCH00018_Test_Bench of ENT00018_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00018 ( ARCH00018 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00018_Test_Bench ;

gpl-3.0

f769c560579445752bc82f35311d4c36

0.562886

3.370076

false

true

false

dcliche/mdsynth

rtl/src/acia6850.vhd

1

34,541

--===========================================================================-- -- -- -- Synthesizable 6850 compatible ACIA -- -- -- --===========================================================================-- -- -- File name : acia6850.vhd -- -- Entity name : acia6850 -- -- Purpose : Implements a RS232 6850 compatible -- Asynchronous Communications Interface Adapter (ACIA) -- -- Dependencies : ieee.std_logic_1164 -- ieee.numeric_std -- ieee.std_logic_unsigned -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- Origins : miniUART written by Ovidiu Lupas [email protected] -- -- Registers : -- -- IO address + 0 Read - Status Register -- -- Bit[7] - Interrupt Request Flag -- Bit[6] - Receive Parity Error (parity bit does not match) -- Bit[5] - Receive Overrun Error (new character received before last read) -- Bit[4] - Receive Framing Error (bad stop bit) -- Bit[3] - Clear To Send level -- Bit[2] - Data Carrier Detect (lost modem carrier) -- Bit[1] - Transmit Buffer Empty (ready to accept next transmit character) -- Bit[0] - Receive Data Ready (character received) -- -- IO address + 0 Write - Control Register -- -- Bit[7] - Rx Interupt Enable -- 0 - disabled -- 1 - enabled -- Bits[6..5] - Transmit Control -- 0 0 - TX interrupt disabled, RTS asserted -- 0 1 - TX interrupt enabled, RTS asserted -- 1 0 - TX interrupt disabled, RTS cleared -- 1 1 - TX interrupt disabled, RTS asserted, Send Break -- Bits[4..2] - Word Control -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop -- Bits[1..0] - Baud Control -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - Reset -- -- IO address + 1 Read - Receive Data Register -- -- Read when Receive Data Ready bit set -- Read resets Receive Data Ready bit -- -- IO address + 1 Write - Transmit Data Register -- -- Write when Transmit Buffer Empty bit set -- Write resets Transmit Buffer Empty Bit -- -- -- Copyright (C) 2002 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Changes -- -- 0.1 Ovidiu Lupas 2000-01-15 New model -- 1.0 Ovidiu Lupas 2000-01 Synthesis optimizations -- 2.0 Ovidiu Lupas 2000-04 Bugs removed - the RSBusCtrl did not -- process all possible situations -- -- 3.0 John Kent 2002-10 Changed Status bits to match MC6805 -- Added CTS, RTS, Baud rate control & Software Reset -- 3.1 John Kent 2003-01-05 Added Word Format control a'la mc6850 -- 3.2 John Kent 2003-07-19 Latched Data input to UART -- 3.3 John Kent 2004-01-16 Integrated clkunit in rxunit & txunit -- TX / RX Baud Clock now external -- also supports x1 clock and DCD. -- 3.4 John Kent 2005-09-13 Removed LoadCS signal. -- Fixed ReadCS and Read -- in miniuart_DCD_Init process -- 3.5 John Kent 2006-11-28 Cleaned up code. -- -- 4.0 John Kent 2007-02-03 Renamed ACIA6850 -- 4.1 John Kent 2007-02-06 Made software reset synchronous -- 4.2 John Kent 2007-02-25 Changed sensitivity lists -- Rearranged Reset process. -- 4.3 John Kent 2010-06-17 Updated header -- 4.4 John Kent 2010-08-27 Combined with ACIA_RX & ACIA_TX -- Renamed to acia6850 -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; --library unisim; -- use unisim.vcomponents.all; ----------------------------------------------------------------------- -- Entity for ACIA_6850 -- ----------------------------------------------------------------------- entity acia6850 is port ( -- -- CPU Interface signals -- clk : in std_logic; -- System Clock rst : in std_logic; -- Reset input (active high) cs : in std_logic; -- miniUART Chip Select addr : in std_logic; -- Register Select rw : in std_logic; -- Read / Not Write data_in : in std_logic_vector(7 downto 0); -- Data Bus In data_out : out std_logic_vector(7 downto 0); -- Data Bus Out irq : out std_logic; -- Interrupt Request out -- -- RS232 Interface Signals -- RxC : in std_logic; -- Receive Baud Clock TxC : in std_logic; -- Transmit Baud Clock RxD : in std_logic; -- Receive Data TxD : out std_logic; -- Transmit Data DCD_n : in std_logic; -- Data Carrier Detect CTS_n : in std_logic; -- Clear To Send RTS_n : out std_logic -- Request To send ); end acia6850; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for ACIA_6850 Interface registees ------------------------------------------------------------------------------- architecture rtl of acia6850 is type DCD_State_Type is (DCD_State_Idle, DCD_State_Int, DCD_State_Reset); ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- -- -- Reset signals -- signal ac_rst : std_logic; -- Reset (Software & Hardware) signal rx_rst : std_logic; -- Receive Reset (Software & Hardware) signal tx_rst : std_logic; -- Transmit Reset (Software & Hardware) -------------------------------------------------------------------- -- Status Register: StatReg ---------------------------------------------------------------------- -- -- IO address + 0 Read -- -----------+--------+-------+--------+--------+--------+--------+--------+ -- Irq | PErr | OErr | FErr | CTS | DCD | TxRdy | RxRdy | -----------+--------+-------+--------+--------+--------+--------+--------+ -- -- Irq - Bit[7] - Interrupt request -- PErr - Bit[6] - Receive Parity error (parity bit does not match) -- OErr - Bit[5] - Receive Overrun error (new character received before last read) -- FErr - Bit[4] - Receive Framing Error (bad stop bit) -- CTS - Bit[3] - Clear To Send level -- DCD - Bit[2] - Data Carrier Detect (lost modem carrier) -- TxRdy - Bit[1] - Transmit Buffer Empty (ready to accept next transmit character) -- RxRdy - Bit[0] - Receive Data Ready (character received) -- signal StatReg : std_logic_vector(7 downto 0) := (others => '0'); -- status register ---------------------------------------------------------------------- -- Control Register: CtrlReg ---------------------------------------------------------------------- -- -- IO address + 0 Write -- -----------+--------+--------+--------+--------+--------+--------+--------+ -- RxIE |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)| -----------+--------+--------+--------+--------+--------+--------+--------+ -- RxIEnb - Bit[7] -- 0 - Rx Interrupt disabled -- 1 - Rx Interrupt enabled -- TxCtl - Bits[6..5] -- 0 1 - Tx Interrupt Enable -- 1 0 - RTS high -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop -- BdCtl - Bits[1..0] -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - reset signal CtrlReg : std_logic_vector(7 downto 0) := (others => '0'); -- control register ---------------------------------------------------------------------- -- Receive Register ---------------------------------------------------------------------- -- -- IO address + 1 Read -- signal RxReg : std_logic_vector(7 downto 0) := (others => '0'); ---------------------------------------------------------------------- -- Transmit Register ---------------------------------------------------------------------- -- -- IO address + 1 Write -- signal TxReg : std_logic_vector(7 downto 0) := (others => '0'); signal TxDat : std_logic := '1'; -- Transmit data bit signal TxRdy : std_logic := '0'; -- Transmit buffer empty signal RxRdy : std_logic := '0'; -- Receive Data ready -- signal FErr : std_logic := '0'; -- Frame error signal OErr : std_logic := '0'; -- Output error signal PErr : std_logic := '0'; -- Parity Error -- signal TxIE : std_logic := '0'; -- Transmit interrupt enable signal RxIE : std_logic := '0'; -- Receive interrupt enable -- signal RxRd : std_logic := '0'; -- Read receive buffer signal TxWr : std_logic := '0'; -- Write Transmit buffer signal StRd : std_logic := '0'; -- Read status register -- signal DCDState : DCD_State_Type; -- DCD Reset state sequencer signal DCDDel : std_logic := '0'; -- Delayed DCD_n signal DCDEdge : std_logic := '0'; -- Rising DCD_N Edge Pulse signal DCDInt : std_logic := '0'; -- DCD Interrupt signal BdFmt : std_logic_vector(1 downto 0) := "00"; -- Baud Clock Format signal WdFmt : std_logic_vector(2 downto 0) := "000"; -- Data Word Format ----------------------------------------------------------------------------- -- RX Signals ----------------------------------------------------------------------------- type RxStateType is ( RxState_Wait, RxState_Data, RxState_Parity, RxState_Stop ); signal RxState : RxStateType; -- receive bit state signal RxDatDel0 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatDel1 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatDel2 : Std_Logic := '0'; -- Delayed Rx Data signal RxDatEdge : Std_Logic := '0'; -- Rx Data Edge pulse signal RxClkDel : Std_Logic := '0'; -- Delayed Rx Input Clock signal RxClkEdge : Std_Logic := '0'; -- Rx Input Clock Edge pulse signal RxStart : Std_Logic := '0'; -- Rx Start request signal RxEnable : Std_Logic := '0'; -- Rx Enabled signal RxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Rx Baud Clock Counter signal RxBdClk : Std_Logic := '0'; -- Rx Baud Clock signal RxBdDel : Std_Logic := '0'; -- Delayed Rx Baud Clock signal RxReq : Std_Logic := '0'; -- Rx Data Valid signal RxAck : Std_Logic := '0'; -- Rx Data Valid signal RxParity : Std_Logic := '0'; -- Calculated RX parity bit signal RxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Rx Bit counter signal RxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Shift Register ----------------------------------------------------------------------------- -- TX Signals ----------------------------------------------------------------------------- type TxStateType is ( TxState_Idle, TxState_Start, TxState_Data, TxState_Parity, TxState_Stop ); signal TxState : TxStateType; -- Transmitter state signal TxClkDel : Std_Logic := '0'; -- Delayed Tx Input Clock signal TxClkEdge : Std_Logic := '0'; -- Tx Input Clock Edge pulse signal TxClkCnt : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Tx Baud Clock Counter signal TxBdClk : Std_Logic := '0'; -- Tx Baud Clock signal TxBdDel : Std_Logic := '0'; -- Delayed Tx Baud Clock signal TxReq : std_logic := '0'; -- Request transmit start signal TxAck : std_logic := '0'; -- Acknowledge transmit start signal TxParity : Std_logic := '0'; -- Parity Bit signal TxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Data Bit Counter signal TxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Transmit shift register begin --------------------------------------------------------------- -- ACIA Reset may be hardware or software --------------------------------------------------------------- acia_reset : process( clk, rst, ac_rst, dcd_n ) begin -- -- ACIA reset Synchronous -- Includes software reset -- if falling_edge(clk) then ac_rst <= (CtrlReg(1) and CtrlReg(0)) or rst; end if; -- Receiver reset rx_rst <= ac_rst or DCD_n; -- Transmitter reset tx_rst <= ac_rst; end process; ----------------------------------------------------------------------------- -- Generate Read / Write strobes. ----------------------------------------------------------------------------- acia_read_write : process(clk, ac_rst) begin if falling_edge(clk) then if rst = '1' then CtrlReg(1 downto 0) <= "11"; CtrlReg(7 downto 2) <= (others => '0'); TxReg <= (others => '0'); RxRd <= '0'; TxWr <= '0'; StRd <= '0'; else RxRd <= '0'; TxWr <= '0'; StRd <= '0'; if cs = '1' then if Addr = '0' then -- Control / Status register if rw = '0' then -- write control register CtrlReg <= data_in; else -- read status register StRd <= '1'; end if; else -- Data Register if rw = '0' then -- write transmiter register TxReg <= data_in; TxWr <= '1'; else -- read receiver register RxRd <= '1'; end if; end if; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- ACIA Status Register ----------------------------------------------------------------------------- acia_status : process( clk ) begin if falling_edge( clk ) then StatReg(0) <= RxRdy; -- Receive Data Ready StatReg(1) <= TxRdy and (not CTS_n); -- Transmit Buffer Empty StatReg(2) <= DCDInt; -- Data Carrier Detect StatReg(3) <= CTS_n; -- Clear To Send StatReg(4) <= FErr; -- Framing error StatReg(5) <= OErr; -- Overrun error StatReg(6) <= PErr; -- Parity error StatReg(7) <= (RxIE and RxRdy) or (RxIE and DCDInt) or (TxIE and TxRdy); end if; end process; ----------------------------------------------------------------------------- -- ACIA Transmit Control ----------------------------------------------------------------------------- acia_control : process(CtrlReg, TxDat) begin case CtrlReg(6 downto 5) is when "00" => -- Disable TX Interrupts, Assert RTS TxD <= TxDat; TxIE <= '0'; RTS_n <= '0'; when "01" => -- Enable TX interrupts, Assert RTS TxD <= TxDat; TxIE <= '1'; RTS_n <= '0'; when "10" => -- Disable Tx Interrupts, Clear RTS TxD <= TxDat; TxIE <= '0'; RTS_n <= '1'; when "11" => -- Disable Tx interrupts, Assert RTS, send break TxD <= '0'; TxIE <= '0'; RTS_n <= '0'; when others => null; end case; RxIE <= CtrlReg(7); WdFmt <= CtrlReg(4 downto 2); BdFmt <= CtrlReg(1 downto 0); end process; --------------------------------------------------------------- -- Set Data Output Multiplexer -------------------------------------------------------------- acia_data_mux : process(Addr, RxReg, StatReg) begin if Addr = '1' then data_out <= RxReg; -- read receiver register else data_out <= StatReg; -- read status register end if; end process; irq <= StatReg(7); --------------------------------------------------------------- -- Data Carrier Detect Edge rising edge detect --------------------------------------------------------------- acia_dcd_edge : process( clk, ac_rst ) begin if falling_edge(clk) then if ac_rst = '1' then DCDDel <= '0'; DCDEdge <= '0'; else DCDDel <= DCD_n; DCDEdge <= DCD_n and (not DCDDel); end if; end if; end process; --------------------------------------------------------------- -- Data Carrier Detect Interrupt --------------------------------------------------------------- -- If Data Carrier is lost, an interrupt is generated -- To clear the interrupt, first read the status register -- then read the data receive register acia_dcd_int : process( clk, ac_rst ) begin if falling_edge(clk) then if ac_rst = '1' then DCDInt <= '0'; DCDState <= DCD_State_Idle; else case DCDState is when DCD_State_Idle => -- DCD Edge activates interrupt if DCDEdge = '1' then DCDInt <= '1'; DCDState <= DCD_State_Int; end if; when DCD_State_Int => -- To reset DCD interrupt, -- First read status if StRd = '1' then DCDState <= DCD_State_Reset; end if; when DCD_State_Reset => -- Then read receive register if RxRd = '1' then DCDInt <= '0'; DCDState <= DCD_State_Idle; end if; when others => null; end case; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Clock Edge Detection --------------------------------------------------------------------- -- A rising edge will produce a one clock cycle pulse -- acia_rx_clock_edge : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxClkDel <= '0'; RxClkEdge <= '0'; else RxClkDel <= RxC; RxClkEdge <= (not RxClkDel) and RxC; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Data Edge Detection --------------------------------------------------------------------- -- A falling edge will produce a pulse on RxClk wide -- acia_rx_data_edge : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxDatDel0 <= '0'; RxDatDel1 <= '0'; RxDatDel2 <= '0'; RxDatEdge <= '0'; else RxDatDel0 <= RxD; RxDatDel1 <= RxDatDel0; RxDatDel2 <= RxDatDel1; RxDatEdge <= RxDatDel0 and (not RxD); end if; end if; end process; --------------------------------------------------------------------- -- Receiver Start / Stop --------------------------------------------------------------------- -- Enable the receive clock on detection of a start bit -- Disable the receive clock after a byte is received. -- acia_rx_start_stop : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxEnable <= '0'; RxStart <= '0'; elsif (RxEnable = '0') and (RxDatEdge = '1') then -- Data Edge detected RxStart <= '1'; -- Request Start and RxEnable <= '1'; -- Enable Receive Clock elsif (RxStart = '1') and (RxAck = '1') then -- Data is being received RxStart <= '0'; -- Reset Start Request elsif (RxStart = '0') and (RxAck = '0') then -- Data has now been received RxEnable <= '0'; -- Disable Receiver until next Start Bit end if; end if; end process; --------------------------------------------------------------------- -- Receiver Clock Divider --------------------------------------------------------------------- -- Hold the Rx Clock divider in reset when the receiver is disabled -- Advance the count only on a rising Rx clock edge -- acia_rx_clock_divide : process( clk, rx_rst ) begin if falling_edge(clk) then if rx_rst = '1' then RxClkCnt <= (others => '0'); elsif RxDatEdge = '1' then -- reset on falling data edge RxClkCnt <= (others => '0'); elsif RxClkEdge = '1' then -- increment count on Clock edge RxClkCnt <= RxClkCnt + "000001"; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Baud Clock Selector --------------------------------------------------------------------- -- BdFmt -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - Reset -- acia_rx_baud_clock_select : process( BdFmt, RxC, RxClkCnt ) begin case BdFmt is when "00" => -- Div by 1 RxBdClk <= RxC; when "01" => -- Div by 16 RxBdClk <= RxClkCnt(3); when "10" => -- Div by 64 RxBdClk <= RxClkCnt(5); when others => -- Software Reset RxBdClk <= '0'; end case; end process; --------------------------------------------------------------------- -- Receiver process --------------------------------------------------------------------- -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop acia_rx_receive : process( clk, rst ) begin if falling_edge( clk ) then if rx_rst = '1' then FErr <= '0'; OErr <= '0'; PErr <= '0'; RxShiftReg <= (others => '0'); -- Reset Shift register RxReg <= (others => '0'); RxParity <= '0'; -- reset Parity bit RxAck <= '0'; -- Receiving data RxBitCount <= (others => '0'); RxState <= RxState_Wait; else RxBdDel <= RxBdClk; if RxBdDel = '0' and RxBdClk = '1' then case RxState is when RxState_Wait => RxShiftReg <= (others => '0'); -- Reset Shift register RxParity <= '0'; -- Reset Parity bit if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data bits RxBitCount <= "110"; else -- WdFmt(2) = '1' => 8 data bits RxBitCount <= "111"; end if; if RxDatDel2 = '0' then -- look for start bit RxState <= RxState_Data; -- if low, start reading data end if; when RxState_Data => -- Receiving data bits RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1); RxParity <= RxParity xor RxDatDel2; RxAck <= '1'; -- Flag receive in progress RxBitCount <= RxBitCount - "001"; if RxBitCount = "000" then if WdFmt(2) = '0' then -- WdFmt(2) = '0' => 7 data RxState <= RxState_Parity; -- 7 bits always has parity elsif WdFmt(1) = '0' then -- WdFmt(2) = '1' => 8 data RxState <= RxState_Stop; -- WdFmt(1) = '0' => no parity PErr <= '0'; -- Reset Parity Error else RxState <= RxState_Parity; -- WdFmt(1) = '1' => 8 data + parity end if; end if; when RxState_Parity => -- Receive Parity bit if WdFmt(2) = '0' then -- if 7 data bits, shift parity into MSB RxShiftReg <= RxDatDel2 & RxShiftReg(7 downto 1); -- 7 data + parity end if; if RxParity = (RxDatDel2 xor WdFmt(0)) then PErr <= '1'; -- If parity not the same flag error else PErr <= '0'; end if; RxState <= RxState_Stop; when RxState_Stop => -- stop bit (Only one required for RX) RxAck <= '0'; -- Flag Receive Complete RxReg <= RxShiftReg; if RxDatDel2 = '1' then -- stop bit expected FErr <= '0'; -- yes, no framing error else FErr <= '1'; -- no, framing error end if; if RxRdy = '1' then -- Has previous data been read ? OErr <= '1'; -- no, overrun error else OErr <= '0'; -- yes, no over run error end if; RxState <= RxState_Wait; when others => RxAck <= '0'; -- Flag Receive Complete RxState <= RxState_Wait; end case; end if; end if; end if; end process; --------------------------------------------------------------------- -- Receiver Read process --------------------------------------------------------------------- acia_rx_read : process( clk, rst, RxRdy ) begin if falling_edge(clk) then if rx_rst = '1' then RxRdy <= '0'; RxReq <= '0'; elsif RxRd = '1' then -- Data was read, RxRdy <= '0'; -- Reset receive full RxReq <= '1'; -- Request more data elsif RxReq = '1' and RxAck = '1' then -- Data is being received RxReq <= '0'; -- reset receive request elsif RxReq = '0' and RxAck = '0' then -- Data now received RxRdy <= '1'; -- Flag RxRdy and read Shift Register end if; end if; end process; --------------------------------------------------------------------- -- Transmit Clock Edge Detection -- A falling edge will produce a one clock cycle pulse --------------------------------------------------------------------- acia_tx_clock_edge : process( Clk, tx_rst ) begin if falling_edge(clk) then if tx_rst = '1' then TxClkDel <= '0'; TxClkEdge <= '0'; else TxClkDel <= TxC; TxClkEdge <= TxClkDel and (not TxC); end if; end if; end process; --------------------------------------------------------------------- -- Transmit Clock Divider -- Advance the count only on an input clock pulse --------------------------------------------------------------------- acia_tx_clock_divide : process( clk, tx_rst ) begin if falling_edge(clk) then if tx_rst = '1' then TxClkCnt <= (others=>'0'); elsif TxClkEdge = '1' then TxClkCnt <= TxClkCnt + "000001"; end if; end if; end process; --------------------------------------------------------------------- -- Transmit Baud Clock Selector --------------------------------------------------------------------- acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC ) begin -- BdFmt -- 0 0 - Baud Clk divide by 1 -- 0 1 - Baud Clk divide by 16 -- 1 0 - Baud Clk divide by 64 -- 1 1 - reset case BdFmt is when "00" => -- Div by 1 TxBdClk <= TxC; when "01" => -- Div by 16 TxBdClk <= TxClkCnt(3); when "10" => -- Div by 64 TxBdClk <= TxClkCnt(5); when others => -- Software reset TxBdClk <= '0'; end case; end process; ----------------------------------------------------------------------------- -- Implements the Tx unit ----------------------------------------------------------------------------- -- WdFmt - Bits[4..2] -- 0 0 0 - 7 data, even parity, 2 stop -- 0 0 1 - 7 data, odd parity, 2 stop -- 0 1 0 - 7 data, even parity, 1 stop -- 0 1 1 - 7 data, odd parity, 1 stop -- 1 0 0 - 8 data, no parity, 2 stop -- 1 0 1 - 8 data, no parity, 1 stop -- 1 1 0 - 8 data, even parity, 1 stop -- 1 1 1 - 8 data, odd parity, 1 stop acia_tx_transmit : process( clk, tx_rst) begin if falling_edge(clk) then if tx_rst = '1' then TxDat <= '1'; TxShiftReg <= (others=>'0'); TxParity <= '0'; TxBitCount <= (others=>'0'); TxAck <= '0'; TxState <= TxState_Idle; else TxBdDel <= TxBdClk; -- On rising edge of baud clock, run the state machine if TxBdDel = '0' and TxBdClk = '1' then case TxState is when TxState_Idle => TxDat <= '1'; if TxReq = '1' then TxShiftReg <= TxReg; -- Load Shift reg with Tx Data TxAck <= '1'; TxState <= TxState_Start; end if; when TxState_Start => TxDat <= '0'; -- Start bit TxParity <= '0'; if WdFmt(2) = '0' then TxBitCount <= "110"; -- 7 data + parity else TxBitCount <= "111"; -- 8 data end if; TxState <= TxState_Data; when TxState_Data => TxDat <= TxShiftReg(0); TxShiftReg <= '1' & TxShiftReg(7 downto 1); TxParity <= TxParity xor TxShiftReg(0); TxBitCount <= TxBitCount - "001"; if TxBitCount = "000" then if (WdFmt(2) = '1') and (WdFmt(1) = '0') then if WdFmt(0) = '0' then -- 8 data bits TxState <= TxState_Stop; -- 2 stops else TxAck <= '0'; TxState <= TxState_Idle; -- 1 stop end if; else TxState <= TxState_Parity; -- parity end if; end if; when TxState_Parity => -- 7/8 data + parity bit if WdFmt(0) = '0' then TxDat <= not(TxParity); -- even parity else TxDat <= TxParity; -- odd parity end if; if WdFmt(1) = '0' then TxState <= TxState_Stop; -- 2 stops else TxAck <= '0'; TxState <= TxState_Idle; -- 1 stop end if; when TxState_Stop => -- first of two stop bits TxDat <= '1'; TxAck <= '0'; TxState <= TxState_Idle; end case; end if; end if; end if; end process; --------------------------------------------------------------------- -- Transmitter Write process --------------------------------------------------------------------- acia_tx_write : process( clk, tx_rst, TxWr, TxReq, TxAck ) begin if falling_edge(clk) then if tx_rst = '1' then TxRdy <= '0'; TxReq <= '0'; elsif TxWr = '1' then -- Data was read, TxRdy <= '0'; -- Reset transmit empty TxReq <= '1'; -- Request data transmit elsif TxReq = '1' and TxAck = '1' then -- Data is being transmitted TxReq <= '0'; -- reset transmit request elsif TxReq = '0' and TxAck = '0' then -- Data transmitted TxRdy <= '1'; -- Flag TxRdy end if; end if; end process; end rtl;

gpl-3.0

a9561e0aa141e988999052e298368f6e

0.425929

4.365647

false

Given-Jiang/Binarization

Binarization_dspbuilder/hdl/Binarization_GN.vhd

2

10,406

-- Binarization_GN.vhd -- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Binarization_GN is port ( Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire Clock : in std_logic := '0'; -- Clock.clk aclr : in std_logic := '0'; -- .reset_n Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire Avalon_MM_Slave_write : in std_logic := '0'; -- Avalon_MM_Slave_write.wire Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire Avalon_ST_Source_endofpacket : out std_logic -- Avalon_ST_Source_endofpacket.wire ); end entity Binarization_GN; architecture rtl of Binarization_GN is component alt_dspbuilder_clock_GNF343OQUJ is port ( aclr : in std_logic := 'X'; -- reset aclr_n : in std_logic := 'X'; -- reset_n aclr_out : out std_logic; -- reset clock : in std_logic := 'X'; -- clk clock_out : out std_logic -- clk ); end component alt_dspbuilder_clock_GNF343OQUJ; component alt_dspbuilder_port_GNOC3SGKQJ is port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_port_GNOC3SGKQJ; component alt_dspbuilder_port_GN37ALZBS4 is port ( input : in std_logic := 'X'; -- wire output : out std_logic -- wire ); end component alt_dspbuilder_port_GN37ALZBS4; component Binarization_GN_Binarization_Binarization_Module is port ( Clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset data_out : out std_logic_vector(23 downto 0); -- wire addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire eop : in std_logic := 'X'; -- wire sop : in std_logic := 'X'; -- wire writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire write : in std_logic := 'X' -- wire ); end component Binarization_GN_Binarization_Binarization_Module; component alt_dspbuilder_port_GN6TDLHAW6 is port ( input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_port_GN6TDLHAW6; component alt_dspbuilder_port_GNEPKLLZKY is port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_port_GNEPKLLZKY; signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Binarization_Binarization_Module_0:sop] signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Binarization_Binarization_Module_0:eop] signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Binarization_Binarization_Module_0:addr signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Binarization_Binarization_Module_0:write signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Binarization_Binarization_Module_0:writedata signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Binarization_Binarization_Module_0:data_in signal binarization_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Binarization_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Binarization_Binarization_Module_0:aclr signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Binarization_Binarization_Module_0:Clock begin clock_0 : component alt_dspbuilder_clock_GNF343OQUJ port map ( clock_out => clock_0_clock_output_clk, -- clock_output.clk aclr_out => clock_0_clock_output_reset, -- .reset clock => Clock, -- clock.clk aclr_n => aclr -- .reset_n ); avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => Avalon_ST_Sink_data, -- input.wire output => avalon_st_sink_data_0_output_wire -- output.wire ); avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_endofpacket, -- input.wire output => avalon_st_sink_endofpacket_0_output_wire -- output.wire ); binarization_binarization_module_0 : component Binarization_GN_Binarization_Binarization_Module port map ( Clock => clock_0_clock_output_clk, -- Clock.clk aclr => clock_0_clock_output_reset, -- .reset data_out => binarization_binarization_module_0_data_out_wire, -- data_out.wire addr => avalon_mm_slave_address_0_output_wire, -- addr.wire eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire write => avalon_mm_slave_write_0_output_wire -- write.wire ); avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6 port map ( input => Avalon_MM_Slave_address, -- input.wire output => avalon_mm_slave_address_0_output_wire -- output.wire ); avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY port map ( input => Avalon_MM_Slave_writedata, -- input.wire output => avalon_mm_slave_writedata_0_output_wire -- output.wire ); avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_valid_0_output_wire, -- input.wire output => Avalon_ST_Source_valid -- output.wire ); avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_valid, -- input.wire output => avalon_st_sink_valid_0_output_wire -- output.wire ); avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire output => Avalon_ST_Source_endofpacket -- output.wire ); avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire output => Avalon_ST_Source_startofpacket -- output.wire ); avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Source_ready, -- input.wire output => avalon_st_source_ready_0_output_wire -- output.wire ); avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_MM_Slave_write, -- input.wire output => avalon_mm_slave_write_0_output_wire -- output.wire ); avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => avalon_st_source_ready_0_output_wire, -- input.wire output => Avalon_ST_Sink_ready -- output.wire ); avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => Avalon_ST_Sink_startofpacket, -- input.wire output => avalon_st_sink_startofpacket_0_output_wire -- output.wire ); avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => binarization_binarization_module_0_data_out_wire, -- input.wire output => Avalon_ST_Source_data -- output.wire ); end architecture rtl; -- of Binarization_GN

mit

11c452a355bc98d653e043a80606e2f7

0.581588

3.428666

false

TWW12/lzw

final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/sim/design_1_rst_ps7_0_100M_0.vhd

3

5,851

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 10 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_10; USE proc_sys_reset_v5_0_10.proc_sys_reset; ENTITY design_1_rst_ps7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END design_1_rst_ps7_0_100M_0; ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END design_1_rst_ps7_0_100M_0_arch;

unlicense

86cf7cdd302d8c9087f1458fad4afbbc

0.705691

3.541768

false

grwlf/vsim

vhdl_ct/ct00546.vhd

1

2,484

-- NEED RESULT: ARCH00546: Architectural library name visibility test failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00546 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.3 (11) -- 10.3 (13) -- -- DESIGN UNIT ORDERING: -- -- ENT00546(ARCH00546) -- ENT00546_Test_Bench(ARCH00546_Test_Bench) -- CONF00546 -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- 19-JAN-1987 - replaced selected name WORK.ARCH00546 with simple -- name ARCH00546 -- -- NOTES: -- -- self-checking -- -- entity ENT00546 is generic ( G : Integer := 0 ) ; port ( P1 : in Boolean ; P2 : out Boolean ) ; end ENT00546 ; -- architecture ARCH00546 of ENT00546 is begin process (P1) begin P2 <= transport Not P1 ; end process ; end ARCH00546 ; -- entity ENT00546_Test_Bench is end ENT00546_Test_Bench ; -- use WORK.STANDARD_TYPES.all ; architecture ARCH00546_Test_Bench of ENT00546_Test_Bench is signal S1, S2 : boolean := false ; signal S3 : boolean := true ; component Comp1 generic ( G : Integer := 0 ) ; port ( P1 : in boolean ; P2 : out boolean ) ; end component ; for CIS1 : Comp1 use entity WORK.ENT00546 ( ARCH00546 ); -- reference in binding indication component Comp2 port ( P1 : in boolean ; P2 : out boolean ) ; end component ; begin CIS1 : Comp1 generic map ( open ) port map ( S1, S2 ) ; Blk : block begin CIS1 : Comp2 port map ( S2, S3 ) ; end block Blk ; process begin wait for 10 ns ; test_report ( "ARCH00546" , "Architectural library name visibility test" , (Not S1) and S2 and (Not S3) ) ; wait ; end process ; end ARCH00546_Test_Bench ; -- configuration CONF00546 of WORK.ENT00546_Test_Bench is for ARCH00546_Test_Bench -- reference in a configuration for Blk for CIS1 : Comp2 use entity WORK.ENT00546 ( ARCH00546 ) -- reference in a binding indication generic map ( G => open ) port map ( P1, P2 ) ; end for ; end for ; end for ; end CONF00546 ; --

gpl-3.0

28581012b36d9f460849eee5c9471e39

0.531804

3.388813

false

true

false

wsoltys/AtomFpga

src/AtomGodilVideo/src/MINIUART/Txunit.vhd

1

3,291

------------------------------------------------------------------------------- -- Title : UART -- Project : UART ------------------------------------------------------------------------------- -- File : Txunit.vhd -- Author : Philippe CARTON -- ([email protected]) -- Organization: -- Created : 15/12/2001 -- Last update : 8/1/2003 -- Platform : Foundation 3.1i -- Simulators : ModelSim 5.5b -- Synthesizers: Xilinx Synthesis -- Targets : Xilinx Spartan -- Dependency : IEEE std_logic_1164 ------------------------------------------------------------------------------- -- Description: Txunit is a parallel to serial unit transmitter. ------------------------------------------------------------------------------- -- Copyright (c) notice -- This core adheres to the GNU public license -- ------------------------------------------------------------------------------- -- Revisions : -- Revision Number : -- Version : -- Date : -- Modifier : name <email> -- Description : -- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity TxUnit is port ( Clk : in std_logic; -- Clock signal Reset : in std_logic; -- Reset input Enable : in std_logic; -- Enable input LoadA : in std_logic; -- Asynchronous Load TxD : out std_logic; -- RS-232 data output Busy : out std_logic; -- Tx Busy DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit end TxUnit; architecture Behaviour of TxUnit is component synchroniser port ( C1 : in std_logic; -- Asynchronous signal C : in std_logic; -- Clock O : out Std_logic);-- Synchronised signal end component; signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer signal TReg : std_logic_vector(7 downto 0); -- transmit register signal TBufL : std_logic; -- Buffer loaded signal LoadS : std_logic; -- Synchronised load signal begin -- Synchronise Load on Clk SyncLoad : Synchroniser port map (LoadA, Clk, LoadS); Busy <= LoadS or TBufL; -- Tx process TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL) variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame begin if Reset = '1' then TBufL <= '0'; BitPos := 0; TxD <= '1'; elsif Rising_Edge(Clk) then if LoadS = '1' then TBuff <= DataI; TBufL <= '1'; end if; if Enable = '1' then case BitPos is when 0 => -- idle or stop bit TxD <= '1'; if TBufL = '1' then -- start transmit. next is start bit TReg <= TBuff; TBufL <= '0'; BitPos := 1; end if; when 1 => -- Start bit TxD <= '0'; BitPos := 2; when others => TxD <= TReg(BitPos-2); -- Serialisation of TReg BitPos := BitPos + 1; end case; if BitPos = 10 then -- bit8. next is stop bit BitPos := 0; end if; end if; end if; end process; end Behaviour;

apache-2.0

86bd78425a7c2e5f7b53c529193e111b

0.463993

4.251938

false

jairov4/accel-oil

solution_kintex7/syn/vhdl/nfa_accept_sample.vhd

1

61,739

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_sample is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); empty : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of nfa_accept_sample is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal reg_374 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_reg_577 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_reg_582 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_s_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_597 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0); signal i_1_reg_601 : STD_LOGIC_VECTOR (15 downto 0); signal sample_addr_1_reg_606 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_17_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_i_reg_612 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_rec_reg_616 : STD_LOGIC_VECTOR (31 downto 0); signal sym_reg_621 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_1_i_reg_626 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_368_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal r_bit_reg_630 : STD_LOGIC_VECTOR (4 downto 0); signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 : STD_LOGIC_VECTOR (1 downto 0); signal j_bucket_index1_ph_cast_fu_436_p1 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_ph_cast_fu_440_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_7_i_cast_fu_444_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_i_cast_reg_650 : STD_LOGIC_VECTOR (13 downto 0); signal j_end_phi_fu_312_p4 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p2 : STD_LOGIC_VECTOR (5 downto 0); signal state_reg_665 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p2 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_6_i_reg_680 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_482_p2 : STD_LOGIC_VECTOR (13 downto 0); signal offset_i_reg_685 : STD_LOGIC_VECTOR (13 downto 0); signal j_bit_reg_701 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_index_reg_706 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_reg_711 : STD_LOGIC_VECTOR (31 downto 0); signal p_s_reg_716 : STD_LOGIC_VECTOR (0 downto 0); signal next_buckets_0_1_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_1_reg_721 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_1_fu_544_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_reg_731 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_1_reg_736 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_reg_741 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_fu_563_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_fu_568_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_756 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_p_read : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_r_bit : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_start : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_done : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_idle : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_ready : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_start : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_done : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_idle : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_ready : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_ce : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_ap_ce : STD_LOGIC; signal i_reg_134 : STD_LOGIC_VECTOR (15 downto 0); signal any_phi_fu_324_p4 : STD_LOGIC_VECTOR (0 downto 0); signal p_01_rec_reg_146 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_reg_158 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_reg_168 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_178 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_0_lcssa4_i_reg_190 : STD_LOGIC_VECTOR (0 downto 0); signal j_bucket1_ph_reg_203 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_ph_reg_216 : STD_LOGIC_VECTOR (1 downto 0); signal j_bit1_ph_reg_227 : STD_LOGIC_VECTOR (4 downto 0); signal j_end_ph_reg_238 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_buckets_1_3_reg_252 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_3_reg_265 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket1_reg_278 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_reg_289 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_reg_299 : STD_LOGIC_VECTOR (7 downto 0); signal j_end_reg_309 : STD_LOGIC_VECTOR (0 downto 0); signal any_reg_319 : STD_LOGIC_VECTOR (0 downto 0); signal p_0_reg_332 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_nfa_get_finals_fu_362_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_fu_392_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_4_i_cast_fu_493_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_i_cast_fu_511_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_402_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_402_p1 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_447_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p0 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_463_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_476_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_482_p0 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_482_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_4_i_fu_486_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_8_i_fu_504_p3 : STD_LOGIC_VECTOR (14 downto 0); signal grp_fu_392_ce : STD_LOGIC; signal grp_fu_402_ce : STD_LOGIC; signal grp_fu_414_ce : STD_LOGIC; signal grp_fu_463_ce : STD_LOGIC; signal grp_fu_476_ce : STD_LOGIC; signal grp_fu_482_ce : STD_LOGIC; signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal grp_fu_476_p00 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_476_p10 : STD_LOGIC_VECTOR (13 downto 0); component bitset_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_get_initials IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_get_finals IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (15 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (5 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (5 downto 0) ); end component; component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (7 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (13 downto 0); din1 : IN STD_LOGIC_VECTOR (13 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; begin grp_bitset_next_fu_344 : component bitset_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, p_read => grp_bitset_next_fu_344_p_read, r_bit => grp_bitset_next_fu_344_r_bit, r_bucket_index => grp_bitset_next_fu_344_r_bucket_index, r_bucket => grp_bitset_next_fu_344_r_bucket, ap_return_0 => grp_bitset_next_fu_344_ap_return_0, ap_return_1 => grp_bitset_next_fu_344_ap_return_1, ap_return_2 => grp_bitset_next_fu_344_ap_return_2, ap_return_3 => grp_bitset_next_fu_344_ap_return_3, ap_ce => grp_bitset_next_fu_344_ap_ce); grp_nfa_get_initials_fu_356 : component nfa_get_initials port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_initials_fu_356_ap_start, ap_done => grp_nfa_get_initials_fu_356_ap_done, ap_idle => grp_nfa_get_initials_fu_356_ap_idle, ap_ready => grp_nfa_get_initials_fu_356_ap_ready, nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_get_initials_fu_356_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_get_initials_fu_356_nfa_initials_buckets_size, ap_ce => grp_nfa_get_initials_fu_356_ap_ce, ap_return_0 => grp_nfa_get_initials_fu_356_ap_return_0, ap_return_1 => grp_nfa_get_initials_fu_356_ap_return_1); grp_nfa_get_finals_fu_362 : component nfa_get_finals port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_finals_fu_362_ap_start, ap_done => grp_nfa_get_finals_fu_362_ap_done, ap_idle => grp_nfa_get_finals_fu_362_ap_idle, ap_ready => grp_nfa_get_finals_fu_362_ap_ready, nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_get_finals_fu_362_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_get_finals_fu_362_nfa_finals_buckets_size, ap_ce => grp_nfa_get_finals_fu_362_ap_ce, ap_return_0 => grp_nfa_get_finals_fu_362_ap_return_0, ap_return_1 => grp_nfa_get_finals_fu_362_ap_return_1); grp_p_bsf32_hw_fu_368 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_368_bus_r, ap_return => grp_p_bsf32_hw_fu_368_ap_return, ap_ce => grp_p_bsf32_hw_fu_368_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 17, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_392_p0, din1 => grp_fu_392_p1, ce => grp_fu_392_ce, dout => grp_fu_392_p2); nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 generic map ( ID => 18, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 16, dout_WIDTH => 16) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_402_p0, din1 => grp_fu_402_p1, ce => grp_fu_402_ce, dout => grp_fu_402_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 19, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_414_p0, din1 => grp_fu_414_p1, ce => grp_fu_414_ce, dout => grp_fu_414_p2); nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 generic map ( ID => 20, NUM_STAGE => 2, din0_WIDTH => 6, din1_WIDTH => 6, dout_WIDTH => 6) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_463_p0, din1 => grp_fu_463_p1, ce => grp_fu_463_ce, dout => grp_fu_463_p2); nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 generic map ( ID => 21, NUM_STAGE => 4, din0_WIDTH => 8, din1_WIDTH => 6, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_476_p0, din1 => grp_fu_476_p1, ce => grp_fu_476_ce, dout => grp_fu_476_p2); nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 generic map ( ID => 22, NUM_STAGE => 4, din0_WIDTH => 14, din1_WIDTH => 14, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_482_p0, din1 => grp_fu_482_p1, ce => grp_fu_482_ce, dout => grp_fu_482_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_return_preg assign process. -- ap_return_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_return_preg <= ap_const_lv1_0; else if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_return_preg <= p_0_reg_332; end if; end if; end if; end process; -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st12_fsm_11 = ap_NS_fsm) and (ap_ST_st11_fsm_10 = ap_CS_fsm) and (tmp_s_reg_597 = ap_const_lv1_0))) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_362_ap_ready)) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- agg_result_bucket_index_0_lcssa4_i_reg_190 assign process. -- agg_result_bucket_index_0_lcssa4_i_reg_190_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0; end if; end if; end process; -- any_reg_319 assign process. -- any_reg_319_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_1; end if; end if; end process; -- bus_assign_reg_178 assign process. -- bus_assign_reg_178_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_1_reg_158; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_0_reg_168; end if; end if; end process; -- i_reg_134 assign process. -- i_reg_134_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then i_reg_134 <= i_1_reg_601; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then i_reg_134 <= ap_const_lv16_0; end if; end if; end process; -- j_bit1_reg_299 assign process. -- j_bit1_reg_299_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit_reg_701; end if; end if; end process; -- j_bucket1_ph_reg_203 assign process. -- j_bucket1_ph_reg_203_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket1_ph_reg_203 <= bus_assign_reg_178; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket1_ph_reg_203 <= ap_const_lv32_0; end if; end if; end process; -- j_bucket1_reg_278 assign process. -- j_bucket1_reg_278_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket1_ph_reg_203; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket_reg_711; end if; end if; end process; -- j_bucket_index1_ph_reg_216 assign process. -- j_bucket_index1_ph_reg_216_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket_index1_ph_reg_216 <= ap_const_lv2_2; end if; end if; end process; -- j_bucket_index1_reg_289 assign process. -- j_bucket_index1_reg_289_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index_reg_706; end if; end if; end process; -- j_end_ph_reg_238 assign process. -- j_end_ph_reg_238_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_end_ph_reg_238 <= ap_const_lv1_0; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_end_ph_reg_238 <= ap_const_lv1_1; end if; end if; end process; -- j_end_reg_309 assign process. -- j_end_reg_309_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_end_reg_309 <= j_end_ph_reg_238; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then j_end_reg_309 <= p_s_reg_716; end if; end if; end process; -- next_buckets_0_reg_168 assign process. -- next_buckets_0_reg_168_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_0_reg_168 <= current_buckets_0_reg_577; end if; end if; end process; -- next_buckets_1_reg_158 assign process. -- next_buckets_1_reg_158_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_1_reg_158 <= current_buckets_1_reg_582; end if; end if; end process; -- p_01_rec_reg_146 assign process. -- p_01_rec_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then p_01_rec_reg_146 <= p_rec_reg_616; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then p_01_rec_reg_146 <= ap_const_lv32_0; end if; end if; end process; -- p_0_reg_332 assign process. -- p_0_reg_332_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then p_0_reg_332 <= ap_const_lv1_0; elsif ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then p_0_reg_332 <= tmp_2_reg_756; end if; end if; end process; -- tmp_buckets_0_3_reg_265 assign process. -- tmp_buckets_0_3_reg_265_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= ap_const_lv32_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721; end if; end if; end process; -- tmp_buckets_1_3_reg_252 assign process. -- tmp_buckets_1_3_reg_252_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= ap_const_lv32_0; elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2; current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0; current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then i_1_reg_601 <= grp_fu_402_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bit1_ph_reg_227 <= r_bit_reg_630; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then j_bit_reg_701 <= grp_bitset_next_fu_344_ap_return_0; j_bucket_index_reg_706 <= grp_bitset_next_fu_344_ap_return_1; j_bucket_reg_711 <= grp_bitset_next_fu_344_ap_return_2; p_s_reg_716 <= grp_bitset_next_fu_344_ap_return_3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm))) then next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then offset_i_reg_685 <= grp_fu_482_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then p_rec_reg_616 <= grp_fu_414_p2; sym_reg_621 <= sample_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then reg_374 <= nfa_forward_buckets_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then sample_addr_1_reg_606 <= grp_fu_392_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then state_reg_665 <= grp_fu_463_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then tmp_17_1_i_reg_626 <= tmp_17_1_i_fu_426_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then tmp_17_i_reg_612 <= tmp_17_i_fu_420_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then tmp_1_reg_751 <= tmp_1_fu_568_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then tmp_2_reg_756 <= tmp_2_fu_572_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then tmp_6_i_reg_680 <= grp_fu_476_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_7_i_cast_reg_650(0) <= tmp_7_i_cast_fu_444_p1(0); tmp_7_i_cast_reg_650(1) <= tmp_7_i_cast_fu_444_p1(1); tmp_7_i_cast_reg_650(2) <= tmp_7_i_cast_fu_444_p1(2); tmp_7_i_cast_reg_650(3) <= tmp_7_i_cast_fu_444_p1(3); tmp_7_i_cast_reg_650(4) <= tmp_7_i_cast_fu_444_p1(4); tmp_7_i_cast_reg_650(5) <= tmp_7_i_cast_fu_444_p1(5); tmp_7_i_cast_reg_650(6) <= tmp_7_i_cast_fu_444_p1(6); tmp_7_i_cast_reg_650(7) <= tmp_7_i_cast_fu_444_p1(7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0; tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then tmp_s_reg_597 <= tmp_s_fu_397_p2; end if; end if; end process; tmp_7_i_cast_reg_650(13 downto 8) <= "000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_597 , tmp_17_i_reg_612 , tmp_17_1_i_reg_626 , j_end_phi_fu_312_p4 , any_phi_fu_324_p4) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => if ((tmp_s_reg_597 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st39_fsm_38; else ap_NS_fsm <= ap_ST_st13_fsm_12; end if; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st21_fsm_20; elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st20_fsm_19; else ap_NS_fsm <= ap_ST_st19_fsm_18; end if; when ap_ST_st20_fsm_19 => if (not((tmp_17_1_i_reg_626 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st24_fsm_23; else ap_NS_fsm <= ap_ST_st21_fsm_20; end if; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => if ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then ap_NS_fsm <= ap_ST_st5_fsm_4; elsif ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then ap_NS_fsm <= ap_ST_st45_fsm_44; else ap_NS_fsm <= ap_ST_st26_fsm_25; end if; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st37_fsm_36; else ap_NS_fsm <= ap_ST_st36_fsm_35; end if; when ap_ST_st37_fsm_36 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st38_fsm_37; else ap_NS_fsm <= ap_ST_st37_fsm_36; end if; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st43_fsm_42; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st44_fsm_43; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190),2)); any_phi_fu_324_p4 <= any_reg_319; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st45_fsm_44 = ap_CS_fsm))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_return assign process. -- ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_332, ap_return_preg) begin if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then ap_return <= p_0_reg_332; else ap_return <= ap_return_preg; end if; end process; current_buckets_0_1_fu_558_p2 <= (next_buckets_0_reg_168 and tmp_buckets_0_reg_731); current_buckets_1_1_fu_563_p2 <= (next_buckets_1_reg_158 and tmp_buckets_1_reg_736); -- grp_bitset_next_fu_344_ap_ce assign process. -- grp_bitset_next_fu_344_ap_ce_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, j_end_phi_fu_312_p4) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st25_fsm_24 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_312_p4)) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then grp_bitset_next_fu_344_ap_ce <= ap_const_logic_1; else grp_bitset_next_fu_344_ap_ce <= ap_const_logic_0; end if; end process; grp_bitset_next_fu_344_p_read <= next_buckets_1_reg_158; grp_bitset_next_fu_344_r_bit <= j_bit1_reg_299; grp_bitset_next_fu_344_r_bucket <= j_bucket1_reg_278; grp_bitset_next_fu_344_r_bucket_index <= j_bucket_index1_reg_289; grp_fu_392_ce <= ap_const_logic_1; grp_fu_392_p0 <= p_01_rec_reg_146; grp_fu_392_p1 <= empty; grp_fu_402_ce <= ap_const_logic_1; grp_fu_402_p0 <= i_reg_134; grp_fu_402_p1 <= ap_const_lv16_1; -- grp_fu_414_ce assign process. -- grp_fu_414_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_597) begin if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((tmp_s_reg_597 = ap_const_lv1_0))) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm))) then grp_fu_414_ce <= ap_const_logic_1; else grp_fu_414_ce <= ap_const_logic_0; end if; end process; grp_fu_414_p0 <= p_01_rec_reg_146; grp_fu_414_p1 <= ap_const_lv32_1; grp_fu_463_ce <= ap_const_logic_1; grp_fu_463_p0 <= (tmp_5_fu_447_p1 & ap_const_lv5_0); grp_fu_463_p1 <= j_bit1_reg_299(6 - 1 downto 0); grp_fu_476_ce <= ap_const_logic_1; grp_fu_476_p0 <= grp_fu_476_p00(8 - 1 downto 0); grp_fu_476_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14)); grp_fu_476_p1 <= grp_fu_476_p10(6 - 1 downto 0); grp_fu_476_p10 <= std_logic_vector(resize(unsigned(state_reg_665),14)); grp_fu_482_ce <= ap_const_logic_1; grp_fu_482_p0 <= tmp_6_i_reg_680; grp_fu_482_p1 <= tmp_7_i_cast_reg_650; grp_nfa_get_finals_fu_362_ap_ce <= ap_const_logic_1; grp_nfa_get_finals_fu_362_ap_start <= grp_nfa_get_finals_fu_362_ap_start_ap_start_reg; grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_get_initials_fu_356_ap_ce <= ap_const_logic_1; -- grp_nfa_get_initials_fu_356_ap_start assign process. -- grp_nfa_get_initials_fu_356_ap_start_assign_proc : process(ap_start, ap_CS_fsm) begin if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_1; else grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_0; end if; end process; grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; -- grp_p_bsf32_hw_fu_368_ap_ce assign process. -- grp_p_bsf32_hw_fu_368_ap_ce_assign_proc : process(ap_CS_fsm) begin if (((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_0; end if; end process; grp_p_bsf32_hw_fu_368_bus_r <= bus_assign_reg_178; j_bit1_ph_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_227),8)); j_bucket_index1_ph_cast_fu_436_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_216),8)); j_end_phi_fu_312_p4 <= j_end_reg_309; next_buckets_0_1_fu_538_p2 <= (tmp_buckets_0_3_reg_265 or reg_374); next_buckets_1_1_fu_544_p2 <= (tmp_buckets_1_3_reg_252 or reg_374); nfa_finals_buckets_address <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_size; -- nfa_forward_buckets_address assign process. -- nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, tmp_4_i_cast_fu_493_p1, tmp_8_i_cast_fu_511_p1) begin if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then nfa_forward_buckets_address <= tmp_8_i_cast_fu_511_p1; elsif ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then nfa_forward_buckets_address <= tmp_4_i_cast_fu_493_p1; else nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_forward_buckets_dataout <= ap_const_lv32_0; nfa_forward_buckets_req_din <= ap_const_logic_0; -- nfa_forward_buckets_req_write assign process. -- nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then nfa_forward_buckets_req_write <= ap_const_logic_1; else nfa_forward_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_forward_buckets_rsp_read assign process. -- nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then nfa_forward_buckets_rsp_read <= ap_const_logic_1; else nfa_forward_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_forward_buckets_size <= ap_const_lv32_1; nfa_initials_buckets_address <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_size; sample_address <= sample_addr_1_reg_606; sample_dataout <= ap_const_lv8_0; sample_req_din <= ap_const_logic_0; -- sample_req_write assign process. -- sample_req_write_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then sample_req_write <= ap_const_logic_1; else sample_req_write <= ap_const_logic_0; end if; end process; -- sample_rsp_read assign process. -- sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n) begin if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then sample_rsp_read <= ap_const_logic_1; else sample_rsp_read <= ap_const_logic_0; end if; end process; sample_size <= ap_const_lv32_1; tmp_17_1_i_fu_426_p2 <= "1" when (next_buckets_1_reg_158 = ap_const_lv32_0) else "0"; tmp_17_i_fu_420_p2 <= "1" when (next_buckets_0_reg_168 = ap_const_lv32_0) else "0"; tmp_1_fu_568_p2 <= (current_buckets_1_1_reg_746 or current_buckets_0_1_reg_741); tmp_2_fu_572_p2 <= "0" when (tmp_1_reg_751 = ap_const_lv32_0) else "1"; tmp_4_i_cast_fu_493_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_486_p3),32)); tmp_4_i_fu_486_p3 <= (offset_i_reg_685 & ap_const_lv1_0); tmp_5_fu_447_p1 <= j_bucket_index1_reg_289(1 - 1 downto 0); tmp_7_i_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(sym_reg_621),14)); tmp_8_i_cast_fu_511_p1 <= std_logic_vector(resize(unsigned(tmp_8_i_fu_504_p3),32)); tmp_8_i_fu_504_p3 <= (offset_i_reg_685 & ap_const_lv1_1); tmp_s_fu_397_p2 <= "1" when (unsigned(i_reg_134) < unsigned(length_r)) else "0"; end behav;

lgpl-3.0

4af02bf1ea3790bf448598a1780ac021

0.579488

2.764103

false

jairov4/accel-oil

impl/impl_test_pcie/hdl/system_clock_generator_0_wrapper.vhd

1

3,263

------------------------------------------------------------------------------- -- system_clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_03_a; use clock_generator_0_v4_03_a.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_clock_generator_0_wrapper : entity is "clock_generator_v4_03_a"; end system_clock_generator_0_wrapper; architecture STRUCTURE of system_clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "virtex5", C_DEVICE => "5vlx50t", C_PACKAGE => "ff1136", C_SPEEDGRADE => "-1" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;

lgpl-3.0

94f5ef2ff125e819d8d5a454e755cf45

0.57585

3.637681

false

jairov4/accel-oil

impl/impl_test_pcie/simulation/behavioral/system_ac1_plb_wrapper.vhd

1

14,574

------------------------------------------------------------------------------- -- system_ac1_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end system_ac1_plb_wrapper; architecture STRUCTURE of system_ac1_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin ac1_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 15, C_PLBV46_NUM_SLAVES => 1, C_PLBV46_MID_WIDTH => 4, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;

lgpl-3.0

2e22b972707dbfb2d46e9ba2d0caf8ef

0.611157

3.041954

false

wsoltys/AtomFpga

src/AtomGodilVideo/src/DCM/DCMSID1.vhd

1

2,037

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity DCMSID1 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end DCMSID1; architecture BEHAVIORAL of DCMSID1 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, CLKFX_DIVIDE => 12, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 65.1, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => CLK2X_OUT, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;

apache-2.0

56c424e6dae00a525802dfae58d64b2c

0.405989

4.306554

false

jairov4/accel-oil

solution_spartan3/impl/vhdl/nfa_accept_samples_generic_hw.vhd

1

92,188

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_req_din : OUT STD_LOGIC; sample_buffer_req_full_n : IN STD_LOGIC; sample_buffer_req_write : OUT STD_LOGIC; sample_buffer_rsp_empty_n : IN STD_LOGIC; sample_buffer_rsp_read : OUT STD_LOGIC; sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_size : IN STD_LOGIC_VECTOR (15 downto 0); begin_index : IN STD_LOGIC_VECTOR (15 downto 0); begin_sample : IN STD_LOGIC_VECTOR (15 downto 0); end_index : IN STD_LOGIC_VECTOR (15 downto 0); end_sample : IN STD_LOGIC_VECTOR (15 downto 0); stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0); accept : IN STD_LOGIC_VECTOR (0 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_accept_samples_generic_hw is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc3s200avq100-5,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.449000,HLS_SYN_LAT=154790016,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100"; constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (5 downto 0) := "101101"; constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (5 downto 0) := "101110"; constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (5 downto 0) := "101111"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_315 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_reg_320 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_fu_240_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_reg_325 : STD_LOGIC_VECTOR (0 downto 0); signal c_load_reg_329 : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_return : STD_LOGIC_VECTOR (31 downto 0); signal offset_reg_335 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal r_reg_340 : STD_LOGIC_VECTOR (0 downto 0); signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC; signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_345 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_251_p2 : STD_LOGIC_VECTOR (31 downto 0); signal c_1_reg_349 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_tmp_14 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_start : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_done : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_idle : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_ap_ready : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_ap_ce : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_194_sample_length : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_start : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_done : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_idle : STD_LOGIC; signal grp_sample_iterator_next_fu_211_ap_ready : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_ap_ce : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_211_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_211_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_211_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_211_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0); signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0); signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_sample_iterator_next_fu_211_ap_start_ap_start_reg : STD_LOGIC := '0'; signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_251_ce : STD_LOGIC; component nfa_accept_sample IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component sample_iterator_get_offset IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sample_iterator_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_nfa_accept_sample_fu_178 : component nfa_accept_sample port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_accept_sample_fu_178_ap_start, ap_done => grp_nfa_accept_sample_fu_178_ap_done, ap_idle => grp_nfa_accept_sample_fu_178_ap_idle, ap_ready => grp_nfa_accept_sample_fu_178_ap_ready, nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size, nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size, nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din, nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n, nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write, nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n, nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read, nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address, nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain, nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout, nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size, nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols, sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din, sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n, sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write, sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n, sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read, sample_address => grp_nfa_accept_sample_fu_178_sample_address, sample_datain => grp_nfa_accept_sample_fu_178_sample_datain, sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout, sample_size => grp_nfa_accept_sample_fu_178_sample_size, tmp_14 => grp_nfa_accept_sample_fu_178_tmp_14, length_r => grp_nfa_accept_sample_fu_178_length_r, ap_return => grp_nfa_accept_sample_fu_178_ap_return); grp_sample_iterator_get_offset_fu_194 : component sample_iterator_get_offset port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_get_offset_fu_194_ap_start, ap_done => grp_sample_iterator_get_offset_fu_194_ap_done, ap_idle => grp_sample_iterator_get_offset_fu_194_ap_idle, ap_ready => grp_sample_iterator_get_offset_fu_194_ap_ready, indices_stride_req_din => grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_get_offset_fu_194_indices_stride_address, indices_stride_datain => grp_sample_iterator_get_offset_fu_194_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, indices_stride_size => grp_sample_iterator_get_offset_fu_194_indices_stride_size, indices_begin_req_din => grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_get_offset_fu_194_indices_begin_address, indices_begin_datain => grp_sample_iterator_get_offset_fu_194_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, indices_begin_size => grp_sample_iterator_get_offset_fu_194_indices_begin_size, ap_ce => grp_sample_iterator_get_offset_fu_194_ap_ce, i_index => grp_sample_iterator_get_offset_fu_194_i_index, i_sample => grp_sample_iterator_get_offset_fu_194_i_sample, indices_samples_req_din => grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_get_offset_fu_194_indices_samples_address, indices_samples_datain => grp_sample_iterator_get_offset_fu_194_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, indices_samples_size => grp_sample_iterator_get_offset_fu_194_indices_samples_size, sample_buffer_size => grp_sample_iterator_get_offset_fu_194_sample_buffer_size, sample_length => grp_sample_iterator_get_offset_fu_194_sample_length, ap_return => grp_sample_iterator_get_offset_fu_194_ap_return); grp_sample_iterator_next_fu_211 : component sample_iterator_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_next_fu_211_ap_start, ap_done => grp_sample_iterator_next_fu_211_ap_done, ap_idle => grp_sample_iterator_next_fu_211_ap_idle, ap_ready => grp_sample_iterator_next_fu_211_ap_ready, indices_samples_req_din => grp_sample_iterator_next_fu_211_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_next_fu_211_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_next_fu_211_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_next_fu_211_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_next_fu_211_indices_samples_address, indices_samples_datain => grp_sample_iterator_next_fu_211_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_next_fu_211_indices_samples_dataout, indices_samples_size => grp_sample_iterator_next_fu_211_indices_samples_size, ap_ce => grp_sample_iterator_next_fu_211_ap_ce, indices_begin_req_din => grp_sample_iterator_next_fu_211_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_next_fu_211_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_next_fu_211_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_next_fu_211_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_next_fu_211_indices_begin_address, indices_begin_datain => grp_sample_iterator_next_fu_211_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_next_fu_211_indices_begin_dataout, indices_begin_size => grp_sample_iterator_next_fu_211_indices_begin_size, indices_stride_req_din => grp_sample_iterator_next_fu_211_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_next_fu_211_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_next_fu_211_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_next_fu_211_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_next_fu_211_indices_stride_address, indices_stride_datain => grp_sample_iterator_next_fu_211_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_next_fu_211_indices_stride_dataout, indices_stride_size => grp_sample_iterator_next_fu_211_indices_stride_size, i_index => grp_sample_iterator_next_fu_211_i_index, i_sample => grp_sample_iterator_next_fu_211_i_sample, ap_return_0 => grp_sample_iterator_next_fu_211_ap_return_0, ap_return_1 => grp_sample_iterator_next_fu_211_ap_return_1); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 38, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_251_p0, din1 => grp_fu_251_p1, ce => grp_fu_251_ce, dout => grp_fu_251_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. -- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; else if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg assign process. -- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_240_p2 = ap_const_lv1_0))) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_194_ap_ready)) then grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg assign process. -- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st36_fsm_35 = ap_NS_fsm) and ((ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm)))) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_211_ap_ready)) then grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- c_fu_94 assign process. -- c_fu_94_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and (or_cond_reg_345 = ap_const_lv1_0))) then c_fu_94 <= c_1_reg_349; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then c_fu_94 <= ap_const_lv32_0; end if; end if; end process; -- i_index_reg_146 assign process. -- i_index_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st47_fsm_46 = ap_CS_fsm)) then i_index_reg_146 <= grp_sample_iterator_next_fu_211_ap_return_0; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_index_reg_146 <= begin_index; end if; end if; end process; -- i_sample_reg_156 assign process. -- i_sample_reg_156_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st47_fsm_46 = ap_CS_fsm)) then i_sample_reg_156 <= grp_sample_iterator_next_fu_211_ap_return_1; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_sample_reg_156 <= begin_sample; end if; end if; end process; -- p_0_reg_166 assign process. -- p_0_reg_166_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st28_fsm_27 = ap_CS_fsm) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then p_0_reg_166 <= ap_const_lv32_1; elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_325 = ap_const_lv1_0)))) then p_0_reg_166 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then c_1_reg_349 <= grp_fu_251_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then c_load_reg_329 <= c_fu_94; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then offset_reg_335 <= grp_sample_iterator_get_offset_fu_194_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st28_fsm_27 = ap_CS_fsm)) then or_cond_reg_345 <= or_cond_fu_247_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st27_fsm_26 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then r_reg_340 <= grp_nfa_accept_sample_fu_178_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then tmp_i_10_reg_320 <= tmp_i_10_fu_235_p2; tmp_i_reg_315 <= tmp_i_fu_230_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then tmp_i_11_reg_325 <= tmp_i_11_fu_240_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , tmp_i_11_reg_325 , grp_nfa_accept_sample_fu_178_ap_done , or_cond_fu_247_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => if (not((tmp_i_11_reg_325 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st48_fsm_47; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done))) then ap_NS_fsm <= ap_ST_st28_fsm_27; else ap_NS_fsm <= ap_ST_st27_fsm_26; end if; when ap_ST_st28_fsm_27 => if ((not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st48_fsm_47; elsif (((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st29_fsm_28; else ap_NS_fsm <= ap_ST_st36_fsm_35; end if; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => ap_NS_fsm <= ap_ST_st42_fsm_41; when ap_ST_st42_fsm_41 => ap_NS_fsm <= ap_ST_st43_fsm_42; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st44_fsm_43; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => ap_NS_fsm <= ap_ST_st46_fsm_45; when ap_ST_st46_fsm_45 => ap_NS_fsm <= ap_ST_st47_fsm_46; when ap_ST_st47_fsm_46 => ap_NS_fsm <= ap_ST_st2_fsm_1; when ap_ST_st48_fsm_47 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= p_0_reg_166; grp_fu_251_ce <= ap_const_logic_1; grp_fu_251_p0 <= c_load_reg_329; grp_fu_251_p1 <= ap_const_lv32_1; grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg; grp_nfa_accept_sample_fu_178_length_r <= sample_length; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols; grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain; grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n; grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n; grp_nfa_accept_sample_fu_178_tmp_14 <= offset_reg_335; grp_sample_iterator_get_offset_fu_194_ap_ce <= ap_const_logic_1; grp_sample_iterator_get_offset_fu_194_ap_start <= grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg; grp_sample_iterator_get_offset_fu_194_i_index <= i_index_reg_146; grp_sample_iterator_get_offset_fu_194_i_sample <= i_sample_reg_156; grp_sample_iterator_get_offset_fu_194_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; grp_sample_iterator_get_offset_fu_194_sample_buffer_size <= sample_buffer_length; grp_sample_iterator_get_offset_fu_194_sample_length <= sample_length; grp_sample_iterator_next_fu_211_ap_ce <= ap_const_logic_1; grp_sample_iterator_next_fu_211_ap_start <= grp_sample_iterator_next_fu_211_ap_start_ap_start_reg; grp_sample_iterator_next_fu_211_i_index <= i_index_reg_146; grp_sample_iterator_next_fu_211_i_sample <= i_sample_reg_156; grp_sample_iterator_next_fu_211_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_next_fu_211_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_next_fu_211_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_next_fu_211_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_next_fu_211_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; -- indices_begin_address assign process. -- indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_address, grp_sample_iterator_next_fu_211_indices_begin_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_next_fu_211_indices_begin_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_get_offset_fu_194_indices_begin_address; else indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_dataout assign process. -- indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, grp_sample_iterator_next_fu_211_indices_begin_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_next_fu_211_indices_begin_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_get_offset_fu_194_indices_begin_dataout; else indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_req_din assign process. -- indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, grp_sample_iterator_next_fu_211_indices_begin_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_next_fu_211_indices_begin_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_din; else indices_begin_req_din <= 'X'; end if; end process; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, grp_sample_iterator_next_fu_211_indices_begin_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_next_fu_211_indices_begin_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_write; else indices_begin_req_write <= 'X'; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, grp_sample_iterator_next_fu_211_indices_begin_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_next_fu_211_indices_begin_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read; else indices_begin_rsp_read <= 'X'; end if; end process; -- indices_begin_size assign process. -- indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_begin_size, grp_sample_iterator_next_fu_211_indices_begin_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_next_fu_211_indices_begin_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_get_offset_fu_194_indices_begin_size; else indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_address assign process. -- indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_address, grp_sample_iterator_next_fu_211_indices_samples_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_next_fu_211_indices_samples_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_get_offset_fu_194_indices_samples_address; else indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_dataout assign process. -- indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, grp_sample_iterator_next_fu_211_indices_samples_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_next_fu_211_indices_samples_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_get_offset_fu_194_indices_samples_dataout; else indices_samples_dataout <= "XXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_req_din assign process. -- indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, grp_sample_iterator_next_fu_211_indices_samples_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_next_fu_211_indices_samples_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_din; else indices_samples_req_din <= 'X'; end if; end process; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, grp_sample_iterator_next_fu_211_indices_samples_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_next_fu_211_indices_samples_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_write; else indices_samples_req_write <= 'X'; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, grp_sample_iterator_next_fu_211_indices_samples_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_next_fu_211_indices_samples_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read; else indices_samples_rsp_read <= 'X'; end if; end process; -- indices_samples_size assign process. -- indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_samples_size, grp_sample_iterator_next_fu_211_indices_samples_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_next_fu_211_indices_samples_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_get_offset_fu_194_indices_samples_size; else indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_address assign process. -- indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_address, grp_sample_iterator_next_fu_211_indices_stride_address) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_next_fu_211_indices_stride_address; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_get_offset_fu_194_indices_stride_address; else indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_dataout assign process. -- indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, grp_sample_iterator_next_fu_211_indices_stride_dataout) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_next_fu_211_indices_stride_dataout; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_get_offset_fu_194_indices_stride_dataout; else indices_stride_dataout <= "XXXXXXXX"; end if; end process; -- indices_stride_req_din assign process. -- indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, grp_sample_iterator_next_fu_211_indices_stride_req_din) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_next_fu_211_indices_stride_req_din; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_din; else indices_stride_req_din <= 'X'; end if; end process; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, grp_sample_iterator_next_fu_211_indices_stride_req_write) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_next_fu_211_indices_stride_req_write; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_write; else indices_stride_req_write <= 'X'; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, grp_sample_iterator_next_fu_211_indices_stride_rsp_read) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_next_fu_211_indices_stride_rsp_read; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read; else indices_stride_rsp_read <= 'X'; end if; end process; -- indices_stride_size assign process. -- indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_325, grp_sample_iterator_get_offset_fu_194_indices_stride_size, grp_sample_iterator_next_fu_211_indices_stride_size) begin if (((ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st44_fsm_43 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_next_fu_211_indices_stride_size; elsif (((ap_ST_st26_fsm_25 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_325 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_get_offset_fu_194_indices_stride_size; else indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size; nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address; nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout; nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din; nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write; nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read; nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size; nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size; or_cond_fu_247_p2 <= (r_reg_340 xor accept); sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address; sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout; sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din; sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write; sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read; sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size; stop_on_first_read_read_fu_104_p2 <= stop_on_first; tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0"; tmp_i_11_fu_240_p2 <= (tmp_i_reg_315 and tmp_i_10_reg_320); tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0"; end behav;

lgpl-3.0

9001108ec1c639fbaf3680f82f61aaf8

0.640376

2.593557

false

wsoltys/AtomFpga

src/Atomic_top_papilio.vhd

1

9,115

-------------------------------------------------------------------------------- -- Copyright (c) 2009 Alan Daly. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : Atomic_top.vhf -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: Atomic_top --Device: spartan3E library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity Atomic_top_papilio is port (clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERST : in std_logic; red : out std_logic_vector (2 downto 0); green : out std_logic_vector (2 downto 0); blue : out std_logic_vector (2 downto 0); vsync : out std_logic; hsync : out std_logic; audiol : out std_logic; audioR : out std_logic; SDMISO : in std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; RxD : in std_logic; TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic; LED3 : out std_logic; LED4 : out std_logic ); end Atomic_top_papilio; architecture behavioral of Atomic_top_papilio is component dcm4 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component dcm5 port ( CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic ); end component; component RAM_2K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (10 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component RAM_8K port ( clk : in std_logic; we_uP : in std_logic; ce : in std_logic; addr_uP : in std_logic_vector (12 downto 0); D_uP : in std_logic_vector (7 downto 0); Q_uP : out std_logic_vector (7 downto 0) ); end component; component InternalROM port ( CLK : in std_logic; ADDR : in std_logic_vector(16 downto 0); DATA : out std_logic_vector(7 downto 0) ); end component; component fpgautils port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0)); end component; component Atomic_core generic ( CImplSDDOS : boolean; CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; MainClockSpeed : integer; DefaultBaud : integer ); port ( clk_vga : in std_logic; clk_16M00 : in std_logic; clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERSTn : in std_logic; IRSTn : out std_logic; SDMISO : in std_logic; red : out std_logic_vector(2 downto 0); green : out std_logic_vector(2 downto 0); blue : out std_logic_vector(2 downto 0); vsync : out std_logic; hsync : out std_logic; RamCE : out std_logic; RomCE : out std_logic; Phi2 : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (16 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout : in std_logic_vector (7 downto 0); audiol : out std_logic; audioR : out std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; uart_RxD : in std_logic; uart_TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic ); end component; signal clk_vga : std_logic; signal clk_16M00 : std_logic; signal ERSTn : std_logic; signal RamCE : std_logic; signal RomCE : std_logic; signal RomCE1 : std_logic; signal RomCE2 : std_logic; signal RamCE1 : std_logic; signal RamCE2 : std_logic; signal ExternWE : std_logic; signal ExternA : std_logic_vector (16 downto 0); signal ExternDin : std_logic_vector (7 downto 0); signal ExternDout: std_logic_vector (7 downto 0); signal RamDout1 : std_logic_vector (7 downto 0); signal RamDout2 : std_logic_vector (7 downto 0); signal RomDout1 : std_logic_vector (7 downto 0); signal RomDout2 : std_logic_vector (7 downto 0); begin inst_dcm4 : dcm4 port map( CLKIN_IN => clk_32M00, CLK0_OUT => clk_vga, CLK0_OUT1 => open, CLK2X_OUT => open); inst_dcm5 : dcm5 port map( CLKIN_IN => clk_32M00, CLK0_OUT => clk_16M00, CLK0_OUT1 => open, CLK2X_OUT => open); ram_0000_07ff : RAM_2K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE1, addr_uP => ExternA (10 downto 0), D_uP => ExternDin, Q_uP => RamDout1 ); ram_2000_3fff : RAM_8K port map( clk => clk_16M00, we_uP => ExternWE, ce => RamCE2, addr_uP => ExternA (12 downto 0), D_uP => ExternDin, Q_uP => RamDout2 ); rom_c000_ffff : InternalROM port map( CLK => clk_16M00, ADDR => ExternA, DATA => RomDout1 ); rom_a000 : fpgautils port map( CLK => clk_16M00, ADDR => ExternA(11 downto 0), DATA => RomDout2 ); RamCE1 <= '1' when RamCE = '1' and ExternA(14 downto 11) = "0000" else '0'; RamCE2 <= '1' when RamCE = '1' and ExternA(14 downto 13) = "01" else '0'; RomCE1 <= '1' when RomCE = '1' and ExternA(15 downto 14) = "11" else '0'; RomCE2 <= '1' when RomCE = '1' and ExternA(15 downto 12) = "1010" else '0'; ExternDout(7 downto 0) <= RamDout1 when RamCE1 = '1' else RamDout2 when RamCE2 = '1' else RomDout1 when RomCE1 = '1' else RomDout2 when RomCE2 = '1' else "11110001"; ERSTn <= not ERST; inst_Atomic_core : Atomic_core generic map ( CImplSDDOS => true, CImplGraphicsExt => true, CImplSoftChar => false, CImplSID => true, CImplVGA80x40 => true, CImplHWScrolling => true, CImplMouse => true, CImplUart => true, MainClockSpeed => 16000000, DefaultBaud => 115200 ) port map( clk_vga => clk_vga, clk_16M00 => clk_16M00, clk_32M00 => clk_32M00, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_mouse_clk => ps2_mouse_clk, ps2_mouse_data => ps2_mouse_data, ERSTn => ERSTn, red => red, green => green, blue => blue, vsync => vsync, hsync => hsync, Phi2 => open, RamCE => RamCE, RomCE => RomCE, ExternWE => ExternWE, ExternA => ExternA, ExternDin => ExternDin, ExternDout=> ExternDout, audiol => audiol, audioR => audioR, SDMISO => SDMISO, SDSS => SDSS, SDCLK => SDCLK, SDMOSI => SDMOSI, uart_RxD => RxD, uart_TxD => TxD, LED1 => LED1, LED2 => LED2 ); LED3 <= '0'; LED4 <= '0'; end behavioral;

apache-2.0

99ad0e800dab96145c1b184b6e6c0b89

0.451454

3.643086

false

jairov4/accel-oil

solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/sample_buffer_if_ap_fifo.vhd

2

2,831

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sample_buffer_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC := '1'; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC := '1'; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of sample_buffer_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;

lgpl-3.0

3507e094a5f76efd4b35a193bb707c7f

0.494172

3.671855

false

wsoltys/AtomFpga

src/AVR8/CommonPacks/std_library.vhd

1

10,374

-- ***************************************************************************************** -- Standard libraries -- Version 0.2 -- Modified 02.12.2006 -- Designed by Ruslan Lepetenok -- ***************************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package std_library is type log2array_type is array(0 to 1024) of integer; constant fn_log2 : log2array_type := ( 0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, others => 10); constant fn_log2x : log2array_type := ( 0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, others => 10); -- ********************************************************************************* function fn_det_x(d : std_logic_vector) return boolean; function fn_det_x(d : std_logic) return boolean; function fn_xor_vect(vect : std_logic_vector) return std_logic; function fn_or_vect(vect : std_logic_vector) return std_logic; function fn_and_vect(vect : std_logic_vector) return std_logic; function fn_to_integer(vect : std_logic_vector) return integer; function fn_to_integer(d : std_logic) return integer; function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector; function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector; function fn_to_std_logic(b : boolean) return std_logic; function fn_dcd(vect : std_logic_vector) return std_logic_vector; function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic; function "+" (vect : std_logic_vector; int : integer) return std_logic_vector; function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector; function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector; function "-" (vect : std_logic_vector; int : integer) return std_logic_vector; function "-" (int : integer; vect : std_logic_vector) return std_logic_vector; function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector; function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector; end std_library; package body std_library is function fn_det_x(d : std_logic_vector) return boolean is variable result : boolean; begin result := FALSE; -- pragma translate_off result := is_x(d); -- pragma translate_on return (result); end fn_det_x; function fn_det_x(d : std_logic) return boolean is variable result : boolean; begin result := FALSE; -- pragma translate_off result := is_x(d); -- pragma translate_on return (result); end fn_det_x; function fn_xor_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '0'; for i in vect'range loop temp := temp xor vect(i); end loop; return(temp); end fn_xor_vect; function fn_or_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '0'; for i in vect'range loop temp := temp or vect(i); end loop; return(temp); end fn_or_vect; function fn_and_vect(vect : std_logic_vector) return std_logic is variable temp : std_logic; begin temp := '1'; for i in vect'range loop temp := temp and vect(i); end loop; return(temp); end fn_and_vect; function fn_to_integer(vect : std_logic_vector) return integer is begin if (not fn_det_x(vect)) then return(to_integer(unsigned(vect))); else return(0); end if; end fn_to_integer; function fn_to_integer(d : std_logic) return integer is begin if (not fn_det_x(d)) then if (d = '1') then return(1); else return(0); end if; else return(0); end if; end fn_to_integer; function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is variable temp : std_logic_vector(width-1 downto 0); begin temp := std_logic_vector(to_unsigned(int, width)); return(temp); end fn_to_std_logic_vector; function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is variable temp : std_logic_vector(width-1 downto 0); begin temp := std_logic_vector(to_signed(int, width)); return(temp); end fn_to_std_logic_vector_signed; function fn_to_std_logic(b : boolean) return std_logic is begin if (b) then return('1'); else return('0'); end if; end fn_to_std_logic; function fn_dcd(vect : std_logic_vector) return std_logic_vector is variable result : std_logic_vector((2**vect'length)-1 downto 0); variable i : integer range result'range; begin result := (others => '0'); i := 0; if (not fn_det_x(vect)) then i := to_integer(unsigned(vect)); end if; result(i) := '1'; return(result); end fn_dcd; function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is variable result : std_logic_vector(vect'length-1 downto 0); variable i : integer range result'range; begin result := vect; i := 0; if (not fn_det_x(sel)) then i := to_integer(unsigned(sel)); end if; return(result(i)); end fn_mux; -- >>>> function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is variable tmp_a : std_logic_vector(vect_a'length-1 downto 0); variable tmp_b : std_logic_vector(vect_b'length-1 downto 0); begin if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b))); -- pragma translate_off else tmp_a := (others =>'X'); tmp_b := (others =>'X'); if (tmp_a'length > tmp_b'length) then return(tmp_a); else return(tmp_b); end if; -- pragma translate_on end if; end "+"; function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(unsigned(vect) + int)); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "+"; function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is variable tmp_a : std_logic_vector(vect'length-1 downto 0); variable tmp_b : std_logic_vector(0 downto 0); begin tmp_b(0) := d; if (not (fn_det_x(vect) or fn_det_x(d))) then return(std_logic_vector(unsigned(vect) + unsigned(tmp_b))); -- pragma translate_off else tmp_b := (others =>'X'); return(tmp_b); -- pragma translate_on end if; end "+"; function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is variable tmp_a : std_logic_vector(vect_a'length-1 downto 0); variable tmp_b : std_logic_vector(vect_b'length-1 downto 0); begin if (not (fn_det_x(vect_a) or fn_det_x(vect_b))) then return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b))); -- pragma translate_off else tmp_a := (others =>'X'); tmp_b := (others =>'X'); if (tmp_a'length > tmp_b'length) then return(tmp_a); else return(tmp_b); end if; -- pragma translate_on end if; end "-"; function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(unsigned(vect) - int)); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "-"; function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is variable temp : std_logic_vector(vect'length-1 downto 0); begin if (not fn_det_x(vect)) then return(std_logic_vector(int - unsigned(vect))); -- pragma translate_off else temp := (others =>'X'); return(temp); -- pragma translate_on end if; end "-"; function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is variable tmp_a : std_logic_vector(vect'length-1 downto 0); variable tmp_b : std_logic_vector(0 downto 0); begin tmp_b(0) := d; if (not (fn_det_x(vect) or fn_det_x(d))) then return(std_logic_vector(unsigned(vect) - unsigned(tmp_b))); -- pragma translate_off else tmp_a := (others =>'X'); return(tmp_a); -- pragma translate_on end if; end "-"; end std_library;

apache-2.0

d57c3c833d710d8be334341d1bcc2cbd

0.600733

2.175755

false

jairov4/accel-oil

impl/impl_test_pcie/simulation/behavioral/system_mdm_0_wrapper.vhd

1

38,992

------------------------------------------------------------------------------- -- system_mdm_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library mdm_v2_10_a; use mdm_v2_10_a.all; entity system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end system_mdm_0_wrapper; architecture STRUCTURE of system_mdm_0_wrapper is component mdm is generic ( C_FAMILY : STRING; C_JTAG_CHAIN : INTEGER; C_INTERCONNECT : INTEGER; C_BASEADDR : STD_LOGIC_VECTOR; C_HIGHADDR : STD_LOGIC_VECTOR; C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_MB_DBG_PORTS : INTEGER; C_USE_UART : INTEGER; C_USE_BSCAN : integer; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; begin mdm_0 : mdm generic map ( C_FAMILY => "virtex5", C_JTAG_CHAIN => 2, C_INTERCONNECT => 1, C_BASEADDR => X"84400000", C_HIGHADDR => X"8440ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 64, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 3, C_SPLB_NUM_MASTERS => 6, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 1, C_MB_DBG_PORTS => 1, C_USE_UART => 1, C_USE_BSCAN => 0, C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32 ) port map ( Interrupt => Interrupt, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Dbg_Clk_0 => Dbg_Clk_0, Dbg_TDI_0 => Dbg_TDI_0, Dbg_TDO_0 => Dbg_TDO_0, Dbg_Reg_En_0 => Dbg_Reg_En_0, Dbg_Capture_0 => Dbg_Capture_0, Dbg_Shift_0 => Dbg_Shift_0, Dbg_Update_0 => Dbg_Update_0, Dbg_Rst_0 => Dbg_Rst_0, Dbg_Clk_1 => Dbg_Clk_1, Dbg_TDI_1 => Dbg_TDI_1, Dbg_TDO_1 => Dbg_TDO_1, Dbg_Reg_En_1 => Dbg_Reg_En_1, Dbg_Capture_1 => Dbg_Capture_1, Dbg_Shift_1 => Dbg_Shift_1, Dbg_Update_1 => Dbg_Update_1, Dbg_Rst_1 => Dbg_Rst_1, Dbg_Clk_2 => Dbg_Clk_2, Dbg_TDI_2 => Dbg_TDI_2, Dbg_TDO_2 => Dbg_TDO_2, Dbg_Reg_En_2 => Dbg_Reg_En_2, Dbg_Capture_2 => Dbg_Capture_2, Dbg_Shift_2 => Dbg_Shift_2, Dbg_Update_2 => Dbg_Update_2, Dbg_Rst_2 => Dbg_Rst_2, Dbg_Clk_3 => Dbg_Clk_3, Dbg_TDI_3 => Dbg_TDI_3, Dbg_TDO_3 => Dbg_TDO_3, Dbg_Reg_En_3 => Dbg_Reg_En_3, Dbg_Capture_3 => Dbg_Capture_3, Dbg_Shift_3 => Dbg_Shift_3, Dbg_Update_3 => Dbg_Update_3, Dbg_Rst_3 => Dbg_Rst_3, Dbg_Clk_4 => Dbg_Clk_4, Dbg_TDI_4 => Dbg_TDI_4, Dbg_TDO_4 => Dbg_TDO_4, Dbg_Reg_En_4 => Dbg_Reg_En_4, Dbg_Capture_4 => Dbg_Capture_4, Dbg_Shift_4 => Dbg_Shift_4, Dbg_Update_4 => Dbg_Update_4, Dbg_Rst_4 => Dbg_Rst_4, Dbg_Clk_5 => Dbg_Clk_5, Dbg_TDI_5 => Dbg_TDI_5, Dbg_TDO_5 => Dbg_TDO_5, Dbg_Reg_En_5 => Dbg_Reg_En_5, Dbg_Capture_5 => Dbg_Capture_5, Dbg_Shift_5 => Dbg_Shift_5, Dbg_Update_5 => Dbg_Update_5, Dbg_Rst_5 => Dbg_Rst_5, Dbg_Clk_6 => Dbg_Clk_6, Dbg_TDI_6 => Dbg_TDI_6, Dbg_TDO_6 => Dbg_TDO_6, Dbg_Reg_En_6 => Dbg_Reg_En_6, Dbg_Capture_6 => Dbg_Capture_6, Dbg_Shift_6 => Dbg_Shift_6, Dbg_Update_6 => Dbg_Update_6, Dbg_Rst_6 => Dbg_Rst_6, Dbg_Clk_7 => Dbg_Clk_7, Dbg_TDI_7 => Dbg_TDI_7, Dbg_TDO_7 => Dbg_TDO_7, Dbg_Reg_En_7 => Dbg_Reg_En_7, Dbg_Capture_7 => Dbg_Capture_7, Dbg_Shift_7 => Dbg_Shift_7, Dbg_Update_7 => Dbg_Update_7, Dbg_Rst_7 => Dbg_Rst_7, Dbg_Clk_8 => Dbg_Clk_8, Dbg_TDI_8 => Dbg_TDI_8, Dbg_TDO_8 => Dbg_TDO_8, Dbg_Reg_En_8 => Dbg_Reg_En_8, Dbg_Capture_8 => Dbg_Capture_8, Dbg_Shift_8 => Dbg_Shift_8, Dbg_Update_8 => Dbg_Update_8, Dbg_Rst_8 => Dbg_Rst_8, Dbg_Clk_9 => Dbg_Clk_9, Dbg_TDI_9 => Dbg_TDI_9, Dbg_TDO_9 => Dbg_TDO_9, Dbg_Reg_En_9 => Dbg_Reg_En_9, Dbg_Capture_9 => Dbg_Capture_9, Dbg_Shift_9 => Dbg_Shift_9, Dbg_Update_9 => Dbg_Update_9, Dbg_Rst_9 => Dbg_Rst_9, Dbg_Clk_10 => Dbg_Clk_10, Dbg_TDI_10 => Dbg_TDI_10, Dbg_TDO_10 => Dbg_TDO_10, Dbg_Reg_En_10 => Dbg_Reg_En_10, Dbg_Capture_10 => Dbg_Capture_10, Dbg_Shift_10 => Dbg_Shift_10, Dbg_Update_10 => Dbg_Update_10, Dbg_Rst_10 => Dbg_Rst_10, Dbg_Clk_11 => Dbg_Clk_11, Dbg_TDI_11 => Dbg_TDI_11, Dbg_TDO_11 => Dbg_TDO_11, Dbg_Reg_En_11 => Dbg_Reg_En_11, Dbg_Capture_11 => Dbg_Capture_11, Dbg_Shift_11 => Dbg_Shift_11, Dbg_Update_11 => Dbg_Update_11, Dbg_Rst_11 => Dbg_Rst_11, Dbg_Clk_12 => Dbg_Clk_12, Dbg_TDI_12 => Dbg_TDI_12, Dbg_TDO_12 => Dbg_TDO_12, Dbg_Reg_En_12 => Dbg_Reg_En_12, Dbg_Capture_12 => Dbg_Capture_12, Dbg_Shift_12 => Dbg_Shift_12, Dbg_Update_12 => Dbg_Update_12, Dbg_Rst_12 => Dbg_Rst_12, Dbg_Clk_13 => Dbg_Clk_13, Dbg_TDI_13 => Dbg_TDI_13, Dbg_TDO_13 => Dbg_TDO_13, Dbg_Reg_En_13 => Dbg_Reg_En_13, Dbg_Capture_13 => Dbg_Capture_13, Dbg_Shift_13 => Dbg_Shift_13, Dbg_Update_13 => Dbg_Update_13, Dbg_Rst_13 => Dbg_Rst_13, Dbg_Clk_14 => Dbg_Clk_14, Dbg_TDI_14 => Dbg_TDI_14, Dbg_TDO_14 => Dbg_TDO_14, Dbg_Reg_En_14 => Dbg_Reg_En_14, Dbg_Capture_14 => Dbg_Capture_14, Dbg_Shift_14 => Dbg_Shift_14, Dbg_Update_14 => Dbg_Update_14, Dbg_Rst_14 => Dbg_Rst_14, Dbg_Clk_15 => Dbg_Clk_15, Dbg_TDI_15 => Dbg_TDI_15, Dbg_TDO_15 => Dbg_TDO_15, Dbg_Reg_En_15 => Dbg_Reg_En_15, Dbg_Capture_15 => Dbg_Capture_15, Dbg_Shift_15 => Dbg_Shift_15, Dbg_Update_15 => Dbg_Update_15, Dbg_Rst_15 => Dbg_Rst_15, Dbg_Clk_16 => Dbg_Clk_16, Dbg_TDI_16 => Dbg_TDI_16, Dbg_TDO_16 => Dbg_TDO_16, Dbg_Reg_En_16 => Dbg_Reg_En_16, Dbg_Capture_16 => Dbg_Capture_16, Dbg_Shift_16 => Dbg_Shift_16, Dbg_Update_16 => Dbg_Update_16, Dbg_Rst_16 => Dbg_Rst_16, Dbg_Clk_17 => Dbg_Clk_17, Dbg_TDI_17 => Dbg_TDI_17, Dbg_TDO_17 => Dbg_TDO_17, Dbg_Reg_En_17 => Dbg_Reg_En_17, Dbg_Capture_17 => Dbg_Capture_17, Dbg_Shift_17 => Dbg_Shift_17, Dbg_Update_17 => Dbg_Update_17, Dbg_Rst_17 => Dbg_Rst_17, Dbg_Clk_18 => Dbg_Clk_18, Dbg_TDI_18 => Dbg_TDI_18, Dbg_TDO_18 => Dbg_TDO_18, Dbg_Reg_En_18 => Dbg_Reg_En_18, Dbg_Capture_18 => Dbg_Capture_18, Dbg_Shift_18 => Dbg_Shift_18, Dbg_Update_18 => Dbg_Update_18, Dbg_Rst_18 => Dbg_Rst_18, Dbg_Clk_19 => Dbg_Clk_19, Dbg_TDI_19 => Dbg_TDI_19, Dbg_TDO_19 => Dbg_TDO_19, Dbg_Reg_En_19 => Dbg_Reg_En_19, Dbg_Capture_19 => Dbg_Capture_19, Dbg_Shift_19 => Dbg_Shift_19, Dbg_Update_19 => Dbg_Update_19, Dbg_Rst_19 => Dbg_Rst_19, Dbg_Clk_20 => Dbg_Clk_20, Dbg_TDI_20 => Dbg_TDI_20, Dbg_TDO_20 => Dbg_TDO_20, Dbg_Reg_En_20 => Dbg_Reg_En_20, Dbg_Capture_20 => Dbg_Capture_20, Dbg_Shift_20 => Dbg_Shift_20, Dbg_Update_20 => Dbg_Update_20, Dbg_Rst_20 => Dbg_Rst_20, Dbg_Clk_21 => Dbg_Clk_21, Dbg_TDI_21 => Dbg_TDI_21, Dbg_TDO_21 => Dbg_TDO_21, Dbg_Reg_En_21 => Dbg_Reg_En_21, Dbg_Capture_21 => Dbg_Capture_21, Dbg_Shift_21 => Dbg_Shift_21, Dbg_Update_21 => Dbg_Update_21, Dbg_Rst_21 => Dbg_Rst_21, Dbg_Clk_22 => Dbg_Clk_22, Dbg_TDI_22 => Dbg_TDI_22, Dbg_TDO_22 => Dbg_TDO_22, Dbg_Reg_En_22 => Dbg_Reg_En_22, Dbg_Capture_22 => Dbg_Capture_22, Dbg_Shift_22 => Dbg_Shift_22, Dbg_Update_22 => Dbg_Update_22, Dbg_Rst_22 => Dbg_Rst_22, Dbg_Clk_23 => Dbg_Clk_23, Dbg_TDI_23 => Dbg_TDI_23, Dbg_TDO_23 => Dbg_TDO_23, Dbg_Reg_En_23 => Dbg_Reg_En_23, Dbg_Capture_23 => Dbg_Capture_23, Dbg_Shift_23 => Dbg_Shift_23, Dbg_Update_23 => Dbg_Update_23, Dbg_Rst_23 => Dbg_Rst_23, Dbg_Clk_24 => Dbg_Clk_24, Dbg_TDI_24 => Dbg_TDI_24, Dbg_TDO_24 => Dbg_TDO_24, Dbg_Reg_En_24 => Dbg_Reg_En_24, Dbg_Capture_24 => Dbg_Capture_24, Dbg_Shift_24 => Dbg_Shift_24, Dbg_Update_24 => Dbg_Update_24, Dbg_Rst_24 => Dbg_Rst_24, Dbg_Clk_25 => Dbg_Clk_25, Dbg_TDI_25 => Dbg_TDI_25, Dbg_TDO_25 => Dbg_TDO_25, Dbg_Reg_En_25 => Dbg_Reg_En_25, Dbg_Capture_25 => Dbg_Capture_25, Dbg_Shift_25 => Dbg_Shift_25, Dbg_Update_25 => Dbg_Update_25, Dbg_Rst_25 => Dbg_Rst_25, Dbg_Clk_26 => Dbg_Clk_26, Dbg_TDI_26 => Dbg_TDI_26, Dbg_TDO_26 => Dbg_TDO_26, Dbg_Reg_En_26 => Dbg_Reg_En_26, Dbg_Capture_26 => Dbg_Capture_26, Dbg_Shift_26 => Dbg_Shift_26, Dbg_Update_26 => Dbg_Update_26, Dbg_Rst_26 => Dbg_Rst_26, Dbg_Clk_27 => Dbg_Clk_27, Dbg_TDI_27 => Dbg_TDI_27, Dbg_TDO_27 => Dbg_TDO_27, Dbg_Reg_En_27 => Dbg_Reg_En_27, Dbg_Capture_27 => Dbg_Capture_27, Dbg_Shift_27 => Dbg_Shift_27, Dbg_Update_27 => Dbg_Update_27, Dbg_Rst_27 => Dbg_Rst_27, Dbg_Clk_28 => Dbg_Clk_28, Dbg_TDI_28 => Dbg_TDI_28, Dbg_TDO_28 => Dbg_TDO_28, Dbg_Reg_En_28 => Dbg_Reg_En_28, Dbg_Capture_28 => Dbg_Capture_28, Dbg_Shift_28 => Dbg_Shift_28, Dbg_Update_28 => Dbg_Update_28, Dbg_Rst_28 => Dbg_Rst_28, Dbg_Clk_29 => Dbg_Clk_29, Dbg_TDI_29 => Dbg_TDI_29, Dbg_TDO_29 => Dbg_TDO_29, Dbg_Reg_En_29 => Dbg_Reg_En_29, Dbg_Capture_29 => Dbg_Capture_29, Dbg_Shift_29 => Dbg_Shift_29, Dbg_Update_29 => Dbg_Update_29, Dbg_Rst_29 => Dbg_Rst_29, Dbg_Clk_30 => Dbg_Clk_30, Dbg_TDI_30 => Dbg_TDI_30, Dbg_TDO_30 => Dbg_TDO_30, Dbg_Reg_En_30 => Dbg_Reg_En_30, Dbg_Capture_30 => Dbg_Capture_30, Dbg_Shift_30 => Dbg_Shift_30, Dbg_Update_30 => Dbg_Update_30, Dbg_Rst_30 => Dbg_Rst_30, Dbg_Clk_31 => Dbg_Clk_31, Dbg_TDI_31 => Dbg_TDI_31, Dbg_TDO_31 => Dbg_TDO_31, Dbg_Reg_En_31 => Dbg_Reg_En_31, Dbg_Capture_31 => Dbg_Capture_31, Dbg_Shift_31 => Dbg_Shift_31, Dbg_Update_31 => Dbg_Update_31, Dbg_Rst_31 => Dbg_Rst_31, bscan_tdi => bscan_tdi, bscan_reset => bscan_reset, bscan_shift => bscan_shift, bscan_update => bscan_update, bscan_capture => bscan_capture, bscan_sel1 => bscan_sel1, bscan_drck1 => bscan_drck1, bscan_tdo1 => bscan_tdo1, bscan_ext_tdi => bscan_ext_tdi, bscan_ext_reset => bscan_ext_reset, bscan_ext_shift => bscan_ext_shift, bscan_ext_update => bscan_ext_update, bscan_ext_capture => bscan_ext_capture, bscan_ext_sel => bscan_ext_sel, bscan_ext_drck => bscan_ext_drck, bscan_ext_tdo => bscan_ext_tdo, Ext_JTAG_DRCK => Ext_JTAG_DRCK, Ext_JTAG_RESET => Ext_JTAG_RESET, Ext_JTAG_SEL => Ext_JTAG_SEL, Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE, Ext_JTAG_SHIFT => Ext_JTAG_SHIFT, Ext_JTAG_UPDATE => Ext_JTAG_UPDATE, Ext_JTAG_TDI => Ext_JTAG_TDI, Ext_JTAG_TDO => Ext_JTAG_TDO ); end architecture STRUCTURE;

lgpl-3.0

67516c6c77ac3e0a64def9cc33d5773b

0.575528

2.800144

false

jairov4/accel-oil

solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_forward_buckets_if_plb_master_if.vhd

2

37,013

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end entity; architecture rtl of nfa_forward_buckets_if_ap_fifo_uw is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype; signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0); signal internal_empty_n, internal_full_n : STD_LOGIC; signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0); begin mNextInPtr <= mInPtr + 1; if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; use_word <= internal_use_word; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); internal_use_word <= (others => '0'); else if clk'event and clk = '1' then if if_read = '1' and internal_empty_n = '1' then mOutPtr <= mOutPtr + 1; end if; if if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; mInPtr <= mNextInPtr; end if; if (if_read = '1' and if_write = '0') then internal_use_word <= internal_use_word - '1'; elsif (if_read = '0' and if_write = '1') then internal_use_word <= internal_use_word + '1'; end if; end if; end if; end process; process (mInPtr, mOutPtr, mNextInPtr) begin if mInPtr = mOutPtr then internal_empty_n <= '0'; else internal_empty_n <= '1'; end if; if mNextInPtr = mOutPtr then internal_full_n <= '0'; else internal_full_n <= '1'; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3 ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- physical address BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n: out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of PLB_Clk : signal is "Clk"; attribute SIGIS of PLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of nfa_forward_buckets_if_plb_master_if is component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end component; component nfa_forward_buckets_if_ap_fifo_uw is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0)); end component; constant PLB_DW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := PLB_DW/8; constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size constant FIFO_ADDR_WIDTH : integer := 5; constant FIFO_DEPTH : integer := 32; -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0); -- burst write counter (only push burst data in and ignore all burst write request except the first one) signal req_burst_write: STD_LOGIC; -- whether last request is a burst write signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0); -- write data FIFO (for bus write data) signal wd_fifo_empty_n : STD_LOGIC; signal wd_fifo_pop : STD_LOGIC; signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_full_n : STD_LOGIC; signal wd_fifo_push : STD_LOGIC; signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); -- read data FIFO (for bus read returned data) signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0); signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0); signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1 signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block signal request, req_nRW: std_logic; signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal pending_rd_req_burst_mode: std_logic; signal pending_rd_req_burst_size: std_logic_vector(3 downto 0); signal pending_wr_req_burst_mode: std_logic; signal pending_wr_req_burst_size: std_logic_vector(3 downto 0); signal pending_read, pending_write: std_logic; signal burst_mode, burst_last : std_logic; signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words --signals for write data mirror signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal conv_counter_comb: std_logic_vector(1 downto 0); signal wr_data_phase : std_logic; signal dataConv_last: std_logic; signal dp_dataConv_last: std_logic; signal dp_dataConv_word_addr: std_logic_vector(1 downto 0); signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64 signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0); signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0); signal dp_PLB_MSSize : std_logic_vector(1 downto 0); --signals for read data mirror signal PLB_MRdDAck_reg : std_logic; signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64 signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0); signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0); -- signals with dp_ prefix stand for data phase signals -- signals with req_ prefix stand for request phase signals begin -- interface to user logic BUS_RdData <= rd_fifo_dout; BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n; BUS_rsp_nRW <= '0'; BUS_rsp_empty_n <= rd_fifo_empty_n; -- interface to PLB M_abort <= '0'; M_busLock <= '0'; M_lockErr <= '0'; M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst M_type <= "000"; -- memory trans M_priority <= "00"; M_RNW <= not req_nRW; M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0'; process (PLB_MSSize) begin M_wrBurst <= '0'; if (pending_wr_req_burst_mode = '1' and (pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then M_wrBurst <= '1'; elsif (request = '1' and req_nRW = '1' and pending_write = '0' and burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then M_wrBurst <= '1'; end if; end process; -- write data mirror section process (PLB_MSSize) begin if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then conv_mode_comb <= "10"; -- conv 64:32 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then conv_mode_comb <= "11"; -- conv 128:64 conv_counter_comb <= "01"; elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then conv_mode_comb <= "01"; -- conv 128:32 conv_counter_comb <= "11"; else conv_mode_comb <= "00"; -- do not need conv conv_counter_comb <= "00"; end if; end process; process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE) begin dataConv_last <= '0'; if (burst_mode = '0' or burst_size = "0000") then if (conv_mode_comb = "00") then -- no conv dataConv_last <= '1'; elsif (conv_mode_comb = "10") then -- 64:32 conv if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "11") then -- 128:64 conv if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; end if; elsif (conv_mode_comb = "01") then -- 128:32 conv if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then dataConv_last <= '1'; elsif (req_address(28 to 29) = "11") then dataConv_last <= '1'; end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_word_addr <= (others => '0'); dp_dataConv_wd_conv_mode <= (others =>'0'); dp_dataConv_wd_burst_counter <= (others => '0'); dp_dataConv_wd_BE <= (others => '0'); dp_dataConv_last <= '0'; wr_data_phase <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then dp_dataConv_wd_BE <= req_BE; dp_dataConv_last <= dataConv_last; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and (PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then wr_data_phase <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0')) then wr_data_phase <= '0'; end if; end if; if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then if (PLB_MWrDAck = '0') then -- only AddrAck asserted dp_dataConv_wd_conv_mode <= conv_mode_comb; dp_dataConv_word_addr <= req_address(28 to 29); dp_dataConv_wd_burst_counter <= conv_counter_comb; else -- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle if (dataConv_last = '0') then dp_dataConv_wd_conv_mode <= conv_mode_comb; end if; if (PLB_MSSize = "00") then -- 32 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +1; elsif (PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= req_address(28 to 29) +2; end if; if (conv_mode_comb /= "00") then -- need conv dp_dataConv_wd_burst_counter <= conv_counter_comb -1; end if; end if; end if; if (wr_data_phase = '1' and PLB_MWrDAck = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or (pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then dp_dataConv_wd_conv_mode <= "00"; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1') then if (dp_PLB_MSSize = "01") then -- 64 bits slave dp_dataConv_word_addr <= dp_dataConv_word_addr +2; else dp_dataConv_word_addr <= dp_dataConv_word_addr +1; end if; if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or dp_dataConv_wd_burst_counter /= "00") then if (dp_dataConv_wd_burst_counter = "00") then if (dp_dataConv_wd_conv_mode = "01") then -- 128/32 dp_dataConv_wd_burst_counter <= "11"; elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_wd_burst_counter <= "01"; end if; else dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1; end if; end if; end if; end if; end process; process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE) begin wd_fifo_pop <= '0'; if (PLB_MWrDAck = '1') then if (wr_data_phase = '1') then if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or (dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or dp_dataConv_wd_conv_mode = "00" )then wd_fifo_pop <= '1'; end if; else -- got addrAck and wrDAck at the same cycle if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then wd_fifo_pop <= '1'; elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then wd_fifo_pop <= '1'; end if; end if; end if; end process; process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr) begin wd_fifo_dout_mirror <= wd_fifo_dout; if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert if (C_PLB_DWIDTH = 32) then wd_fifo_dout_mirror <= wd_fifo_dout; elsif (C_PLB_DWIDTH = 64) then if (req_address(29) = '0') then wd_fifo_dout_mirror <= wd_fifo_dout; else wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2); end if; elsif (C_PLB_DWIDTH = 128) then case req_address(28 to 29) is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; else -- in data phase wd_fifo_dout_mirror <= wd_fifo_dout; if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or (dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64 wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2); elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32 case dp_dataConv_word_addr is when "00" => wd_fifo_dout_mirror <= wd_fifo_dout; when "01" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4); when "10" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2); when "11" => wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4); when others => null; end case; end if; end if; end process; process(wd_fifo_dout_mirror) variable i: integer; begin for i in 0 to C_PLB_DWIDTH-1 loop M_wrDBus(i) <= wd_fifo_dout_mirror(i); end loop; end process; process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word, pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size) begin M_request <= '0'; if (request = '1') then if (req_nRW = '0' and pending_read = '0') then -- read request if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then M_request <= '1'; elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available M_request <= '1'; end if; elsif (req_nRW = '1' and pending_write = '0') then -- write request if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then M_request <= '1'; elsif (wd_fifo_use_word > burst_size) then M_request <= '1'; end if; end if; end if; end process; M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address; process(req_nRW, burst_mode, burst_size, req_BE) variable i:integer; begin M_BE <= (others => '0'); if (burst_mode = '1') then if (burst_size = "0000") then M_BE <= (others => '1'); -- first single,then burst 16 else M_BE(0 to 3) <= burst_size; -- fixed length burst end if; elsif (req_nRW = '0') then M_BE <= (others => '1'); else for i in 0 to PLB_BYTE_COUNT-1 loop M_BE(i) <= req_BE(i); end loop; end if; end process; -- user req FIFO, for both read request and write request U_req_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_WIDTH, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_push <= BUS_req_push and not req_burst_write; req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size; req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then req_burst_write <= '0'; req_burst_write_counter <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_write <= '1'; req_burst_write_counter <= BUS_size - 1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then req_burst_write_counter <= req_burst_write_counter -1; end if; if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data req_burst_write <= '0'; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then request <= '0'; req_size <= (others => '0'); req_nRW <= '0'; req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0'); burst_mode <= '0'; burst_size <= (others => '0'); req_fifo_pop <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then req_fifo_pop <= '0'; if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then request <= '1'; if (conv_mode_comb(1) = '1') then -- 2:1 conv req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0'); else -- 128:32 if (req_address(28 to 29) = "00") then req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0'); elsif (req_address(28 to 29) = "01") then req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0'); elsif (req_address(28 to 29) = "10") then req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0'); end if; end if; if (PLB_MSSize = "00") then -- 32 bits slave req_address <= req_address + 4; elsif (PLB_MSSize = "01") then -- 64 slave req_address <= req_address + 8; end if;-- 128 bits slave does not need conversion cycle elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then request <= '1'; -- req next burst section, this will be pending until previous burst finished req_size(0 to 27) <= req_size(0 to 27) - 1; req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1; req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); -- low bits of addr must be reset for possible data_conv modifications of 10 lines above burst_mode <= '1'; burst_size <= "1111"; -- burst 16 words else if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; end if; request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1); req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64); req_address <= req_fifo_dout(63 downto 32); if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0'); end if; -- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst burst_mode <= req_fifo_empty_n; -- fetched req may be null req -- req of burst 17 will be single + burst 16, please check burst_size also else burst_mode <= '0'; end if; burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words end if; end if; end if; end process; process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_read <= '0'; pending_write <= '0'; dp_PLB_MSSize <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or (pending_rd_req_burst_mode = '0'))) then pending_read <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='0') then pending_read <= '1'; end if; if (PLB_MWrDAck = '1' and wr_data_phase = '1' and ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or pending_wr_req_burst_mode = '0')) then pending_write <= '0'; elsif (PLB_MAddrAck = '1' and req_nRW='1' and (PLB_MWrDAck = '0' or burst_size /= "0000")) then pending_write <= '1'; end if; if (PLB_MAddrAck = '1') then dp_PLB_MSSize <= PLB_MSSize; end if; end if; end process; process(req_size) begin if (req_size(0 to 27) = "000000000000000000000000000") then burst_last <= '1'; -- one request is ok else burst_last <= '0'; end if; end process; -- user write data FIFO, for data of bus write request U_wd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => wd_fifo_empty_n, if_read => wd_fifo_pop, if_dout => wd_fifo_dout, if_full_n => wd_fifo_full_n, if_write => wd_fifo_push, if_din => wd_fifo_din, use_word => wd_fifo_use_word ); wd_fifo_push <= BUS_req_push and BUS_req_nRW; wd_fifo_din <= BUS_WrData; -- returned bus read data fifo U_rd_nfa_forward_buckets_if_fifo: component nfa_forward_buckets_if_ap_fifo_uw generic map( DATA_WIDTH => PLB_DW, ADDR_WIDTH => FIFO_ADDR_WIDTH, DEPTH => FIFO_DEPTH) port map( clk => PLB_Clk, reset => PLB_Rst, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, if_write => rd_fifo_push, if_din => rd_fifo_din, use_word => rd_fifo_use_word ); process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then dp_dataConv_rd_conv_mode <= (others =>'0'); dp_dataConv_rd_burst_counter <= (others => '0'); dp_dataConv_rd_burst_counter_reg <= (others => '0'); PLB_MRdDAck_reg <= '0'; elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then dp_dataConv_rd_conv_mode <= conv_mode_comb; dp_dataConv_rd_burst_counter <= conv_counter_comb; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then dp_dataConv_rd_conv_mode <= "00"; end if; if (PLB_MRdDAck = '1' and ((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or (pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then if (dp_dataConv_rd_burst_counter = "00") then if (dp_dataConv_rd_conv_mode = "01") then -- 128/32 dp_dataConv_rd_burst_counter <= "11"; elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64 dp_dataConv_rd_burst_counter <= "01"; end if; else dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1; end if; end if; dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter; PLB_MRdDAck_reg <= PLB_MRdDAck; end if; end process; rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0'; process(PLB_MRdDBus) variable i: integer; begin -- change to little endian for i in 0 to C_PLB_DWIDTH-1 loop PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i); end loop; end process; process(PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then rd_fifo_din <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MRdDAck = '1') then case dp_dataConv_rd_conv_mode is when "00" => rd_fifo_din <= PLB_MRdDBus_reverse; when "10" | "11" => if (dp_dataConv_rd_burst_counter = "00") then rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); else rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0); end if; when "01" => case dp_dataConv_rd_burst_counter is when "00" => rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "01" => rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "10" => rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when "11" => rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0); when others => null; end case; when others => null; end case; end if; end if; end process; rd_fifo_pop <= BUS_rsp_pop; pending_read_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_rd_req_burst_mode <= '0'; pending_rd_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '0') then if (burst_mode = '1' and burst_size /= "0000") then pending_rd_req_burst_mode <= burst_mode; end if; pending_rd_req_burst_size <= burst_size; elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then if (dp_dataConv_rd_burst_counter = "00") then pending_rd_req_burst_size <= pending_rd_req_burst_size - 1; if (pending_rd_req_burst_size = "0000") then pending_rd_req_burst_mode <= '0'; end if; end if; end if; end if; end process; pending_write_req_p: process (PLB_Clk, PLB_Rst) begin if (PLB_Rst = '1') then pending_wr_req_burst_mode <= '0'; pending_wr_req_burst_size <= (others => '0'); elsif (PLB_Clk'event and PLB_Clk = '1') then if (PLB_MAddrAck = '1' and req_nRW = '1') then if (burst_mode = '1' and burst_size /= "0000") then pending_wr_req_burst_mode <= '1'; end if; pending_wr_req_burst_size <= burst_size; if (PLB_MWrDAck = '1') then if (conv_counter_comb = "00") then pending_wr_req_burst_size <= burst_size -1; else pending_wr_req_burst_size <= burst_size; end if; end if; elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then if (dp_dataConv_wd_burst_counter = "00") then pending_wr_req_burst_size <= pending_wr_req_burst_size - 1; if (pending_wr_req_burst_size = "0000") then pending_wr_req_burst_mode <= '0'; end if; end if; end if; end if; end process; end IMP;

lgpl-3.0

3d13ecbd9c9f83c9d75e01710dac4501

0.535001

3.311829

false

jairov4/accel-oil

solution_virtex5_plb/syn/vhdl/nfa_accept_sample_multi_next_buckets.vhd

1

3,201

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nfa_accept_sample_multi_next_buckets_ram is generic( mem_type : string := "block"; dwidth : integer := 64; awidth : integer := 4; mem_size : integer := 16 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of nfa_accept_sample_multi_next_buckets_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array; attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_sample_multi_next_buckets is generic ( DataWidth : INTEGER := 64; AddressRange : INTEGER := 16; AddressWidth : INTEGER := 4); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_sample_multi_next_buckets is component nfa_accept_sample_multi_next_buckets_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_sample_multi_next_buckets_ram_U : component nfa_accept_sample_multi_next_buckets_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0); end architecture;

lgpl-3.0

9509007816150f82db7c41a2c328f35c

0.555764

3.521452

false

wsoltys/AtomFpga

src/DCM/dcm4.vhd

1

2,051

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity dcm4 is port (CLKIN_IN : in std_logic; CLK0_OUT : out std_logic; CLK0_OUT1 : out std_logic; CLK2X_OUT : out std_logic); end dcm4; architecture BEHAVIORAL of dcm4 is signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKFX_BUFG_INST : BUFG port map (I => CLKFX_BUF, O => CLK0_OUT); DCM_INST : DCM generic map(CLK_FEEDBACK => "NONE", CLKDV_DIVIDE => 4.0, -- 25.175 = 32 * 11 / 14 CLKFX_DIVIDE => 14, CLKFX_MULTIPLY => 11, CLKIN_DIVIDE_BY_2 => false, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => true, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => false) port map (CLKFB => GND_BIT, CLKIN => CLKIN_IN, DSSEN => GND_BIT, PSCLK => GND_BIT, PSEN => GND_BIT, PSINCDEC => GND_BIT, RST => GND_BIT, CLKDV => open, CLKFX => CLKFX_BUF, CLKFX180 => open, CLK0 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLK180 => open, CLK270 => open, LOCKED => open, PSDONE => open, STATUS => open); end BEHAVIORAL;

apache-2.0

d3b01e0f70dd04bba46dfe95885232ec

0.403218

4.29979

false

jairov4/accel-oil

solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_finals_buckets_if_async_fifo.vhd

1

5,827

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_finals_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_finals_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;

lgpl-3.0

9b2ebabfdfd90b59002178d95bfb6c02

0.554144

3.403621

false

jairov4/accel-oil

impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/sample_iterator_get_offset/_primary.vhd

1

2,496

library verilog; use verilog.vl_types.all; entity sample_iterator_get_offset is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_pp0_stg0_fsm_0: vl_logic := Hi0; ap_const_lv32_1 : integer := 1; ap_const_lv32_30: integer := 48; ap_const_lv32_37: integer := 55; ap_const_lv56_0 : vl_logic_vector(0 to 55) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; indices_req_din : out vl_logic; indices_req_full_n: in vl_logic; indices_req_write: out vl_logic; indices_rsp_empty_n: in vl_logic; indices_rsp_read: out vl_logic; indices_address : out vl_logic_vector(31 downto 0); indices_datain : in vl_logic_vector(55 downto 0); indices_dataout : out vl_logic_vector(55 downto 0); indices_size : out vl_logic_vector(31 downto 0); ap_ce : in vl_logic; i_index : in vl_logic_vector(15 downto 0); i_sample : in vl_logic_vector(15 downto 0); sample_buffer_size: in vl_logic_vector(31 downto 0); sample_length : in vl_logic_vector(15 downto 0); ap_return : out vl_logic_vector(31 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_30 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_37 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv56_0 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end sample_iterator_get_offset;

lgpl-3.0

ca5bef7176f29d33beddbcb6a5d57148

0.580929

2.929577

false

takeshineshiro/fpga_fibre_scan

HUCB2P0_150701/usb_core/usb_121pll.vhd

1

18,162

-- megafunction wizard: %Altera PLL v14.0% -- GENERATION: XML -- usb_121pll.vhd -- Generated using ACDS version 14.0 200 at 2015.05.21.11:40:18 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity usb_121pll is port ( refclk : in std_logic := '0'; -- refclk.clk rst : in std_logic := '0'; -- reset.reset outclk_0 : out std_logic; -- outclk0.clk outclk_1 : out std_logic; -- outclk1.clk locked : out std_logic -- locked.export ); end entity usb_121pll; architecture rtl of usb_121pll is component usb_121pll_0002 is port ( refclk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic; -- clk outclk_1 : out std_logic; -- clk locked : out std_logic -- export ); end component usb_121pll_0002; begin usb_121pll_inst : component usb_121pll_0002 port map ( refclk => refclk, -- refclk.clk rst => rst, -- reset.reset outclk_0 => outclk_0, -- outclk0.clk outclk_1 => outclk_1, -- outclk1.clk locked => locked -- locked.export ); end architecture rtl; -- of usb_121pll -- Retrieval info: <?xml version="1.0"?> -- -- Retrieval info: <instance entity-name="altera_pll" version="14.0" > -- Retrieval info: <generic name="debug_print_output" value="false" /> -- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" /> -- Retrieval info: <generic name="device_family" value="Cyclone V" /> -- Retrieval info: <generic name="device" value="Unknown" /> -- Retrieval info: <generic name="gui_device_speed_grade" value="8" /> -- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" /> -- Retrieval info: <generic name="gui_reference_clock_frequency" value="20.0" /> -- Retrieval info: <generic name="gui_channel_spacing" value="0.0" /> -- Retrieval info: <generic name="gui_operation_mode" value="normal" /> -- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" /> -- Retrieval info: <generic name="gui_fractional_cout" value="32" /> -- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" /> -- Retrieval info: <generic name="gui_use_locked" value="true" /> -- Retrieval info: <generic name="gui_en_adv_params" value="false" /> -- Retrieval info: <generic name="gui_number_of_clocks" value="2" /> -- Retrieval info: <generic name="gui_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" /> -- Retrieval info: <generic name="gui_divide_factor_n" value="1" /> -- Retrieval info: <generic name="gui_cascade_counter0" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency0" value="60.0" /> -- Retrieval info: <generic name="gui_divide_factor_c0" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units0" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle0" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter1" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency1" value="60.0" /> -- Retrieval info: <generic name="gui_divide_factor_c1" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units1" value="degrees" /> -- Retrieval info: <generic name="gui_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle1" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter2" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c2" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units2" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle2" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter3" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c3" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units3" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle3" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter4" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c4" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units4" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle4" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter5" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c5" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units5" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle5" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter6" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c6" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units6" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle6" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter7" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c7" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units7" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle7" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter8" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c8" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units8" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle8" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter9" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c9" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units9" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle9" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter10" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c10" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units10" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle10" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter11" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c11" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units11" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle11" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter12" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c12" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units12" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle12" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter13" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c13" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units13" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle13" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter14" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c14" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units14" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle14" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter15" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c15" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units15" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle15" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter16" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c16" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units16" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle16" value="50" /> -- Retrieval info: <generic name="gui_cascade_counter17" value="false" /> -- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" /> -- Retrieval info: <generic name="gui_divide_factor_c17" value="1" /> -- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" /> -- Retrieval info: <generic name="gui_ps_units17" value="ps" /> -- Retrieval info: <generic name="gui_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" /> -- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" /> -- Retrieval info: <generic name="gui_duty_cycle17" value="50" /> -- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" /> -- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" /> -- Retrieval info: <generic name="gui_en_reconf" value="false" /> -- Retrieval info: <generic name="gui_en_dps_ports" value="false" /> -- Retrieval info: <generic name="gui_en_phout_ports" value="false" /> -- Retrieval info: <generic name="gui_phout_division" value="1" /> -- Retrieval info: <generic name="gui_en_lvds_ports" value="false" /> -- Retrieval info: <generic name="gui_mif_generate" value="false" /> -- Retrieval info: <generic name="gui_enable_mif_dps" value="false" /> -- Retrieval info: <generic name="gui_dps_cntr" value="C0" /> -- Retrieval info: <generic name="gui_dps_num" value="1" /> -- Retrieval info: <generic name="gui_dps_dir" value="Positive" /> -- Retrieval info: <generic name="gui_refclk_switch" value="false" /> -- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" /> -- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" /> -- Retrieval info: <generic name="gui_switchover_delay" value="0" /> -- Retrieval info: <generic name="gui_active_clk" value="false" /> -- Retrieval info: <generic name="gui_clk_bad" value="false" /> -- Retrieval info: <generic name="gui_enable_cascade_out" value="false" /> -- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" /> -- Retrieval info: <generic name="gui_enable_cascade_in" value="false" /> -- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" /> -- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" /> -- Retrieval info: </instance> -- IPFS_FILES : usb_121pll.vho -- RELATED_FILES: usb_121pll.vhd, usb_121pll_0002.v

apache-2.0

730e27a773d0c3d6f58dd8cc6677355a

0.672888

3.00248

false

dcliche/mdsynth

rtl/src/sound/lfsr.vhd

1

6,012

------------------------------------------------------------------------------- -- File downloaded from http://www.nandland.com ------------------------------------------------------------------------------- -- Description: -- A LFSR or Linear Feedback Shift Register is a quick and easy -- way to generate pseudo-random data inside of an FPGA. The LFSR can be used -- for things like counters, test patterns, scrambling of data, and others. -- This module creates an LFSR whose width gets set by a generic. The -- o_LFSR_Done will pulse once all combinations of the LFSR are complete. The -- number of clock cycles that it takes o_LFSR_Done to pulse is equal to -- 2^g_Num_Bits-1. For example, setting g_Num_Bits to 5 means that o_LFSR_Done -- will pulse every 2^5-1 = 31 clock cycles. o_LFSR_Data will change on each -- clock cycle that the module is enabled, which can be used if desired. -- -- Generics: -- g_Num_Bits - Set to the integer number of bits wide to create your LFSR. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity lfsr is generic ( g_Num_Bits : integer := 5 ); port ( i_Clk : in std_logic; i_Enable : in std_logic; -- Optional Seed Value i_Seed_DV : in std_logic; i_Seed_Data : in std_logic_vector(g_Num_Bits-1 downto 0); o_LFSR_Data : out std_logic_vector(g_Num_Bits-1 downto 0); o_LFSR_Done : out std_logic ); end entity lfsr; architecture rtl of lfsr is signal r_LFSR : std_logic_vector(g_Num_Bits downto 1) := (others => '0'); signal w_XNOR : std_logic; begin -- Purpose: Load up LFSR with Seed if Data Valid (DV) pulse is detected. -- Othewise just run LFSR when enabled. p_LFSR : process (i_Clk) is begin if rising_edge(i_Clk) then if i_Enable = '1' then if i_Seed_DV = '1' then r_LFSR <= i_Seed_Data; else r_LFSR <= r_LFSR(r_LFSR'left-1 downto 1) & w_XNOR; end if; end if; end if; end process p_LFSR; -- Create Feedback Polynomials. Based on Application Note: -- http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf g_LFSR_3 : if g_Num_Bits = 3 generate w_XNOR <= r_LFSR(3) xnor r_LFSR(2); end generate g_LFSR_3; g_LFSR_4 : if g_Num_Bits = 4 generate w_XNOR <= r_LFSR(4) xnor r_LFSR(3); end generate g_LFSR_4; g_LFSR_5 : if g_Num_Bits = 5 generate w_XNOR <= r_LFSR(5) xnor r_LFSR(3); end generate g_LFSR_5; g_LFSR_6 : if g_Num_Bits = 6 generate w_XNOR <= r_LFSR(6) xnor r_LFSR(5); end generate g_LFSR_6; g_LFSR_7 : if g_Num_Bits = 7 generate w_XNOR <= r_LFSR(7) xnor r_LFSR(6); end generate g_LFSR_7; g_LFSR_8 : if g_Num_Bits = 8 generate w_XNOR <= r_LFSR(8) xnor r_LFSR(6) xnor r_LFSR(5) xnor r_LFSR(4); end generate g_LFSR_8; g_LFSR_9 : if g_Num_Bits = 9 generate w_XNOR <= r_LFSR(9) xnor r_LFSR(5); end generate g_LFSR_9; g_LFSR_10 : if g_Num_Bits = 10 generate w_XNOR <= r_LFSR(10) xnor r_LFSR(7); end generate g_LFSR_10; g_LFSR_11 : if g_Num_Bits = 11 generate w_XNOR <= r_LFSR(11) xnor r_LFSR(9); end generate g_LFSR_11; g_LFSR_12 : if g_Num_Bits = 12 generate w_XNOR <= r_LFSR(12) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1); end generate g_LFSR_12; g_LFSR_13 : if g_Num_Bits = 13 generate w_XNOR <= r_LFSR(13) xnor r_LFSR(4) xnor r_LFSR(3) xnor r_LFSR(1); end generate g_LFSR_13; g_LFSR_14 : if g_Num_Bits = 14 generate w_XNOR <= r_LFSR(14) xnor r_LFSR(5) xnor r_LFSR(3) xnor r_LFSR(1); end generate g_LFSR_14; g_LFSR_15 : if g_Num_Bits = 15 generate w_XNOR <= r_LFSR(15) xnor r_LFSR(14); end generate g_LFSR_15; g_LFSR_16 : if g_Num_Bits = 16 generate w_XNOR <= r_LFSR(16) xnor r_LFSR(15) xnor r_LFSR(13) xnor r_LFSR(4); end generate g_LFSR_16; g_LFSR_17 : if g_Num_Bits = 17 generate w_XNOR <= r_LFSR(17) xnor r_LFSR(14); end generate g_LFSR_17; g_LFSR_18 : if g_Num_Bits = 18 generate w_XNOR <= r_LFSR(18) xnor r_LFSR(11); end generate g_LFSR_18; g_LFSR_19 : if g_Num_Bits = 19 generate w_XNOR <= r_LFSR(19) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_19; g_LFSR_20 : if g_Num_Bits = 20 generate w_XNOR <= r_LFSR(20) xnor r_LFSR(17); end generate g_LFSR_20; g_LFSR_21 : if g_Num_Bits = 21 generate w_XNOR <= r_LFSR(21) xnor r_LFSR(19); end generate g_LFSR_21; g_LFSR_22 : if g_Num_Bits = 22 generate w_XNOR <= r_LFSR(22) xnor r_LFSR(21); end generate g_LFSR_22; g_LFSR_23 : if g_Num_Bits = 23 generate w_XNOR <= r_LFSR(23) xnor r_LFSR(18); end generate g_LFSR_23; g_LFSR_24 : if g_Num_Bits = 24 generate w_XNOR <= r_LFSR(24) xnor r_LFSR(23) xnor r_LFSR(22) xnor r_LFSR(17); end generate g_LFSR_24; g_LFSR_25 : if g_Num_Bits = 25 generate w_XNOR <= r_LFSR(25) xnor r_LFSR(22); end generate g_LFSR_25; g_LFSR_26 : if g_Num_Bits = 26 generate w_XNOR <= r_LFSR(26) xnor r_LFSR(6) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_26; g_LFSR_27 : if g_Num_Bits = 27 generate w_XNOR <= r_LFSR(27) xnor r_LFSR(5) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_27; g_LFSR_28 : if g_Num_Bits = 28 generate w_XNOR <= r_LFSR(28) xnor r_LFSR(25); end generate g_LFSR_28; g_LFSR_29 : if g_Num_Bits = 29 generate w_XNOR <= r_LFSR(29) xnor r_LFSR(27); end generate g_LFSR_29; g_LFSR_30 : if g_Num_Bits = 30 generate w_XNOR <= r_LFSR(30) xnor r_LFSR(6) xnor r_LFSR(4) xnor r_LFSR(1); end generate g_LFSR_30; g_LFSR_31 : if g_Num_Bits = 31 generate w_XNOR <= r_LFSR(31) xnor r_LFSR(28); end generate g_LFSR_31; g_LFSR_32 : if g_Num_Bits = 32 generate w_XNOR <= r_LFSR(32) xnor r_LFSR(22) xnor r_LFSR(2) xnor r_LFSR(1); end generate g_LFSR_32; o_LFSR_Data <= r_LFSR(r_LFSR'left downto 1); o_LFSR_Done <= '1' when r_LFSR(r_LFSR'left downto 1) = i_Seed_Data else '0'; end architecture rtl;

gpl-3.0

1067162bf4df73e56767e37495d169af

0.601464

2.86969

false

grwlf/vsim

vhdl_ct/ct00379.vhd

1

1,969

-- NEED RESULT: ARCH00379: Elaboration of a block header failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00379 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 12.2 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00379) -- ENT00379_Test_Bench(ARCH00379_Test_Bench) -- -- REVISION HISTORY: -- -- 31-JUL-1987 - initial revision -- 6-APR-1988 - JW: Initial value on block port was not static -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES.all ; architecture ARCH00379 of E00000 is begin B1 : block generic ( g1 : integer ; g2 : integer := 27 ) ; generic map ( g1 => 11 ) ; signal s : bit_vector (1 to 32) ; constant c : bit_vector (g1 to g2) := B"10101010101010101"; -- JW begin B : block -- JW: port ( vec : in bit_vector := s ( g1 to g2 ) ) ; port ( vec : in bit_vector := c ); -- JW constant vec_left : integer := vec'left ; constant vec_right : integer := vec'right ; begin process begin test_report ( "ARCH00379" , "Elaboration of a block header" , (vec_left = 11) and (vec_right = 27) ) ; wait ; end process ; end block B ; end block B1 ; end ARCH00379 ; entity ENT00379_Test_Bench is end ENT00379_Test_Bench ; architecture ARCH00379_Test_Bench of ENT00379_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00379 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00379_Test_Bench ;

gpl-3.0

c6b5c9b25d2e906087b81f2681d7ff81

0.479431

3.4363

false

true

false

grwlf/vsim

vhdl_ct/ct00027.vhd

1

3,486

-- NEED RESULT: *** An assertion with Report ARCH00027: An assertion with complex string expressions passed and severity of Note should follow -- NEED RESULT: ARCH00027: An assertion with complex string expressions passed -- NEED RESULT: *** An assertion with Report ARCH00027: An assertion with complex string expressions passed and severity of Note should follow -- NEED RESULT: ARCH00027: An assertion with complex string expressions passed -- NEED RESULT: *** An assertion with Report ARCH00027: An assertion with complex string expressions passed and default severity of Error should follow -- NEED RESULT: *** An assertion with Report ARCH00027: An assertion with complex string expressions failed and default severity of Error should follow ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00027 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.2 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00027(ARCH00027) -- ENT00027_Test_Bench(ARCH00027_Test_Bench) -- -- REVISION HISTORY: -- -- 26-JUN-1987 - initial revision -- -- NOTES: -- -- Check that assertion messages match comment messages in output -- use WORK.STANDARD_TYPES.all; entity ENT00027 is generic ( Lowb : Integer := 1 ; Highb : Integer := 12 ) ; port ( msg1 : in string ; msg2 : in string ) ; constant c_msg : string ( 1 to 12 ) := "passedfailed" ; end ENT00027 ; architecture ARCH00027 of ENT00027 is subtype sm_string is string ( Lowb to Highb ) ; constant cc_msg : sm_string := "failedpassed" ; procedure Proc1 ( part1, part2, part3 : in string ) is begin print ( "*** An assertion with Report " & part1 & part2 & part3 & " and default severity of Error should follow" ) ; assert false report part1 & part2 & part3; end Proc1 ; signal Dummy : Boolean := false ; begin p1 : process ( Dummy ) begin print ( "*** An assertion with Report " & msg1 & msg2 & c_msg(1 to 6) & " and severity of Note should follow" ) ; assert Dummy report msg1 & msg2 & c_msg(1 to 6) severity NOTE ; print ( "*** An assertion with Report " & msg1 & msg2 & cc_msg(7 to Highb) & " and severity of Note should follow" ) ; assert Dummy report msg1 & msg2 & cc_msg(7 to HighB) severity NOTE ; Proc1 ( msg1, msg2, cc_msg(7 to HighB) ) ; Proc1 ( msg1, msg2, cc_msg(1 to 6) ) ; end process p1 ; end ARCH00027 ; entity ENT00027_Test_Bench is end ENT00027_Test_Bench ; architecture ARCH00027_Test_Bench of ENT00027_Test_Bench is begin L1: block component UUT generic ( Lowb : Integer ; Highb : Integer ) ; port ( msg1 : in string ; msg2 : in string ) ; end component ; for CIS1 : UUT use entity WORK.ENT00027 ( ARCH00027 ) ; subtype Name_ST is string (1 to 11) ; signal DU_Name : Name_ST := "ARCH00027: "; subtype Msg_St is string (1 to 45) ; signal msg : Msg_ST := "An assertion with complex string expressions " ; begin CIS1 : UUT generic map ( 1, 12 ) port map ( DU_Name, msg ) ; end block L1 ; end ARCH00027_Test_Bench ;

gpl-3.0

ab593cdf5663f8a06562632142ad48fc

0.592943

3.760518

false

true

false

grwlf/vsim

vhdl_ct/ct00295.vhd

1

6,964

-- NEED RESULT: ARCH00295: Bit short circuiting results passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- TEST NAME: -- -- CT00295 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.1 (6) -- 7.2.1 (7) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00295) -- ENT00295_Test_Bench(ARCH00295_Test_Bench) -- -- REVISION HISTORY: -- -- 24-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00295 of E00000 is begin P00295 : process variable vbit : bit; variable bit0 : bit := '0'; variable bit1 : bit := '1'; variable bool : boolean := true ; function do_not_evaluate return bit is begin test_report ( "ARCH00295" , "Bit short circuiting correct" , false ) ; return '0' ; end do_not_evaluate ; begin vbit := bit0 and (do_not_evaluate and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit1 and (bit0 and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit0) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit1 and (bit1 and bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit1) and bit0 ; bool := bool and vbit = '0' ; vbit := bit1 and (bit1 and bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit1) and bit1 ; bool := bool and vbit = '1' ; vbit := bit0 or (bit0 or bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit0) or bit0 ; bool := bool and vbit = '0' ; vbit := bit0 or (bit0 or bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit0) or bit1 ; bool := bool and vbit = '1' ; vbit := bit0 or (bit1 or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit1) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit1 or (do_not_evaluate or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 or do_not_evaluate) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit0 or (bit0 and do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit0) and do_not_evaluate ; bool := bool and vbit = '0' ; vbit := bit0 or (bit1 and bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 or bit1) and bit0 ; bool := bool and vbit = '0' ; vbit := bit0 or (bit1 and bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 or bit1) and bit1 ; bool := bool and vbit = '1' ; vbit := bit1 or (do_not_evaluate and do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 or do_not_evaluate) and bit0 ; bool := bool and vbit = '0' ; vbit := (bit1 or do_not_evaluate) and bit1 ; bool := bool and vbit = '1' ; vbit := bit0 and (do_not_evaluate or do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) or bit0 ; bool := bool and vbit = '0' ; vbit := (bit0 and do_not_evaluate) or bit1 ; bool := bool and vbit = '1' ; vbit := bit1 and (bit0 or bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 and bit0) or bit0 ; bool := bool and vbit = '0' ; vbit := bit1 and (bit0 or bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit0) or bit1 ; bool := bool and vbit = '1' ; vbit := bit1 and (bit1 or do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit1 and bit1) or do_not_evaluate ; bool := bool and vbit = '1' ; vbit := bit0 nand (do_not_evaluate nand do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := bit1 nand (bit0 nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit1 nand bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 nand bit1) nand bit0 ; bool := bool and vbit = '1' ; vbit := bit1 nand (bit1 nand bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 nand bit1) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit0 nor bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 nor bit0) nor bit0 ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit0 nor bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 nor bit0) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit1 nor do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit0 nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := bit0 nor (bit1 nand bit0) ; bool := bool and vbit = '0' ; vbit := (bit0 nor bit1) nand bit0 ; bool := bool and vbit = '1' ; vbit := bit0 nor (bit1 nand bit1) ; bool := bool and vbit = '1' ; vbit := (bit0 nor bit1) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit1 nor (do_not_evaluate nand do_not_evaluate) ; bool := bool and vbit = '0' ; vbit := (bit1 nor do_not_evaluate) nand bit0 ; bool := bool and vbit = '1' ; vbit := (bit1 nor do_not_evaluate) nand bit1 ; bool := bool and vbit = '1' ; vbit := bit0 nand (do_not_evaluate nor do_not_evaluate) ; bool := bool and vbit = '1' ; vbit := (bit0 nand do_not_evaluate) nor bit0 ; bool := bool and vbit = '0' ; vbit := (bit0 nand do_not_evaluate) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit0 nor bit0) ; bool := bool and vbit = '0' ; vbit := (bit1 nand bit0) nor bit0 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit0 nor bit1) ; bool := bool and vbit = '1' ; vbit := (bit1 nand bit0) nor bit1 ; bool := bool and vbit = '0' ; vbit := bit1 nand (bit1 nor do_not_evaluate) ; bool := bool and vbit = '1' ; test_report ( "ARCH00295" , "Bit short circuiting results" , bool ) ; wait ; end process P00295 ; end ARCH00295 ; entity ENT00295_Test_Bench is end ENT00295_Test_Bench ; architecture ARCH00295_Test_Bench of ENT00295_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00295 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00295_Test_Bench ;

gpl-3.0

477178724bab90c8468067187dad0585

0.498995

3.115884

false

jairov4/accel-oil

solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_forward_buckets_if.vhd

2

21,283

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_forward_buckets_if is generic( MPMC_BASE_ADDRESS : std_logic_vector := X"00000000"; USER_DATA_WIDTH : integer := 32; USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width) ); port( --/////////////////////////////////////////////////////////////////////////////// --// MPMC Port Interface - Bus is prefixed with NPI_ NPI_clk : in std_logic; NPI_reset : in std_logic; NPI_Addr : out std_logic_vector(31 downto 0); NPI_AddrReq : out std_logic; NPI_AddrAck : in std_logic; NPI_RNW : out std_logic; NPI_Size : out std_logic_vector(3 downto 0); NPI_WrFIFO_Data : out std_logic_vector(63 downto 0); NPI_WrFIFO_BE : out std_logic_vector(7 downto 0); NPI_WrFIFO_Push : out std_logic; NPI_RdFIFO_Data : in std_logic_vector(63 downto 0); NPI_RdFIFO_Pop : out std_logic; NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0); NPI_WrFIFO_Empty : in std_logic; NPI_WrFIFO_AlmostFull : in std_logic; NPI_WrFIFO_Flush : out std_logic; NPI_RdFIFO_Empty : in std_logic; NPI_RdFIFO_Flush : out std_logic; NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0); NPI_RdModWr : out std_logic; NPI_InitDone : in std_logic; -- signals from user logic ap_clk : in std_logic; ap_reset : in std_logic; USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS USER_size : in std_logic_vector(31 downto 0); -- burst size of word USER_req_nRW : in std_logic; -- req type 0: Read, 1: write USER_req_full_n : out std_logic; -- req Fifo full USER_req_push : in std_logic; -- req Fifo push (new request in) USER_rsp_empty_n: out std_logic; -- return data FIFO empty USER_rsp_pop : in std_logic -- return data FIFO pop ); end entity; architecture arch_nfa_forward_buckets_if OF nfa_forward_buckets_if IS component nfa_forward_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : IN STD_LOGIC; clk_r : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; component nfa_forward_buckets_if_ap_fifo_af is generic ( DATA_WIDTH : integer := 64; ADDR_WIDTH : integer := 6; DEPTH : integer := 64; ALMOST_FULL_MARGIN : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC); end component; constant C_PI_ADDR_WIDTH : integer := 32; constant C_PI_DATA_WIDTH : integer := 64; constant C_PI_BE_WIDTH : integer := 8; constant C_PI_RDWDADDR_WIDTH: integer := 4; constant RSW : integer := 7; -- req size width constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data constant REQ_FIFO_ADDR_WIDTH : integer := 3; constant REQ_FIFO_DEPTH : integer := 8; type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ); signal req_cs, req_ns : req_state_type; type rdata_state_type is (RESET, IDLE, RDATA); signal rdata_cs, rdata_ns : rdata_state_type; -- User interface signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0); signal User_address_local : STD_LOGIC_VECTOR(31 downto 0); -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_dout_req_nRW : STD_LOGIC; signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_reg_en : STD_LOGIC; signal nRW_reg : STD_LOGIC; signal address_reg : STD_LOGIC_VECTOR(31 downto 0); signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0); -- internal request information signal req_nRW : STD_LOGIC; signal req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0); signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0); signal req_WrData_wdAddr : STD_LOGIC; signal req_WrData_reg_en : STD_LOGIC; signal req_WrData_push : STD_LOGIC; signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0); signal req_valid : STD_LOGIC; -- burst write signal burst_write_reg_en : STD_LOGIC; signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits -- burst read signal burst_read_reg_en : STD_LOGIC; signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0); signal burst_read_wdAddr : STD_LOGIC; -- rsp FIFO constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2) constant RSP_FIFO_ADDR_WIDTH : integer := 2; constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation signal rsp_fifo_empty_n : STD_LOGIC; signal rsp_fifo_pop : STD_LOGIC; signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); signal rsp_fifo_full_n : STD_LOGIC; signal rsp_fifo_push : STD_LOGIC; signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0); -- internal rdata pop logic signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC; -- rd FIFO: input: MPMC data out, output: user async fifo signal rd_fifo_empty_n : STD_LOGIC; signal rd_fifo_pop : STD_LOGIC; signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_full_n : STD_LOGIC; signal rd_fifo_push : STD_LOGIC; signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0); -- rd user FIFO: async fifo to user signal rd_user_fifo_empty_n : STD_LOGIC; signal rd_user_fifo_pop : STD_LOGIC; signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_user_fifo_full_n : STD_LOGIC; signal rd_user_fifo_push : STD_LOGIC; signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); begin -- NPI interface NPI_WrFIFO_Flush <= '0'; NPI_RdFIFO_Flush <= '0'; NPI_RdModWr <= '0'; NPI_AddrReq <= req_valid; NPI_Addr <= address_reg; NPI_RNW <= not nRW_reg; NPI_WrFIFO_Push <= req_WrData_push; NPI_WrFIFO_BE <= req_WrData_BE; NPI_RdFIFO_Pop <= rdata_pop; process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data) begin NPI_WrFIFO_Data <= (others => '0'); if (req_WrData_wdAddr = '0') then NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low; else NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low; NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data; end if; end process; process (size_reg) begin NPI_Size <= (others => '0'); if (size_reg = "0000100") then --4w NPI_Size <= "0001"; elsif (size_reg = "0001000") then --8w NPI_Size <= "0010"; elsif (size_reg = "0010000") then --16w NPI_Size <= "0011"; elsif (size_reg = "0100000") then --32w NPI_Size <= "0100"; elsif (size_reg = "1000000") then --64w NPI_Size <= "0101"; end if; end process; -- User interface USER_req_full_n <= req_fifo_full_n; USER_rsp_empty_n <= rd_user_fifo_empty_n; USER_RdData <= rd_user_fifo_dout; rd_user_fifo_pop <= USER_rsp_pop; USER_size_local <= User_size(RSW-1 downto 0) when User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW); USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0); USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0'); -- reqest fifo logics req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0); req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData; req_fifo_push <= USER_req_push; U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_async_fifo generic map( DATA_WIDTH => REQ_FIFO_DATA_WIDTH, ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH, DEPTH => REQ_FIFO_DEPTH) port map( clk_w => ap_clk, clk_r => NPI_clk, reset => NPI_reset, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1); req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32); req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW); process(req_fifo_dout) variable i,j: integer; begin -- change byte endian to big endian for i in 0 to USER_DATA_WIDTH/8-1 loop j := USER_DATA_WIDTH/8 -1 -i; req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8); end loop; end process; p_req_fifo_out_reg: process (NPI_clk, NPI_reset) variable i,j: integer; begin if (NPI_reset = '1') then nRW_reg <= '0'; address_reg <= (others => '0'); size_reg <= (others => '0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_reg_en = '1') then nRW_reg <= req_fifo_dout_req_nRW; address_reg <= req_fifo_dout_req_address; size_reg <= req_fifo_dout_req_size; end if; end if; end process; -- write and burst write will be controlled by state machine due to MPMC limitation -- read and burst read will have seperate return data phase logic for a pipelined access p_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then req_cs <= req_ns; end if; end process; -- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq -- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW, NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count, req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull) begin req_ns <= FETCH_REQ; req_reg_en <= '0'; req_fifo_pop <= '0'; rsp_fifo_push <= '0'; req_WrData_reg_en <= '0'; burst_write_reg_en <= '0'; req_valid <= '0'; req_WrData_push <= '0'; req_WrData_BE <= "11111111"; case req_cs is when RESET => req_ns <= RESET; if (NPI_InitDone = '1') then req_ns <= FETCH_REQ; end if; when FETCH_REQ => req_ns <= FETCH_REQ; if (req_fifo_empty_n = '1') then if (req_fifo_dout_req_nRW = '1') then req_reg_en <= '1'; req_ns <= REQ; elsif (rsp_fifo_full_n = '1') then req_reg_en <= '1'; req_fifo_pop <= '1'; rsp_fifo_push <= '1'; req_ns <= REQ; end if; end if; when REQ => req_ns <= REQ; if (nRW_reg = '0') then req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then req_valid <= '1'; if (NPI_AddrAck = '1') then req_WrData_reg_en <= '1'; req_ns <= WD_SINGLE; end if; elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then burst_write_reg_en <= '1'; req_ns <= WD_BURST1; end if; when WD_SINGLE => req_ns <= WD_SINGLE; if (NPI_WrFIFO_AlmostFull = '0') then req_WrData_push <= '1'; req_fifo_pop <= '1'; req_ns <= FETCH_REQ; end if; if (req_WrData_wdAddr = '0') then req_WrData_BE <= "00001111"; else req_WrData_BE <= "11110000"; end if; when WD_BURST1 => req_ns <= WD_BURST1; if (req_fifo_empty_n = '1') then req_fifo_pop <= '1'; req_WrData_reg_en <= '1'; req_ns <= WD_BURST2; end if; when WD_BURST2 => req_ns <= WD_BURST2; if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then req_fifo_pop <= '1'; req_WrData_push <= '1'; if (burst_write_count /= "000001") then -- not last word req_ns <= WD_BURST1; else req_ns <= WD_BURST_REQ; end if; end if; when WD_BURST_REQ => req_ns <= WD_BURST_REQ; req_valid <= '1'; if (NPI_AddrAck = '1') then req_ns <= FETCH_REQ; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then req_WrData_low <= (others =>'0'); req_WrData_wdAddr <= '0'; burst_write_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (req_WrData_reg_en = '1') then req_WrData_low <= req_fifo_dout_wr_data; req_WrData_wdAddr <= req_fifo_dout_req_address(2); end if; if (burst_write_reg_en = '1') then burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6); elsif (req_WrData_push = '1') then burst_write_count <= burst_write_count-1; end if; end if; end process; -- below is the response (read data) part U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo generic map( DATA_WIDTH => RSP_FIFO_DATA_WIDTH, ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH, DEPTH => RSP_FIFO_DEPTH) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rsp_fifo_empty_n, if_read => rsp_fifo_pop, if_dout => rsp_fifo_dout, if_full_n => rsp_fifo_full_n, if_write => rsp_fifo_push, if_din => rsp_fifo_din ); rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size; rsp_fifo_din(0) <= req_fifo_dout_req_address(2); rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_pop_reg1 <= '0'; rdata_pop_reg2 <= '0'; elsif (NPI_clk'event and NPI_clk = '1') then rdata_pop_reg1 <= rdata_pop; rdata_pop_reg2 <= rdata_pop_reg1; end if; end process; process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2) begin if (NPI_RdFIFO_Latency = "00") then rd_fifo_push <= rdata_pop; elsif (NPI_RdFIFO_Latency = "01") then rd_fifo_push <= rdata_pop_reg1; else rd_fifo_push <= rdata_pop_reg2; end if; end process; rd_fifo_din <= NPI_RdFIFO_Data; -- 1. this fifo provide two 64w burst storage -- 2. with almost full signal for MPMC has potential 2 latency from pop to data -- 3. can't replace this fifo with asyn fifo which doesn't support almost_full U_nfa_forward_buckets_if_rd_fifo: component nfa_forward_buckets_if_ap_fifo_af generic map( DATA_WIDTH => C_PI_DATA_WIDTH, ADDR_WIDTH => 6, DEPTH => 64, ALMOST_FULL_MARGIN => 2) port map( clk => NPI_clk, reset => NPI_reset, if_empty_n => rd_fifo_empty_n, if_read => rd_fifo_pop, if_dout => rd_fifo_dout, if_full_n => rd_fifo_full_n, -- this is almost_full signal if_write => rd_fifo_push, if_din => rd_fifo_din ); process(rd_fifo_dout) variable i,j : integer; begin -- change byte endian to big endian for i in 0 to C_PI_BE_WIDTH-1 loop j := C_PI_BE_WIDTH-1 -i; rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8); end loop; end process; p_rdata_state_trans: process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then rdata_cs <= RESET; elsif (NPI_clk'event and NPI_clk = '1') then rdata_cs <= rdata_ns; end if; end process; p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count) begin rdata_ns <= RESET; case rdata_cs is when RESET => if (NPI_InitDone = '1') then rdata_ns <= IDLE; end if; when IDLE => rdata_ns <= IDLE; if (rsp_fifo_empty_n = '1') then rdata_ns <= RDATA; end if; when RDATA => rdata_ns <= RDATA; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then rdata_ns <= IDLE; end if; when others => null; end case; end process; p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count, rd_fifo_empty_n, rd_user_fifo_full_n) begin burst_read_reg_en <= '0'; rd_fifo_pop <= '0'; rd_user_fifo_push <= '0'; rsp_fifo_pop <= '0'; case rdata_cs is when RESET => null; when IDLE => if (rsp_fifo_empty_n = '1') then burst_read_reg_en <= '1'; end if; when RDATA => if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and rd_user_fifo_full_n = '1') then if (burst_read_count(0) = '1') then rd_fifo_pop <= '1'; end if; rd_user_fifo_push <= '1'; end if; if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then rsp_fifo_pop <= '1'; end if; when others => null; end case; end process; process (NPI_clk, NPI_reset) begin if (NPI_reset = '1') then burst_read_count <= (others =>'0'); elsif (NPI_clk'event and NPI_clk = '1') then if (burst_read_reg_en = '1') then burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW); burst_read_wdAddr <= rsp_fifo_dout(0); elsif (rd_user_fifo_push = '1') then burst_read_count <= burst_read_count -1; burst_read_wdAddr <= not burst_read_wdAddr; end if; end if; end process; rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH); U_nfa_forward_buckets_if_rd_user_fifo: component nfa_forward_buckets_if_async_fifo generic map( DATA_WIDTH => USER_DATA_WIDTH, ADDR_WIDTH => 3, DEPTH => 8) port map( clk_w => NPI_clk, clk_r => ap_clk, reset => NPI_reset, if_empty_n => rd_user_fifo_empty_n, if_read => rd_user_fifo_pop, if_dout => rd_user_fifo_dout, if_full_n => rd_user_fifo_full_n, if_write => rd_user_fifo_push, if_din => rd_user_fifo_din ); end arch_nfa_forward_buckets_if;

lgpl-3.0

a03da993ab775b87cdf381ff8d0b42e7

0.577033

3.097511

false

grwlf/vsim

vhdl/assign3.1.vhd

1

44,434

-- 500 variable assignments in 2 processes. Assigning a signal. entity main is end entity main ; architecture arch of main is signal clk : integer := 0; constant CYCLES : integer := 1000; begin main: process(clk) --{{{ variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0502 := clk; a0503 := clk; a0504 := clk; a0505 := clk; a0506 := clk; a0507 := clk; a0508 := clk; a0509 := clk; a0510 := clk; a0511 := clk; a0512 := clk; a0513 := clk; a0514 := clk; a0515 := clk; a0516 := clk; a0517 := clk; a0518 := clk; a0519 := clk; a0520 := clk; a0521 := clk; a0522 := clk; a0523 := clk; a0524 := clk; a0525 := clk; a0526 := clk; a0527 := clk; a0528 := clk; a0529 := clk; a0530 := clk; a0531 := clk; a0532 := clk; a0533 := clk; a0534 := clk; a0535 := clk; a0536 := clk; a0537 := clk; a0538 := clk; a0539 := clk; a0540 := clk; a0541 := clk; a0542 := clk; a0543 := clk; a0544 := clk; a0545 := clk; a0546 := clk; a0547 := clk; a0548 := clk; a0549 := clk; a0550 := clk; a0551 := clk; a0552 := clk; a0553 := clk; a0554 := clk; a0555 := clk; a0556 := clk; a0557 := clk; a0558 := clk; a0559 := clk; a0560 := clk; a0561 := clk; a0562 := clk; a0563 := clk; a0564 := clk; a0565 := clk; a0566 := clk; a0567 := clk; a0568 := clk; a0569 := clk; a0570 := clk; a0571 := clk; a0572 := clk; a0573 := clk; a0574 := clk; a0575 := clk; a0576 := clk; a0577 := clk; a0578 := clk; a0579 := clk; a0580 := clk; a0581 := clk; a0582 := clk; a0583 := clk; a0584 := clk; a0585 := clk; a0586 := clk; a0587 := clk; a0588 := clk; a0589 := clk; a0590 := clk; a0591 := clk; a0592 := clk; a0593 := clk; a0594 := clk; a0595 := clk; a0596 := clk; a0597 := clk; a0598 := clk; a0599 := clk; a0600 := clk; a0601 := clk; a0602 := clk; a0603 := clk; a0604 := clk; a0605 := clk; a0606 := clk; a0607 := clk; a0608 := clk; a0609 := clk; a0610 := clk; a0611 := clk; a0612 := clk; a0613 := clk; a0614 := clk; a0615 := clk; a0616 := clk; a0617 := clk; a0618 := clk; a0619 := clk; a0620 := clk; a0621 := clk; a0622 := clk; a0623 := clk; a0624 := clk; a0625 := clk; a0626 := clk; a0627 := clk; a0628 := clk; a0629 := clk; a0630 := clk; a0631 := clk; a0632 := clk; a0633 := clk; a0634 := clk; a0635 := clk; a0636 := clk; a0637 := clk; a0638 := clk; a0639 := clk; a0640 := clk; a0641 := clk; a0642 := clk; a0643 := clk; a0644 := clk; a0645 := clk; a0646 := clk; a0647 := clk; a0648 := clk; a0649 := clk; a0650 := clk; a0651 := clk; a0652 := clk; a0653 := clk; a0654 := clk; a0655 := clk; a0656 := clk; a0657 := clk; a0658 := clk; a0659 := clk; a0660 := clk; a0661 := clk; a0662 := clk; a0663 := clk; a0664 := clk; a0665 := clk; a0666 := clk; a0667 := clk; a0668 := clk; a0669 := clk; a0670 := clk; a0671 := clk; a0672 := clk; a0673 := clk; a0674 := clk; a0675 := clk; a0676 := clk; a0677 := clk; a0678 := clk; a0679 := clk; a0680 := clk; a0681 := clk; a0682 := clk; a0683 := clk; a0684 := clk; a0685 := clk; a0686 := clk; a0687 := clk; a0688 := clk; a0689 := clk; a0690 := clk; a0691 := clk; a0692 := clk; a0693 := clk; a0694 := clk; a0695 := clk; a0696 := clk; a0697 := clk; a0698 := clk; a0699 := clk; a0700 := clk; a0701 := clk; a0702 := clk; a0703 := clk; a0704 := clk; a0705 := clk; a0706 := clk; a0707 := clk; a0708 := clk; a0709 := clk; a0710 := clk; a0711 := clk; a0712 := clk; a0713 := clk; a0714 := clk; a0715 := clk; a0716 := clk; a0717 := clk; a0718 := clk; a0719 := clk; a0720 := clk; a0721 := clk; a0722 := clk; a0723 := clk; a0724 := clk; a0725 := clk; a0726 := clk; a0727 := clk; a0728 := clk; a0729 := clk; a0730 := clk; a0731 := clk; a0732 := clk; a0733 := clk; a0734 := clk; a0735 := clk; a0736 := clk; a0737 := clk; a0738 := clk; a0739 := clk; a0740 := clk; a0741 := clk; a0742 := clk; a0743 := clk; a0744 := clk; a0745 := clk; a0746 := clk; a0747 := clk; a0748 := clk; a0749 := clk; a0750 := clk; a0751 := clk; a0752 := clk; a0753 := clk; a0754 := clk; a0755 := clk; a0756 := clk; a0757 := clk; a0758 := clk; a0759 := clk; a0760 := clk; a0761 := clk; a0762 := clk; a0763 := clk; a0764 := clk; a0765 := clk; a0766 := clk; a0767 := clk; a0768 := clk; a0769 := clk; a0770 := clk; a0771 := clk; a0772 := clk; a0773 := clk; a0774 := clk; a0775 := clk; a0776 := clk; a0777 := clk; a0778 := clk; a0779 := clk; a0780 := clk; a0781 := clk; a0782 := clk; a0783 := clk; a0784 := clk; a0785 := clk; a0786 := clk; a0787 := clk; a0788 := clk; a0789 := clk; a0790 := clk; a0791 := clk; a0792 := clk; a0793 := clk; a0794 := clk; a0795 := clk; a0796 := clk; a0797 := clk; a0798 := clk; a0799 := clk; a0800 := clk; a0801 := clk; a0802 := clk; a0803 := clk; a0804 := clk; a0805 := clk; a0806 := clk; a0807 := clk; a0808 := clk; a0809 := clk; a0810 := clk; a0811 := clk; a0812 := clk; a0813 := clk; a0814 := clk; a0815 := clk; a0816 := clk; a0817 := clk; a0818 := clk; a0819 := clk; a0820 := clk; a0821 := clk; a0822 := clk; a0823 := clk; a0824 := clk; a0825 := clk; a0826 := clk; a0827 := clk; a0828 := clk; a0829 := clk; a0830 := clk; a0831 := clk; a0832 := clk; a0833 := clk; a0834 := clk; a0835 := clk; a0836 := clk; a0837 := clk; a0838 := clk; a0839 := clk; a0840 := clk; a0841 := clk; a0842 := clk; a0843 := clk; a0844 := clk; a0845 := clk; a0846 := clk; a0847 := clk; a0848 := clk; a0849 := clk; a0850 := clk; a0851 := clk; a0852 := clk; a0853 := clk; a0854 := clk; a0855 := clk; a0856 := clk; a0857 := clk; a0858 := clk; a0859 := clk; a0860 := clk; a0861 := clk; a0862 := clk; a0863 := clk; a0864 := clk; a0865 := clk; a0866 := clk; a0867 := clk; a0868 := clk; a0869 := clk; a0870 := clk; a0871 := clk; a0872 := clk; a0873 := clk; a0874 := clk; a0875 := clk; a0876 := clk; a0877 := clk; a0878 := clk; a0879 := clk; a0880 := clk; a0881 := clk; a0882 := clk; a0883 := clk; a0884 := clk; a0885 := clk; a0886 := clk; a0887 := clk; a0888 := clk; a0889 := clk; a0890 := clk; a0891 := clk; a0892 := clk; a0893 := clk; a0894 := clk; a0895 := clk; a0896 := clk; a0897 := clk; a0898 := clk; a0899 := clk; a0900 := clk; a0901 := clk; a0902 := clk; a0903 := clk; a0904 := clk; a0905 := clk; a0906 := clk; a0907 := clk; a0908 := clk; a0909 := clk; a0910 := clk; a0911 := clk; a0912 := clk; a0913 := clk; a0914 := clk; a0915 := clk; a0916 := clk; a0917 := clk; a0918 := clk; a0919 := clk; a0920 := clk; a0921 := clk; a0922 := clk; a0923 := clk; a0924 := clk; a0925 := clk; a0926 := clk; a0927 := clk; a0928 := clk; a0929 := clk; a0930 := clk; a0931 := clk; a0932 := clk; a0933 := clk; a0934 := clk; a0935 := clk; a0936 := clk; a0937 := clk; a0938 := clk; a0939 := clk; a0940 := clk; a0941 := clk; a0942 := clk; a0943 := clk; a0944 := clk; a0945 := clk; a0946 := clk; a0947 := clk; a0948 := clk; a0949 := clk; a0950 := clk; a0951 := clk; a0952 := clk; a0953 := clk; a0954 := clk; a0955 := clk; a0956 := clk; a0957 := clk; a0958 := clk; a0959 := clk; a0960 := clk; a0961 := clk; a0962 := clk; a0963 := clk; a0964 := clk; a0965 := clk; a0966 := clk; a0967 := clk; a0968 := clk; a0969 := clk; a0970 := clk; a0971 := clk; a0972 := clk; a0973 := clk; a0974 := clk; a0975 := clk; a0976 := clk; a0977 := clk; a0978 := clk; a0979 := clk; a0980 := clk; a0981 := clk; a0982 := clk; a0983 := clk; a0984 := clk; a0985 := clk; a0986 := clk; a0987 := clk; a0988 := clk; a0989 := clk; a0990 := clk; a0991 := clk; a0992 := clk; a0993 := clk; a0994 := clk; a0995 := clk; a0996 := clk; a0997 := clk; a0998 := clk; a0999 := clk; a1000 := clk; --}}} end process; main1: process(clk) --{{{ variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0502 := clk; a0503 := clk; a0504 := clk; a0505 := clk; a0506 := clk; a0507 := clk; a0508 := clk; a0509 := clk; a0510 := clk; a0511 := clk; a0512 := clk; a0513 := clk; a0514 := clk; a0515 := clk; a0516 := clk; a0517 := clk; a0518 := clk; a0519 := clk; a0520 := clk; a0521 := clk; a0522 := clk; a0523 := clk; a0524 := clk; a0525 := clk; a0526 := clk; a0527 := clk; a0528 := clk; a0529 := clk; a0530 := clk; a0531 := clk; a0532 := clk; a0533 := clk; a0534 := clk; a0535 := clk; a0536 := clk; a0537 := clk; a0538 := clk; a0539 := clk; a0540 := clk; a0541 := clk; a0542 := clk; a0543 := clk; a0544 := clk; a0545 := clk; a0546 := clk; a0547 := clk; a0548 := clk; a0549 := clk; a0550 := clk; a0551 := clk; a0552 := clk; a0553 := clk; a0554 := clk; a0555 := clk; a0556 := clk; a0557 := clk; a0558 := clk; a0559 := clk; a0560 := clk; a0561 := clk; a0562 := clk; a0563 := clk; a0564 := clk; a0565 := clk; a0566 := clk; a0567 := clk; a0568 := clk; a0569 := clk; a0570 := clk; a0571 := clk; a0572 := clk; a0573 := clk; a0574 := clk; a0575 := clk; a0576 := clk; a0577 := clk; a0578 := clk; a0579 := clk; a0580 := clk; a0581 := clk; a0582 := clk; a0583 := clk; a0584 := clk; a0585 := clk; a0586 := clk; a0587 := clk; a0588 := clk; a0589 := clk; a0590 := clk; a0591 := clk; a0592 := clk; a0593 := clk; a0594 := clk; a0595 := clk; a0596 := clk; a0597 := clk; a0598 := clk; a0599 := clk; a0600 := clk; a0601 := clk; a0602 := clk; a0603 := clk; a0604 := clk; a0605 := clk; a0606 := clk; a0607 := clk; a0608 := clk; a0609 := clk; a0610 := clk; a0611 := clk; a0612 := clk; a0613 := clk; a0614 := clk; a0615 := clk; a0616 := clk; a0617 := clk; a0618 := clk; a0619 := clk; a0620 := clk; a0621 := clk; a0622 := clk; a0623 := clk; a0624 := clk; a0625 := clk; a0626 := clk; a0627 := clk; a0628 := clk; a0629 := clk; a0630 := clk; a0631 := clk; a0632 := clk; a0633 := clk; a0634 := clk; a0635 := clk; a0636 := clk; a0637 := clk; a0638 := clk; a0639 := clk; a0640 := clk; a0641 := clk; a0642 := clk; a0643 := clk; a0644 := clk; a0645 := clk; a0646 := clk; a0647 := clk; a0648 := clk; a0649 := clk; a0650 := clk; a0651 := clk; a0652 := clk; a0653 := clk; a0654 := clk; a0655 := clk; a0656 := clk; a0657 := clk; a0658 := clk; a0659 := clk; a0660 := clk; a0661 := clk; a0662 := clk; a0663 := clk; a0664 := clk; a0665 := clk; a0666 := clk; a0667 := clk; a0668 := clk; a0669 := clk; a0670 := clk; a0671 := clk; a0672 := clk; a0673 := clk; a0674 := clk; a0675 := clk; a0676 := clk; a0677 := clk; a0678 := clk; a0679 := clk; a0680 := clk; a0681 := clk; a0682 := clk; a0683 := clk; a0684 := clk; a0685 := clk; a0686 := clk; a0687 := clk; a0688 := clk; a0689 := clk; a0690 := clk; a0691 := clk; a0692 := clk; a0693 := clk; a0694 := clk; a0695 := clk; a0696 := clk; a0697 := clk; a0698 := clk; a0699 := clk; a0700 := clk; a0701 := clk; a0702 := clk; a0703 := clk; a0704 := clk; a0705 := clk; a0706 := clk; a0707 := clk; a0708 := clk; a0709 := clk; a0710 := clk; a0711 := clk; a0712 := clk; a0713 := clk; a0714 := clk; a0715 := clk; a0716 := clk; a0717 := clk; a0718 := clk; a0719 := clk; a0720 := clk; a0721 := clk; a0722 := clk; a0723 := clk; a0724 := clk; a0725 := clk; a0726 := clk; a0727 := clk; a0728 := clk; a0729 := clk; a0730 := clk; a0731 := clk; a0732 := clk; a0733 := clk; a0734 := clk; a0735 := clk; a0736 := clk; a0737 := clk; a0738 := clk; a0739 := clk; a0740 := clk; a0741 := clk; a0742 := clk; a0743 := clk; a0744 := clk; a0745 := clk; a0746 := clk; a0747 := clk; a0748 := clk; a0749 := clk; a0750 := clk; a0751 := clk; a0752 := clk; a0753 := clk; a0754 := clk; a0755 := clk; a0756 := clk; a0757 := clk; a0758 := clk; a0759 := clk; a0760 := clk; a0761 := clk; a0762 := clk; a0763 := clk; a0764 := clk; a0765 := clk; a0766 := clk; a0767 := clk; a0768 := clk; a0769 := clk; a0770 := clk; a0771 := clk; a0772 := clk; a0773 := clk; a0774 := clk; a0775 := clk; a0776 := clk; a0777 := clk; a0778 := clk; a0779 := clk; a0780 := clk; a0781 := clk; a0782 := clk; a0783 := clk; a0784 := clk; a0785 := clk; a0786 := clk; a0787 := clk; a0788 := clk; a0789 := clk; a0790 := clk; a0791 := clk; a0792 := clk; a0793 := clk; a0794 := clk; a0795 := clk; a0796 := clk; a0797 := clk; a0798 := clk; a0799 := clk; a0800 := clk; a0801 := clk; a0802 := clk; a0803 := clk; a0804 := clk; a0805 := clk; a0806 := clk; a0807 := clk; a0808 := clk; a0809 := clk; a0810 := clk; a0811 := clk; a0812 := clk; a0813 := clk; a0814 := clk; a0815 := clk; a0816 := clk; a0817 := clk; a0818 := clk; a0819 := clk; a0820 := clk; a0821 := clk; a0822 := clk; a0823 := clk; a0824 := clk; a0825 := clk; a0826 := clk; a0827 := clk; a0828 := clk; a0829 := clk; a0830 := clk; a0831 := clk; a0832 := clk; a0833 := clk; a0834 := clk; a0835 := clk; a0836 := clk; a0837 := clk; a0838 := clk; a0839 := clk; a0840 := clk; a0841 := clk; a0842 := clk; a0843 := clk; a0844 := clk; a0845 := clk; a0846 := clk; a0847 := clk; a0848 := clk; a0849 := clk; a0850 := clk; a0851 := clk; a0852 := clk; a0853 := clk; a0854 := clk; a0855 := clk; a0856 := clk; a0857 := clk; a0858 := clk; a0859 := clk; a0860 := clk; a0861 := clk; a0862 := clk; a0863 := clk; a0864 := clk; a0865 := clk; a0866 := clk; a0867 := clk; a0868 := clk; a0869 := clk; a0870 := clk; a0871 := clk; a0872 := clk; a0873 := clk; a0874 := clk; a0875 := clk; a0876 := clk; a0877 := clk; a0878 := clk; a0879 := clk; a0880 := clk; a0881 := clk; a0882 := clk; a0883 := clk; a0884 := clk; a0885 := clk; a0886 := clk; a0887 := clk; a0888 := clk; a0889 := clk; a0890 := clk; a0891 := clk; a0892 := clk; a0893 := clk; a0894 := clk; a0895 := clk; a0896 := clk; a0897 := clk; a0898 := clk; a0899 := clk; a0900 := clk; a0901 := clk; a0902 := clk; a0903 := clk; a0904 := clk; a0905 := clk; a0906 := clk; a0907 := clk; a0908 := clk; a0909 := clk; a0910 := clk; a0911 := clk; a0912 := clk; a0913 := clk; a0914 := clk; a0915 := clk; a0916 := clk; a0917 := clk; a0918 := clk; a0919 := clk; a0920 := clk; a0921 := clk; a0922 := clk; a0923 := clk; a0924 := clk; a0925 := clk; a0926 := clk; a0927 := clk; a0928 := clk; a0929 := clk; a0930 := clk; a0931 := clk; a0932 := clk; a0933 := clk; a0934 := clk; a0935 := clk; a0936 := clk; a0937 := clk; a0938 := clk; a0939 := clk; a0940 := clk; a0941 := clk; a0942 := clk; a0943 := clk; a0944 := clk; a0945 := clk; a0946 := clk; a0947 := clk; a0948 := clk; a0949 := clk; a0950 := clk; a0951 := clk; a0952 := clk; a0953 := clk; a0954 := clk; a0955 := clk; a0956 := clk; a0957 := clk; a0958 := clk; a0959 := clk; a0960 := clk; a0961 := clk; a0962 := clk; a0963 := clk; a0964 := clk; a0965 := clk; a0966 := clk; a0967 := clk; a0968 := clk; a0969 := clk; a0970 := clk; a0971 := clk; a0972 := clk; a0973 := clk; a0974 := clk; a0975 := clk; a0976 := clk; a0977 := clk; a0978 := clk; a0979 := clk; a0980 := clk; a0981 := clk; a0982 := clk; a0983 := clk; a0984 := clk; a0985 := clk; a0986 := clk; a0987 := clk; a0988 := clk; a0989 := clk; a0990 := clk; a0991 := clk; a0992 := clk; a0993 := clk; a0994 := clk; a0995 := clk; a0996 := clk; a0997 := clk; a0998 := clk; a0999 := clk; a1000 := clk; --}}} end process; terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; clk <= (clk+1) after 1 us; end;

gpl-3.0

6c1913ef843634fe476b700dafdbb19e

0.636517

2.729194

false

takeshineshiro/fpga_fibre_scan

HUCB2P0_150701/p2s_dac.vhd

1

897

library ieee; use ieee.std_logic_1164.all; entity p2s_dac is port( a,clk,clr: in std_logic; datain1:in std_logic_vector(15 downto 0); ld,s_data: out std_logic); end p2s_dac; architecture art of p2s_dac is begin process(a,clk,clr) variable I: integer; begin if(clr='1') then I:=0;ld<='0'; elsif( clk'event and clk='1') then if(a='1') then if(I=0) then I:=16; s_data<='0'; else s_data<=datain1(I-1); I:=I-1; ld<='1'; end if; else ld<='0'; end if; end if; end process ; end art;

apache-2.0

3adee115ec36b0157a23fdb7b08196ff

0.354515

4.022422

false

grwlf/vsim

vhdl_ct/ct00489.vhd

1

7,554

-- NEED RESULT: ARCH00489: Aggregates with others choice associated with formal generic (locally static) passed -- NEED RESULT: ARCH00489: Aggregates with others choice associated with formal parameter (locally static) passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00489 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (3) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00489(ARCH00489) -- ENT00489_Test_Bench(ARCH00489_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00489 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; constant r1 : integer := 1 ; constant a11 : boolean := false ; constant a12 : boolean := true ; constant a21 : integer := 1 ; constant a22 : integer := 5 ; constant b11 : integer := 0 ; constant b12 : integer := 0 ; constant b21 : integer := -5 ; constant b22 : integer := -3 ; constant c1 : integer := 0 ; constant c2 : integer := 4 ; constant d1 : integer := 3 ; constant d2 : integer := 5 ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - r1 to r1 ; -- f2 : rec_arr (-r1 to r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-r1 to r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range a11 to a12 ; subtype arange2 is integer range a21 to a22 ; subtype brange1 is integer range b11 to b12 ; subtype brange2 is integer range b21 to b22 ; subtype crange is integer range c1 to c2 ; subtype drange is integer range d1 to d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00489 ; -- architecture ARCH00489 of ENT00489 is begin B1 : block generic ( g_arr_1 : st_arr_1 ; g_time_matrix : st_time_matrix ; g_bit_vector : st_bit_vector ; g_string : st_string ; g_rec_1 : rec_1 ) ; generic map ( ( ( c_rec_1_1, others => c_rec_1_2 ), others => (others => c_rec_1_1) ) , ( st_time_matrix'right(1) => ( st_time_matrix'right(2) => 10 ns, others => 5 fs), others => (brange2'left => 10 ps, others => 15ms) ) , ( 0 => '1', 2 => '1', others => '0' ) , ( 3 => 'a', 4 => 'b', others => '0' ) , -- ( f2 => (r1 => true, others => false ) , ( f3 => 1, others => 0) ) ; -- procedure p1 ( p_arr_1 : st_arr_1 ; p_time_matrix : st_time_matrix ; p_bit_vector : st_bit_vector ; p_string : st_string ; p_rec_1 : rec_1 ) is variable bool : boolean := true ; begin bool := bool and g_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and g_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and g_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and g_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and g_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and g_bit_vector = B"10100" ; -- bool := bool and g_string = "ab0" ; -- bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0 and g_rec_1.f3 = 1 ; -- bool := bool and g_rec_1.f2(1) = true -- and g_rec_1.f2(0) = false and -- g_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00489" , "Aggregates with others choice associated with formal" & " generic (locally static)" , bool ) ; -- bool := true ; bool := bool and p_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and p_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and p_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and p_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and p_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and p_bit_vector = B"10100" ; -- bool := bool and p_string = "ab0" ; -- bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0 and p_rec_1.f3 = 1 ; -- bool := bool and p_rec_1.f2(1) = true -- and p_rec_1.f2(0) = false and -- p_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00489" , "Aggregates with others choice associated with formal" & " parameter (locally static)" , bool ) ; end p1 ; begin process begin p1 ( ( ( c_rec_1_1, others => c_rec_1_2 ), others => (others => c_rec_1_1) ) , ( st_time_matrix'right(1) => ( st_time_matrix'right(2) => 10 ns, others => 5 fs), others => (brange2'left => 10 ps, others => 15ms) ) , ( 0 => '1', 2 => '1', others => '0' ) , ( 3 => 'a', 4 => 'b', others => '0' ) , -- ( f2 => (r1 => true, others => false ) , ( f3 => 1, others => 0) ) ; wait ; end process ; end block B1 ; end ARCH00489 ; -- entity ENT00489_Test_Bench is end ENT00489_Test_Bench ; -- architecture ARCH00489_Test_Bench of ENT00489_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00489 ( ARCH00489 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00489_Test_Bench ;

gpl-3.0

ab9cf63a25938b4bf05220378c6d30da

0.459624

3.317523

false

true

false

grwlf/vsim

vhdl_ct/ct00625.vhd

1

5,945

-- NEED RESULT: ARCH00625: Concurrent proc call 1 passed -- NEED RESULT: ARCH00625.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00625: Concurrent proc call 2 passed -- NEED RESULT: ARCH00625: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00625: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00625 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00625(ARCH00625) -- ENT00625_Test_Bench(ARCH00625_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00625 is end ENT00625 ; -- -- architecture ARCH00625 of ENT00625 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_rec3_select : select_type := 1 ; -- signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- procedure P1 (signal s_st_rec3 : in st_rec3 ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_2.f3(lowb,true) after 10 ns, -- c_st_rec3_1.f3(lowb,true) after 20 ns ; -- when 1 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_2.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_1.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_2.f3(lowb,true) after 10 ns , -- c_st_rec3_1.f3(lowb,true) after 20 ns , -- c_st_rec3_2.f3(lowb,true) after 30 ns , -- c_st_rec3_1.f3(lowb,true) after 40 ns ; -- when 3 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_2.f3(lowb,true) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec3.f3(lowb,true) <= transport -- c_st_rec3_1.f3(lowb,true) after 5 ns ; -- when 4 => correct := s_st_rec3.f3(lowb,true) = c_st_rec3_1.f3(lowb,true) and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00625" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00625" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00625" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec3_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_rec3 , st_rec3_select , s_st_rec3_savt , chk_st_rec3 , s_st_rec3_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_rec3_select select s_st_rec3.f3(lowb,true) <= transport c_st_rec3_2.f3(lowb,true) after 10 ns, c_st_rec3_1.f3(lowb,true) after 20 ns when 1, -- c_st_rec3_2.f3(lowb,true) after 10 ns , c_st_rec3_1.f3(lowb,true) after 20 ns , c_st_rec3_2.f3(lowb,true) after 30 ns , c_st_rec3_1.f3(lowb,true) after 40 ns when 2, -- c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ; -- end ARCH00625 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00625_Test_Bench is end ENT00625_Test_Bench ; -- -- architecture ARCH00625_Test_Bench of ENT00625_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00625 ( ARCH00625 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00625_Test_Bench ;

gpl-3.0

2e421ff5c2a9dee1a1ca70583f8e3cf3

0.507485

3.216991

false

true

false

grwlf/vsim

vhdl_ct/ct00098.vhd

1

15,031

-- NEED RESULT: ARCH00098.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098.P2: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098.P3: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00098: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00098 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00098(ARCH00098) -- ENT00098_Test_Bench(ARCH00098_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00098 is port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- end ENT00098 ; -- architecture ARCH00098 of ENT00098 is begin PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_arr1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_arr1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P1" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_1(highb) ( st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_arr2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P2" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_arr3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00098.P3" , "Multi transport transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00098" , "One transport transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00098" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- -- end ARCH00098 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00098_Test_Bench is signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00098_Test_Bench ; -- architecture ARCH00098_Test_Bench of ENT00098_Test_Bench is begin L1: block component UUT port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00098 ( ARCH00098 ) ; begin CIS1 : UUT port map ( s_st_arr1_vector , s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00098_Test_Bench ;

gpl-3.0

3580077d237c74535aed5ac827aa8f3e

0.505223

3.591637

false

true

false

grwlf/vsim

vhdl_ct/ct00408.vhd

1

22,816

-- NEED RESULT: ARCH00408.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00408 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00408(ARCH00408) -- ENT00408_Test_Bench(ARCH00408_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00408 is port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00408 ; -- -- architecture ARCH00408 of ENT00408 is subtype chk_time_type is Time ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_rec2_vector_savt : chk_time_type := 0 ns ; signal s_st_rec3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_rec1_vector_select : select_type := 1 ; signal st_rec2_vector_select : select_type := 1 ; signal st_rec3_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns, -- c_st_rec1_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_vector_select <= transport 2 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; st_rec1_vector_select <= transport 3 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 4 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 5 ; -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_2(lowb).f2 after 10 ns , -- c_st_rec1_vector_1(lowb).f2 after 20 ns , -- c_st_rec1_vector_2(lowb).f2 after 30 ns , -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1_vector(lowb).f2 <= -- c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(lowb).f2 and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_vector_savt <= transport Std.Standard.Now ; chk_st_rec1_vector <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ; wait until (not s_st_rec1_vector(lowb).f2'Quiet) and (s_st_rec1_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_rec1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec1_vector(lowb).f2 <= c_st_rec1_vector_2(lowb).f2 after 10 ns, c_st_rec1_vector_1(lowb).f2 after 20 ns when st_rec1_vector_select = 1 else -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when st_rec1_vector_select = 2 else -- c_st_rec1_vector_1(lowb).f2 after 5 ns when st_rec1_vector_select = 3 else -- c_st_rec1_vector_1(lowb).f2 after 100 ns when st_rec1_vector_select = 4 else -- c_st_rec1_vector_2(lowb).f2 after 10 ns , c_st_rec1_vector_1(lowb).f2 after 20 ns , c_st_rec1_vector_2(lowb).f2 after 30 ns , c_st_rec1_vector_1(lowb).f2 after 40 ns when st_rec1_vector_select = 5 else -- -- Last transaction above is marked c_st_rec1_vector_1(lowb).f2 after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_st_rec2_vector_cnt is when 0 => null ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns, -- c_st_rec2_vector_1(lowb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_vector_select <= transport 2 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; st_rec2_vector_select <= transport 3 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 4 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 5 ; -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_2(lowb).f2 after 10 ns , -- c_st_rec2_vector_1(lowb).f2 after 20 ns , -- c_st_rec2_vector_2(lowb).f2 after 30 ns , -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2_vector(lowb).f2 <= -- c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(lowb).f2 and (s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_vector_savt <= transport Std.Standard.Now ; chk_st_rec2_vector <= transport s_st_rec2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ; wait until (not s_st_rec2_vector(lowb).f2'Quiet) and (s_st_rec2_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_rec2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_rec2_vector(lowb).f2 <= c_st_rec2_vector_2(lowb).f2 after 10 ns, c_st_rec2_vector_1(lowb).f2 after 20 ns when st_rec2_vector_select = 1 else -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when st_rec2_vector_select = 2 else -- c_st_rec2_vector_1(lowb).f2 after 5 ns when st_rec2_vector_select = 3 else -- c_st_rec2_vector_1(lowb).f2 after 100 ns when st_rec2_vector_select = 4 else -- c_st_rec2_vector_2(lowb).f2 after 10 ns , c_st_rec2_vector_1(lowb).f2 after 20 ns , c_st_rec2_vector_2(lowb).f2 after 30 ns , c_st_rec2_vector_1(lowb).f2 after 40 ns when st_rec2_vector_select = 5 else -- -- Last transaction above is marked c_st_rec2_vector_1(lowb).f2 after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_st_rec3_vector_cnt is when 0 => null ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns, -- c_st_rec3_vector_1(highb).f3 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_vector_select <= transport 2 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; st_rec3_vector_select <= transport 3 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 4 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 100 ns ; -- when 5 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 5 ; -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_2(highb).f3 after 10 ns , -- c_st_rec3_vector_1(highb).f3 after 20 ns , -- c_st_rec3_vector_2(highb).f3 after 30 ns , -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 6 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_2(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3_vector(highb).f3 <= -- c_st_rec3_vector_1(highb).f3 after 40 ns ; -- when 7 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3_vector(highb).f3 = c_st_rec3_vector_1(highb).f3 and (s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00408" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_vector_savt <= transport Std.Standard.Now ; chk_st_rec3_vector <= transport s_st_rec3_vector_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ; wait until (not s_st_rec3_vector(highb).f3'Quiet) and (s_st_rec3_vector_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_st_rec3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_rec3_vector(highb).f3 <= c_st_rec3_vector_2(highb).f3 after 10 ns, c_st_rec3_vector_1(highb).f3 after 20 ns when st_rec3_vector_select = 1 else -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when st_rec3_vector_select = 2 else -- c_st_rec3_vector_1(highb).f3 after 5 ns when st_rec3_vector_select = 3 else -- c_st_rec3_vector_1(highb).f3 after 100 ns when st_rec3_vector_select = 4 else -- c_st_rec3_vector_2(highb).f3 after 10 ns , c_st_rec3_vector_1(highb).f3 after 20 ns , c_st_rec3_vector_2(highb).f3 after 30 ns , c_st_rec3_vector_1(highb).f3 after 40 ns when st_rec3_vector_select = 5 else -- -- Last transaction above is marked c_st_rec3_vector_1(highb).f3 after 40 ns ; -- end ARCH00408 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00408_Test_Bench is signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- end ENT00408_Test_Bench ; -- -- architecture ARCH00408_Test_Bench of ENT00408_Test_Bench is begin L1: block component UUT port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00408 ( ARCH00408 ) ; begin CIS1 : UUT port map ( s_st_rec1_vector , s_st_rec2_vector , s_st_rec3_vector ) ; end block L1 ; end ARCH00408_Test_Bench ;

gpl-3.0

45ad81bee1f443f64b1d792425f14b0c

0.5103

3.294254

false

jairov4/accel-oil

impl/impl_test_pcie/hdl/system_ac1_plb_wrapper.vhd

1

14,691

------------------------------------------------------------------------------- -- system_ac1_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_ac1_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_ac1_plb_wrapper : entity is "plb_v46_v1_05_a"; end system_ac1_plb_wrapper; architecture STRUCTURE of system_ac1_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin ac1_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 15, C_PLBV46_NUM_SLAVES => 1, C_PLBV46_MID_WIDTH => 4, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;

lgpl-3.0

5d7a89905b39706b2cfcfc3e077b90e5

0.611871

3.039098

false

grwlf/vsim

vhdl_ct/ct00025.vhd

1

7,581

-- NEED RESULT: ENT00025: Associated composite in ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00025 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (4) -- 1.1.1.2 (7) -- -- DESIGN UNIT ORDERING: -- -- ENT00025(ARCH00025) -- ENT00025_Test_Bench(ARCH00025_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00025 is port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; begin end ENT00025 ; -- architecture ARCH00025 of ENT00025 is begin process variable correct : boolean := true ; begin correct := correct and i_bit_vector_1 = c_st_bit_vector_1 and i_bit_vector_2 = c_st_bit_vector_1 ; correct := correct and i_string_1 = c_st_string_1 and i_string_2 = c_st_string_1 ; correct := correct and i_t_rec1_1 = c_st_rec1_1 and i_t_rec1_2 = c_st_rec1_1 ; correct := correct and i_st_rec1_1 = c_st_rec1_1 and i_st_rec1_2 = c_st_rec1_1 ; correct := correct and i_t_rec2_1 = c_st_rec2_1 and i_t_rec2_2 = c_st_rec2_1 ; correct := correct and i_st_rec2_1 = c_st_rec2_1 and i_st_rec2_2 = c_st_rec2_1 ; correct := correct and i_t_rec3_1 = c_st_rec3_1 and i_t_rec3_2 = c_st_rec3_1 ; correct := correct and i_st_rec3_1 = c_st_rec3_1 and i_st_rec3_2 = c_st_rec3_1 ; correct := correct and i_t_arr1_1 = c_st_arr1_1 and i_t_arr1_2 = c_st_arr1_1 ; correct := correct and i_st_arr1_1 = c_st_arr1_1 and i_st_arr1_2 = c_st_arr1_1 ; correct := correct and i_t_arr2_1 = c_st_arr2_1 and i_t_arr2_2 = c_st_arr2_1 ; correct := correct and i_st_arr2_1 = c_st_arr2_1 and i_st_arr2_2 = c_st_arr2_1 ; correct := correct and i_t_arr3_1 = c_st_arr3_1 and i_t_arr3_2 = c_st_arr3_1 ; correct := correct and i_st_arr3_1 = c_st_arr3_1 and i_st_arr3_2 = c_st_arr3_1 ; -- test_report ( "ENT00025" , "Associated composite in ports with static subtypes" , correct) ; wait ; end process ; end ARCH00025 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00025_Test_Bench is end ENT00025_Test_Bench ; -- architecture ARCH00025_Test_Bench of ENT00025_Test_Bench is begin L1: block signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector := c_st_bit_vector_1 ; signal i_string_1, i_string_2 : st_string := c_st_string_1 ; signal i_t_rec1_1, i_t_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_t_rec2_1, i_t_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_t_rec3_1, i_t_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_t_arr1_1, i_t_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_t_arr2_1, i_t_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_t_arr3_1, i_t_arr3_2 : st_arr3 := c_st_arr3_1 ; signal i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- component UUT port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00025 ( ARCH00025 ) ; -- begin CIS1 : UUT port map ( i_bit_vector_1, i_bit_vector_2, i_string_1, i_string_2, i_t_rec1_1, i_t_rec1_2, i_st_rec1_1, i_st_rec1_2, i_t_rec2_1, i_t_rec2_2, i_st_rec2_1, i_st_rec2_2, i_t_rec3_1, i_t_rec3_2, i_st_rec3_1, i_st_rec3_2, i_t_arr1_1, i_t_arr1_2, i_st_arr1_1, i_st_arr1_2, i_t_arr2_1, i_t_arr2_2, i_st_arr2_1, i_st_arr2_2, i_t_arr3_1, i_t_arr3_2, i_st_arr3_1, i_st_arr3_2 ) ; end block L1 ; end ARCH00025_Test_Bench ;

gpl-3.0

4e9dc50f41cbbbc3b11bb394eac75486

0.415908

2.749728

false

grwlf/vsim

vhdl_ct/ct00529.vhd

1

3,403

-- NEED RESULT: ARCH00529: Actual parameter list absent in function calls passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00529 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.3 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00529) -- ENT00529_Test_Bench(ARCH00529_Test_Bench) -- -- REVISION HISTORY: -- -- 17-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00529 of E00000 is type arr_1 is array ( boolean range <> , integer range <> ) of bit ; type arr_2 is array ( integer range <> ) of integer ; type rec_1 is record f1 : boolean ; f2 : integer ; end record ; subtype st_arr_1 is arr_1 ( true downto false , 1 to 4 ) ; subtype st_arr_2 is arr_2 ( -2 to 3 ) ; begin process variable correct : boolean := true ; function f1 return boolean is begin return false ; end f1 ; function f2 return integer is begin return 3 ; end f2 ; function f3 return arr_1 is variable v_st_arr_1 : st_arr_1 ; begin v_st_arr_1(false, 1) := '1' ; v_st_arr_1(false, 2) := '0' ; v_st_arr_1(false, 3) := '1' ; v_st_arr_1(false, 4) := '0' ; v_st_arr_1(true, 1) := '0' ; v_st_arr_1(true, 2) := '1' ; v_st_arr_1(true, 3) := '0' ; v_st_arr_1(true, 4) := '1' ; return v_st_arr_1 ; end f3 ; function f4 return st_arr_1 is begin return ( ( '1' , '0', '1', '0' ), ( '0' , '1', '0', '1' ) ) ; end f4 ; function f5 return st_arr_2 is begin return (-2, -1, 0, 1, 2, 3) ; end f5 ; function f6 return rec_1 is begin return (false, 3) ; end f6 ; begin correct := correct and f3(false, 1) = '1' and f3(false, 2) = '0' and f3(false, 3) = '1' and f3(false, 4) = '0' and f3(true, 1) = '0' and f3(true, 2) = '1' and f3(true, 3) = '0' and f3(true, 4) = '1' ; correct := correct and f4(true, 1) = '1' and f4(true, 2) = '0' and f4(true, 3) = '1' and f4(true, 4) = '0' and f4(false, 1) = '0' and f4(false, 2) = '1' and f4(false, 3) = '0' and f4(false, 4) = '1' ; correct := correct and f5(-2 to 3) = (-2, -1, 0, 1, 2, 3) ; correct := correct and f6.f1 = false and f6.f2 = 3 ; test_report ( "ARCH00529" , "Actual parameter list absent in function calls" , correct and f1 = false and f2 = 3 ) ; wait ; end process ; end ARCH00529 ; -- entity ENT00529_Test_Bench is end ENT00529_Test_Bench ; architecture ARCH00529_Test_Bench of ENT00529_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00529 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00529_Test_Bench ; --

gpl-3.0

89e23f6af5b727a17331748ac4503594

0.458419

3.06853

false

true

false

MilosSubotic/huffman_coding

RTL/src/rtl/quasi_tree.vhd

1

3,423

------------------------------------------------------------------------------ -- @license MIT -- @brief Building quasi-tree. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.global.all; entity quasi_tree is port( i_clk : in std_logic; in_rst : in std_logic; i_stage : in t_stage; i_pipe_en : in std_logic; i_sort_sym : in t_sym_array(0 to 15); i_sort_cnt : in t_cnt_array(0 to 15); o_child0 : out t_node_and_cnt; o_child1 : out t_node_and_cnt; o_new_parent : out t_node_and_cnt ); end entity quasi_tree; architecture arch_quasi_tree_v1 of quasi_tree is signal leaves : t_node_and_cnt_array(0 to 15); signal parents : t_node_and_cnt_array(0 to 15); signal parents_end : std_logic_vector(3 downto 0); signal new_parent_node : t_node; signal child0 : t_node_and_cnt; signal child1 : t_node_and_cnt; signal new_parent : t_node_and_cnt; signal next_leaves : t_node_and_cnt_array(0 to 15); signal next_parents : t_node_and_cnt_array(0 to 15); signal leaves_shift : std_logic_vector(1 downto 0); signal parents_shift : std_logic_vector(1 downto 0); signal leaves_shifter : t_node_and_cnt_array(0 to 15); signal parents_shifter : t_node_and_cnt_array(0 to 15); signal push_new_parent : std_logic; signal cmp0 : std_logic; signal cmp1 : std_logic; signal cmp2 : std_logic; begin process(i_clk, in_rst) begin if in_rst = '0' then leaves_node <= (others => ("11111", "11111")); parents_node <= (others => ("11111", "11111")); elsif rising_edge(i_clk) then leaves <= next_leaves; parents <= next_parents; end if; end process; next_leaves <= i_sort_sym when stage_i = 16 else leaves_shifter; ls: for i in 0 to 13 generate with leaves_shift select leaves_shifter(i) <= leaves(i) when "00", leaves(i+1) when "01", leaves(i+2) when others; end generate; with leaves_shift select leaves_shifter(14) <= leaves(14) when "00", leaves(15) when "01", ("11111", "11111") when others; with leaves_shift select leaves_shifter(15) <= leaves(15) when "00", ("11111", "11111") when "01", ("11111", "11111") when others; next_parents <= (others => "11111") when stage_i = 16 else parents_pusher; pp: for i in 0 to 15 generate parents_pusher(i) <= new_parent when parents_end = i and push_new_parent = '1' else parents_shifter; end generate; ps: for i in 0 to 13 generate with parents_shift select parents_shifter(i) <= parents(i) when "00", parents(i+1) when "01", parents(i+2) when others; end generate; with parents_shift select parents_shifter(14) <= parents(14) when "00", parents(15) when "01", ("11111", "11111") when others; with parents_shift select parents_shifter(15) <= parents(15) when "00", ("11111", "11111") when "01", ("11111", "11111") when others; cmp0 <= '1' when leaves(0).cnt < parents(0).cnt else '1'; cmp1 <= '1' when leaves(1).cnt < parents(0).cnt else '1'; cmp2 <= '1' when parents(1).cnt < leaves(0).cnt else '1'; end architecture arch_quasi_tree_v1;

mit

eb91b44d70eac823523ccb445a415be0

0.577564

2.908241

false

TWW12/lzw

ip_repo/axi_compression_1.0/src/dictionary_block_2.vhd

4

5,040

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity dictionary_block_2 is generic( block_num : integer := 0); port ( clk : in std_logic; rst : in std_logic; start_search : in std_logic; search_entry : in std_logic_vector(19 downto 0); halt_search : in std_logic; --Write enable & entries wr_en : in std_logic; wr_addr : in std_logic_vector(10 downto 0); wr_entry : in std_logic_vector(19 downto 0); --Outputs prefix : out std_logic_vector(10 downto 0); entry_found : out std_logic; search_completed : out std_logic); end dictionary_block_2; architecture Behavioral of dictionary_block_2 is component bram_2048_0 is PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); end component; component bram_2048_1 is PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); end component; type state_type is (S_RST,S_GO,S_WAIT,S_SEARCH); signal state : state_type; signal rd_addr : std_logic_vector(11 downto 0); signal addr : std_logic_vector(10 downto 0); signal bram_out : std_logic_vector(19 downto 0); signal full : std_logic; signal rd_addr_delay : std_logic_vector(11 downto 0); signal wr_entry_delay : std_logic_vector(19 downto 0); begin GEN_BLOCK_0: if block_num = 0 generate U_BRAM : bram_2048_0 port map( clka => clk, ena => '1', wea(0) => wr_en, addra => addr, dina => wr_entry_delay, douta => bram_out); end generate GEN_BLOCK_0; GEN_BLOCK_1 : if block_num = 1 generate U_BRAM : bram_2048_1 port map( clka => clk, ena => '1', wea(0) => wr_en, addra => addr, dina => wr_entry_delay, douta => bram_out); end generate GEN_BLOCK_1; with wr_en select addr <= wr_addr when '1', rd_addr(10 downto 0) when others; process(clk,rst) begin if rst = '1' then state <= S_RST; rd_addr <= (rd_addr'range => '0'); entry_found <= '0'; search_completed <= '0'; prefix <= (prefix'range => '0'); wr_entry_delay <= (wr_entry_delay'range => '0'); rd_addr_delay <= (rd_addr_delay'range => '0'); elsif rising_edge(clk) then rd_addr_delay <= rd_addr; wr_entry_delay <= wr_entry; case state is when S_RST => state <= S_GO; --idle until its time to search when S_GO => rd_addr <= (rd_addr'range => '0'); entry_found <= '0'; search_completed <= '0'; prefix <= (prefix'range => '0'); if start_search = '1' then state <= S_WAIT; end if; when S_WAIT => state <= S_SEARCH; when S_SEARCH => rd_addr <= std_logic_vector(unsigned(rd_addr)+to_unsigned(1,12)); --Did we find the entry? if search_entry = bram_out then state <= S_GO; entry_found <= '1'; search_completed <= '1'; prefix <= rd_addr_delay(10 downto 0);--std_logic_vector(unsigned(rd_addr(10 downto 0))-to_unsigned(1,11)); rd_addr <= (others => '0'); end if; --Did we go through the whole dictionary? if start_search = '1' then state <= S_SEARCH; rd_addr <= (others => '0'); elsif halt_search = '1' then state <= S_GO; rd_addr <= (others => '0'); elsif rd_addr = std_logic_vector(unsigned(wr_addr)+to_unsigned(3,12)) then state <= S_GO; rd_addr <= (others => '0'); search_completed <= '1'; end if; end case; end if; end process; end Behavioral;

unlicense

c28bbd5306de6b0a77eeedfc4ffade14

0.44504

4.094232

false

TWW12/lzw

ip_repo/axi_compression_1.0/src/clock_counter.vhd

3

1,794

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clock_counter is Port ( enable : in STD_LOGIC; count : out STD_LOGIC_VECTOR (31 downto 0); done : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC); end clock_counter; architecture Behavioral of clock_counter is type state_type is (RESET,COUNT_CLOCK,COUNT_DONE); signal state : state_type; signal temp_count : std_logic_vector (31 downto 0); begin count <= temp_count; process(clk,rst) begin if rst = '1' then state <= RESET; temp_count <= (temp_count'range => '0'); elsif rising_edge(clk) then case state is when RESET => state <= RESET; if enable = '1' then state <= COUNT_CLOCK; end if; when COUNT_CLOCK => if done = '1' then temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32)); state <= COUNT_DONE; elsif done ='0' then temp_count <= std_logic_vector(unsigned(temp_count)+to_unsigned(1,32)); state <= COUNT_CLOCK; else temp_count <= temp_count; state <= COUNT_CLOCK; end if; when COUNT_DONE => temp_count <= temp_count; state <= COUNT_DONE; end case; end if; end process; end Behavioral;

unlicense

d4bc33b0a0d6a27b0361df11ea1d4519

0.432553

4.83558

false

jairov4/accel-oil

solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if_async_fifo.vhd

1

5,831

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_initials_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_initials_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;

lgpl-3.0

cd81fa65ca3a197638e589ce0906c032

0.55445

3.405958

false

grwlf/vsim

vhdl_ct/ct00314.vhd

1

5,437

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00314 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (1) -- 7.2.3 (2) -- 7.2.3 (8) -- 7.2.3 (9) -- 7.2.3 (10) -- -- DESIGN UNIT ORDERING: -- -- ENT00314(ARCH00314) -- ENT00314_Test_Bench(ARCH00314_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES ; use WORK.ARITHMETIC.ALL ; entity ENT00314 is generic ( i_int_1 : integer := c_int_1 ; i_int_2 : integer := c_int_2 ; i_t_int_1 : t_int := c_t_int_1 ; i_t_int_2 : t_int := c_t_int_2 ; i_st_int_1 : st_int := c_st_int_1 ; i_st_int_2 : st_int := c_st_int_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00314 ; architecture ARCH00314 of ENT00314 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; -- variable v_int_1, v2_int_1 : integer := c_int_1 ; variable v_int_2, v2_int_2 : integer := c_int_2 ; variable v_t_int_1, v2_t_int_1 : t_int := c_t_int_1 ; variable v_t_int_2, v2_t_int_2 : t_int := c_t_int_2 ; variable v_st_int_1, v2_st_int_1 : st_int := c_st_int_1 ; variable v_st_int_2, v2_st_int_2 : st_int := c_st_int_2 ; -- constant c2_int_1 : integer := (((+i_int_1) + (-i_int_2)) + ((-i_int_1) + (-i_int_2))) - (((+i_int_1) - (-c_int_2)) - ((-c_int_2) - (-i_int_1))) - 28 ; constant c2_t_int_1 : t_int := (((+i_t_int_1) + (-i_t_int_2)) + ((-i_t_int_1) + (-i_t_int_2))) - (((+i_t_int_1) - (-c_t_int_2)) - ((-c_t_int_2) - (-i_t_int_1))) - 5 ; constant c2_st_int_1 : st_int := -(((+i_st_int_1) + (-i_t_int_2)) + ((-i_st_int_1) + (-i_st_int_2))) - (((+i_st_int_1) - (-c_st_int_2)) - ((-c_t_int_2) - (-i_st_int_1))) - 5 ; begin -- -- static expression -- case bool is when ( (((+c_int_1) + (-c_int_2)) + ((-c_int_1) + (-c_int_2))) - (((+c_int_1) - (-c_int_2)) - ((-c_int_2) - (-c_int_1))) - 28 = ans_int1 and (((+c_t_int_1) + (-c_t_int_2)) + ((-c_t_int_1) + (-c_t_int_2))) - (((+c_t_int_1) - (-c_t_int_2)) - ((-c_t_int_2) - (-c_t_int_1))) - 5 = ans_int2 and -(((+c_st_int_1) + (-c_t_int_2)) + ((-c_st_int_1) + (-c_st_int_2))) - (((+c_st_int_1) - (-c_st_int_2)) - ((-c_t_int_2) - (-c_st_int_1))) - 5 = ans_int3 ) => null ; when others => cons_correct := false ; end case ; -- -- generic expression -- gen_correct := c2_int_1 = ans_int1 and c2_t_int_1 = ans_int2 and c2_st_int_1= ans_int3 ; -- -- dynamic expression -- v_int_1 := (((+v2_int_1) + (-v2_int_2)) + ((-v2_int_1) + (-v2_int_2))) - (((+v2_int_1) - (-c_int_2)) - ((-c_int_2) - (-v2_int_1))) - 28 ; v_t_int_1 := (((+v2_t_int_1) + (-v2_t_int_2)) + ((-v2_t_int_1) + (-v2_t_int_2))) - (((+v2_t_int_1) - (-i_t_int_2)) - ((-c_t_int_2) - (-v2_t_int_1))) - 5 ; v_st_int_1 := -(((+v2_st_int_1) + (-v2_t_int_2)) + ((-v2_st_int_1) + (-v2_st_int_2))) - (((+v2_st_int_1) - (-c_st_int_2)) - ((-i_t_int_2) - (-v2_st_int_1))) - 5 ; dyn_correct := true ; dyn_correct := v_int_1 = ans_int1 and v_t_int_1 = ans_int2 and v_st_int_1 = ans_int3 ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait ; end process ; end ARCH00314 ; use WORK.STANDARD_TYPES.all ; entity ENT00314_Test_Bench is end ENT00314_Test_Bench ; architecture ARCH00314_Test_Bench of ENT00314_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end component ; for CIS1 : UUT use entity WORK.ENT00314 ( ARCH00314 ) ; begin CIS1 : UUT port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then WORK.STANDARD_TYPES.test_report ( "ARCH00314" , "+ and - unary and binary operators are correctly" & " predefined for integer types" , true ) ; end if ; end process ; end block L1 ; end ARCH00314_Test_Bench ;

gpl-3.0

21c8d273569c6167f49da55a964194df

0.448225

2.833246

false

true

false

jairov4/accel-oil

solution_spartan6/impl/vhdl/p_bsf32_hw.vhd

4

81,430

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity p_bsf32_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end; architecture behav of p_bsf32_hw is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001"; constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010"; constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011"; constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100"; constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101"; constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110"; constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111"; constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000"; constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001"; constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010"; constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011"; constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100"; constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101"; constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110"; constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111"; constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000"; constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001"; constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010"; constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011"; constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100"; constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101"; constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110"; constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111"; constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000"; constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001"; constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010"; constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011"; constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100"; constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101"; constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110"; constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_true : BOOLEAN := true; signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_1_reg_526 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_530 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_3_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_3_reg_534 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_4_reg_538 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_reg_542 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_6_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_6_reg_546 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_7_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_7_reg_550 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_reg_554 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_558 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_reg_562 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_reg_566 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_reg_570 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_13_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_13_reg_574 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_14_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_14_reg_578 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_15_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_15_reg_582 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_reg_586 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_reg_590 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_reg_594 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_reg_598 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_20_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_20_reg_602 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_21_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_21_reg_606 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_22_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_22_reg_610 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_reg_614 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_reg_618 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_reg_622 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_reg_626 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_27_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_27_reg_630 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_reg_634 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_reg_638 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_30_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_30_reg_642 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0); signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0); signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0); signal ap_sig_bdd_764 : BOOLEAN; signal ap_sig_bdd_178 : BOOLEAN; signal ap_sig_bdd_183 : BOOLEAN; signal ap_sig_bdd_189 : BOOLEAN; signal ap_sig_bdd_196 : BOOLEAN; signal ap_sig_bdd_204 : BOOLEAN; signal ap_sig_bdd_213 : BOOLEAN; signal ap_sig_bdd_223 : BOOLEAN; signal ap_sig_bdd_234 : BOOLEAN; signal ap_sig_bdd_246 : BOOLEAN; signal ap_sig_bdd_259 : BOOLEAN; signal ap_sig_bdd_273 : BOOLEAN; signal ap_sig_bdd_288 : BOOLEAN; signal ap_sig_bdd_304 : BOOLEAN; signal ap_sig_bdd_321 : BOOLEAN; signal ap_sig_bdd_339 : BOOLEAN; signal ap_sig_bdd_358 : BOOLEAN; signal ap_sig_bdd_378 : BOOLEAN; signal ap_sig_bdd_399 : BOOLEAN; signal ap_sig_bdd_421 : BOOLEAN; signal ap_sig_bdd_444 : BOOLEAN; signal ap_sig_bdd_468 : BOOLEAN; signal ap_sig_bdd_493 : BOOLEAN; signal ap_sig_bdd_519 : BOOLEAN; signal ap_sig_bdd_546 : BOOLEAN; signal ap_sig_bdd_574 : BOOLEAN; signal ap_sig_bdd_603 : BOOLEAN; signal ap_sig_bdd_633 : BOOLEAN; signal ap_sig_bdd_664 : BOOLEAN; signal ap_sig_bdd_696 : BOOLEAN; signal ap_sig_bdd_730 : BOOLEAN; begin -- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. -- ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_764) then ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1'; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1); ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2); ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3); ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4); end if; end if; end if; end process; -- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. -- ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_730) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E; elsif (ap_sig_bdd_696) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D; elsif (ap_sig_bdd_664) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C; elsif (ap_sig_bdd_633) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B; elsif (ap_sig_bdd_603) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A; elsif (ap_sig_bdd_574) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19; elsif (ap_sig_bdd_546) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18; elsif (ap_sig_bdd_519) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17; elsif (ap_sig_bdd_493) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16; elsif (ap_sig_bdd_468) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15; elsif (ap_sig_bdd_444) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14; elsif (ap_sig_bdd_421) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13; elsif (ap_sig_bdd_399) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12; elsif (ap_sig_bdd_378) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11; elsif (ap_sig_bdd_358) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10; elsif (ap_sig_bdd_339) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F; elsif (ap_sig_bdd_321) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E; elsif (ap_sig_bdd_304) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D; elsif (ap_sig_bdd_288) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C; elsif (ap_sig_bdd_273) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B; elsif (ap_sig_bdd_259) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A; elsif (ap_sig_bdd_246) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9; elsif (ap_sig_bdd_234) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8; elsif (ap_sig_bdd_223) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7; elsif (ap_sig_bdd_213) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6; elsif (ap_sig_bdd_204) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5; elsif (ap_sig_bdd_196) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4; elsif (ap_sig_bdd_189) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3; elsif (ap_sig_bdd_183) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2; elsif (ap_sig_bdd_178) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1; elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3))) then tmp_10_reg_562 <= bus_r(10 downto 10); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3))) then tmp_11_reg_566 <= bus_r(11 downto 11); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3))) then tmp_12_reg_570 <= bus_r(12 downto 12); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3))) then tmp_13_reg_574 <= bus_r(13 downto 13); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3))) then tmp_14_reg_578 <= bus_r(14 downto 14); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3))) then tmp_15_reg_582 <= bus_r(15 downto 15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3))) then tmp_16_reg_586 <= bus_r(16 downto 16); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3))) then tmp_17_reg_590 <= bus_r(17 downto 17); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3))) then tmp_18_reg_594 <= bus_r(18 downto 18); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3))) then tmp_19_reg_598 <= bus_r(19 downto 19); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then tmp_1_reg_526 <= bus_r(1 downto 1); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3))) then tmp_20_reg_602 <= bus_r(20 downto 20); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3))) then tmp_21_reg_606 <= bus_r(21 downto 21); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3))) then tmp_22_reg_610 <= bus_r(22 downto 22); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3))) then tmp_23_reg_614 <= bus_r(23 downto 23); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3))) then tmp_24_reg_618 <= bus_r(24 downto 24); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3))) then tmp_25_reg_622 <= bus_r(25 downto 25); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3))) then tmp_26_reg_626 <= bus_r(26 downto 26); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3))) then tmp_27_reg_630 <= bus_r(27 downto 27); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3))) then tmp_28_reg_634 <= bus_r(28 downto 28); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3))) then tmp_29_reg_638 <= bus_r(29 downto 29); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0))) then tmp_2_reg_530 <= bus_r(2 downto 2); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3))) then tmp_30_reg_642 <= bus_r(30 downto 30); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3))) then tmp_3_reg_534 <= bus_r(3 downto 3); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3))) then tmp_4_reg_538 <= bus_r(4 downto 4); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3))) then tmp_5_reg_542 <= bus_r(5 downto 5); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3))) then tmp_6_reg_546 <= bus_r(6 downto 6); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3))) then tmp_7_reg_550 <= bus_r(7 downto 7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3))) then tmp_8_reg_554 <= bus_r(8 downto 8); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3))) then tmp_9_reg_558 <= bus_r(9 downto 9); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then tmp_reg_522 <= tmp_fu_278_p1; end if; end if; end process; ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1'; ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1; ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1; ap_return <= merge_phi_fu_269_p4; -- ap_sig_bdd_178 assign process. -- ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3) begin ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_1_fu_282_p3 = ap_const_lv1_0))); end process; -- ap_sig_bdd_183 assign process. -- ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3) begin ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_290_p3))); end process; -- ap_sig_bdd_189 assign process. -- ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3) begin ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and not((ap_const_lv1_0 = tmp_3_fu_298_p3))); end process; -- ap_sig_bdd_196 assign process. -- ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3) begin ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and not((ap_const_lv1_0 = tmp_4_fu_306_p3))); end process; -- ap_sig_bdd_204 assign process. -- ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3) begin ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and not((ap_const_lv1_0 = tmp_5_fu_314_p3))); end process; -- ap_sig_bdd_213 assign process. -- ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3) begin ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and not((ap_const_lv1_0 = tmp_6_fu_322_p3))); end process; -- ap_sig_bdd_223 assign process. -- ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3) begin ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and not((ap_const_lv1_0 = tmp_7_fu_330_p3))); end process; -- ap_sig_bdd_234 assign process. -- ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3) begin ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and not((ap_const_lv1_0 = tmp_8_fu_338_p3))); end process; -- ap_sig_bdd_246 assign process. -- ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3) begin ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and not((ap_const_lv1_0 = tmp_9_fu_346_p3))); end process; -- ap_sig_bdd_259 assign process. -- ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3) begin ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and not((ap_const_lv1_0 = tmp_10_fu_354_p3))); end process; -- ap_sig_bdd_273 assign process. -- ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3) begin ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and not((ap_const_lv1_0 = tmp_11_fu_362_p3))); end process; -- ap_sig_bdd_288 assign process. -- ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3) begin ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and not((ap_const_lv1_0 = tmp_12_fu_370_p3))); end process; -- ap_sig_bdd_304 assign process. -- ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3) begin ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and not((ap_const_lv1_0 = tmp_13_fu_378_p3))); end process; -- ap_sig_bdd_321 assign process. -- ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3) begin ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and not((ap_const_lv1_0 = tmp_14_fu_386_p3))); end process; -- ap_sig_bdd_339 assign process. -- ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3) begin ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and not((ap_const_lv1_0 = tmp_15_fu_394_p3))); end process; -- ap_sig_bdd_358 assign process. -- ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3) begin ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and not((ap_const_lv1_0 = tmp_16_fu_402_p3))); end process; -- ap_sig_bdd_378 assign process. -- ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3) begin ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and not((ap_const_lv1_0 = tmp_17_fu_410_p3))); end process; -- ap_sig_bdd_399 assign process. -- ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3) begin ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and not((ap_const_lv1_0 = tmp_18_fu_418_p3))); end process; -- ap_sig_bdd_421 assign process. -- ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3) begin ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and not((ap_const_lv1_0 = tmp_19_fu_426_p3))); end process; -- ap_sig_bdd_444 assign process. -- ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3) begin ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and not((ap_const_lv1_0 = tmp_20_fu_434_p3))); end process; -- ap_sig_bdd_468 assign process. -- ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3) begin ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and not((ap_const_lv1_0 = tmp_21_fu_442_p3))); end process; -- ap_sig_bdd_493 assign process. -- ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3) begin ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and not((ap_const_lv1_0 = tmp_22_fu_450_p3))); end process; -- ap_sig_bdd_519 assign process. -- ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3) begin ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and not((ap_const_lv1_0 = tmp_23_fu_458_p3))); end process; -- ap_sig_bdd_546 assign process. -- ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3) begin ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and not((ap_const_lv1_0 = tmp_24_fu_466_p3))); end process; -- ap_sig_bdd_574 assign process. -- ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3) begin ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and not((ap_const_lv1_0 = tmp_25_fu_474_p3))); end process; -- ap_sig_bdd_603 assign process. -- ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3) begin ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and not((ap_const_lv1_0 = tmp_26_fu_482_p3))); end process; -- ap_sig_bdd_633 assign process. -- ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3) begin ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and not((ap_const_lv1_0 = tmp_27_fu_490_p3))); end process; -- ap_sig_bdd_664 assign process. -- ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3) begin ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and not((ap_const_lv1_0 = tmp_28_fu_498_p3))); end process; -- ap_sig_bdd_696 assign process. -- ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3) begin ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and not((ap_const_lv1_0 = tmp_29_fu_506_p3))); end process; -- ap_sig_bdd_730 assign process. -- ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3, tmp_30_fu_514_p3) begin ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3) and not((ap_const_lv1_0 = tmp_30_fu_514_p3))); end process; -- ap_sig_bdd_764 assign process. -- ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_1_fu_282_p3, tmp_2_fu_290_p3, tmp_3_fu_298_p3, tmp_4_fu_306_p3, tmp_5_fu_314_p3, tmp_6_fu_322_p3, tmp_7_fu_330_p3, tmp_8_fu_338_p3, tmp_9_fu_346_p3, tmp_10_fu_354_p3, tmp_11_fu_362_p3, tmp_12_fu_370_p3, tmp_13_fu_378_p3, tmp_14_fu_386_p3, tmp_15_fu_394_p3, tmp_16_fu_402_p3, tmp_17_fu_410_p3, tmp_18_fu_418_p3, tmp_19_fu_426_p3, tmp_20_fu_434_p3, tmp_21_fu_442_p3, tmp_22_fu_450_p3, tmp_23_fu_458_p3, tmp_24_fu_466_p3, tmp_25_fu_474_p3, tmp_26_fu_482_p3, tmp_27_fu_490_p3, tmp_28_fu_498_p3, tmp_29_fu_506_p3, tmp_30_fu_514_p3) begin ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_1_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_290_p3) and (ap_const_lv1_0 = tmp_3_fu_298_p3) and (ap_const_lv1_0 = tmp_4_fu_306_p3) and (ap_const_lv1_0 = tmp_5_fu_314_p3) and (ap_const_lv1_0 = tmp_6_fu_322_p3) and (ap_const_lv1_0 = tmp_7_fu_330_p3) and (ap_const_lv1_0 = tmp_8_fu_338_p3) and (ap_const_lv1_0 = tmp_9_fu_346_p3) and (ap_const_lv1_0 = tmp_10_fu_354_p3) and (ap_const_lv1_0 = tmp_11_fu_362_p3) and (ap_const_lv1_0 = tmp_12_fu_370_p3) and (ap_const_lv1_0 = tmp_13_fu_378_p3) and (ap_const_lv1_0 = tmp_14_fu_386_p3) and (ap_const_lv1_0 = tmp_15_fu_394_p3) and (ap_const_lv1_0 = tmp_16_fu_402_p3) and (ap_const_lv1_0 = tmp_17_fu_410_p3) and (ap_const_lv1_0 = tmp_18_fu_418_p3) and (ap_const_lv1_0 = tmp_19_fu_426_p3) and (ap_const_lv1_0 = tmp_20_fu_434_p3) and (ap_const_lv1_0 = tmp_21_fu_442_p3) and (ap_const_lv1_0 = tmp_22_fu_450_p3) and (ap_const_lv1_0 = tmp_23_fu_458_p3) and (ap_const_lv1_0 = tmp_24_fu_466_p3) and (ap_const_lv1_0 = tmp_25_fu_474_p3) and (ap_const_lv1_0 = tmp_26_fu_482_p3) and (ap_const_lv1_0 = tmp_27_fu_490_p3) and (ap_const_lv1_0 = tmp_28_fu_498_p3) and (ap_const_lv1_0 = tmp_29_fu_506_p3) and (ap_const_lv1_0 = tmp_30_fu_514_p3)); end process; -- merge_phi_fu_269_p4 assign process. -- merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_1_reg_526, tmp_2_reg_530, tmp_3_reg_534, tmp_4_reg_538, tmp_5_reg_542, tmp_6_reg_546, tmp_7_reg_550, tmp_8_reg_554, tmp_9_reg_558, tmp_10_reg_562, tmp_11_reg_566, tmp_12_reg_570, tmp_13_reg_574, tmp_14_reg_578, tmp_15_reg_582, tmp_16_reg_586, tmp_17_reg_590, tmp_18_reg_594, tmp_19_reg_598, tmp_20_reg_602, tmp_21_reg_606, tmp_22_reg_610, tmp_23_reg_614, tmp_24_reg_618, tmp_25_reg_622, tmp_26_reg_626, tmp_27_reg_630, tmp_28_reg_634, tmp_29_reg_638, tmp_30_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1) begin if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_1_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_2_reg_530)) or not((ap_const_lv1_0 = tmp_3_reg_534)) or not((ap_const_lv1_0 = tmp_4_reg_538)) or not((ap_const_lv1_0 = tmp_5_reg_542)) or not((ap_const_lv1_0 = tmp_6_reg_546)) or not((ap_const_lv1_0 = tmp_7_reg_550)) or not((ap_const_lv1_0 = tmp_8_reg_554)) or not((ap_const_lv1_0 = tmp_9_reg_558)) or not((ap_const_lv1_0 = tmp_10_reg_562)) or not((ap_const_lv1_0 = tmp_11_reg_566)) or not((ap_const_lv1_0 = tmp_12_reg_570)) or not((ap_const_lv1_0 = tmp_13_reg_574)) or not((ap_const_lv1_0 = tmp_14_reg_578)) or not((ap_const_lv1_0 = tmp_15_reg_582)) or not((ap_const_lv1_0 = tmp_16_reg_586)) or not((ap_const_lv1_0 = tmp_17_reg_590)) or not((ap_const_lv1_0 = tmp_18_reg_594)) or not((ap_const_lv1_0 = tmp_19_reg_598)) or not((ap_const_lv1_0 = tmp_20_reg_602)) or not((ap_const_lv1_0 = tmp_21_reg_606)) or not((ap_const_lv1_0 = tmp_22_reg_610)) or not((ap_const_lv1_0 = tmp_23_reg_614)) or not((ap_const_lv1_0 = tmp_24_reg_618)) or not((ap_const_lv1_0 = tmp_25_reg_622)) or not((ap_const_lv1_0 = tmp_26_reg_626)) or not((ap_const_lv1_0 = tmp_27_reg_630)) or not((ap_const_lv1_0 = tmp_28_reg_634)) or not((ap_const_lv1_0 = tmp_29_reg_638)) or not((ap_const_lv1_0 = tmp_30_reg_642)))) then merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1; else merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1; end if; end process; tmp_10_fu_354_p3 <= bus_r(10 downto 10); tmp_11_fu_362_p3 <= bus_r(11 downto 11); tmp_12_fu_370_p3 <= bus_r(12 downto 12); tmp_13_fu_378_p3 <= bus_r(13 downto 13); tmp_14_fu_386_p3 <= bus_r(14 downto 14); tmp_15_fu_394_p3 <= bus_r(15 downto 15); tmp_16_fu_402_p3 <= bus_r(16 downto 16); tmp_17_fu_410_p3 <= bus_r(17 downto 17); tmp_18_fu_418_p3 <= bus_r(18 downto 18); tmp_19_fu_426_p3 <= bus_r(19 downto 19); tmp_1_fu_282_p3 <= bus_r(1 downto 1); tmp_20_fu_434_p3 <= bus_r(20 downto 20); tmp_21_fu_442_p3 <= bus_r(21 downto 21); tmp_22_fu_450_p3 <= bus_r(22 downto 22); tmp_23_fu_458_p3 <= bus_r(23 downto 23); tmp_24_fu_466_p3 <= bus_r(24 downto 24); tmp_25_fu_474_p3 <= bus_r(25 downto 25); tmp_26_fu_482_p3 <= bus_r(26 downto 26); tmp_27_fu_490_p3 <= bus_r(27 downto 27); tmp_28_fu_498_p3 <= bus_r(28 downto 28); tmp_29_fu_506_p3 <= bus_r(29 downto 29); tmp_2_fu_290_p3 <= bus_r(2 downto 2); tmp_30_fu_514_p3 <= bus_r(30 downto 30); tmp_3_fu_298_p3 <= bus_r(3 downto 3); tmp_4_fu_306_p3 <= bus_r(4 downto 4); tmp_5_fu_314_p3 <= bus_r(5 downto 5); tmp_6_fu_322_p3 <= bus_r(6 downto 6); tmp_7_fu_330_p3 <= bus_r(7 downto 7); tmp_8_fu_338_p3 <= bus_r(8 downto 8); tmp_9_fu_346_p3 <= bus_r(9 downto 9); tmp_fu_278_p1 <= bus_r(1 - 1 downto 0); end behav;

lgpl-3.0

b7a94bb746a66b7320ccdffc3742a15f

0.614552

2.114955

false

jairov4/accel-oil

solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_initials_buckets_if_ap_fifo.vhd

2

2,845

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_initials_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC := '1'; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC := '1'; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of nfa_initials_buckets_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;

lgpl-3.0

ee2d019d8eb19371b2fac493691e3160

0.495958

3.642766

false

grwlf/vsim

vhdl_ct/ct00631.vhd

1

3,742

-- NEED RESULT: ARCH00631: Index constraints passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00631 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 3.2.1.1 (4) -- 3.2.1.1 (5) -- 3.2.1.1 (6) -- 3.2.1.1 (7) -- 3.2.1.1 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00631) -- ENT00631_Test_Bench(ARCH00631_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- 18-JAN-1987 - removed refs to predefined attributes on func calls -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES; use STANDARD_TYPES.all ; architecture ARCH00631 of E00000 is begin P : process constant c : STANDARD_TYPES.t_arr1 := c_st_arr1_1 ; variable v : integer ; attribute a : STANDARD_TYPES.t_arr1 ; attribute a of v : variable is c_st_arr1_1 ; type array_access is access STANDARD_TYPES.t_arr1 ; variable ptr : array_access ; variable low1, high1, left1, right1, low2, high2, left2, right2 : integer := 9999 ; variable st : STANDARD_TYPES.st_arr1 := c_st_arr1_1 ; subtype t_100 is STANDARD_TYPES.t_arr1 (100+st_arr1'left to 100+st_arr1'right) ; variable t : t_100 := c_st_arr1_1 ; procedure proc_with_unconstrained_array ( a : in STANDARD_TYPES.t_arr1 ; lo,hi,lft,rght : out integer ) is begin lo := a'low ; hi := a'high ; lft := a'left ; rght := a'right ; end proc_with_unconstrained_array ; procedure proc_with_constrained_array ( a : in STANDARD_TYPES.st_arr1 ; lo,hi,lft,rght : out integer ) is begin lo := a'low ; hi := a'high ; lft := a'left ; rght := a'right ; end proc_with_constrained_array ; begin proc_with_unconstrained_array ( st, low1, high1, left1, right1 ) ; proc_with_constrained_array ( t, low2, high2, left2, right2 ) ; ptr := new t_arr1(1 to 10) ; test_report ( "ARCH00631" , "Index constraints" , (c'low = st_arr1'low) and -- these test 3.2.1.1 (4) (c'high = st_arr1'high) and (c'left = st_arr1'left) and (c'right = st_arr1'right) and -- (v'a'low = st_arr1'low) and -- these test 3.2.1.1 (5) -- (v'a'high = st_arr1'high) and -- (v'a'left = st_arr1'left) and -- (v'a'right = st_arr1'right) and (ptr.all'low = 1) and -- these test 3.2.1.1 (6) (ptr.all'high = 10) and (ptr.all'left = 1) and (ptr.all'right = 10) and (low1 = st_arr1'low) and -- these test 3.2.1.1 (8) (high1 = st_arr1'high) and (left1 = st_arr1'left) and (right1 = st_arr1'right) and (low2 = st_arr1'low) and -- these test 3.2.1.1 (7) (high2 = st_arr1'high) and (left2 = st_arr1'left) and (right2 = st_arr1'right) ) ; wait ; end process P ; end ARCH00631 ; -- entity ENT00631_Test_Bench is end ENT00631_Test_Bench ; architecture ARCH00631_Test_Bench of ENT00631_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00631 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00631_Test_Bench ; --

gpl-3.0

d9992477999a174278e253c8f3770245

0.495991

3.069729

false

true

false

TWW12/lzw

ip_repo/axi_compression_1.0/src/bram_1024_2/synth/bram_1024_2.vhd

4

14,457

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY bram_1024_2 IS PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) ); END bram_1024_2; ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" & "f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" & "PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" & "_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "bram_1024_2.mif", C_INIT_FILE => "bram_1024_2.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 20, C_READ_WIDTH_A => 20, C_WRITE_DEPTH_A => 1024, C_READ_DEPTH_A => 1024, C_ADDRA_WIDTH => 10, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 20, C_READ_WIDTH_B => 20, C_WRITE_DEPTH_B => 1024, C_READ_DEPTH_B => 1024, C_ADDRB_WIDTH => 10, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "1", C_COUNT_18K_BRAM => "0", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END bram_1024_2_arch;

unlicense

e0716f4d3170d600acd22fd66e4a2ce2

0.625372

3.002492

false

grwlf/vsim

vhdl_ct/ct00034.vhd

1

27,414

-- NEED RESULT: ARCH00034.P1: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P2: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P3: Target of a variable assignment may be a slice passed -- NEED RESULT: ARCH00034.P4: Target of a variable assignment may be a slice passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00034 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00034) -- ENT00034_Test_Bench(ARCH00034_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00034 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P1" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00034.P2" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P3" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; variable v_st_bit_vector : st_bit_vector := c_st_bit_vector_1 ; variable v_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; variable v_st_string : st_string := c_st_string_1 ; variable v_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_time_vector : st_time_vector := c_st_time_vector_1 ; variable v_st_phys1_vector : st_phys1_vector := c_st_phys1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; variable v_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; variable v_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; variable v_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; variable v_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; variable v_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; variable v_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_boolean_vector : inout st_boolean_vector ; v_st_bit_vector : inout st_bit_vector ; v_st_severity_level_vector : inout st_severity_level_vector ; v_st_string : inout st_string ; v_st_enum1_vector : inout st_enum1_vector ; v_st_integer_vector : inout st_integer_vector ; v_st_int1_vector : inout st_int1_vector ; v_st_time_vector : inout st_time_vector ; v_st_phys1_vector : inout st_phys1_vector ; v_st_real_vector : inout st_real_vector ; v_st_real1_vector : inout st_real1_vector ; v_st_rec1_vector : inout st_rec1_vector ; v_st_rec2_vector : inout st_rec2_vector ; v_st_rec3_vector : inout st_rec3_vector ; v_st_arr1_vector : inout st_arr1_vector ; v_st_arr2_vector : inout st_arr2_vector ; v_st_arr3_vector : inout st_arr3_vector ) is begin v_st_boolean_vector(lowb+1 to highb-1) := c_st_boolean_vector_2(lowb+1 to highb-1) ; v_st_bit_vector(lowb+1 to highb-1) := c_st_bit_vector_2(lowb+1 to highb-1) ; v_st_severity_level_vector(lowb+1 to highb-1) := c_st_severity_level_vector_2(lowb+1 to highb-1) ; v_st_string(lowb+1 to highb-1) := c_st_string_2(lowb+1 to highb-1) ; v_st_enum1_vector(lowb+1 to highb-1) := c_st_enum1_vector_2(lowb+1 to highb-1) ; v_st_integer_vector(lowb+1 to highb-1) := c_st_integer_vector_2(lowb+1 to highb-1) ; v_st_int1_vector(lowb+1 to highb-1) := c_st_int1_vector_2(lowb+1 to highb-1) ; v_st_time_vector(lowb+1 to highb-1) := c_st_time_vector_2(lowb+1 to highb-1) ; v_st_phys1_vector(lowb+1 to highb-1) := c_st_phys1_vector_2(lowb+1 to highb-1) ; v_st_real_vector(lowb+1 to highb-1) := c_st_real_vector_2(lowb+1 to highb-1) ; v_st_real1_vector(lowb+1 to highb-1) := c_st_real1_vector_2(lowb+1 to highb-1) ; v_st_rec1_vector(lowb+1 to highb-1) := c_st_rec1_vector_2(lowb+1 to highb-1) ; v_st_rec2_vector(lowb+1 to highb-1) := c_st_rec2_vector_2(lowb+1 to highb-1) ; v_st_rec3_vector(lowb+1 to highb-1) := c_st_rec3_vector_2(lowb+1 to highb-1) ; v_st_arr1_vector(lowb+1 to highb-1) := c_st_arr1_vector_2(lowb+1 to highb-1) ; v_st_arr2_vector(lowb+1 to highb-1) := c_st_arr2_vector_2(lowb+1 to highb-1) ; v_st_arr3_vector(lowb+1 to highb-1) := c_st_arr3_vector_2(lowb+1 to highb-1) ; -- end Proc1 ; begin Proc1 ( v_st_boolean_vector , v_st_bit_vector , v_st_severity_level_vector , v_st_string , v_st_enum1_vector , v_st_integer_vector , v_st_int1_vector , v_st_time_vector , v_st_phys1_vector , v_st_real_vector , v_st_real1_vector , v_st_rec1_vector , v_st_rec2_vector , v_st_rec3_vector , v_st_arr1_vector , v_st_arr2_vector , v_st_arr3_vector ) ; correct := correct and v_st_boolean_vector(lowb+1 to highb-1) = c_st_boolean_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_bit_vector(lowb+1 to highb-1) = c_st_bit_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_severity_level_vector(lowb+1 to highb-1) = c_st_severity_level_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_string(lowb+1 to highb-1) = c_st_string_2(lowb+1 to highb-1) ; correct := correct and v_st_enum1_vector(lowb+1 to highb-1) = c_st_enum1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_integer_vector(lowb+1 to highb-1) = c_st_integer_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_int1_vector(lowb+1 to highb-1) = c_st_int1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_time_vector(lowb+1 to highb-1) = c_st_time_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_phys1_vector(lowb+1 to highb-1) = c_st_phys1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real_vector(lowb+1 to highb-1) = c_st_real_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_real1_vector(lowb+1 to highb-1) = c_st_real1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec1_vector(lowb+1 to highb-1) = c_st_rec1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec2_vector(lowb+1 to highb-1) = c_st_rec2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_rec3_vector(lowb+1 to highb-1) = c_st_rec3_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr1_vector(lowb+1 to highb-1) = c_st_arr1_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr2_vector(lowb+1 to highb-1) = c_st_arr2_vector_2(lowb+1 to highb-1) ; correct := correct and v_st_arr3_vector(lowb+1 to highb-1) = c_st_arr3_vector_2(lowb+1 to highb-1) ; -- test_report ( "ARCH00034.P4" , "Target of a variable assignment may be a " & "slice" , correct) ; end process P4 ; -- end ARCH00034 ; -- entity ENT00034_Test_Bench is end ENT00034_Test_Bench ; -- architecture ARCH00034_Test_Bench of ENT00034_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00034 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00034_Test_Bench ;

gpl-3.0

834bfcdf74efbce805a9045c9412b35b

0.514372

3.003945

false

grwlf/vsim

vhdl_ct/ct00218.vhd

1

5,433

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00218 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.1 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00218(ARCH00218) -- ENT00218_Test_Bench(ARCH00218_Test_Bench) -- -- REVISION HISTORY: -- -- 10-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00218 is generic (G : integer) ; port ( s_st_arr1_vector : inout st_arr1_vector ) ; -- constant CG : integer := G+1; attribute attr : integer ; attribute attr of CG : constant is CG+1; -- end ENT00218 ; -- -- architecture ARCH00218 of ENT00218 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; -- procedure Proc1 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_2(1)(1) ; s_st_arr1_vector(2)(1 to 2) <= transport c_st_arr1_vector_2(2)(1 to 2) after 10 ns ; wait until s_st_arr1_vector(2)(1 to 2) = c_st_arr1_vector_2(2)(1 to 2) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(2)(1 to 2) = c_st_arr1_vector_2(2)(1 to 2) )) ; -- when 1 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_1(1)(1) ; s_st_arr1_vector(G)(G-1 to G) <= transport c_st_arr1_vector_2(G)(G-1 to G) after 10 ns ; wait until s_st_arr1_vector(G)(G-1 to G) = c_st_arr1_vector_2(G)(G-1 to G) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(G)(G-1 to G) = c_st_arr1_vector_2(G)(G-1 to G) )) ; -- when 2 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_2(1)(1) ; s_st_arr1_vector(CG)(CG-1 to CG) <= transport c_st_arr1_vector_2(CG)(CG-1 to CG) after 10 ns ; wait until s_st_arr1_vector(CG)(CG-1 to CG) = c_st_arr1_vector_2(CG)(CG-1 to CG) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(CG)(CG-1 to CG) = c_st_arr1_vector_2(CG)(CG-1 to CG) )) ; -- when 3 => s_st_arr1_vector(1)(1) <= transport c_st_arr1_vector_1(1)(1) ; s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) <= transport c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) after 10 ns ; wait until s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) = c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) ; Test_Report ( "ENT00218", "Wait statement longest static prefix check", ((savtime + 10 ns) = Std.Standard.Now) and (s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) = c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) )) ; -- when others => wait ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time := 0 ns ; begin Proc1 ( s_st_arr1_vector , counter , correct , savtime , chk_st_arr1_vector ) ; end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Wait longest static prefix test completed", chk_st_arr1_vector = 3 ) ; end if ; end process PGEN_CHKP_1 ; -- -- end ARCH00218 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00218_Test_Bench is end ENT00218_Test_Bench ; -- -- architecture ARCH00218_Test_Bench of ENT00218_Test_Bench is begin L1: block signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; -- component UUT generic (G : integer) ; port ( s_st_arr1_vector : inout st_arr1_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00218 ( ARCH00218 ) ; begin CIS1 : UUT generic map (lowb+2) port map ( s_st_arr1_vector ) ; end block L1 ; end ARCH00218_Test_Bench ;

gpl-3.0

6c8378613eb040f7ca4a9f476d51409a

0.492546

3.296723

false

true

false

jairov4/accel-oil

solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw_add_64ns_64ns_64_2.vhd

1

7,164

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(63 downto 0); b: in std_logic_vector(63 downto 0); s: out std_logic_vector(63 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is port ( faa : IN STD_LOGIC_VECTOR (32-1 downto 0); fab : IN STD_LOGIC_VECTOR (32-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (32-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (32-1 downto 0); fab : IN STD_LOGIC_VECTOR (32-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (32-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(63 downto 0); signal b_reg : std_logic_vector(63 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(31 downto 0); signal b0_cb : std_logic_vector(31 downto 0); signal a1_cb : std_logic_vector(63 downto 32); signal b1_cb : std_logic_vector(63 downto 32); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(31 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; -- wires for each full adder sum signal fas : std_logic_vector(63 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo0 is array (0 downto 0) of std_logic_vector(31 downto 0); signal s0_ca_rego0 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(63 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(31 downto 0); b0_cb <= b_reg(31 downto 0); a1_cb <= a_reg(63 downto 32); b1_cb <= b_reg(63 downto 32); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(31 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(63 downto 32), facout => faccout1_co1); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(31 downto 0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(31 downto 0) <= s0_ca_rego0(0); s_tmp(63 downto 32) <= fas(63 downto 32); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is generic(N : natural :=32); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is generic(N : natural :=32); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_2 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_64ns_64ns_64_2 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0_U : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_AddSubnS_0 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;

lgpl-3.0

b4c7fe4ed217da6c8362e4b07163573a

0.620324

3.03688

false

jairov4/accel-oil

solution_spartan6/impl/vhdl/sample_iterator_get_offset.vhd

1

42,907

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0'; signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0); signal indices_begin_addr_reg_135 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_147 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_162 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_2_reg_167 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0); signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_116_ce : STD_LOGIC; signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_116_p0, din1 => grp_fu_116_p1, ce => grp_fu_116_ce, dout => grp_fu_116_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 1, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_125_p0, din1 => grp_fu_125_p1, ce => grp_fu_125_ce, dout => grp_fu_125_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it10 assign process. -- ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it10 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it11 assign process. -- ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it11 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it12 assign process. -- ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it12 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it13 assign process. -- ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it13 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it14 assign process. -- ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it14 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it15 assign process. -- ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it15 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it16 assign process. -- ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it16 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it17 assign process. -- ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it17 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130; ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1; ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2; ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3; ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0) <= indices_begin_addr_reg_135(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1) <= indices_begin_addr_reg_135(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2) <= indices_begin_addr_reg_135(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3) <= indices_begin_addr_reg_135(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4) <= indices_begin_addr_reg_135(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5) <= indices_begin_addr_reg_135(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6) <= indices_begin_addr_reg_135(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7) <= indices_begin_addr_reg_135(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8) <= indices_begin_addr_reg_135(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9) <= indices_begin_addr_reg_135(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10) <= indices_begin_addr_reg_135(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11) <= indices_begin_addr_reg_135(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12) <= indices_begin_addr_reg_135(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13) <= indices_begin_addr_reg_135(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14) <= indices_begin_addr_reg_135(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15) <= indices_begin_addr_reg_135(15); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14); ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_130 <= i_sample; indices_begin_addr_reg_135(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0); indices_begin_addr_reg_135(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1); indices_begin_addr_reg_135(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2); indices_begin_addr_reg_135(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3); indices_begin_addr_reg_135(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4); indices_begin_addr_reg_135(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5); indices_begin_addr_reg_135(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6); indices_begin_addr_reg_135(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7); indices_begin_addr_reg_135(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8); indices_begin_addr_reg_135(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9); indices_begin_addr_reg_135(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10); indices_begin_addr_reg_135(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11); indices_begin_addr_reg_135(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12); indices_begin_addr_reg_135(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13); indices_begin_addr_reg_135(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14); indices_begin_addr_reg_135(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_162 <= indices_begin_datain; tmp_2_reg_167 <= grp_fu_116_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_147 <= indices_stride_datain; end if; end if; end process; indices_begin_addr_reg_135(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it9 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it17, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= grp_fu_125_p2; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_116_ce assign process. -- grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_116_ce <= ap_const_logic_1; else grp_fu_116_ce <= ap_const_logic_0; end if; end process; grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0); grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5),24)); grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0); grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_147),24)); -- grp_fu_125_ce assign process. -- grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_125_ce <= ap_const_logic_1; else grp_fu_125_ce <= ap_const_logic_0; end if; end process; grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_2_reg_167),32)); grp_fu_125_p1 <= indices_begin_addr_read_reg_162; indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0); indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64)); end behav;

lgpl-3.0

f70f775b9fa76f104860b9cbdb8b7ef8

0.616939

2.635403

false

grwlf/vsim

vhdl_ct/ct00354.vhd

1

12,986

-- NEED RESULT: ARCH00354.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00354 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00354(ARCH00354) -- ENT00354_Test_Bench(ARCH00354_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00354 is port ( s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- end ENT00354 ; -- -- architecture ARCH00354 of ENT00354 is subtype chk_time_type is Time ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; -- begin CHG1 : process ( s_st_rec1 ) variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1.f2 <= transport -- c_st_rec1_2.f2 after 10 ns, -- c_st_rec1_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec1.f2 = c_st_rec1_2.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1.f2 = c_st_rec1_1.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1.f2 <= transport -- c_st_rec1_2.f2 after 10 ns , -- c_st_rec1_1.f2 after 20 ns , -- c_st_rec1_2.f2 after 30 ns , -- c_st_rec1_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec1.f2 = c_st_rec1_2.f2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1.f2 <= transport -- c_st_rec1_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1.f2 = c_st_rec1_1.f2 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec1.f2 <= transport c_st_rec1_2.f2 after 10 ns, c_st_rec1_1.f2 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2.f2 after 10 ns , c_st_rec1_1.f2 after 20 ns , c_st_rec1_2.f2 after 30 ns , c_st_rec1_1.f2 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1.f2 after 5 ns ; -- CHG2 : process ( s_st_rec2 ) variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2.f2 <= transport -- c_st_rec2_2.f2 after 10 ns, -- c_st_rec2_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec2.f2 = c_st_rec2_2.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2.f2 = c_st_rec2_1.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2.f2 <= transport -- c_st_rec2_2.f2 after 10 ns , -- c_st_rec2_1.f2 after 20 ns , -- c_st_rec2_2.f2 after 30 ns , -- c_st_rec2_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec2.f2 = c_st_rec2_2.f2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2.f2 <= transport -- c_st_rec2_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2.f2 = c_st_rec2_1.f2 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_rec2.f2 <= transport c_st_rec2_2.f2 after 10 ns, c_st_rec2_1.f2 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2.f2 after 10 ns , c_st_rec2_1.f2 after 20 ns , c_st_rec2_2.f2 after 30 ns , c_st_rec2_1.f2 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1.f2 after 5 ns ; -- CHG3 : process ( s_st_rec3 ) variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f2 <= transport -- c_st_rec3_2.f2 after 10 ns, -- c_st_rec3_1.f2 after 20 ns ; -- when 1 => correct := s_st_rec3.f2 = c_st_rec3_2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3.f2 = c_st_rec3_1.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00354.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3.f2 <= transport -- c_st_rec3_2.f2 after 10 ns , -- c_st_rec3_1.f2 after 20 ns , -- c_st_rec3_2.f2 after 30 ns , -- c_st_rec3_1.f2 after 40 ns ; -- when 3 => correct := s_st_rec3.f2 = c_st_rec3_2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3.f2 <= transport -- c_st_rec3_1.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3.f2 = c_st_rec3_1.f2 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00354" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00354" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_st_rec3.f2 <= transport c_st_rec3_2.f2 after 10 ns, c_st_rec3_1.f2 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2.f2 after 10 ns , c_st_rec3_1.f2 after 20 ns , c_st_rec3_2.f2 after 30 ns , c_st_rec3_1.f2 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1.f2 after 5 ns ; -- end ARCH00354 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00354_Test_Bench is signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- end ENT00354_Test_Bench ; -- -- architecture ARCH00354_Test_Bench of ENT00354_Test_Bench is begin L1: block component UUT port ( s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00354 ( ARCH00354 ) ; begin CIS1 : UUT port map ( s_st_rec1 , s_st_rec2 , s_st_rec3 ) ; end block L1 ; end ARCH00354_Test_Bench ;

gpl-3.0

1ac5fbe597bd9ac081a43ba0a39e23ab

0.485215

3.321228

false

true

false

grwlf/vsim

vhdl/entity1.vhd

1

938

-- Simple entity test, in/out ports entity main is end entity main; entity unit1 is port ( inum : in integer; oled : out integer); end entity unit1; architecture unit1_a of unit1 is signal a : integer := 1; begin oled <= inum + a; end architecture unit1_a; architecture main of main is constant CYCLES : integer := 100; signal clk : integer := 0; signal o1 : integer; signal o2 : integer; signal o : integer; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; end if; end process; u1:entity unit1(unit1_a) port map(inum=>clk, oled=>o1); u2:entity unit1(unit1_a) port map(inum=>clk, oled=>o2); clk <= clk + 1 after 1 us; o <= o1 + o2; reporter : process(o) begin report "o=" & integer'image(o); end process; end architecture main;

gpl-3.0

3ebf7e9f82e22b0c7e05ca065760f4b8

0.607676

3.314488

false

grwlf/vsim

vhdl_ct/ct00030.vhd

1

16,190

-- NEED RESULT: ARCH00030.P1: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P2: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P3: Target of a variable assignment may be a simple name passed -- NEED RESULT: ARCH00030.P4: Target of a variable assignment may be a simple name passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00030 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (1) -- 8.4 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00030) -- ENT00030_Test_Bench(ARCH00030_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00030 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P1" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00030.P2" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_boolean := c_boolean_2 ; v_bit := c_bit_2 ; v_severity_level := c_severity_level_2 ; v_character := c_character_2 ; v_st_enum1 := c_st_enum1_2 ; v_integer := c_integer_2 ; v_st_int1 := c_st_int1_2 ; v_time := c_time_2 ; v_st_phys1 := c_st_phys1_2 ; v_real := c_real_2 ; v_st_real1 := c_st_real1_2 ; v_st_rec1 := c_st_rec1_2 ; v_st_rec2 := c_st_rec2_2 ; v_st_rec3 := c_st_rec3_2 ; v_st_arr1 := c_st_arr1_2 ; v_st_arr2 := c_st_arr2_2 ; v_st_arr3 := c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ; correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P3" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_boolean : boolean := c_boolean_1 ; variable v_bit : bit := c_bit_1 ; variable v_severity_level : severity_level := c_severity_level_1 ; variable v_character : character := c_character_1 ; variable v_st_enum1 : st_enum1 := c_st_enum1_1 ; variable v_integer : integer := c_integer_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_time : time := c_time_1 ; variable v_st_phys1 : st_phys1 := c_st_phys1_1 ; variable v_real : real := c_real_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_rec1 : st_rec1 := c_st_rec1_1 ; variable v_st_rec2 : st_rec2 := c_st_rec2_1 ; variable v_st_rec3 : st_rec3 := c_st_rec3_1 ; variable v_st_arr1 : st_arr1 := c_st_arr1_1 ; variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( p_boolean : inout boolean ; p_bit : inout bit ; p_severity_level : inout severity_level ; p_character : inout character ; p_st_enum1 : inout st_enum1 ; p_integer : inout integer ; p_st_int1 : inout st_int1 ; p_time : inout time ; p_st_phys1 : inout st_phys1 ; p_real : inout real ; p_st_real1 : inout st_real1 ; p_st_rec1 : inout st_rec1 ; p_st_rec2 : inout st_rec2 ; p_st_rec3 : inout st_rec3 ; p_st_arr1 : inout st_arr1 ; p_st_arr2 : inout st_arr2 ; p_st_arr3 : inout st_arr3 ) is begin p_boolean := c_boolean_2 ; p_bit := c_bit_2 ; p_severity_level := c_severity_level_2 ; p_character := c_character_2 ; p_st_enum1 := c_st_enum1_2 ; p_integer := c_integer_2 ; p_st_int1 := c_st_int1_2 ; p_time := c_time_2 ; p_st_phys1 := c_st_phys1_2 ; p_real := c_real_2 ; p_st_real1 := c_st_real1_2 ; p_st_rec1 := c_st_rec1_2 ; p_st_rec2 := c_st_rec2_2 ; p_st_rec3 := c_st_rec3_2 ; p_st_arr1 := c_st_arr1_2 ; p_st_arr2 := c_st_arr2_2 ; p_st_arr3 := c_st_arr3_2 ; -- end Proc1 ; begin Proc1 ( v_boolean , v_bit , v_severity_level , v_character , v_st_enum1 , v_integer , v_st_int1 , v_time , v_st_phys1 , v_real , v_st_real1 , v_st_rec1 , v_st_rec2 , v_st_rec3 , v_st_arr1 , v_st_arr2 , v_st_arr3 ) ; correct := correct and v_boolean = c_boolean_2 ; correct := correct and v_bit = c_bit_2 ; correct := correct and v_severity_level = c_severity_level_2 ; correct := correct and v_character = c_character_2 ; correct := correct and v_st_enum1 = c_st_enum1_2 ; correct := correct and v_integer = c_integer_2 ; correct := correct and v_st_int1 = c_st_int1_2 ; correct := correct and v_time = c_time_2 ; correct := correct and v_st_phys1 = c_st_phys1_2 ; correct := correct and v_real = c_real_2 ; correct := correct and v_st_real1 = c_st_real1_2 ; correct := correct and v_st_rec1 = c_st_rec1_2 ; correct := correct and v_st_rec2 = c_st_rec2_2 ; correct := correct and v_st_rec3 = c_st_rec3_2 ; correct := correct and v_st_arr1 = c_st_arr1_2 ; correct := correct and v_st_arr2 = c_st_arr2_2 ; correct := correct and v_st_arr3 = c_st_arr3_2 ; -- test_report ( "ARCH00030.P4" , "Target of a variable assignment may be a " & "simple name" , correct) ; end process P4 ; -- end ARCH00030 ; -- entity ENT00030_Test_Bench is end ENT00030_Test_Bench ; -- architecture ARCH00030_Test_Bench of ENT00030_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00030 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00030_Test_Bench ;

gpl-3.0

9498bb0d7d036ec0c1b23baba731be32

0.450154

3.336768

false

grwlf/vsim

vhdl_ct/ct00549.vhd

1

3,106

-- NEED RESULT: ARCH00549: Constant declarations - composite static subtypes failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00549 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00549) -- ENT00549_Test_Bench(ARCH00549_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00549 of E00000 is begin process variable correct : boolean := true ; constant co_bit_vector_1 : bit_vector := c_st_bit_vector_1 ; constant co_string_1 : string := c_st_string_1 ; constant co_t_rec1_1 : t_rec1 := c_st_rec1_1 ; constant co_st_rec1_1 : st_rec1 := c_st_rec1_1 ; constant co_t_rec2_1 : t_rec2 := c_st_rec2_1 ; constant co_st_rec2_1 : st_rec2 := c_st_rec2_1 ; constant co_t_rec3_1 : t_rec3 := c_st_rec3_1 ; constant co_st_rec3_1 : st_rec3 := c_st_rec3_1 ; constant co_t_arr1_1 : t_arr1 := c_st_arr1_1 ; constant co_st_arr1_1 : st_arr1 := c_st_arr1_1 ; constant co_t_arr2_1 : t_arr2 := c_st_arr2_1 ; constant co_st_arr2_1 : st_arr2 := c_st_arr2_1 ; constant co_t_arr3_1 : t_arr3 := c_st_arr3_1 ; constant co_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and co_string_1 = c_st_string_1 ; correct := correct and co_t_rec1_1 = c_t_rec1_1 ; correct := correct and co_st_rec1_1 = c_st_rec1_1 ; correct := correct and co_t_rec2_1 = c_t_rec2_1 ; correct := correct and co_st_rec2_1 = c_st_rec2_1 ; correct := correct and co_t_rec3_1 = c_t_rec3_1 ; correct := correct and co_st_rec3_1 = c_st_rec3_1 ; correct := correct and co_t_arr1_1 = c_t_arr1_1 ; correct := correct and co_st_arr1_1 = c_st_arr1_1 ; correct := correct and co_t_arr2_1 = c_t_arr2_1 ; correct := correct and co_st_arr2_1 = c_st_arr2_1 ; correct := correct and co_t_arr3_1 = c_t_arr3_1 ; correct := correct and co_st_arr3_1 = c_st_arr3_1 ; test_report ( "ARCH00549" , "Constant declarations - composite static subtypes" , correct) ; wait ; end process ; end ARCH00549 ; -- entity ENT00549_Test_Bench is end ENT00549_Test_Bench ; -- architecture ARCH00549_Test_Bench of ENT00549_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00549 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00549_Test_Bench ;

gpl-3.0

eda3aca7a06c9b741070c25e49a55f99

0.515454

2.919173

false

true

false

grwlf/vsim

vhdl/entity5.vhd

1

854

entity test is end entity test; entity unit is port ( inum : in integer; oled : out integer); end entity unit; architecture unit_a of unit is subtype oneten is integer range 1 to 10 ; signal a : oneten := 1; begin oled <= inum + a; end architecture unit_a; architecture test_arch of test is subtype onetwo is integer range 1 to 2 ; constant CYCLES : integer := 100; signal clk : integer := 0; signal i : integer := 0; signal o1,o2 : integer; begin terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; u1:entity unit(unit_a) port map(inum=>i, oled=>o1); u2:entity unit(unit_a) port map(inum=>i, oled=>o2); clk <= clk + 1 after 1 us; end architecture test_arch;

gpl-3.0

c0b1693ebaef8f5c30915bd43f88f9b8

0.640515

3.247148

false

true

false

jairov4/accel-oil

solution_kintex7/syn/vhdl/sample_iterator_get_offset.vhd

1

35,975

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sample_iterator_get_offset is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of sample_iterator_get_offset is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0'; signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0); signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_reg_135 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_tmp_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal indices_stride_addr_read_reg_145 : STD_LOGIC_VECTOR (7 downto 0); signal indices_begin_addr_read_reg_165 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_p2 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_7_reg_170 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_110_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_110_ce : STD_LOGIC; signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_125_ce : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal grp_fu_110_p00 : STD_LOGIC_VECTOR (23 downto 0); signal grp_fu_110_p10 : STD_LOGIC_VECTOR (23 downto 0); component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (7 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (23 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 generic map ( ID => 0, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 8, dout_WIDTH => 24) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_110_p0, din1 => grp_fu_110_p1, ce => grp_fu_110_ce, dout => grp_fu_110_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 1, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_125_p0, din1 => grp_fu_125_p1, ce => grp_fu_125_ce, dout => grp_fu_125_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it10 assign process. -- ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it10 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it11 assign process. -- ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it11 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it12 assign process. -- ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it12 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it13 assign process. -- ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it13 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it8 assign process. -- ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it8 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it9 assign process. -- ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it9 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130; ap_reg_ppstg_tmp_reg_135_pp0_it1(0) <= tmp_reg_135(0); ap_reg_ppstg_tmp_reg_135_pp0_it1(1) <= tmp_reg_135(1); ap_reg_ppstg_tmp_reg_135_pp0_it1(2) <= tmp_reg_135(2); ap_reg_ppstg_tmp_reg_135_pp0_it1(3) <= tmp_reg_135(3); ap_reg_ppstg_tmp_reg_135_pp0_it1(4) <= tmp_reg_135(4); ap_reg_ppstg_tmp_reg_135_pp0_it1(5) <= tmp_reg_135(5); ap_reg_ppstg_tmp_reg_135_pp0_it1(6) <= tmp_reg_135(6); ap_reg_ppstg_tmp_reg_135_pp0_it1(7) <= tmp_reg_135(7); ap_reg_ppstg_tmp_reg_135_pp0_it1(8) <= tmp_reg_135(8); ap_reg_ppstg_tmp_reg_135_pp0_it1(9) <= tmp_reg_135(9); ap_reg_ppstg_tmp_reg_135_pp0_it1(10) <= tmp_reg_135(10); ap_reg_ppstg_tmp_reg_135_pp0_it1(11) <= tmp_reg_135(11); ap_reg_ppstg_tmp_reg_135_pp0_it1(12) <= tmp_reg_135(12); ap_reg_ppstg_tmp_reg_135_pp0_it1(13) <= tmp_reg_135(13); ap_reg_ppstg_tmp_reg_135_pp0_it1(14) <= tmp_reg_135(14); ap_reg_ppstg_tmp_reg_135_pp0_it1(15) <= tmp_reg_135(15); ap_reg_ppstg_tmp_reg_135_pp0_it2(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(0); ap_reg_ppstg_tmp_reg_135_pp0_it2(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(1); ap_reg_ppstg_tmp_reg_135_pp0_it2(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(2); ap_reg_ppstg_tmp_reg_135_pp0_it2(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(3); ap_reg_ppstg_tmp_reg_135_pp0_it2(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(4); ap_reg_ppstg_tmp_reg_135_pp0_it2(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(5); ap_reg_ppstg_tmp_reg_135_pp0_it2(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(6); ap_reg_ppstg_tmp_reg_135_pp0_it2(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(7); ap_reg_ppstg_tmp_reg_135_pp0_it2(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(8); ap_reg_ppstg_tmp_reg_135_pp0_it2(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(9); ap_reg_ppstg_tmp_reg_135_pp0_it2(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(10); ap_reg_ppstg_tmp_reg_135_pp0_it2(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(11); ap_reg_ppstg_tmp_reg_135_pp0_it2(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(12); ap_reg_ppstg_tmp_reg_135_pp0_it2(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(13); ap_reg_ppstg_tmp_reg_135_pp0_it2(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(14); ap_reg_ppstg_tmp_reg_135_pp0_it2(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(15); ap_reg_ppstg_tmp_reg_135_pp0_it3(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(0); ap_reg_ppstg_tmp_reg_135_pp0_it3(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(1); ap_reg_ppstg_tmp_reg_135_pp0_it3(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(2); ap_reg_ppstg_tmp_reg_135_pp0_it3(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(3); ap_reg_ppstg_tmp_reg_135_pp0_it3(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(4); ap_reg_ppstg_tmp_reg_135_pp0_it3(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(5); ap_reg_ppstg_tmp_reg_135_pp0_it3(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(6); ap_reg_ppstg_tmp_reg_135_pp0_it3(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(7); ap_reg_ppstg_tmp_reg_135_pp0_it3(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(8); ap_reg_ppstg_tmp_reg_135_pp0_it3(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(9); ap_reg_ppstg_tmp_reg_135_pp0_it3(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(10); ap_reg_ppstg_tmp_reg_135_pp0_it3(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(11); ap_reg_ppstg_tmp_reg_135_pp0_it3(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(12); ap_reg_ppstg_tmp_reg_135_pp0_it3(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(13); ap_reg_ppstg_tmp_reg_135_pp0_it3(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(14); ap_reg_ppstg_tmp_reg_135_pp0_it3(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then i_sample_read_reg_130 <= i_sample; tmp_reg_135(0) <= tmp_fu_93_p1(0); tmp_reg_135(1) <= tmp_fu_93_p1(1); tmp_reg_135(2) <= tmp_fu_93_p1(2); tmp_reg_135(3) <= tmp_fu_93_p1(3); tmp_reg_135(4) <= tmp_fu_93_p1(4); tmp_reg_135(5) <= tmp_fu_93_p1(5); tmp_reg_135(6) <= tmp_fu_93_p1(6); tmp_reg_135(7) <= tmp_fu_93_p1(7); tmp_reg_135(8) <= tmp_fu_93_p1(8); tmp_reg_135(9) <= tmp_fu_93_p1(9); tmp_reg_135(10) <= tmp_fu_93_p1(10); tmp_reg_135(11) <= tmp_fu_93_p1(11); tmp_reg_135(12) <= tmp_fu_93_p1(12); tmp_reg_135(13) <= tmp_fu_93_p1(13); tmp_reg_135(14) <= tmp_fu_93_p1(14); tmp_reg_135(15) <= tmp_fu_93_p1(15); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_addr_read_reg_165 <= indices_begin_datain; tmp_7_reg_170 <= grp_fu_110_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_addr_read_reg_145 <= indices_stride_datain; end if; end if; end process; tmp_reg_135(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it1(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it2(31 downto 16) <= "0000000000000000"; ap_reg_ppstg_tmp_reg_135_pp0_it3(31 downto 16) <= "0000000000000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it5 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it13, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it13) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return <= grp_fu_125_p2; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- grp_fu_110_ce assign process. -- grp_fu_110_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_110_ce <= ap_const_logic_1; else grp_fu_110_ce <= ap_const_logic_0; end if; end process; grp_fu_110_p0 <= grp_fu_110_p00(16 - 1 downto 0); grp_fu_110_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1),24)); grp_fu_110_p1 <= grp_fu_110_p10(8 - 1 downto 0); grp_fu_110_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_145),24)); -- grp_fu_125_ce assign process. -- grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then grp_fu_125_ce <= ap_const_logic_1; else grp_fu_125_ce <= ap_const_logic_0; end if; end process; grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_7_reg_170),32)); grp_fu_125_p1 <= indices_begin_addr_read_reg_165; indices_begin_address <= ap_reg_ppstg_tmp_reg_135_pp0_it3; indices_begin_dataout <= ap_const_lv32_0; indices_begin_req_din <= ap_const_logic_0; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_req_write <= ap_const_logic_1; else indices_begin_req_write <= ap_const_logic_0; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_begin_rsp_read <= ap_const_logic_1; else indices_begin_rsp_read <= ap_const_logic_0; end if; end process; indices_begin_size <= ap_const_lv32_1; indices_samples_address <= ap_const_lv32_0; indices_samples_dataout <= ap_const_lv16_0; indices_samples_req_din <= ap_const_logic_0; indices_samples_req_write <= ap_const_logic_0; indices_samples_rsp_read <= ap_const_logic_0; indices_samples_size <= ap_const_lv32_0; indices_stride_address <= tmp_fu_93_p1; indices_stride_dataout <= ap_const_lv8_0; indices_stride_req_din <= ap_const_logic_0; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_req_write <= ap_const_logic_1; else indices_stride_req_write <= ap_const_logic_0; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it5, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then indices_stride_rsp_read <= ap_const_logic_1; else indices_stride_rsp_read <= ap_const_logic_0; end if; end process; indices_stride_size <= ap_const_lv32_1; tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),32)); end behav;

lgpl-3.0

f8ce0d382451392c704eb2e404a4957c

0.607088

2.598786

false

grwlf/vsim

vhdl_ct/pro000012.vhd

1

3,978

-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00009_Test_Bench is end ENT00009_Test_Bench; architecture ARCH00009_Test_Bench of ENT00009_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b2 : byte2 := x"00"; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal ea : enum_array(0 to 3) := (others => a_v); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; signal bit_1, bit_2, bit_3, bit_4 , bit_5, bit_6, bit_7, bit_8 , bit_9, bit_10, bit_11, bit_12 : bit; begin bit_1 <= bv'Transaction; bit_2 <= ra'Transaction; bit_3 <= r'Transaction; bit_4 <= ea'Transaction; bit_5 <= e'Transaction; bit_6 <= I_sa'Transaction; bit_7 <= I_baa'Transaction; bit_8 <= I_saa'Transaction; bit_9 <= b1'Transaction; bit_10 <= b2'Transaction; bit_11 <= clk'Transaction; bit_12 <= clk2'Transaction; clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00009_Test_Bench;

gpl-3.0

0ec03f22e37b08d26f3bb845698b0bd4

0.548014

2.467742

false

Given-Jiang/Binarization

tb_Binarization/reports/Binarization/Binarization_example.vhd

1

2,455

library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity Binarization_example is port( Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0); Avalon_ST_Source_startofpacket : out STD_LOGIC; Avalon_ST_Sink_endofpacket : in STD_LOGIC; Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0); Avalon_ST_Source_valid : out STD_LOGIC; Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0); Avalon_ST_Sink_valid : in STD_LOGIC; Clock : in STD_LOGIC; aclr : in STD_LOGIC; Avalon_ST_Source_ready : in STD_LOGIC; Avalon_MM_Slave_write : in STD_LOGIC; Avalon_ST_Sink_ready : out STD_LOGIC; Avalon_ST_Sink_startofpacket : in STD_LOGIC; Avalon_ST_Source_endofpacket : out STD_LOGIC; Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0)); end entity; architecture rtl of Binarization_example is component Binarization port( Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0); Avalon_ST_Source_startofpacket : out STD_LOGIC; Avalon_ST_Sink_endofpacket : in STD_LOGIC; Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0); Avalon_ST_Source_valid : out STD_LOGIC; Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0); Avalon_ST_Sink_valid : in STD_LOGIC; Clock : in STD_LOGIC; aclr : in STD_LOGIC; Avalon_ST_Source_ready : in STD_LOGIC; Avalon_MM_Slave_write : in STD_LOGIC; Avalon_ST_Sink_ready : out STD_LOGIC; Avalon_ST_Sink_startofpacket : in STD_LOGIC; Avalon_ST_Source_endofpacket : out STD_LOGIC; Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0)); end component; begin Binarization_instance : component Binarization port map( Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Clock => Clock, aclr => aclr, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_data => Avalon_ST_Source_data); end architecture rtl;

mit

182768af9911e3feb515ead5054bb1e3

0.719756

3.042131

false

grwlf/vsim

vhdl_ct/ct00613.vhd

1

49,229

-- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613: Concurrent proc call 1 passed -- NEED RESULT: ARCH00613.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613.P10: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: Concurrent proc call 2 passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00613: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00613: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P10: Transport transactions completed entirely passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00613 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00613(ARCH00613) -- ENT00613_Test_Bench(ARCH00613_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00613 is end ENT00613 ; -- -- architecture ARCH00613 of ENT00613 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; -- signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; -- procedure P1 (signal s_st_boolean_vector : in st_boolean_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns, -- c_st_boolean_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_2(lowb) after 10 ns , -- c_st_boolean_vector_1(lowb) after 20 ns , -- c_st_boolean_vector_2(lowb) after 30 ns , -- c_st_boolean_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_2(lowb) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_boolean_vector(lowb) <= transport -- c_st_boolean_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_boolean_vector(lowb) = c_st_boolean_vector_1(lowb) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_boolean_vector_cnt + 1 ; -- end ; -- procedure P2 (signal s_st_severity_level_vector : in st_severity_level_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns, -- c_st_severity_level_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_2(lowb) after 10 ns , -- c_st_severity_level_vector_1(lowb) after 20 ns , -- c_st_severity_level_vector_2(lowb) after 30 ns , -- c_st_severity_level_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_2(lowb) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_severity_level_vector(lowb) <= transport -- c_st_severity_level_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_severity_level_vector(lowb) = c_st_severity_level_vector_1(lowb) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_severity_level_vector_cnt + 1 ; -- end ; -- procedure P3 (signal s_st_string : in st_string ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns, -- c_st_string_1(highb) after 20 ns ; -- when 1 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_string(highb) <= transport -- c_st_string_2(highb) after 10 ns , -- c_st_string_1(highb) after 20 ns , -- c_st_string_2(highb) after 30 ns , -- c_st_string_1(highb) after 40 ns ; -- when 3 => correct := s_st_string(highb) = c_st_string_2(highb) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_string(highb) <= transport -- c_st_string_1(highb) after 5 ns ; -- when 4 => correct := s_st_string(highb) = c_st_string_1(highb) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_string_cnt + 1 ; -- end ; -- procedure P4 (signal s_st_enum1_vector : in st_enum1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns, -- c_st_enum1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_2(highb) after 10 ns , -- c_st_enum1_vector_1(highb) after 20 ns , -- c_st_enum1_vector_2(highb) after 30 ns , -- c_st_enum1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_2(highb) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_enum1_vector(highb) <= transport -- c_st_enum1_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_enum1_vector(highb) = c_st_enum1_vector_1(highb) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_enum1_vector_cnt + 1 ; -- end ; -- procedure P5 (signal s_st_integer_vector : in st_integer_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns, -- c_st_integer_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_2(lowb) after 10 ns , -- c_st_integer_vector_1(lowb) after 20 ns , -- c_st_integer_vector_2(lowb) after 30 ns , -- c_st_integer_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_2(lowb) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_integer_vector(lowb) <= transport -- c_st_integer_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_integer_vector(lowb) = c_st_integer_vector_1(lowb) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_integer_vector_cnt + 1 ; -- end ; -- procedure P6 (signal s_st_time_vector : in st_time_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns, -- c_st_time_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_2(lowb) after 10 ns , -- c_st_time_vector_1(lowb) after 20 ns , -- c_st_time_vector_2(lowb) after 30 ns , -- c_st_time_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb) = c_st_time_vector_2(lowb) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_time_vector(lowb) <= transport -- c_st_time_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_time_vector(lowb) = c_st_time_vector_1(lowb) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_time_vector_cnt + 1 ; -- end ; -- procedure P7 (signal s_st_real_vector : in st_real_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns, -- c_st_real_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_2(highb) after 10 ns , -- c_st_real_vector_1(highb) after 20 ns , -- c_st_real_vector_2(highb) after 30 ns , -- c_st_real_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb) = c_st_real_vector_2(highb) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_real_vector(highb) <= transport -- c_st_real_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_real_vector(highb) = c_st_real_vector_1(highb) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_real_vector_cnt + 1 ; -- end ; -- procedure P8 (signal s_st_rec1_vector : in st_rec1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns, -- c_st_rec1_vector_1(highb) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_2(highb) after 10 ns , -- c_st_rec1_vector_1(highb) after 20 ns , -- c_st_rec1_vector_2(highb) after 30 ns , -- c_st_rec1_vector_1(highb) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_2(highb) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec1_vector(highb) <= transport -- c_st_rec1_vector_1(highb) after 5 ns ; -- when 4 => correct := s_st_rec1_vector(highb) = c_st_rec1_vector_1(highb) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec1_vector_cnt + 1 ; -- end ; -- procedure P9 (signal s_st_arr2_vector : in st_arr2_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns, -- c_st_arr2_vector_1(lowb) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_2(lowb) after 10 ns , -- c_st_arr2_vector_1(lowb) after 20 ns , -- c_st_arr2_vector_2(lowb) after 30 ns , -- c_st_arr2_vector_1(lowb) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_2(lowb) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2_vector(lowb) <= transport -- c_st_arr2_vector_1(lowb) after 5 ns ; -- when 4 => correct := s_st_arr2_vector(lowb) = c_st_arr2_vector_1(lowb) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_vector_cnt + 1 ; -- end ; -- procedure P10 (signal s_st_arr2 : in st_arr2 ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns, -- c_st_arr2_1(highb,false) after 20 ns ; -- when 1 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613.P10" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_2(highb,false) after 10 ns , -- c_st_arr2_1(highb,false) after 20 ns , -- c_st_arr2_2(highb,false) after 30 ns , -- c_st_arr2_1(highb,false) after 40 ns ; -- when 3 => correct := s_st_arr2(highb,false) = c_st_arr2_2(highb,false) and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2(highb,false) <= transport -- c_st_arr2_1(highb,false) after 5 ns ; -- when 4 => correct := s_st_arr2(highb,false) = c_st_arr2_1(highb,false) and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00613" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00613" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_boolean_vector , st_boolean_vector_select , s_st_boolean_vector_savt , chk_st_boolean_vector , s_st_boolean_vector_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb) <= transport c_st_boolean_vector_2(lowb) after 10 ns, c_st_boolean_vector_1(lowb) after 20 ns when 1, -- c_st_boolean_vector_2(lowb) after 10 ns , c_st_boolean_vector_1(lowb) after 20 ns , c_st_boolean_vector_2(lowb) after 30 ns , c_st_boolean_vector_1(lowb) after 40 ns when 2, -- c_st_boolean_vector_1(lowb) after 5 ns when 3 ; -- CHG2 : P2( s_st_severity_level_vector , st_severity_level_vector_select , s_st_severity_level_vector_savt , chk_st_severity_level_vector , s_st_severity_level_vector_cnt ) ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb) <= transport c_st_severity_level_vector_2(lowb) after 10 ns, c_st_severity_level_vector_1(lowb) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb) after 10 ns , c_st_severity_level_vector_1(lowb) after 20 ns , c_st_severity_level_vector_2(lowb) after 30 ns , c_st_severity_level_vector_1(lowb) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb) after 5 ns when 3 ; -- CHG3 : P3( s_st_string , st_string_select , s_st_string_savt , chk_st_string , s_st_string_cnt ) ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb) <= transport c_st_string_2(highb) after 10 ns, c_st_string_1(highb) after 20 ns when 1, -- c_st_string_2(highb) after 10 ns , c_st_string_1(highb) after 20 ns , c_st_string_2(highb) after 30 ns , c_st_string_1(highb) after 40 ns when 2, -- c_st_string_1(highb) after 5 ns when 3 ; -- CHG4 : P4( s_st_enum1_vector , st_enum1_vector_select , s_st_enum1_vector_savt , chk_st_enum1_vector , s_st_enum1_vector_cnt ) ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb) <= transport c_st_enum1_vector_2(highb) after 10 ns, c_st_enum1_vector_1(highb) after 20 ns when 1, -- c_st_enum1_vector_2(highb) after 10 ns , c_st_enum1_vector_1(highb) after 20 ns , c_st_enum1_vector_2(highb) after 30 ns , c_st_enum1_vector_1(highb) after 40 ns when 2, -- c_st_enum1_vector_1(highb) after 5 ns when 3 ; -- CHG5 : P5( s_st_integer_vector , st_integer_vector_select , s_st_integer_vector_savt , chk_st_integer_vector , s_st_integer_vector_cnt ) ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb) <= transport c_st_integer_vector_2(lowb) after 10 ns, c_st_integer_vector_1(lowb) after 20 ns when 1, -- c_st_integer_vector_2(lowb) after 10 ns , c_st_integer_vector_1(lowb) after 20 ns , c_st_integer_vector_2(lowb) after 30 ns , c_st_integer_vector_1(lowb) after 40 ns when 2, -- c_st_integer_vector_1(lowb) after 5 ns when 3 ; -- CHG6 : P6( s_st_time_vector , st_time_vector_select , s_st_time_vector_savt , chk_st_time_vector , s_st_time_vector_cnt ) ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb) <= transport c_st_time_vector_2(lowb) after 10 ns, c_st_time_vector_1(lowb) after 20 ns when 1, -- c_st_time_vector_2(lowb) after 10 ns , c_st_time_vector_1(lowb) after 20 ns , c_st_time_vector_2(lowb) after 30 ns , c_st_time_vector_1(lowb) after 40 ns when 2, -- c_st_time_vector_1(lowb) after 5 ns when 3 ; -- CHG7 : P7( s_st_real_vector , st_real_vector_select , s_st_real_vector_savt , chk_st_real_vector , s_st_real_vector_cnt ) ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb) <= transport c_st_real_vector_2(highb) after 10 ns, c_st_real_vector_1(highb) after 20 ns when 1, -- c_st_real_vector_2(highb) after 10 ns , c_st_real_vector_1(highb) after 20 ns , c_st_real_vector_2(highb) after 30 ns , c_st_real_vector_1(highb) after 40 ns when 2, -- c_st_real_vector_1(highb) after 5 ns when 3 ; -- CHG8 : P8( s_st_rec1_vector , st_rec1_vector_select , s_st_rec1_vector_savt , chk_st_rec1_vector , s_st_rec1_vector_cnt ) ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb) <= transport c_st_rec1_vector_2(highb) after 10 ns, c_st_rec1_vector_1(highb) after 20 ns when 1, -- c_st_rec1_vector_2(highb) after 10 ns , c_st_rec1_vector_1(highb) after 20 ns , c_st_rec1_vector_2(highb) after 30 ns , c_st_rec1_vector_1(highb) after 40 ns when 2, -- c_st_rec1_vector_1(highb) after 5 ns when 3 ; -- CHG9 : P9( s_st_arr2_vector , st_arr2_vector_select , s_st_arr2_vector_savt , chk_st_arr2_vector , s_st_arr2_vector_cnt ) ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb) <= transport c_st_arr2_vector_2(lowb) after 10 ns, c_st_arr2_vector_1(lowb) after 20 ns when 1, -- c_st_arr2_vector_2(lowb) after 10 ns , c_st_arr2_vector_1(lowb) after 20 ns , c_st_arr2_vector_2(lowb) after 30 ns , c_st_arr2_vector_1(lowb) after 40 ns when 2, -- c_st_arr2_vector_1(lowb) after 5 ns when 3 ; -- CHG10 : P10( s_st_arr2 , st_arr2_select , s_st_arr2_savt , chk_st_arr2 , s_st_arr2_cnt ) ; -- PGEN_CHKP_10 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions completed entirely", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- -- with st_arr2_select select s_st_arr2(highb,false) <= transport c_st_arr2_2(highb,false) after 10 ns, c_st_arr2_1(highb,false) after 20 ns when 1, -- c_st_arr2_2(highb,false) after 10 ns , c_st_arr2_1(highb,false) after 20 ns , c_st_arr2_2(highb,false) after 30 ns , c_st_arr2_1(highb,false) after 40 ns when 2, -- c_st_arr2_1(highb,false) after 5 ns when 3 ; -- end ARCH00613 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00613_Test_Bench is end ENT00613_Test_Bench ; -- -- architecture ARCH00613_Test_Bench of ENT00613_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00613 ( ARCH00613 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00613_Test_Bench ;

gpl-3.0

edd1737484561ec4d3ae61df8ac24acd

0.5266

3.565252

false

true

false

jairov4/accel-oil

impl/impl_test_pcie/simulation/behavioral/system_dlmb_cntlr_wrapper.vhd

1

18,331

------------------------------------------------------------------------------- -- system_dlmb_cntlr_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_if_cntlr_v3_10_c; use lmb_bram_if_cntlr_v3_10_c.all; entity system_dlmb_cntlr_wrapper is port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to 31); LMB_WriteDBus : in std_logic_vector(0 to 31); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to 3); Sl_DBus : out std_logic_vector(0 to 31); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to 31); LMB1_WriteDBus : in std_logic_vector(0 to 31); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to 3); Sl1_DBus : out std_logic_vector(0 to 31); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to 31); LMB2_WriteDBus : in std_logic_vector(0 to 31); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to 3); Sl2_DBus : out std_logic_vector(0 to 31); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to 31); LMB3_WriteDBus : in std_logic_vector(0 to 31); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to 3); Sl3_DBus : out std_logic_vector(0 to 31); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to 3); BRAM_Addr_A : out std_logic_vector(0 to 31); BRAM_Din_A : in std_logic_vector(0 to 31); BRAM_Dout_A : out std_logic_vector(0 to 31); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end system_dlmb_cntlr_wrapper; architecture STRUCTURE of system_dlmb_cntlr_wrapper is component lmb_bram_if_cntlr is generic ( C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_FAMILY : string; C_MASK : std_logic_vector(0 to 31); C_MASK1 : std_logic_vector(0 to 31); C_MASK2 : std_logic_vector(0 to 31); C_MASK3 : std_logic_vector(0 to 31); C_LMB_AWIDTH : integer; C_LMB_DWIDTH : integer; C_ECC : integer; C_INTERCONNECT : integer; C_FAULT_INJECT : integer; C_CE_FAILING_REGISTERS : integer; C_UE_FAILING_REGISTERS : integer; C_ECC_STATUS_REGISTERS : integer; C_ECC_ONOFF_REGISTER : integer; C_ECC_ONOFF_RESET_VALUE : integer; C_CE_COUNTER_WIDTH : integer; C_WRITE_ACCESS : integer; C_NUM_LMB : integer; C_SPLB_CTRL_BASEADDR : std_logic_vector; C_SPLB_CTRL_HIGHADDR : std_logic_vector; C_SPLB_CTRL_AWIDTH : INTEGER; C_SPLB_CTRL_DWIDTH : INTEGER; C_SPLB_CTRL_P2P : INTEGER; C_SPLB_CTRL_MID_WIDTH : INTEGER; C_SPLB_CTRL_NUM_MASTERS : INTEGER; C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER; C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER; C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0); C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1); BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC); Interrupt : out std_logic; UE : out std_logic; CE : out std_logic; SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_PAValid : in std_logic; SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1)); SPLB_CTRL_PLB_RNW : in std_logic; SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1)); SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3); SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2); SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_addrAck : out std_logic; SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1); SPLB_CTRL_Sl_wait : out std_logic; SPLB_CTRL_Sl_rearbitrate : out std_logic; SPLB_CTRL_Sl_wrDAck : out std_logic; SPLB_CTRL_Sl_wrComp : out std_logic; SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1)); SPLB_CTRL_Sl_rdDAck : out std_logic; SPLB_CTRL_Sl_rdComp : out std_logic; SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31); SPLB_CTRL_PLB_SAValid : in std_logic; SPLB_CTRL_PLB_rdPrim : in std_logic; SPLB_CTRL_PLB_wrPrim : in std_logic; SPLB_CTRL_PLB_abort : in std_logic; SPLB_CTRL_PLB_busLock : in std_logic; SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_lockErr : in std_logic; SPLB_CTRL_PLB_wrBurst : in std_logic; SPLB_CTRL_PLB_rdBurst : in std_logic; SPLB_CTRL_PLB_wrPendReq : in std_logic; SPLB_CTRL_PLB_rdPendReq : in std_logic; SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1); SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15); SPLB_CTRL_Sl_wrBTerm : out std_logic; SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3); SPLB_CTRL_Sl_rdBTerm : out std_logic; SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1)); S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic ); end component; begin dlmb_cntlr : lmb_bram_if_cntlr generic map ( C_BASEADDR => X"00000000", C_HIGHADDR => X"00000fff", C_FAMILY => "virtex5", C_MASK => X"80000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_NUM_LMB => 1, C_SPLB_CTRL_BASEADDR => X"FFFFFFFF", C_SPLB_CTRL_HIGHADDR => X"00000000", C_SPLB_CTRL_AWIDTH => 32, C_SPLB_CTRL_DWIDTH => 32, C_SPLB_CTRL_P2P => 0, C_SPLB_CTRL_MID_WIDTH => 1, C_SPLB_CTRL_NUM_MASTERS => 1, C_SPLB_CTRL_SUPPORT_BURSTS => 0, C_SPLB_CTRL_NATIVE_DWIDTH => 32, C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF", C_S_AXI_CTRL_HIGHADDR => X"00000000", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => LMB1_ABus, LMB1_WriteDBus => LMB1_WriteDBus, LMB1_AddrStrobe => LMB1_AddrStrobe, LMB1_ReadStrobe => LMB1_ReadStrobe, LMB1_WriteStrobe => LMB1_WriteStrobe, LMB1_BE => LMB1_BE, Sl1_DBus => Sl1_DBus, Sl1_Ready => Sl1_Ready, Sl1_Wait => Sl1_Wait, Sl1_UE => Sl1_UE, Sl1_CE => Sl1_CE, LMB2_ABus => LMB2_ABus, LMB2_WriteDBus => LMB2_WriteDBus, LMB2_AddrStrobe => LMB2_AddrStrobe, LMB2_ReadStrobe => LMB2_ReadStrobe, LMB2_WriteStrobe => LMB2_WriteStrobe, LMB2_BE => LMB2_BE, Sl2_DBus => Sl2_DBus, Sl2_Ready => Sl2_Ready, Sl2_Wait => Sl2_Wait, Sl2_UE => Sl2_UE, Sl2_CE => Sl2_CE, LMB3_ABus => LMB3_ABus, LMB3_WriteDBus => LMB3_WriteDBus, LMB3_AddrStrobe => LMB3_AddrStrobe, LMB3_ReadStrobe => LMB3_ReadStrobe, LMB3_WriteStrobe => LMB3_WriteStrobe, LMB3_BE => LMB3_BE, Sl3_DBus => Sl3_DBus, Sl3_Ready => Sl3_Ready, Sl3_Wait => Sl3_Wait, Sl3_UE => Sl3_UE, Sl3_CE => Sl3_CE, BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, Interrupt => Interrupt, UE => UE, CE => CE, SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus, SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid, SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID, SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW, SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE, SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size, SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type, SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus, SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck, SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize, SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait, SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate, SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck, SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp, SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus, SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck, SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp, SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy, SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr, SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr, SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus, SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid, SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim, SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim, SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort, SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock, SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize, SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr, SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst, SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst, SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq, SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq, SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri, SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri, SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri, SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute, SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm, SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr, SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm, SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ, S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK, S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN, S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR, S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID, S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY, S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA, S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB, S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID, S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY, S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP, S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID, S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY, S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR, S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID, S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY, S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA, S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP, S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID, S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ); end architecture STRUCTURE;

lgpl-3.0

ec10d3d7ce49d40e892ebe82fa1fc114

0.615078

2.93296

false

grwlf/vsim

vhdl_ct/ct00490.vhd

1

8,474

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00490 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (3) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00490(ARCH00490) -- ENT00490_Test_Bench(ARCH00490_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00490 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00490 ; -- architecture ARCH00490 of ENT00490 is begin B1 : block generic ( g_arr_1 : st_arr_1 ; g_time_matrix : st_time_matrix ; g_bit_vector : st_bit_vector ; g_string : st_string ; g_rec_1 : rec_1 ) ; generic map ( ( others => (others => c_rec_1_1) ) , ( others => (others => 15ms) ) , ( others => '0' ) , ( others => 'a' ) , -- ( f2 => (others => false), others => 0) ) ; ( others => 0) ) ; -- procedure p3 is variable bool : boolean := true ; begin for i in 1 to 5 loop bool := bool and g_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and g_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and g_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and g_bit_vector = B"00000" ; -- bool := bool and g_string = "aaa" ; -- bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0 and g_rec_1.f3 = 0 ; -- bool := bool and g_rec_1.f2(1) = false -- and g_rec_1.f2(0) = false and -- g_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00490" , "Aggregates with others choice associated with formal" & " generic (generic and dynamic)" , bool ) ; -- end p3; procedure p2 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- procedure p1 ( p_arr_1 : st_arr_1 ; p_time_matrix : st_time_matrix ; p_bit_vector : st_bit_vector ; p_string : st_string ; p_rec_1 : rec_1 ) is variable bool : boolean := true ; begin for i in 1 to 5 loop bool := bool and p_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and p_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and p_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and p_bit_vector = B"00000" ; -- bool := bool and p_string = "aaa" ; -- bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0 and p_rec_1.f3 = 0 ; -- bool := bool and p_rec_1.f2(1) = false -- and p_rec_1.f2(0) = false and -- p_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00490" , "Aggregates with others choice associated with formal" & " parameter (generic and dynamic)" , bool ) ; end p1 ; begin p1 ( ( others => (others => c_rec_1_1) ) , ( others => (others => 15ms) ) , ( others => '0' ) , ( others => 'a' ) , -- ( f2 => (others => false), others => 0) ) ; ( others => 0) ) ; p3 ; end p2 ; begin process begin p2( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; wait ; end process ; end block B1 ; end ARCH00490 ; -- entity ENT00490_Test_Bench is end ENT00490_Test_Bench ; -- architecture ARCH00490_Test_Bench of ENT00490_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00490 ( ARCH00490 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00490_Test_Bench ;

gpl-3.0

73f55ae8268fee31919b89937af8be16

0.457753

3.44052

false

MilosSubotic/huffman_coding

RTL/src/sim/huffman_encoder_tb.vhd

1

3,199

------------------------------------------------------------------------------ -- @license MIT ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.global.all; use work.huffman_encoder; entity huffman_encoder_tb is end entity huffman_encoder_tb; architecture arch_huffman_encoder_tb of huffman_encoder_tb is -- Possible values: note, warning, error, failure; constant assert_severity : severity_level := error; file stdout: text open write_mode is "STD_OUTPUT"; procedure println(s: string) is variable l: line; begin write(l, s); writeline(stdout, l); end procedure println; --Inputs signal aclk : std_logic := '0'; signal axi_resetn : std_logic := '0'; signal s_axis_tdata : std_logic_vector(7 downto 0) := (others => '0'); signal s_axis_tvalid : std_logic := '0'; signal s_axis_tlast : std_logic := '0'; signal m_axis_tready : std_logic := '0'; --Outputs signal s_axis_tready : std_logic; signal m_axis_tdata : std_logic_vector(7 downto 0); signal m_axis_tvalid : std_logic; signal m_axis_tlast : std_logic; -- Clock period definitions constant aclk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity huffman_encoder port map ( aclk => aclk, axi_resetn => axi_resetn, s_axis_tdata => s_axis_tdata, s_axis_tvalid => s_axis_tvalid, s_axis_tready => s_axis_tready, s_axis_tlast => s_axis_tlast, m_axis_tdata => m_axis_tdata, m_axis_tvalid => m_axis_tvalid, m_axis_tready => m_axis_tready, m_axis_tlast => m_axis_tlast ); -- Clock process definitions clk_p: process begin aclk <= '0'; wait for aclk_period/2; aclk <= '1'; wait for aclk_period/2; end process; -- Stimulus process axi_master_p: process variable symbol_idx : natural; type t_symbol_batch is array(0 to 15) of std_logic_vector(7 downto 0); constant symbol_batch : t_symbol_batch := ( x"62", x"61", x"62", x"61", x"64", x"65", x"64", x"61", x"64", x"65", x"61", x"64", x"62", x"65", x"65", x"66" ); begin wait for aclk_period*2; axi_resetn <= '1'; wait for aclk_period; symbol_idx := 0; while symbol_idx <= 15 loop s_axis_tdata <= symbol_batch(symbol_idx); s_axis_tvalid <= '1'; if symbol_idx = 15 then s_axis_tlast <= '1'; else s_axis_tlast <= '0'; end if; -- If slave is ready then symbols is considered sent, -- and we proceed to next symbol. if s_axis_tready = '1' then symbol_idx := symbol_idx + 1; end if; wait for aclk_period; -- Make pause for 3 clock periods. if symbol_idx mod 8 = 5 then s_axis_tvalid <= '0'; wait for aclk_period*3; end if; end loop; s_axis_tvalid <= '0'; s_axis_tlast <= '0'; wait for aclk_period*10; println("--------------------------------------"); println("Testbench done!"); println("--------------------------------------"); wait; end process; end architecture arch_huffman_encoder_tb;

mit

13694de662026fced49ec49e8c44afe5

0.556736

3.08486

false

jairov4/accel-oil

solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.vhd

3

9,502

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(16 downto 0); b: in std_logic_vector(16 downto 0); s: out std_logic_vector(16 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is port ( faa : IN STD_LOGIC_VECTOR (5-1 downto 0); fab : IN STD_LOGIC_VECTOR (5-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (5-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (2-1 downto 0); fab : IN STD_LOGIC_VECTOR (2-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (2-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(16 downto 0); signal b_reg : std_logic_vector(16 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(4 downto 0); signal b0_cb : std_logic_vector(4 downto 0); signal a1_cb : std_logic_vector(9 downto 5); signal b1_cb : std_logic_vector(9 downto 5); signal a2_cb : std_logic_vector(14 downto 10); signal b2_cb : std_logic_vector(14 downto 10); signal a3_cb : std_logic_vector(16 downto 15); signal b3_cb : std_logic_vector(16 downto 15); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; -- wires for each full adder sum signal fas : std_logic_vector(16 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0); signal s0_ca_rego0 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal s1_ca_rego1 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal s2_ca_rego2 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(16 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(4 downto 0); b0_cb <= b_reg(4 downto 0); a1_cb <= a_reg(9 downto 5); b1_cb <= b_reg(9 downto 5); a2_cb <= a_reg(14 downto 10); b2_cb <= b_reg(14 downto 10); a3_cb <= a_reg(16 downto 15); b3_cb <= b_reg(16 downto 15); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(4 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(9 downto 5), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(14 downto 10), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(16 downto 15), facout => faccout3_co3); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(4 downto 0); s1_ca_rego1 (0) <= fas(9 downto 5); s2_ca_rego2 (0) <= fas(14 downto 10); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s1_ca_rego1 (1) <= s1_ca_rego1 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(4 downto 0) <= s0_ca_rego0(2); s_tmp(9 downto 5) <= s1_ca_rego1(1); s_tmp(14 downto 10) <= s2_ca_rego2(0); s_tmp(16 downto 15) <= fas(16 downto 15); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is generic(N : natural :=5); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is generic(N : natural :=2); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;

lgpl-3.0

9ee1d0cac8bbe1c27af5f88eb52b8429

0.608293

2.864637

false

MrDoomBringer/DSD-Labs

Lab 4/name_detector.vhd

1

1,073

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY name_detector IS PORT ( b6, a, b, c, d, e: IN STD_LOGIC; first_cond, last_cond, first_sel, last_sel: OUT STD_LOGIC); END name_detector; ARCHITECTURE selective_name OF name_detector IS SIGNAL inputs: STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN inputs <= b6 & a & b & c & d & e; WITH inputs SELECT first_sel <= '1' WHEN "100011" | "100110" | "101100" | "101001", '0' WHEN OTHERS; WITH inputs SELECT last_sel <= '1' WHEN "100001" | "100011" | "101101" | "101110" | "101000" | "110000", '0' WHEN OTHERS; first_cond <= '1' WHEN inputs = "100011" ELSE '1' WHEN inputs = "100110" ELSE '1' WHEN inputs = "101100" ELSE '1' WHEN inputs = "101001" ELSE '0'; last_cond <= '1' WHEN inputs = "100001" ELSE '1' WHEN inputs = "100011" ELSE '1' WHEN inputs = "101101" ELSE '1' WHEN inputs = "101110" ELSE '1' WHEN inputs = "101000" ELSE '1' WHEN inputs = "110000" ELSE '0'; END selective_name;

mit

200c4b07b220ce34cb1c27771e6cf0c2

0.586207

2.853723

false

wsoltys/AtomFpga

src/AVR8/Memory/XDM32Kx8.vhd

1

2,088

--************************************************************************************************ -- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx) -- Version 0.1 -- Designed by Ruslan Lepetenok -- Modified 29.10.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- For Synplicity Synplify --library virtexe; --use virtexe.components.all; -- Aldec library unisim; use unisim.vcomponents.all; entity XDM32Kx8 is port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(14 downto 0); din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); we : in std_logic ); end XDM32Kx8; architecture RTL of XDM32Kx8 is type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0); signal cp2n : std_logic; signal gnd : std_logic; begin gnd <= '0'; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0'; end generate ; RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate RAM_Byte:component RAMB4_S8 port map( DO => RAMBlDOut(i)(7 downto 0), ADDR => address(8 downto 0), DI => din(7 downto 0), EN => ce, CLK => cp2, WE => WEB(i), RST => gnd ); end generate; -- Output data mux dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9))); end RTL;

apache-2.0

2901724ab805feab15c1fe5dc21b37cd

0.440134

3.939623

false

jairov4/accel-oil

impl/impl_test_pcie/simulation/behavioral/system_lmb_bram_wrapper.vhd

1

2,663

------------------------------------------------------------------------------- -- system_lmb_bram_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library lmb_bram_elaborate_v1_00_a; use lmb_bram_elaborate_v1_00_a.all; entity system_lmb_bram_wrapper is port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to 3); BRAM_Addr_A : in std_logic_vector(0 to 31); BRAM_Din_A : out std_logic_vector(0 to 31); BRAM_Dout_A : in std_logic_vector(0 to 31); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to 3); BRAM_Addr_B : in std_logic_vector(0 to 31); BRAM_Din_B : out std_logic_vector(0 to 31); BRAM_Dout_B : in std_logic_vector(0 to 31) ); end system_lmb_bram_wrapper; architecture STRUCTURE of system_lmb_bram_wrapper is component lmb_bram_elaborate is generic ( C_MEMSIZE : integer; C_PORT_DWIDTH : integer; C_PORT_AWIDTH : integer; C_NUM_WE : integer; C_FAMILY : string ); port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1) ); end component; begin lmb_bram : lmb_bram_elaborate generic map ( C_MEMSIZE => 16#1000#, C_PORT_DWIDTH => 32, C_PORT_AWIDTH => 32, C_NUM_WE => 4, C_FAMILY => "virtex5" ) port map ( BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_Din_A => BRAM_Din_A, BRAM_Dout_A => BRAM_Dout_A, BRAM_Rst_B => BRAM_Rst_B, BRAM_Clk_B => BRAM_Clk_B, BRAM_EN_B => BRAM_EN_B, BRAM_WEN_B => BRAM_WEN_B, BRAM_Addr_B => BRAM_Addr_B, BRAM_Din_B => BRAM_Din_B, BRAM_Dout_B => BRAM_Dout_B ); end architecture STRUCTURE;

lgpl-3.0

f6387af42a506d758fb28df75d920b7c

0.558768

2.910383

false

grwlf/vsim

vhdl_ct/ct00496.vhd

1

10,355

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00496 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (6) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00496(ARCH00496) -- ENT00496_Test_Bench(ARCH00496_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00496 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - g_r1 to g_r1 ; -- f2 : rec_arr (-g_r1 to g_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-g_r1 to g_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range g_a11 to g_a12 ; subtype arange2 is integer range g_a21 to g_a22 ; subtype brange1 is integer range g_b11 to g_b12 ; subtype brange2 is integer range g_b21 to g_b22 ; subtype crange is integer range g_c1 to g_c2 ; subtype drange is integer range g_d1 to g_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00496 ; -- architecture ARCH00496 of ENT00496 is begin B1 : block signal s_arr_1 : st_arr_1 ; signal s_time_matrix : st_time_matrix ; signal s_bit_vector : st_bit_vector ; signal s_string : st_string ; signal s_rec_1 : rec_1 ; signal toggle : boolean := false ; procedure p1 ( constant d_a11 : boolean := false ; constant d_a12 : boolean := true ; constant d_a21 : integer := 1 ; constant d_a22 : integer := 5 ; constant d_b11 : integer := 0 ; constant d_b12 : integer := 0 ; constant d_b21 : integer := -5 ; constant d_b22 : integer := -3 ; constant d_c1 : integer := 0 ; constant d_c2 : integer := 4 ; constant d_d1 : integer := 3 ; constant d_d2 : integer := 5 ; constant d_r1 : integer := 1 ) is -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - d_r1 to d_r1 ; -- f2 : rec_arr (-d_r1 to d_r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-d_r1 to d_r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range d_a11 to d_a12 ; subtype arange2 is integer range d_a21 to d_a22 ; subtype brange1 is integer range d_b11 to d_b12 ; subtype brange2 is integer range d_b21 to d_b22 ; subtype crange is integer range d_c1 to d_c2 ; subtype drange is integer range d_d1 to d_d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- variable v_arr_1 : st_arr_1 ; variable v_time_matrix : st_time_matrix ; variable v_bit_vector : st_bit_vector ; variable v_string : st_string ; variable v_rec_1 : rec_1 ; variable bool : boolean := true ; -- begin v_arr_1 := ( others => (others => c_rec_1_1) ) ; v_time_matrix := ( others => (others => 15ms) ) ; v_bit_vector := ( others => '0' ) ; v_string := ( others => 'a' ) ; v_rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in signal assignment" & " (dynamic)" , bool ) ; end p1 ; -- begin process variable v_arr_1 : st_arr_1 ; variable v_time_matrix : st_time_matrix ; variable v_bit_vector : st_bit_vector ; variable v_string : st_string ; variable v_rec_1 : rec_1 ; variable bool : boolean := true ; -- begin s_arr_1 <= ( others => (others => c_rec_1_1) ) ; for i in 2 to 5 loop s_arr_1 (false, i) <= c_rec_1_2; end loop; s_time_matrix <= ( others => (others => 5 fs) ) ; s_time_matrix (0, -3) <= 10 ns; s_bit_vector <= ( others => '0' ) ; s_bit_vector (g_c1) <= '1'; s_bit_vector (g_c1+2) <= '1'; s_string <= "ab0" ; s_rec_1 <= -- ( f2 => (others => false), others => 0) ; ( others => 0) ; s_rec_1.f3 <= 1; toggle <= true ; v_arr_1 := ( others => (others => c_rec_1_1) ) ; v_time_matrix := ( others => (others => 15ms) ) ; v_bit_vector := ( others => '0' ) ; v_string := ( others => 'a' ) ; v_rec_1 := -- ( f2 => (others => false), others => 0) ; ( others => 0) ; for i in 1 to 5 loop bool := bool and v_arr_1(false, i) = c_rec_1_1 ; end loop ; for i in 1 to 5 loop bool := bool and v_arr_1(true, i) = c_rec_1_1 ; end loop ; -- for i in integer'(-5) to -3 loop bool := bool and v_time_matrix(0, i) = 15 ms ; end loop ; -- bool := bool and v_bit_vector = B"00000" ; -- bool := bool and v_string = "aaa" ; -- bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0 and v_rec_1.f3 = 0 ; -- bool := bool and v_rec_1.f2(1) = false -- and v_rec_1.f2(0) = false and -- v_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in signal assignment" & " (globally static)" , bool ) ; wait ; end process ; process ( toggle ) variable bool : boolean := true ; begin if toggle then bool := bool and s_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and s_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and s_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and s_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and s_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and s_bit_vector = B"10100" ; -- bool := bool and s_string = "ab0" ; -- bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0 and s_rec_1.f3 = 1 ; -- bool := bool and s_rec_1.f2(1) = true -- and s_rec_1.f2(0) = false and -- s_rec_1.f2(-1) = false ; -- -- test_report ( "ARCH00496" , "Aggregates with others choice in variable assignment" & " (globally static)" , bool ) ; end if ; p1 ( open, open, open, open, open, open, open, open, open, open, open, open, open ) ; end process ; end block B1 ; end ARCH00496 ; -- entity ENT00496_Test_Bench is end ENT00496_Test_Bench ; -- architecture ARCH00496_Test_Bench of ENT00496_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00496 ( ARCH00496 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00496_Test_Bench ;

gpl-3.0

66143fca6efd33ce54e0375adc69f93f

0.461709

3.345719

false

grwlf/vsim

vhdl_ct/ct00286.vhd

1

2,562

-- NEED RESULT: ARCH00286: Integer types and predefined integer types passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00286 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 3.1.2 (1) -- 3.1.2 (2) -- 3.1.2 (3) -- 3.1.2.1 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00286) -- ENT00286_Test_Bench(ARCH00286_Test_Bench) -- -- REVISION HISTORY: -- -- 22-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00286 of E00000 is -- these will test 3.1.2 (2) type negative_integers is range -2147483647 to 0 ; type positive_integers is range 0 to +2147483647 ; type all_integers is range -2147483647 to +2147483647 ; -- this tests 3.1.2 (3) type backward_integers is range +2147483647 downto -2147483647 ; -- these will test 3.1.2 (1) type signed_byte is range -128 to +127 ; type signed_nibble is range -8 to +7 ; type signed_something is range signed_nibble'left to signed_byte'right ; begin P : process begin test_report ( "ARCH00286" , "Integer types and predefined integer types" , (negative_integers'left = -2147483647) and (negative_integers'right = 0) and (positive_integers'left = 0) and (positive_integers'right = +2147483647) and (all_integers'left = -2147483647) and (all_integers'right = +2147483647) and (backward_integers'left = +2147483647) and (backward_integers'right = -2147483647) and (signed_byte'left = -128) and (signed_byte'right = +127) and (signed_nibble'left = -8) and (signed_nibble'right = +7) and (signed_something'left = -8) and (signed_something'right = +127) and (integer'left <= -2147483647) and -- test 3.1.2.1 (1) (integer'right >= +2147483647) ) ; wait ; end process P ; end ARCH00286 ; entity ENT00286_Test_Bench is end ENT00286_Test_Bench ; architecture ARCH00286_Test_Bench of ENT00286_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00286 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00286_Test_Bench ;

gpl-3.0

bcd75882b1905557d658b5dc20a72e05

0.556206

3.45749

false

true

false

MrDoomBringer/DSD-Labs

Lab 9/vendi.vhd

1

4,597

-- FPGA Clock Circuit for Altera DE-2 board -- Cliff Chapman -- 11/04/2013 -- -- Lab 9 - Digital Systems Design LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY vendi IS PORT ( -- Coins input nickel_in : IN STD_LOGIC; dime_in : IN STD_LOGIC; quarter_in : IN STD_LOGIC; -- User actions dispense : IN STD_LOGIC; coin_return : IN STD_LOGIC; -- Machine data clk : IN STD_LOGIC; rst : IN STD_LOGIC := '1'; -- LED dispense status change_back : OUT STD_LOGIC; red_bull : OUT STD_LOGIC; -- Coin amount displays HEX0_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); HEX1_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END vendi; ARCHITECTURE a OF vendi IS COMPONENT sevenseg_bcd_display PORT ( r : IN STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; SIGNAL coin_val : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Build an enumerated type for the state machine -- This feels like a GREAT way to screw yourself over with -- overloading common names. Maybe that's just me. -- Either way that's why we have the _s hungarian postfix on these. TYPE state_type IS ( idle_s, nickle_s, dime_s, quarter_s , enough_s, excess_s, vend_s, change_s ); -- Register to hold the current state SIGNAL state : state_type; BEGIN -- Display output of current coin value display : sevenseg_bcd_display PORT MAP ( r => coin_val, s => '1', HEX2 => OPEN, HEX1 => HEX1_disp, HEX0 => HEX0_disp ); state_monitor : PROCESS (rst, clk) BEGIN IF (rst = '0') THEN state <= idle_s; ELSIF (rising_edge(clk)) THEN CASE state IS -- IDLE STATE WHEN idle_s => IF (nickel_in = '1') THEN state <= nickle_s; ELSIF (dime_in = '1') THEN state <= dime_s; ELSIF (quarter_in = '1') THEN state <= quarter_s; ELSIF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; -- Coins states WHEN nickle_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; WHEN dime_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; WHEN quarter_s => IF (coin_val >= "01001011") THEN state <= enough_s; ELSE state <= idle_s; END IF; -- Enough money WHEN enough_s => IF (coin_return = '1') THEN state <= change_s; ELSIF (dispense = '1') THEN state <= vend_s; ELSIF (nickel_in = '1') THEN state <= excess_s; ELSIF (dime_in = '1') THEN state <= excess_s; ELSIF (quarter_in = '1') THEN state <= excess_s; ELSE state <= enough_s; END IF; -- Too much money (Display may overload, can store up to 255 cents) -- TODO: add auto-return dump for values over 2 dollars? WHEN excess_s => IF (coin_return = '1') THEN state <= change_s; ELSIF (dispense = '1') THEN state <= vend_s; -- Coin block again ELSIF (nickel_in = '1') THEN state <= excess_s; ELSIF (dime_in = '1') THEN state <= excess_s; ELSIF (quarter_in = '1') THEN state <= excess_s; ELSE state <= excess_s; END IF; WHEN vend_s => IF (coin_val = "00000000") THEN state <= idle_s; ELSIF (coin_val > "00000000") THEN state <= change_s; END IF; WHEN OTHERS => state <= idle_s; END CASE; END IF; END PROCESS state_monitor; PROCESS (state) BEGIN IF (state = vend_s) THEN red_bull <= '1'; ELSE red_bull <= '0'; END IF; IF (state = change_s) THEN change_back <= '1'; ELSIF (state = excess_s) THEN change_back <= '1'; ELSE change_back <= '0'; END IF; END PROCESS; state_output : PROCESS (state, clk, rst) VARIABLE coin_cnt : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000"; BEGIN IF (rst = '0') THEN coin_cnt := "00000000"; ELSIF (rising_edge(clk) AND rst = '1') THEN CASE state IS WHEN nickle_s => coin_cnt := coin_cnt + "00000101"; WHEN dime_s => coin_cnt := coin_cnt + "00001010"; WHEN quarter_s => coin_cnt := coin_cnt + "00011001"; WHEN vend_s => coin_cnt := coin_cnt - "01001011"; WHEN change_s => coin_cnt := "00000000"; WHEN OTHERS => coin_cnt := coin_cnt; END CASE; ELSE coin_cnt := coin_cnt; END IF; coin_val <= coin_cnt; END PROCESS state_output; END ARCHITECTURE;

mit

f706701c5f0a649294f83c32ea40e09c

0.583206

2.864174

false

grwlf/vsim

vhdl_ct/ct00160.vhd

1

25,015

-- NEED RESULT: ARCH00160.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00160: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Inertial transactions entirely completed passed -- NEED RESULT: P2: Inertial transactions entirely completed passed -- NEED RESULT: P1: Inertial transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00160 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- ENT00160(ARCH00160) -- ENT00160_Test_Bench(ARCH00160_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00160 is port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- -- procedure Proc1 ( signal s_st_arr1_vector : inout st_arr1_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P1" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_1(highb) ( st_arr1'Right) after 100 ns; -- when 5 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 6 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns; -- when 7 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_st_arr2_vector : inout st_arr2_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr2_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P2" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_st_arr3_vector : inout st_arr3_vector ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr3_vector : out chk_sig_type ) is begin case counter is when 0 => s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160.P3" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00160" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- -- end ENT00160 ; -- architecture ARCH00160 of ENT00160 is begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_st_arr1_vector, counter, correct, savtime, chk_st_arr1_vector ) ; wait until (not s_st_arr1_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_st_arr1_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_st_arr2_vector, counter, correct, savtime, chk_st_arr2_vector ) ; wait until (not s_st_arr2_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_st_arr3_vector, counter, correct, savtime, chk_st_arr3_vector ) ; wait until (not s_st_arr3_vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- -- end ARCH00160 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00160_Test_Bench is signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00160_Test_Bench ; -- architecture ARCH00160_Test_Bench of ENT00160_Test_Bench is begin L1: block component UUT port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00160 ( ARCH00160 ) ; begin CIS1 : UUT port map ( s_st_arr1_vector , s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00160_Test_Bench ;

gpl-3.0

04f35e81b40a69b948179a8ba3a41eff

0.491585

3.565422

false

grwlf/vsim

vhdl_ct/ct00616.vhd

1

48,823

-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616: Concurrent proc call 1 passed -- NEED RESULT: ARCH00616.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: Concurrent proc call 2 passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00616: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00616: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00616 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00616(ARCH00616) -- ENT00616_Test_Bench(ARCH00616_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00616 is port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_boolean_vector : chk_sig_type := -1 ; signal chk_st_severity_level_vector : chk_sig_type := -1 ; signal chk_st_string : chk_sig_type := -1 ; signal chk_st_enum1_vector : chk_sig_type := -1 ; signal chk_st_integer_vector : chk_sig_type := -1 ; signal chk_st_time_vector : chk_sig_type := -1 ; signal chk_st_real_vector : chk_sig_type := -1 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; -- end ENT00616 ; -- -- architecture ARCH00616 of ENT00616 is subtype chk_time_type is Time ; signal s_st_boolean_vector_savt : chk_time_type := 0 ns ; signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ; signal s_st_string_savt : chk_time_type := 0 ns ; signal s_st_enum1_vector_savt : chk_time_type := 0 ns ; signal s_st_integer_vector_savt : chk_time_type := 0 ns ; signal s_st_time_vector_savt : chk_time_type := 0 ns ; signal s_st_real_vector_savt : chk_time_type := 0 ns ; signal s_st_rec1_vector_savt : chk_time_type := 0 ns ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ; signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ; signal s_st_string_cnt : chk_cnt_type := 0 ; signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ; signal s_st_integer_vector_cnt : chk_cnt_type := 0 ; signal s_st_time_vector_cnt : chk_cnt_type := 0 ; signal s_st_real_vector_cnt : chk_cnt_type := 0 ; signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_boolean_vector_select : select_type := 1 ; signal st_severity_level_vector_select : select_type := 1 ; signal st_string_select : select_type := 1 ; signal st_enum1_vector_select : select_type := 1 ; signal st_integer_vector_select : select_type := 1 ; signal st_time_vector_select : select_type := 1 ; signal st_real_vector_select : select_type := 1 ; signal st_rec1_vector_select : select_type := 1 ; signal st_arr2_vector_select : select_type := 1 ; -- procedure P1 (signal s_st_boolean_vector : in st_boolean_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_boolean_vector_cnt is when 0 => null ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns, -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 20 ns , -- c_st_boolean_vector_2(lowb to highb-1) after 30 ns , -- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_2(lowb to highb-1) and (s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_boolean_vector(lowb to highb-1) <= transport -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_boolean_vector(lowb to highb-1) = c_st_boolean_vector_1(lowb to highb-1) and (s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_boolean_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_boolean_vector_cnt + 1 ; -- end ; -- procedure P2 (signal s_st_severity_level_vector : in st_severity_level_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_severity_level_vector_cnt is when 0 => null ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , -- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , -- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_2(lowb to highb-1) and (s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_severity_level_vector(lowb to highb-1) <= transport -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_severity_level_vector(lowb to highb-1) = c_st_severity_level_vector_1(lowb to highb-1) and (s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_severity_level_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_severity_level_vector_cnt + 1 ; -- end ; -- procedure P3 (signal s_st_string : in st_string ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_string_cnt is when 0 => null ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns, -- c_st_string_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_2(highb-1 to highb-1) after 10 ns , -- c_st_string_1(highb-1 to highb-1) after 20 ns , -- c_st_string_2(highb-1 to highb-1) after 30 ns , -- c_st_string_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_string(highb-1 to highb-1) = c_st_string_2(highb-1 to highb-1) and (s_st_string_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_string(highb-1 to highb-1) <= transport -- c_st_string_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_string(highb-1 to highb-1) = c_st_string_1(highb-1 to highb-1) and (s_st_string_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_string_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_string_cnt + 1 ; -- end ; -- procedure P4 (signal s_st_enum1_vector : in st_enum1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_enum1_vector_cnt is when 0 => null ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_2(highb-1 to highb-1) and (s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_enum1_vector(highb-1 to highb-1) <= transport -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_enum1_vector(highb-1 to highb-1) = c_st_enum1_vector_1(highb-1 to highb-1) and (s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_enum1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_enum1_vector_cnt + 1 ; -- end ; -- procedure P5 (signal s_st_integer_vector : in st_integer_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_integer_vector_cnt is when 0 => null ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns, -- c_st_integer_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , -- c_st_integer_vector_1(lowb to highb-1) after 20 ns , -- c_st_integer_vector_2(lowb to highb-1) after 30 ns , -- c_st_integer_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_2(lowb to highb-1) and (s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_integer_vector(lowb to highb-1) <= transport -- c_st_integer_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_integer_vector(lowb to highb-1) = c_st_integer_vector_1(lowb to highb-1) and (s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_integer_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_integer_vector_cnt + 1 ; -- end ; -- procedure P6 (signal s_st_time_vector : in st_time_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_time_vector_cnt is when 0 => null ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns, -- c_st_time_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_2(lowb to highb-1) after 10 ns , -- c_st_time_vector_1(lowb to highb-1) after 20 ns , -- c_st_time_vector_2(lowb to highb-1) after 30 ns , -- c_st_time_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_2(lowb to highb-1) and (s_st_time_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_time_vector(lowb to highb-1) <= transport -- c_st_time_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_time_vector(lowb to highb-1) = c_st_time_vector_1(lowb to highb-1) and (s_st_time_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_time_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_time_vector_cnt + 1 ; -- end ; -- procedure P7 (signal s_st_real_vector : in st_real_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_real_vector_cnt is when 0 => null ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_real_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_2(highb-1 to highb-1) and (s_st_real_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_real_vector(highb-1 to highb-1) <= transport -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_real_vector(highb-1 to highb-1) = c_st_real_vector_1(highb-1 to highb-1) and (s_st_real_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_real_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_real_vector_cnt + 1 ; -- end ; -- procedure P8 (signal s_st_rec1_vector : in st_rec1_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_rec1_vector_cnt is when 0 => null ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , -- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , -- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_2(highb-1 to highb-1) and (s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_rec1_vector(highb-1 to highb-1) <= transport -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ; -- when 4 => correct := s_st_rec1_vector(highb-1 to highb-1) = c_st_rec1_vector_1(highb-1 to highb-1) and (s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_rec1_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_rec1_vector_cnt + 1 ; -- end ; -- procedure P9 (signal s_st_arr2_vector : in st_arr2_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns, -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 20 ns , -- c_st_arr2_vector_2(lowb to highb-1) after 30 ns , -- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_2(lowb to highb-1) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2_vector(lowb to highb-1) <= transport -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ; -- when 4 => correct := s_st_arr2_vector(lowb to highb-1) = c_st_arr2_vector_1(lowb to highb-1) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00616" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00616" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_vector_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_boolean_vector , st_boolean_vector_select , s_st_boolean_vector_savt , chk_st_boolean_vector , s_st_boolean_vector_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_boolean_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_boolean_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_boolean_vector_select select s_st_boolean_vector(lowb to highb-1) <= transport c_st_boolean_vector_2(lowb to highb-1) after 10 ns, c_st_boolean_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_boolean_vector_2(lowb to highb-1) after 10 ns , c_st_boolean_vector_1(lowb to highb-1) after 20 ns , c_st_boolean_vector_2(lowb to highb-1) after 30 ns , c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG2 : P2( s_st_severity_level_vector , st_severity_level_vector_select , s_st_severity_level_vector_savt , chk_st_severity_level_vector , s_st_severity_level_vector_cnt ) ; -- PGEN_CHKP_2 : process ( chk_st_severity_level_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_severity_level_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_severity_level_vector_select select s_st_severity_level_vector(lowb to highb-1) <= transport c_st_severity_level_vector_2(lowb to highb-1) after 10 ns, c_st_severity_level_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns , c_st_severity_level_vector_1(lowb to highb-1) after 20 ns , c_st_severity_level_vector_2(lowb to highb-1) after 30 ns , c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG3 : P3( s_st_string , st_string_select , s_st_string_savt , chk_st_string , s_st_string_cnt ) ; -- PGEN_CHKP_3 : process ( chk_st_string ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_st_string = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- with st_string_select select s_st_string(highb-1 to highb-1) <= transport c_st_string_2(highb-1 to highb-1) after 10 ns, c_st_string_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_string_2(highb-1 to highb-1) after 10 ns , c_st_string_1(highb-1 to highb-1) after 20 ns , c_st_string_2(highb-1 to highb-1) after 30 ns , c_st_string_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG4 : P4( s_st_enum1_vector , st_enum1_vector_select , s_st_enum1_vector_savt , chk_st_enum1_vector , s_st_enum1_vector_cnt ) ; -- PGEN_CHKP_4 : process ( chk_st_enum1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_st_enum1_vector = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- with st_enum1_vector_select select s_st_enum1_vector(highb-1 to highb-1) <= transport c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns, c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns , c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns , c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG5 : P5( s_st_integer_vector , st_integer_vector_select , s_st_integer_vector_savt , chk_st_integer_vector , s_st_integer_vector_cnt ) ; -- PGEN_CHKP_5 : process ( chk_st_integer_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_integer_vector = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- with st_integer_vector_select select s_st_integer_vector(lowb to highb-1) <= transport c_st_integer_vector_2(lowb to highb-1) after 10 ns, c_st_integer_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_integer_vector_2(lowb to highb-1) after 10 ns , c_st_integer_vector_1(lowb to highb-1) after 20 ns , c_st_integer_vector_2(lowb to highb-1) after 30 ns , c_st_integer_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG6 : P6( s_st_time_vector , st_time_vector_select , s_st_time_vector_savt , chk_st_time_vector , s_st_time_vector_cnt ) ; -- PGEN_CHKP_6 : process ( chk_st_time_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_st_time_vector = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- with st_time_vector_select select s_st_time_vector(lowb to highb-1) <= transport c_st_time_vector_2(lowb to highb-1) after 10 ns, c_st_time_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_time_vector_2(lowb to highb-1) after 10 ns , c_st_time_vector_1(lowb to highb-1) after 20 ns , c_st_time_vector_2(lowb to highb-1) after 30 ns , c_st_time_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ; -- CHG7 : P7( s_st_real_vector , st_real_vector_select , s_st_real_vector_savt , chk_st_real_vector , s_st_real_vector_cnt ) ; -- PGEN_CHKP_7 : process ( chk_st_real_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_real_vector = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- with st_real_vector_select select s_st_real_vector(highb-1 to highb-1) <= transport c_st_real_vector_2(highb-1 to highb-1) after 10 ns, c_st_real_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_real_vector_2(highb-1 to highb-1) after 10 ns , c_st_real_vector_1(highb-1 to highb-1) after 20 ns , c_st_real_vector_2(highb-1 to highb-1) after 30 ns , c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG8 : P8( s_st_rec1_vector , st_rec1_vector_select , s_st_rec1_vector_savt , chk_st_rec1_vector , s_st_rec1_vector_cnt ) ; -- PGEN_CHKP_8 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- with st_rec1_vector_select select s_st_rec1_vector(highb-1 to highb-1) <= transport c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns, c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns when 1, -- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns , c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns , c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 2, -- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ; -- CHG9 : P9( s_st_arr2_vector , st_arr2_vector_select , s_st_arr2_vector_savt , chk_st_arr2_vector , s_st_arr2_vector_cnt ) ; -- PGEN_CHKP_9 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb to highb-1) <= transport c_st_arr2_vector_2(lowb to highb-1) after 10 ns, c_st_arr2_vector_1(lowb to highb-1) after 20 ns when 1, -- c_st_arr2_vector_2(lowb to highb-1) after 10 ns , c_st_arr2_vector_1(lowb to highb-1) after 20 ns , c_st_arr2_vector_2(lowb to highb-1) after 30 ns , c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 2, -- c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ; -- end ARCH00616 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00616_Test_Bench is signal s_st_boolean_vector : st_boolean_vector := c_st_boolean_vector_1 ; signal s_st_severity_level_vector : st_severity_level_vector := c_st_severity_level_vector_1 ; signal s_st_string : st_string := c_st_string_1 ; signal s_st_enum1_vector : st_enum1_vector := c_st_enum1_vector_1 ; signal s_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; signal s_st_time_vector : st_time_vector := c_st_time_vector_1 ; signal s_st_real_vector : st_real_vector := c_st_real_vector_1 ; signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; -- end ENT00616_Test_Bench ; -- -- architecture ARCH00616_Test_Bench of ENT00616_Test_Bench is begin L1: block component UUT port ( s_st_boolean_vector : inout st_boolean_vector ; s_st_severity_level_vector : inout st_severity_level_vector ; s_st_string : inout st_string ; s_st_enum1_vector : inout st_enum1_vector ; s_st_integer_vector : inout st_integer_vector ; s_st_time_vector : inout st_time_vector ; s_st_real_vector : inout st_real_vector ; s_st_rec1_vector : inout st_rec1_vector ; s_st_arr2_vector : inout st_arr2_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00616 ( ARCH00616 ) ; begin CIS1 : UUT port map ( s_st_boolean_vector , s_st_severity_level_vector , s_st_string , s_st_enum1_vector , s_st_integer_vector , s_st_time_vector , s_st_real_vector , s_st_rec1_vector , s_st_arr2_vector ) ; end block L1 ; end ARCH00616_Test_Bench ;

gpl-3.0

6992b2d913b5fbed0c0ca0c14e908f9e

0.538701

3.452585

false

true

false

takeshineshiro/fpga_fibre_scan

HUCB2P0_150701/driver/pll_conf.vhd

1

13,329

--***************************************************************************** -- @Copyright All rights reserved. -- Module name : adc_conf -- Call by : -- Description : Configuration for AD9518-3, read datasheet for reference -- IC : -- Version : A -- Note: : -- -- Author : Weibao Qiu -- Date : 2010.08 -- Update : -- --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity pll_conf is port ( I_clk : in std_logic; I_reset_n : in std_logic; O_ADC_ready : out std_logic; O_FPGA_ADC_d : out std_logic; O_FPGA_ADC_clk : out std_logic; O_FPGA_ADC_en : out std_logic; O_FPGA_ADC_reset : out std_logic ); end pll_conf; architecture rtl of pll_conf is component pll_intf is port ( I_clk : in std_logic; I_reset_n : in std_logic; I_ADC_data : in std_logic_vector(23 downto 0); O_ADC_ready : out std_logic; I_ADC_trig : in std_logic; O_FPGA_ADC_d : out std_logic; O_FPGA_ADC_clk : out std_logic; O_FPGA_ADC_en : out std_logic; O_FPGA_ADC_reset : out std_logic ); end component pll_intf; signal S_ADC_trig : std_logic; signal S_adc_cnt : std_logic_vector(4 downto 0); signal S_ADC_data : std_logic_vector(23 downto 0); signal S_ADC_ready : std_logic; signal S_ADC_ready_1buf : std_logic; signal S_ADC_ready_2buf : std_logic; signal S_ADC_ready_3buf : std_logic; signal S_ADC_ready_4buf : std_logic; signal S_data_start : std_logic; signal S_data_finish : std_logic; signal s_delay_cn : std_logic_vector(31 downto 0); signal s_delay_symbol : std_logic; constant C_DATA_NUMBER : std_logic_vector := "10111"; --The total number of data to be setted, plus 1 is the actual amount because of 0 start constant C_N0 : std_logic_vector := "00000"; constant C_N1 : std_logic_vector := "00001"; constant C_N2 : std_logic_vector := "00010"; constant C_N3 : std_logic_vector := "00011"; constant C_N4 : std_logic_vector := "00100"; constant C_N5 : std_logic_vector := "00101"; constant C_N6 : std_logic_vector := "00110"; constant C_N7 : std_logic_vector := "00111"; constant C_N8 : std_logic_vector := "01000"; constant C_N9 : std_logic_vector := "01001"; constant C_N10 : std_logic_vector := "01010"; constant C_N11 : std_logic_vector := "01011"; constant C_N12 : std_logic_vector := "01100"; constant C_N13 : std_logic_vector := "01101"; constant C_N14 : std_logic_vector := "01110"; constant C_N15 : std_logic_vector := "01111"; constant C_N16 : std_logic_vector := "10000"; constant C_N17 : std_logic_vector := "10001"; constant C_N18 : std_logic_vector := "10010"; constant C_N19 : std_logic_vector := "10011"; constant C_N20 : std_logic_vector := "10100"; constant C_N21 : std_logic_vector := "10101"; constant C_N22 : std_logic_vector := "10110"; constant C_N23 : std_logic_vector := "10111"; constant C_N24 : std_logic_vector := "11000"; begin O_ADC_ready <= S_ADC_ready; U0 : pll_intf port map ( I_clk => I_clk , I_reset_n => I_reset_n , I_ADC_data => S_ADC_data , O_ADC_ready => S_ADC_ready , I_ADC_trig => S_ADC_trig , O_FPGA_ADC_d => O_FPGA_ADC_d , O_FPGA_ADC_clk => O_FPGA_ADC_clk , O_FPGA_ADC_en => O_FPGA_ADC_en , O_FPGA_ADC_reset => O_FPGA_ADC_reset ); ------------------- --prepare the sending data ------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_ADC_data <= (others => '0'); S_ADC_trig <= '0'; elsif(I_clk'event and I_clk = '1')then if(S_data_start = '1') and (S_data_finish = '0') then S_ADC_trig <= '1'; case S_adc_cnt is when C_N0 => S_ADC_data <= "0000" & x"000" & "10111101"; --reg 0x000 Serial port configuration --Soft reset, delay when C_N1 => S_ADC_data <= "0000" & x"000" & "10011001"; when C_N2 => S_ADC_data <= "0000" & x"010" & "01111100"; --PLL normal when C_N3 => S_ADC_data <= "0000" & x"018" & "00000111"; --reg 0x018, calibration set when C_N4 => S_ADC_data <= "0000" & x"011" & "00000001"; --reg 0x011 14-bit R divider, Bits[7:0] (LSB) when C_N5 => S_ADC_data <= "0000" & x"014" & "00011110"; --reg 0x014 B counter Bits[7:0] (LSB) --S_ADC_data <= "0000" & x"014" & "00101101"; when C_N6 => S_ADC_data <= "0000" & x"016" & "00000100"; --reg 0x016 PLL Control 1, DM mode, divide by 8 --S_ADC_data <= "0000" & x"016" & "00000011"; when C_N7 => S_ADC_data <= "0000" & x"017" & "10011100"; --set STATUS to monitor the REF1 state, good output high, HL2 light when C_N8 => S_ADC_data <= "0000" & x"01C" & "00000010"; --ref1 power on when C_N9 => -- S_ADC_data <= "0000" & x"0F0" & "00000011"; --reg 0x0F1 output 0, off S_ADC_data <= "0000" & x"0F0" & "00001100"; --reg 0x0F1 output 0, on when C_N10 => S_ADC_data <= "0000" & x"0F1" & "00000011"; --reg 0x0F1 output 1, off when C_N11 => -- S_ADC_data <= "0000" & x"0F2" & "00000011"; --reg 0x0F2 output 2, off S_ADC_data <= "0000" & x"0F2" & "00001100"; --reg 0x0F2 output 2, on when C_N12 => S_ADC_data <= "0000" & x"0F3" & "00000011"; --reg 0x0F3 output 3, off when C_N13 => S_ADC_data <= "0000" & x"0F4" & "00001100"; --reg 0x0F4 output 4, on when C_N14 => S_ADC_data <= "0000" & x"0F5" & "00000011"; --reg 0x0F5 output 5, off when C_N15 => S_ADC_data <= "0000" & x"191" & "00000000"; --reg 0x191 OUTPUT0 use divider, 0+0+2 --S_ADC_data <= "0000" & x"191" & "10000000"; -- Bypass divider --for 600MHz output when C_N16 => S_ADC_data <= "0000" & x"193" & "00000000"; --reg 0x193 OUTPUT1 divide by 2, 0+0+2 --S_ADC_data <= "0000" & x"194" & "10000000"; --194 bypass divider, when C_N17 => S_ADC_data <= "0000" & x"1E0" & "00000011"; --reg 0x1E0, divide by 5 --S_ADC_data <= "0000" & x"1E0" & "00000001"; when C_N18 => S_ADC_data <= "0000" & x"1E1" & "00000010"; --Internal PLL --S_ADC_data <= "0000" & x"1E1" & "00000001"; --External clk when C_N19 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register when C_N20 => S_ADC_data <= "0000" & x"018" & "00000110"; --reg 0x018 when C_N21 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register --Wait for calibration, delay when C_N22 => S_ADC_data <= "0000" & x"018" & "00000111"; --reg 0x018 when C_N23 => S_ADC_data <= "0000" & x"232" & "00000001"; --reg 0x232, Set 1 to active all register --Wait for calibration finish, delay when C_N24 => S_ADC_data <= "1000" & x"01F" & "00000100"; when others => S_ADC_data <= (others => '0'); end case; else S_ADC_data <= (others => '0'); S_ADC_trig <= '0'; end if; end if; end process; -------------------------------------------------------------------------------------------------- --Control the start of sending data and the delay -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_ADC_ready_1buf <= '0'; S_ADC_ready_2buf <= '0'; S_ADC_ready_3buf <= '0'; S_ADC_ready_4buf <= '0'; S_adc_cnt <= (others => '1'); S_data_start <= '0'; S_data_finish <= '0'; s_delay_cn <= (others => '0'); s_delay_symbol <= '0'; elsif(I_clk'event and I_clk = '1')then if (S_data_finish = '0') then s_delay_cn <= s_delay_cn + '1'; S_ADC_ready_4buf <= S_ADC_ready_3buf; S_ADC_ready_3buf <= S_ADC_ready_2buf; S_ADC_ready_2buf <= S_ADC_ready_1buf; S_ADC_ready_1buf <= S_ADC_ready; if(S_ADC_ready_2buf = '0')and (S_ADC_ready_1buf = '1')then --rising edge0 if (S_adc_cnt = C_DATA_NUMBER)then --Count the number of data to be sent S_data_finish <= '1'; S_adc_cnt <= (others => '0'); elsif(S_adc_cnt = C_N0 or S_adc_cnt = C_N21 or S_adc_cnt = C_N23)then --There is a delay after this value, set 4 means 5 data are sent s_delay_cn <= (others => '0'); s_delay_symbol <= '1'; else S_data_finish <= '0'; S_data_start <= '1'; S_adc_cnt <= S_adc_cnt + '1'; end if; elsif(S_ADC_ready_4buf = '0')and (S_ADC_ready_3buf = '1')then S_data_start <= '0'; elsif(s_delay_symbol = '1' and s_delay_cn = 500000)then --Delay 10ms to wait proper setting S_data_start <= '1'; s_delay_symbol <= '0'; S_adc_cnt <= S_adc_cnt + '1'; elsif(S_data_start = '1' and s_delay_cn = 500002)then --Two cycles for start S_data_start <= '0'; end if; else S_ADC_ready_1buf <= '0'; S_ADC_ready_2buf <= '0'; S_ADC_ready_3buf <= '0'; S_ADC_ready_4buf <= '0'; S_adc_cnt <= (others => '0'); end if; end if; end process; end rtl;

apache-2.0

1db61d12e1793547494edbbe0b6dce2d

0.370095

3.892815

false

grwlf/vsim

vhdl_ct/pro000019.vhd

1

4,233

-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00016_Test_Bench is end ENT00016_Test_Bench; architecture ARCH00016_Test_Bench of ENT00016_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); signal I_saa_lv : std_array_array; subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b1_lv : byte; signal b2 : byte2 := x"00"; signal b2_lv : byte2; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); signal I_baa_lv : bit_array_array; type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; signal I_sa_lv : std_array; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal e_lv : enum; signal ea : enum_array(0 to 3) := (others => a_v); signal ea_lv : enum_array(0 to 3); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal r_lv : rec; signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal ra_lv : rec_array(0 to 3); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal bv_lv : bit_vector(15 downto 0); signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; signal clk_lv : std_ulogic; signal clk2_lv : std_ulogic; begin clk_lv <= clk'Last_value; clk2_lv <= clk2'Last_value; bv_lv <= bv'Last_value; ra_lv <= ra'Last_value; r_lv <= r'Last_value; ea_lv <= ea'Last_value; e_lv <= e'Last_value; I_sa_lv <= I_sa'Last_value; I_baa_lv <= I_baa'Last_value; I_saa_lv <= I_saa'Last_value; b1_lv <= b1'Last_value; b2_lv <= b2'Last_value; clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00016_Test_Bench ;

gpl-3.0

d8df33bb6ec8ddaa4d237514b1cf23f9

0.551854

2.435558

false

jairov4/accel-oil

solution_spartan6/impl/vhdl/nfa_get_finals.vhd

4

14,969

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_get_finals is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_get_finals is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal nfa_finals_buckets_read_reg_63 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_136 : BOOLEAN; signal ap_sig_bdd_67 : BOOLEAN; signal ap_sig_bdd_135 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it0_preg assign process. -- ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then ap_reg_ppiten_pp0_it0_preg <= ap_start; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then nfa_finals_buckets_read_reg_63 <= nfa_finals_buckets_datain; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it2 , ap_reg_ppiten_pp0_it3 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; end if; when ap_ST_pp0_stg1_fsm_1 => if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; end if; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg) begin if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then ap_reg_ppiten_pp0_it0 <= ap_start; else ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg; end if; end process; ap_return_0 <= nfa_finals_buckets_read_reg_63; ap_return_1 <= nfa_finals_buckets_datain; -- ap_sig_bdd_135 assign process. -- ap_sig_bdd_135_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce) begin ap_sig_bdd_135 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_136 assign process. -- ap_sig_bdd_136_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_136 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))); end process; -- ap_sig_bdd_67 assign process. -- ap_sig_bdd_67_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_67 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_address assign process. -- nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_136, ap_sig_bdd_67, ap_sig_bdd_135) begin if (ap_sig_bdd_135) then if (ap_sig_bdd_67) then nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0); elsif (ap_sig_bdd_136) then nfa_finals_buckets_address <= ap_const_lv32_0; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_dataout <= ap_const_lv32_0; nfa_finals_buckets_req_din <= ap_const_logic_0; -- nfa_finals_buckets_req_write assign process. -- nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_req_write <= ap_const_logic_1; else nfa_finals_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_rsp_read assign process. -- nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_rsp_read <= ap_const_logic_1; else nfa_finals_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_finals_buckets_size <= ap_const_lv32_1; end behav;

lgpl-3.0

d0e6bbcd60cfed50cf91043ac210dcb5

0.595497

2.69275

false

wsoltys/AtomFpga

src/AtomGodilVideo/src/mouse/ps2interface.vhd

1

32,429

------------------------------------------------------------------------ -- ps2interface.vhd ------------------------------------------------------------------------ -- Author : Ulrich Zoltn -- Copyright 2006 Digilent, Inc. ------------------------------------------------------------------------ -- Software version : Xilinx ISE 7.1.04i -- WebPack -- Device : 3s200ft256-4 ------------------------------------------------------------------------ -- This file contains the implementation of a generic bidirectional -- ps/2 interface. ------------------------------------------------------------------------ -- Behavioral description ------------------------------------------------------------------------ -- Please read the following article on the web for understanding how -- the ps/2 protocol works. -- http://www.computer-engineering.org/ps2protocol/ -- This module implements a generic bidirectional ps/2 interface. It can -- be used with any ps/2 compatible device. It offers its clients a -- convenient way to exchange data with the device. The interface -- transparently wraps the byte to be sent into a ps/2 frame, generates -- parity for byte and sends the frame one bit at a time to the device. -- Similarly, when receiving data from the ps2 device, the interface -- receives the frame, checks for parity, and extract the usefull data -- and forwards it to the client. If an error occurs during receiving -- or sending a byte, the client is informed by settings the err output -- line high. This way, the client can resend the data or can issue -- a resend command to the device. -- The physical ps/2 interface uses 4 lines -- For the 6-pin connector pins are assigned as follows: -- 1 - Data -- 2 - Not Implemented -- 3 - Ground -- 4 - Vcc (+5V) -- 5 - Clock -- 6 - Not Implemented -- The clock line carries the device generated clock which has a -- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle -- it is placed in high impedance. The clock is only generated when -- device is sending or receiving data. -- The Data and Clock lines are both open-collector with pullup -- resistors to Vcc. An "open-collector" interface has two possible -- states: low('0') or high impedance('Z'). -- When device wants to send a byte, it pulls the clock line low and the -- host(i.e. this interfaces) recognizes that the device is sending data -- When the host wants to send data, it maeks a request to send. This -- is done by holding the clock line low for at least 100us, then with -- the clock line low, the data line is brought low. Next the clock line -- is released (placed in high impedance). The devices begins generating -- clock signal on clock line. -- When receiving data, bits are read from the data line (ps2_data) on -- the falling edge of the clock (ps2_clk). When sending data, the -- device reads the bits from the data line on the rising edge of the -- clock. -- A frame for sending a byte is comprised of 11 bits as shown bellow: -- bits 10 9 8 7 6 5 4 3 2 1 0 -- ------------------------------------------------------------- -- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START | -- ------------------------------------------------------------- -- STOP - stop bit, always '1' -- PAR - parity bit, odd parity for the 8 data bits. -- - select in such way that the number of bits of '1' in the data -- - bits together with parity bit is odd. -- D0-7 - data bits. -- START - start bit, always '0' -- -- Frame is sent bit by bit starting with the least significant bit -- (starting bit) and is received the same way. This is done, when -- receiving, by shifting the frame register to the left when a bit -- is available and placing the bit on data line on the most significant -- bit. This way the first bit sent will reach the least significant bit -- of the frame when all the bits have been received. When sending data -- the least significant bit of the frame is placed on the data line -- and the frame is shifted to the right when another bit needs to be -- sent. During the request to send, when releasing the clock line, -- the device reads the data line and interprets the data on it as the -- first bit of the frame. Data line is low at that time, at this is the -- way the start bit('0') is sent. Because of this, when sending, only -- 10 shifts of the frame will be made. -- While the interface is sending or receiving data, the busy output -- signal goes high. When interface is idle, busy is low. -- After sending all the bits in the frame, the device must acknowledge -- the data sent. This is done by the host releasing and data line -- (clock line is already released) after the last bit is sent. The -- devices brings the data line and the clock line low, in this order, -- to acknowledge the data. If data line is high when clock line goes -- low after last bit, the device did not acknowledge the data and -- err output is set. -- A FSM is used to manage the transitions the set all the command -- signals. States that begin with "rx_" are used to receive data -- from device and states begining with "tx_" are used to send data -- to the device. -- For the parity bit, a ROM holds the parity bit for all possible -- data (256 possible values, since 8 bits of data). The ROM has -- dimensions 256x1bit. For obtaining the parity bit of a value, -- the bit at the data value address is read. Ex: to find the parity -- bit of 174, the bit at address 174 is read. -- For generating the necessary delay, counters are used. For example, -- to generate the 100us delay a 14 bit counter is used that has the -- upper limit for counting 10000. The interface is designed to run -- at 100MHz. Thus, 10000x10ns = 100us. ----------------------------------------------------------------------- -- If using the interface at different frequency than 100MHz, adjusting -- the delay counters is necessary!!! ----------------------------------------------------------------------- -- Clock line(ps2_clk) and data line(ps2_data) are passed through a -- debouncer for the transitions of the clock and data to be clean. -- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized -- value of the clock and data line to the system clock(clk). ------------------------------------------------------------------------ -- Port definitions ------------------------------------------------------------------------ -- ps2_clk - inout pin, clock line of the ps/2 interface -- ps2_data - inout pin, clock line of the ps/2 interface -- clk - input pin, system clock signal -- rst - input pin, system reset signal -- tx_data - input pin, 8 bits, from client -- - data to be sent to the device -- write - input pin, from client -- - should be active for one clock period when then -- - client wants to send data to the device and -- - data to be sent is valid on tx_data -- rx_data - output pin, 8 bits, to client -- - data received from device -- read - output pin, to client -- - active for one clock period when new data is -- - available from device -- busy - output pin, to client -- - active while sending or receiving data. -- err - output pin, to client -- - active for one clock period when an error occurred -- - during sending or receiving. ------------------------------------------------------------------------ -- Revision History: -- 09/18/2006(UlrichZ): created ------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- simulation library library UNISIM; --use UNISIM.VComponents.all; -- the ps2interface entity declaration -- read above for behavioral description and port definitions. entity ps2interface is generic ( MainClockSpeed : integer ); port( ps2_clk : inout std_logic; ps2_data : inout std_logic; clk : in std_logic; rst : in std_logic; tx_data : in std_logic_vector(7 downto 0); write : in std_logic; rx_data : out std_logic_vector(7 downto 0); read : out std_logic; busy : out std_logic; err : out std_logic ); -- forces the extraction of distributed ram for -- the parityrom memory. -- please remove if block ram is preffered. attribute rom_extract : string; attribute rom_extract of ps2interface: entity is "yes"; attribute rom_style : string; attribute rom_style of ps2interface: entity is "distributed"; end ps2interface; architecture Behavioral of ps2interface is ------------------------------------------------------------------------ -- CONSTANTS ------------------------------------------------------------------------ -- Values are valid for a 49.152MHz clk. Please adjust for other -- frequencies if necessary! -- upper limit for 100us delay counter. -- 4915 * 20.34ns = 100us --constant DELAY_100US : std_logic_vector(13 downto 0):= "01001100110011"; constant DELAY_100US : std_logic_vector(13 downto 0):= std_logic_vector(to_unsigned(MainClockSpeed * 100 / 1000000, 14)); -- upper limit for 20us delay counter. -- 983 * 20.34ns = 20us -- constant DELAY_20US : std_logic_vector(10 downto 0) := "01111010111"; constant DELAY_20US : std_logic_vector(10 downto 0) := std_logic_vector(to_unsigned(MainClockSpeed * 20 / 1000000, 11)); -- upper limit for 63clk delay counter. constant DELAY_63CLK : std_logic_vector(5 downto 0) := "111111"; -- 63 clock periods -- delay from debouncing ps2_clk and ps2_data signals constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111"; -- number of bits in a frame constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11 -- parity bit position in frame constant PARITY_BIT: positive := 9; -- (odd) parity bit ROM -- Used instead of logic because this way speed is far greater -- 256x1bit rom -- If the odd parity bit for a 8 bits number, x, is needed -- the bit at address x is the parity bit. type ROM is array(0 to 255) of std_logic; constant parityrom : ROM := ( '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1', '1','0','0','1','0','1','1','0', '1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1' ); ------------------------------------------------------------------------ -- SIGNALS ------------------------------------------------------------------------ -- 14 bits counter -- max value DELAY_100US -- used to wait 100us signal delay_100us_count: std_logic_vector(13 downto 0) := (others => '0'); -- 11 bits counter -- max value DELAY_20US -- used to wait 20us signal delay_20us_count: std_logic_vector(10 downto 0) := (others => '0'); -- 11 bits counter -- max value DELAY_63CLK -- used to wait 63 clock periods signal delay_63clk_count: std_logic_vector(5 downto 0) := (others => '0'); -- done signal for the couters above -- when a counter reaches max value,the corresponding done signal is set signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic; -- enable signal for 100us delay counter signal delay_100us_counter_enable: std_logic := '0'; -- enable signal for 20us delay counter signal delay_20us_counter_enable : std_logic := '0'; -- enable signal for 63clk delay counter signal delay_63clk_counter_enable: std_logic := '0'; -- synchronzed input for ps2_clk and ps2_data signal ps2_clk_s,ps2_data_s: std_logic := '1'; -- control the output of ps2_clk and ps2_data -- if 1 then corresponding signal (ps2_clk or ps2_data) is -- put in high impedance ('Z'). signal ps2_clk_h,ps2_data_h: std_logic := '1'; -- states of the FSM for controlling the communcation with the device -- states that begin with "rx_" are used when receiving data -- states that begin with "tx_" are used when transmiting data type fsm_state is ( idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready, tx_force_clk_l,tx_bring_data_down,tx_release_clk, tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h, tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack, tx_error_no_ack ); -- the signal that holds the current state of the FSM -- implicitly state is idle. signal state: fsm_state := idle; -- register that holds the frame received or the one to be sent. -- Its contents are shifted in from the bus one bit at a time -- from left to right when receiving data and are shifted on the -- bus (ps2_data) one bit at a time to the right when sending data signal frame: std_logic_vector(10 downto 0) := (others => '0'); -- how many bits have been sent or received. signal bit_count: std_logic_vector(3 downto 0) := (others => '0'); -- when active the bit counter is reset. signal reset_bit_count: std_logic := '0'; -- when active the contents of the frame is shifted to the right -- and the most significant bit of frame is loaded with ps2_data. signal shift_frame: std_logic := '0'; -- parity of the byte that was received from the device. -- must match the parity bit received, else error occurred. signal rx_parity: std_logic := '0'; -- parity bit that is sent with the frame, representing the -- odd parity of the byte currently being sent signal tx_parity: std_logic := '0'; -- when active, frame is loaded with the start bit, data on -- tx_data, parity bit (tx_parity) and stop bit -- this frame will be sent to the device. signal load_tx_data: std_logic := '0'; -- when active bits 8 downto 1 from frame are loaded into -- rx_data register. This is the byte received from the device. signal load_rx_data: std_logic := '0'; -- intermediary signals used to debounce the inputs ps2_clk and ps2_data signal ps2_clk_clean,ps2_data_clean: std_logic := '1'; -- debounce counter for the ps2_clk input and the ps2_data input. signal clk_count,data_count: std_logic_vector(3 downto 0); -- last value on ps2_clk and ps2_data. signal clk_inter,data_inter: std_logic := '1'; begin --------------------------------------------------------------------- -- FLAGS and PS2 CLOCK AND DATA LINES --------------------------------------------------------------------- -- clean ps2_clk signal (debounce) -- note that this introduces a delay in ps2_clk of -- DEBOUNCE_DELAY clocks process(clk) begin if(rising_edge(clk)) then -- if the current bit on ps2_clk is different -- from the last value, then reset counter -- and retain value if(ps2_clk /= clk_inter) then clk_inter <= ps2_clk; clk_count <= (others => '0'); -- if counter reached upper limit, then -- the signal is clean elsif(clk_count = DEBOUNCE_DELAY) then ps2_clk_clean <= clk_inter; -- ps2_clk did not change, but counter did not -- reach limit. Increment counter else clk_count <= clk_count + 1; end if; end if; end process; -- clean ps2_data signal (debounce) -- note that this introduces a delay in ps2_data of -- DEBOUNCE_DELAY clocks process(clk) begin if(rising_edge(clk)) then -- if the current bit on ps2_data is different -- from the last value, then reset counter -- and retain value if(ps2_data /= data_inter) then data_inter <= ps2_data; data_count <= (others => '0'); -- if counter reached upper limit, then -- the signal is clean elsif(data_count = DEBOUNCE_DELAY) then ps2_data_clean <= data_inter; -- ps2_data did not change, but counter did not -- reach limit. Increment counter else data_count <= data_count + 1; end if; end if; end process; -- Synchronize ps2 entries ps2_clk_s <= ps2_clk_clean when rising_edge(clk); ps2_data_s <= ps2_data_clean when rising_edge(clk); -- Assign parity from frame bits 8 downto 1, this is the parity -- that should be received inside the frame on PARITY_BIT position rx_parity <= parityrom(conv_integer(frame(8 downto 1))) when rising_edge(clk); -- The parity for the data to be sent tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk); -- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line -- ('Z' = +5Vcc because of pull-ups) ps2_clk <= 'Z' when ps2_clk_h = '1' else '0'; -- Force ps2_data to '0' if ps2_data_h = '0', else release the line -- ('Z' = +5Vcc because of pull-ups) ps2_data <= 'Z' when ps2_data_h = '1' else '0'; -- Control busy flag. Interface is not busy while in idle state. busy <= '0' when state = idle else '1'; -- reset the bit counter when in idle state. reset_bit_count <= '1' when state = idle else '0'; -- Control shifting of the frame -- When receiving from device, data is read -- on the falling edge of ps2_clk -- When sending to device, data is read by device -- on the rising edge of ps2_clk shift_frame <= '1' when state = rx_down_edge or state = tx_clk_l else '0'; --------------------------------------------------------------------- -- FINITE STATE MACHINE --------------------------------------------------------------------- -- For the current state establish next state -- and give necessary commands manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write,tx_data, bit_count,rx_parity,frame,delay_100us_done, delay_20us_done,delay_63clk_done) begin -- if reset occurs, go to idle state. if(rst = '1') then state <= idle; elsif(rising_edge(clk)) then -- default values for these signals -- ensures signals are reset to default value -- when coditions for their activation are no -- longer applied (transition to other state, -- where signal should not be active) -- Idle value for ps2_clk and ps2_data is 'Z' ps2_clk_h <= '1'; ps2_data_h <= '1'; load_tx_data <= '0'; load_rx_data <= '0'; read <= '0'; err <= '0'; case state is -- wait for the device to begin a transmission -- by pulling the clock line low and go to state -- rx_down_edge or, if write is high, the -- client of this interface wants to send a byte -- to the device and a transition is made to state -- tx_force_clk_l when idle => if(ps2_clk_s = '0') then state <= rx_down_edge; elsif(write = '1') then state <= tx_force_clk_l; else state <= idle; end if; -- ps2_clk is high, check if all the bits have been read -- if, last bit read, check parity, and if parity ok -- load received data into rx_data. -- else if more bits left, then wait for the ps2_clk to -- go low when rx_clk_h => if(bit_count = NUMBITS) then if(not (rx_parity = frame(PARITY_BIT))) then state <= rx_error_parity; else load_rx_data <= '1'; state <= rx_data_ready; end if; elsif(ps2_clk_s = '0') then state <= rx_down_edge; else state <= rx_clk_h; end if; -- data must be read into frame in this state -- the ps2_clk just transitioned from high to low when rx_down_edge => state <= rx_clk_l; -- ps2_clk line is low, wait for it to go high when rx_clk_l => if(ps2_clk_s = '1') then state <= rx_clk_h; else state <= rx_clk_l; end if; -- parity bit received is invalid -- signal error and go back to idle. when rx_error_parity => err <= '1'; state <= idle; -- parity bit received was good -- set read signal for the client to know -- a new byte was received and is available on rx_data when rx_data_ready => read <= '1'; state <= idle; -- the client wishes to transmit a byte to the device -- this is done by holding ps2_clk down for at least 100us -- bringing down ps2_data, wait 20us and then releasing -- the ps2_clk. -- This constitutes a request to send command. -- In this state, the ps2_clk line is held down and -- the counter for waiting 100us is eanbled. -- when the counter reached upper limit, transition -- to tx_bring_data_down when tx_force_clk_l => load_tx_data <= '1'; ps2_clk_h <= '0'; if(delay_100us_done = '1') then state <= tx_bring_data_down; else state <= tx_force_clk_l; end if; -- with the ps2_clk line low bring ps2_data low -- wait for 20us and then go to tx_release_clk when tx_bring_data_down => -- keep clock line low ps2_clk_h <= '0'; -- set data line low -- when clock is released in the next state -- the device will read bit 0 on data line -- and this bit represents the start bit. ps2_data_h <= '0'; -- start bit = '0' if(delay_20us_done = '1') then state <= tx_release_clk; else state <= tx_bring_data_down; end if; -- release the ps2_clk line -- keep holding data line low when tx_release_clk => ps2_clk_h <= '1'; -- must maintain data low, -- otherwise will be released by default value ps2_data_h <= '0'; state <= tx_first_wait_down_edge; -- state is necessary because the clock signal -- is not released instantaneously and, because of debounce, -- delay is even greater. -- Wait 63 clock periods for the clock line to release -- then if clock is low then go to tx_clk_l -- else wait until ps2_clk goes low. when tx_first_wait_down_edge => ps2_data_h <= '0'; if(delay_63clk_done = '1') then if(ps2_clk_s = '0') then state <= tx_clk_l; else state <= tx_first_wait_down_edge; end if; else state <= tx_first_wait_down_edge; end if; -- place the least significant bit from frame -- on the data line -- During this state the frame is shifted one -- bit to the right when tx_clk_l => ps2_data_h <= frame(0); state <= tx_wait_up_edge; -- wait for the clock to go high -- this is the edge on which the device reads the data -- on ps2_data. -- keep holding ps2_data on frame(0) because else -- will be released by default value. -- Check if sent the last bit and if so, release data line -- and go to state that wait for acknowledge when tx_wait_up_edge => ps2_data_h <= frame(0); -- NUMBITS - 1 because first (start bit = 0) bit was read -- when the clock line was released in the request to -- send command (see tx_bring_data_down state). if(bit_count = NUMBITS-1) then ps2_data_h <= '1'; state <= tx_wait_up_edge_before_ack; -- if more bits to send, wait for the up edge -- of ps2_clk elsif(ps2_clk_s = '1') then state <= tx_clk_h; else state <= tx_wait_up_edge; end if; -- ps2_clk is released, wait for down edge -- and go to tx_clk_l when arrived when tx_clk_h => ps2_data_h <= frame(0); if(ps2_clk_s = '0') then state <= tx_clk_l; else state <= tx_clk_h; end if; -- release ps2_data and wait for rising edge of ps2_clk -- once this occurs, transition to tx_wait_ack when tx_wait_up_edge_before_ack => ps2_data_h <= '1'; if(ps2_clk_s = '1') then state <= tx_wait_ack; else state <= tx_wait_up_edge_before_ack; end if; -- wait for the falling edge of the clock line -- if data line is low when this occurs, the -- ack is received -- else if data line is high, the device did not -- acknowledge the transimission when tx_wait_ack => if(ps2_clk_s = '0') then if(ps2_data_s = '0') then -- acknowledge received state <= tx_received_ack; else -- acknowledge not received state <= tx_error_no_ack; end if; else state <= tx_wait_ack; end if; -- wait for ps2_clk to be released together with ps2_data -- (bus to be idle) and go back to idle state when tx_received_ack => if(ps2_clk_s = '1' and ps2_data_s = '1') then state <= idle; else state <= tx_received_ack; end if; -- wait for ps2_clk to be released together with ps2_data -- (bus to be idle) and go back to idle state -- signal error for not receiving ack when tx_error_no_ack => if(ps2_clk_s = '1' and ps2_data_s = '1') then err <= '1'; state <= idle; else state <= tx_error_no_ack; end if; -- if invalid transition occurred, signal error and -- go back to idle state when others => err <= '1'; state <= idle; end case; end if; end process manage_fsm; --------------------------------------------------------------------- -- DELAY COUNTERS --------------------------------------------------------------------- -- Enable the 100us counter only when state is tx_force_clk_l delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0'; -- Counter for a 100us delay -- after done counting, done signal remains active until -- enable counter is reset. delay_100us_counter: process(clk) begin if(rising_edge(clk)) then if(delay_100us_counter_enable = '1') then if(delay_100us_count = (DELAY_100US)) then delay_100us_count <= delay_100us_count; delay_100us_done <= '1'; else delay_100us_count <= delay_100us_count + 1; delay_100us_done <= '0'; end if; else delay_100us_count <= (others => '0'); delay_100us_done <= '0'; end if; end if; end process delay_100us_counter; -- Enable the 20us counter only when state is tx_bring_data_down delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0'; -- Counter for a 20us delay -- after done counting, done signal remains active until -- enable counter is reset. delay_20us_counter: process(clk) begin if(rising_edge(clk)) then if(delay_20us_counter_enable = '1') then if(delay_20us_count = (DELAY_20US)) then delay_20us_count <= delay_20us_count; delay_20us_done <= '1'; else delay_20us_count <= delay_20us_count + 1; delay_20us_done <= '0'; end if; else delay_20us_count <= (others => '0'); delay_20us_done <= '0'; end if; end if; end process delay_20us_counter; -- Enable the 63clk counter only when state is tx_first_wait_down_edge delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0'; -- Counter for a 63 clock periods delay -- after done counting, done signal remains active until -- enable counter is reset. delay_63clk_counter: process(clk) begin if(rising_edge(clk)) then if(delay_63clk_counter_enable = '1') then if(delay_63clk_count = (DELAY_63CLK)) then delay_63clk_count <= delay_63clk_count; delay_63clk_done <= '1'; else delay_63clk_count <= delay_63clk_count + 1; delay_63clk_done <= '0'; end if; else delay_63clk_count <= (others => '0'); delay_63clk_done <= '0'; end if; end if; end process delay_63clk_counter; --------------------------------------------------------------------- -- BIT COUNTER AND FRAME SHIFTING LOGIC --------------------------------------------------------------------- -- counts the number of bits shifted into the frame -- or out of the frame. bit_counter: process(clk) begin if(rising_edge(clk)) then if(reset_bit_count = '1') then bit_count <= (others => '0'); elsif(shift_frame = '1') then bit_count <= bit_count + 1; end if; end if; end process bit_counter; -- shifts frame with one bit to right when shift_frame is acitve -- and loads data into frame from tx_data then load_tx_data is high load_tx_data_into_frame: process(clk) begin if(rising_edge(clk)) then if(load_tx_data = '1') then frame(8 downto 1) <= tx_data; -- byte to send frame(0) <= '0'; -- start bit frame(10) <= '1'; -- stop bit frame(9) <= tx_parity; -- parity bit elsif(shift_frame = '1') then -- shift right 1 bit frame(9 downto 0) <= frame(10 downto 1); -- shift in from the ps2_data line frame(10) <= ps2_data_s; end if; end if; end process load_tx_data_into_frame; -- Loads data from frame into rx_data output when data is ready do_load_rx_data: process(clk) begin if(rising_edge(clk)) then if(load_rx_data = '1') then rx_data <= frame(8 downto 1); end if; end if; end process do_load_rx_data; end Behavioral;

apache-2.0

ed12585bba5504711afad7b97d9f6c44

0.539517

3.957169

false

grwlf/vsim

vhdl_ct/ct00107.vhd

1

11,994

-- NEED RESULT: ARCH00107.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00107: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00107 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00107) -- ENT00107_Test_Bench(ARCH00107_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00107 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- begin PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_rec1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns, c_st_rec1_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P1" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns , c_st_rec1_vector_1(highb).f2 after 20 ns , c_st_rec1_vector_2(highb).f2 after 30 ns , c_st_rec1_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_rec2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns, c_st_rec2_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P2" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns , c_st_rec2_vector_1(highb).f2 after 20 ns , c_st_rec2_vector_2(highb).f2 after 30 ns , c_st_rec2_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_rec3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns, c_st_rec3_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00107.P3" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns , c_st_rec3_vector_1(highb).f2 after 20 ns , c_st_rec3_vector_2(highb).f2 after 30 ns , c_st_rec3_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00107" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00107" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- -- end ARCH00107 ; -- entity ENT00107_Test_Bench is end ENT00107_Test_Bench ; -- architecture ARCH00107_Test_Bench of ENT00107_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00107 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00107_Test_Bench ;

gpl-3.0

aba916ef8864d61a85d80dca36a1f69c

0.5341

3.676885

false

true

false