repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
wsoltys/AtomFpga | src/MC6522/m6522.vhd | 1 | 25,323 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
I_CB1 : in std_logic;
O_CB1 : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic_vector(1 downto 0);
RESET_L : in std_logic;
ENA_4 : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0);
signal p2_h_t1 : std_logic;
signal cs : std_logic;
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0);
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
-- timer 2
signal t2div16 : std_logic_vector(3 downto 0);
signal t2c : std_logic_vector(15 downto 0);
-- signal t2c : std_logic_vector(15 downto 0);
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_off_delay : std_logic;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg : std_logic;
signal cb1_ip_reg : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg : std_logic;
signal cb2_ip_reg : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
wait until rising_edge(CLK);
phase <= I_P2_H;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') then
cs <= '1';
end if;
end process;
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
if (r_acr(7) = '1') and (t1_toggle = '1') then
r_orb(7) <= not r_orb(7);
end if;
end if;
end process;
p_write_reg : process(RESET_L, CLK)
begin
------------------------------
if (RESET_L = '0') then
r_t2l_l <= x"ff";
r_t2l_h <= x"ff";
elsif rising_edge(CLK) then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end process;
p_read : process
begin
wait until rising_edge(CLK);
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c(7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c(7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end process;
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= sr_cb1_out;
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '0';
O_CB2 <= '0';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= '0'; -- input
when "001" => O_CA2 <= '0'; -- input
when "010" => O_CA2 <= '0'; -- input
when "011" => O_CA2 <= '0'; -- input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= '0'; -- input
when "001" => O_CB2 <= '0'; -- input
when "010" => O_CB2 <= '0'; -- input
when "011" => O_CB2 <= '0'; -- input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg <= '0';
cb1_ip_reg <= '0';
ca2_ip_reg <= '0';
cb2_ip_reg <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg <= I_CA1;
cb1_ip_reg <= cb1_in_mux;
ca2_ip_reg <= I_CA2;
cb2_ip_reg <= I_CB2;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PB(7 downto 0) <= r_orb(7 downto 0);
end process;
--
-- Timer 1
--
p_timer1_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
if (phase = "11") then
t1_reload_counter <= done and (r_acr(6) = '1');
end if;
end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c(7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
elsif (phase = "11") then
t1c <= std_logic_vector(unsigned(t1c) - 1);
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
t1_toggle <= '1';
t1_irq <= '1';
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
p_timer2_done : process(t2c, phase)
variable done : boolean;
begin
done := (t2c = x"0000");
t2c_done <= done and (phase = "11");
t2_reload_counter <= done;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (r_acr(5) = '0') then
ena := true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0');
end if;
if t2_load_counter and (phase = "11") then
t2c(7 downto 0) <= not r_t2l_l;
t2c(15 downto 8) <= not r_t2l_h;
else
if (ENA_4 = '1') then
if (phase = "11") and ena then
t2c <= t2c + 1;
end if;
end if;
end if;
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if RESET_L = '0' then
t2c_active <= false;
end if;
if t2c_active and t2c_done then
t2_irq <= '1';
elsif RESET_L = '0' or t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '1';
sr_off_delay <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
case r_acr(4 downto 2) is
when "000" => ena := '0'; cb1_ip := '1';
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "010" => ena := '1'; cb1_op := '1';
when "011" => ena := '1'; cb1_ip := '1';
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
when "110" => ena := '1';
when "111" => ena := '1'; cb1_ip := '1';
when others => null;
end case;
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
if sr_write_ena then
r_sr <= load_data;
else
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
r_sr <= r_sr(6 downto 0) & I_CB2;
end if;
end if;
sr_out <= '1';
else
-- output
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
r_sr(7 downto 1) <= r_sr(6 downto 0);
r_sr(0) <= r_sr(7);
sr_out <= r_sr(7);
end if;
else
sr_out <= '1';
end if;
end if;
end if;
sr_count_ena := sr_strobe_rising;
if sr_write_ena or sr_read_ena then
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= sr_cnt + "1";
end if;
if (phase = "00") then
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL;
| apache-2.0 | a45435d05ca4af19e9fba6bf5d3993fc | 0.394029 | 3.389506 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00367.vhd | 1 | 5,385 | -- NEED RESULT: ARCH00367.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00367: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00367: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00367
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00367(ARCH00367)
-- ENT00367_Test_Bench(ARCH00367_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00367 is
end ENT00367 ;
--
--
architecture ARCH00367 of ENT00367 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00367.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00367" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00367" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00367" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ;
--
end ARCH00367 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00367_Test_Bench is
end ENT00367_Test_Bench ;
--
--
architecture ARCH00367_Test_Bench of ENT00367_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00367 ( ARCH00367 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00367_Test_Bench ;
| gpl-3.0 | dd31d6f21855a64a790e46c07a17b309 | 0.505107 | 3.150965 | false | true | false | false |
grwlf/vsim | vhdl/bigvector2-1.vhd | 1 | 779 | entity test is
end entity test;
architecture test_arch of test is
constant CYCLES : integer := 100;
-- constant size : integer := 60000;
constant size : integer := 16#10000#;
-- constant size : integer := 16#10000#;
-- constant size : integer := 3000;
-- constant size : integer := 16#2#;
type vector_t is array (0 to size-1) of integer;
signal clk : integer := 0;
begin
main: process(clk)
variable big_vector : vector_t;
begin
for i in 0 to size-1 loop
big_vector(i) := clk;
end loop;
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end architecture test_arch;
| gpl-3.0 | d1f929c41a5f80b0e28f8a02ca228356 | 0.641849 | 3.300847 | false | true | false | false |
dcliche/mdsynth | rtl/src/ps2_keyboard.vhd | 1 | 33,504 | --===========================================================================--
-- --
-- ps2_keyboard.vhd - Synthesizable PS/2 Keyboard Interface --
-- --
--===========================================================================--
--
-- File name : ps2_keyboard.vhd
--
-- Purpose : Implements a PS/2 Keyboard Interface
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Author : Original Verilog version by John Clayton
-- Converted to VHDL by John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description :
--
-- This is a state-machine driven serial-to-parallel and parallel-to-serial
-- interface to the ps2 style keyboard interface. The details of the operation
-- of the keyboard interface were obtained from the following website:
--
-- http://www.beyondlogic.org/keyboard/keybrd.htm
--
-- Some aspects of the keyboard interface are not implemented (e.g, parity
-- checking for the receive side, and recognition of the various commands
-- which the keyboard sends out, such as "power on selt test passed," "Error"
-- and "Resend.") However, if the user wishes to recognize these reply
-- messages, the scan code output can always be used to extend functionality
-- as desired.
--
-- Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
-- The rx interface provides separate indicator flags for these two conditions
-- with every valid character scan code which it provides. The shift keys are
-- also trapped by the interface, in order to provide correct uppercase ASCII
-- characters at the ascii output, although the scan codes for the shift keys
-- are still provided at the scan code output. So, the left/right ALT keys
-- can be differentiated by the presence of the rx_entended signal, while the
-- left/right shift keys are differentiable by the different scan codes
-- received.
--
-- The interface to the ps2 keyboard uses ps2_clk clock rates of
-- 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
-- machine runs should be at least twice the rate of the ps2_clk, so that the
-- states can accurately follow the clock signal itself. Four times
-- oversampling is better. Say 200kHz at least. The upper limit for clocking
-- the state machine will undoubtedly be determined by delays in the logic
-- which decodes the scan codes into ASCII equivalents. The maximum speed
-- will be most likely many megahertz, depending upon target technology.
-- In order to run the state machine extremely fast, synchronizing flip-flops
-- have been added to the ps2_clk and ps2_data inputs of the state machine.
-- This avoids poor performance related to slow transitions of the inputs.
--
-- Because this is a bi-directional interface, while reading from the keyboard
-- the ps2_clk and ps2_data lines are used as inputs. While writing to the
-- keyboard, however (which may be done at any time. If writing interrupts a
-- read from the keyboard, the keyboard will buffer up its data, and send
-- it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
-- and pullup resistors are used to bring the lines high again, by setting
-- the drivers to high impedance state.
--
-- The tx interface, for writing to the keyboard, does not provide any special
-- pre-processing. It simply transmits the 8-bit command value to the
-- keyboard.
--
-- Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
-- whether they be internal to an FPGA I/O pad, or externally placed.
-- If internal pullups are used, they may be fairly weak, causing bounces
-- due to crosstalk, etc. There is a "debounce timer" implemented in order
-- to eliminate erroneous state transitions which would occur based on bounce.
--
-- Parameters are provided in order to configure and appropriately size the
-- counter of a 60 microsecond timer used in the transmitter, depending on
-- the clock frequency used. The 60 microsecond period is guaranteed to be
-- more than one period of the ps2_clk_s signal.
--
-- Also, a smaller 5 microsecond timer has been included for "debounce".
-- This is used because, with internal pullups on the ps2_clk and ps2_data
-- lines, there is some bouncing around which occurs
--
-- A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
-- from producing scan codes (along with their "undefined" ASCII equivalents)
-- at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
-- key status will only be reported by rx_shift_on. No ascii or scan
-- codes will be reported for the shift keys. This is useful for those who
-- wish to use the ASCII data stream, and who don't want to have to "filter
-- out" the shift key codes.
--
-- Copyright (C) 2001 - 2010 John Clayton and John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Author: John Clayton
-- 2001-04-30 copied this file from lcd_2.v (pared down).
-- 2001-05-24 changed the first module from "ps2_keyboard_receiver"
-- to "ps2_keyboard_interface"
-- 2001-05-29 Added input synchronizing flip-flops. Changed state
-- encoding (m1) for good operation after part config.
-- 2001-05-31 Added low drive strength and slow transitions to ps2_clk
-- and ps2_data in the constraints file. Added the signal
-- "tx_shifting_done" as distinguished from "rx_shifting_done."
-- Debugged the transmitter portion in the lab.
-- 2001-06-01 Added horizontal tab to the ascii output.
-- 2001-06-01 Added parameter TRAP_SHIFT_KEYS.
-- 2001-06-05 Debugged the "debounce" timer functionality.
-- Used 60usec timer as a "watchdog" timeout during
-- receive from the keyboard. This means that a keyboard
-- can now be "hot plugged" into the interface, without
-- messing up the bit_count, since the bit_count is reset
-- to zero during periods of inactivity anyway. This was
-- difficult to debug. I ended up using the logic analyzer,
-- and had to scratch my head quite a bit.
-- 2001-06-06 Removed extra comments before the input synchronizing
-- flip-flops. Used the correct parameter to size the
-- 5usec_timer_count. Changed the name of this file from
-- ps2.v to ps2_keyboard.v
-- 2001-06/06 Removed "&& q[7:0]" in output_strobe logic. Removed extra
-- commented out "else" condition in the shift register and
-- bit counter.
-- 2001-06-07 Changed default values for 60usec timer parameters so that
-- they correspond to 60usec for a 49.152MHz clock.
--
-- Author: John Kent
--2001-02-10 Converted to VHDL
-- 2004-09-11 Added ctrl key
-- Changed undefined key codes to x"ff"
-- Reversed clock polarity
-- 2004-10-18 Added ctrl keys to ASCII ROM
-- Added CAPS Lock toggle.
-- 2007-02-06 Added Generic Clock parameter
-- 2010-05-31 Revised header, added GPL
-- 2010-06-17 Change some signal names for consistancy
-- 2010-10-24 Rearranged code to prevent shift key outputting characters
--
--
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
entity ps2_keyboard is
generic (
CLK_FREQ_MHZ : integer
);
port(
clk : in std_logic;
reset : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_read : in std_logic;
rx_data_ready : out std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_on : out std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_data_empty : out std_logic;
tx_error : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end ps2_keyboard;
-------------------------------------------------------------------------------
-- Architecture for ps2 keyboard interface
-------------------------------------------------------------------------------
architecture rtl of ps2_keyboard is
-----------------------------------------------------------------------------
constant TOTAL_BITS : integer := 11;
constant EXTEND_CODE : integer := 16#E0#;
constant RELEASE_CODE : integer := 16#F0#;
constant LEFT_SHIFT : integer := 16#12#;
constant RIGHT_SHIFT : integer := 16#59#;
constant CTRL_CODE : integer := 16#14#;
constant LEFT_ALT : integer := 16#11#;
constant CAPS_CODE : integer := 16#58#;
constant SCROLL_LOCK : integer := 16#7E#;
constant NUM_LOCK : integer := 16#77#;
-- constants
-- The timer value can be up to (2^bits) inclusive.
-- Values for 49.152 MHz clock
--constant TIMER_60USEC_VALUE_PP : integer := 2950; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 186; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
-- Values for 12.5 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 750; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 10; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 62; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 6; -- Number of bits needed for timer
-- Values for 25 MHz Clock
--constant TIMER_60USEC_VALUE_PP : integer := 1500; -- Number of sys_clks for 60usec.
--constant TIMER_60USEC_BITS_PP : integer := 11; -- Number of bits needed for timer
--constant TIMER_5USEC_VALUE_PP : integer := 125; -- Number of sys_clks for debounce
--constant TIMER_5USEC_BITS_PP : integer := 7; -- Number of bits needed for timer
-- Values for generic Clock up to 50 MHz
constant TIMER_60USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 60; -- Number of clock cycles for 60usec.
constant TIMER_60USEC_BITS_PP : integer := 12; -- Number of bits needed for timer
constant TIMER_5USEC_VALUE_PP : integer := CLK_FREQ_MHZ * 5; -- Number of clock cycles for debounce
constant TIMER_5USEC_BITS_PP : integer := 8; -- Number of bits needed for timer
constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Default: No shift key trap.
-- State encodings, provided as constants
-- for flexibility to the one instantiating the module.
-- In general, the default values need not be changed.
-- State "m1_rx_clk_l" has been chosen on purpose. Since the input
-- synchronizing flip-flops initially contain zero, it takes one clk
-- for them to update to reflect the actual (idle = high) status of
-- the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
-- allows the state machine to transition to m1_rx_clk_h when the true
-- values of the input signals become present at the outputs of the
-- synchronizing flip-flops. This initial transition is harmless, and it
-- eliminates the need for a "reset" pulse before the interface can operate.
type m1_type is ( m1_rx_clk_h, m1_rx_clk_l,
m1_tx_wait_clk_h, m1_tx_force_clk_l,
m1_tx_clk_h, m1_tx_clk_l,
m1_tx_wait_keyboard_ack, m1_tx_done_recovery,
m1_tx_error, m1_tx_rising_edge_marker,
m1_tx_first_wait_clk_h, m1_tx_first_wait_clk_l, m1_tx_reset_timer,
m1_rx_falling_edge_marker, m1_rx_rising_edge_marker );
-- Internal signal declarations
signal timer_60usec_done : std_logic;
signal timer_5usec_done : std_logic;
signal extended : std_logic;
signal released : std_logic;
signal shift_key_on : std_logic;
signal ctrl_key_on : std_logic;
signal caps_key_on : std_logic;
-- NOTE: These two signals used to be one. They
-- were split into two signals because of
-- shift key trapping. With shift key
-- trapping, no event is generated externally,
-- but the "hold" data must still be cleared
-- anyway regardless, in preparation for the
-- next scan codes.
signal rx_output_event : std_logic; -- Used only to clear: hold_released, hold_extended
signal rx_output_strobe : std_logic; -- Used to produce the actual output.
signal tx_parity_bit : std_logic;
signal rx_shifting_done : std_logic;
signal tx_shifting_done : std_logic;
signal shift_key_plus_code: std_logic_vector(8 downto 0);
signal q : std_logic_vector(TOTAL_BITS-1 downto 0);
signal m1_state : m1_type;
signal m1_next_state : m1_type;
signal bit_count : std_logic_vector(3 downto 0);
signal enable_timer_60usec: std_logic;
signal enable_timer_5usec : std_logic;
signal timer_60usec_count : std_logic_vector(TIMER_60USEC_BITS_PP-1 downto 0);
signal timer_5usec_count : std_logic_vector(TIMER_5USEC_BITS_PP-1 downto 0);
signal ascii : std_logic_vector(7 downto 0); -- "REG" type only because a case statement is used.
signal left_shift_key : std_logic;
signal right_shift_key : std_logic;
signal hold_extended : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal hold_released : std_logic; -- Holds prior value, cleared at rx_output_strobe
signal ps2_clk_s : std_logic; -- Synchronous version of this input
signal ps2_data_s : std_logic; -- Synchronous version of this input
signal ps2_clk_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal ps2_data_hi_z : std_logic; -- Without keyboard, high Z equals 1 due to pullups.
signal tx_data_empty_o : std_logic;
--
-- key lookup table
--
component keymap_rom
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
begin
my_key_map : keymap_rom
Port map (
clk => clk,
rst => reset,
cs => '1',
rw => '1',
addr => shift_key_plus_code,
data_in => "00000000",
data_out => ascii
);
----------------------------------------------------------------------------
-- Module code
-- assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
-- assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
--
ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z )
begin
if( ps2_clk_hi_z = '1' ) then
ps2_clk <= 'Z';
else
ps2_clk <= '0';
end if;
if( ps2_data_hi_z = '1' ) then
ps2_data <= 'Z';
else
ps2_data <= '0';
end if;
end process;
-- Input "synchronizing" logic -- synchronizes the inputs to the state
-- machine clock, thus avoiding errors related to
-- spurious state machine transitions.
ps2_synch : process(clk, ps2_clk, ps2_data)
begin
if clk'event and clk='0' then
ps2_clk_s <= ps2_clk;
ps2_data_s <= ps2_data;
end if;
end process;
-- State register
m1_state_register : process( clk, reset, m1_state )
begin
if clk'event and clk='0' then
if (reset = '1') then
m1_state <= m1_rx_clk_h;
else
m1_state <= m1_next_state;
end if;
end if;
end process;
m1_state_logic : process( m1_state, q,
tx_shifting_done, tx_write,
ps2_clk_s, ps2_data_s,
timer_60usec_done, timer_5usec_done )
begin
-- Output signals default to this value, unless changed in a state condition.
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
case (m1_state) is
--
-- receive clock transitions
--
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
end if;
when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;
when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;
--
-- write to keyboard (Tx)
--
when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;
when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;
when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
-- This state must be included because the device might possibly
-- delay for up to 10 milliseconds before beginning its clock pulses.
-- During that waiting time, we cannot drive the data (q[0]) because it
-- is possibly 1, which would cause the keyboard to abort its receive
-- and the expected clocks would then never be generated.
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;
when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;
when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;
when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;
when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;
when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
end if;
when m1_tx_error =>
tx_error <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error;
end if;
when others =>
m1_next_state <= m1_rx_clk_h;
end case;
end process;
--
-- This is the bit counter
--
bit_counter: process(clk, reset, m1_state, bit_count )
begin
if clk'event and clk = '0' then
if ( reset = '1' ) or ( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then -- After tx is done.
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and
( m1_state = m1_rx_clk_h ) and
( ps2_clk_s = '1' ) then
bit_count <= "0000"; -- rx watchdog timer reset
elsif ( m1_state = m1_rx_falling_edge_marker ) or -- increment for rx
(m1_state = m1_tx_rising_edge_marker) then -- increment for tx
bit_count <= bit_count + 1;
end if;
end if;
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;
if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
end process;
assign: process( bit_count, tx_write, m1_state, tx_data_empty_o, m1_state )
begin
--
-- This is the signal which enables loading of the shift register.
-- It also indicates "ack" to the device writing to the transmitter.
--
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_data_empty_o <= '1';
else
tx_data_empty_o <= '0';
end if;
tx_data_empty <= tx_data_empty_o;
end process;
-- This is the shift register
q_shift : process(clk, tx_data_empty_o, tx_parity_bit, tx_data,
m1_state, q, ps2_data_s, rx_shifting_done )
begin
--
-- This is the ODD parity bit for the transmitted word.
-- assign tx_parity_bit = ~^tx_data;
--
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4) xor
tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );
if clk'event and clk='0' then
if (reset = '1') then
q <= (others=>'0');
elsif (tx_data_empty_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
end process;
--
-- This is the 60usec timer counter
--
timer60usec: process(clk, enable_timer_60usec, timer_60usec_count)
begin
if clk'event and clk = '0' then
if (enable_timer_60usec = '0') then
timer_60usec_count <= (others => '0');
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;
if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
end process;
--
-- This is the 5usec timer counter
--
timer5usec : process(clk, enable_timer_5usec, timer_5usec_count )
begin
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= (others => '0');
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
end process;
--
-- Create the signals which indicate special scan codes received.
-- These are the "unlatched versions."
--
extend_release_decode : process( q, rx_shifting_done, extended, released )
begin
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
else
rx_output_event <= '0';
end if;
end process;
--
-- Store the special scan code status bits
-- Not the final output, but an intermediate storage place,
-- until the entire set of output data can be assembled.
--
special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended, released )
begin
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
end process;
--
-- convert scan code to ascii code
--
scan_to_ascii : process( shift_key_on, caps_key_on, q )
begin
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);
end process;
--
-- These bits contain the status of the two shift keys
--
left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and (rx_shifting_done = '1') then
left_shift_key <= not hold_released;
end if;
end if;
end process;
right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and (rx_shifting_done = '1') then
right_shift_key <= not hold_released;
end if;
end if;
end process;
shift_proc : process( left_shift_key, right_shift_key, shift_key_on, caps_key_on, q )
begin
shift_key_on <= left_shift_key or right_shift_key;
rx_shift_on <= shift_key_on;
end process;
--
-- Control keys
--
ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and (rx_shifting_done = '1') then
ctrl_key_on <= not hold_released;
end if;
end if;
end process;
--
-- Caps lock
--
caps_proc : process(clk, reset, q, rx_shifting_done, hold_released, caps_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and (rx_shifting_done = '1') then
if (hold_released = '0') then
caps_key_on <= not caps_key_on;
end if;
end if;
end if;
end process;
--
-- Output the special scan code flags, the scan code and the ascii
--
special_scan_proc : process(clk, reset, rx_output_strobe,
hold_extended, hold_released,
ascii, ctrl_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
rx_data <= (others=>'0');
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
if ctrl_key_on = '1' then
rx_data <= ascii and x"1f";
else
rx_data <= ascii;
end if;
end if;
end if;
end process;
--
-- Store the final rx output data only when all extend and release codes
-- are received and the next (actual key) scan code is also ready.
-- (the presence of rx_extended or rx_released refers to the
-- the current latest scan code received, not the previously latched flags.)
--
rx_output_proc : process( clk, reset,
rx_shifting_done, rx_output_strobe,
extended, released,
hold_extended, hold_released,
q, ascii, rx_read )
begin
if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and (rx_output_strobe = '0') and
(extended = '0') and (released = '0') and
(hold_released = '0' ) and
(ascii /= "00000000" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
end process;
--
-- This part translates the scan code into an ASCII value...
-- Only the ASCII codes which I considered important have been included.
-- if you want more, just add the appropriate case statement lines...
-- (You will need to know the keyboard scan codes you wish to assign.)
-- The entries are listed in ascending order of ASCII value.
--
--shift_map : process( shift_key_plus_code )
--begin
-- case shift_key_plus_code is
-- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"00d" => ascii <= x"09"; -- Horizontal Tab
-- when x"10d" => ascii <= x"09"; -- Horizontal Tab
-- when x"05a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"15a" => ascii <= x"0d"; -- Carriage return ("enter" key)
-- when x"076" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"176" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"029" => ascii <= x"20"; -- Space
-- when x"129" => ascii <= x"20"; -- Space
-- when x"116" => ascii <= x"21"; -- !
-- when x"152" => ascii <= x"22"; -- "
-- when x"126" => ascii <= x"23"; -- #
-- when x"125" => ascii <= x"24"; -- $
-- when x"12e" => ascii <= x"25"; --
-- when x"13d" => ascii <= x"26"; --
-- when x"052" => ascii <= x"27"; --
-- when x"146" => ascii <= x"28"; --
-- when x"145" => ascii <= x"29"; --
-- when x"13e" => ascii <= x"2a"; -- *
-- when x"155" => ascii <= x"2b"; -- +
-- when x"041" => ascii <= x"2c"; -- ,
-- when x"04e" => ascii <= x"2d"; -- -
-- when x"049" => ascii <= x"2e"; -- .
-- when x"04a" => ascii <= x"2f"; -- /
-- when x"045" => ascii <= x"30"; -- 0
-- when x"016" => ascii <= x"31"; -- 1
-- when x"01e" => ascii <= x"32"; -- 2
-- when x"026" => ascii <= x"33"; -- 3
-- when x"025" => ascii <= x"34"; -- 4
-- when x"02e" => ascii <= x"35"; -- 5
-- when x"036" => ascii <= x"36"; -- 6
-- when x"03d" => ascii <= x"37"; -- 7
-- when x"03e" => ascii <= x"38"; -- 8
-- when x"046" => ascii <= x"39"; -- 9
-- when x"14c" => ascii <= x"3a"; -- :
-- when x"04c" => ascii <= x"3b"; -- ;
-- when x"141" => ascii <= x"3c"; -- <
-- when x"055" => ascii <= x"3d"; -- =
-- when x"149" => ascii <= x"3e"; -- >
-- when x"14a" => ascii <= x"3f"; -- ?
-- when x"11e" => ascii <= x"40"; -- @
-- when x"11c" => ascii <= x"41"; -- A
-- when x"132" => ascii <= x"42"; -- B
-- when x"121" => ascii <= x"43"; -- C
-- when x"123" => ascii <= x"44"; -- D
-- when x"124" => ascii <= x"45"; -- E
-- when x"12b" => ascii <= x"46"; -- F
-- when x"134" => ascii <= x"47"; -- G
-- when x"133" => ascii <= x"48"; -- H
-- when x"143" => ascii <= x"49"; -- I
-- when x"13b" => ascii <= x"4a"; -- J
-- when x"142" => ascii <= x"4b"; -- K
-- when x"14b" => ascii <= x"4c"; -- L
-- when x"13a" => ascii <= x"4d"; -- M
-- when x"131" => ascii <= x"4e"; -- N
-- when x"144" => ascii <= x"4f"; -- O
-- when x"14d" => ascii <= x"50"; -- P
-- when x"115" => ascii <= x"51"; -- Q
-- when x"12d" => ascii <= x"52"; -- R
-- when x"11b" => ascii <= x"53"; -- S
-- when x"12c" => ascii <= x"54"; -- T
-- when x"13c" => ascii <= x"55"; -- U
-- when x"12a" => ascii <= x"56"; -- V
-- when x"11d" => ascii <= x"57"; -- W
-- when x"122" => ascii <= x"58"; -- X
-- when x"135" => ascii <= x"59"; -- Y
-- when x"11a" => ascii <= x"5a"; -- Z
-- when x"054" => ascii <= x"5b"; -- [
-- when x"05d" => ascii <= x"5c"; -- \
-- when x"05b" => ascii <= x"5d"; -- ]
-- when x"136" => ascii <= x"5e"; -- ^
-- when x"14e" => ascii <= x"5f"; -- _
-- when x"00e" => ascii <= x"60"; -- `
-- when x"01c" => ascii <= x"61"; -- a
-- when x"032" => ascii <= x"62"; -- b
-- when x"021" => ascii <= x"63"; -- c
-- when x"023" => ascii <= x"64"; -- d
-- when x"024" => ascii <= x"65"; -- e
-- when x"02b" => ascii <= x"66"; -- f
-- when x"034" => ascii <= x"67"; -- g
-- when x"033" => ascii <= x"68"; -- h
-- when x"043" => ascii <= x"69"; -- i
-- when x"03b" => ascii <= x"6a"; -- j
-- when x"042" => ascii <= x"6b"; -- k
-- when x"04b" => ascii <= x"6c"; -- l
-- when x"03a" => ascii <= x"6d"; -- m
-- when x"031" => ascii <= x"6e"; -- n
-- when x"044" => ascii <= x"6f"; -- o
-- when x"04d" => ascii <= x"70"; -- p
-- when x"015" => ascii <= x"71"; -- q
-- when x"02d" => ascii <= x"72"; -- r
-- when x"01b" => ascii <= x"73"; -- s
-- when x"02c" => ascii <= x"74"; -- t
-- when x"03c" => ascii <= x"75"; -- u
-- when x"02a" => ascii <= x"76"; -- v
-- when x"01d" => ascii <= x"77"; -- w
-- when x"022" => ascii <= x"78"; -- x
-- when x"035" => ascii <= x"79"; -- y
-- when x"01a" => ascii <= x"7a"; -- z
-- when x"154" => ascii <= x"7b"; -- {
-- when x"15d" => ascii <= x"7c"; -- |
-- when x"15b" => ascii <= x"7d"; -- }
-- when x"10e" => ascii <= x"7e"; -- ~
-- when x"071" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when x"171" => ascii <= x"7f"; -- (Delete OR DEL on numeric keypad)
-- when others => ascii <= x"00"; -- 0xff used for unlisted characters.
-- end case;
--end process;
end rtl;
| gpl-3.0 | ca4307c3691c045228ddd3632b0b9b00 | 0.594586 | 3.000269 | false | false | false | false |
Given-Jiang/Binarization | tb_Binarization/hdl/Binarization.vhd | 2 | 2,729 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Binarization;
architecture rtl of Binarization is
component Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Binarization_GN;
begin
Binarization_GN_0: if true generate
inst_Binarization_GN_0: Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
| mit | 66555f1842bf20ad697a95f9aa20ce4a | 0.739831 | 3.104664 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00096.vhd | 1 | 15,349 | -- NEED RESULT: ARCH00096.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096.P2: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096.P3: Multi transport transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: One transport transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00096: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00096
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00096)
-- ENT00096_Test_Bench(ARCH00096_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00096 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00096.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00096" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00096.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00096" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00096.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00096" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00096" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00096 ;
--
entity ENT00096_Test_Bench is
end ENT00096_Test_Bench ;
--
architecture ARCH00096_Test_Bench of ENT00096_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00096 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00096_Test_Bench ;
| gpl-3.0 | 8907d8d589496f8b01378c6761feacae | 0.482507 | 3.77218 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00183.vhd | 1 | 44,638 | -- NEED RESULT: ARCH00183.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00183: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00183
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00183
-- PKG00183/BODY
-- ENT00183(ARCH00183)
-- ENT00183_Test_Bench(ARCH00183_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00183 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00183 ;
--
package body PKG00183 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00183 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00183.all ;
entity ENT00183 is
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00183 ;
--
architecture ARCH00183 of ENT00183 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00183" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00183 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00183.all ;
entity ENT00183_Test_Bench is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
end ENT00183_Test_Bench ;
--
architecture ARCH00183_Test_Bench of ENT00183_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00183 ( ARCH00183 ) ;
begin
CIS1 : UUT
port map (
s_r_st_arr1_vector
, s_r_st_arr2_vector
, s_r_st_arr3_vector
, s_r_st_rec1_vector
, s_r_st_rec2_vector
, s_r_st_rec3_vector
) ;
end block L1 ;
end ARCH00183_Test_Bench ;
| gpl-3.0 | 6bb635e75bc36fe33d7fa37d2d459850 | 0.479748 | 3.377573 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00142.vhd | 1 | 21,614 | -- NEED RESULT: ARCH00142.P1: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142.P2: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142.P3: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00142: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00142
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00142(ARCH00142)
-- ENT00142_Test_Bench(ARCH00142_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00142 is
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_arr1 : inout st_arr1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 100 ns;
--
when 5 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_1 (st_arr1'Right) after 40 ns;
--
when 7 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_arr2 : inout st_arr2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_arr3 : inout st_arr3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00142" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00142 ;
--
architecture ARCH00142 of ENT00142 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1,
counter,
correct,
savtime,
chk_st_arr1
) ;
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_arr2,
counter,
correct,
savtime,
chk_st_arr2
) ;
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_arr3,
counter,
correct,
savtime,
chk_st_arr3
) ;
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00142 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00142_Test_Bench is
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00142_Test_Bench ;
--
architecture ARCH00142_Test_Bench of ENT00142_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00142 ( ARCH00142 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00142_Test_Bench ;
| gpl-3.0 | 2d5f72bb63de0f951b0e17a951732471 | 0.467336 | 3.556104 | false | false | false | false |
dcliche/mdsynth | rtl/src/char_rom2k_b16.vhd | 1 | 8,631 | --===========================================================================--
-- --
-- Synthesizable Character Generator using Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : char_rom2k_b16.vhd
--
-- Entity name : char_rom
--
-- Purpose : Implements a character generator ROM
-- using one Xilinx RAMB16_S9 Block RAM
-- Used by vdu8.vhd in the System09 SoC
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
--
-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Characters are 7 pixels x 11 rows x 128 characters
-- Stored as 8 bits x 16 locations x 128 characters
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2004-10-18 John Kent Initial relaease
--
-- 0.2 2010-06-17 John Kent Updated header and description and added GPL
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
entity char_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end char_rom;
architecture rtl of char_rom is
signal we : std_logic;
signal dp : std_logic;
begin
ROM : RAMB16_S9
generic map (
INIT_00 => x"0000000009090F09090038043840380000000000070404040400444C54644400",
INIT_01 => x"00000000110A040A110078407040780000000000110A040A1100380438403800",
INIT_02 => x"000000000D1215110E0078407040780000000000040404041F00784070407800",
INIT_03 => x"000000000F080808080070487048700000000000090A0C0A0900487848483000",
INIT_04 => x"00000000040404041F0044447C444400000000000E010E100E00704870487000",
INIT_05 => x"00000000040404041F001028444444000000000010101E101F007C4040404000",
INIT_06 => x"0000000011111E111E003C4040403C000000000008080E080F00404070407800",
INIT_07 => x"00000000070202020700380438403800000000000E1111110E00380438403800",
INIT_08 => x"00000000070202060200704848487000000000000F080E080F00704848487000",
INIT_09 => x"000000000E0107020F00704848487000000000000F0806090700704848487000",
INIT_0a => x"00000000090A0C0A0900444C546444000000000001010F090900704848487000",
INIT_0b => x"000000000E090E090E0078407040780000000000111315191100380438403800",
INIT_0c => x"000000001111151B110078407040780000000000111315191100384040403800",
INIT_0d => x"000000000E1010100E00784070407800000000000E090E090E00380438403800",
INIT_0e => x"000000000E010E100E00384858403800000000000E010E100E00404070407800",
INIT_0f => x"000000000E010E100E00304848484800000000000E010E100E00485070487000",
INIT_10 => x"0000000008080000080808080808080000000000000000000000000000000000",
INIT_11 => x"000000002424247E2424247E2424240000000000000000000000001212121200",
INIT_12 => x"0000000043434020100804020161610000000000083E4909093E4848493E0800",
INIT_13 => x"00000000000000000000002010080C00000000003D4244444438444444443800",
INIT_14 => x"0000000020100804040404040810200000000000020408101010101008040200",
INIT_15 => x"0000000000000808087F0808080000000000000000004122147F142241000000",
INIT_16 => x"0000000000000000007F00000000000000402010181800000000000000000000",
INIT_17 => x"0000000040404020100804020101010000000000181800000000000000000000",
INIT_18 => x"000000003E080808080808082818080000000000081422414141414122140800",
INIT_19 => x"000000003E410101010E010101413E00000000007F4020100804020141423C00",
INIT_1a => x"000000003E410101615E404040407F000000000002020202027F22120A060200",
INIT_1b => x"00000000404020100804020101017F00000000001E214141615E404040211E00",
INIT_1c => x"000000003C420101013D434141423C00000000003E414141413E414141413E00",
INIT_1d => x"0000402010181818000000181818000000000000001818180000001818180000",
INIT_1e => x"00000000000000007F00007F0000000000000000010204081020100804020100",
INIT_1f => x"00000000080800080808060101413E0000000000402010080402040810204000",
INIT_20 => x"0000000041414141417F414122140800000000001C224140404E494541221C00",
INIT_21 => x"000000001E2141404040404041211E00000000007E212121213E212121217E00",
INIT_22 => x"000000007F404040407C404040407F00000000007C2221212121212121227C00",
INIT_23 => x"000000001E2141414147404040211E000000000040404040407C404040407F00",
INIT_24 => x"000000003E0808080808080808083E000000000041414141417F414141414100",
INIT_25 => x"00000000414244485060504844424100000000003C4202020202020202020700",
INIT_26 => x"00000000414141414141494955634100000000007F4040404040404040404000",
INIT_27 => x"000000003E4141414141414141413E0000000000414141434549495161414100",
INIT_28 => x"000000003D4245494141414141413E000000000040404040407E414141417E00",
INIT_29 => x"000000003E410101013E404040413E000000000041424448507E414141417E00",
INIT_2a => x"000000003E414141414141414141410000000000080808080808080808087F00",
INIT_2b => x"0000000022225555494941414141410000000000080814141422222241414100",
INIT_2c => x"0000000008080808080814224141410000000000414141221408142241414100",
INIT_2d => x"000000001E1010101010101010101E00000000007F4040201008040201017F00",
INIT_2e => x"000000003C0404040404040404043C0000000000010101020408102040404000",
INIT_2f => x"000000007F000000000000000000000000000000000000000000004122140800",
INIT_30 => x"000000003F41413F01013E000000000000000000000000000000000204081800",
INIT_31 => x"000000001E21404040211E0000000000000000005E61616141615E4040404000",
INIT_32 => x"000000003E40407F41413E0000000000000000003D43414141433D0101010100",
INIT_33 => x"003C4202023E424242423D0100000000000000001010101010107C1010110E00",
INIT_34 => x"000000003E0808080808180000080800000000004141414141615E4040404000",
INIT_35 => x"00000000414448704844414040404000003C4202020202020202020000020200",
INIT_36 => x"00000000414141494955220000000000000000001C0808080808080808081800",
INIT_37 => x"000000003E41414141413E0000000000000000004141414141615E0000000000",
INIT_38 => x"00010101013D434343433D000000000000404040405E616161615E0000000000",
INIT_39 => x"000000003E01013E40403E0000000000000000002020202020314E0000000000",
INIT_3a => x"000000003D4242424242420000000000000000000C12101010107C1010101000",
INIT_3b => x"0000000022554949414141000000000000000000081414222241410000000000",
INIT_3c => x"003C4202023A4642424242000000000000000000412214081422410000000000",
INIT_3d => x"00000000070808081020100808080700000000007F20100804027F0000000000",
INIT_3e => x"0000000070080808040204080808700000000000080808080800080808080800",
INIT_3f => x"0000000049224922492249224922490000000000000000000000000046493100"
)
port map (
do => data_out,
dop(0)=> dp,
addr => addr,
clk => clk,
di => data_in,
dip(0)=> dp,
en => cs,
ssr => rst,
we => we
);
my_char_rom : process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
| gpl-3.0 | cc8b167951158349c2f32ddb9d521467 | 0.705712 | 3.780552 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00214.vhd | 1 | 5,804 | -- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00214: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00214
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00214(ARCH00214)
-- ENT00214_Test_Bench(ARCH00214_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00214 is
generic (G : integer) ;
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00214 ;
--
--
architecture ARCH00214 of ENT00214 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(2)(2) <= transport
c_st_arr1_vector_2(2)(2) after 10 ns ;
wait until s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) ;
Test_Report (
"ENT00214",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) )) ;
--
when 1
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(G)(G) <= transport
c_st_arr1_vector_2(G)(G) after 10 ns ;
wait until s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) ;
Test_Report (
"ENT00214",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) )) ;
--
when 2
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(CG)(CG) <= transport
c_st_arr1_vector_2(CG)(CG) after 10 ns ;
wait until s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) ;
Test_Report (
"ENT00214",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) )) ;
--
when 3
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(CG'Attr)(CG'Attr) <= transport
c_st_arr1_vector_2(CG'Attr)(CG'Attr) after 10 ns ;
wait until s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) ;
Test_Report (
"ENT00214",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_arr1_vector
, counter
, correct
, savtime
, chk_st_arr1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_arr1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00214 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00214_Test_Bench is
end ENT00214_Test_Bench ;
--
--
architecture ARCH00214_Test_Bench of ENT00214_Test_Bench is
begin
L1:
block
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00214 ( ARCH00214 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00214_Test_Bench ;
| gpl-3.0 | d64b601263829b8d48e0d7488580bd37 | 0.490696 | 3.418139 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00289.vhd | 1 | 7,235 | -- NEED RESULT: ARCH00289: Logical operators are correctly predefined for boolean array types passed
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for bit array types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00289
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (2)
-- 7.2.1 (9)
-- 7.2.1 (10)
-- 7.2.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00289(ARCH00289)
-- ENT00289_Test_Bench(ARCH00289_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00289 is
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 : out boolean ;
dynamic_correct_1, dynamic_correct_2 : out boolean ) ;
end ENT00289 ;
architecture ARCH00289 of ENT00289 is
signal sbit1, sbit2 : st_bit_vector := B"10100" ;
signal sboolean1, sboolean2 : st_boolean_vector ;
constant answer : boolean := true ;
begin
sbit2 <= B"01011" ;
sboolean1 <= (true, false, true, false, false);
sboolean2 <= (false, true, false, true, true);
-- bit vector
g1: if (((bit1 and bit1) = B"10100") and
((bit1 and bit2) = B"00000") and
((bit2 and bit1) = B"00000") and
((bit2 and bit2) = B"01011") and
((bit1 or bit1) = B"10100") and
((bit1 or bit2) = B"11111") and
((bit2 or bit1) = B"11111") and
((bit2 or bit2) = B"01011") and
((bit1 nand bit1) = B"01011") and
((bit1 nand bit2) = B"11111") and
((bit2 nand bit1) = B"11111") and
((bit2 nand bit2) = B"10100") and
((bit1 nor bit1) = B"01011") and
((bit1 nor bit2) = B"00000") and
((bit2 nor bit1) = B"00000") and
((bit2 nor bit2) = B"10100") and
((bit1 xor bit1) = B"00000") and
((bit1 xor bit2) = B"11111") and
((bit2 xor bit1) = B"11111") and
((bit2 xor bit2) = B"00000") and
((not bit1) = bit2) and
((not bit2) = bit1) ) generate
process ( sbit2 )
variable bool : boolean ;
begin
if sbit2 = B"01011" then
locally_static_correct_1 <= true ;
dynamic_correct_1 <=
((sbit1 and sbit1) = B"10100") and
((sbit1 and sbit2) = B"00000") and
((sbit2 and sbit1) = B"00000") and
((sbit2 and sbit2) = B"01011") and
((sbit1 or sbit1) = B"10100") and
((sbit1 or sbit2) = B"11111") and
((sbit2 or sbit1) = B"11111") and
((sbit2 or sbit2) = B"01011") and
((sbit1 nand sbit1) = B"01011") and
((sbit1 nand sbit2) = B"11111") and
((sbit2 nand sbit1) = B"11111") and
((sbit2 nand sbit2) = B"10100") and
((sbit1 nor sbit1) = B"01011") and
((sbit1 nor sbit2) = B"00000") and
((sbit2 nor sbit1) = B"00000") and
((sbit2 nor sbit2) = B"10100") and
((sbit1 xor sbit1) = B"00000") and
((sbit1 xor sbit2) = B"11111") and
((sbit2 xor sbit1) = B"11111") and
((sbit2 xor sbit2) = B"00000") and
((not sbit1) = sbit2) and
((not sbit2) = sbit1) ;
end if ;
end process ;
end generate ;
-- boolean vector
process ( sboolean2 )
variable bool : boolean ;
variable true_vector, false_vector : st_boolean_vector ;
begin
true_vector := (true, true, true, true, true);
false_vector :=(false, false, false, false, false);
if sboolean2 = (false, true, false, true, true) then
locally_static_correct_2 <= true ;
bool := (sboolean1 and sboolean1) = sboolean1 and
(sboolean1 and sboolean2) = false_vector and
(sboolean2 and sboolean1) = false_vector and
(sboolean2 and sboolean2) = sboolean2 and
(sboolean1 or sboolean1) = sboolean1 and
(sboolean1 or sboolean2) = true_vector ;
bool := bool and
(sboolean2 or sboolean1) = true_vector and
(sboolean2 or sboolean2) = sboolean2 and
(sboolean1 nand sboolean1) = sboolean2 and
(sboolean1 nand sboolean2) = true_vector and
(sboolean2 nand sboolean1) = true_vector and
(sboolean2 nand sboolean2) = sboolean1 ;
bool := bool and
(sboolean1 nor sboolean1) = sboolean2 and
(sboolean1 nor sboolean2) = false_vector and
(sboolean2 nor sboolean1) = false_vector and
(sboolean2 nor sboolean2) = sboolean1 and
(sboolean1 xor sboolean1) = false_vector ;
bool := bool and
(sboolean1 xor sboolean2) = true_vector and
(sboolean2 xor sboolean1) = true_vector and
(sboolean2 xor sboolean2) = false_vector and
((not sboolean1) = sboolean2) and
((not sboolean2) = sboolean1) ;
dynamic_correct_2 <= bool ;
end if ;
end process ;
end ARCH00289 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00289_Test_Bench is
end ENT00289_Test_Bench ;
architecture ARCH00289_Test_Bench of ENT00289_Test_Bench is
begin
L1:
block
signal locally_static_correct_1, dynamic_correct_1 : boolean := false ;
signal locally_static_correct_2, dynamic_correct_2 : boolean := false ;
constant local_c_st_bit_vector_1 : st_bit_vector := B"10100";
constant local_c_st_bit_vector_2 : st_bit_vector := B"01011";
component UUT
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 :
out boolean := false ;
dynamic_correct_1, dynamic_correct_2 : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00289 ( ARCH00289 ) ;
begin
CIS1 : UUT
generic map ( local_c_st_bit_vector_1, local_c_st_bit_vector_2,
c_boolean_1, c_boolean_2 )
port map ( locally_static_correct_1,
locally_static_correct_2 ,
dynamic_correct_1 ,
dynamic_correct_2 ) ;
process ( locally_static_correct_1, locally_static_correct_2,
dynamic_correct_1, dynamic_correct_2 )
begin
if locally_static_correct_1 and dynamic_correct_1 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for boolean array types" ,
true ) ;
end if ;
if locally_static_correct_2 and dynamic_correct_2 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for bit array types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00289_Test_Bench ;
| gpl-3.0 | c6fe5b0e37fab07c5902293af6c9ebcb | 0.54264 | 3.480038 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00630.vhd | 1 | 5,940 | -- NEED RESULT: ARCH00630: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00630.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00630: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00630: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00630: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00630
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00630(ARCH00630)
-- ENT00630_Test_Bench(ARCH00630_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00630 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00630 ;
--
--
architecture ARCH00630 of ENT00630 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
procedure P1
(signal s_st_rec3 : in st_rec3 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00630" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00630.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00630" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00630" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00630" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00630" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec3_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_rec3 ,
st_rec3_select ,
s_st_rec3_savt ,
chk_st_rec3 ,
s_st_rec3_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f2.f2 <= transport
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2.f2 after 5 ns when 3 ;
--
end ARCH00630 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00630_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00630_Test_Bench ;
--
--
architecture ARCH00630_Test_Bench of ENT00630_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00630 ( ARCH00630 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00630_Test_Bench ;
| gpl-3.0 | 4d0a26083b8f07ef5b7054f2dc943515 | 0.491414 | 3.312883 | false | true | false | false |
jairov4/accel-oil | solution_kintex7/impl/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 88,720 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg676-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.350000,HLS_SYN_LAT=129178013,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_316 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_321 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_240_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_326 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_330 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_336 : STD_LOGIC_VECTOR (31 downto 0);
signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_341 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC;
signal grp_fu_252_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_345 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_tmp_14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_211_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_178 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_178_ap_start,
ap_done => grp_nfa_accept_sample_fu_178_ap_done,
ap_idle => grp_nfa_accept_sample_fu_178_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_178_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_178_sample_address,
sample_datain => grp_nfa_accept_sample_fu_178_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_178_sample_size,
tmp_14 => grp_nfa_accept_sample_fu_178_tmp_14,
length_r => grp_nfa_accept_sample_fu_178_length_r,
ap_return => grp_nfa_accept_sample_fu_178_ap_return);
grp_sample_iterator_get_offset_fu_194 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_194_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_194_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_194_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_194_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_194_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_194_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_194_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_194_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_194_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_194_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_194_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_194_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_194_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_194_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_194_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_194_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_194_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_194_i_index,
i_sample => grp_sample_iterator_get_offset_fu_194_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_194_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_194_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_194_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_194_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_194_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_194_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_194_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_194_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_194_ap_return);
grp_sample_iterator_next_fu_211 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_211_ap_start,
ap_done => grp_sample_iterator_next_fu_211_ap_done,
ap_idle => grp_sample_iterator_next_fu_211_ap_idle,
ap_ready => grp_sample_iterator_next_fu_211_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_211_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_211_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_211_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_211_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_211_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_211_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_211_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_211_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_211_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_211_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_211_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_211_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_211_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_211_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_211_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_211_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_211_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_211_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_211_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_211_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_211_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_211_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_211_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_211_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_211_indices_stride_size,
i_index => grp_sample_iterator_next_fu_211_i_index,
i_sample => grp_sample_iterator_next_fu_211_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_211_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_211_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_252_p0,
din1 => grp_fu_252_p1,
ce => grp_fu_252_ce,
dout => grp_fu_252_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_240_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_194_ap_ready)) then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st30_fsm_29 = ap_NS_fsm) and ((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_211_ap_ready)) then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_94 assign process. --
c_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and (or_cond_reg_341 = ap_const_lv1_0))) then
c_fu_94 <= c_1_reg_345;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_94 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_146 assign process. --
i_index_reg_146_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
i_index_reg_146 <= grp_sample_iterator_next_fu_211_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_146 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_156 assign process. --
i_sample_reg_156_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
i_sample_reg_156 <= grp_sample_iterator_next_fu_211_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_156 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_166 assign process. --
p_0_reg_166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
p_0_reg_166 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_326 = ap_const_lv1_0)))) then
p_0_reg_166 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st29_fsm_28 = ap_CS_fsm)) then
c_1_reg_345 <= grp_fu_252_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_330 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
offset_reg_336 <= grp_sample_iterator_get_offset_fu_194_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then
or_cond_reg_341 <= or_cond_fu_247_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_321 <= tmp_i_10_fu_235_p2;
tmp_i_reg_316 <= tmp_i_fu_230_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_326 <= tmp_i_11_fu_240_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , tmp_i_11_reg_326 , or_cond_fu_247_p2 , grp_nfa_accept_sample_fu_178_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_326 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
if ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((or_cond_fu_247_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_166;
-- grp_fu_252_ce assign process. --
grp_fu_252_ce_assign_proc : process(ap_CS_fsm, stop_on_first_read_read_fu_104_p2, or_cond_fu_247_p2, grp_nfa_accept_sample_fu_178_ap_done)
begin
if (((ap_ST_st29_fsm_28 = ap_CS_fsm) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0)) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm))) then
grp_fu_252_ce <= ap_const_logic_1;
else
grp_fu_252_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_252_p0 <= c_load_reg_330;
grp_fu_252_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_178_length_r <= sample_length;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_nfa_accept_sample_fu_178_tmp_14 <= offset_reg_336;
grp_sample_iterator_get_offset_fu_194_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_194_ap_start <= grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_194_i_index <= i_index_reg_146;
grp_sample_iterator_get_offset_fu_194_i_sample <= i_sample_reg_156;
grp_sample_iterator_get_offset_fu_194_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_194_sample_length <= sample_length;
grp_sample_iterator_next_fu_211_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_211_ap_start <= grp_sample_iterator_next_fu_211_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_211_i_index <= i_index_reg_146;
grp_sample_iterator_next_fu_211_i_sample <= i_sample_reg_156;
grp_sample_iterator_next_fu_211_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_211_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_211_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_211_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_211_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_211_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_address, grp_sample_iterator_next_fu_211_indices_begin_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_211_indices_begin_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_194_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, grp_sample_iterator_next_fu_211_indices_begin_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_211_indices_begin_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_194_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, grp_sample_iterator_next_fu_211_indices_begin_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_211_indices_begin_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, grp_sample_iterator_next_fu_211_indices_begin_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_211_indices_begin_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, grp_sample_iterator_next_fu_211_indices_begin_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_211_indices_begin_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_size, grp_sample_iterator_next_fu_211_indices_begin_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_211_indices_begin_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_194_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_address, grp_sample_iterator_next_fu_211_indices_samples_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_211_indices_samples_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_194_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, grp_sample_iterator_next_fu_211_indices_samples_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_211_indices_samples_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_194_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, grp_sample_iterator_next_fu_211_indices_samples_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_211_indices_samples_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, grp_sample_iterator_next_fu_211_indices_samples_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_211_indices_samples_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, grp_sample_iterator_next_fu_211_indices_samples_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_211_indices_samples_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_size, grp_sample_iterator_next_fu_211_indices_samples_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_211_indices_samples_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_194_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_address, grp_sample_iterator_next_fu_211_indices_stride_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_211_indices_stride_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_194_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, grp_sample_iterator_next_fu_211_indices_stride_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_211_indices_stride_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_194_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, grp_sample_iterator_next_fu_211_indices_stride_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_211_indices_stride_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, grp_sample_iterator_next_fu_211_indices_stride_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_211_indices_stride_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, grp_sample_iterator_next_fu_211_indices_stride_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_211_indices_stride_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_size, grp_sample_iterator_next_fu_211_indices_stride_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_211_indices_stride_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_194_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size;
or_cond_fu_247_p2 <= (grp_nfa_accept_sample_fu_178_ap_return xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size;
stop_on_first_read_read_fu_104_p2 <= stop_on_first;
tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0";
tmp_i_11_fu_240_p2 <= (tmp_i_reg_316 and tmp_i_10_reg_321);
tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0";
end behav;
| lgpl-3.0 | d6e1169477b02f232b110dc9cd2645f6 | 0.642752 | 2.622292 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00221.vhd | 1 | 5,295 | -- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00221
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00221(ARCH00221)
-- ENT00221_Test_Bench(ARCH00221_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00221 is
generic (G : integer) ;
port (
s_st_rec3_vector : inout st_rec3_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00221 ;
--
--
architecture ARCH00221 of ENT00221 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(2).f2 <= transport
c_st_rec3_vector_2(2).f2 after 10 ns ;
wait until s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 )) ;
--
when 1
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(G).f2 <= transport
c_st_rec3_vector_2(G).f2 after 10 ns ;
wait until s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 )) ;
--
when 2
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(CG).f2 <= transport
c_st_rec3_vector_2(CG).f2 after 10 ns ;
wait until s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 )) ;
--
when 3
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(CG'Attr).f2 <= transport
c_st_rec3_vector_2(CG'Attr).f2 after 10 ns ;
wait until s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00221 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00221_Test_Bench is
end ENT00221_Test_Bench ;
--
--
architecture ARCH00221_Test_Bench of ENT00221_Test_Bench is
begin
L1:
block
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00221 ( ARCH00221 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3_vector
)
;
end block L1 ;
end ARCH00221_Test_Bench ;
| gpl-3.0 | 75ef78d420611fedd5788145be974728 | 0.493484 | 3.366179 | false | true | false | false |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_finals_buckets_if_ap_fifo_af.vhd | 2 | 6,292 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_af is
component nfa_finals_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_finals_buckets_if_ap_fifo_af_ram : nfa_finals_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
| lgpl-3.0 | 12566070876c114194ba4af9e2d427df | 0.51637 | 3.589276 | false | false | false | false |
dcliche/mdsynth | rtl/src/keyboard.vhd | 1 | 8,329 | --===========================================================================--
-- --
-- keyboard.vhd - Synthesizable Interface to PS/2 Keyboard Module --
-- --
--===========================================================================--
--
-- File name : keyboard.vhd
--
-- Entity name : keyboard
--
-- Purpose : Implements a CPU interface to John Clayton's PS/2 Keyboard
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
--
-- Uses : ps2_keyboard_interface
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Registers :
--
-- IO address + 0 read - Status Register
--
-- Bit[0] - RX Data Ready
-- Bit[1] - TX Data Empty
-- Bit[2] - Extended
-- Bit[3] - Released
-- Bit[4] - Shift On
-- Bit[5] - Error (no keyboard acknowledge received)
-- Bit[6] - TX Interrupt Flag
-- Bit[7] - RX Interrupt Flag
--
-- IO address + 0 write - Control Register
--
-- Bit[0] - Undefined
-- Bit[1] - Undefined
-- Bit[2] - Undefined
-- Bit[3] - Undefined
-- Bit[4] - Undefined
-- Bit[5] - Undefined
-- Bit[6] - TX Interrupt Enable
-- Bit[7] - RX Interrupt Enable
--
-- IO address + 1 read - Receive Data Register
--
-- IO address + 1 write - Transmit Data Register
--
-- Copyright (C) 2004 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Description
-- 0.1 John Kent 2nd April 2004 Interface to John Clayton's PS2 keyboard
-- 0.2 John Kent 7th Februaury 2007 Added Generics for Keyboard Timing
-- 0.3 John Kent 30th May 2010 Updated Header, added unisim library
-- 0.4 John Kent 17th June 2010 Cleaned up signal names,
-- added TX interrupt enable
-- Modified assignment of status register
-- Revised hanshake control and input registers
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
entity keyboard is
generic (
KBD_CLK_FREQ : integer
);
port(
--
-- CPU Interface Signals
--
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
--
-- Keyboard Interface Signals
--
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end keyboard;
architecture rtl of keyboard is
constant CLK_FREQ_MHZ : integer := KBD_CLK_FREQ / 1000000;
signal kbd_status : std_logic_vector(7 downto 0);
signal kbd_control : std_logic_vector(7 downto 0);
signal kbd_rx_data : std_logic_vector(7 downto 0);
signal kbd_tx_data : std_logic_vector(7 downto 0);
signal kbd_read : std_logic;
signal kbd_write : std_logic;
signal kbd_data_ready : std_logic; -- => kbd_status(0)
signal kbd_data_empty : std_logic; -- => kbd_status(1)
signal kbd_extended : std_logic; -- => kbd_status(2)
signal kbd_released : std_logic; -- => kbd_status(3)
signal kbd_shift_on : std_logic; -- => kbd_status(4)
signal kbd_error : std_logic; -- => kbd_status(5) (No receive acknowledge)
component ps2_keyboard
generic (
CLK_FREQ_MHZ : integer := CLK_FREQ_MHZ
);
port(
clk : in std_logic;
reset : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_read : in std_logic;
rx_data_ready : out std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_on : out std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_data_empty : out std_logic;
tx_error : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end component;
begin
my_ps2_keyboard : ps2_keyboard
generic map (
CLK_FREQ_MHZ => CLK_FREQ_MHz
)
port map(
clk => clk,
reset => rst,
rx_data => kbd_rx_data,
rx_read => kbd_read,
rx_data_ready => kbd_data_ready,
rx_extended => kbd_extended,
rx_released => kbd_released,
rx_shift_on => kbd_shift_on,
tx_data => kbd_tx_data,
tx_write => kbd_write,
tx_data_empty => kbd_data_empty,
tx_error => kbd_error,
ps2_clk => kbd_clk,
ps2_data => kbd_data
);
--
-- Keyboard Read strobe
--
keyboard_read : process( clk, rst, cs, rw, kbd_data_ready )
begin
if rst = '1' then
kbd_read <= '0';
elsif( clk'event and clk='0' ) then
if( cs = '1' and addr = '1' and rw = '1' ) then
kbd_read <= '1';
elsif kbd_data_ready = '1' then
kbd_read <= '0';
end if;
end if;
end process;
--
-- Keyboard Write strobe
--
keyboard_write : process( clk, rst, cs, rw, addr,
kbd_write, kbd_data_empty )
begin
if rst = '1' then
kbd_write <= '0';
elsif( clk'event and clk='0' ) then
if( cs = '1' and addr = '1' and rw = '0' ) then
kbd_write <= '1';
elsif kbd_data_empty = '1' then
kbd_write <= '0';
end if;
end if;
end process;
--
-- Keyboard register input
--
keyboard_in : process( clk, rst, cs, rw, addr, data_in, kbd_rx_data )
begin
if rst = '1' then
kbd_control <= (others => '0');
kbd_tx_data <= (others => '0');
elsif( clk'event and clk='0' ) then
if( cs = '1' and rw = '0' ) then
if addr = '0' then
kbd_control <= data_in;
else
kbd_tx_data <= data_in;
end if;
end if;
end if;
end process;
--
-- Keyboard register output
--
keyboard_out : process( addr, kbd_rx_data, kbd_status )
begin
if( addr = '0' ) then
data_out <= kbd_status;
else
data_out <= kbd_rx_data;
end if;
end process;
--
-- Assign Keyboard Status bits
--
keyboard_status : process( kbd_data_ready, kbd_data_empty,
kbd_extended, kbd_released, kbd_shift_on, kbd_error,
kbd_control, kbd_status )
begin
kbd_status(0) <= kbd_data_ready;
kbd_status(1) <= kbd_data_empty;
kbd_status(2) <= kbd_extended;
kbd_status(3) <= kbd_released;
kbd_status(4) <= kbd_shift_on;
kbd_status(5) <= kbd_error;
kbd_status(6) <= kbd_control(6) and kbd_data_empty; -- TX Interrupt Flag
kbd_status(7) <= kbd_control(7) and kbd_data_ready; -- RX Interrupt Flag
irq <= kbd_status(7) or kbd_status(6);
end process;
end rtl;
| gpl-3.0 | 544162ac7ce6aa78a84e0080d35d6ff4 | 0.511946 | 3.613449 | false | false | false | false |
dcliche/mdsynth | rtl/src/sound/sound.vhd | 1 | 11,559 | -- MDSynth Sound Chip
--
-- Copyright (c) 2012-2022, Daniel Cliche
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Write:
--
-- Base + 0: bits 2 downto 0: Waveform (0x00: DAC direct, 0x01: Square, 0x02: Sawtooth, 0x03: Sine, 0x04: Phase Modulation, 0x05: Noise)
-- bit 7: Note ON/OFF (0: OFF, 1: ON)
-- Base + 1: Pitch Hi (see below)
-- Base + 2: Pitch Low (see below)
-- Base + 3: Carrier Octave (4-bit, PM only)
-- Base + 4: bits 5 downto 0: Message Gain (6-bit, sine and PM only)
-- bits 7 downto 6: Waveform Message (0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0))
-- Base + 5: bits 5 downto 0: Modulated Gain (6-bit, PM only)
-- bits 7 downto 6: Waveform Modulated (0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0))
-- Base + 6: DAC value (8-bit, DAC-direct only)
-- Base + 7: bits 3 downto 0: Attack Rate (0xF: fastest)
-- bits 7 downto 4: Release Rate (0xF: fastest)
--
-- Read:
-- Base + 0: bits 1 downto 0: Envelope Phase (0x0: Idle, 0x1: Attack, 0x2: Sustain, 0x3: Release)
--
-- The pitch is a 16-bit value with the following format:
-- bits 15 downto 12: octave (A4 is octave 5)
-- bits 11 downto 0: phase_delta (see below)
--
-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
-- phase_delta = freq * 2^32 / (50E6 * 2^octave)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sound is
port (
clk : in std_logic;
clk_50 : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(5 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
audio_out : out std_logic
);
end;
architecture sound_arch of sound is
constant nb_voices : integer := 4;
component channel is
port ( clk: in std_logic;
reset: in std_logic;
waveform: in std_logic_vector(2 downto 0); -- 0: DAC direct, 1: Square (message only), 2: Sawtooth (message only), 3: Sine (message only), 4: Phase Modulation, 5: Noise
note_on: in std_logic;
gain_message: in unsigned(5 downto 0);
gain_modulated: in unsigned(5 downto 0);
phase_delta: in unsigned(11 downto 0);
octave_message: in unsigned(3 downto 0);
octave_carrier: in unsigned(3 downto 0);
waveform_message: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
waveform_modulated: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
attack_rate: in unsigned(3 downto 0);
release_rate: in unsigned(3 downto 0);
reset_phase: in std_logic;
dac_direct_value: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
envelope_phase: out std_logic_vector(1 downto 0));
end component;
component dac is
port ( clk: in std_logic;
dac_in: in std_logic_vector(9 downto 0);
reset: in std_logic;
dac_out: out std_logic);
end component;
type voices_waveform_type is array (0 to nb_voices) of std_logic_vector(2 downto 0);
signal voices_waveform : voices_waveform_type;
type voices_pitch_type is array (0 to nb_voices) of unsigned(15 downto 0);
signal voices_pitch: voices_pitch_type;
type voices_phase_delta_type is array (0 to nb_voices) of unsigned(11 downto 0);
signal voices_phase_delta: voices_phase_delta_type;
type voices_octave_type is array (0 to nb_voices) of unsigned(3 downto 0);
signal voices_octave_message: voices_octave_type;
signal voices_octave_carrier: voices_octave_type;
type voices_gain_type is array (0 to nb_voices) of unsigned(5 downto 0);
signal voices_gain_message: voices_gain_type := (others => to_unsigned(63, 6));
signal voices_gain_modulated: voices_gain_type := (others => to_unsigned(63, 6));
type voices_op_waveform_type is array (0 to nb_voices) of std_logic_vector(1 downto 0);
signal voices_waveform_message: voices_op_waveform_type := (others => "00");
signal voices_waveform_modulated: voices_op_waveform_type := (others => "00");
signal voices_reset_phase: std_logic_vector(0 to nb_voices) := (others => '0');
type voices_note_on_type is array (0 to nb_voices) of std_logic;
signal voices_note_on: voices_note_on_type := (others => '0');
type voices_dac_direct_value_type is array (0 to nb_voices) of std_logic_vector(7 downto 0);
signal voices_dac_direct_value: voices_dac_direct_value_type := (others => (others => '0'));
type voices_rate_type is array (0 to nb_voices) of unsigned(3 downto 0);
signal voices_attack_rate: voices_rate_type := (others => to_unsigned(0, 4));
signal voices_release_rate: voices_rate_type := (others => to_unsigned(0, 4));
signal dac_in: std_logic_vector(9 downto 0);
type voices_output_type is array (0 to nb_voices) of std_logic_vector(9 downto 0);
signal voices_output: voices_output_type := (others => (others =>'0'));
type voices_envelope_phase_type is array (0 to nb_voices) of std_logic_vector(1 downto 0);
signal voices_envelope_phase: voices_envelope_phase_type := (others => (others =>'0'));
begin
dac0 : dac port map (clk => clk_50, dac_in => dac_in, reset => rst, dac_out => audio_out);
channels : for i in 0 to 3 generate
channelx : channel port map(
clk => clk_50,
reset => rst,
waveform => voices_waveform(i),
note_on => voices_note_on(i),
gain_message => voices_gain_message(i),
gain_modulated => voices_gain_modulated(i),
phase_delta => voices_phase_delta(i),
octave_message => voices_octave_message(i),
octave_carrier => voices_octave_carrier(i),
waveform_message => voices_waveform_message(i),
waveform_modulated => voices_waveform_modulated(i),
attack_rate => voices_attack_rate(i),
release_rate => voices_release_rate(i),
reset_phase => voices_reset_phase(i),
dac_direct_value => voices_dac_direct_value(i),
output => voices_output(i)(7 downto 0),
envelope_phase => voices_envelope_phase(i));
end generate channels;
process(clk_50)
begin
if clk_50'event and clk_50 = '1' then
dac_in <= std_logic_vector(unsigned(voices_output(0)) + unsigned(voices_output(1)) + unsigned(voices_output(2)) + unsigned(voices_output(3)));
end if;
end process;
process(clk)
begin
if clk'event and clk = '0' then
if rst = '1' then
voices_pitch <= (others => to_unsigned(0, 16));
voices_waveform <= (others => (others=>'0'));
voices_reset_phase <= (others=>'1');
voices_note_on <= (others=>'0');
elsif cs = '1' then
if rw = '0' then
-- write data
case addr(3 downto 0) is
when "0000" => voices_waveform(to_integer(unsigned(addr(5 downto 4)))) <= data_in(2 downto 0);
voices_note_on(to_integer(unsigned(addr(5 downto 4)))) <= data_in(7);
if (data_in(7) = '1') then
voices_reset_phase(to_integer(unsigned(addr(5 downto 4)))) <= '1';
end if;
when "0001" => voices_pitch(to_integer(unsigned(addr(5 downto 4))))(15 downto 8) <= unsigned(data_in);
when "0010" => voices_pitch(to_integer(unsigned(addr(5 downto 4))))(7 downto 0) <= unsigned(data_in);
when "0011" => voices_octave_carrier(to_integer(unsigned(addr(5 downto 4))))(3 downto 0) <= unsigned(data_in(3 downto 0));
when "0100" => voices_gain_message(to_integer(unsigned(addr(5 downto 4))))(5 downto 0) <= unsigned(data_in(5 downto 0));
voices_waveform_message(to_integer(unsigned(addr(5 downto 4)))) <= data_in(7 downto 6);
when "0101" => voices_gain_modulated(to_integer(unsigned(addr(5 downto 4))))(5 downto 0) <= unsigned(data_in(5 downto 0));
voices_waveform_modulated(to_integer(unsigned(addr(5 downto 4)))) <= data_in(7 downto 6);
when "0110" => voices_dac_direct_value(to_integer(unsigned(addr(5 downto 4)))) <= data_in;
when "0111" => voices_attack_rate(to_integer(unsigned(addr(5 downto 4)))) <= unsigned(data_in(3 downto 0));
voices_release_rate(to_integer(unsigned(addr(5 downto 4)))) <= unsigned(data_in(7 downto 4));
when others =>
end case;
end if;
else
voices_reset_phase <= (others=>'0');
end if;
voices_phase_delta(0) <= voices_pitch(0)(11 downto 0);
voices_phase_delta(1) <= voices_pitch(1)(11 downto 0);
voices_phase_delta(2) <= voices_pitch(2)(11 downto 0);
voices_phase_delta(3) <= voices_pitch(3)(11 downto 0);
voices_octave_message(0) <= voices_pitch(0)(15 downto 12);
voices_octave_message(1) <= voices_pitch(1)(15 downto 12);
voices_octave_message(2) <= voices_pitch(2)(15 downto 12);
voices_octave_message(3) <= voices_pitch(3)(15 downto 12);
end if;
end process;
process(addr, voices_envelope_phase)
begin
case addr(3 downto 0) is
when "0000" =>
data_out(1 downto 0) <= voices_envelope_phase(to_integer(unsigned(addr(5 downto 4))));
data_out(7 downto 2) <= (others=>'0');
when others =>
data_out <= (others=>'0');
end case;
end process;
end sound_arch;
| gpl-3.0 | af82bdcef9e4aa51603835de616bb272 | 0.598841 | 3.527312 | false | false | false | false |
KaskMartin/Digiloogika_ALU | ALU_FPGA/func_1.vhdl | 2 | 532 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Fun1 = A + B (aritmeetiline liitmine)
entity func1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func1;
architecture design of func1 is
signal a_sign, b_sign,o_sign: signed(3 downto 0);
begin
a_sign <= signed(a);
b_sign <= signed(b);
o_sign <= a_sign + b_sign;
o <= std_logic_vector(o_sign);
end design; | mit | 0d9f7b56c563d99e472bb2077102ef6e | 0.652256 | 2.646766 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00077.vhd | 1 | 12,604 | -- NEED RESULT: ARCH00077.P1: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077.P2: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077.P3: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00077: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00077
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00077)
-- ENT00077_Test_Bench(ARCH00077_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00077 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00077.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00077" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00077.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00077" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00077.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00077" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00077" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00077 ;
--
entity ENT00077_Test_Bench is
end ENT00077_Test_Bench ;
--
architecture ARCH00077_Test_Bench of ENT00077_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00077 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00077_Test_Bench ;
| gpl-3.0 | 0ad0e5c3096fdabae9e094527e7ba754 | 0.484291 | 3.59293 | false | true | false | false |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_generic_cstr.vhd | 9 | 120,061 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
kw3yXYLk0kP6AlPpha92siE6fvgrA/b6Gfh9b+rwrIStnZCw0gTv90KfLNjkAUjFOhNJJrEjwTJ0
AbqzoJUqwg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I+EZGbWvUb71CdDvxRbl/DqRRL0rqD0YbBjUR9ivz6ATnadNPgFQs5SFnQtoep4/VArF7VnNv5KM
LO5iM8w2eGiZQP5DByxT9pptYCwZ43thns2NdrlTZpc56tsyULWGrSW7FPeQJYgFg1apS3+4AdAN
3FLRdq1d+ljbopKCqx0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TMaqotYudCgWb42kNIyByy/25niUtv4UAAWx/bAuuvxcKn9m0G/qPlaZbVgQg/cVKP5QNfmEldA1
xoF/X51Wh124c65tgVaxs3FwIlyNbCuY/W7zMwhJHrvWNhflgd+siXJOWqNloqHTlnLq/xW1opDp
3uveAGEOWGYTcdbV3Znh/riR+TH2IivaxHCB+M/Cygo0xSx02eDnAz790k7v4eCw1hTwuZ+fM+BE
GOedM9pASNDB/l/tYJc9mS7ylTxzx5Ojy0RPiuqsk1MQcmsLRSNHt8hwUyyTsRSMvOeDEii50KKB
5zdLXGjpsc+GH/hoFzIIWD2p8c4kKOryOgQacw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gTM4DpUUylB3otsX6RmUbSV3/x8rxdjzZmfdnJhzVV/oqhyLofn5UkflAFayBi5UCUP3j+18fYB6
A29/K2m1F4By5mFPUl1H+NbNPu4EwUuBR2u3c9P84SwET+EQ9deZXRCL0B5TkfeifspVL2J28sB0
84EAkdKawzksOwvW3zU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lhX5OOoDUJqMZ9w/R+kNEwVM7u4++U27NGFwvTNE0tF346tk+EQFl2bUZboS0/Nz1y+gTzTsW3dg
2RztRxW1X7ImlV2urniAzLw8h2P+giNDBQtYnm3+R594eGPwR5uYX3pytLy2hD4M6QLxgfdCuXFG
fe1T9GpWNTjMG6fMjgyc3xKlj2aZ1PRZGpZs7J9mZP4ZTm4ST3Kid8WdHPGCWvuXkAgXLIkjsHZT
GqZoT4h23l1CucEvMZTYzjvBs5OnKwCK2bqsjzjfHq6/kQiXkqRJoBihL2OVMFu6sWuDg7yGxUVu
8Ddwo1/Se1WHeyXXi/JrMYQ6SBsTBNQzaH2Pjg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 87136)
`protect data_block
zDiQiERe+WpehFi04nLNF1egttYMJo8L1/ArlKtVPl9qOEnajw58X0Bh2M30dxSb3KamUzTEUHAc
JjK/NsIWRpNjSK3d5y+ZJ5S4qWxPan4NWqFQKR7yyzKTp8rGvospNezOhXrSP56xW7Zcr7ZMdRcH
E17qcxpTcgPvKzcvVkCkZbCWRpuHkMkn5AyvUineIGV6ptDSDhmPkBt9z+u+oLwF3XcJX96S51MM
ZHkpgFgRJswq2PrfkcrBZg8L+FfICpcX3b78cXLqNJMKWMGOGN6zHr3QInIj/MevKynPtOVSeh3B
kiYnfkq9fnPeRoS+U8atnRtmAOlGRW8fAuvTmuF9eCbAkO/R+bzIckTbspPi/4JL0jlMrlybm5z8
/GQzs4M+QFfGfDl5f3wUEKlOrqbBKITfQymreUT5+ZtQUNmxcoSAY1vtG8WLX+Ihx+hQC4Cs7xoM
aYxZuwijxdoWD+A86kZ+pMibyY3CGSOGEgJy2HsKheYxYL6nAO40pBNlffi5VBO/ZPjDSq3X9NgY
oVyESNxvS0c6kfbSwHYN+46U5MnPc+f9muT0yfBd6onervvkh1bUgH6KLmd8m9MyZ26lKSiyHCcU
BzPyDsMIVmKY687gT04QcfQhSJ20SvGvnFVJd0l3ojNRDIv3ClEH79m2tgwRSVRX/TlVWWTf7i21
QWrHmt68HFz6APIi1IMaJAJdRMePPmcdf5GrFCi4+Gjx+f7d9WvUqdlPtAQIdO+cf7CB0eaxK4xk
pvbQMJ4psvAzPE2YeaycaU3/9cRdqZ7n3RVhpfkXQzCWxK96MPelxYXMVvhpK7s+IRxPnfCcFNtT
zkNkGJmTod8OTDrujp46eDx+9Dc2M7x0v2oTLR9vOKwIs3LQnSbXuKpK+sTPhw7jYv4GYDSExDp+
4o0M3W6pOhNUXp4r+8LX9CYrzyOSarGD3J9JnxQxa+qhrwfxgaV26rUHL/eXJbQB2jvjvlg5Cq+F
6DHY7Fo28ggWbAzwxFB8iNkjhwLbYeJwMYL9LRhucdZF2gHCihEztVpCpjjY2plJMo5SNND3Blh1
cFdQCKdnetjqnUeBmxU6Tz4bh4RpIl6bO1UeGqH+o0RpdOuL0FB8GaogL9x6KgUPZEekDyx16Fh3
rJ99mSsM3HGIoZt58pFqvnO9VuptLqlYhrZ8Tt0OKZJ1QbJuioyLbFiCZiYh6DPtzYD8o30Uu3y4
lsZpKgr7r0PQCngAFmSgiGo72uKToIjRDETAYZl47bQwLNEqFGfT5yiAd9pjmrtZ2HlCIrpCmQ3E
gkeNBmULUjZlZrNyGvidFWHVJ6JndAwyrEFArBs+JWbem4KDJzYrtzSFcsvbYRaliuNz9AKgciPK
SjsL+sCqPikIvdOh6wqPCNFh0A04Cf3yJBSg++/kHk7cS9qyJgfJ4oS0G5qVwfiw2VqjR9E6SBt/
bSRjvUi0BZFVCb5/V1hon3PnWupJ3tLciaIo7Jm+jNqSQkc+pFEQ26d+yf8MLv8oOv3vSGTuGYvv
s/ZN9BumMKHfNpLfmSPnPDXkViowlei8Le5qAvphkzlRqqGL3BfRO0wmyezHiuBDBM7e8a2N5XDS
7IEONPOvMeYx9Ii/1LHv2kQd9W46Sy0EGfY6uN4zYxjNREjDr/Feq8Qppc4Vqc9XnWVE3fcdLoCX
sNYmWBLqWCMXel6LtftXnqSClV79sALPkVNLlNm8fBOK1ulk+d4ey+S4skb+qhqmV7cx7bK+qp8K
MUr9CsgE1KhHizIuzZo4Qd8oMez1PO329OBWxaRFW2RL2WVLYVe73ssV+YowisFtKfqXSr+CwCrt
/BeutDxkNy/7NymCulZ1UswlBT3LR9TjovRGc6Xuk01YWQz5enD3i0BZOJpsrfd36w4+3fNhNpi9
fWrQYaSnawu+gRkTYd4I1hdKxNCj3fGw1NpPN0I+zC7tN6eKkHEfzMBObbwaQk6tr4RDrHbf52pM
PHRxOsMD0N+xjVXUs7w/R9rIMkYbpEJ2gkZ3VU9VMjyIGviaY0grkobH8tXASBxZTyBs3O4dbYMa
OLYVAYxstJF0EFq5IT6+gYSAKgQZFgMzQreU8yvcAWbwe31h9gQpitUWQcSuXrUIbJo5Ai15wRxR
CvLyyz9xnO9auQB6Lvrclx0M+5IufRUU5avV+L+Fv4BXJ4t4GKaL9ajTYfcQ40vItH54rBmmq6yV
AJ1Th1vopKs4VLeBBFsRK92NKFncuKyn6bgnTIB3zaUMYeYvJ/7Yd/IjsqGU0y41NZxO/3Gh2MbW
8PYcn97c9WpIsQH9q5n08Fmb4CcAl858pZD8tt6omdf4l7kSAUekNd8gZ51g0g6/T+RVd4tvH6h1
U64smNO4TcFO3OsdA6HzRO86ZmadBYKHlyOxHlEjk7MIjcMHjxEhOLySOS/t0wVgvUvarCPiCQl2
Vj5NMipp+VR3NYv6YiIHL8b/mtSUw/ayrP+Xryi+lXGc4Q7szxZDhkuGB2sdms1PD3NuqyANl8kB
vcO7W3YGt6eBxN5gVWqhZAqnx9/D62PzQmZT40VK/HSY7v2545xFUSyaXvjeDyCk38wyDMz+uzrv
Z2ArFsC9hDZsbGQGpMn3+FOrLMbuchjCERpdrJO1ycmYlpXjNvE9a1j8mZMx38G6SMi7Aycx6TxG
Zgl8QL+3XCOJyKjsqnTb18btTAQ2VAE0YlgGLaC6Ru09lZ2m/5Lta0DHbOpt/GzLlzqtcSmmIrtV
+SQI9StV2Yw12yUbsVEJv7iAwNq95PBpiPrDBnG4eRcDRC1jHN9TUHWG/909yeazQAMqP0OYx6ht
wYbI9HFVNHgcpyk729d1EiPE3qpusZUZzO081X0nZLi3Z2toPTsb5zwrZ2VZF8N1kIOoMu1YaZFf
owx6Jp9zEqQSrF029WGENhX2gyx+W4poyEuZqqrXBQF7asaLvbBUICFYiwHNQnCMb0iB7XSWCA0f
vDieYfLPPkI/uS1jm/FFVw2GxYhOZXcrkq6JOuUomEgtDKnU/CvoLxztciBV7n2sL7N7KwTDMhxB
evjK+egrSta5iy2OWODt+VQoWe9aUpbZdAP/rkQ7VPDJauGXBQxiLTQZ/hbKGYndflpyy0qxps/a
IuMkIvN74DPZmZtmLLonKCtyuL1tEiAwFgdVvpgGz2GjXxRMIRCnrHmQhlDg/fCQ40a6YJJX+/Tu
mjCGq5U2mTs6fPZEdS/fTUoOMUwvCTIA/fe+Wb/1WVpK7HNiHfbKYO2Km6B5RKkp76emx+g3y/dx
QxWR9MndcZ4vtfFDirfJm/MA9Wx1NjdYaXRO8z9EkjxK9VeWjtQ8Dj4smcOKqjrJ6/WsBZ3c36NK
agrQwqGMqdsQ4k+Xz+s3m0JOaT5yAHAKNc4Oi/FENUOoTPSjCda3J7HXlUkQaDobT266ZObKwyuV
k+2aTCJrDJzhL0ATWhqyjA4YRT1Fn5mGMLnvYXJc0xAMtuNedmifbNiPQnY7AQHuY1zE2I5CTTf2
mxmJXDq3Gt+VJ6N5xHWm0IzjGlIVKxVyxRV7Yxal03Uoui0V5QxLdr6EYYv7eh2yZpADXh5+lr4+
ECdgOts7+Xntu4O/UjoeoWrTCr25rvy8QY+Cns04y5NPMo3gb68eqmSoLKSF8nWGggSsaw8gSMev
r2pl0inaaxDzY4kCryoBcBDSlR1c1HNqkaxZZENas8ho4FxjXT95jKZSLTJsczEQSszlrUMPxT8S
7ZXZ4cFA6sCwAE0QmhmUlqSGJyKiyvAiIXw4IX1bCL7+P3gkD4AVfeHvN55X/FKsle0PO2TR7YwP
H8jjqcWxod/KQYPrMpqV4xawx05VXpUvBeP/Z83D86JH5P5BmtTLfx1fg3iEROYzv0cwOOEE4Tvb
cggnCVDPj8JZ1TIxvvrMDiGUKYJcPTi++N1EnsCkxydSRbYd9Sn8siNIFKkJVyo+w6X4AYiIVtjt
/YhtFC/zqf4y2rzt8/J2rNU1Db+31Zif3wiWtoXHn26aRXhaoOSa5dR46eH91F+cT9uLwyAewyK4
5pG1QC8xGDC8f5Vqr/1EWCSJGy/G+uLZIoWVCnWB4DzX+ZrPXWNzq9cla7Zqg5czdSJo749b4Yqv
vmyTpw16MP4O0BZb/kjTcAecL57X+lRmB8zgrLBT6ttDtoPBcF0i2qIT4oQq556GfTdYLHfXVLIp
8L3Dw3GQ6RQBRjEv8X691HCFldRRwvF4MvAX7vYkU2PshxvC0AqO09LMDgXExuIXvK1Q3qI2VAc3
v3nUe+5EztWfCEK8VMnxqSjxhVXeOyWQ/swRG3taC7oVc87HII36B7Qrc0HUcxXeiKQ/aECMbJRT
3o9Q6B2XSWSK8U9PbqHaw2sPeWmDRPppqCPUMZXwY6+kHyUAiCMh8e4ukiI6/N1XXP6ardnyqCya
YzXVQ69dehUl91Sdw5fkvxYGMfqb4anoXLCoogk7iOZghkZhs1FgKuE1J5td/Bh1149VbNzzOu+Q
3bbDuL469/bGo7UTXXDt5164G5vyJ9mTJbPa6H/aHHxv7efiDacwNYFirE1NnY13t5DZpB+CJxch
TA3WeN9kmdFEUEl3FBfHzKntLVMjRgEow5H1Er9o1HpH7OKnUWQ0RVldkk2I5g6nCUndfzg9/6ok
nGh9Sl2uWCl/7KT8Q9KUQDFZb9ylZlajHEocuZ4QqzBRCQDDEZPBCz/8IPe/sY5fqtZR0PVgLIiN
7VSOs6pr7lKjFBMXiH0rA6gkuRe3YCoNaAydA2Iqv/pT/MvzB9EtlzsqVt+nwAfUKcdY55B8aOmh
OypCK64uGEPRfo35CU7EnCHNcMPXaGtYmkwxZYfvCggoS4oq5cKF5k/xSHKwgXd6TJFYvjLr9Yo+
M223VwAV50L9x3qclWyLnEaiLmOAndaM91xNkImBbW6pEtL5qwq90hccpa/UFMsbEnz1h2No4mye
zbPDyKmWaJk+YJ/FzihWZCqak2QGEvF6SFfj8IwOfY/ZCbPkINfzhoeNs4hDgJuPyIfS/uVK1tJl
6mkPiv0pTzx/l+p6N/j9qs84EVPN5OWY8RjdWL6OS/yD2uvou83LR1fyxH8qA71Zvf9e7sZEy9oO
KseSfx9e9oSSXU5Y7j2/tK5Jqavmy4j2ANw2k2p8kqjase086t1XQljOYck2I9adH51gPjhW1igo
Q1iFv+/QDc/TR1E61QZgzbP3njeYVL8PuaBZlFTvLuFmRcdyw9g1OCgIXCJlMDUIO6bSLE/5oE5H
nDFLjW10MF+j4bjRNDSYwM6HhlCt9InJjrS+5X3N1ztHC2m0bvB/I6sK/EPppNrzEaChrxqyfBWU
8m/vlueTRfc9kfRo+h0LWGbGi7gqCdajDX4O/mepnm/bHypgU+LC/OXRxUdGiucCCfCHs2OteKnb
jIdKFtAT3dNf7y25par+RG07Qws/rAwiWqdO0qQpSJEiwtOl0GwzajDlkDn1Ck2VFgR319/TsrBb
mUgsmHc1nbaF9OiTx2pNjLB9k1rXtXSefrV3lDGUIWsTciAAmMaqqZrctJW1xbfl0oIxZRsOuoTU
yrhlc78Seucm+xSr1brrcrfoIBk8fGBOGCyorDYcUgUAk2xIyz/qzt5mJsWVX4RV/lMJmfqVISxj
vwMMFKdPCIH+sA1TaVc7BYX/1tcGIblfdHI/itGXf8nWcX13jwjnFK+3YFTriYXsRuPlhoYaRztU
C+RTH8gjhpSucyP6GS+5D018dVNS5JnK8nWYDashSmAfJImtAmSVZ5Hv62r9XDkWZ2nfg+t/lzSA
lrdbk1iHXGxaf+/uaAhhwP1jd2+WGQvn8ZFNBOaKwnLTjl1bQ5P7oICnVGbS8t7+WQ04gEHaSwBm
sXsbt5VW5qDBxulJk6D73lTBf2gmdEEKu08I6FfNZnVkkgnxSkSNDQZsmeqynAkE4UqPcwRnzxmT
N417aXEJE4NwA21uUJq/saMQW8zhkRyv3BOOrYZStkqzrISb+nvvDHssGeMBtgpN5cC/eL32Wc41
NqDef7jHk0Rc9aKvDsYPEq5uu0FqMdb//8Iy7eNs0Ocxb8Z/2NYRE0rFoLQ6Bo+GDp0hjhMiKU4f
CeYM7Uu04Y0UTmKdDJqMrqvEL3qvGD2BPViWSnIHLorlIS+t7w3BXw/KHs5PsOzu9XeGMbAeOG8l
mMN4k6m3HlHUp2zG0uM6Tj26XS2nbS+MspO1S0oOZTDmKy/UJv0QPEd0xxGmcIp5+EFX40CSi7dM
D7FTvTp8taS/mfa+twUWRKqnW1sng1puo1Uq8DoIAyOlyCDPCde77a3Lo7hzpfp2Kp544XrOqWde
DrNyhJHfmDACcCWRRyOO/6ktcJWI2DXFc7iM1sHWdF5jRvxxS0dmdlPhVM3YJLYhmATAVXKxRXtk
XDPRB32GmGBGXRSxLeZWd0AlKj4oT2O4uP4s7k26wpxQoe3H0/O9WM/nA37OFpPd4Zn/fOf3VEYF
Eai2Jd2/8+mRvPf6ZiddtpiDW+1bxW+dqldcC22vsTIIyHALpar+BdUpyrJUjvgQYyl4VM0TcgSb
MWnXt/OLfvLLusQnmJcBc8gG1cc/VSfoKcgXNZ3+TY21M3UCrijCK9pzbTcUIdv+RWS/9QzJ5RwK
WCtIrJ/+U386KtzG3kofIsgcg1yibtqW5VQ7QnrmXMk+dGuVGUw2vXHm69z+UlJpJEsjvfaDsp6r
+2gmkUG9Pjk4NxaTLqkzW5OrzRIqCqxj9gZrbUSrS8xbrvG7yy8PDZu/qkNA9BBHpsNJLoE8ORrv
GXosnf6saya84MiRdyJhH523xrzkBVWxmAVIlSIRBX9zyMegW1y5Hr0NeynlX80koEluiPvgBoNQ
yegiy55ipIVjMTR8c2iKM4J08j/U1qJqDYdZoBfjAq2Iomm8vStf0aOmCte9eczrq2c/fMcdXRm0
tSXTmzOguLvtwfqG3Ou+YhZTebMFrmh8mpU7T+gaZzwf7/95RXgZ4P9N3+1wPNdfLj2eQuINzf1m
ZFkJzY6MvzFxRWpFVGFG7cWv/iknQWZgvt3HFDSeJj7O8ZewjEvkknMtOiAO8M5Crq2y/1PQR55n
xErJJFDWYw9jGhyEpfvtYfZnJIwkxAWprEFNf++Pnu2zCxBVkeqnVJRV1TDyZvnTV16ifOLt3/CM
8rKiJ0pEFAyLglftXNMJVtNZa2lXZMJacnseKXvy4tWwtswJDnxT2IArEhoyyxLxRC5Ed3WE8Fn4
jXCQrilr5lnQbuapp4NeY0vyowlSS/EIDdl/aQkag+RcMaqdSJkZPiRbWNRJbHQ3aLOzxhHuJYrt
ffgG9xBrMlR3mfVYyGgYqbHvspsrm0SvqOucSFp1c4OBU3bzY6YJioJzhgMzf0fo2HwiqGi/FRvh
ZKUmQ/twSNW0WUNnRlVC7RvMQc3ORUpJtVB2n0rLsaezvEor7q4M7RliUQqs0+rcO0u5LODwxR8/
lDC05zqkJEnHjq6h2EjSk7Qy+ICgfaDe+zsIKPmJm86cuxS518thKxz2CGr1PjB5jZZyfOlI9ODh
/R3xr1wot2pvZUALuZ33PgFkJZggST/KlT0EoKzyjYhLRsslceL1iuOPM8z0g+lVYNMXhip/g3JZ
itEmHPP5UjR2whjPu9MyT1k6yyKCltGY0VRCMnf0hZpgWLMFJ0p7a6DYSn8eIysWs3RZ6oDzO73X
4pat1PBEu6pf2bIjLKjYmhbyn4Ykdw8qz386bn4EkOuBKQ6MDoXJDkeLCpU3aUKgVbYr+lKv2a6t
1yGO/9ATcH4i/J/guOVEOsCPVYqPJvRCIvamFKus3WU/IZ4D22mGjeJwKKy0G4g24ZQdNZAJNoV+
rlA+utV8pY5xCTkMFArUh2Jx6LU3aNVAQ1ey2Xr/lb9/g9gjGGGrMGxFS2lbcBoXBRha6/TeSrGK
RL2F37dGn2feKMKMIydUl7So3/3P/i6lVVxzNp0X+pwY2O0cv03qAdiUFlJTcwrEMZbjn/fmnFH2
CYyjxYfcCppYcFxpge/43Jsb8ghl4gFSY6G1gi5crJSa9dvfWJNDKnf6SJOtVCdoMCJvxlCnJF0W
hQVlfPdjboTHg/x2SpZwKXN3ahP5sQFi5Jgv5pcs9siyV7iUe4wL85Aa8I+puROCxJAQSCl2tX+Z
FU+hooEoyC8kMrUsynKv0NHTvkuioXDfBXOSzcTqIUixOGvb5RgAEReRo8GOqlTaVVYQSFCjNsWG
mh6aS2CIrm8DTEIubb0bRp8Nah8504m+FHPywlOCZ9nYODeC/RI3RdeMYetMuSS0TUZFPQ4rJtjQ
Asopw/qhp5Dit5Lp3YZZLM2TzhSJv+9wj17jvWGBePcw2lhC3RV5a2L5vEkms6A6JBDVD3kF9y8g
SFVHyTAPN8nCKfiesTlpv3BAnM+2kvq7aFaMD+m6Z6nRicIrJWNBaDKnPm/cB1tWBAxH2MlhQTQZ
jHjynNNYiiWpuuB1Y80invWKl8srj3ghrIMg5X3+BXXuHvF+wIcfipBNEUZS7rdPxu96bsZusANZ
ZeBumvQsHrh4yTphnxzzAiD8UBX1FTgb2is69MNroXk96et4n0JYiiORevfijynfoe/8pAKKnaI0
fXAPVLgMM/+a9vJcv+ZuQ46riptaQAHO3N1t6bMs953aKLwsBba+1z+FbquKwgZ+mbtIykVx/U5r
FLj+kGYUo6zOIZ5AqPi975X8geU6xg1kOyDqg1L6q11kP5nfgbVBTnPVKj23ywfLJkszhOuHQVhh
ePBIY9PoHNYXpJ86mDLnJF0ATFzeXMEBsx2BjZQMPJ619M0KsVaCj0zcBpCF5CfY4RZUqa/5hl7p
7WREgN8bzCcebz1PqzasNfYXnZ6D82U4PTE1gvEwpiGzzhtKjdMdNy7grcCLDURH+8VptxfUoh+N
piIwT6y2wmB/fwM4gT8hsz2c5Fbi7GpF4ay9XQPYMMeM0+GQjrbX7TIskwuH6xAQnqM4kScA0lk+
kbBWYMG7AncKeYHIeT8QutTnBVfVM3/fcgqX95DXp6L5zekpgYrDw3GSDHpEpT2XmjnPZHmX0g8n
KdOawmBKmywM6bgCzzOb/eU6DKwC2SqCK5RfFBw/ZmuQNqnpbz1M52gt1H8rV0NaLlnqgy0qU6Gs
wSTLaPqBx2n9yrGtPBlJbzUyUIWVKMpp09OC+50ACJBGYXuEsfAXlmZiQsYDBeL5O5jLP9F07k7f
+cith0I7oe72zIURFCuwQVgceV8KasYL7NgSwfLI+RUg6sDTUydsuve/lAB8JzKlZURR7YH0RZ6G
OhIRfVCfPWPaZ3mWj4es3sAk6i5ho0/cisypffKg3fM7fKkU9qgHIVwZnEVNpTA5+86XIAkY61Ba
XkXQW4zTaI+RK0JzKrvGiSwCM8xENy9XaWJYghQauHQ5Bcoz5wnv+qlW2wAbBNBFHvLUcVZ+QX+B
mzcaUpVDXc949RroIZsCRi53L5BuC3kcXeCkYlFu+wpd7+6Gv0u3jI/otp0YnJF1BoMKZYJg5uCB
xuSnevJHWgNu4AKHQUuoHtJ4GTv32OoBLiRQZ4WPPhX/Y57PTObpDro76nrVWNo7gnhjFfhb44Mk
G1Gc6p1c+LbNVmLBG9BTO+q83o3/kl8aSqxscdmbUGWHVjs770zPv+GXc3dmv4A0YD0JrzAtnh5r
yd1hcRTMp7SOnKWHfh6X8D0KnoEgxnjlNZe+D6YqP62FcKep7ZK72cZDgqApY/iIFBr6OaAt0VEb
Z/kRwsDlx2kj1wtZr/hM3/IIBEyGr3/zOuumlmIjFjB8mzjBWHdO0qEK2YVpB42SfxFRbflstgfM
r9Rev26qmvRjzydOPDVD4OOEbjdTKlxjkq7fs9rs0d1VD6Iww8LB4v81li3H7E6rPfrRctQmNaDh
l2xSsfD4pN8W1w+CMnvFuf17c77mG5FdbUTOQRbAU4OZYgVOxfZgO23r7nIHQKPFab3U5/5igZNS
GDEo0oEu7IV3olC2NllIGU3Rkg9p4jL7EyreVHZ78JSp5ll4GOm/qyH4mDIJVeo45OA+DvSJWnAS
+tU/hxxhfHxaFKwum2FPyvUSLxOtaWG6/fQW6iNVjDCx5NU8UOW9UKQSQp69SeADIcG1EDobn2B+
NWZx6jHwUu2wDlPwIaRgHLql0jT4rOJ1E4j0AsyfmwK9EcLfodKs+vx0rXjYgaIvlFAFTOevnpg6
pcWmEs5vQWZoGpT3KwrpFNWCii30BtikvMEgDawlEgTOWEcRhK7WN5AfWLe9Nd76GUlzuCxOV0NG
pWNsLzvGG687stE44EGwjQPOuyr1LjWyPAZne4dS1iz0Ykv+SCm9rG/w9R26gRKSqGAKG8WFmUB+
kc2xK1a69pR5+pT7io/oOxLQvPf22A98EsQgv6rX7Ng6vsHK4J/Llf9sbPhQFsd53ERB8ceZ8Ol+
3jImbUKVwRWXbOCqJKgG3A6/l79ekkdRDghi+czjKWaGMIm5Q9dTjzlIRbUTwBVPSdQuHST+L9w0
57sV0bvI4p1ZouvsH8S8c4T7r5K1I2Z35SyW8OZ+iLzl0GV5jUMij6CArXl3QwEk2lVyCByf/fJO
M2A2I/CDdO1EGXyQsrGASrzvLsc5WCXk+CHtS5i8U7pdowZSbfYfglTLA5NfuQppDB6FqXKfhcAR
pLdnGet6pS2RGJZzR4GhD+y6rcFI4SPNDSBTNiryy3iq6GDAxXcm0BD/9ycYPbs5hcNBO2ZboBVd
A1m2yawROP4tB3lncqd2qf4KEcWIjksC/kcG5VNJ20SOKobGxyFTi3jgm3E292csBYz38br4FE13
JkZOAqmYWWFjRKEXjBrhJVIrgL7Rj5YdhJK12fVDcHpqH2felBStji9OOq1sUa6upYG8PeQlbULb
Cd7ETuI+Jbw+p65nxJPjtssjTq42r4HYUX1Vlts3r3d9bKloFJhKKjVtdJAGzo5vXur8J78X+HG6
D/5KwMdbllEauYX/JtWqMryJrz7OKJw0FcWF0b9tfZ8ykyltxRVpR5nZRnJwvQXwNlXv6YYLvvK/
fFLew2IYXr3Na7gyEoF4GOFlvUidiS0J0QOmzvw62x0EGSHNiGOD8Hz9uMs0vtgq+JoBng/o2fmX
dcYgCEa41TXaTD0KD6b8ph3dpb6ue714jn8O2uJJqB9V75nbpLMVILrtaZxZMxOzk6oqYPpSpmNC
77WgN8t7nkvTzqAAL226ax12kM6FZ0+hF3B0fmld8ZG1YD184GJkQclbGEL7KbRujWPmqLva2I/F
pyDYoAfiK7ZFiVLFWoV1zB8wrX+trjsxkOUa45OqlBTaRwcYiYGMWdORyJ70Qx1CiIl5MIX0iME5
1fRW5P8PzDU1KPgUWF0o0Ov34CWR9xvl/mr8+4Iepb/txA+6rPlgjujknZyecNEln3khgB5xw5as
zAgbqOE3E77+7v7SPcc3H97ELrBXUAmQY3IzEbl6f2P5zv052hhpRSSHF75vIGFjOmePkYO4CNWJ
Aoa42achieyyFqZEDPPelvf78bh1wa2WotU3RolqJt58G0FAb5zAV5aSVnJu2+CPWDBs3sgxTe1y
so3WrP3W8V6S9OWkyh/X5rYKbI4hmOI1mRBD8h0iBgtd13EyYAYtbuwxjklRF1yUahy3I+VXvgD1
wx9zHJEVKXkbWm24/tDDcFu1MTqsuc4gT2zmoJbfw4jUubOM6CLeaUjc1TJC6YMIo7KFn2huUOxn
LH1aomlNdiixh8qdweqWBpOKWWqdmbQ0yugJ7IG6tbD6jyoYB+sp2xMM9Qe7H01EVKAy1SZNMlod
qlsBLBPiHYMVuN8nwchJgkMUOBFXBMTWbJQB5oEkXK0zNN3gCEdR1q/X2Nc0wnmMnzJcLfae+uss
epNxpymvDEj368lx47MH7NlZ04o7L/4qO3kFr8QtZ1NFDtElhUQ9Y1c4U5siZAUvRlToEumJSU8Z
xjSratRgLViMCrpUQSXt0HT9QZcX1GXTrBU1A6g05o1hZmrUhGjtCaIrOT+RO8GpwakGTtTEkeMk
3jc1DTZs+02gLkJF7HiDI+wnVJTQCIqPJkppUCDXH3hAs9TxHrAx4Z44NAsPQO/FgdbuVJmhZS+J
YIISQMMBGbXCeDjKyog4MJjA/S3IOixM93SK+cDhtbm3p3g7zBliQmRtPcAiysgMM9ikd4rBs7sX
x14pvVBdDVRB/qKgCj2LVAtzazoQJKSPu6sCP2vSUP3crmEHOZYBVWNbo9zRU47t0OrsQAHxFTd0
wHFLBhylVSLC4SEfC2n8jwN3AVqtAfpbmsJVRZDjO7YtJKaYbM30PRPJmM4WXCLMe7exyCM8WnpO
kILzqnnLm8Ra8e1h+oqSqQqESnwCtuIMLXQJ8gnG1fR/ls5g/Seixao48jszebxx5OsYFoi+wA30
6d93G2218fBGVivfHE6wpiWrW0EhjmFOWumr//9D19dPGVyNjzZLrTNB1EwSnsCzJi1j+oPo2e6K
I8T20SskRITTdftv0vQGq6g/iWPKgtdApHZ3kFR7aG+07SpW4CjEpqf5+S/xF5VWYgL3Gd2Pf54C
7i0JYYY075kviokgnZBK8DQyjFf2JSapmq0eGu1mL5Plao1NfGebHC59WbTqMGou2q+mpI9gP09A
lIHd3jWXjEbhD2WanCkICA2QwI9wkFqpyptH+ywUXSe88kblt1ViIMtKvAXhOVH8LbRXc9uq/FtO
k6QJje4dubKGc8W48fCuNqB0kvMpAfcDLncQGgOvLpIS83bT8zrWaZt7klJb7KOgtUN6eM/nT8PE
qn+Ruggv7ACFl+E/4ybL+PLRHm/YJRvdMW7SoZ3dBrkgta3Pfj0W8zPZiZySK0G4KWlMb/rEfy16
H1jqFm6V7hm40XP8NZZZuakcfOrmhO8li+SFbQQssQRbazOaHsdM5kha5y7uFi7Bx4mpiCimF7jd
K4vDR9z5/bG/3shc45MGHtHH5h13RU1lVlUABxAGLh+TlD8XZSlYrceu46iLt6wRVtt6wRVDsHBv
piAn/o8iTPX1pCw9nIAbQCBG2+BGUEeqhBCy65BqsRnr/25f/rJbv3FYH98agyA5TRkDKkaQTAj8
IKH+Q6jdCq0Nfuzmw5txUKrkOVYoAhfF9I5DidS+ySQy/haAMNl4DLFWn4fjzMhYouwHn0aamxvD
Y/vVZAV/DimUTXHBpLakC5qw6EJ+CrrEEdNkl5b0bWnaUqT/TXJZ4YH3y7WHE3GwCepoCV14s/2N
PtgSBt7WoTZavH5e40EWWuOsjj1pK/69WZyjXx1IV2iWP9MNQNeN94MTo+qtwohp6o6h2H6tVr/f
waolVks76XazAFOkyhq0Yl82qcArvdHqGlMq+AJ3lbYa8CYjOu7qoTkUEfwlU8XtHlECT2pIiU25
gjUGrhT68OxVEGSO9CMAU7YvwiEuSswv2h8n5OxSCIQGj1/T5ipjWVUlAg/awnDhsWzTPDRFsVhS
BPv5C1HhV7/UZV7mZwk6PWRx5c+OCutrFXHzYPgWf35Z7RhqoCvtM8DafVYPvyBvJ5/jDPz94/I/
KVuvtobGulsACRx6VYcnkHj7rxqP6QOS6h0+uz4Fpd0OJQfiAOeDlsy+1WzU7M4am0fkaWWZMtHo
iGVUkkeXXwr2uHtHAnX4iH9yPFENo5PFsudEEUxlp5MHt6h7zHHznXfqngVXvnGM1bm1ezTsD1bT
MSrSANqNY0PY92ynMjIz4twf8xHUqOdODbHpWEm0Ty7VCAc42B9rLC00m/cIxfi9OBm8Ur1ucoe2
vKkSrP+Q7LQYcrSOZWOgP4+KWzElUPZSzplVnbqD43I8EuRfzij3zSzi5eEgG6WP1cjxymOObPnP
KzipWjHA9sCyAuKhzE50KkCOJgp6zfsTZAVbAkvTzRsX3Hgk/IksMlPY0se1UCbGr/AEyxcfP7Ua
oVgmUAo+oe7oIMqu9yWSlKBTqSjvKwL+5S5e1em6BelUjI8XMD8SpLyYPAnhq6700XoAKjVD3zhG
/1QtsPoKfk3TPtycdDcW2vr8Jvgdift7BJMjQTc/hl9ExbLbtNQA1DY1M4lNDUyexn18yxItnCZu
7sX5Noj5hgbeJsUgzSkHWmP0UuAwnei2b6QrJr5D+NK6a59pqVIPmx8tzv0YfYbUz62VmvLyTWN1
Z2I12r/E7pF3GwJ++/idzVePg00fXw0UlwzpbI3RXaQD7DNAu1gbg60WVGU0rDYkDavuC4ygVlBV
xMzmkmhC1WRoQzGsfcyWwnB3jzdVjUKcRdQfIPhRdgQEYXZYemfOuKd2oJdrl2sDle49XGv2iYeH
0ppr9+++kJRLQDeiBQ80ymDoCC0iscxHLdSUOfXXE4VUlp746WrdEkX2f6V2sRVzV8tFbUplsq6H
H7dd6JPYSagE1azv4oIVeOFhkkVeIqxehcXuzwVtq8CcEooWukVLy022l8t7Z5MJUTjS5ZMhGlLC
vydhhv4tMqUV3KILpKZVZ5ErrsE249lYyIrGGt17bFAPJIK1BToZ6h33LOEqzEQ789EEB8wVsR+s
kXCVhmebW2Hy/Ufr5p4sgxv1bUVaLX+7L1mQROidKDib4Idk1a0aSbu0h1P/1enTlCFVV/4tJEO8
iT1YQZjLAVTPCvrxrBxSm+DXVptcSiaQbfpH77IAvFk/c6XTUwYC6N4cvEdpmAzAHZSWh/RUKHc5
DppcoTEjvSSV/UPo5CW4DBqtF7fbvRR4qGqS6YmZjl9FFAEnuAqlEnVX1+LFczmwhbUqShawcQ8a
KLJIMhvXbELREH/UlpwCERrJhf3HUD3nmjr7UIGlF33ndwXJPqjgfVgoofZe2dhzn6MM9D20NnPT
EqQ+VPQPRn7LkhIMe5aGftrYXnPSS3++n7hWMTDzhbeLY5T9zTMgS/u0nprIJTYKHhGzPHOCRiDY
3wp6UctlUNLMPtdmxMrOAH5iPmtZx5tcShvXoGLeLyhSEwziLaNbgSX1DnkBkVKrx8l+DINEMrVR
NZ8ORAdjgCQivuoHMXkj51WO4CmShE5iSmHDHlOjT0Xr0fNB0LV0ZKz3tx2jgXGbsDRSwN7J6Xjh
lq12UwMbS6HxKFtvJ6TDATrll+Z/tiVmnvG//4UW3buWz4XJJAbNcHfAQR/y0CV6ZufDMu3q5NAI
cvGVMqaA4B7gJMquUAcB5GTkPOLY0IDHj+r0eKlJR8dV0K8DaXOjxOtefedwTbvZTiXAqday5ddq
kAbXxtyl720S1UUIstdtbTmmoL4P58IaVKHvJJ5AnRRRSZL7ICAM8Wjo6JCZ+85PZeqF+IO21CTD
YOKIa2EV5GPHKiWJjMVJHDllYp5cYIRzkmxKmEIvg8Fv3NFLXBU8f9EaJm8MR/WV7h3ZXG+xrWpQ
3t//EGmA0xtRlIVwBILYULz/Ee357amSCrp0fTo7BTv5LiJaR75YkXMX2zWRkRYwc/uyTAls1OB5
RWZBjCsLX3nX7QNNebqOOw+IxSimpRqsHeMwhaE5AXi424mWhzdvy9t+BOuY6UbecMYsA2h9VMFR
iZWZ8YjxkZ89RIv2rprwaKAWq5DXvtivGTKlRYXyKA6Sa0gN4l6CNQHCx5eQDK82kreUmeqvRzc2
MMFupb64sWLuwykYreptVreIAPDvVD/jlZUtToXMyO+6wolML5mEG5xJoyLP7/IXmNSoeXyikXDq
Hhd4LMHifpkz5t3e+nNx/SXd9kpvnqhV+ITJoPzmpv/kuGQDlUiIo1nieHEDou1MlbT+bVsHnRnW
xz1azHbfNfAdLN7N6sfg04Osj+kyM6cbQWAOkTzNoS99M9tZFl1b+d7WuUM1SXw0IMPfumroHx2Y
l4Vflm0n3unW39jnFeFBI8v0GBnLMtRaDNR3mP3AkQCFVkPvCR6ZX5aLXro730hdroIAXDx4S4QP
QDnx9rRaTMRhWS3lolQeAWRIVd/v84jyeCLn9WeZ3CLn6Xfja525Q5mobTu0EjiNSQlh4lrqm2W+
8kfvPiTePRxvVlymc1OFdeBeSVYWb5nUIcAL1p83L3KgBbT7sDUp/SHKpUpz09wHMiuz3qvwqDd8
ujuxgG2NzzqksVSJt9W6zgcb4LyqB/0AHKjGUouojwsmF+EEIjsFaJfvWaLfhciCV7m7d+eMVTpr
42JbkuteQNMepGm1dlPT+/z7kDmNOmLama4ALf+fbexOi0BJNZrdkgkERWZZjhcePLcqZR2u0by3
rvYUOcoCfbSfDwQ1BVFAZzZdqMIuoittIxkf9GYtAM93P6rN/swKbkgRz4GIvIUcDd2+rPKxQFbH
aq1aWl1AXtSCl/rrzLn5aro2NJ1cxzTWEOt/2MQ4uHT6B5GyjEYunmUwOZ1+1lNbBa8y/arQPg+K
+anafTd/a2RgD4QPoZ+0sPr9+L+wBu6uoSIWXhYrEQh10+J/oNL7b4tc4QJHmhLi+gaSOhTAUjZM
4E5uLnpngGo6YIXE04jHA7/2wgM/fe+xTTkZZ8Z+ozc55PlIwbxKQ7ynUBdW5D9t4mD7Ych2zdk7
t9xPkbWoonBG3B77Ho+mp9d/v7NoFfKjS9NJnbfyAgtvWNy/xGnwEG3YfGaClXDfUOH59LArJVjN
ch2QsWFbNYttIEwVj1AJAdbG1Z3ANn+EGwNxz5Gfwk6ylcVz+hnmimBykJgohEboo1dUDcI4t5jV
EPkKh4XtJRVx/gWUChbFdE27ySx26+oyU6cltN65WHPOgBqBoC/hNpm1Grkjf59X/NIB+WTaDpP9
QG1nvfUEi7PACBdtZ363EAajQT6xWAbVjRwYjV7J2RSuxq6PNi8qzwSkaXcCLATVNy0RY41cPPiZ
sSSOyU0D5WGukj55mlLCGXV2yk3AkoE1FjvU/LRhnzeRPvfEPSFV2RiaDEE0Vfd8RV6hZk5dryRm
2eXCUG4eAsRI7oNgnLBKxGJ6u6/qw1OeL0t93S2HKCtSRSpqnII+Kktpg3k6Q4pKSrQebJc+1yFh
c+/7Qpo9KazxuNl3grt2ke6OwykPnmbN6P3mW5i7R2UYWZC4EDk4+r0qncz9TqKjmEiZp9s5YGnI
n4UkpZIUIPuMDwE0ND/Pen6X4r2YWafzO156SV/B7ob2UYhVadIBIZ1Z38EXJ5ZT+Kj3zWZrrQPi
Y7yf5RobFEP7aTm6Wsg3a07zcvwe+SUaiYj06fXMT8X7o8+zdGBdGB9+J8t4Zf7i0EBeJeUlWNbU
1pJXtuPSe6cBqrlocBwGBAOea5vID7UDTOSZ9w/90r+PzXIme3Ol+W8G3V5iBYteoBZNZeKDNfgz
IlMBx526clq56XqccyqPjrpP0JKwRw7HvwtlPKD8urWmWUpvy1xPlggYlZQV2tyxK5ivxKj6i5s2
vloVmoxbnAUBhJuF1Jk+1oaRmvcZskguXPv0q/1RIh4B/HLoJaoavZbkQPIvE8spgALTqMdF2BFa
P2qi5STct5eIhXhlm/2TfMK+OL00IpHS1oT9/M9KfUNVb0llFlWdGeeFPTZhZLXSlVbWOwRGAFyr
5DY5oIPYtLwXmMxBxC5DGyAiadVyeHuIel9dJX7gqyN9EKL9nIPfDtI0syX2fqJti0ddgwuAyNUh
AU2BR9EPqfj49Ua1Ad6VN+Ubx7dBwCv1HfUZsrTon5bneDXGJCKqZRvc4vDYIJ+/4ZCCKlQlSNVz
7xoXN/M2u8aIesoGsLCme36ZmnTsr8gL4avm+BjA02ieLe9BaBAZn4778dJhdlMabtc2xbld0SXN
n6k3Ad96U5bC7pzL9f3FMwbck743kE0tKNtg2GyzQT/TMq1c4T5y5UI2dkhINTpV4jkJBHLI7fTf
9EXc/aSfVjL/42+x2UjYncsWLEdQhIhj7uQjbWxeIC4aRSLv4ki++HJ/0r7ymyU5wnQjNpVTrUlO
euPKMaZQ05c+oW5e2TkpOxMC2dybYOdWygRIp6Yim3umB6ak1GBbf6Ug34m/d2OJokMwBty63Oxl
YEAcNTaj7rD+UhT4C5pjAppxPy6Fds9lvH9KRoT7e0bd1/YKHUjdd70VCGbRCZ1x+KFiSwDzFSTp
Z2PejKQtvjyUDWLCLeOZ2jCVKu0xZe0tKeRoLuCOfoeZSwC3mnH/7IbcfvIgYi5bM8XDHbbhIEfZ
U0Vc6Ab2ygkFj70AUOmujzuvhZmyH+yRfVss9GmgmUnYaHYUOmqU6Q/naoAMKX7BXf3pi52YISF4
TbrwmXLjIhBRAdm3EA05Kyo9vWmadUh8onixSBjTqovQSZAfS5C0lyTWLtQBlW1mP9og4nq26Plc
AzlKbiuNYNXvZiyuUXLbU93sYT8vxYcYe9nK/o0LDnv1O7fVHdiJ7lLBBmUOd2BZFenbnxPhlYro
3ZjFNy3tgJTghcEkOx4aKb00XkcTZ9jVWOKp8RSLXyYaJm8LmuJn/YGtrGucFsRIyZZrNBEycvPm
TUmH2725xVNqlBg9KFKXZf49XwSXO1jQJBjNRG/gxN01CGB4UHpL+jarJtH6OwI6oUuVXRwPTAyV
a+tMY7f/7zlNXettVktGR9O+THxNtl07723aWSOgEJx34c313LJpZ6Vv15ZV4mL1K2aXDAooHIII
GzXlECuaT+EXttH30d8jOKgJtpdWseaKMGPD1Z9SYArNSOCJE3Z6hL7ogej+2BTq0y1fEKE+LnW8
f9csc1jDz5D4hp6u9xoOHipepI8hdXK2JhAxTJ/KbwQuBh3+3h0F6+SnX04T2bR0x4jsyaJGhwY9
c2NudeRGY3WIEPUgdCAq955wQvmhhb0juIh2GCxBiDZnPglYsHXg/KesAzNtPgA9aBBf70rApVXX
ft3wPTGGQcC2SWLikoeczBGNGC5yrPszTHdnzde8eDeTV9lAHJCZV5lsGua3hnP/gfWlxHZykn6L
bzYVOJwm+0b69Mh0i9mSCbYwpaNq0RYIEDL3Z7s+oInlJ3YbZGY76Q6/4iMgIzGMvq78ejktUYUR
GC4AXvtvzki1iZ9LF+64nw7YqXy9LF2zEGOLDe2c+C8r5zvnCyJ2hZxVMQNoksehgkRLNu3eYnnQ
a04wO/4sjLdRNeSFQl8HsZIvXjcY2r/6aUDHUIEg71JXG2O7r/oBcO+Ca54ZbSV5y+X0AWPzBvjV
Bis79GB3nD3doRsOxVhGsmFuKrpfgjmoQIKNIBIAQw0lR73RTbmcg5I+xz+q5d4jJZDB1d13/55E
VDiYulw3ePEM3ePwPD5WJTbw/De9/r13ktPtgxoGz+jbRtH8oOlfdfLi5+dDxcqehgeYnuX75JTJ
EPPc65HzSfbrePly0gj8t/4Ex/9RSOijTECx9i803dbFcLeFSToo3zTfVaUBtzV2sFmiHclUPmx6
gkXSEekIuRwHaVQpYGKB38PzNFx0tL+NeEJkqUPeqyTAzCB8E/6hCxLoh6207lKNQoossU7TpmJO
AeoM7q3dqUobCqr61vX7kk7l8DVFmlWOJb1SZ/2vKHUp0/pHA0ZZ5XMMU7G1tXua/Q+BxqWplZxi
UlqLkYAc405wHP+QOv16C+dvYhd07QBv8xevOcl2jTkAQBfe4yEL7MnGiYldpcR9hyWuULrFm51V
VgdCiu8rHDml8OZ1G80wiVaCeGEixpjohNc9/oq12Jo+lSXYFM5k9YNzeRzawMGEizjDukDOzWwA
i1L8YrDBXaIGh+c+huws4RIvZkQ/lIp1VeSbiD7vl6T91AJo0C/oTObF9ZN8aAvL/IFsiMxKJQjI
kqLdgHa0ZXdZ388H6TCLscmThsyGeVu7yaKyLclIPgBhMtuYk+G4E/Xjtx4Kf/xjYScQskuUbXcw
0gosfxd+NsOIcZni9igtfBlEEAMBhSvWYTsOBJqXb9OP1+Z968znuvRA0d40qJo7t333mZnqt+lm
PRBrcJN3ZewhwrVOlaif6OdeoUHJ1MW/0AbnevQtCaohqH03rD/suv8EscvszNZr5DLdcM1qWBSb
vKJooywkA6Tb7Hl4UVBXPQvSnnd/yrxv4wedOlypi/Zgd3CA+Ao6U5QW1gM7ZTQiUDN+99fWBoPV
LDRuYr06sDdi//l9Q/4jwc7PvQncwkvZU5oGHLENo6dO1z34NuQrhe0vyEs4sGUESRobOcoFAo8k
0Vji5aYT4/nyISiquWxPKc9sNKr1t0/PSzjA463qGlbifzP9eB9KIBe+1FBGnsqS/oPd0LqvY0/o
eQWuEUgAzQ1P0TksfJOAKsji0BUlOvnLFbNSKN4aAPLNTw1Mc+d2egsCAOJb6fO77u1tL19RYFPN
vfQfq4edVAMjJUvCQipCzH6EBGydGYsNjskMUj8vBsgZjBw0kLriuFixpn3vwbE0/Yip6ZBMK/vp
amTE3FIyx+bp9Fp0fjeyAe15cz24TN2X5pfE+t6E37MwX4jquxkR4gu47n6k1Jz1JMKsAMGPWg6g
5z62qHrpaumss8yiTbQAhZCC5mKitm5Fam4tnZVAAG72gvQUrmd+xXgwNpV285NU5FHn6Y7giMTO
t3+rPF7B0q1udQ3R82vHOUiWl/kSAjMJbNj0B9czOkghfTQx3OwWvL8s3wtBrl4NGZEBvr0S0Vus
cBGl6FF2KYRiLVipnAFfqslVPqbWJMNYGc4w9EQdQYcs58dXFtT8lx0yFsMSXdKMCB6bTejnsSop
HWh3GkVDeFv4Cpiimer/XfbmFcbrQ7pdm/LZ79oMoPcVQw16zp4eKtUVqd5RJfsFGlDKqVgmVLoS
eLdB4x0rKygScGwObOEHf7QrDMI3T/YOj8Lq5CrQyL9mAwJeAn66Is+OLxngXSqFE54PbG1WL2sn
JTK+iulES5LLGrrB0Em87ERzQbUqLH2ZHcBixXv80OiI3VT7mdlAIoLgCMiirWxcoDDJxIq1FmSh
37vbAHLf+9RUjr1CFIJo7HEjHpgmjKeL/Qm4s5m99nduOUYQcFEpziaGbtjdNEkhIFjo5o9chmRw
69rFwKU7d6lo5yDOYJxWq5tLfh1DUsDQXzGmEz5uUQlAc2VI5r4FC5lls5TxFl9GwzQCrnpO90QF
MVeOPc1oqoFO5z54iFcDgDwdg4pB/gttZ2ZnbivBX55t1bpcjkocZfDDYcWu1PzFa2Ip085B5N0m
GIKXui80u4DuxMgUMOF7n6izhY8F7Tz93rFDpH/kCMuIzRBFn2smZFSAHe8bVHiHavYNeQQjgUSx
2W3AH+jJ0F3wT8zkgp6iywtuEHRCGg4LS0m8HDcul8u+ADEbJ5XyiEEdm6xzOWqtF5VliwkqDMF2
UEM7vYHycfl5zXc17EFq/MO8qUHXX7kscmgLRoj4QCrKwjvfman+bPa0niLYeAbygBaa2AEZTLuR
nBTGO91IdSEYB4oMI47p3gugtK1HzLxJRXyh2a7gZnyUiu3f7SkH+TGolNsvAAi+ufuJF0qkZgX/
J5bIABrT3U3FHJJmWStSwgKlsGg2vM9cvuAtqSrgrfGQfc57IR/GAu5v6xjB5Xc0klhmDlwNl5M4
ek4c+YpayatFAeCyAb2kW4/QKP/o8jZsSePjr2zAue5At4HNaBP+5wVqGt+5So0ZVqN+Q3RREEbE
9KnbH8Q1y8l6rjUeuz6uxIkHFGkyD2Dzrzvm8KmONTSqflRQsP1CmTwoPID0JRf13TWRvKh5BiQ4
35Pigfpn1LV8vdqauVz+8ot6uBbnEzMMgAX2BkOy51V+HHzCW4a/7C1ClD+K3H4jyVpsEaSv3ciI
vwJJR+0/4sBoqesz2zhjVUzhTylSUGIqbd6aO02Qjy+a5weS1dlkJiqZ15/tidp6auKiZr6H80mN
M4mIE0V3Q4UrINz79UAJVYoY6TwZOIpSE6Ct4gD6QPEQU6LdblifW6nEdT3c02YYMJAB1L1YY8QZ
2EBHDcrfwA3Z7jpaJTvZa4vxQYBSEsqAyWMcpHVqZGK5vxNSIFgD6aS2CX/GO0VYYLTaKgqX6s9a
T1Z5PsXs5/G9S0KvUXLaYop/Xu8XyNTmQz9AnwBLMM+VFLjhQEwaNLLLEpkFQG6RytlC2KOBpZ3b
uzchEgyUmoHU4FkNDGQOEy8U2CvHwyPEI8KtWI7iG7E0I9JErKK6glkguf5/ZPIUhYnyOuwuG40B
YXbGt1WaZz/K1sMsjlhmjki3gjjyv8b6O0vhXnnq+gMZDnHQyqk0V3KPgjo2tlNxizzb0y2qxfso
ZPIhmsSRX76UExIy/tUzM0EPBV1dqRZij35xOl4kc8PMq2kcj9H7EJ9dVZ+YPiHfDHGVI5vH7ahS
jUHA4ExnMt9gkEomu+JJaawO9MLietVLbts0DL4w5W57kt21J8gHaJ2TCeC4Am5AcLkK79pLUWfn
Ofk7x7Gs5kRc988h+dwug55VYt31ET1DnpCfI6SfnUIM3kJqukvA4TWATKAXKfRqe6/pATweY1HP
zj4rImhGfj9facxx54w4ky7lVlaIl9fEcCWVflg+b2qbEhY3sIr33KCwhT7kS8TFM5yJHodwEF1Z
VQ1hgsPT5h3zDV47UFbXuvXww98VqxP2BD3yktowAbDjqQfMh31d7b1qwVcyHX8xtFLEFTSZkMC2
CMrbpiVGdoIzQzzhmgNXWUEPjDtx0kbzD0fQnQ1UB6F3kAJAejgDX0tol4Qxo0so9Sf1SM83gVlv
yQ+DaL+5mRdnNeggdVsq62R2jmLu6lDDXc/tdmUeNePQkoG53HrCp0B6zozW9KHtDMf8AJbTbzrF
tmdGDw9Yvm8Z7KHiQM1G4MeQBlt7Q64lOJyWiN5FlJJhQHnqnqD6+CKYIuc8tLMbVqW015/lV3Fo
3pFNMcykQB7S+OLCAMbxV5gF1Ev5TmkbuC8TPURQ3OBEEXMmh0p4JDEn9jbnjmIw/SgJtb8w5vY1
djTbufIzjDEqOHNkNVGNHIZMhmJ8qbTPAKcjgYR2Borf7Fj9X6mgCLCLXcBQImTqNK5NM0q6TwDH
VTknZgmUfROvFFi+bZENcA+gcNTR1e4eHNm7MBTvn30KJSlUDktvzfDw+rMgpG4cB3h9CxY/0VD+
KeNcVpcCHzw1Z59U8AjHrhtNcY9hHSOEC36aD219VRmy2cXXycMXPbhxYXkZikZ/8r3hLhRjaCIl
G7sqPmKxcWKjPNUKEFczVcnF1SOcWCePzNBTrX9UPvxNhktQP0XJ5kB5KJq15sJRWH8gqpJ09UUm
6YORfh/9CIUBbIo8aEhE8OkcJudtZUptZFcX5Qn21WKUAiJbwjIL9Ca0ku1ceIC1/8RwTk0TxASe
eirxK+zywJznFv/CKD0ctFjsPJHy6Esxpg5aPytCyFDOhfINrIH9deT3cdTnb12o6ti7rp8iloV5
i2ng2jA/14foeFSXxPlS2sgSYbq1oTw3UYNyqUq4SyleDxIl5WjEqvkFlXKJPZR9ApeX20eUb67L
1YgMbNGbfC3h7toHoSZVZs2E5Rys4OqEL6+lUVz0qIxWO74bw8vrkObNy1B1FSgOPtx5bYj9h4wW
+LCc0cCD5ZEzfziVu08dMNMaSW6FrESjaq9lPouAbJ2zULbM5aLWJAJT5Gej5jqPELOPx69dmUEq
8R11OwYAJk9n45qOBKXoqq8HZo6tyIBGxLG2b1CAcNgEwGvKbwp3/2J/t6X8KKofKC8OywvpguwN
X2PJThf3WD8SjHB7ygwTE6OuXGUutgVOQrFM36x7lC1ygN2Ns1BiVTKUVbuEUsg/9JhsFHYsjPFx
sRJ1s3BrhAiV2w8zPdcejtVuTg6Dp6oT33rhUdcKL5dQ+xlnuSQIXR1RukpwyOWcaGZqeCAyPiA6
7VDdDaBXKyDRKLxlKQ/mbV4XeIQMubEflJZfmsLof82es+SEATaF52qEsaeAVDdY+IPK0th9S4pO
dAN7rWAPPNzw+H5KSHmdHtnBkg/43VTDs7NIxkRThyz8qLBYN79L8+TbMX/bwx2dYoAynjenH5QL
DcS/mPaDfjIVTDtr1suGwaNwREn1U990JpF3VOzJxu0ISZgINz+9/AJBuix0c684oouIk5Gji9pH
v4jwDkAsWlcrsbNJL+hMB2sY0CsAOopkw8Dt0d0i7MpxAcNmxht3kkZqbo6AZhGK6CSgZ7JuqO43
+ljWF16sfbNwFNUWUZKAWK4ACFVuo5mO3kitAAU/aMqFr3WUPuoFY/9+m3gBhZM/gnY3+YuAJLbH
gZn7cDSmZXzR6GEaUKXgocCfhogp1x0g6z+veyxQYiwEyc1+aXizUFYhBZcsgbuOgE2GXG9TRfx1
aSDOtrJ4KdaYOst4NDCplqTytfaejM/HLyze1KREztN7RzOCVZieHLj+nmmL+/OYgcecPocu80B2
kU0shSerEnPPXJbXXxCD7mmq3yCStyEOupLsyixRi0aWglQGtwhJx3RsealJoG/ReVeQCW72hM1M
0EtiqW1QHnXeW4sbdw0eFpWUx2rGeJvj382VRDIGHJQMTk8A2Y+siRkL/OQ/yT3hC0zpBKYVzUUy
Rn6rRGHpd+1j8OynHdAu3UK7WesOlPs/PQ6/rf0ghAZYzi3jXYCSx8l1FNahWPjJcGwigLQf/VvL
xQU0QYxD9ny9FiU8KvHjuuhHeTee+Q4xJ2PhRJGrXcITZMZVamw8VVX82cGoeC0i3Xs3yS4G0uX6
v2UBVuGsOAmbzqL95rRb/xi+WSG/T+hEuRpiESNlv44uutoKsOFh06UHd/iI16zt90UBYryM3GDv
76y0g+3z1WKDUxtx2/rxQ/IklUtYN0ZUcv/AKi3rpBsBZovJoAo8WrWx4FzY1SsHHzzxP5zIEml4
x094W/sc2Ma1leWmsw8vz0z/NHGXXEnGvdFWvNhb7g2UFSwaFNs6QfPd4YbTYNIOg3E0NzgI200U
LvmMrcb/ZdzxPQbyHRIAUZBC8DBDdhAK88dpLOuduMYOmJDtjqwtACRm6pLlV9Mb02wsoP1U4f9O
dMQP8iPabIIC1EywXlMhD508PUPG1SCIA64lLKFm7aqm4U6Xao1QS9FmQfmVt3RBQMi29/eCxqtr
T+QUhUAR6aCMdYgsBubyazu5zwJ/AalDla3XZF8It+eBzyY23JsPWUs32946joQMCNTNatB04kc8
AyO1qE3ym2lI8FYFb2/YowhDGnyAL4kXKzmzsu78lHseMrjJnjUuVhpdvhSKT7aEZK1FX7JVQu20
OPrE4TVd6oQ7BUtDAGCV49ajJHZarinOy/MuDySuXAwfRhEV8Xi8t3seVjHWOE8iGCPETOWuiRKk
NOs/ys+T8k76xsJq3L7GZYQlslwQU206HactTENtK9gy6tCbLMcFFsVmfrNd5HdeoqQysEYHq+tR
U0rWwoaKJ6MKRuBqgX9o5kU+rC8d0mIP2kL8EGPnla7ULlbL26jM1Gn5RX0VShnKqNjFzL8La/4O
8FvSDzueM32U7UazaSo0xiVDRT/D3iYSNvh2dNFccI/5zk1F9WM1dlQ9o3VPlkdxyCNsl5rw4yOS
mbA41r9+p7sgrNW5fA0ieoRflw87L9OdrF769Z1pLeHDxQt9q+cSa4iooUc3PNoa9THD8c8xaJNx
4WlZloSiM4AvQGV/PMiIhljfkMD9xIJ8ffMv5PTcLRuTkyOdM3xOIYLhFYY4tunrl550PArT59lv
bbLtY9FjV2f/FSginyHE0iUiP6zavWmuvOMdEkHCgoPR08oilyj/ts5nt2nVkVw4mjiuiHMu0HJe
eMxwutTIuhxaisqL8I5z4ASKHcvUB5x1i5aFLeDrBwOaeJ/RVAUV6VX6G+bBTjPQFYy5iU8sEe+v
OuMk1+LdJga2tqUIKbzeUHIZzDWeF5ypL1/PlSdKFDw7JH8aLzZlQmc8UhCWjuzbBHCKCjMMtSZV
H4i26DQASfEtL52ZMvNc5QsTfPWK8khazmwyfLRiNHN3wqS53R5Y4AklR4G9mFp4IblT0APU3P1i
g1xCu7Z9DM0iWVixCrysOcrR2mNA+crieq/WvB9fF71avKdu+4RP3Lv224Ol9kR8ab5V4NeknN/W
7wd5f4N7QNnPHnj16rsctoUvFd2ZpGsYDUwhxi/5Y8ZTTU4cO6aUtzYSS86UH/JlqvffN3Zj+ECZ
H01AneccvkeVkAkkq3hJGvZXTjMFESaS3j2ubnzF22BtOjBczWZmFRw6nRp9eP/nGAWnzaesd/pz
/3n2UxrMRtiPR5dwBXZwWwNrrmBJcxUAw6+OwEWwaNh6PQpWUBvUt5gnM8bw9xggnqvVR8N/KDF6
Ro8iosPlOz7jQ5jh1sD3jUQyEynMBnLrxjfB/CTxm86T3wzHTy1g71KkQQwpC1os5zDg77yE6Jxz
qmpi6RA7uTO3h4G0zRfsP7y8f7O1M5lyXsa9rqAbN75jarqebTJez7k6gJ1jim8COLG80jY+x9tb
+xlKl3XRN9vdUWvEBUo3U/AZUBq0IvRyW/j+P8lZ0SbWhzyN6crBcnBe/inlhWpo9jMeprav1D0o
o+CTyReJ3/QipPd5Y5NXdB01UEbszS10EXaa8YWPnjPLCx7wXYyN9/nQw1+Mu3X2k5fa09LUOZhf
V+OD1FwNKPkwZ6IO97gJmrJ61/rHzOknp/ZKV7arRK2ujxwnh2v/okN0H8nhTZ/i4l8/9ttCjbhW
NnzR7KzNmrU5sUBeE4p5F9emoAtzNAjQCMCdEXA8+bLp/3YaE45KenYac+BeWyHwpwVjbYZFq/+v
V9/H3orgHOdcYVRy2EJN6OofD8YFA6LbqG+w+n34ZTQUAmPEnKvGyWEmajf75ZKgaaqwwtCLQOz7
Qlh/4U0UhPaeCP7AGM4dbESHdY/IK3NmrMmUWXDM0c/EuORY78AeRnrFxmnSzabZtCIvZ8SAWOec
9Q+jXEkWuPuo39v92GblwAFYXhHI/85/c/HMBrgjaqwlfnpO6Ir6f0Zos0fqIoWMuTHaRGE8dDhh
Oo+6/+6zJr/FYbSO5+csMnRAiF3/zQWAMvipM+cRdnBJJJ5XQt8Hw5b0pJypxEwjJCo9jn5v3bgL
hzwzGHj1/aTm1gwuiLFhXvZv/E6sKqYx+iO74PKWtODjFtiWUacZ2KWRTo85yKHaH7ptL84AFFhP
NOnMTg1FwedDS8R8iQ0HctgQGKx3THWlUg/mBzmOOUDuHi0jG0yerI8ZONjly6dmrPWE2KY6Gh7j
FRzfGYPYSDU6C3OTjzKptbXcaXrbecfSR1JUKWAmZcOwkZkH/39FiQh+UE0k29CV3jWJ2KH0aJnN
PaRY1Iq/jsYJQrRqbVJlKrdc13DgpZM6JUQNScA1CJyqc6ANm/8POogYFoPeNRelvbB95MuKAH0S
tb50aCEY8HUozabo8mT7UBowDen0HozoR962hvL64O83WLC83ic+7byi6i4lUrUjuGNMLKPjXkPL
NpRikyWGcEveacu6SQMVfmsNTltDd3VbrQK+tEyZ0HeQckM6FQ7+i+007ftfd1/HRosOGljlQoo2
xXNEmt+w15/K2mY6qnYjHXOAkFzcql+vZq1x8mjMUO14UujykINNv7GY0SYBxiZTMSpjyql3ndef
KE+5wbR0dYFIhurF6HOnaYnFiTK9a4F4Wlz1AI6yo+nm8Y8abLywM/+HdP7tRWTIGmFuNJA5EgVK
EEdyWp/Md/C/0fmLorz78ty2YHY5TJHi3FeLVNVUQHaDifo8uGWcg7noUrwlGBuxDwuuTFpf8CNv
q/6CF6RtP0Fal57I8QApLs0235geaTvclUv3hkoumG9AfnpSTo3PctLHD8TbmRJLT/9GF/29yjmK
F6pZtlbt0RSrzvjJY4elF/N4TW08BgVnAAoXF/wm6jr00mcfh2WIHcTmBpEnWOcp3U4EsHjxuWWS
zO84tpnZzFwwETjNiqpKl1k3pdKjEKXzeRSC4RGx8TU02h+MGNYH8I/1javZe+wNlyD2MV4lBkDg
7V80OyzqJkIIvNtodn2B9BB/woG6lAZgHfUlbdayPetd8gBUVR/0RU9QfwQN8EmXaC9kbNdHk2n8
gGYRwZE19JLA2cLitDGLNaO8kLtTOb3muyyug+0J4uZWiv3l1h2aiiHGpU5x0CjZLdzolgyOdr7P
eX4enyuEf/6hfkvxoQq9aUnwWLJEg1AHCkx0qjf9WkzcMUYAHGD/d2vr8nP160gdo1F6khUK0SgI
KTfw4T3Jf9wblhjhN2jwDsrBv9LRxRdt0E3seinPUNV27g6FpWMmjpwdm9fVe6PAHAvKtUv+McMS
vy7FgKkQB3sKRTnPhBkbo3dLiOYYQk3ejF10/HjKEUytumEcjSDvpg97v+fHCehn9zt3FCCrdwgk
P1G/VqpYcykcMWm6HPqlbg/2/4dKr7KKnHFY+fRz+BazQxYq+dCBFUJ1lNL59ohKDfa8hNYCLeYV
YswJb5s+mGceoJ5mOQCcUNGdytLivO4HqpGyjVgcnzDgVzt+Z5TGENggXParrSDqW+XPYgcV9B2m
DgDcXsChav9PPv+KHbZgicIB1yBMusHiK9CueFBqfFSA/nJuca/xyehn5JgNyhVb8XZFAUqKzg3Z
IZEMvWalKrnagu0ZhuWxTsj+4GV6rB1dG7ziwFj76tXMfNg8am8BKc5hBcl3rsV2nUJdlcNrNSSH
ssNwEfMeYDkemOSHJgIwQf5iks5iw0rmCGNsBhlzQvVGKcy7Rnrrokk275jFEhCnBh4kHSFrMXxq
U/EJ9LzfNNXDXc+uggFG3N17EIKiXbjQxvNFl5EujJMXsJbO5QMczBGHozMiQi44aJ77CIqXy7IN
Qpv4RGyl0yWo12nNp1y0t4PSO34+inPJ+a57DRytV4EO7OMs5RgrAO8hrXVZE4Ke8I76G3f70uay
JMN/B2fqh4w612hmkoQPK6gWVrQFRZhlfpClxCoS3e/5bOOqT/MwzYaL1gGHRX9ASoIdNEJcFGne
VdW/qEt8ZnAS7VAG4IPqxUPU8hvezsseHMIqwyHHdwZ8SjWJOrHt/zYKmAhwVGKXqwRxXl/XfrtF
f1VmN0aQgS9kNr1gExtBHFdX2DDb5+sSmZwO61glXpHfqbwbT46nslNtmnbjLsjxMgf7KdJlomr0
WZ1v27UK5OXgAa6/QW+JxSDuEZi/UgbKYSWhrWnCG2t9D8TpaDPHIIspewRcgh4id9a31vTEMVuJ
Nc333ZLUVSPa7SzXIFGBshcbzGfLoWLu8dOEV/5lRmaO0dhzeF8AyIG2vizgXbTWsvzeh8UbSiZE
+YxqvT/ZB433KzjZrMPzST/NH8vpcp7Wzw5Koj7GJ1Jeu+PxaxdrFDyqkgYVvISlDWK07YGQuY9m
UzjEkY0ZBTvahG7svrx+D0/dj5TQVnQVSf3XQmJBux8rc8PtI2qHzGJWm1wd3RBcznyQ5kXkK1u+
maCUVd0EYideRswo+5yka7JfXTbFy3IFJ93turnuVaCkFoLve0SW9voevGI9wXQhsgFl0gToYr8C
BXCeUE91YA2d1OS/VlkfKChZSlhowzGAg/hf/tz9/zERcri8nZrkFRL+vIw3iWStPfJhFX5SrNKF
1D5M3zzwujmBOigqsY+35p1UXKjNu/IEenHPcQyNvyIrxlnyRvQ2FiVm3OxduREG2AXc7yyR9Kti
kV5U4eBQlFxVDPQMzg4iOl59uLV63ezPU9ruKbmOtVv2vL6+hX0MMQqwVF/tgC6+Yi8KSlc+aNVk
V8zNaBD3Rykhx1JE8LXh9NCuA+4eye9fpHd0DjNeb3bS/Ts6w4Mub8mrd7rO56H0u2WS2C6VzjJX
E7tOhk9hV010jiVqerTTOyzLvAmGC9BYT7w9ZRSBDQO+qvs2SHZgBf5FNuT84grjKL27ds+lIoZM
XqQ27gzLAqtREIQht5EOlnvSn/4IYBi9YEWJrM6udxE5vx25uMnotXnU4FFNKt3Sg+vd/GC+ZVfa
8kv9eLYkfnIIcptz3sUtfWvF5YG6cVes31YLEHk08huW3A5mOmlkR3l2XiO04oe3hFtESol/7Rso
x/9lZCJ0Twayk7BoWGlEgPDzuuTgiy7JwlkbK4x/gq8ZcYmRG0fVW6c0x+YItQmF266yOfiprBYr
R96u/HU2jrAeTEPDhwQiMThkNj1w3Cd2yPOB5d3rXTaLeLkLY+dMC2D3osqv/vQV/+HpcrRcWBX9
NA3tFWH/udlorT7+pZDtE56TRyRyzYeyLsqyXk2Qz241lBJQmUI0TUdeQM5dWECPryEbukdh3w0I
43O09p8FpftGgujRFh621P/lXQ1AJB+aJGznO3F6cnb1ZcAroy0Y4B5dOxL+uQDPndn0fMk0JDtz
hbjLLvPE/mI56f2yXSL++QCuTkaUQtnb7rQOPDDXLg6QFNBSrueJ9xobgQhhPscSnaF02BPXsRrU
IeTYK5wFYT17cF036KPz9G36L1Idxh2yVCbZWUm7FSA/BsU43s8PDjWehruI9oSGxv6AwHC3kGLT
nuC3DcjzCYnadNJ+VsibrfHiXo/H7IhzCdRvZby0JcOBWmZlslrMCVMfk0BQSZm1mYzQareYGSBL
6YE4sFcwWRsmFtSRihrAekLoyDsxUyZrj199z+Kzjseiq0hctnuZcK1uapd1OkNSwbvjSYaCEXr+
eWXSZ+VYtJ+C7syFWiHoHI8ZxVggU9pCr80t48Nyv8NnGNA9xriLEDN/g2cjzscH/tnzvgbwnL8B
x52idHh1NVpbsZucvDkCytGGinpIVasFdtHa1U3/6CIqBHSbCmqVeuMT9NBhvDYujljscDN/UJNm
ywDYqwIWXR9MhvD7Mxx1hSeknWjIfwkTD4svTAFW9S+BdB0k5GLp+1rbv3ejzM4y3rh9FoCuzf0V
eEXyyTLHjYsfUV9lT1rSWLQTqvEMM61Tbs7QHoFhLjlrQkI7fAAiij290imuvr4z3fhnJg4zcQ4l
ZCJ7grBXJmAXxetgC9Vvc5PM7UNreP6HxEb4Xg5EziZnJT0Iu/+4+QxHeATrx0krk/JyhFFEhXHt
HNHyK1ZPw7ruYWZC/kCiPPGEs/42dt9pkLuuQF5jdjeTbNP9M8iSzFJgzJui3au1Xh2EU9NSjJEo
9/tVvBGIUIC7WL1olZXV5ThppsVTxYH6I913s/nXZn6P5xITUXDwrqlrnIiKtDfxWHeq5L8luwKG
2WJ3eMVr4k4vBEQWy2m2VH+pzBYVLGtIR5ytiopIvgI9+zA7C32ChskbQPxsn20rZgdcWmwooQu/
i1ePMHmBjsKn3zIwGdsDw8upKRYOw98keLhcY506R/HuiF8gM18qIOSvWutyIAZvu4iXTkJ4QtP4
UplJOaxiTrSwM77hC1FLt+/0ZwbzpuCqQafBnI3lBxzENNjfMvEl+lWvR/CmGjXtBOxUuwHjeQDh
Z7Smgyr2rmhmiuxjHvTuOSkF7BP9fC0g7pNyGTEVpesrt1zZMJ3rpJHqndv3qvNGnPP2Ng60JTBF
zc45f6NVxJLxX2bo+cqseIRfMe/sqf4AXxk9ZKzn+2IQp0bBgBpm+oJBLCsrl3Qa2aaCsl2toNFv
b5lNH14BD563H9iOChJJPMJyK/7NYhVXwYSXRB/e8aOJTGv0ROZN/4acT8XKDUC/dY0hLtCf3K1C
5OBE6xK7mxPj3pNWmqSlNiC6d5sWCPDBZVW2DcBtQwzT1jThBmtcqy7WH/LlmGHPKy14NmC4hPgU
kY1tTCcTNN9CYXof2DiDb/VPe+1ZyQSQ7/io++0nhs+BCATACTPhjnwXfhmrA1mRBPTQw5/ZwJBO
i6robJjC/YbR02tZRH12ZQqaIYHsXMe4oIBqmnpNTjippcnUA1qgEjMVUXrvTfzdowJelAeICfnK
r/+cUvOB8qFwWScDybVZv2o6x570SbX2UoJHIzZv3Uskt41so6FFDAkheXQTh8utNYD5jZDWGScp
cl5imzilhxSFZm4Phss5IyJUpx+R7OfoZ08+rHBG6bVbCY76OJr1msk6QmqlLoAZpnJwvUnxXGdA
QK5y+LhSQ78RomFubbqWoi2z7M/NEdBe/j3V5V8XU0/U+22/VJEm765oaJOgu3l0vCIU8f1jRJlc
VrLd7jAmvsuD5rEM8sLrFW7ZBaQSb1W6suMbpd7xAuB0HhnKjtlxzcy+FDYyRU9gxWWf9GavSEzs
JfvK5ze54C2TDCNtM+xhTIvnhpNgbFSTwsi8grcHD1cBYV283KSJ2HlFRbFqrk4F3tYR6uty3m5R
5CPmM1JagE6RR7n09FWZHOxwn/lnxhIpW7qUwz0bJRKeuvzuLRq4E/sAQw7gbOWw0QexJnbZNYLj
mCoqhv0NrDmN2R5El1DzXmAoehY54OI2DvHgQOZ3xFs9/9fSJYvlBm5ga0EZDCtEHXHzBhsi0zwJ
lNad6VA1qSi4bQYQOyW4lPV1Ern2d5XrqJo2IqxgXVOpvbWzjYC+AETqM016m6joS1CayKNtQFme
Nue13stSPxFCOhG077cZhIRplPTuCRBs9Ob8c+UWF70i3N12YbSLWYwQ/8Rf+hRQM2XmLJkQmSe3
IvEUOZnuWyYtlnFBkdy6Q43ScsZI/zfL+Lype8a/jjOwzJ1heU8TDTpWeH0RSEHxveF402Jw9FB7
vKwt90A2WuF6S5plJedpDRk/rf4uGHjVXgaRqFkix/b5H/Yo7gzSQAGF8+p10/eDrxXShu9qpyXO
vx7HEeuXuisbN7UwKTAxFQ3q9mQfEhM2sPFj2fgBD+cV5BGJSDzFIvW2vwEY5aTI1HNKO5UMCV1T
rDGF+FnVJ6R/kdO6GNLnKcdgeqhFOxkq/RN5LQTaSajJWAFwjDJA8mJzTo7n2qU/AGKo9EFMC+bh
uLFpEz7eA1QOUpXtt2EqPLVxlqfR4YnBCsdgV3ChTWbjMdRdLPZenEb9akm4O2+nTcxkjlf3mPDn
j8aKttiKuooe24CPvpd1YULjPLHreqdfej+jhRQsZXDItRsbiu4gqisYm5ezIQtIjsDK+61tayJE
5QOteOjzcEw9UI4oSZUzNWbPSTNSxVMzgLTGPpb5iACCx2FLdxJjDrW3qMiS3ntPDsXQX0Bjpwik
uCNhXSh78APHhDATRtPj4ez5cHSiYBMVXMCCVfMSK2FgKP8OC/xQ0r8ayhzofzzgc8B0pX7BQBxt
08M2xy5xWlY7Q0S3bFk9RjhG6iVPSgIc9j6jq3fB8G19ja0T63zMjLPZp6eX1IGYYTUY41ttjHbz
dcdqAj5LdgPF5rN27O0ST9A8ZmKE4X3yjs6aQA+bAtbdapSGiBsyIsOqWjwlEqbtQvv0e7COALft
KkGgtn0jN969yStMGRjTBeQbBnmpv6KUVsAZawR7GlP4L67pA58da4SZ7rNXUTQwY+iIAfv1dRJP
AnQ1wGoUxnqaNWPOfH8cANqsr2aCFEWoK//3vpKm6uRHo4WP++uWdU71twoGjhedy8Cs194V8GVn
cAAeGf9RmduLqrFqmJwSY5SHOwKiMKgGnb+EfBUxQgQtr8F4LIlvv1A4uUsl1x57Gm+J51hLbZZY
ET6/fXIE0roXnigKSOlODMrLCACQV9rPvAxiWuBW7mGJRjHQKorj3gd3bgJ2feX+FOJpRSBMVLiC
4A1PDtxPrbNx3M5SM2cckRXrzF1lfr76hdEUSI9Bfi9OAk7jzm5jEKhLSrvUiRABjPMn3BjGQFxb
lu1Q9HdrYJFgzfxX69MsAAlABK4Bn817DRqljE/d5gfEiYR8IWEAuYOW6bMF0K6ENXUhmEL2hNf3
BmoVCVUzQ54vcMpaG0VjcXOFKh7ZT+aZbmnh1M5yqfgi06oxOHPpwQOlaYYwNtVFfrO1xHumVEGq
KNOXDkWQ8aBG9WU2WIrXMKlpjmwt9+VHsv1L9oQ88ctpEkRaQ+pAN0Za0LYvBxQbh6mGM9DoeeNY
f1QtrqNaCzn2EEA1r1JAm0ezN9w1cROAw/XXsY1YcfdXktMyPDpa0BeCICq6kwhSrovT+X9HNkeU
QVvlwnQdiR0j2+1ME6BcHdriqFYEXaC0CLw8PzGWTqXYvdY+spJYybfLEbzYfhfxX2QopiehYMup
ZjVaBohqRX6pDfDOnch9piHB4R6Hv9oTvuA2TtkR2QuF2ODwTgQBnlvTTeEsbrm8lboWpFXR9fty
RD3Avr6yX7pFidJ4z+M2UxMGhzjIBT6XkQMZ9bafg8XzZzQUEpMHq9KMRfLxFeSzY5CE0by2p0uO
Nf5BN4zWD3kGQUXssMcx9ZPw0fup1vIa9AvJD6jLWRMSzhMRtx+tsdEaZB0kkWt/WcDxGz8t3adw
Qi+wNguSqQCi5uDudDg6Ojm43KvG1vbOdCXSkQ99ISaSs78pEgApkm2/Er4xhnvrtV7dLpWxUF5w
CLCyYR4kIQveNPY0/ruXO0TcWc/mr9eugia9KmgOuKVi6P+0J9pmQ0XDXH5RNX4T1VB9Mj+6yS+x
4gasnEbkJQoJ4GM6wG5tdOtz/oEefii7u/jb8PeGuvPgnJjENRGClcFYoB17xgQ//BlZ1XIHLCxZ
g8LSYoK9lYcTjQ6aHeVL0SBDO+NaCpTbUdkZWCP2e0p4nsLDmgTN+ZSzoHqLBnoS9Xu0U/uAEpqB
05/fmlu7H//Y2RJJn9ervCQ128eLuCnRZq/OTAxHfJCOmx0B9gt1J99PQGeL1QZ02sijlE16a5P7
Jw1wpwf9uOdppXE2WQnS4+sk0N/+p6PTYJpI5CJQPJ3nLx0rpC2bFEsUp0h3lZU8aN1JURDNDITQ
+IE+8vrs6T03NUTWYjbP79VFarpId4qg+ulI5AeHA0BajfMrX9Ukk8e6kruMfcHjGWRkVJp6KTf8
CWsi4DGrB62JxabfdO5Y3FE6NaaFtZv0S9sj5ELjG1cee4kNP3STqPnNK+kIwFTYcHfuUoi71ALn
lMLDgv8VPiGNf6oAzu78T+Rilz2LJLIWVDYqUnpiTceT0BMIJhbijNi9OY7UXEd4dXetxYD7yVnC
E95jlhIhe/1Qly4C4otIGklc3RYKlbwxj0LIsNGI13MzSZW/xScfadSDYybothF6aUb0KXDiBtSd
J3dgPA0ca1d6H/emj6b3MEKAqqkzmQ6Iy1BhABS286uZB0NkX6JLSxndJ/g4J+ZSls9UMN8KuJ1A
fLcMF/dN5x+0GIOUVjcW+s7/xFj227ml3hoCgak/faMHM9YhIvrPwe2WpvvjsUAXi9VwUukzn1vt
MHRjsFjSCs93QXEAxSae5xzoz7MM8wWwjiI8QnqG2w8Fw4N45K6ZR+UWFdx1U3asndS1CnjhLzaO
MhOhmgNhDjf1cvmYoTPRNOtynQ+ApJSJvtZWmFcumFgkl2AVKmoynFeU9IfJ76uUdYEfs7CCdAl7
k6i10QrWZrkCTnaJV5O0z7qZH8o3EhoxKHALfiyDnquk8o2EE3nktbRY8JQ6FjEPlidTZ5wC8Hxr
E2w2fj3bD+hJXxkZNSG/UwVHkdBeQ0LmVUHk1IHEcbUH2nmliGMC3B9rWVosAgfCk/RWINkKOzv1
nl0tWnyd9NVoyLtwtWeZN4CSOkZvntf8rp64nVE/b7hXj/w314w79D4loU5xC5+iCuvAa++4zQUg
qRYNeFlNSrvK42asuO6onfIhKAijbwcBnW/brZmrsKSfy+eZ+/amzfg9jnM5eYSTs4JTjY+bGEq2
oJ4+omt/4ABwKqhtRXk0Wi/FsvJrVA/UJmqYnx0eQXTQb4RocsI/4YxusvdFXG+9eTyPYIHt1mBe
DXgKpAfVacuSCAl/gpO9an3pc5b+ZJVPI9qU74lPVHG8lxq9nztYoJjCdpeUIw5Q/sgo44ogXUsD
7HY7xMHcF5OYm2oVX+otcbTMVXn3ykvYDPhaUpTWJIUjXkxuz6njuG8x71bDHNSl4g7hHD/57P6H
Ah/K/3IDZvgOSVSYCpZqaYWZHneGs4fFoEY7/MUiZIj+Gx/JPzF8mQ4gy1MXUL1pf46giZADM/vJ
QgMsfw/AzRbUY9uSf6/pXyAvqUhmKUABQSUz56Skz53rkVZS1Gax4J+MVVQPFMMQNgZOYoGLuOvc
+6Wrbdntk7mT/wYiVd4lZRB4y7PS84TOzYnpJOUNcqNYnlhnt+XmcSKN59XNVJzqyuzwiyxZ+4jo
mIERKEsWAJ12NPEr0dI+Un6pNxRK5Ci98pDOMLoG3wb4k/H87g0rP8iSQcYdEPEVODRYDYaL1J/s
ovqnEeUZRS6AHYgxhw1lo+V7QwRGyWpJ1M2zsfa+n/vGRmuyus33WGpyGTpo+D97/eRjd+ekH9m5
rpNGUL4I4QAXiRPni/96McqlKUsuV/IlvFBiMFY58hrqDN/GhUscyOQU++Pl8S+kIFwCdpBo4EhD
f/j/V2/c2cMaNRCOzVbsG3AztIlZw9uIwkvdHXp9zDBx6xzZNLas92nlbZ8aPXNSXSaPCnNAmxeC
wIOr96ChmbGDKx2QCArVPOmnoMZgoaVRdK/iyDhjHSv0jPFvG7mZE6e6KWfngHFR8URNE7t+9iHF
SyGHd7lloB0Fss8aEw5GE34782lCnOvx53VuDbSO+KlH9FIXExppKZsttLc7BTUZJM2KcP2KhChl
ey3Ljhi4afvRs+5yzf6UW5y/pqvmiE/rZzwgiD0yiT5nHNc4l71Fa+LwxP59KIvjS/ucb8iVh4e4
10gZgr44HumX/Y9bM87AnILsF+YZg95sPzCQioxb0IsfCxK9Q95YUQt0ZtHlkmnH3ASHkfmIj/2M
mdq8ARqtV9Fwxoy208sr3U/+dUJQUUEAdO9GB8FpBPeltu434+fcxU1+7+xyD9kRlKyWY7AE/FR5
nQRDfuNcoZttz5XA8JVo95cmL6uiEFHzSw39zzHQGIRCFrDueEB7lO8OzNogWSSwtpNEPm1SM7+X
1FPYWOZyiWyBIStvy3/fIhaRG87OKuAagz2gdXWabG25xpDb0svcjiYTqMXCfLALFspb4yFBJXsP
KEt0QyYxClNQfXgXPzZymHsOH9s+ZK0KPimkqsK1mvQw5VjA6ZhYsc2nkLxMLmaOKWIXKXg+24Cy
cM7g0X7OZXfx5W0C5DsfLaeuia5vXj2T7Y9l2f4yDMVKQwI3X5KQfhgloJ68pJR/GPNzOX+dMPun
leirVMFFkWota1IVs2l3a0fdBzuhgJ1ZUnJ/z+3HbfCwM3GLbEDwMdSw2OvfSu/taYiOtKU4L7GA
peciBYhLTJJud1zYSPcztGJM3Cw8uIn/ZM5wGlTgyTj8PvPIdmpjnA4MIZ78XTK1q2K/JuPcG73D
lOA+56GIBj8anKItxC4CzdcoYYWznNeE4zlQ34BEfw8BDXAxZS7AWZaO13mFGfGzX9xpQdo9fM/b
p23KtrVqIiVdlJFa7ynpfGK4Q6ANFOrxNhoo1xYi3lwYlKOLGP5ynYdzmMOceO5RXM8PtZQbr4YW
3aGx+Iuk6guZYsaCw+nvw2tb1QZ4JkCb66LAPwAVbNnYEklVjjM9UdvY14yoN9DZm60YHuycFmYe
WfxF3V1Q1kKlXTGUc74nmAeqXZxssr1pEKPcq+rd8uTCLoGgbnx5vLD0JcbhG5jHzEJizuJh591d
H1XB1SeY/LnmcGrRqnc5ViAAJV7e9/zsBTJorCwM935RpX2UnEXYsXErPHllT1bY6w6w9lXDFss5
OpD5OVTBl+c7MdPgdhmlewRHbup5tS7UOZ/GUSgtIF5j+Q3I8LBiifNWedFVKQlk8NRPDW9ebar0
NULOYhqw3JONioG3oQW7rAcuX6XEBCKLx+oV9YgHjXRiO3VIwgePFu8IEHFu6flhKWPtfDEnrK6M
KhmzRki6bsJczEQM++402+oXCkQ1phdvxUSyqOLGWX5i5hCHKtibVpisX8lAuCAAY8iyfNE4CTev
TDJPJnxIUfBtwqRMyTjqZLM3DRnMDhYab5FOeSqXw6OKJvIXWDgDS8wQ4TE3ttSqaD4EQJQ6J33H
OYAfA/h/tPX3HftqrhB9lJuk12FjwJRRgagJJnpguXX8vnHtWsULV95k5tiS8MArCOps6FNC7TPD
Wr/23QkTGiqymcttKE3rCsPvHiSAFEdhSv64mnRSTxidR/i7JbwdKZgvnp9RBuDLge5x8z9gO4MG
cCbs2APW4cyJknwKYJGkOr0E2ppQJ2QRLnlRyXx+NBhVd2/dj/3NxWV18YOGS73TWys74JVd0jus
zsDb2g/HyEEMYZ5kfZF7aV1HejYfOYEbT7dvfkqMarOyXH73vXhKK1DUfi0TNGwPcTi/MSY+YpKw
UMBLE2eC9qoS0WFFw2YvpXHn5O3H/zC5AlNxg01D2rZKjKf88xaXMYxabrDUaD0r64k3H6YkwniG
wUgt+l2h1bvhyuWwIuKIe1PEqhyesa3XZ0o60fsrqyfYqvQbUVFTKYEmn3iek6M8LRKoBETvS1Qw
r8r1Y58x67lr9jUFSJIPDNbBji/rl3wyHqus1qnPmWlhws70xeNRyooUMbmiI+u+gmn/VhfpuSfo
5Yg+WkNNbkiaCemvyk5DVMi+p6XD+MIT8brjC42zi9dGeiH8cNtNxxqzelk+iX2RDZqjAVLX738F
5XwjPATeq0xXe+0KkiK11IE5ehqFU6yly5xqq4X0nBKzVnObxDfQMI8TDnlmWsDMM3sJjbRbq36O
wZKd+6aFHW2D8tUoSvlZeWcU81wnObdfJlBuSfLo0fhGZ0HkAciTa0Vg0ELdQeMXWDXJ0FFr6s82
75vYRzRRIgT+PEP+JKX56stITcPpigk4rJ2EM/J17bOUHXQnaN8V38hMupfndz0CkmBYIkYRZOPW
i7SQUchQwtoIoZCR1b690XWsCTwvVvz3BITFmA+XejebtC9hkcQMkhdzkfSUCQUf1MISme5hdSc+
6iBQ80kIw1zrd5I4N/W3YqQMOBVjAvUYOUAfKIOHrVPHwK4vJs+pvQJdj3Df89icvb7ia9MOXvdP
4wl7MVTXU1DtVArQXhWDRh8OzTkpdgXs9dKxUGVDMqS5VytW0t6qQRJGwNkj9MGXMF5gyzNTCl2c
NlMGzqRWEskWCLPjZzAfLdQ0ngjfuzBVurEV2KJOBOKQ+lGkM9T6XLajtxQFG9u9HCdAbw+bNIXg
mVLlui1nNnAK9slfsmFBlLkj4VnZ3h6vG6bnrTJKHufJP0s306rSD/GbwPKlo8lCXs0MOj69i7oZ
xhUXx0nLjxTYlq0glQ/Nx1rPieE+UYlNgbWH1mazIjIb5DFYKI9Il1ESMcvodUdjFlVOBU1E9VzA
j3DE44egn/tHffG7fXS+9o9PadOW1mIeL/dykP/aGSILk1ZY21AX0X+vsQydH7KKFyXPrMKeVgRb
KqB/gt6I3wH4P3PaQ4BMrqDF1eg7fc2iCYQUnCSQRedjn7zWdOXK/4AE5rcawZFvPO62bH+aAGUB
w81FNmWtUEFGuftqkn8aVIFkWOrfM1m93rEz/X0jAqI5y1qS/Eg2hnhzMMFCAnNxjLNS8m/gHBL0
EnEooVuKKBUmeNx92/r5aaaucSkDKYiguB4KSpBeLl0NTPYDbkO0MI7A+Gg8kg7zuShNBXvelB22
BCkYmqLiOM9gfuBEZp1d19SdaMQEgbD9ymQ7IgXw+LUFl4wSWIxPHzUZuDoFc3TEakksyRJ2rwgW
mxBnwhQUTGa7mJPSqqRfvVJXcDZ2fUpEOC0lVg5gsGbPvSkfnaxQ4VhSnGN7Yg3PV1gNtMSAPH8C
r86zLs9J1yfrQzXosRiZpWI7HhzzN/5wWNnwuV/rWAP27Xe6zqsmGQTFrIvKvZTVXEfqP5jqi7YO
iXKS0fMdIWE7Q27pdnGzGdZKfCIin8O32EHh3/lkLelDQOANudsDm5Pa3AYtSUrzqpVjwD8mlM6i
vt3jdOqs38MDXGjM9RNOKi4WvY8rQOypa5PP1r7LLZ9FubHIjuSGr3gHeTo28lo0gS4vyrXI2LBc
MfIsqrFCjsfKfOxNWh5vsF0xtC30oGV5PhSKMoOqtgsVvl8i2uCvtYwR0Kvft/x4jIkkWUfc+r/f
1gqRTcck3auy2HMcSqQ+gvXWqC4a47CBA6Mb4aNsvzE0l9PTyevPTDIWYkIqeimOEpPbaYeBkY03
o35rYeNkHp2nA8snBilx6AdPdT1oaxfvoeqR0dx+sMaholDEee/vGvItow+GSJ3hiiWRxlM3sFSj
rnkVbW96NxQD7jZ4TLGr3TUsB03bnxm+Y8kXZPi23lve0xbYNB19eJBW4T6e0YdzkH0vd7VGdgPJ
A6WW30psjQ3oVKl9MPFdYMY2xbYw5KHoXkeNAaSGfITiRFQYl1h+1IXsz932O5XX/zdm0NL3oD0Y
l/7h1Oph7i2B/ugDibF0AyjbhyH7aMnqSM8ChclBE36QTCLKb9LvgYYMNJuBXmBF7Z9JJ5S8nAay
+30lslsvxov5vTNfTIvb+iAcGfkSnS4Rc2njr9tqVI2ChI0Fib7Bz2OMz8xEpcvgXkJwMP4EFju0
maulDM66sitC0jGyWWDAoMcQDVxEBPUZ6aP26R7Z6hGCIRmmTfJs5Px7WA/vTXl5PYIoiynGrgJ8
Bf6R45kFhSpDI7sSlUt0V47q6ED+c4s4YDjA+T4iTkRzud6JK/Fbxkk/5n6EczK9gX1P33FFXMez
3qRFbdNgRU+25l4bydwGhLh+BJI0WEu/M40QGoo+5kM+4YdhykPxLz1N94C8IzPIO2YbuEFRxUkL
lOofAoIuwNTQZY9d1VMud4aX4rp0hm99iNVZDGdXY3x7yqjikSrwwYgukgdufp3BcQ0h2JYtlc5p
sZbUUhyabrCmin0ak/ylVKj8qewZNjCP7MrMOCWJLGgTRv6ljY0lVeztBFB7F6mtwofEvtQmph+A
dsY4iGpW48/4CI4LMS3oLBxznXbw6WCXd+J2S1M4Sh2u6Lg+24oUxsStMHKRrpHFCll/sDPsn9ne
cd8ZQjjJ13zPwZRXPgW8KlQZ49Cj8PQy90sXbJqWtmydfihaEE9o4U6Vif6wNd0FM6aXaNIX1GNR
nrIBaWHDXAI6A1ZDpKBhCHqEOnffueJEpztK7scBfjKZPxO+cn7uxFTmIxWtHRF30y0x0iT7w3bM
JPtVupI7Zyd6IAnvuQXfjTNIcKjZbBjqgVGfL6g7/hTZNq+xrcxIDaijAQBC6lp7PjWdaohMXGuN
hRTqcUlN0+RDOmJfmXko/32RCspxGi1E/FkkfSpRK+/LvsHwGk/lSSRAzR/S+T4owQiTE8tt321a
vFguGbqYJnLhhHC/13p/QzivPbLLSa5X6Mj+TtUh55PrbMFGqIKkIR/TcnD/v7xxw7pQ4l1nTe2l
m+3WjUPwqI+138Rbro87Akupt4BE9LaZCQbE7tKXhw/1u14SKFTCBzfLEzL0dH6XP/P3zVBV89s0
HzTaHyOBCu7N8/uhLmEbdIEMbNNGfa289p+BnFvWhP1zWuyajj0prpxi/+U7tVNksrbRjlk40CIa
9lz3kYlAVmJlJ8ErV0Nh5Is0UnTDu/rqVt7glWW8vXdDaU5sZziW/2IRQmrvrxdbURuB2u7iwdzl
kGrtxosDX+5hcjQFdw9+MmKfMS/pkELU6ed3gwygpDjRCpnr7E1perG+tVMctFo0mspw/NlqhM/B
4LKpUqOUS7TPyIXjkTVov9PxF7TaYP8NoGHxCsjlQZEtaKhyrzdqCvvqgNa+m/Fx8xw+cgKexXzi
oM/81hP8awI4y8RwIImM8Pw6l3fOXoUsx/tjZQcKlm8Opgjouvptc4lbb5hwOLuEU2fB17TucRDy
g/Q6MXj9IPXUNs4uMIWXuoBf/sNUD+FjbKnj3KUGyAy0+mX/yCl2Q65SKLZYak1hqFUvPIRBllCQ
/co1El5Gg09Y7ABjXxDfbXAtp33uwL+vQomHkYaM+Nm4F/xelKmUYeA3+gz7VPY3QEcta7f+CZZe
Fj5oaM/kH1D7j2WqmrxSOOXajwOhf4MyPjIdQx2O0kXE6LKiz7FAdsDV+0EezPpSsLqk9kTFM8xo
BHLct4x7zchTMqymyMRmTfe249HIW07n4B6R2SApXNDTDzK8Fio92oCYRjyBuTPNHyXeh5AUvU5p
/D8/xz9Bds4kGVhDroU4pl2kH8ibHl5YHyn4ExGXOTbNmKPfic7vnEmw9gcrSxOwN6tkNn7EOtN3
TdGqYdGYCG8++1PQsqqE+Dm3KfmF8MIdrwBC1Z1reL0PyxjNUBHs/ARBuGRkiZUt/Q+3fIgaUo8P
5Ng5jNIiYd7SB/PAsqfyGI2P7zWIvftCAg3r41cbj1yQustNP1X74kf45lTtRUEVo6tmJ5SQWj+7
yEBH5goPZGa4JdEy3yquPw3MAClf8X/rlxrd3MS1ie8g4p7m/AWMP+97yXwM5vZz9TxBOMe0IJXC
J+UODGHKSL083ZmUJIIQHzyY/WEw9VPT++GdqHeFHCDx/sWzZe5+MYZpo0NAvTU0NnDN0/hTYb93
S8HfX8BLIPGS3ZJepecGLB8WbjcQSmK5ne1MC4ut2NiKYunEvmks0na5syDJ2iAK0wAaNk+Lk5yy
6DxmKk17ECt51qpTtSIchS9CeiaVcRcgJrMSkecoO6MrUyfioCaZKhLlsw5mGJY1dTlnBK0Rpp5K
GrLbfLR2DqJzIH6q7fygf/VYOog92t2r9dnhgHVEGNqdLvAW/SwWJIvUScxWQgfBL1nw9cBQ8un0
dlCVCFTZ4BUjGYS/7+bgbi8JgaKJVZYhAHrYsa9cE9t25PVwpa/qv9L0/S5qMHIz9tjXwsXIpvaf
4nCQB7gexOdJmSn/7J+LltEyI0frnn8PKH5hlbN1m/8srMNZPkQBhUNsDDdN+d1ne9gfy72IjQnt
Sbp1WFIBlAJV+OVXW50k5Tcs+jf7nj5h6RbWTinE9TN6oYzzEU/VZ2O6u98/Cw4ZH8lYp5m3E6qn
Pv9HB+5YT4Y5hMzPqT7gylittvlMC9GMY5JWSDtRLHAJhdraYrDMnVQb9qQ3+uRqLwO3FiBxXC1C
8eckB91mQxpYYRfbjvLaUZV0cYVmAoDANkdMBVrBIBe7RPn1a2pdvSWUceTYuHnuynI+1jUsXDPs
f+Vua73MUbUI1RXAr94WsHN2Gq/hXSlMzctTpysxr86lPpTrhXlFxQxHuZH9tsOyJH1wyy4ESrVR
XULrO0bjdMEy62vmy7a2fbsrzDBzlAOtWWx6A+kuVFWhQKOQfRRO+r3AC6CKbjbW76uwQeNN2Fik
ey0srTiyhk1vn3KvK9457jbyTD0l5DfMwfjfpYOqSWIN4CtC5aj4UQpBS3L2aisleDJeYK29k3oP
JRv/M9jgKHvBqK5qii56DIghMsLiIJXynwyfcFS3tnNYCHE26XMzdqHcrz/7Hi3SL4Cy9rwykjOn
MQQ9EF3ieQtDZPZ7ZnDa2pwSHvY6AUXcSCq4bAlDSTiDAA2X6g4HaNglon8+baI9V0kDNllVHpFK
2FWVScDu1rIsdp1Q11TfawWAD4bLovv+uBlJJ1Bx3+uP5gXdbKxC9rWmtMG517LjAwdaQf+75sXQ
QQansJ+NpW306iPVB62AdUOO7OYX1cF43fn91+dQiXcy40pscawwE1Co8fI86mthS/TmV4I01asd
o0kQa89mfYNKgBgjTHEApf3r9aXNGZRNG9PWkmUBj5JqQhQB7pvJyydcTTknCDhUHGI9iICFOGoY
qJpUvMr2nzPTkb/WTGP3a7keMLmjFlzz/xs0c7lTmzcn3f1XR+VlQdYZR3ZcD4bO/LYfioTgeUE6
LwvCWOLQCT0uY1dFc4cG39qr5GJ6h0SfAev9K5Dc6tjEJXDmxZd3JH8mHtjH66sWOh1XVsFJCF4o
Z7xFawVMkGuZhSIup0PUVxUpKBZGc/c6TgoeeWor+YccYlzrmcUw2AwD6EAbJHvuNrp0xlgcBYWT
qnaaTNdpuJOrkAooLwaHUEZ/DQQ5V54bpWWimgaqH+BpzgbQ6+vItgJJLC4LEiSnWc3tx3YbdngC
1c+eedv6MC/J2fKJ13c5miDCNlicIA0vC1burR8aJruHvL68aLC6dXecr3swfGKAjwBeBhkBlwER
uKmqliYGRHdC3ORA+I4kJT3z7kg6J6/XVvhwOttuY631TfgjiQadf++GA4IRQBpbLYdNjAq5ZivO
wfdCNzt3gAjGGSjFXMwtrHYiOJ/FxO+zfq9FAsupD+l6hGib1hmChNGl96mGQEBhCzfCnx29FTmK
qyLYsKc1sY5YEpKfEK3CaeflwpojNsGo+RtuvUt3GrXSnqPH4WvGiV49BRzUyVyc/J5KEHVc8pgG
OGNlrkwNQ883ojRufOWH1yDr5uOd+A/XZuPYRwA5uksdxi0bnEJrnUMZYlJYxIiy5Dra9C1us6YV
canpquoHXkfmF4OTEgusk1Muz1B6QJNl5C+mUyUu73EOUNF2wjDLVoY1sro2muuqs6jXrRoccjHi
bkgVapAoeiexuXp/F4VLSfZC2cBj/vwNMqQ88Vio9V7zm2SgRfTZjSybuF7JETNS6zS0tHAtPbP7
8NxCNBNr6JsfWkgs1SMJLHD6eagq/AYcRIuU5VWP8ny8o7PwlwaWHm7FmV4uHaqssvtahwRLXC85
u/K37CF+EI2mo+dJkBIVD051bHRLFqfZEEi6Qubi7PniN1oFOqTwijJX8hCvv1HrRbGdQF1yMs/A
ws5hYlu1qzuGDbprvB1u0KNIz95wOEPdYjEvYeLglBol2yr99tLwF0xVY5lcREiDOaU3AxlvZtcY
d6CHXkBhkL6Vmb4W0vMZ9c26bfFlLZYrd3lxr2ZxuWiZdBYVOkAwOWqo1LTzSdu4BkC078pZNZeo
K1LFjnfMpO7gYAPnrbNdzrbYUIgZhnV85cb4LNq+YhJm1VCF1c3/5whjp+Fhbdbqiu8cYbjmw2OE
FcEXWPeiHo1uMlXkISyT0m8VDGtjcfBv+NdUCxj1pAFM5HPS61rCF86nQ62FsEgzCdicEMqqmVQI
aMihwNqvJRE/m7upQtVK/AlY0MwYtos2XXYN6Hz0zLgl4vZyYkXM5Z4XgkV+c+Qi38E56/tC47zF
3CXjsRRIyO+RtIldTY4DQRjXh9buBkOadzgMJQYkevShpN7r/SXz9CWgJVfY+jRRiPshfy4E+aCD
f7aoZuN1poNTr76Z+OB55nuhtEWcPz8BZliMUYVgKjdQuBtRz6DjoeokQC5gMJkSemCt4F0FNuYu
e52aNwGyJihm0OO6LIXq1BauGOjdZ3e+PexghJtFjfPs0w31ownrxuKzxkHuyGwxkwubEmNVw91o
MQ2DoxxabEHk91xctTx7hwvCBku4QIyY4cFfR+oU5NQT31/SiOkg9WQUN+lXlHwFpoEpeNVgQrWq
a6Rdw284WH6IUVReyENIrtWEawxDuF24m1LiIWadiNiB6ww8zQ7z8UidouJwLR/UurcB2GUFYAp3
aTRn6ZlXdrSPj/tlLMrw84tHLBKBvw+g93FPAFs5pRVAlXsjh3Ptswl+34bvkKubc4BYdRTwt+zl
wkChxga1Z+q5mVOkB5NjmgC9o0DPrfnO6MSzmtU2UBExACQpOJ0hJ2Fu2GFuApvYyQwiFnEykbfl
ztbmWa+j+DlcVm0BFlWPPaVobARr+jUobmcXs5w0A/GuvLiZJUtJ9YRgIUS8+Vk2nOmBdNKmDBdd
wBk3rPcm/qvsW9Q1SOO3zOvLYBYmgtKg5uPuIo9a/vmYazVBry/mmkIaE9DO6aA7p14EBPys83Xz
igkPFKO/ftOuSGZhdyuze7xdVqcSkwFa8ftoQruJ0LoQ/R84y6s5uwqHTLRUKNQgMo0RO2WqFs8n
gr4l4qODVLtakjreWRZVgE59emBQm6iPVeacBm2ka1mqGAQupM8ublV0w0ZyG0ZwaETKSpIdVItu
be+6J2fDsGSs8P8FsmJXnpe3tProrrXifWztQNYB3ggaK1rwlyFkJ468GQ516LMnbKtHovQ+y+bg
0NQiUWJ4MUwrq/4+MUoye38CGbflP067upWcPwaDeiOyOlBRW+TnHqJVwuF4FtEE0lRCl6amz1Uz
/+iGQKNgl7nDYRFN7NzpZOIubP8tFBFs1rS6hh9bs7NSUkEA6XBQfGO8iYEhG6t7f1S+w0jG6H1X
IUT2JOTyDRTbRqoEsc41HPbuFsUFEbL0iTJGKZqjIHW5khJCQymQ40YKtMEnwsbSoGeIXI5lMy9/
Ilf5YPAq9Du6ulD8NzcX+GmhAr82AkwQ5m1o2P6lsd74B1o3mMaG8JXtaYpPe4QHUgbSgzjg1Spz
4cPuOzefc36+sKO10pGHum2v6DhpAjWAtMQ+wRasHXjbr3iujLMw7PR5wvJy504cTNHMRl9NQxgy
/sRqU5ut6nLw3YhR8OiEoE5npcXhtkTpIh6n+o9onjHfV1bPCsHKxthZqhDYPUMl5dAezrhJHjdO
L4KRmCyqsmjP1tHTVeuojGdq/mAmBW18gIuXdkyB/vB0ZgVhqJ1163D0n65xlLaXzIZMdFHZduU8
pvHXErhjflxC2WvQil+ocAniQy/GFrae5ekWqzx35ks9auidC5FeZ3w96VbZLjrz/u0DT6JS+1LF
ZhZ9lDhm7BQ0+B+2QEUDRwuWsm1cfJrnZjk0i/1AlxctN901hYZZyvwMN+8+kdniBY3YYJ+vMZbb
lznl0afGYESFGIvZ+oAfQmSAOZPNJrbEkLcJrOfQdAD06M/z2twsZvoTvFlsMIMJrjwDq3FUclVT
RMLcT/73U9sxJ/IdaKAkChhUX3tPehRY+VmarHQEz5o6QRdv/4jrJ1PGHPuJH6hyqQX4wy95zEHG
bGX5RwiX5jqmHP7lpasYr18r6h1wW3abu8XOy2GeFzho07F4qifmR8keaGYZPg1N/ni3k5z0mlFB
k/INsZql6kv4YMZaXQhwEJljVlKIVYjkqPNnO5RCvKX4UlhC7qyVv3LakpYj3ieiQO0dW71QvMO8
0RGsHygTm5b9Ly/7yQAWhjslfNM2hLDwABWpCrXEWE4qovGjfOKU2Xe14I4gmc7HJscfyTAmzmVB
urCn4LdAEmnKwRECa46ddic8nQNqy7j4PvomGeIn1c+szbifOPyHIg5M25yl8uzwtbkEQkPBxC/h
rIvvZ2M8bA9nhHJcVMdD18oio/UXsaXCgt+57zWSGp0TqHzDiR6fXDMqa1vyxufStv+gS6L/HAbn
nedmvXWrEOhTpWqhWQPuW58pKwOe70GysDcNBv6tDLGar23l+rc0GCUJYHvtolwb4dFVIVtR+IdK
kM2FevDbDKgt9DXCQxsePybnU+683QBuiIWwsYK/EIebHB8iteCfs5xKrNmRjzxRPSv7HT1xfDp1
gdFA0O8npt4W60Es/+GPhzEARcsFYKqkcAzQQ8LNnK/6ePaQcMnbaJ5h+uKg3qLITM3dUBuua7rM
jGxbKmA6R0ukIcDiLrrON01MvFq0uaSAFaE24/8idLzOoIHt9CLAF9CEiow0gq+9XYCkjwfZpkYr
+N3KNf5+N96nHW/loPEAKfhwF0/Pzg+nUEtxmddaYhCRTmBZGIMA6c+PiKjHWA0DqRPv+f0BGRAn
U4VgarjixDeB5Z7t4a86hfLHAwDdqzvH8q6l1biV539bWkpikd8MuVrikrbzxo66fd/PzZB0HZan
Jqb9H280JVR2DiqnYNl2QmcZ2QnVgZ3qWjsRG7sON/9PxHLyRFgytgGwZDmcL4RYW/uAZU6ssKrd
oRCixftjQVhznP2H98plKYnDuiWPVkJMkkXsMfOWAu6W5Fm4iMdhewZQ6WujnNEYqrf3wB7HEtcA
zKuKKvjAFT5u8SqD9owskyiOIMw4maaZ4VudDXNdTgT4v1kPVy9qrlGW4PnFIVkzC/2MpvsQS3Ai
eRLihrzXsNWnrbcRsFl9P+ASlHJ2sZcsDL95tmfM81fmnvufPi3XNbDBp+qpVV8npfo/fikRtpGy
o+hiJkgNKrJLcS4XokWCTedI1EjwZEva5LmIDNK1WvpRfjo2tfZ4AZIYmlQrDjjPQGc/XYa0k/pZ
0RCam2VDRSr6p/9Myo3212akKUTTi0p0fSti7LyL7zmcLLBQ7tqdluucUj0IUcRJHi+3B6kP7reW
EDpeht1YqpDCjRSoOGihezfBTCSjHHXRLe6VvRtcGjE4YvOVHvypMZ7ll8caPHraLR8i7MfMXPSh
dSdA4y5+Z0OI8m9TWtYKx245KQ2Ou95TNW+lProPTnGyrBhLr3BpRIcEaR7r6mZHLqW9IfZypMTi
e2HskiH5ORCweHyBu6co54yS2t9iaXVqAMqMP3v8kAWrLB4cozUXGkWuC3OeeUTb/ohXXOBqvRcJ
HUJc4qXkEhWcF3q1MYoJGeThAP2KxKBpYRFcJZpKCJzNhOr9+VrQ+rhtNNL0nkexZdP7m2VxbG2O
VD2UvgcSAOCDKyZwaTFjHyIsN+cP8ZD8mssBB8ZIJsc6D7Rkl31C9KMl2KLQZNB0XW3/AWaLGOJJ
3d5Fb09dmfpj310kal3XzEBBDcqZP3ZOEoDU+sSZXfaxuUwZsDTNThY3KYNtsI16JHpCv/p8UkUh
YYNwlaUlo/qqaDm7QUAfgdp8zr8NFuhMsZ4G5DX/0kqdjbWA4Oc8opcoxu7iZGCNiy4pNvrz7d1Q
D5+Rl1vY/N4U4z7cG4wLmVDpfVZRFB0edt+UBbqRNxdy4ROlgqzo7eIzT0g9Wu3VH6Nom6NVHAee
YTCtQk8zVyL+DsloMCe2gQjGY7TbMr2nF6l8h9O8lNpGlLGsi9EtdYCxwDpIZ2oRPH7R19S4IKW9
nB2GDngdjcx4/dfT6NBXlxRnG3dn1msNAprnCbd/8wbViO79lTwf4E7w9fu2UJtZZrL5ppHNusQY
xLoNxXwfLAGMgcmJ7vUrU/ci401HnV85D5Caw6WogNA0xdxp8IzMwT4oEm6iPTHec7FuLavTBcLe
EEAMiQxnjNPxpd55eazMc9jiylgYylTYBh49PLz+baGyoagYBlOcMp3HNAIwRW48Nexjrfsy2hN4
C3j+XTenJLkpEv/ZKXBLNmCJzf80b3Wzf7Vw1RVozoS4nFzfL58Hu7stmTv3oE4/wZ0ebZaOY+Sv
fElY334H3E8yYVH9ViGzVO7CtjRsTuutUE4xkUCNfC6xD+ZSxDlnDzHYtAP3GPn6clOHiWowRi9E
6JHBBFhkjL1H8TviqOdaUoJ34uWUsYWEcWT4LVhjJWHpTOMxsxNtTughtdetOxFkb/4DX2qDFLQp
yik6ty+rrPqKLbGe3WeUTxYAaBY+uNUP75KbjewY4yj/NHwNTBQ7o7hbSZX8gEajd+GvqDB1BPI5
LkswRb1mpBJ4SxnfBHAok20wRLwrGLQoivzSgnBq3Y2f44mgroZhEBRHp3InznWfiX1TqueYpq5k
MjdRI8t5PTa3moOF34Ru8nkF6zt1CF9RkjvQKuERAT36YCATaC8tI8ptQGlYLAdlx/rpRwUeMq9G
1qRv5ENYR7gPvWXS9Q7uhrLV1ub8y4zUS65JmAObRO5dX4x014i67Ts7+Y+CqdFWAyvuz7Qoan/3
gzSEUcT8RDs3zux/jCAnBfuenqPELNtTEQLnASPVn88xXgBBs0vFCcE/kVHPe3w3n7iYBEZmVvOe
Yb+hCpVU2WPVqpxXDpzFJ1tpILBE24T9sKj2PKUNeGPw+YwauEdN/ghIpfcRKxlz1oeNmBkjxMTe
ZWPIRzR3iMLu1EM4Hd0qfqSBq4lJNDLx6axtu9bqui7+6LXFg1Z9zAJz8d0QPuvMeA8u4vNIOMVp
rrt6Q4xQ+iNJmHpVdBvzrQrWkvyoqcs3VXlnCMYEUJKCm85+ofaGQH9EgO0bjxUhXBtcRsqqoYZr
jy1xWqfsGmHJZE0K2NmrdDEP4/bJD8F9hCBrD1a4TBzPdg98MrAPutf09uzkPLc6uE42AYplLCJl
LeSyq611iTMM6+4PDrZfFxUDyuA08w5C+XLhsfCL9EaseWSPa+A0GusF4KFDzldPGuTIkifvOhoN
L1NOZqnHKdvHHEo9pfd1J+GF5RgKM9IJulxKMKxd/2h+7kbryZjI6cKSwy5z8vBW6rNFC5M/kaO5
RpHmCUICWL1eNAuUln3XcxJ9d0GecXSpU5Lguixzx8ZNEkQr9TI9QPQuB2Ys1f0BgcddU9anKfuW
LBMOKoNXPC9r7D95yFGCLe4YMQQzPEBOZ+H1FPVqXZaYgJudkfp4+NSAgig2icDqC+7TtbY8jD98
Ld3bOvKyDNazb4AQdpP+o+vW0MIWSuu4X+uzWvx7Je76XOcHvslKXoiscbQr7Cr23rXGR12wEmts
DmqQvnaxbFIPEaVAO/YEc02ZnfvRzmpkgGWkl28qpcc35E3j2QAnXaZycHknRMN64pr5MqhBP1vx
dbjfb3jgT4mloAV8lmr3E1vt0a7CTOidLeMhpdKZ7lK9k+fTZCCQlAx45NhLrr/fEtX93F96mp/6
YXPFvh4MOnl04vUQpfMSZ7G1ZjIJ/EL+7hVCEPyFXiwkymH/S9S/oFZuumc3s+1b9N9z6WWTuNA/
Plkb20awEqazSPsKs6jLQDxEkVUn0j76sAqcjpBKbH8GI7gDo+loDf5i+GOR9Li+hE1kvmT8pL2/
4yCNanfmORFtyxV5rPVJuxvyTKG7zMg4o+gi6X8X44Vo+ZaPXkdDPkPPrgXEJNxmvj5jaLuZ+hkA
xClF9kWcy/0Oua4Opmhm8Bhe/nJSvb0XFSjJGE59fE8QTiYKJW5mOVSyQlZ/zkXojhwdL/6bAvVN
W30zlTlDPPCu38Vlntg2zhCLoepu5uYEsgHJoUJiWRG78qpmyxmjs9jWT6AfnG3PkKN7KOMvnpA5
j/c5V9btYTYNTJ7vt/tH72cuQVqmDuAPM56ScOdkRTcCtsTtMbPZSNLmBp8n+ZdXWVC7Hu1INf+Z
1YcebW/vPWvckuEH9Op9wxnV57sKDHfiTDv5d3NH0CJ/mY+G36hU2/mqlunqj0zeA5BkeyEKbBj2
zS1klHPmnfFhu9KVTN+7yAA9HQfU2xORlFtSEoMaQdvJ7+rN1W8pPW9SHG/UDw9mDkY7kLL+jPQf
6o/tfTNAoiO3j/ZdrGzhvwSJPjygkljkHwQeCOQc7BZg30o0WIqOOWpvqlFmeap+7xxGuA/TfNur
+d2CiSMwBy5CiaTj5CdXHzL3rJc3ZnJ51Ej71oqInRzMvGCmM6FG04qes8jZnZyZYT18Hy+Uy3Og
9ZX5uLn6FyXXMJSsCP9kY+p4ntHhD6ThaBPxfYfoMjnZbAttVwWM4DeezYhE9H+/egbm7GuAMb4m
QyVwyN6xpExyHR4w4cmqfEcTGxBYQygNZhqKquCIfCRXRWbW1VC8fvdq114TIRU8RUE4JHuKHi7b
N8+1ohx/XHOsRQigM2Fi9ZB1Usa1qjO0Bgunrxc/VjzLEVNkTEdDboXLMKeq+neMmnIb2MAVKG+7
wB2xp6jqEBrhrqptdiPwA4SEec7/2TdNPDqbWohGvucjGKfG1t3XaWE+mFiVRia1P/te6cSKi4Zg
w58BbIphPe7oyH3gqp5pZ21JH0nSZ14c8EXsXoUuN4XSlSTW4fjn3BvnVJL5OR22f5ATleCIWXvT
dyOf7gQG3SNzzx4szkVFGZsPa9+puodAbCmgBzpRyardw93AYHvZGQCwaa2wHw+wdaXFkUBEWIdH
AAzbNHlKOnqfIhAeCLMmjhfWp2DsdzRPbXM6sn3rRdSHpMAqqDVMa2G9DP4oFdXG5xBhg2EE0OWn
T137SMK5cne3FzOVxVDTN95z9/R15x6eDNFWAglmvf9hnxNIsPf89A48IYzra1zINBCYERrKAZ9R
sr5dp7BXEx0SoCFqf0b15g64C9habGZIPMVNKWcqrzjn98Ocri3+OSB2Fbt9plE6a5Yo2cv6nqSy
BGPxYwO3kYLLXqbV0C3wUQlk13wvvepiOnK/o4YOo2hxErqeVPjSBgJMkc+X1Gg/5Tl+vMiV3Ssm
Ldttdjo70l4ew91sLUW4aUf/bJVf4V7K7fFx0cLsfwHGu7a/r5kOFnvpCAgm9n2PdeDjndxoqaK5
ObWNsiHsOzD7ULWfc0gVBjTPyRFzG8H4boYlO9b3Y4L4ASoMu3y0B5X37bcIVxXcArOJI7fL5poN
GBrIc74FyXW4Tg7BWQp+EU+TIxMA1SbZJcxVRtKCA5+SPSf38Dh9T5OPJDQqF9lzDGCK0b4YAFsX
aQD0jyt0tYKJqjqkzvqyo96RsSlQZ/RMN+ilezXsH9fba+0Z7XHx44r4SxrGneFuaXHvlWuoIvsT
lqnWP1X27ZSE4QGOf3KWRHXAvM926+yKLNBfQHY9V4ab/1auRdkgQds2WQJVeLWWCJvsH10/ty9r
xXDO1IW6SGUWGmU+bYg4oFCFED5m4HhClAa93eIlNnITWHNunhnXufATST0rFoBqpxN2e4PjoBJf
cSqp/lHXwI/NNxQ+2kKeusZ5t9Hg0t+jymtlZwBsKKa63H+fGr1O7hHtXFzgdRdazUag8R+JB1C6
U16I9KkmW3YBqC0bGGhycmOkYdPLUL0TRmScsrKuSAA8edMKSbHaqA0Oj+NgJR4zKdLhtGrHkxWI
KiTRB1GzJoR7WuaVt1g1o3kv666B61oXblPJetfUNYVQJeHqV8cJUBUPOxd7JBlmewN4dVxqCCkz
LoxmzaN55QLaOSfa6AVpor7Xtj1IQzV2N5zruy9lT8zE8paERi4rk+Zy/FigY7aAAPRcCklZmr0j
EXoQ/nzo9HFANLSDcnhpYRUcUvCwShzdP4b2pKtbkDLXll0gV1hGFqShbcvtkI26B9bOQuJwXAi1
W5M6rhCtDdrkMfzSW1YGRlcFjCuv6OlIgP1l++0K2I2lnUhfyLy+EhpOrkqbUzwaSt2I+RcuLk36
zVYxInJwjnN0D2SLphb2XbBYQfztko++sTAxVJKqA5uPBjVvBl8AEdgydVRPNeXrKrJFY9MW5e2o
mVGoSBYzrNtjyRVX8K5oWTCcPhZ5WtnyYbkBbopuJrQxDQzLHXqyk4l7fMFAiibchcvhFvgc+AcG
hNxHay7J0ylKKENWXlZQOmZkFJWGzWaDugzqZ0mx4fq1iQIenPxAqCVp3RXKqAwraxGcKrql1REd
l6p85rUfshPPLb+JoItNjQ8woutE9kuu+UgDQVo/f/NrY2yQP8vKlpTHnghYrEhfs8mTxZ6WQgIN
rl2uqazkA+ApmXu4KUpM880AwaagFunDABXXhgKenFKdIJi+oINVX2tUZpO2qfiiAVzwcrL5Bom+
3MGEQjrdZ8s7wP5+ZuifnD3FGXLeSoeRLLbeSKXFXgm0BRctRZpvXrP5I9brM9yyqawcc/RwZMrU
82teCcpQRkkw80Pl26DVcA+jcmUmZRRTqWdpRT3/EWR/x+OTFJsGoXS2MMLuRlAYOKIam1s6CpoU
FFicBZRByM10O7hPrqvs/hWcfljkmJuOIKSGVAsLkgJfTGUGZibhPr+IHJHdO1C+VRTWDLCKN6H7
IoHjJ2Q4oc1i1fPkXZtSYZ4rmjEXDt6PeohGcQ8oUlfU9VgfKRgxODlME+u7UqaymvHoYPwno6vf
ICKfsw0dJ2AbFgcsxeUiD6QyqYf+Lv+y0NUl3jjee/Op62/fHecMvUySNo2IKXws3RWmpFlulKuM
dH3pkR1BxX7paZSgI3Exb7ayd+s+viySM2mZ2F7aqeQo62RRBre4gaqS3c3sypy3af6pTRTHhm0a
mcVbw9fNjkMrxIMMHJLJvIQELcV+E/XG2b1UFqWZsg1Uesx9eHnEPu5acLjHoRbPnS1IzB6DwiAs
eG/e5oMeDoLCcQKJ9FLO1rzolxKWC4A0jzk8q2n4cCUDUgroOXI4pSsjBigE5ydJn3KIaB08Zeau
w3fTZqIiYNzldhWN00fn+TppWowe5mzpwX5mPv7R4qMlPR9rEyBXZEocZNYcpxQ/X26vdJGyKqIB
aYjnOz/diFgG4LTZSdkxNIUX7srEgLsQaXFD4AOcqeW6hbDQUnU/RnGVmP4TEp00H1EcuZVg2z/Y
kzB3xoBFyPFt7mAvb14I0hrZEhiiqUjOB51pAxI+SFI7jzMm2IwTdxMM5RUzyANuzTgaGKX6cIq1
bd4Hlz0SoR+9qzLOBpDLmns1AQeuYlbXfhxy1FgO0m9RF9N+KR+tGnQ92UfPpMfx9aZ9F0F6+0bp
FZQtlYXaLEE4tmT0kzF9xcHvI7esatDi9GgxOuuYkgmQGema+vP+0TQ3VtQiJ/vAHdK8+21CCM4j
nfmqIg3nV4gAzDVv5ORm5WCkpazIOkD45n6HxjIHeDA4rRufqWQpMDJHLSF3c8SgrfA5pA02vaZz
Di4ETYTDdfuMeVFy60jutYHLJP+24dqALqmcCQBiyLcac9sqAfM5ESenRHtrlBVp11AB2DPP8Skv
o306GIiUKKqlYO8BhvNSlWMG5bvvCva4NQj5MgsgZNHBR//w3m/3tgnzYdf8eMiOu/KpU6J8dILM
FttJFffB+sY/XqXh/Ktim6ki8ankLaKRf4bucKSvAhRnX5AW/esb5owHd05EIVdUt+z5tsAj44Ea
gOWz1ndS21balNvDOkCpXbcYfTTg7SRxQDi7HUs0RK2wChMyVpQHfDdmcO47ebdAxcXUaWKzUPV7
BQrNK9DILgJxXI0TjRU9CbTX8w1l7ZKYJ1VCuQUE5VZJCgGuFTzd9oHlThDXNf/AuL5V3k0aegqo
AeRLLCCxTpH93e6jgi9jQHeI95zRppzon+cEn7zyNGsFc2i1vglCpNWhT2iJa0Ex1KVZ5dR0B7U8
U6yblUI+gIlhHRXeZ8QkEimiuWkFKMOZs+xu96bej+gCGOzGxYytXE2wRxqgbSI0mKY9yHdkjq5S
MO4oI2rRyRzkEKGztlN7ol7Czyw17Ak7rHJ65ULf6A0WtSSk3MTB+PLvFTR37UloaLatddjinueM
nuuggMNMgL0tc/60xhJeg0c0708vfDyCER9M+blPuQPx/c/GxATGqePj+HjtWRp5JXvc2A0v34YN
dIuxGa7AxAaD1i2OYEB84NXrSLoCjsVi+K8Wkjnpr8rRwalXs6zOdi/DZ0XPKZ/XfecjQZWYAT2Q
/vSO28jZHdkBRfGQlgAbxfBdINUAlCVZD966z6HxZeO9jHtRT2zMBkSouyOU2zfHxv8kCHHEzk/8
9vo25846Zgrl3XJdybVyGhHy+NTozjDF0hKoQw3U0yvD4akMA7ssD/KcRSDFnUjfRBku3lAlpJyF
NLtY44fBbokjoxLUDi/HZT2Um3WqtvvxZh0frLKGqyiUWogeyswC7PbaRBgiD3B501YQAl87WWbm
gewz4VS+W8nTMrELasIRCVBuFdUZug8Nwt+18a4n92ta+Tes3DKEdfwjWFq1taueksC7WgykZHag
iTnXikViNaHgB/HXJ/dXhYUxA4KcY2iXulZ7qd6xQh/AQEOSm26/8sELUY0PwtvOXQfFjXggr9s/
Onehq+tqP11Xe/zky3N54ki22K0WVcW/12L2lyhcRr48gpFQK6WmWbHLkHjgHsRCii6uFs9kFMob
hqc5Wm/+IuRC9dxZd9Jof55Puj5Ip/R/tK2SuihGH0nd+WzSz6icLV9kqjcbDLNz8EKKxinYP+A6
zULOFvZvHqHoS8an4OKPL5eOAD4t7cw9m57SPp4+6Emvq1ZVxIjdnWLrh44tHaCeQ06wf5Taenbx
wzyGUkrAWhxIYD8e/YuhkLgS7lKcjriJJn6bBULc3CHeLFgWlQ5ygUp/GV+Nydzf1Aq4Tb3Zsk9L
tNay4cIlgXv9iOcGU+5gcIYrEdbKs6hfUpZZQBbA16rJdDg47Fs4PNWrlC2JuLGUn33a0irHS9Wc
C0JGdUSwSqPuIqz4T18QJBmBiDgDQ9Nzv/YUKbqm1CJUsqcmWAn4zHSQHYvkHUJXQys/dM9Q5/2Y
YrcInf7TKY1mJ7nNytKyAjEkiHiRN6I+OdyWuNS8+lypTmdnqMU8t9cM1/fmgErXvGWAHORhygZD
YK4GiuKPaeNm3vW9rT5MEUSwhYhyAizuhsmICMYmGGbnJtRFNY0ZmMFDophjehZmUJxJJ2ZCVx4R
0hLo5RrHqj2aRRtaZfpbk16SlS2q1b0e5tbkgQ6S3mXWS8oYq4enHbWgIAXVcdxiWCA9DRRUTlvC
VS1aLrznqTT6Qfsg4JbCEfkYERBnnDByE7UXx0p+2lnr/jdqAobhyNVhq9F2eQi6LdzPc/VQkuZU
2zSQpg1++31MxCeHNnQypiPDOnF8iSfPB5QNxVrrdf49VVRN6HNCCfWpciwxCPhnuipj5xjvNl9/
UEAmusqu6JqucdGBs9D5/dQETGbl5YQ+maF6dvrTlQVt2PO7yiQgsOrIT31MWDpZU9ypklELiZ0i
NM4bmWpsk0wiYzmuunTFYQkknwtBbW9tqQXCMKx2cQ6VjfQ7QLuSIZtfeOP+QRXhsqycn8IZn6Ap
I2NRoCnhlIzL8NRN4X5VsIhz3j3FL9KZEn2/CsMAluWnLtsnfCr/dg0aRc28wsbJCfSffIPbp6hB
LTCwSPfdykXZ/k2gcCEet8R+HJp/Fej2a4BLkjp8iMqAh1NshkP0UGIOIMk4QPw/iXo1AArvSBIc
Enfvi1iytQ7tX33s6gZNUnVEpqaoNs08qiEODBxOe2S/IAD7GR8geUbL666BAFOIsZQaBlIxSDSJ
IIHUZqoVl2auEpxsk6CSE7v/s9EZ+UHUNlJjczssEIAN7ekBBpqN2nsCfO8A/oqL5/BX7P/1wZnS
vLwogXAPNa4CBQMUPl5PnItRfQDxhr9Kr9u116L49a/OtehNraga6Ouct2a1b56I67o66B12rTLP
FNrSuH5f2vCbfCkOdH+8aNuo8nyxX0gbXzqpyy38Ma9PXEi93z0NKJK+qEOftIzrHv/wIvDrMczY
Ra6J3hr+urEDzcHtHwW1RUii52rWwli14KreL6I2oFkQkcyKpoH+loHBggDd3V7B7MgFR8LhkvUs
0SUSHWRQF52bbzbCl10e/wTpvBhDFvzS+OUDB4PUKgJBOBVbk6AoRse+ijdjkN9ctIttM85muPN6
vdWW3ldfqaN/t062fM/Qd5QyiG/qsFX0oxwE+n5CUFehgsds/wgfgb2zlubJgr5P0rdxDQUDfqqL
+S6gDJ8GcEdlv5UcpWAB9mPXzMdLk0LGQGnBYN8rrgvLiSh0MHX92v7qZy+uyeZo+PRsC2ZZI4fh
3JuUIE5CEZ3B8XZCWAOi8wVEB4HUc5wO7s4H5P2jlwS8qno+IVJYgtG+ddtKCIJsXEDRVik8FdUP
M/K4gljbePWrltCiMcgi0iv0yfynJZ4BE9immR87l8yospsCsnRCm2/aslSDIujblAbTB++o1lCy
T9mGjlO8p2y3jj0qCADdxvdNjOfn3TKqSAM/8Oqomfwshp+GaANMAJjXtgoD5GFUSqVYbfOLtStZ
0cnrXrzyxaRoPF0H5JqRGxIJRQbdzMZt/25fjc5kB/KZqtZtnTX1Tpe2kRUdn579P1cpofkaj58Y
/IsEZOUSH5x7wXJzAGdXio9YYXbNCHZn7ZQFaenZFhh2xKVLWuG1qoCCYzYqb1dS5DhlGqJGhkjn
3FeGyZPjxDiXUJ3ry/acPVIjE+c2heUWbpA0T4zj2TPKahEV2KpZfzz3usax8IfSURL2con9FJAy
UX7eHtu2+4dJwzjCCe//5bSBt6iGKjPaFbb6daUjTfnt3i0utyC+3LxW6T00lhxQTFiVn3q2hdV9
KQ3ifjcBzeiu5tXuv5cm9MVZroHiX+fSLo20+78kLp0LM3YRK/PTZaxUEImFvlNb95XmuiAJpzXG
FQ0PMRa43aYe3xdhymGhzE07bUWSDyk5kyCZJ312prs6GBOfZMfM5PR2VDLNi+Tv0xArX1P4RZVP
WLb0KnwZyknzXH9i2xs7s/3tLtv24Y1n+0XJtw2PUliWDmFudObB/WTMuig75daKy48ZvmK3XZqU
lCtcazuuDsckUUF3c9EUfSM1vYGTqvuCrJAuJwct+5kx8FyYLIRC/TTWlBUv79IUqnvzwhHhLCTf
6mOUyWZtU4A4cIbDR+TW6D8YWM+Tz2YVPebbCPYcuFi8dehQ2nNWh4Hp68gSr8qY0Vl3xKWgMEvD
xBSy+apR1tB1bSlBGYne7uHHcH16TOILotKN2LfDQ5bFwCKR8h8lr8twMs9SYAkDjwY37+4ml4mw
vVhzSi9LqCVg62PUe7yZVbioRv8S2P4QcM6JcJ15DcREtJxs9y6jJOPcVxFqbODBU0eaPBCBHywg
Aa+2t1l9M8rpJNQ8YxqijHJSGHPSiTsjP8mKE7KtI+jF3hb7FpX7pGG+EhhhFfBRULKPcElFmrjT
FJfOP7E9d1WebuGz/IJGV6n9gk7yoS6ufg0Rt7DMeskGbxoB1P92etvhNGIRSNifWEcOwb5jML0O
N7vBXx7pl48voMCHdP5CUcAQeKSDXSjoa0jHLWQtaBM1sAOSoZ/+3PFSHQT5NEszJl1InYxOyAzF
ljMrxTooxaUaMIipeiodeKXqVsPYkEBdepvryongKFl4aefaDRTFTkqoxJr68gPHPPkQHD0WZt/Q
8OrPz+dI5iYpXyUb/UoQX18p1VfLHOtfo5rc/RXtf7tT6WVfTeFRf/bFDO3QvI9X3363OEMULES3
lJq/iqOwKyJcPDlYgXXVJf/HFQ8J7+illDcr0VHFtTBg8EGcCfXArqYenxLbEfTL7Rk2N+YG4LZr
vggTXA1+Y82RfCbFvn0wHis2neMKGAZOfp5gJPnKEVM01+vZjVHw6UcNJebG6LzFdEaCReoJ5fC0
IOHRxtXV4OGOmc/keOcEKfexVQifb3Io1lQLFa4+erE2VYpWhsJV58jj6spTqlJYvBttBtYv3mfh
b0axj6Oh7mfN5PGIWQxrip5XHUczgQ0PEtPxbwBHcsxfhu6up3KLLSF/CCuH4GPrWhBz+3z/tsrh
JZRmZxW5uJ1N/pLzpioN3TR4i8PhmmmGZuPXl0kh5WUuGZMi8mSL+mS86JqbZ+dd0xn774WSJeB2
3h68fvTZiNhXrXov0eAZJVMUNiIb2UtY0D1HxpDNLzPSgIGxYDwdDkjny82AqJl7sVgwRS3hozkw
RUJAUpUOGAcDP1+t4R6m6MrhxJjU6Bdg1xM382FV2yOHftukRLeMyOyRTdmbzLcDUm9uUzAOcksn
z+vEbjU31ms/EuJDY9G2jhzWAxqASxIuIqZmCSfe6IZ4sGeMpp+zByOt38hNW5YpI3dWw6gTXE5V
/j9r0/HFk4Jbr+SBxBRAD/7jJn7bH894LU0/498b18vwAcnCWarPYoEK796i05Ha1bXksK7NYK1D
WNesqMYjmx42O3Ka/xnTAHoBKOngFKvqiJHhYBzkJHqKHeoD9cEa8EvYCZn9WCuTf/bTuClm53jh
M4SkFoas/eAriur7qvc++Tsm2am4FY4EySwi4xmmuFIFCoXYVM/+FphRAjY7zrMLYy1Zjb2MkU+R
SrsPdFJ9h93tahCKv2rCecSdYqyDN5G2dWbpWo8caLa5fMPoXHyMWpIVA+pwaiF8WgZG1JCtUdB9
hr7+DdkDTPXqaDmkS6CehBMjznrpHmD2+HClqtLr9TM6EV7rbbp2LpQ+odjhO/yyr9Oq4f+RIc+p
s9nLQ5Hxi/o+VE6xl+yL7K7k9KtIlHB+vZS3Cn965G65HdTPTkb99HVzjcYJpf1QpLkRjabqs3YI
V7BZYymwkI4g8o8PFxk5SRew3vZ5Vj+1CgRKqjexFLxrqE0B7jgdzqYXtRl3gIS/9oUzoyIvL2LV
QLxaXHqJRVqqA7PMfk+itc3jomoigD281sYKZYFkOxoMlUFSLWlWZI/uAenO+OFRqw++J6IFes7A
D/Ut1XpB1Y2MzFFTwC2oRGdfuiwJ2TX57IYNiS71kKXlJ1n3P5dODsHTD2zkAdZBwbK4imyNjOfm
Sn4PQWFbcA5EsU5Bdwy8yspuI6tvtKJqPCgVsPrihRb8Vt0EFPtmQnPfN/D5KQBR0ihGpBf6iRSP
Y5oTGuJEeTlfZ4Nq8z5ae89BxwsYeZjZG9j4zPVCgaIkXcIC2gmuatbxQG0eNMaC+0whNNC3P633
W82WTG1r3eqnXJXe3CXa6copr27GrJBS9YvoLPwzNElSMevafrpgmAAkVwEJzd3VnBk73CZ1WbRv
vxsrxoYKUrSK4ajsJOjB/DQ6HVI8nCGc2rizrnfBDXLc5EX+4b/w5ozH2QTxXAmjDMGq0Fo7CXd1
zJSG/oQbTI5YUii7sgNOQk+5s2pLltxhzQwTdPbZ8xKwoPjn0qqFkirYYztgaS4RMdk+4eRDTn6p
vl+lWiv8hsiAPGc4LyNuJoS5DZ3AXO2WwRJ8ougS014H8J/oSDlSazt8FQlUiH4PArEqQOXdbQMu
TwX0r5u6m3EW84xyDbKbd0L7eT+pqGxmhQGI7EFAhQeov9FEEZtj0V7eIXguk1E4onqk0h+kZkwH
1I+Wl1dEJx+WTMjyAz0hLyAhB9RF1s0FTB75Y/5s5QCGIiHg4uJ4mFTCC9y+6qDWVc8gPy7OvGDj
81nzSVO+BUVsa/aCHT+ou1gQsjFoZRIaYksc+44mvA2hRCmTCJPtCCZ/5SnFjiiIkeXJsywV2k/6
MlKjIxELdlny8ap2yBxo50Cy8ruaKyWIP0Q0lDqDXHxtbnfBk4JPUbxIEvCWGy9ZnhAOI9nmJHu7
2KSBYPMlcsb9O8pypbXvYSBK429RfFgMqaVmtSIl4uzdzPBBMtX8sc5CE6+Yky/TrzNA7wCOQRwj
wPRspFApFO8iSsr/HESPkvAw7n333VVQvP0s/szTmtk5eYDW0329ze8aTD47dAOZtBMbA5xrhDf+
7+kaK70RspGP3IS3SIqoWwQw4k2VvMbAhCdIf5TVSWGDI7dXHJ71L9JEm/HfRiXZ65uKbCFoi7e3
1phhV9XkHizFy39f55flFGPBz3NQ4K1EmIuA5q8COsKmSXClgqPNBhRsEpqLYEeIhQuNTfqAFX2S
zJBfQoNPa2w/z9MehiJE3sF2Myh+zPVDKl0Bv4fvKKrzDA4k642CNSn0t5d5wE1GLE5vW+lH+Vks
S2M3fqBeWkBOWt0cDeLaZN5NKmwll1ncfFH+jj4dXLaFiH6yn0Sk9aju4EzpoMHvhNOgt2CbHy8z
p2U3WMdPWMYx2TcplqgjldPOdPfdbtGtRQyt890MJDHt4hT/es5FM8VZs8HcSyske+Tp69ahhoIg
j/B8fVtrQuV3yiJG5yZQWdEKqtqnMf0yRE0gPwYepeRNPkQHMBlBfe4ZfLrlHpA+C+oxM3H+J7m8
O/wMvvcRYpOYaQQ8idqFu5hxDa/Xa7fdAxu9sFVH2ID0Q3C0RlW14g+bu+Pkp9t7Uiej4sRqGijT
rDMbqYDfcQBbb9zI6A32kt+XKFkHu9XvbeXNbWl9OtKl30M31yzl5iJZSFyzxICVe3DYn1cSsu70
wwpvTr+tC9jbgSzVzlBLQyq8ABsWZNXLHzzXQIprjO9NtB7FoR1kenvIM46dQrPeHdLo/BFBXEPw
MSl5/xUkqnBXmc90vRGd2cub+I1+/MsWoptEn0dxj6OGqmu9F/GIJFDfpY1Cq8pV3rcdnlunnw7o
flJ9T2cEf2dybIM7w/IRsiuzwQUfObCaDqF+UQzBnWrFPfMEQjAT8vRRglzFp90kOJUJBhHkWiLX
56CYEhNSnEbg+AbTE7oqz6AHJtvIvjPAYAei0KGkBfCS0CUCwxphcB/yy1+80IXa1HYRh/jsQXjL
399+rNGw4HLWh2a0Ih8uWef3aIgXEmsmsA5f5aKMbC09765Ezp3nIi0aWWejrsezvW765sp7aJLv
kmoGT5v6PxnugkwKRACSingIErmpaRudhMxfNYijPPq440Kn21zIj8kCBSWF13dq7Me8DEBR/hlK
1lY5gxlTHWUAMXrAfBt8MNQ35ebxSPswqak3U1Gd0hNSHtssqh1F1lJNBfvY8+ZdOuiw6FyI6hKO
fvJQI10lAJ4i/HNgFAhKpAUOos+Y7gFshAnilbnDUqAfOBFVeZAsl0m8XfJOv/gNyqLFVQ/wqVh9
Iz8r3dRr8NtxGwNO7ddxu84EUWhP7MwzKiwaFibArRvoIo5I5pGvMkHX29ZI0I8Vx9VsfHcGKRxu
GI7A873EN2KFa4SKWxDxBNp4lo7X/zoyzNaLRrcGmjROmRcVfilH1+LS7or9iR7girS4Na2YpkOw
9KxK/lnXHIBnalKUdi0KSP8sCUzO8REVSUOKnwjX1geKcX0a9bz7CsNH1W9BpX+IfCIF4VwrzC3V
lwTLnavBt5kRbrE8VpsrD2jp3VOFcDSV72RV5AL7ZXm/YuZz1LFFGiOCat/QqUFZs/uBH6SO+mYE
Vwikivbj769g9FjOW0O62H0ejdxGkAXvyz5vPew72EPs35CTBRGRsNTA+ZI5ViHCbCpukskZNdNL
znfOnuG3EbN6P1j9qOYdCrfOgstmRuVmcgmFdFlatLBKohUY07+N90WFDKULnfkdTCEp8FZKYgoE
/qDK1fg+t061z57ilNjxlLZMqEJHhUwB1MeOqn81pRAgx6Wh8P49bsYt79VnMUagT3i5DU3fq2N/
p0z6Paal4rWtLHokKzMq5PtYUVOQRsgyJD9sPEdErQSFBs+AXUtNGZduHLrJytbMpyhF2IY4/EXl
kh2InDcdfMxDz2iVUMlEim8j9N+bHQMbBWSWVSGVVbX1KrMwgc4idf04hO7+NY02nx3pff5Rks3u
8ruQwTjq64J6VuMJKaJHjh6iO4s1KVp5Xy0GVbJp7PY94PdLFSQsvHqdZ9R86TVMSlgaXn4d1TUd
1zVDLpyLRyC6R1RL0C93d6Xaj9lPFtC3aURVbce/+4HcOLwqtjB3ZrHMzDRi1aWoraYGfRUJeGoZ
IUCO0FBrjhOGFDKXc5MDCFnSMQfRffQK5vSIZTgG06lqYJvJWJOFQV5dDZXvwcxhni2iMLmZmZcR
CqHeU/U2+f6+QL5A9Ik3LNJw4F7naGByBj3wQ8KFGmFMbWFetl3H82Zz2Z5Ybt7bUKv9CNN3h4Ic
RH+Ju3g8wKhP79Y8/XSkjUXyYpr1Iv/26cLDW+hTLJkSjWRpurnUTgwnuzQTmIN8QAMiHVWwLVJb
8JsN0yoqYQzZqlZTaqIu8Y9CT/6JkVRwtIDXkB/d7rQqSdgP6/X2bHB7aHvMnWLL+5JX142U1PGM
cL0qwRdUilT/aDG+Uza/VdrvN/sz5mI/8Di5UFodZHVP5w8VnrC8DbIyVyzbDoRwQfqDMAMbjufE
+V+IuR+wnKiW7rCqWTFaF5+Ld3+TZn38uZFQjhYT1KYy8PxLxTOVTXPoSQmCOBug3PsOpFShx39h
Y3p2zdRGRiZ6KQBhM7G0XDDq6S1zewO1xeZ8/pDFVnsUkCrinzpSInkeNA1Vvs7AFmTY+Zfv6Bzp
a2lQFZPv0Zgzqu3RKIH81iDg98tk0HB8vuM0EcqGiZzB5ozV+K7UWP0ZIvUJmco3k71OTszxqYcn
64z1hZESVMeLl/CqxO9qgA77JD3ddTfhfd1tL5hrtvdMDHmHhPU03cFdc9XHvZeTN30GPaXR3vqD
v62b+wjQtZgYMbfbUk/3wZTFlv/UqVaCWTZB85m+B/TWCsH/ImgyXq2jeYOVQUzRbH2tZIETt+Rw
//WE8KnJ+KzaQx6CvGY5NP2fzddK4+ABWllkbAE8bZFcrWKgn8pigy6OkDxX+9LBHJevtLH8RM1b
Y8FwNUFBClHkSJkWac5SCv2DddYOfzdTMyVDfO9YRsI2INSTgT3xnmcPZYaZRyS7vaAzk+7zev2y
+H3RNFpYEe0XjfSgORdd2z7px+cC+lPpg+erQHs9cadlbbK8KrbGtrkv8BU9ITfTXfXWR+L2CjPn
1UuQ79QUYdkXYr+sJjtD7WdjoEZX0pqmvnvCGaBYBOMB4VmB54u0j5AHdpb5QABEvf7K5e9xSyH8
yLOJoFruAJ3gbkmzMX0AbiWI3+IoWOjTAB0dX/tl792j5bqlbIQ1NMtIZs/PsiO2ihj1mgh1VYkE
D62JJxSXFGULpqf4s+QqKzAlkV8dHqpZ0mbDST/WCsBCuRIBUWTRDD/dDM7Sz9eu3l2R+g4Im2aq
Ib/KYMzKgQxWS3LoXoXp4ziROEwijxvGy++715R8Fc7c6OkGaIekQ8W+5YJIvXCkPLR3AKMajZ8g
yK+XanuXEf2l2WjcVfbI4wH86Q7hsWUoo6QocNEZIFhIN0jPT4NDic3YNBRWA8IPcymH9oMa5ZrV
7AmNy816eXSaqekJZ8thV93qe+I5CE0blQxgKbzARtnrJcGeha7Lkup6HyvSMAZ9qWeJNmrJ+qYz
HYMlgcHDvCzPYwRh1yAyXjX18APGfCw3NSEhhQY87ODAu5IxwONpjtvdl9I958fU2fA851MZMB24
ejNCIBEuV/0iyT1yv08BgVZ/3zp+s3KMfVu/snWRv8kh7ytbBu/8K0eFSpefpeU8VvIGE2TWxGYP
eVcp2ptwplh0LR7/1PZ5l6HxT3kfBCknQv+4807DTMWmLQbdC3rCF8d1BHhPgv++1Ce+q9hs81Pr
TIcGObAZiRR7clXMCApSSplV/qIp9gsHT/uxiAiBg06fazq5Fv3SjKIKnDQf6c8xj2NxNddqq0m9
JrMpdzWWqTFXatITE9OZBBRnOr3xtoDcCG8ljNLFRGMqxzv3ePQqUmvjK0uxIvpfF7n9bv2oq8Vr
Mr5fIKhQxlEfSUY3Z6ydz3xQVXZiDkHS2qnO9c7XCG0hkYnkOr1Ykm4IFeqWUh3UPgF+e2OPZAMM
4dmotmD5yN/7qBGDObeT7BrNnEHX4rdhf/tkdxpg+3bC9T2SJWxFr+pcO496okci+ctXkQq0pFRr
3lij6AkwHB8VkpKmO7FJr/Ng7wPYSESTdwX09sfV59VkB/4BC6ARhXk/iSpUVAF3xZcQoOA8zMHH
DKtykIKW0XbUuNJq95SuwqdaYl+03dImV7LcAPZpMeGTduxELtSBGoxiX/5g2BL7egklMYFTe0aq
dbcd0WkxNPtWmRJ9Qioabs1RnBcUKqk5Ob59NUzCQgwsTKtYvHqgKYzlSQ4l1lwvC7Yi74gvygCT
y64adm7GM1n81Ujcsz8+gUECK+ZzurK12tIBC+06o/q0F1xrNXqu6FlRYJeEDBjHtIq4K8X7xG0B
H4z5HPWyvhSiegTB2crFESujrfwN7PPXv2piG63i5Qq6G86M490Bj9kSbUDB7ebdeUxT/bgYSpYI
7YDQ36DWvu+rBwZ0SHXLNdLhGyVfQyPxFC8gvDOS1gEnQ0cdsawcs0TE4/bhzMPDRmm4aY4MWPFm
QR+YJjH1e6hecM47gpJDRkbdTmvqWVgc2/IKvvnT0QTwIb+a9zIIr9i8t3nTOgGWEL2b2St2o7Rn
LgzlOCFAnDUisoqNiqGBdVeEWI+4dzgIHvAWPq+5n8B4sYkxJE8rkxou7HR1+K+lyO5eWyR9II+G
MBMpDk45rE0wXTitYBUMN+n/AEA8vJsOirKxLLe99z1j6OtYi4Y2+dWPByEcLWMbnoou/iXTarnE
pM9BoboRcHg+V+oSlSXOFPZUvXxt4BLmjgEFEMw6ljfLAuswFhLEMpko6GqT/CsyP3bje67RMfOw
XOOhJqnPC0/S5ObalJL6KvGlJflPPZvyoiCLcPv2UFtYyLcd+F+PP5O6tdv73iDeblY4lEWh39AL
DNxXNED3tDAvowLAdn2YuHADqYSoRg404AWS1mv2xvAzsJywGS8k2slXSiTxxWdgPT+IuzyTBpl0
BdYbH3CWEAr2LcDEAW+1KOq/nDiDZMC3uFNRmlHmu8ay5nlZeyrIwPzHgjMRQzLwsK/uJlstksbO
sos2ckGdr3b2Ih64M251eZMv4AUKSUgn1h1w8ZtkBA9lkDkul/kYFAqwYAeZor9cw9ITX3JUNeMJ
M/iTR8hFkbczvytGHGiKe3CJib+bPhONxne4XXgvwYeQl+6oQDGsc80AH0d85flKYH5iGo7FTXuH
ud5ajKCxqjGpk0LEE8Nfpq6UUp1qrFw7//ciInsxVYbSdLIKpPemPzlXABDbmH3TsOIvQTeP1Nx1
DWZC7mrK3QFFJzGUdWVf5MGPEvBnMVL+Hgu68kfpgRfpzQRe/Z10iAW2OVKDbTPyq1OmyPSl+ddN
GDkqZgSDeUnChiLKfYNW34XFFgjmAxSFGCabbgAlaIh7OW8hp8J0xbDvvEQb9+qgqOifnsrxhjBS
3QKQxtGStBXDLqWwJXuncSrSsO/ynHzTmEW21MxgrJDdubSfASY8mxdZ9AhjJMaUS8YGD5rRfHq6
uCLpdAGHF5/VDyMi99m14aw3a+pjnmOeToZf0CVVYL6wE9vKxV0V0VzvDtB1Mi4tmYmueeujg2tM
ach2yEcEuW0h0iCpCey42oR/t9/ym8TsOuG8MObq+Qdltu3RFFTY/dko1tlMFQjRhLt/Z8qT1389
3mp0WKtlpImMPZLQQ25iw7kbBdYxAp3RsSoDZrW+BZmW5wgFcg35bEOe1eA5vQihDkown5jIBazN
OtDCZBysxVt1JkI0CbXrqGWmXwxubCXwp47dGNL3zIqJdoLDtFqSKLeiVzvGg3CMZCv1GkIzWBry
3GmgrIoJefRaAAcjNwUFOAUKeh0Ci72bHoxU7FyYY3VL9QOKsrss/Gh4FCFxHVxjfs7xNjY0fydL
gSk5+mGpX+Pc2HjnrvSMOy30ldZM+NotD1auczzJy2Fp+cZYToB/SJr2QmHFZCv0vIZquz2nq43k
c8Eb3uBRb+G+d0rPYi+jYjjN3eM7voFIPo38CLkjt/PbMYaovi8j9sff7Eq2dnxhsXHk6Y8OMy4+
aJO9QKy7MhNYxMw+qDOjqZHb27+2wsAUvsJ7CSo+hQtPOSpVoM8C2Rl3lQ/kNzcwLGVW5wnBBtrE
xcub+2q0L/D24OSL/9mqbj7mkaIEhuTlnPqUht37rAkeSPr6u1kbUxCp0Nsf0dXQ/IDJALtqUbxm
5AMiEyRkFIQrKGialgguv7JHxDzrWpn+cpALSU8OxZ0/LZcLoW3HYPPi0e4o1p8bH+anWl2zZcvd
LTp5Xe435/wGP+iNQrMHxtkwAtf9AhYO3e31U7VLPQZhu7HbVujipeN0gC1+3MymM5P9YhcdW+8i
/Pbom79+dzJAXeUKaOJzvXkwZ1UexFMAO5bqY/KIgH/fmR38d1XPphwdbbZrUGCrN438k0T3zdGq
JAHcm2l/vRwZqNZP3ZXqninUfFkeVYs023MSThRr++G0Hh53X1MugU2Hio2oUAO+HpdqUEsUcyKA
JPcO7WKpB2srnnGV3CyiYWFj/hsLlnl5zPRmHwv9Yvi+OAG+ZDmhk5Br9reMUrKDof+Ix8kdo+sq
sGIdJpgy99LLr5tR8FHQnY96hyTt1lzsas9euh5CrcKtrJ4Wz3GtyUMb4nwGlNh2ANgAEoixl4Ug
0jmmRNGbkjfM4qziqrdDFBp+Wdt06KPyTdxwiM7FdtmRvJ4Fv+nppFpsHyfSzuZ78M2dce4/O/hj
jTYEJBtSI6jjSCaV11msxfKlQ+IjmZsFzxL8geUnOjlvWrj3hZCn3pD3w4TxLTm+Fl4zxpTLjrke
rh7UzIws+1lgjtHkoqvSIo623oTPcqDCLqHdRQeczJBhx9K9h4LMfgA+HGpAM+DT9kYFwvzJOEWN
QjdPKk86CVJu4d6CRpWhVgGZjKrbBaezAcp8KRjRfh46K/qIp7kH/CHaFfDcjuryk0KcZvB4xIAY
B28x4Cn/tZ/BuK75Ln3R3OHByB7XQHhYhZbMcq3RaK/255IETehjwyy27GMIku+xhy9WGbnJYziN
UF9+aoqcFQKUOPYu5K1IVYFdfFSdGjjfAeFaKngamh6Oay0rXG0K498HNQlvvR9YEGbo8VCW5e9k
pVjJZimkBrn1aO+9y9UaZ2erwyvrhKFDKltgqXn4VdFGy1fKQrM4LQgZnLl0Mvow56za7IxCeCVI
g/62VqEEriXAgGl+sDfSOWSExs2XP+dAfVLT44u/WisK3V5TiVVC/59ITmC6aXQgnVaLU/82yQCh
iNboaqLH8PmEOvIDCeMf6jC0u0vmooNY6wb44LtXyrvaNtx0TvLd9ncqI7pGKnbzTrITgQKkB7tK
Qj0v5q1vZ5pn/rbKi+w2t209p3iHKo73IRb1PgpYl/CJqZILm8jetWQZPSJ28e1QH8CXTYSp/4aQ
D2VcJo3yw/GB8GUNnE+QDUqXFmrd7P9crGJGjGzWgv8NUbKOE7waPUchRDLDqRcGLFPMD3HwajLZ
2VuYJfC82vQZdIH5CwWtI7UGCkD81UvFJa+EzGz9h6LG1Pa88L24mk2sBSbH0nLZ4CXy+kGZgvIU
eFfnjO7zLDrRM/HscLh93EH9ONqfsFEhdaz6OsVEmQhorhwvUnw5iOAQMWipp1D7pud9kBku9c+H
TWKX5CE3Z3BDvV8KV6nZFC2Ew1GqcDkwoJYtLmghLKEdiWajotIq/YGaGPJUEGSkPLnR7SWVFP8+
rcskvbfrAm60pUZFdVIfkV7SuEMZyLAmqArlfgoo07pEmNbhuYXmgqUtYTclSL3bgbSg+XwOE0jp
dvun9NxV/7rj42gyQgOwTIKk/H0X1+5ePO7RkRRBNpmtUesE7K7bbt7p74DRqgrxI/e/ISjOA7XT
/3mPiTiqXukKUrdYID+YcPzIQyGDG2YFgn21WYtRv5WPFf4mbhQ78c1rAMz8ALsMaBUVvVjMn0jZ
4rUhe5vp0KkKzkfQ4Y1tpp53SzCjrWUBv+HcxcC1HgV3n+IaChk+QB0Fs7P8dY26Wh5lIm5yBTJr
YOUviSoV+madmeKjnMcC4xnOXWhdW47syiDCVJvjVXkirB4ft78ZMrmIllIA01XXxb387KU14Us/
pLW+/Gu0coNlsDELNOFrpaJ1URExu/LJJYnUAPjNIaLnVLyQfrwrShxeyCHLTrASIKRYPWXfhFCI
Ea0d/UvOTBkvpXAoSZqCkpe0NM3yFi68r/PtPf8vQ1aR1G80hkeUuqi3/7EsfN/oBe0sSShKjM43
3G2E/WfMc4YIhOCtncmaCrUxlYLpZ/cj7ykbdFEMBn2PMGlkbw07G//KfdXeZsFc5hHOHjuqP9ey
luoXN5AgmvsZ2aRMlALiy2iCY7QcANymZ9GnVGyI01r2880MbEuj7I+N8zm04AsEIh8iomDyzUfF
tC0TsxfkKJg4RgwGYorJJM5O8Kf4n05oRH0xtU4uYlWapyoNSbE1pamMiPHAMB5x5Z47LlwxpA7R
L/B/0SqJ0XdZ3o1wEIg44Spivbzd6UxiolIZPwT/lA2eJcSaDiD1mz6NqKc6bn62CpTncD5lX1b1
hHrHEJHii++vGN1NIUwHUhEgduNcpxH83GG57Gx+kKSn3uAtzt0NpyFDLw7WOd6TrkyxY0Rq6BLZ
6sMYhMOT60C24Ej0tNNLyS9H3UwQxKaoMdnLnqtDsskPSPRpthPXTO1bqjRRziAt7X686qZoKA6E
idLmUEmdw7a5ubUZmT7fnDKbIVQcLn38U+/BEYslW0tVxqbKm2SK5/9zxqNU9SEIjC3q9Frcmjqs
uINVN0Vhj7hhGQHG3aw3IuHZGaHVRdujOVay722iKdIgxBCkWE8+sFkZuWVwtd6bieUKD65ZFpeO
5qG+rIvgm/iChr0DA6X5TsWVCHnSNrrdK+hsM6Q0Hd8XXGAzCgeB8dxSBwLDRxpwHK9qn7/yDDs2
wMfy6WImhEo5P5ZoXRD281BPJnqoJL5du4N/+lGNT+87NbBwM2dy20tSCoR/irWvhnpI1d3qhgtW
wr73nKVBYzrf4sNXmMeAVpxPe4//3AnyT75BJSCtpbydrkrhzkZ7djDGRO+4Grm8BsGoaS94JnBR
L8IgtSulT6E+BZOd4S4JNfqQ+rufSruQcLiM0M7kkqh8ZJZbrUXa6kUHKVdkSNm5x9WhVIGHjxh6
eXZyY1PgvJvgOxWFnp1mz7HW0VN7U8kX31kl/dGZys5X7EOmPh4CSEz4oaQ/R2BEBUAMjDdRFxhc
mpE81lfZ0qzRd2I4M6v7OPYH2FBuOQH9x8YYB/aRmKR3zkN1g56N8dyXchGQqnQUVo2ahkU7lCNt
i95xSTAAH9j+POXtNgucaMQ4mSrW3xgUz2/nAhI1Ex6KhLvaSLx7b0Y59u4x2R1MR5IfIjy74NCO
fDNcqo+ni44Rf6hnRMkH+WH0Y6gaQ/1WuDEVKfAhCRiercgDc1BkroLBOAP+A/MPuhMPwQhr4hQU
YnXmWd1xDWo+rnnWSOX6NsC3NQrrdv8FdRqi2x1h8qpR3zN62120H5uXyk7BXN0EmLOnXBex4al+
maWcsE3YtMnAwdf/8Cqn9k6oOlYEklyT88ADP1k64pXFyyEpboI7h5Y1QUlqnlgwc60UpfsyLRLE
f3R/NcArytIJe9QeMOgww4dkGFFqx7GPLcj7ZfJjZz4qEXmAsIlMMyl7fHcrv7P82kFpzdUWXEUd
AX49TprxFzXZ557ziR995/HO5pJz3Xq4M6umzRhHgAQbpPr8YfWRBnDf1FyPZAG8e4X/N56WTml5
+QjldBaK4mcEedK0s0b4qUwGFnK5nPw+tSkEsbQcmZQKGID048Sh7LpT/7GbPocYSXPxD2KvhS25
Enumryz/aSOMLUzYcpnRodQw50sdi9AJL7vcoXPG38g5D+k7BcNUVXR/OvOu7gCA9cDfpXR3md+B
11PTOelR0XeJkgzhuzSXnhMvflIiO+1L9uwcxt+EKanXVyxmEC/+mN4lqeCLXDMw1uPol3r3RKlt
UkGMsbkINoYEdyuTzSAtQrLT6G5FPcgRqybyt1kI6lg8yxS5ASq1l0+BT+ZiEhP1BaKskEXLwB+N
egNIOMd2xFy4zzE9LjURGLhe+/x6UQ773pXem7XX0M9UmY3ISwDBMtAYPCgqrd5VorMRhMGGffqi
6n9rXISC6b7sPj4JypXlnUJMM3fZj7jXO8fFsnd6HyFajTZ1fvOUKHMzqEqsjmPPbsxkvzl8J5iN
TEalT/CKqJkyHVS83f3I9eaJrLuR9q2IPgesHkxPTr0U69x2H/wPKSpBuMov96hhQw/iOjAtAozG
JAJW6BX7IYMi5/k1can/YJMx9mpTxgEo2lyDjIAxR5ftmz7llX9Czqu9lH7ebjAyjO+JUhNfXn1Y
17vie6LqRAT6ssDXf97nJniJywSODr5sKG478nDq8Bxp+yHWrIlIPGCgy9goZo/33csYKxCWcBJ4
2DGzuD3MrqMuRQxjaN/XTvOF8Fi24ZItQBktE3zDVWQ8VcHeu3bSTOvj5LMNQlP9G/R9yOSNTruD
wSUwdhetI+5cNdTl4ikobEFNwDwdF2aXMAbbvq6WGucXHPKDxrdo069PCG2YjRjOPHI+8IlB4SFd
eZCIWCHwxHYN4JwAi8bcok07kokPttSdExiaNL/pV1J6N8BVYq4N63rWjvEwJzAcyGLuKVjL0VyO
WYacSUL8oXseOTElAw2O/YomDSTLuAOSz7Qja42nI0Ov7fveFQv9dT9KwNqLZt/yjil/MFWrztra
Zxiry27d7NrynunhaMkkwS/+05yzVsV3tvc2v1zq/rwjLpYqh9rxVsPMgvSyJe9p2aGlYyJlAiV4
8d4nnAcl+ptCE0gv/Uiho5K9aZe7khuI5Orios7ofUxHEUPc2lUTQePTmujedsDbp0ZRl/We5x5K
2504GBUn7Hrb640o4JnlbnVx14NAjaxVyOWjZfuvwMF2VP+pYqYWzUe9gNK0uMrvo046UbT2oVwg
8u9aYlza731MlXiv/e46JytYPNpXLVdhlt+lFphvaexGe/wM+p3eqfCSiMc1oeZz4h5KuPbIT87x
9R6ufR7gUWGdLo7CVzxxOZuTy3S2riiTlRBLsKr1n0dWOpnK2Mntrc4eU6N7bXaPlfTJKjISbMZT
M/rbm0ix/4UVuNJ4RXdFcmQUxkPUTIw1O8GafGoul4UI98qRHQK/2+HwLGRGD/4aUuzEqRgUu9nw
mo4jFtBQC7ZrGQDL1ufVCZGVpGgDCRYE5JKfhWvUDwhDVIVet2AVFcpMK8u2gBB1p+xKk4FO9YNH
A1RDqcFxDE8Xa8IIGh8NKO0bksMruFIR7pnueZezyrcsso1MswmZazZUGdfdxLZA58wmFON3tI8/
y4MvlXfGTiDiEyPGJmJqBhVd4wPIBGi48gNM/AAf7vy1NaS1WTqSwKZAXRA4cZkmmDiVhdVfiroL
GKSBslC0vKt3qvZGGJBF5YW/V74Waq/aoBfQ7qRy9U+om7PokcdL/upGVOhflgWAiDTbnNPL3JSr
opdKgsA+qZkM7mtSAX6PIcgdoAMz+Be+Z+xaNDpEaWNSCWfcHA+MM79Eyqghfqa8T05TYJdZmbrV
JpMnhKDcKUti0r7Je2CIIrS1M0EB6zFeqErJ5viGBfDGHUTsYlXDdELsxF80U+Dn9PaJ5gqDTyan
lL/985tGVLxYvNlSMMMChnXxg0HVbK0IBhCKjt6rGmFCaw33QDOgWOt1KH3Ea1cdPBf6XABISX6J
ZYymjJilaIMdqo8LvXFFVUzZYzRXDhmBIW72OKLiFlNfQjCwN3oxEm1LBxRwC799QoFNt6IVXn5X
xmn7AFbwTb3qIDZ4jRrVAhe749wOLjoARFDtRhCGZM0K6/UCMBCNEfMS6ek/tR7LF60tx/fcHQ7k
np2VaDaHxlJGU6Prvf2sFJpImd1zx7pkP983XbBrVlsGdYKTNXinfcRJGcrbzrqxCRFD961geE01
BQWK0iKzWtz/JxW7498Bm1AF1bEydh0jsbicDYb+tR42Gt9wzRWI6e4j8Aj5eG2ZfDA05Hep7PiT
qHg57PsoQMmi526499DbNX8lWeyhkNw8UiAngV1M8qHNByJOPXE9pMFs3lTeVl3MSsAh+hxUgIFn
EVlDJmF4GH5bSjR/JrrHiC7eoYAlNoL72Oe+KRXqgqNMcszbH25gBMMSfEM6DUuxv5/11GyJCB/D
+S0WalK35obPjux0N/FkjMOoclN/tOdd1KANgWUj+miVLd64wk4TMotZjGVKutsiHcsygyDyL+Fb
kd9GZmXbXib9n4qy02vNKy/o1vz6bNPdqTjGHRD4HOxx11Y4br9lqENS2hPcp/IMWVv4HFQX0cg0
c2VmbIb3IyfiRUR6NUmBVHg4IEH0n1aGk9w99BT5IQe9E7cvMwAdSsnPs6sxf1fP7jFGN9FToM//
VDxRoK9BojMwwFWB0+Iby1SEZKD45wPSy58sA6e7lBNjDALfhmhMOwMgFspGMpNgs8yodm+tZvK9
zW9zdBlDjwlAhil4BzXOr6b7knjq1DGgP7KKDDFlbZw83OWdCO0iznUrkP4mVrdKtwlgrS/kYDds
mJqNEeSu/LwxUhnqwJ1DruKKneBh7aUR8UtDTJ4UM0BY8CVS8Umo+dJIrrZjdR3fePraJOxZViFC
SSDRmhA61hrMtl+Q+pwdhzeUwRa5PGXanVXjFFUnBveT2s0ZALtHNz7ZxFiTCx6Q9hM9xJWTcWnm
z8w/jXam7HNwnyBqgwfwVznAkZblf2ltG/plI+Ws+DEIGxtCrDOTktz+Zu9oHqJQNN/KxFrrefDp
VYXzCXTMTw1jH40MZrHgL9vCO8r2Nwc3q5JZvyxEYHQE58I6fz8U42KJ26KPFtPGTxUQQAafbWWK
FZuFPE9McVNP9t39UdJdY99vUNjod5uV6qDBOVXnJ2lLPjoqkyoJ+cJziivqzwwFZCrrR86DLeKc
9rcmDVfsL4ZyeFiuw6j5YDDsSaXjEnJ37mBCZz1H5bHsq+4LClZYSTTFejL5o3vAZ9W0UET5iUqb
Ifjh9egK2LRG5b/kUbu+RqKtsnSM+TTPFW7atCapGyjZrbemQbZXBD+QSrVmPYpJv45O0v1DZDfS
UjMPTs/xKuHXTdagLsvh+rALBDOlqD+3m0m7CwYueVK0IrTitgikX+LWkItcMC6mna9aAnf2V/ks
AK36JbAqHpYzlkLQNv4q9mT1GKfJMNhaag32+KnGLb6mnCs3CtYDeM7Tl9aRCxIir6iddTpZzq+U
kJx3V7P4/sKu6J5R7aWww0QhkOHpySGMh2i1ZnAjF0xJRfaN6IRTA5jp9+aVTaDwtWaTneNVa6Wc
xrIKz7ZMRTC8r12MvaOLNYO8W54PLqVSJssAL6BDmD38p/37WHvjIAbLngLeojBIggCzjkDCuaVP
7co8hTks+S/1gOZcG3T7y4+yCuKOlgyX+CPYYor+vOs97oszhAvfw60rwHTpqRmj2x6uWIQyOIXs
bwhGDaAhDL+z/ZrLfSvnkXmqh0s3nmgfkCrMAKBsVSxMj+1mDeR8+LE9r1AoFVISY3i47ForgInn
JobJHcbRhTizlb1dOnbXU5PFa/pUbmtvU9cIz1xAiol4em8MCAe5T2CrhwPiRJ6r4L39oiueJFaH
14V4dw63rqdhvCy7CK7MF82m8yZl2PftiMYe7zQzdNhbpMGGmUtiLpZc68QC0ikK/r4OCGQ9v3HU
glnx/bTCRHR9Gq9GK4PaNqyFjDbm+wA6iPke7o1whrTBBeM/4yM4ZDN/mhDQic1xOkKgBezwoLaQ
Z88ayY0xpWrXUBdrMVZpYiYGOxc9wBCujzuMfp+8DHEpL2msOjtr32ZBZ2oPiOHDy2t9plq5oG3j
91z9v/Ex2j/Jrgi/4sYsKOeIoFUPzc6eD/XDwFb6rHGbtl9fHGiqjyfuBHpQMDt3fVcZKcS6h87t
YZL19+alWHWMBCd0zv6QDD2wPkwndz25to1byZKCIAs2F6A46qIgLYg7TIgq2++K6//bRcvfXNkf
TD7uzxU4SZdGwQT2P31+kTMIkcq1rguQ81r3dlp/dZlK7zOjPXdo+vwg9zaS2gZIp2Gqt0cU+673
R3C0LkStqIv3DZs+6xNw29aOTK1U79e64YSRLKIqD4fcslQQbEvS7fiP+s0Ft1/5qizpoELD5FAd
1dNeU4wuiH8prJQspbGDltW0So0z7bKpOeo4/kjPzI2iLCPqRPU3aa3Ps+Fof5+5K6Z2uBisT7RW
rIc3KNEbqef8EbwWkcLYlWk91y2Ejz5tf5ylQIpmLS7QaRMP5s2a5ENBdVOUXZoYnciV4GHTNEnc
UkE++ml3X8J2445n+lmVgac/2t0IhME0Yg6cUFx+h9fcMZgu8/FHmgco7DtrvuiK9g6ecC21eEi6
XohYSyHbI9ets0sh5knFqOSdiPErh13F1gb8HnREItVou9RI386sgMm9dyBiu2HoxS61o3P6P4Gq
cWSKzwn0K76Nr3UEBUrajpGEwMmVy45OfrmxY0u4CY2w8QbKPkvfb8H3HO8EBCYAohC4TEpF/kz7
dUlprFWblUiFxbT/ZyDFcIIY6ENqmTV4Hwv9kJRNO+dCJI6+yi6HRlRNzCLQztjCckuVngoWh6+n
L1EXcvGgsRQkfxW//9Qpn9fjOkXWX/EO63vJri0sdeqQxev8mQIyRntfx48ZFpEsEJnXnTHxdkQg
Y2lbMsu8wQgBHSfPInYG2mHi9YvS1qvIGiiJ4Jx6C6B72A4+pA3pzJCSnJZ/Z3tcWcygIBlJPUG+
i194gCKqh1u6IxAShjj0deV6mOVd8oVhmqlDUjgIxTWiwEvWlX6vLQbwkE0FiUyXuX1kx7ZnBhwb
VB+rmqp/O9uksguX5MzZ6msTmVlZtfjdCDZwC8h81nIotgvkwQeFqCbNtrMk5eLuPS1aiSuVtc0C
rUmnx6Gsej3tGDSXh5e1VhHHsR+wQ5CTXG0OIcXSrbgbLzbsJn7sunKhU4k410wj3d89cnHkwHSR
i9944JONUlWxZgE2il8gvXvsnRhUxJYdQkRRWoAU1BZ4rEVzu8dTBpKfIU+YTSJi168pDJTThrV4
Yiy5nUDVvCEwq/5c1miJZLIVjiRq1HLrtO5/VhuB7b+tXAu1ZZFaAtKZ4TjyySBJBLMGDsEOKoL+
8EJqfZiy3deiyCN9gQF0q1Kvr7wfOjcdOyvRPct0Pgp9I9p4HVEN4A9elXyKPnNXba3W3jqeJ2tX
BjZJh0C1svafjqNs440qfH+U8lv+YcWSjz0UVllbZBkJ2v55JUWOVcdtyl2dMdWqivI2dLhMORxz
D2a1m91DcsOYtBO9W3cHhBCd7Djem+Y4j5YtTw2L3f24UISez46HImbTmZ34TgzMJQZPSBUnfRWf
T2YcTshTMXbE2Um88R2f6st9GPCmkfkTeQhs4vePBb5CV9erqS3tp/0DWsLmz7uhSWFmmoKkKi9m
HV3Gw9oeSIAEfQ+fUYCd1pu1Nd81oV21KAIXTknB9Umud/KDNCPny3eq9cxQv5UsAl7Zh1hMO3f6
3nvgd+joaT+VetiqwElb99zRmyGZ2ZEmouqZU01EehdLVPeIHsFfNcVOzlFq9pehedcYPtrmFJHG
QhwK/BV+Qx67+a5O55mgL6w0oG9TOJpBB3B5aRxkNmW1k1YyG8rLv9BnGytEZqQdXGq/z/ZzdJp5
qjkNQtEHj+t9CXMcAKkCtf25RCEML5soAvUSIRCj1Bu1FEaPEHujdG0hvHXDTVtlyGt/oJu0Z4H8
T7WdFwxWZJLDkHllCcXVU/2TpBaj2PIZaZPEUoPur9pYhz5yaW70uRcsnxrcXlO71wcVJBZ1id9c
vfjHlxTt7YdStgtX4zF911EUWk5qWICgbtMjZRhpEpXbqv+9NDecBNaKlsMH1JIhtC6teWvZ5mxO
5yAEulAUnJ5xdsI5XdfFs6Kr1n/ySg2jKIPbMOwGGa+XPbto7jYF3IwzBJYivTaw/zDByy9nQVpz
gur5Y4JWAhiCWTQlsWOuJYXNekKT1cFBEY98133wKupGODMs+JKxX1C7meBwusBKCUdEeZ9Y3ul4
trK5Wkq7A1WaZS0iG7MPNNIBLFoPihaulBfcz3xt57Vxy/EH2WOgJaHayDm5CnKXGJZC+wLSUyjr
yKVJwuL8AcQ6w6BkRURvWga3CrY7b5NH7pNvW8pukanBK4B2GVnRU4q7Kfy4wdR5nbeo+qG810HR
s2YwaqGaU1JHow5wyRLwxG48Y3Y1ZuJTWhtehfGq3gdBgfng8tC199zttW2fxH+6wmZvgCdSGYat
ZRonEqUFkEPdGH7krTFgbuF7+FzkNNJcBUHkHlfryQDifRlW7ObHkd5cWH0h957FSb8RmgpQtraR
fSWILm+glXh/dYC2wgeaBtdDS4qOUCzUuac9zBM/vRlLkkKcuIew9vM+0Lys3Jjl/jbBE6kpV9is
SRNU85vqyImCKQBOhwA8wlHOsDs8pGoB4RcmyzIcPgDOJmxBjl+wN9dVENA6D1y2u8HKfhIgqG3i
Y+tDaIe8HmpSIiSpvHOKYPxEUqMUYfeRCdRKnzv5UQ1Xj36xgvYnwhrIIUs5mOrfmVn1ELPt1xbg
c0VZrzXBq4NkOs0FnXm6ocAzdevVhCqgUZem6n8xGVPFjo6+Np4nzjSR04NiwV/I7TVCfT/99a3T
IicL7iyWcVXfaLLJjnIiggcgwN3qLDODPAs+xWmNwSljOc2/nAdctzig4L0QtAL0W7daBYa5OGhl
sKGAyz6TeTpModVVqCP57UkBbv0+lbw4nuEjgvSaVlnh/Hx6jBkHKltWhUitJvAKf4WoER2deG6Y
52sOOSheDuwxyXJJ538heg+87psVrN2LJFnIkM93MdDTisX/LIxv7oW8QN98lyDLxdQ5x8YLiZLt
0cixwdG1bLJ/0lHdvIZb62yM7QvN23V1ZhhNCqnTwRbkkAjtTx2DUq28pisAFdWASDcBxKZWaM29
VLdf8+mX/0on29/rIUHM0ps5aAgCrMN2H11DUb6dm+/Ow0w9g7209DbUEWIkMcJEcczMdT0Ft78X
/ipQ+fdTJS6OfHSWwgAMeWrMh5Dn/IZcNQMuQIKUpIQKFgzQl4Fkp5fQPVKUjJVhqAwD03roAYTN
xc7PcjsquntNbv5d8wi4Fby2MAXvnGCRw0q2983LcdCkrdzUX+U5IDxynOeQyevim6CdMPo/LdPX
RSXjP67Ivp7ewGcbhL+BrkGe8T7ZjuaPQv/U+UKOYsQby9ON6RbYZVyxI2IWTOrssm/vZLSOCsyh
JOzN/qyz7/EfG0lPrbLPO+gFgaKCf8U6Tf6IL5KM/KoK4X9xXMDXqWSQkI67CIAj7r/NFDY7GuCK
U5uabqEe21lr9LfX4MRAc10lZuIsYvECLOxTUKOHnqUlj0KE9O5bVgRC+DImPJJOtDVf0aA5yAQk
IoLGGNC/kb80QzMsNHI8eztbr5H6XgTrzh7vVH83wn3JSUCCQHb+Faq9zjKY5PTXEV5yPOTm5sI0
cK2jVL0hYGa6ZJYZuxW0nRb/4pm8vG1CN81jcs49zI66Vv6KKolxMRlk60e/lVt1ivvNe9SygkCt
Xnrowj7YEv+N8MD3aRTJShRE/OLv743tSQ/Af6KCWirG76CBiUA5uOi7dWt1lfMdv574Ln5JNGr5
OyS2LfTnjRrM/LEr/NDj5al/TBD6JX1es37o/flSbQobfV/t+fw+j3qB6kq9SaBXncGWG3e9a0QP
JcUy0uy3nuw51ISgciNvmmz2UotrbTwS+dUmxf60ipN3WzfJs+yfBcglbWHBJuDOmDcDmYSVJaKU
qeQNkvpkaUH4OdGEGLiXVenDj8TBzXcva2myeJo4VYTl6SsaDwN40/qP89HhCBMplJy/Eyknev5V
oR6VmehoDejE5GDyV+AB/R7NnyNmXp7xP/4Z9aHvqG3E2yeMdtsAw8irU15j86M5tuAjoeNSoD/K
LkzDRrEslri75wxI2RoDGPTnkTeawl7kpls9tC4l3Mv2nXi/a9ebNS7DKRwaVrIA+oCucaC5ug6z
kDm8iaPElW6qIem5qF8pNMuLz8DYSqld64O41WzXNS8/1wzQT5o46r+kIrHnUz2AcWl7RydYiuXU
6rcZW5Jnw0V1yWNbPHSAIFUfu6dxKOcIbQu5ai0XxS9JTmejWGJkwP6QLRy9ALdycc+mnMc4uzVb
EdWdR79JWrUV0SuRp6kqKpqEiuu8bHdsr4I+GohigFta1HPV6BcaOX3dx5HBNAg4/m4VusKvZYGe
VH5QIaEtwyXsDgO95NYda9yoCNS1FjrTJYdjiPSRzU6FQnW+L0ZQGMgcuz9ndo4bsVJLJiZhq9Hj
SUmR9gmUUHGrp0ZwSZ83LrbSJXb/DyNE1Uirqg3mjr1KjQUNbk1b2x3Kr3GtkE6sl2TOGH3wB8SD
wHoxGhHztt8uNPy2gA1L2DAuQNnYyMQcfzNTeoNKHMVyzV73yUrryMDEtbRvSj/w6mudW3FUm0J6
xSwONp9cSQ9ObyfqHQvR6fRzxqvOxdzSKfMhq+67Wnc/nWLEQgd/uHN8jCxINrXSqFrLdLq6xrhz
Q1fwGQUMQltvhLo8u6Ac7ZXoSkrtiZjjP0vQzH0qY2+PkI12mEJjuRX/REGjrt2FxFA0bckl4tn/
RNwcSZHaLj+GyxDXmEXxWKqsnMDzGwK+TDU0wXw60RZ1uFA1apfsL2JM8K6NloS2x006LMZPVLaF
70wvoYTjTQnFn8D/C4zBh7oBId+OjwNpMq6/+iv3mVAIxB72tP+mzHtFPddgyzJeM6i0yx35kbiQ
7XUWzzSi3FXiXWY5hP3fEJR5RvLStoHWZ/qsJj1m5EUJHk4Jdo7wXLjpNU5LtKcVyRvIIOfhmrpa
2MBoW9wbwSHX+LcOPyRp03QDaSBJlNoKy37vyd73Up7Lk39z601HKgiLMGzMhgg61Sl7f82GoxpS
ewei68Ui69RjuG8bvb9k1KyIUBExOyioniJCOiMlAivSilI2inPC/wx8PXKRSn7XFbFuYIKwRX8k
AFJgc33UtTE07rTCVDxy08nr1u5TnTu6B3CAByRpjj41UE90NU1llkvtXKS3Czm47nRXU7bF9fO4
SqPyH/V86u7dujziDN7zOEP137duJSV90rQHSAslwQW8WbccWWAqUVQyqNNtjotSLQFsOqdn6GUA
WuVNXwaVe86KpRQo/Sap0xdYhPvmYbOjzJDHNobh1gVWeGgFo5uUdNzJeELtnoBjJs6KFbfJgGtx
11BoiqtdCh5B8QaOhj52GHO9yuFMaGih112JijGc+NkL+sx6tmK/1OVuuafvA6XmgPpu8t3vsz9r
wkleF8nZu0kMPBcb/ZFeqEoouyRHw2eBh/L4ZylSmuz2MitR7glWH0eypOXenHJ1gvo+AZigwf9J
QwLF83sbBwamvy6yPQC1JBFVa9OBqp5Jy1whQAHKPjpfwQqFsWtsihaGzC8dtiNjsGyWBrCk/523
5CeLxcyqjifqz1JbNVtHChHdvUeaAQOEFic2h3my4G8CLYxW83NMIwQvd3ITG78BAwJD+2ohh16P
UOoq67GiZCYNc0mX8S205iUtilGXxYhTKRASaNqzv6A+HtANLuCyYiz7YJ3D0h6Z89H6af0qLuFp
Ef7peK0gz7D4XjmErFglO6EfjrVYaPA92RmePG0Q1RCxw6DQ6StQiJxqdLbPmSt8xE3y+cUedaYF
Pe7lKdN3wRTUJ2GE4+f6tocLUngpY/T2CcGfPepaxgL2+S1JKqLQiq4s/LbQ/udFIKwsPnyV1xGi
AjCjEHWmC0U66uF0z1FBihQMWeX5IvWdDjm4SQJf1h1kzmcHW+NCLHwMgoEfAQ1b6jH0PLKK+8WG
CBZBTfHsaqXyxwxgYXiA8v+obcyggjC6B+wgUvSWIHxUjFbpOH7B5hYEseJg77wFj3IbyJ5lfYE1
PD8xsAiM3XA86AKqQVOrv2R7ir0ZOJ2R1AuK4VzjJvULDmAcsv0lY723HbGwb550BiA27uXaF3Ds
Za0UXpnO3zkTTP2K+xKMvETegtZ1PKgaKlJmLOae6YHvKvK2CRrFyY2btyw5segHASFvMbhMaDxl
6WfxoFUfWVj0ozorx69ECJSKOsd6HwYfDiZwdD3UHl/CHwPxHG6c3yrgMS6RUPPed7pHrZ65BiTM
EZughaWDtKCZxEeTuqq4qOK+sjBVmMsUVe3JYqelDbrwjrAusCey2QUXHN6Uq7Df80XBzFP6yTab
GrAfhkNFxrSyx39wyaJRAWH509WSCtHgF/GgaHQ7jp068AGSGWywGbhPoJfoYPNgJ28OY8LBWN5A
LQZ1cbs8n3fMDpnoJhggMgdFO+FZ925Xt7ihbvvdcYxNXePqB3yuWIJqjwCjKe3hZPvseXy5Sf6g
8P5VpZez3Lq2zrIMh9Plq8d1ZyN5i96uiYIqYgDmorXuhb0ziB3mzaqZEY/T8QNbc9UrTFRV0UZ6
WRfzDI+IEpxdprbOx01SP6W9+Q+UXaTUeFmcaxcH/rJ3yjlDCbG2UbVDMMCHyRhRbeqie2LEgaDd
5qZpoDTg4R5X1EzqNTrjLbEWl0BmMyMWLbQkz3c2fUZkNtWvTvK9PIg/ViZkNiMohV5GvwNXP3rj
LoH0zT8PcdQsnFCgp8JbLCWc0m+Ewo7biJHhWodGXfjyUhP/tZLPkiZ3prBitUhRjN0CXqfe43/L
hgY8OXG6cSV0/a75/ffC5/VZSVHjRFLtk7SAvGX0AuGVPGW8W+4yUFgJlb6yH9VHUFWtHWz9n9fT
uNBROU0aBLZxzpUIqnGnNVut1ym6x9OPUZUYRp3Iq0Np1noXCJ/hnr7nMu0wYVLk7lf1QL6fObzH
i7rMDUfodaxGOw7cNVOUSOG1DTZKO+DoIjFZ92Z0oSYsYZbVek4qiNkKzS88kJzZItoAEuqmTNl7
w0Nz9vzxuQ2XNl1ypTBxTVF7X2zMaDsco8s0+qZK+Y6jmKdogoA/hx3TtpWWlOhKhIcTJyDpnzF7
N0NTG8JaRIuS5mbCFyGJguGNSA6hm1VE90rBg37fNb4CUc4xpt9nhnZXgHsJ7rCXtI8n2XrHIfJo
yy1y0EfuSTCsoah+/aYmpokqQbC9OZy/+qu02kjenolZr1HPmctuZewbqfvE38KeIBV1bsFgNvTC
qPx9gkSnQ28vYBujgGHD2Uh34gGnfv6t/6cAaEQ4aF0o4OGnNcIydgkTYD2jsHtynM3oxJrGEcuB
qzf6dKT1ke4cYhjT/2s9fS1KvlAxuR4otsf6uXW7wn45bFAA18WOONj4cYRs5sF6McS8nUbHghfc
SpV4kmgBouACpH1b5ENAAs0JlS3o9K8jINunUuf6XiqiTD7T6OX/RLxG9CNx6o4VAaTt3dz0BFeR
+sPrlS1MBKotN98M6+wkdt08HDU9cTGAmnraqLu6BLb1/foceAxbvIEsYQPyzHQBnLzqQK5UoGxD
KWH+xpgQVzLKK1wnknLPj9bcx3yssJFAB4x5CppIZTsHR0/32/gl/wy3fHUV/pmJtxmXervLKKcd
9gZ/A7a9jiySP5GNGhPR6H7pem9seuUmmZPwDh5+X9NSiYIC8gBHc0aBSfWFDLZXVQ4IEBzdf3i3
0cGmjbxrVxsHE4RfIZLZqmQSGJ+3MDtLJOzAVteGSKN65zZ6LlQrJ/UBe82igEFv6p681e88mJrk
FSXT4Bn+VtdTdcRBwKs1Wh1a/h2dAdyVf5jMinGFyNtf/0h05rowJhsVUvm02VHRoEsXvqKNvLuS
JjDI4EC+Xa8n6N3LctX5wmg3AvdTuk7Rb1504/nZsotdaa87pM76jqvsAfcmLL/YzfucTBg4MRBE
Y+6jVJDYaCGLM7YXGDz/NdC2HE7Xd008VhglogejBfrTa2SJizpkYB+3tYeMxPB/441stZp3+zYo
0GNsRjL0Hz7RQE43fNan88cy8Gh1Oj5BbCY5BcjHjwYf/aCdylZl3qaPABTlXqBacScmjrZ7Zll7
xieXzgrEl/kfPpL73mf/P/+VHQmb0Ie9rqUALgZDC9omoSr57W8L54qAMCfSZuBsDbfStDMsHOFc
JFoDrlxijXM6qLCblBTUWAviPw2Vvka1HqON5nSqfU3JEGQS37emjoTSzaGTgoFbFfVR3/ivuf2Z
NuW7gxL3i355dJjxqtuBAD01Qq8iTmk78NOfqcA2pkSRiqd7E9VoE/PArnW132/fXxYfucy4CTO5
fdT2qcBriHSakqecho9Inh7AiV6MCci7ZR1qwICBBoP9cyfOIlsz4sh8OfLdqYFCteMaqCauWkNn
PaKb85IELtig8rQ6XJfWOrbuhwatvSSCV4kgHRQthM6Gz//f8qCV76SqtUEytGaLuU0XVVnMSgoF
TEVaOdPWTAoC3zIOIScG1yNcwJkV1WaVJcCcodW2i+gM/0lRSQ+144MIBr7uVHHigaLFNNMPS5wn
QZTlYKIQJOAQn5bPYZJz4DytC0bOdLNONWtOwx0C4Wr50tWDGXNfDO+ITwkcfWXV+eQpCHEO/MZ7
KKJMR+KAbqOSVjmnHvB7QVPgYX1dZ0NQz17iVqBzuNILiozKZbeOTlLKCeKk0GO5f3+VhbmVsvwW
Uf0+LdnsdOsdjtwQqC4eVz0oj1KKotwcnM7B4dIuvnWmUrUUk+VZ0z0Xts1hMrWlLGJB7vidO+HW
z/C0yrO349/i/ITWYWaT0K7Abc2NFoqSIMKilPgXRr18ZuNCOFkNAl5V4D6ptRwkVbI1OqYvPNEi
07g9ZmM78hYmZE3xzTe5bIrTOoV3ZgrjF1S652r/SLy9UpoKmgV5afTAHdvE/F4pmIQPFl+33hCr
7ztvmgSXS/cq8ET1yWSpcZvFXQrObx7b/f+9gbgvRDeHviv6nOM29dKpB/vCemVgXKlQjqZsnUNy
ORMivJijwwTCBR2HEB/Bf/JmxUgjOZItgYbBml0pS54TKtgq9Rf6mQJuo451nlGGHpQV46HoXZmP
3cMJKxIWSsfKeQep7BRUJlcjxEIscHTCDi9Uxjp2ZAWtoKC7FUwvzWy0ng+HD6Pfpsg2nbgRn64Z
gH6Yi8ZE02r+/jcoTLaCCdydTZ3cJJMzS48fuhli9evzRb7rQ/j+ilGUvJSuIh+YZCQTqAOTCcO7
jr6nw/yx/snING9cLJqDUeGMcxHMVQTYqLVh3FcVvXccFjrV9yZgfOEY6hp89SwFSx9H05NPYte7
QtBX9cwc3Z1MRpZ8WWiatCX9sbOGj3l+26n1gkGXVKFHkJlgHW0r0IlpESd/zPiV+PKw/+Npz07w
1WNQD+GjV7CatKADMGRTWybfaKcNL2iFMVCUtvB2+UO6mkpzbKmt+ZDvPpmhpfZeBH+7eT5u0p1r
2QWoEehXK0BXTZSwbCAeoN1T5/Xj75lze2LBkFD+TJ659LLuY1ffitejHEWuLwdDZqygHNOy2jme
cR5N7+50A42Ndau5r7a25f9hmSInasC/VptNQ6w1IW/qdrZKPjiz54gkcSZjQtciLkzqNf+GIJi5
UqsQnMNGYBChDbHdsmMHbHTm3+PL9OT6SZkssoeg2PdqzLCswOwvfo/Pfs93DuiJPQtdqQ7SUasj
88HfQ0ku7mN372FLaS3P7YEblShOwFGA44sbXfDtuYUTRLw9CSayKDlRG9FE2oRyF1K+uKgvCONP
xify2eabY7TPPUYHDcquNrim1wTtv2L+zwbXoWzw91Xb3Hou8R+amLnSZ9lOx8Ltx396RmSOlZCP
RC7nXC2iN5b4MEaGwZ2Y+wYZcHQhiMmIKKuMlQrgcPU6YlOI9znbUw0nIjp6zycHKABK8Mn0MA1D
Znem0kjIGPslHMvSrsyXX4YITMkT9fMB68CaympEe+M+iIv8l/E0BNPHPbL+nXVasfHPjYxVJ4O6
pIsaI7dcQ8mYyHtVbNIgyFUrvxgUF0bP9Yor7+kxQv68MqKnmjrjeycMPJrryw0VHrAh3uJm4tMy
lb0ZIyVFiH1s+gIu/tJVvBT+P4qLaOrC7dmbeOnuTnk2bZNfSffLskPnXhyjkmpQ/lRS6A5+Ya1K
Z59lcmKgIzGi60GXDf3fGS4FJi+PvDwgaH+0f96dyhnVV/E186b0GXtsEgfpI7jTL0STtArX5Kcn
2wAGICw07MVpLwTrUUq3SGrJaEh9q9V55ipJ+NQbCbp0gRVhXZVZUT70XwQBg0rZgWGcuzK1QEa6
9UaUW2obsGWQFDcjAsMlZxOVpGYGpwIVbdPwGs/M+/K7uuGS43x8cryTbz24vgd/NQOgyp+Xg0Bd
bdvnhLaRjXVJVTL/Tr62Wpyvm/YqJUj2kDbwaNuzmF5A+z7GkPrFpe+cSFsZPFx8HRlkym6mf7BT
5mjlLIjwirD/hKz8+5Y/4NDYrXN6fP42rGX+C9Z05f1l6sF8xH47r7ShC0hZ9c9i5Puy6vWIYaEa
U5RmqvdXz/h0UkH4/YWmbbUub48d0lJSbuz9iiNqobo4vW46UtOnN8emswfmsK64vmGiUYKVhMNY
SxJ94DUxjCNEP4OFPCAaksT9DrKZB01rrid9TTGpnvFcMKQfVj9rNvjlGBoceL+kEq57xU6kCRXv
9c3yT6rBga2yeQ4pJJ6uIRcp2eSN32qUVxqglBT0lPDRu738AxTB8HIFAOont0V4UqiGbPTdFywn
3UHWHhchduKtW9bjNaU+GtQZv59VTVoA8c2mY7fO/a3aSae99w8vGsSdZvn4QYD75+Fbypa61F8/
FUs78GI6hSer+p+w+DW4oUnpEI0qGk2uExDD8gWr4YLY/cEvF0bmWwyurTTCOXJ/U8/ErPQ38DvH
gMJcb/wkcpH0M5JWYOiJCAGOH/KT/aMVaVpdF0buS3TnClqZ4FCCG9L9LkfFVoQNMPZUvdku6jaW
FI1lLt1PMDWSSmu3oLjQrD1ZVoEt410qeZbDEnaZm32AM/meYdd4Pc1o1/9OvpfAw6ptAF/ZM7c/
Sag77c92rrFOUXB9nJPOXbQKVKWOwODdtMSCKPrMPIYPYfjRxMJlAMBonayWl3QmanZrsVxRBPT8
+ER5wnQa71f3UtpvXA7LNNaRfG8USd8NKBxRhxQFps/8N9PyBzpPjKh1XbctJMM+4xA3f0tPttZ9
h2+rlYACDZu5CiWvYbhLly2uV6kuV7jlPpLfniVz+nREC4YPGdrdHb0ifAdxdrgPTMyTj4lVP+sO
FF5pGL9qDbfYTIJ0x3QMrOy3Fqp/kUans4JnjuXjfxxkVUmvmWxJamlgH6XFsoauiuugjGdksJ/P
X5QbJomPf6wWL/t0/ROsOEWptYtSmEd+lnRulJdMcVHkmn9HmNUyA5iOOSCdRVANdLLoxBMhJuZr
S7AJz//rozQ712lLtZAf6zfnZcyYt1e2CxgtJ0NXiOE/SBYwogEkN8yDSsQYCxBN9uthIn39uaMY
klQ9nHfizFsDwrbxLfx8VmJXp6trOsqAIDEjbwcstHx4oyOAlD7KSo2Q4hBYiQtl5CsZ35P6BY+R
1+VBUTE5y7WGodyi0PwrRHzKQVCdBlS8TbnhyiU9rGjxClL4f65eWklJAdWwC9uaVc7ggKljb1JW
iBO9MwSkUvHR9em100j5how4sy80mxQqvv8UINLQdDpgdrlbJysMGnzInVORv588nMGBC+m9d8BO
xN2rCwO8BiQj8QiVh3jwbHEdtJj2ReMuZPljqgFl5OOZ8mzagQRp/uB2Bo33ktNEr1DfrbitDmIa
iC9LjUOMx8o9JtgkO8yUYyJUbiJ9tCl/W9xoauDQqrC5k/FhYArJ+fHeXC6gf81dfPkNXaZKq/+F
dUrL3az/cF05ndGWtPsdlBhavW0EEu0kieRVgs4Jz0vwQvWxn3TVanjX6PPyWRndNR1qh17VI+Av
NvzWEYkVRghb/2fsuPusrGZPlU4eoO2AdexX3uP5wSsSeLRiV9ZjNJWe1EuGVEvUuZrsmxtKLolX
JVpi6fr+u1z3wuoIFzNzgtN6ym0mZ++W7edyUcgo3KqSmy6ZdlSnGuBBGzM9+g+uXBqlHrV34twv
3N3fU+f8SwYQsnocnZel/M+x+xBhSJbXFJlVkEgF09BPeyfCSiv/4JTcu4dCZy1m+LYGTVUrdZZD
KfVsD0+cJw7wAF/zAleqPVeu9OEuMFSIcKueqJO5r+Tg4HYFTQm2wPnDWumQv1cdEZ1LhF3IBX91
wTrgRC1PXgkOqf5dqNp9zzsdrZmAiG7xGE0IuZvacTmmC/uJeidUVnGbQ+u8kPI+KYZPPoHR+vV4
lfWKFD/sn98D7Y8DlvJ5+eDOLD2yN45MMy9JG3ceh7ikUOgSe6xDwYWa+BNsM7QFZrKliU1GnJjf
r7l+YcT2OUoh1VRUWuipVJF9IQB5XUCMYzpYARlzwpmLh7wFoCosjVmn9QKfbhKt49F9sYHh3kRq
mWqFpykMbfYnEhx68D6zwqr2YDRls+kMZzdG9Mgkg9bbfrelGCe03eDsbX1/wL/Wrxm9f3fsYnSI
tW3XVHEhWU+hNuSt1mTbk9n+097PXX3/OB7uTTdDFVtEC2lLl1uZecEGnfeayVdQZ8vSwqCitw/U
wX4LKDE21PCvbLxi0V/VCZTLmCI6BwZ2GK/FZo7Ydgpt+bEDKkUAIY9HDpz8n82rTICUQ9i1A0Tt
8H6/PI4IcZZpPOLibXsajQ/rytkNxMF845n3+cqwXFZsEA/EIGDprgTTShOHwTOHKsFjmAywEmEk
WpnuxP9ZBFSu7CWBumW+cl3snmRaRQjsp54THwzUMXXZUYbO9prangQ/+PQyVKwocY3VHRJC4NbF
MSN0mhfaTV1JNmHzokxBwcispwmDuMhf8A7szKutckeeJepUuDsIpHfDtYX/4XU0Fpy7wRPGrNQf
dwv3PGJ+MhZXLSz+9LIAvixDsY1rUgQAdxJrPk54i1Bxjx/Uh94fwqfeB9qnfxklsi1zU/tAgMc+
g612wdIWmqLnFW9F7vyShoodXZDtgGfzbZOLI3hXk0MUUUDDUsfSZaHQcmH7nutClxqc7dl/gH5+
p/h0mqxYBewLcJzP5WIUbVFkAkLpZwFaU1moagmVuqUkzSOjnfOjNuknoxPrEo815GocrE9PsxOO
Uh34LvggMyF/Pouo3BbLvuGOfxTG1j0Tyx4eSJJnQFuzx4NUfjFzB6oJWOYnygzg8RSdfojEbpKJ
68eunf+dlzUKaQRZ/5/NsexLbiEgixwux6yUNZibsjS/EZnrC2P6zHb+J6aYKBs55FKPPQjEkkmA
YKwQFz3Y2c4h3G6ctRqJ4o74gQzDHWDfaCcMpe32e4pPp65EgS0v+CmgIMezOjFOgtU6GZ4mH0hG
LX/K8F+gtHqhvbaNwzbRHO5JbN9EXfCDzgqY2BzAG53tXRrYjdQqYXxcNDMfqV4bsiSJd9UR++km
BPSAPaooCozWQgTTRerhu9S6Bvt5n6jJp87n5aVQPYV+57caF2xriNM+mey5a8e/hAdsTm7ETepq
B8+MsWiJt6EmULKzhEFhw2OZ7HIK4WMzFGeD13Fv9e+2EnJhqZQddcS+xDnMe60g6Fl4OxTbdRsX
heSYDKggxgdQuMBmejSe8adi4fwx3jYk2UuzodPkoNCaESKiQJuMNWDKfhlSb7P1EOtBei+YsHUh
z6ESv2v8P3gJFP7RhFyiEB4qyTJQ6dynzztxzshJAc4PC3Lf+iSum+7hzd/JzwzaAkQdCIMT68+C
Vwvo5YhLeNxP50fvPFh357pjwlY3LBAO7oLnIIUk9ppbwlvRRbbWf6Ybc5Bin2MU8A8DcAAu8vuu
Rm0wuRhd+eOljH+sBIQvkkee2TQajia8kYtR9ro3ymKahhqGBXUsYYGjfJt8WI4fvAPQolT5M6P+
GOeiRPsiUmv3BTZr+x2uqb+2YOUH9GY0/F8rErV8TTDBBTRCWa7tIsk61+EQZZIM9PG9bAutliBm
kq6Tmrh03DdYoZO0Pp9N4VqSU8LptDX5QFDNMHIgxXgowxHxAR4+5QXx/tw769pytFEXeclkrOQQ
4uFJp7MJqru7ghNpXZbbZ4YF4vLq4GYIVJlvVS3U8TH70kSFuzvPgDSYjI2bjLC2rqxljVCtZb4b
HrWzGagANhFcFA4nlC3RV5oLZ0O2WCum9mFA4qmuBys+cVmsAOHGGgCcdU6MvDjSI8fMDWIWwkfa
/KJ8BvNWjKe2B9aD8RbgKcagWV1SP8laoovkRjjCHzxfDlhgKgG4FY8//FvESBA4J7+k5B4YhuVz
Mmym4r2M3IhpSZRczZeGIkGgEw7Ku4H3LCjjkqifVzFeKCExMjkvGTfKc4tYSeT7wdUVM/ovaAeq
QovWex+c75glEXfQcF/miscav+FIcGNNyB40hyAfszDnF3HoBQjLjN7T3Rlv03URXXaotTEFCQPq
xtSh2rvtZNNkdqWh8RFi/POj8Lbgk803H/EcuiTHimKfJyy349lfpShufu0oPdQLfT6X5UTOP8rA
9kxgO+3JkmlPnQg5QvILcK5zeBybAXFHrktPUHRuMH1KIiiUSF3Jhl0rTqyjC36eWDkcwapCqjI4
0qPSDJrZWU6QXeZ+AZoNwRnsKtwO+JLhKLqQOpjjxwsbURwLviame1EuYP/E9aWEkAdbHDFdtiJr
13dej3bRCTP4JW8QcV9CZ5FPx6KfnCLFjG+t3py3M4YLRAPVZLLiH4cskp9I8aWkBw9y9qNnmYRv
QWTAwZSfEnhkiqDfMF6lHQzq4VVZU4DgFKQCc3hPoPR5wSliwJ+qcmUaRxBdgIngozk4u+Vb99eJ
XjoDzdBdHmK28bQxGKYGaVOoOrA27Rz8GEJvG2gIO7VL/vmJK0iR0c5x1rXBPC0JPAdJIgKpwdgq
SzVjcpRLh3tv1JRYR01Atg39FkpTs5cZPsvr8e0wEesgNz/Nu/bpWiATeO9L5HG606cXc9e/Bykk
VtlixO+TBND4YWQu8+K7DRkFfmYs6danCCM5ipVz8T7WuKJ6KU5/PFLcgvjB6geEv+Yt5NmmO1cD
eYEwF4Eqdfbdu1Yyi1ybGkVR9lFqug4quiSxY1I94nlconqXhwDVCk91CsfKXF49lnEKQYdh1bn0
HT+nO0orPAVOympqLX73TZrI9Ss0gH6aBMmpVXB+JncRSUfpDwq2wrW2qo5HNwHPkKzw4Gzos/iy
1VthIIfDwCi5VZXlzXvhUGEYNFF10GnNbkNP5bybnwLchn6hUgT2e/Yy9pA3SNx/4ybQ0QAK3cxW
g3QJjOyz2R4H1NbH8ZtMRRGqRP159u7YuadnXA0z+IYM8kt9GjIsAZjz29i6JlOmDhIjFWkQ5w5X
7VdYEq0BwaaLTC80x5GeyZoUrxN1oGFs9cZBsVe1u5+lcicfN9JE+7ZuQ6cvx8/DWc8235I+bwwS
yv2QVHBmJwmjzdl2Evm7vZUtQfx+iP1MryqSAOWiojfHUo/vBKPvkfIyx5M7FBZmlyqjJKds2s7C
IhOnviPph5DBD1zSG7qHVIlka/DkXXZJ3PxmWNA9cOu5Mhco8jUWUqbk8owzEcQCBGuhiEu3eWsx
X2F2lawysHIIeQ8mmstEMk2oEXRRsuvlz/wJXzKe8B0vXNWbT9aByNQPqrhaE1vg7rd3BrEjHCGg
DXzTYr+EpDDyN0jlH31sKAi3YkOi8nZzWHMv049LM4YO7KvVnsEqroVe87Kl5NM7aQeZkrVtLSnL
3RmJ2uqjEt+QX+XkNSUUOKh2va9JoHSo7DpkFUfpQzluQPKKu+ZuIRDsPq4rJE6dwcVLg5JJPSZd
haU16CKpeIqbtDprGU96/T4YeCXwVLJcSTdp89oBSmQnZJ2M+pQkP8TI2CqBUD3BOfTPBvPdhQY4
ba5OfeJkqN9ufKaZz743yCLsyDlj/W/8kOfCmnSzabouPo1CvAxMfqyo75D6h+zlC6rf0g5igXzd
B0FzB4c4Ju+dysywNKSrYa18TZP8bdYfIEs9NXO0S3CYx3snzdACwj5F9knl5htE6LiwFJndENam
Z+weGmy215nX1bdFQVt5SqUc2TjWAJd5YoIgebynmwx1XuLW0b0F2hlIG8ZIFxdTfRDq8fddPBAr
JigGoSshYxAQ7R7/zgcluKq8ZnlJv4wwJ9noUUt8/Q4D+icQOzi/cr7g6MbtBBvw6kDeYzep1gE2
D3fwpfOn669GnNx5sYyDZWG6k2ft6EfXYkAQ+McamBll5cjzXoO8RcpxkLwelgjZZt0jx3EyOtX6
Wrjr63qCjbnUOa8mItvKC16UfE1qFRqySE+eS3FEehZjkBWK4+wItPRtCS+sDHW9zs1SKExKsy96
yK1vS7nQeoI7hXLv6ZKlDouJLPgtNPqqFIqEIOsUNn+/dNMz7+yUhhi8mAAtQm21exUf6zUUlFlX
efOUfSuXVA3dWy2PlqchM0jUXcB94R6OKMgVQCClWCfWz+oPPmBwDCVVWN5Qv1CEtwbYJquuaGRj
RIn5BRFc9Hdacc8yqUTEhDPLohscwlwDV+ff/xKH1Briog9/uwGPRWZn4p/s35uAbWPDSceznq7K
ZlZLpkv0iXlBaqsLHmPuVp/4ejkcK160H8R6ySmIVoNycU3X4aySsvn1FDTMNmH1R7+7mACjTSi/
IvnM89tysdXmVp1v6wPcS9M+W2lc2qHfg9j/uNz22/Wk9unH4BQaPHw9dpgxPfldMy1IcBO5xRMy
wulxIUTennC5DGXjV5URMfZ3BA9E5X8Gsf0a5XnCsp5vKbCo/3ubbzQIQgJ0KiFXKbEdWiJwIvls
b0Wq2h2jYqvqQSOrfbVIjPk/1BtKkWylMGGsETzxSRQW4eL99AT2mcw/EuctCUdkE6ISLMCMS/gh
/HfPY6TJ5P43Y/wGK5WuxR+xx921JAJdUHgfT8cBPdxuQedTgYrjlzjxhN7z515MiDt6M7E8zPov
ehxFpZNxMgU58ziw9awsgapZSmNEyqi1wsIqtF8ms8kGB2brFwaF6+meyZyy8/D0eTHzYbuI4cWk
wwN4TQp33kDED11trVXj5vov3neLEquSeBl4JSNNFQPLL4QjCM/74jDDoA/gUJlmQ7JmyhX0D5p4
frbLH4jnVT4zJ2GxBC6M42rlJalE1fHPpNT4QRQpWl7SXOFJTSNajPS9jiTBuYCruWKfK4AFp7p4
5sU3koUzIFSYPvmUuK6IkaiTFR7UczBvDkJSBB3WAnEK6JRHUd4lg/hfdiCNKiM0Yt6J2U9IoY3V
yIq7DmfvzsBoPww6JQL9X/9IGjiPpgk9AJC16P7X1TdC1UYDam9yiGcLpsRCHRCjV6WalAcVe87l
oV5SNLQ/Yf5HwyGdO4RJ4A9CK6Lx0pawuVHN3oE1mkANvsBi8kvPnZJdSuwcIQYJJc5ewpQNwTd4
JaipKqlGMxWpHLzgkCVmwEwZKlDsaAx49+Z1qNuMfmjmlG11Kf8GAOW7hrDkrsLVVxuSbU5avZH9
wHGw4WvHjRfJTb1Fi0XUZ/NXExqSpQI1EnPAWVdxWtcpoeSi6tNzcyWCU1MWk84Vu8uCeXHvAz+3
/KBgCnxb8qRKTR4avu3IOEe+LINixx2om7ovyebAS2bHa0fwUT/GNa+ke1CUkTCvfLrqTRoKzfHu
jObDZ9+ekccYYdZHuLqn7rVsC68Rtf3O4rWofmQVAVdY86mtVHTUB0jzGe3bDypsQa2CoRqk1emB
a7tgB54Ss4QXH9Hs5TKdb9Ty5Y5m56iuy+gZyGEngci7HyPvI+tjMFsGbpR153KItAT+J6jurxaV
+SqlsO5S0WOIll6+UjigjIjMkEF7WZYCLeB0btUcIyFMS4V8mQRLiCNf1KK5HeAXxx63aDVlYQc3
QQJR1x2V4aWUCOoKICxX6hWv1fxXqUBEIwasMy7z414kOqJrbWYVssgfh+9BviSPtCwdPR1KvS+V
IA/p7znPIGvPK8m1O8kbKMRDTt8jBoCJv6YIPfZ7p2BokQKj1kRFQw8F0oU9Mk70v8n/4/dm5ZyS
B3wQHfuafaGJZDPK/GY+8QAcK7TTpHZZ3uMmo0+QaFmi9pQPUT1me2hud89DDbYjU3J+PSJGWw/L
4aTzGwNSvNZYtbmL+ab7ynky+4rPtE0EyRH5ohpVGglk5yImKkD9HuF1wlnT6TJ5CviPLQrLOn0r
X8IE6+PQvRCKu8iNOQMd+8J+ncidDdedfjjmw/EamjwMV/Dd0hTRgs62jNMJBd2JoDf6RDYnbRIA
tURDatxSj8P2XK2OOgNaEHUtpxmL2o5Mvs9CbwLdwBwEIpde30pCGdLX/XljwKofeAE27H4kXdj5
PHjLq76zWv+r3bSwS2+2xsA5pBf3wZJQZAHkX2UGBMJVda7Z8WrdzGP2435x6w4lk7u2/Z3J8Shq
iSatbInEiFGAKkp6SMAxOSmRy8AR+jiJo2iJlEfC11sX8i0tUeO3Ky6Og+VFot/jzrqkM7JwhwNn
n3/jG7ETy3vFuzhdmg21jmaKonwzI+pemMov5FAmEFsc435fZBX0ZM0USMwYiQNyPNq79WiKwTO9
+Pi5n4rmoFhg2RjgmW5Oiq+AZ7MW/u/SIzkc+PXawdzywdTEunAjBwrmg9MwA5FjVTSDceagTOwY
05qf2CC4k4aDj82JpQk6khT2qjPMV5UO9iQIfQ+xikHx0YMiALCiXbtIX80MzG2KeUUYAlUWhNXL
OrKHaFOWYHrRqiVIK6n6bT78SmNjK29HkPwbAfFBF9qC4VDX+HRSZjJwv4Sq1XCjlRTWReTbvJJx
2zo2Tf901iEj0prwN6jVruR8nQ4kmLdyZ2k67XUIVtG+DieOgXbB/O4RtjOjW2thRjLRs8ICJhqt
ZJG6N6VHkbr0jeWor5UVIB3fyblAcJl6QrDxhk5/lGTDyjiWXB1dsWyWmXXRs0JTgcsZrD8mYwDU
bScuYbq3Gn7UUifl7PKAt8iAOwo2SYQPLoNLze+i+28obF0dV5BOkLXSmiHE9HCLNFfxOjPa2VLu
aSO5iUJha72k4V0OBoLZv53+RfptXZ7m9ndVb7JLzxPG2PiDvkbkjJCaYmJLY3xCE58fjJz8Ixyh
AA15dyfMIWPgN3O7H37FrgqkVazkCjrSFZJso2MJ4z5Z3PTZzVw17FsYBizQpX8KDsUSmVzCxvrW
7PDXT0h375hp2oUssoX2DD07weN7WHZx7STdO0xXQpgKrqCMxwIxTe0kVuVy2u0BF9I+NwnPiSqA
sHxPRIMj/E9fohC2TwgM3RZ9wVo9LTX1sxRP5jjD/Xf93VJZk0gLacSjHLBx9yXUpa00HaW9+ypz
pYLgEiQsqlE8PDpjgxeUNvzdph7hwUv87J/l8rtBptBv3RKeNbUDZFmLm3jxsmSJE47DU+1sIMlT
XtsKX+eBEAnfQJxbzpOKspYtVGpd7Ce0/70nJWdV91nrpp4Pt92WGL6MB1HSyUZb4drrGMqppoc9
eJw/ythzorrVavvPRfX5eoOcns2jLs9hbvTF+AGom0H83GhVcCbfRXZz23lbfJKTCYtCwywRZhjf
7NKGrIJBmO9nqLZaSbzV3oEY5CA+8BMLwTrXnt6YBrugPg43F+/fFMfSP97Rr9+nzI4IbVZuYV2C
psamHt0lRLEm7Y1l9MlS5i3doMBQAHxUZW+t/Qp5GUzcCVcjYlQF+29a0v969m39S82wWiNoAN/t
mYDc8fYbsX3uqRmz5zDRiG9gM2SSLmB1zAX0rgvJbn9s9EPibClCvg2Y0zkfQWxx4rdxKqMqBptm
5bO77qbA0L99y7VIVQT30GyiPsESpLisSj3sUqI3roiTsiAO39sTqLtFzmgtRh8h36tPn+o0PLCO
HoOaByEmyOnkQ+VKbBQyExArOZLSyJk6LiGqxsPnSG2wof/pVQOVv+loLwGYOb5SvpUqstrZYBxk
CuFCwVKL/3zSgU5YzvJZC6Oj2O+kIyogHJ1kfZK5MAh5Zrez98d1PLZaYZSVJ5dtGCeZ4a2jxg0L
ZnIUw6TqVGSPuIXVwp5pOnlMb39ShL/wzdQDoBseZtGNi1HOdueDBcr2bgEv1hXB+zVSKWiTh6Ob
Qfojq4nMsaBOgaotWDZgu5ERTnuSG2OVbtqJxQQ9qMsYcq9PzXwPt+pBAh3g5D8UXX6Yazncuoj7
SIsw4glm4tCG9CREE93TEs8UgEunXmD5qBS+WswIiPdbhsdXmh5nzR7GlMsz0fLbSL7oG9kT7yle
IVi5O4LLdrDxBsPG19ZfaNKCZOSvxcQJ/tKxAc6hI5eCu3nBU/N3PCTOQPAMqKvztbITtFBBZ3xV
VpQuva1d8uMHnxfecSCtVXNaOfChQa8sTsik5934sB3QhRscPG08NiVAnctGoa3IiTCKBPaUXFC4
UtsBbk2c8FNgIbaJw3mU27fFJ8G1+wJDlx1dVXAgKUAGfB+CXr5fsuk6njkREHWiK71yFIE2t6MT
AWxTYifIrtRw1INc4cUmUYKcQg5huNlPZ7X+cCY7ZsOa/uI+h+pa5E6nXDmV0/d2zXoTUQSUzkiF
Itf62yDKUs72KCjSqR27Qcwo1hfMmC2ivz+NwrwTNGjwVQWzPv1WsBgxw3Onxvc6wRDKjMA7kZEu
ifQtz9FiEdi0S/vhkV16j9OroK9A/Ue6z5swr5Ldp4ddYYC2hjSFOrSzoiprxRh4dl6hYcEchuAP
ohOF6sUthcIlWmcal7aak+ehQyqCcniNNPKGcKQtl8S8XaZxxDiXY23XKZSejutv+k4pu1wlQe37
LwEEsdTT1tLnegd8q+cBXk9cOw52YHgJof49zi9cBLEdXZEseisP+L5na+jO6JS2uGbNBJmfXfIJ
j+FA0muETwodjlRMJ14pcqwpbXGH3MAb52PcjTC1ngHkvgEDdQilCCzrRHdyrCTecxVgkPn+huh8
m9SnpEDShwxmDgq8NBiE2ylOXVvdtGZiErmVoDJ51qy6eZW+pvqPjzV5+idQHCzv1p4XFcQ3uVaT
sHV52Caz0oxyqbBHUo+ADRovH4Ci2JCFooV50nHhMr9Q5iJoLS3Cz8W6QeHQ+kzBBjngbeoeK3F9
oNPxOjqWHWBnm+MMt+449jVKIksC7ac38H4LTuugXGTKmrJIl67XCWp7fGYIWlZaYk0FPaMZflLB
bsp/SHAGo/YFVvOEiNm2McXWdqm9kBtmjNgVY5rK5s6zvkRN3Pge3kbCytfyencijV3QAJl/z0Vp
vGSSYK2cBOBKq+wklx4gc6gFKd/hLeoJcIq6RGY7SXisXEB8gWpy2GRDyyLCPl/8bSzX9H1IDLSy
Tk3Vklo/Q1FLJB2l0Lz9QgK1NKAjIy2e8EpNMIAo62nRWniWKz2jXzu8vfDgv1fQWUKz9puFlj0+
aJ/+sH0UraQgO4dNg8/Dwcw68ECu4gHHIJlVEolZDj3pARb3LduF3EbhwZ7iEq0p11eEROIBQQFe
bBRHsuNfmYOEmuyO2X3AZ5IGcv3L+1wg0zzMGpKifxh2IwB0d4l/iRGpGBYZKrZlXxPXuupiw+py
h9vDpQKvilNGqlfo1cj+5cEZ+2e1jAl/iwsGYNLwX37tXfLrUOBJefhIYTOr+ozv4Y1S1j+NhA4A
lfgWGveLu9eW/qy6/oKB5bMy37BLzFGQBQAkO2bIncKg120yjoEHGQIZVZZALMW6lSKJpxr4V5+M
kLkKUS0iTK0T8+GTHfF6fFpB4uusoP5tHacbjkgVt5VW9aeRmn3Zun/uOEVamMnt0UtOE8SO5+Ak
jMuFj9qy4/accQfAa+wBB3rV2rskKchycNmIeOqdobEkgFG4F+2jq1TOBB9HmG9PLUEepUs0ebbg
3zu5x4ojYFFy3P+AAOntnI4z8fsGvOAy6I7k2Mt5DmFxDofEt1fX1Oj/g60ow1smZn2RU+h4fsEU
tfVXzcI3vfKyf74CPZxDbFlJTIshnFEolYRZgNxRkJNWykhCI3HCtm/HA+S/0xeJTcSgLNZBmNi4
DLh55u8nHqeCCQu+QMy/xArVPz+52VzXxidujgW8D84GViv7at93Gn5fp6bz2MIGQz+zO5Z1xgfR
pUTjsP/MgAv8XQylOzqLrn54yU8C2LrLsHoyEuZMLfIcUPPCpYD2hop++QpzmeJknHhNOUsuqjy1
j+U2UYYLnK0wEbg6Utq5zff79Lb2dQEcxhzg5/KjvnJkAl8wblGKSxIZJJ2GKDxYKrrjHM1zfxBW
R//+teTbHwjuUd48N0GiOzMjN+d7mvwB7+J1fj6wHCOKfG5tx+ewDi7aLZrWVFPqS10YazaMiOse
gQK22UKXEdm2DlpOdyj5IgNaQeeeS5TPEg9D7sxOkrLt8ZDm5T2OlAVMMWtcCOrclokRaNlaTyN9
cd+EChOQ7l9IRi8feqUcObxbmCWBPmKukm0/wFuU1jUHtTw4yIW6UzhvSptUkw5jACACkuGIB2o3
kk2e040PMGy0yxeNVj98EaeTGFE2cQN32cNMq/BdKiYuwH4e9jQXoBKYZv/sj6F0aA3JOn+9OREJ
5ziKXR1tRwO1myQNIaGgRWEBJ8NRkTQdo7EMDTWEmCL/roBO6tbvt0yIH2/udUnMJmxc6uJvazQF
FTxfrRwlpL/nFP7jxOuyfKnDR8Tni6x1Lf0ZwqaHimtvUl3BNl8Zzr8YX2ANVhS71CCotNEVeKbF
MPugRb3Aba4hoyGHvMffg0DB3+7my23+QT7MMcDiv7cR5P9qM1QltubW0sblH2pTab0SeKPba7bL
zrRm1C6Ue/F9/SmyAinhMqOScc6GhFvUy6wB3UJ5mCAGYWuK7FYfDKa5xzVS54rl7pvoja2cHUaw
VRdksO2nkC4+Dy51LXo/x47+TVik7ktbCMsqRI6DxoptuWTGpYgEsT1fZ9QEvh9HpRNK+838x6lZ
PbJAO0Ih/JxatqjTldNJH1buSFf4GANwmxNxJ2DaoldbaNwPXurA5fMhy6UzPoQ7ZK+TZVInv+L8
yR//ARLF4YZRZMoE6FU7ItEd+zI/AYeUDr4zxU7V8ENARnrc3VujFywLe6GVapsgu3Q5pydO0EmT
fI9CPISTCEsXqYZpCa97w3Toxjw5Nc/7dlVQgccQBBfYcW/+Pp9eeNLvv1ymT6UtoZH/4M4TbKRU
5mFJPmyhOWIXCcReQJxp7PAC5zGCaSRbeBCrfHC3ReuROoTqNOU+XG0npfA4+Cl6/hcSWaj1LjNB
BHfh98k9njDCMT85hHo+H2nGyqLlHRSIZe3mDeH3OXxg5IbE4kroA9NftDzu3n93CqJ/G6se72aZ
J4mtldsRxl6GrWo5oyHkDDP9qpXPdXpLunSy1GeZvAWZRYIcyzx5RDnwXEltcMvfkpsepJQdthrm
7nQLS4UXKJRtxVf8C0Fj/JRLUvd8dH6qWHyB2TFZAuUWI3Zbr0VHFliGWBFshCs2vVFugnX0kUfx
2XkbLql7QHUTRmrPISqXcqvk2YikuZ6MIsnK5VwUBs36mq7mxpkOQuocSYFxuo433I1auoeY7fz5
5ffEzoHnG+zOnpZtrRrKuqWONbN4R24NcZt8laQ+jgalhHnL9PQnwE3KeFO5PgOUTgo3zgGUU+HZ
+Bs0VKZd1OAG4gO5W0GtzdSv8sbm+OdPw+wvNEChg4XyrVdsFyU1qfR2bmvvNjCxoeoaHLnut8hI
DnalcF28rI+ktAvjojMGDQNT7qNd6Y1US09o4ztz4hNa2slGYi/2TgeA8bHZwM27XNpvyg+DkR8f
HccFAry62E/KE5ATfMHMnhJuNvkWXveAO3QQZ94ncUSu3NyPzmrKvhkpcgPRY8G7bUMMjiOdK9DD
3DKszSQS3Ciarjl74+hTnrm3bpV6mlz29BB2RqTejpKeijVMKEJR9PCezE0OV3XzYIE6DhmDEFM9
llDID/8Hj9oZDtb+tzgaGZi1YcXmC1dsuBYuTkdK8T74+cdUtiYESbiI/GM4FGeXDppRnBlvl0fJ
1LH7teqmh74RXfC8kLcR/isONzytqgYibku8kSFe+YW/6ag6xYnmMiGbqvYAXFCnfisLH66ivx5a
6PofYUATUCKX1ubkmDfqMRdI/Tsu/AdQb8Zot+Ygxxy4iRv8S/rxLK4VRk/1zsqk21HJ0eTfuhkm
qHGFRUASE89nblZ6mJPCgTW1pPwXYI4s8CerCxpdlyCzkklcwb9N+9gSbuZA9y3jB63xLATvbjR/
0D1dJxpTZ68+BT8v5tqPkXR8cc6+jOn9g+kRlm16zpbrSkctf2Uj5yHFms+m5PhyWXVTVl2FPDS6
gdx4TnRRwJeDWlbdmdX8rhShKBDuoBNXT56J1lUW12eBamcf3cfgEit9gnYx/BIqRp0Dv8a4IOvs
lhEp/rywpD33t0JMCxmJaShtyo+/35Bgnm9pHyRMqpgOYt3iC6eerFq/SFrniLADpxPGZ2NUIcYg
dkC19KQX+B6YLJbl7sdERUWGqRYt1ZLUU9W2TVOLJOWGyNfXpCQV5g82A11nTxHzyULU3dbmk9T3
GV6mFzicq1+Vas/bU0NVCAwLJpkza+cQ/AMO/sR1A6zocFbKezPtLnS+O2h0bSpPoPpA38OLSyh4
XQfiQZm/CygAQSm8R8FxIoLm0r31Ss05tOgyYCoQHsH98KoV3ijheX9SyIhubbH6v47/y5v2r2LC
FVk+LGEXxMzAmL6ySlmK/hcmgA08voQeBVr1AQYE+wWSpDZSoooSIegCujmzKhNH6uV0XqnAfKa1
K1+ulgX3p2xVtaSqdzjTojFiXkptNH/t7qqzUCwgWGjy9zTm08ViLUxIZ0wbsk1BXjrvtZRcAHWy
ak/Qlss+MpKLIQJlLQywlHquZw6iti0t68L78ZEmxXMNAsndu4NvigNSp/3y3mS263M+GxJ8zwZY
4CzxMansiyssD50t1GzCLowXOPna2IRD+c9CSdP08or6byIkLoVkhEOJ4eYZ2CRDTd01SQ9+Sjyh
2tZFVRXiO0cBph4LqG8WUDB+Tj/bjxq11E8h0Y28aQysBvPcSJykS430XVIiUwlS+VI2pPIfDfU+
faCLCG2sR+qXvsZpSKOC3dJhhWVvs0qUkr5j2t7e0vlVLjEhaLvyqTWwngBHKdrLwFHDkf5Djbiw
NmZ+BsKdZG41y4vgeOBiZ/W93sN+dxsSmqcdrvepviVNDfcxmXDDz3gXJ2EOn9Oni0Y9wKYhF8Qi
b79VUsNNlsgk7OUQhiKG5N/tvJ4y+ILb0KxCJM1NJRfKFjOC+R12Eabi92ybMZ2fhtcLgFAs01hL
u3wf9CxaCAPxVtZR9fOu36Z1a2+xYRXwqnhVoMHjItZy4mTVkHgNucrXyvxC1WWGNK+bWvI9ZGt5
OVEosu3Z4dAmggqQeLyI6fyCA0MPkKHauYmarNa6R9d6stCBqabG+K48JGNNyaazGKjdDYwQGzvC
jK0AqRySlx1Auq0b1ZeE05uplSi6oVJBRMhKnTC6eWrIORV8xJdkriGDPmeLQ0/U4C8q+SavV8yg
8XQM5mFHBM+MjSO7Vin1VXBAYabo03PnYxmBq/jA8O7UUIe01gx0i1vUkCEpEex7IZZFP6mGUPOJ
FafELw8d/BSpmz3zZhCX5MjCNfIdQyrHC4bOGhJrWjUR1N7ZOmVRZje2+gzo09j5CaWQmBkmxV2O
bvLQg6pBdKbX9vmh3mM5Kxfm3mDadmd2aSSwPbV3Ysx4i+5V53aik3bCsa/35yrUOJdfQUB2Ygeb
A2goCmfxIFhUnw4SDlzMcMvoolea0SAfaarQhYdpEHjO90LCyPC1toeNsOzYcyyYcX27mzroywOj
r35h5TZ17+iRQ9dWiFi3uMMNSFLLDKiZxQtCqsJKq5KJCA6OUyENe7emrsa4nwZVwU3b0mcvCnJj
eGGglAPAlrRuR2TAta5V1QbM3tuWkXXdG7sPI7jJR9rXbfuVYU6ru0BAKoEOSsCWhglmYWaagywo
fjStTDE1FpfZWxOneg9IDyFCu0M4N1ue98md0AConGWW6mplL+Vs3+WWkltztrLkDuIJU86YaLgj
xBUX0uT6fosj+xNhu53w/hJsUSN/nfpCGaBDp/PMNsB6+/m4eah53S0copBJPvTgV5CeciWpvujH
0Y9s+hvKPJ7if9s9hQ05qshWOxfl7ijhmZlvvGkwKL5IWy97HL6IT81UWrjdbUIna2tjm+q5Ll5l
3g5GgR84irro5kxvGr1u1DVHeDoSGUA7usWskhq3xTN/thh5tG/Y2aszOLhblKZ94iknY+kPbXxL
Tc+U5dSsONfM4EA2e0IB5Fed0ofrjkrzRQ0ecJdM2snheIoMjsAO5tN+b3wMdFVJdVtcPivBEgpg
vUjWON7O/cNOhkdOid/Z0o0kCn5sKgDXbctCEQLaxMhljwddGs7qYvpjyiRQXQkZ+sQq/b8UyjcR
dXmQtOY9xMu/mS2ZK83iMOgazCzApy7eLsYXw6Btzl0p2l3ED0Ba0gzx4iRLNOTQPM5lki2c4M8e
wt9f3Dotz4VNCM2k6Iq5nTh43ZmMGWV2I1Taw3MxNJFcKhplQ9bPPGshFo1WS+uixzlL8vJG2Wtc
XG+4/S2f6hHqPbdGp69U5Xz1Gs0X/V9YRzuCcYP4l9z3taKc7Of66vKF+N4KjTE/rKdOtS1i/7y2
Yed8UDh5kyGajjlbL992AfTM2E+5PPX+Lrw3an1RM38Vs21gOB60NeBeuyg6U6J5hI2bTegjNYFQ
wxUUCe2npjSr3utUISq/t1SWMIyNOSEO/fySJKb+0jfTto1dpNeCt/Nl/fB6DhEKj5OWJWsHj6Yg
PhDPmJnPs9O/hPtfBQ+k5QAqGoRVHvdcQp7ywwd3eyRJ9BR3tBfUE++L1MdUAOD5LhSoQveHzmAz
c2R9WM1F5BFyukTulmhANyeCFYKfFv856xtQahVVYJKbG14DMg/prVi2GFt+8VI6rKDsH10YKUTw
bng1uMqSMp9SK1brZFGKWZtUZzfEGRdvgUyFJ99X56TFItb5TtBJN8b9eroEUrgw7Zguh38U8FVf
OdTHVWTnQJRDP6hdw1rVW0bQnmFlCge/va/MYqEnzLIHbh4yFIQCQNPPIV5B8l108wYPbzsUWESs
6XJtdxoPN1C3dupHAYG++1jcHTk6OfBfXioVP50VbxjZ9vfpK6HeOriiM2Ove04tNjfbvmm8LZKU
zweD//JiPObG9o35VQeYfWeP/oc37FipYMONWDBYcxDtAu8Q2DRtAEsTyTpFGHabFrfGcNlDyOZ7
NmB78D3DnZIfCnJ+d081wUjp3S4O1eOZjnXrYxKBxN495k2wUD5e6qhTNwSXj+igCmTrVQriewTm
AV2CcXWghujE2AnQ8f5N9XrQDSnHnZ+z9x09VRKEQaRRxUpLtXGlm8/Oi3Pg9uvke1TPjdBIFw7I
hr5fckIVWb5gruq/k8cr4rSUmOUVh7/7ltwSL0UWZ1vzq7FNselAJrsIQsE6nVailQ07om1lGW1M
W2vwCJsspKL0EzqZLfBbFJXvHEgzlWhF2Z6BylorOzn6UbdwnKY6e9EM3WPH0IyuLraXbC1emTrY
XNm6sJQXEUwoHZOdahQqOKag0Mieofr5Q6uTJ8vFNCd66jTTD1L+aHvcrC/ShE/DaYH12IUeuxYg
tWln4rPSp9L/xbUx9j95ectJQG0L16IHkqGoFIuJ7iLbApNvT4TwD8FPKNlIG42fot5wr2u0B1Xp
qxEXtiS0oHV9hZdYzC31kv7RQa0/RQcYfFlUtTYLl3auDQqtk4zgdnotMmvUy68oeXEC/Qa8xTrI
7Ul85YMrtWOIwOR0+HNytEG4gMINZbqmbjLJ4ohnxE4DhNCc71V9yhojoyGwNxv4piKQBClrivjG
HB2y067yc7WF8JQZL9kDWCrUod347yWzkZymXeUtTjm8E8urD/+w5laPJ7A29DztjsC4gY3wIaLN
9tRH88eY4y7pfQTdCjoeUDfIODHEwGzJjHDk6z48xZbL4td6+TVybez31gjDGJ+ueVmZCWFg6LuT
oOam6B4gJhHjGyiKI+AZIKRTpadPeApRfj5FeUCOo4mCAtaW6VqQMcKSgQoCocSA2G7QjOTwc9/n
mMyJpWlSXS7jpFLho1qng4a9e2yh/yBp0wGjTFec3dAldQcRVqOmCtTVkUVhsqQKTbt2FfQKVT9o
ZviArWRUrT0l3OKMUwjDWq2H43qFdEqf7+cKh3Gbth3CNlGS5kNycJj7GDdMfmG21CRGSu0+iZuU
kIaO3GI27timKJFlNoghJXwYxl8yyjP8hwkDIEFukAy5BWYqODOqE8ex6ey/xGN/VzViRM6IgOLU
pvaAPfpCrFHugcA+EddclN9dneLffhoHgAPgFnGvS1wK9IWph50pWAFtCWUlUBq8Ws6PHrMheVVi
qRLkax9Ngkt3m1ClE0K5PDXBGlmasdO1zkL9j/KWFgsw3AL0zxEwDj8fnMH/QHc4s9AtlSzlZfmk
mOsSkjM98bavlhe3hE1J47qQIpQUaGHVsf0yZxe/PbJZNhdpdoJKx8BWsJCusLD6qpxCTNb2oiBv
7HfaWIzgVzgeDVXA4ccmFADwBnzzvGWHPXQN2AvcKLuEEXKdSRXVNnFS1M8M+l0NV/UnWZqoTTCA
VjnsyGUipFolMAghHz2gO3cdL2bjurwbvzrOsFHZZwWx0s/S7esKHypITaJwC65ATiB05jgeaimU
TP9i+ZGC9eRn1bDt9QlvjYs5HXTEa+8kOoQM7WnVm0eJ/gBJ0GpP+CWJHkTaw4yFVddNuQA2stSw
WJhiE8Vz12fhzVfaOr/Gtqxr57P9vbcIkvPp1n6eJ/3Kih4Uv1MWXU/RDcn5dmdjjjmJVU9xlxL5
HloDleHP2RZYrpw30TF6tCl4PTj5RMyRQqcM/vrb762a67ajTWXfFuuzltEJbfxuNgZ5FngXy1MU
FihzlJjVZI1MpVW7Umgm0BnEZMKCVartQX/PTNj6uARfllpNdPuyhnRJe9qHJY/BpHw9J0h/Exqt
MVwLHxsOeF/lCL698bI2Wbd45eqmhfJJGgZwxzHgBJOJHNFuAyX65G/tPpdtisBmwNgxOieXkez9
NAh2Ev1c35fn0Cf3FjUmxf+fYuYwuWoz0QkukecmbM+6qJQ0iR+m07YfvTIEWPnedHDgiGsCE+oy
fryf5QKcHbzjd6rcsMSI4/wQqP0e9RCpHiyADwJxVSQjaJxrV2pBZCmbmOr1+NlVhetVa8bsedv2
3fC1wibHxTvqk1FA4TrWuHJaczkzCicpaYYu/SYsi8Y4+ep7cVbvpLs1qzJGbSW+6jU5RvzWiVep
WQ5ueylAMO8hCT5harWTemWtmQO1k2cto9A7fhth6BA5rbOKzwJYIC3iVazbcowqS1/mKLaO0MRI
UU3KRijpy6xdk6mkLmqWrgR4qiloCxDbRHIU3DnFKEYbtkwD8r6EzdBp++t1g0KTm3bGB/doUXHW
74HOg56xlXiYXEKwXo9BBKUd0UxvIGa50hhqay1wf48dJrobto9kCTaYEJrwb0XOinrUQ7afsY6t
edrL7qyT0nRdxo59ndQ7As7srhIZwoc9KKFp9fjMVP0uGMdMK+CjtR5kh+C/LZWVrnEzwPZGBIRP
tIsHYMgilckC/eLG9J/H8UjLu/G2WYuQAB4Jt+U3FvFWHuEBBsjX1iXpBsM7WM2QpO9gDnxDlAvA
E7wQ1nJm6vYMeLoEDUftcYn22l+nia5b6Nxz5y0tyWRO7I8EJQZSqQi58Mt9KGP/TBevHzjgZgJ4
YrtKpd5AdORUS3gOsDv2fXHB8PUxvDm8afntXDt8GbLAAybZshL1rS9kmNOcYpgb7GfjkfkP7uU2
+k7C3MmZpj3vudW3GuALapiNEh/WiPwbcrLYn+/WYHcnpL6F6ptHL/IwdAWJ2jnDwv0ve4ivcLMF
zZM9h+MERDgh0LMkaP5qg4l7j2VGcX/Uxu8q1Inywejs2j7O3IBQusae1+oP2IFgsDI9+dsrXiAD
hlFtoiwfmQ03zNvVjFsOu8nd9ioGtr+BcQiX4fD8CAXoKrrRn766UKewceDJnRGcGOqpQf6JyzJ0
HiVDuxbmW39yk9gRYyHewcFvng5/KTURh1tm4wXNRQiiGw/QH/NRULoT8CVbnb1D4XV0LvKqgKkg
2oJMJ5EFq1kvU3SSCMeotZgwX3M6VZBpthhGia2IoMOH99Kx/RQNAMJAyBUyICmG6RAWCxu4/lew
k/6Blc8uzBwssNauIEP96DmUE/0INBagQla7sVCalf6c5Q/F/Fin4H+Pp3SRb52pmNwzjkEBeLBB
PD1aF6gTrcByhHe3N6GRJ+zPC7iODDfeanvF6ifw56EGQtbRQLhIdsT9gVvAquLBrZROhKwlhBQy
IOBV/lJNjEC5C7GWpwYPfSRnUBdPSPRCq1XraKBfySh9saNxu2OKr1foD1zrrlxNMKEu5hpQKCX0
q6Mi7LSce0CuCGTGlaQAK0IAk4d6WMufRJjPv4fHtP/qgRrrEUVTTfxs+nU4L6kYMjN/xkOJjCM1
O/1v4PTP3xuWG9kTJkLAyQvnHxHVp8mSgU6dTlrZe0hTEne2LpRTrT2qAhkXD4a8e+zexdejaMmi
3YQs9TKAZAH4DLz9KRtTd/+BB7wKLSFm9gQbXvVLy2lwOnztJSLR2raW1c5ga4WKTm1LHXyA+nqp
53Ndg0Q/0E+XqKPPyatMfTqlvIbbU3BWaFnbkeGSdl6izwZ8UQ34sT3j0LMsC/WzONVx5v2s7x03
5CR2N6a+C1PFmkZ6Z0u3vh3l444HgJWkNosnyI86ol39MTBgXxFK1lZqj0cRp/D1vab1SwyI6sDU
gvnbthqAJQZaLmxLK2WXe+ysWO/w+VbLUUCV+E00XltFC2CrIgAbWudLbijTnVy441y8BfhVd7gQ
2GXGFzQ6akJNUDYpZdlT3yKr0PVMC2UH6KoUhtG/S8xlw3vFXZmuNCbpgpolB7zsjy+AW2up5HcP
y+fJe5n/amFeR3ecOUJj5DI/9u1sRAjUslYWxhhD60l1x8m3JIfHh+LlRv2QHrXtC3zU77cJyi1D
i+By9z5avgdiWj7mIPfn2QpVkGlNFpEnSuXvkWFsT7mxdmP0PWIbP6yvPknYRfC1becR5CPaxNiV
myvx+ugQ2Shkh1rKDmXXnQtK1gfD0oUTFmX8hh74d5HUsEB4R5sl7TVqC4TMs/OAWxsxmgoc8hGE
s/x4gIUAEh4lCLuRexA0FfJ+MS7VqgHP6Bi1aajn0S6r5Nbe0BqyDhbEB6ARe4zwQjM4N/WI56sC
rLaWpHl9TIaoI/sU30UVjNWLMqn5qnH4eNj66IEa00Qt4QWJKqRNFxjpZGzdOOp0kZKk72O2FcaY
SnI2mnRQ9qEgU9SQ499hQYXqe+yqu0dxZTL8bxCCfxMXGHZrqqmaWks8K28sB5Ht2/5tgUDk9WDP
E62xhamiCkuUq0tAbZxn60h13ubNmEU8uKuOzfdez52WmDV+n6sCVzYkiVV4nFSg8NASycgc70qx
qdmclUDonKFo1zmi7QBE8I75r79VVtgK+MyUjl8988JqNy+6JDYu1lciob4wlnjyVw4kMfroAQdn
m0+6EgKPIKGQ0DWArIXRlH7PUrfrq8L82dF6UMaamlqwUaIP3G8R0EVR7RQgfnfTP2oZp5OYeQ+F
auGU4nZzpdKG+YY+PXdu7Qb78lkjmg9TEENHPXoNbda84KPRIpEdryJFEd7qWUwZr7puCIyjLerC
KGhJD6q9Pp77Cwy7DyUdASzvryn+2MIgtNofZbdB1p+3xIXUUeHdnSb8OH3fs1iteVIyvZX+rKeY
VceEjgy5YKSAdAGF7svWm1dCA3A/xNsq/tLiHIYU3cqUevXabuyei5b4Ter5iWWtTWaXQtZt7fLy
/tfMUTEtRHRM1sGJ+MiiPZO52wcfqEWCODzhHcQne80s+VJS9/DKMGjd46QoL9uHuDVGPnPBAjW0
EQPUQ/Me3hCdBdETICIQxmI02P+6PAv19uB/MAjFr8bSzBBwVv4928iPfK48u5XMBMXEsrUlCFSI
My9IG7ZDuMUuew3kYEdo5rXfF+Tv60LnqsJ2iFj35Ce1OsFHptTnuyUnBX25ceNRlFzlJMHCBdcu
PknITGRqVSV8tCAJ8g6NJwAT29BzPQ1Lt77GFo+AuGfvPYEtJvV9jDJtpKFmLeVIZzByQzlhwe5b
KeOrkY1nfPbJ5w4WFukI8r0/Cvjl0ZkchutRrwwHY/BTs+G6yMgrgeo1O7KncQgr92SqN6k5XoLY
usNN4252fKfcTaowDhwkbH7ysmjbKXGi5Npli0T48zg2fp+9+rK5RbRc823w0JYvJWusPyP7k4+t
MMyfpmFFkVkU9SyvoyFBHUYxFKtQbTf6NQhVC/lohmKg2W3aZt/tIuV8dnWljiA5Y7OWKCc7HSoY
hhO/GWaiAZaIwkJ3pbwQohZJZXW37/qRRZy3/n03g+sVxt9/f3Hl0xELCX3frQasbz7lkBpGopr0
CMlYFO0NBIObS1PxRc1QuoGX8+0wCFAwtuKUZhS5KEsZUs9dBd2MATgJGMJteWbL+e0UG/CwbMCr
w/AJdhmDS5ygyahTpoZ1g8vRSr3RAAaJebhr2aU0sByNT+I8l4zZpO2zaHuYvNUYbWbcwDYi665D
S3wPv5oAF/61Uf0SdE9BJr/Y0d/IDplD5aO0PPMtlgzBbit9NzsFzVrozB5II/NHUnhRIltnGN2/
O78gJZJ+3rP4Q4YnSqP9HHRUF7gLIL4gsd+rzQSyZ/vFsQgvPAYNyPQsxs2c2NcbJVOpd0zd2ehA
KjDrWzbOS7yB0dZFtivXeRRS/3Ukk0Kp335M28LZRnO7GtBtJ9I3yof9DLDbB69RArVXy0mFvf8q
SI7DNciGSgpAIXU9SPatJILU5LLVSYTv5K+sBZ0WCe1MWr8EA2lJkOnfCdsUfeFerco33ji9JbhY
ad9x6IehsDRn6ovw0b/NoqGuSJ9sYgINXHstlCp/YSgOY4OI/SeaRSWCffpLbdt7ppSIrsSoygsl
omj1kF0wYUL6/0aIdtYOnMfbjLKWtMQiAIRAlrw71GniyIBNnLhx7N58pB8FLWSw9yRNtaQQbJWG
dRsFWll4Uc4JMigTYUfgI947uwHa5p9zLAYcl8vJ/WyLdbiNG3S6dlFr2BwYFPq5Fs4gEZVD4Eew
F9Bla8z+tONYP70bfx2tW10NOZilwv/NGqkQluZmjmpeZeBnvYJb0jFbxpbxIoiElGlFWxThM1cd
LLyjhGAF9AkvhwhhIaVHnNq3yGlH25Q2pNC76nCwQt8cqbFp06jSbgNE3k75vXric6EZf4n1utT7
eYbUv+BZeLL7MT1afraNOHduU3CgPlonjrcbCYi0rQzfxsvpvufoxJ6aENrpPkxZnfACDSK/VSJ8
qj2eQqJcDbRJ6cdFunyQJMwPoovturLpzpzUEf5JA30rTvqefl6HRcVxgV50eh9ITBxh4f/RzvkZ
Egi6BAxZDGOkaE0LYEOt89j7ccGhXqYyt+RkRGIxU0Ps5iA//Kx9n7bGEb4p9kcTM1lmhc5lueOz
z97qgH8qFLDUhkpOaerhBDaNvXF5ZgPsTNbeVE7nIL6lw4COQTgRjh0pIi77+Df+QNpg1F99ND9w
FkZ0R8rCAzXE+69W+g8mcHg/1XjVzvqnxI3shsW9g04l3zJzhtI3gYw0rpGoGjky0sRg1jTq/kkl
Xfoh2YBKBeZz6Af1dRb/EWtLqs84QZ5HeUYny2o3jTSt7o4ZCf4DkIGYyJdiquNGIBxeZ1zW70x6
5YHyeB1UxEKd7eiMbh4qrtpUjbsPTiE5UINo/OGP+9d0+owcXL59XlMFhysUlUQoo49GdfiqG0Z9
4k8ECT5amyUWWV9ipW9H79FNnuAQKG5/NnBoT//ePL+mRoABZpXzHTxzqcHLpURNcKz0o0BJC18E
NY863JImJ/sISkNjlgZSQLW8eOuIBpFmu1PCAouOIcYBpJXIMno/XdVq4SiYTwuij10BvLAy2nEX
oQ+KRQyc2W0tMmlt0s259EIaLm6isJC2xwG56vliihsisWWYI16+Iv307KRMqX8fjd8oyqBzoZqk
jZ7/nUM9yynl53W6MwgrPWgk+XDbPhZRYh3ggpz/RKOBAYnP1UHdPd1bzIJuWtNeZtgZT0UlpPsY
zI+T81ZCzfK7CUT91KbvQJ6xhbXIHZG0mFAZOPyqGAMZ2ns/XMguqBOOwKL+9zabMNvBKsHNHxDe
bGSQl2K3idGUslsEVkr+matsFL0+iNxVo05ntelkG2c0k+YsU2ebRyB+57KSYkvHojKs+MX/L1Yu
cjE2IAs1WWHguEKvKvJnuVDbkDwyz8qKkgCSQYSuO5LUjWOX5a2aFseaVdi7PAvHfapXQMUij9WI
6vKL0n3IimT8Mknh12JP1b9kH0bdegEK01QXQvo/dXgcx6oY34CLy3jOxUEtlLb8SUwOyffuRRYo
WUvZNxAcrJC8xQSfg3VFLE8ZYVY1TA3kVA3CVshkOYma30x742v+jggPQrzHAs8FcnZXAPu/CARD
uqpbQ26egpouR066EO/qRxc5+3MnCev9PBHYnUS2c6S5TPxWCJBYybCRzCkQdImzUQe79GwxSszH
895xiE0aQ8gm7a1siVNLWXWSyhBjmZW3z0XxakjYLI/l0azMI26CqO50S+cajTZexpVhRPn7nxxd
sDN9chKBIJ4VGc0w+NPbjiOppzRCppFUQoSMf/PuWDMiI+AQuLXmX8XOC9ynA7RMhYx/49w30jZ/
LbpUHMRBZvHxyDjVEUTEepLiFJJ573dqg7Q17Pgyjit5PlxNFbDrnTg3UtF16Xz3jIrYSfxpmACD
TwBd+/HUGQ5D4XDNdbuECxr6luY6dg9NUL0xDoGsnPU3KO94hH5lVf7YQPhxo9CYDLzw+2dInrU9
Gtsbej4QKwLHcURvaq38xrjCupxQAazo69R01c23176Z5aKWkoBEIWTEPIcPZ8qi+bhmuzHabiLx
2uQL2RZL0QGCqH3l9WbEKrBb8dBQzR5ilsXGG6ri/Ci+l+19LLPFOI1UtenrQJWxTAYXDXufMeNw
N+Jccq0w1U7s19t+PCaaYDfoi1yf9ankswGbIsjecwAsyZP0Cy77c8ih6ZXd+BdJA/UOUo4Ptm+a
9BJe/OrWcwOcHuKqX0tVaMUbQJgePKSegGZsfLuvq5I3yQmvcxsNnkd6c0mUnegYbkE8usJvfnYs
ayaNlgWSgC0lol+1dSRw+tej43exNc1TWd9hm1a7LVmCmoKyKDowm5UyJ/2+Oem3s3utkvck8kfR
IhkpgP/kk+VSargIxm8OrcJrGQjJy/k+LEYLwUfMclwFKgS86PPx3i/i/oCijf6yKAH0WeMAdRuO
tFsKW3ZRJyHkhkJpnhVLKlS7TyEXK1ZmC33HOrL0v1h/cqTZ1o4I4+hRWvx4SLN6+TSwC7ZaYOAI
2balOEMtDqb8Qjlan8TeL9jhfSItZwiQwqQZ8KexTuc4a/UG8xjUnedN9nuVSGCMe0RsUJGyTjGU
dyge35NepVZC0OPHwo66wakxllLLVJeJ/SYgcm++0QtnB+lUjOCbz5F3lGRHe7H03nCxTUgkjzVX
eL7cO4iVBQBWkv8iJJ2Mld8ihl59l2dFmEXX4WzqPknY/I2fcKEoLxRriHiL0CP4xnjaSv+OAvbY
bTKPja0zcbHfTU63aG3fKm2jbhAZ1mfscH7mqrYcSYcwo/Ae46N2wqrSRALSPa/Wir+Hgp8yegeN
+kDLJAMCEjTI5JNXN/dse1fEF49Y2RwjvZmJGEnHQMg6wGSbCma2PM6MOtSXOhO+AJgiRIK2YJ8i
pf3l22/EBQ/7Pa1XyVoqgp2vYbNmXzFNw6MKczgbi1GArxkMPkmywGPHlZ/JO/nz7mf8gAKaznCl
FygZ4bNUMsI3lnKU+1yrq6AFStOFMgh82fFdz52BNjr5tYeF7REp/ditxqVZMA2H7gFy/jnyqGqQ
wkw5nwmjuX8Y4kNLkrwnfaCpOLdm9v6QlKK7QYp4vY7XpQKIAIg1DcFppgooCmN70GkoIOErwgkp
q13e7XDwsdTb+J2maKSpwezuyULuyzshlaLcEFBEXKA9QIIedj4KLBHHCj9pXs/9v05yc9ofFM6J
oWWGkJuWyjLvn98jqRzZO94R7BkoicMadJsCDGseIYyj+6Sn2/hSBjpugrymMOMJANvQw1a7ynsM
TRVGRW+GRjRZEKEShgVJnzuGWV5fdBP0Uzf9b/iHyBWAq9hkuPRt4OimTq75dQ6qtVEK4MXrY3Z1
O3lc1YTOuc8U6ScGhT4cPvH0p9XPZ3S5LXsBv0e1+Xm3ZzZUCaMpv7zE4F/LbiIQh1Ali8hQRMAy
PW1idCjbYtWggqadNNNAU4U5R4yXhCewt1XDMDth8DMs0BrhUDWzrQMaCM0bPuiP7Oosrx3ici3b
dabQxOAJ4i/zip1DIA+8iBpv1n7CVDCPFBTNxOqCu4izrDgmOnV9An3yaNEG17c7039dCA/Oa1UF
r49JvrGWXGByEnznqdprmYUR3EzrHotvTeFc5CeMsiIww6ip+ZZ+mBXZNOJ0idEdKABvYHejFLbn
l2Sue4Izia6Bi/l4bQmVuxDcPXlbeNywoTIwWFqfStalh98PG6ol1mLr9opI6V52zPRa62tkuGsm
gz1VVFW2RiQ9ntbC3FK0gCs2S0hd4xx4y+6tBihxMAIYX+HNbJc6McOeXDFSI0dgdrQPVW13IQ5H
7PeBLrIPsaSxqFUc8gZnqBt5qN/59qGKTzA8xPgq4w4G5fymkaLSTtARPQWLebvMYm84x+H9wN5q
v8KZEYEV0vm6ZZRCcUFuO5XOfP+m4BAVWZ0d3QQrfQi5NvxihGLIYdu9sk7VTS+PFRkDMzd8wuPV
LFJauYyxLqRlqsPb6ChfOdwPhHvTl2sSEblejwi4LkBpC2+L6mLMu7Qw/Id2XkD5RHwYpw0ZPT/b
3FdqTlGtZ1G3dPIqFwvhnGFxHpXb1ZBLUHPom9eZ068PtlfConoNjUtYbAad5pqNd5IOz1XkH70i
WhLrvTJSbpS6+72spbaQGPewzz4yBn1k+xD6Up30xSo6tXsGqkh3+2C3HrHuuw717vb1cACY/QQb
GFs3dG44DHpcFpbOt7rcz27UAjk9zpAQdpW68qkhK4j7CzN4pk8E0EP26cmHalnptq4t/HXCN0Jy
NTHLx5G4UyRrUZlM1CoN8bV+FZzBepk4Ntex73DNzMFaRXSsMm1jLxACgH8Bd/PIKXujVgvcE02d
307oLjPnAsrtXaMuK9jxJeMwWOpFf4LgSoWHyHA1gjy6FPYVeOA/15DBp4+AbNipCnnGSxnNbgd1
eRu5esKGjYitupecgWJ1Lj5ImG73ZUrFQL5lDWgNWw5rxwZSpPIsX+YrlQzZhUqc+MyzPuDYQHqc
0AKE2wZzMuVZe0xZnIpMqDH6noI00PEh5k/G8zX1OYzYZRVij8v3CSkicSQTg2T8W8O0BnZQRDxv
hJw5zjKzyFvxSvS+uF68b/WxrCiBBOnsXOwha41an9hjkL6s/au/x4RQfMquASPvj63usAbh3KhN
EnB+PoMRHUsQqFxEspvIkEDsUf5gLxkR18a8Ek/N6aBa7z3Pq5QblrM9xaaWpVRK8yRYFLVBJ5rt
XBW2emb5GGKzPbF+vmA71K6xe6pdn+agtjjFARwf719e4v9wlOODlbyerqykJ2hRdeUYiOWDckHy
XGHlSUF5pTkwn/iNiXgyoWKEBjIaVWA2JO7fRi98dtpSHmeIp9qznKkE2Fp52mDdaFIdXQeVYats
jDao7x7ZrDxKuH4dcHW9kAX+Tv1Xx3vVc3fyb5Rur5cv3sfvntdlEOdcqu2V1WccfEv7KVFkxwbt
XrSVTbKaiVKaAzaqVlwLUmTA+eJDSH38CQU4b6EivXg//Fo6nGyyImngPdIp6zVPPz6oBHcb6O74
7CuBCzeGyYzzQMbneuPSyV/iEdwhGmMmbvxSCoRvuY92W1htP6nPdW/WpFoL3ZPwU9GEmbv8Bw4+
G4HmiYOFUyi4Jau5YOqgjv3B+/CYZHK7WU1gx9DsBcusLc9Vk+FdKmV6hEmB4WOfQIoDGXY8LCuc
87A7lBE5dzsZuLQ8oRAHjMs9Iv4cs1GaCEI2bEKvEdGGmV3ONTaVKTd7Tavxcvk6xXFxVg9PebUq
DA75mr58Y7kXyLqEChBkF1ShqjTCQQzUZVsoeukpXkzoW15TesqjhYMjJWjoxoRdEafcU2pnx9QP
qENyUdFZxKY6vVp7s9p4RZ8MfXg2rooolPVHP7+Jrf2JDttpSqqajgfof4KruQ7oHGZO3Egr+3FP
PzltQw0wT47P0EzbeI9WoVqiUr0XGZQD83pS5Xq8QlPku3+2MHR/XUEsXEMBxpTUvshHAMQK/Oad
0I5TB7xtLPadoLKazXrQuE9L4s0kWEVcPYSFotQjte9bI5AS8eJmMGDjyP4x3Wms7wjckJMV6Rd2
Ds6kuXQQJWIPLubgwPZu0pJPQjuCFIzZeMWsAAD1nHUvyaB/ikCRSBORBrJOrus1Z+AAm6sXwcyC
CZfVnZ/ziVQB/eU8K6HldeU176qLP0FYXDcIrAEmW2U/Ipyd13FhiBXqCSDVDyEhWfE+LFE8ZN+W
tVC3IcJYWvkYeQE8jfzJXOmN5ENDDXHk4BLjejsp9a6WBOXE+rpSpL9zluk4Nb6vTOs6zort0+hD
KOdGoQsSVAZSphFBbSJrshUBZK1dTAURotaSarYGjYCbm8EHE6qBhLAjW6N0Fqzm4+j9mdlCfVkp
Jea1HH8YvFF/9Yboyw+HJpoJzJo3BliHDlIHDgqlsvOxLs7EswT317diG1yEncFMCW2qUKpv4qKV
t30hcLcTW2gLuw6QNBYLuwKAQwwGD1bNG06dtOhZG/xKwI4f7+GdS8P7PB0h0cDtxGgq67dwe1oq
Pu0QuEYDTAOO1e4E5K8k96JGHBo/9G3aL8GM99vmNs7DRg/PIWC344M1lTXgyGu7sI00OCAtP+DU
FOD7UH0gY5mxU2OsywfXbH+X3bEgZrmDa0agL01VM2KDqOmhYCfLk8gjuBFqfa3ufZqiBA2mnca0
bYvWnvSXt89cqh8NbIeQ9Vh/HiMwrKYm3v+ier2oRVnGfEdP5e9XrZZuhyDw+uHOyc2B3jDiPcD5
O/bWlP4DNEH7WJmQ8iiQStJUFoQBJjb1FeWOE3838+5lNsck9xvFAjGItoYDi1/6X6Jm1KFRzw6w
uoYcYv7byHNFiSrAmMuPkro3iJqyZfNWzlnFfhVAouayU6rVDznlnGFZYjfVjpqMdcXsKNb7GCuA
xhnmnw/8eOLRrE4fWSmkt6r+heXj38V2/xAHiorzcH/VfsFicZs4SAKWwRNzaC1hxad204sZNuLz
gn9n5RR0+wjbvgHhC+WnqZ36S751gRpr0WY/W3LYDXOqc3jjewdSSr/I4JSbSYm4eEPtYMbt7QmA
QB+DJKtMLETpWm7xOARn2Zf0k73B4j4xdle+o/qhft3W8GMPNbQB3/q+SbCVxYl49HRvUN/dscAp
Jq6pFvEwYthisKNrNzqtZwUaisaD8LUz6qkYyFHVzqlBZZd4FF8BHLVwqNPnCK2oyoer5UZjbfAF
VWmFQZ32W/79InU4tKtw7p2bTjPq/HXch73WJ/dnZN03xepcfao+k+5o5G0EoP8D2ccNhsPEgLD7
43TbPc8wEiPLBb8GtHVA4HUeJzOFRm+8Pu+QXbZCeJPqkLASFDpSEBo3SFQWpskhxDaoeBsttEs9
jNJPqpi8BuriD3Zoml6t/Oax1zxdJtQqe7/3nHi4QYoTyj4Jr9FLfiUsZ8fQ/Y8mT8iYO+lnpKY5
h5r2FP6ZTa4/LRRVX772tDfOcMvcc8UZVOPluttugE474EVCu6G8s0zCfjyA/GDsvlpTUMGi9NIo
kFkv018fuJ2UG6n3YrRrVc68uSNIjyWyrDfcKFgAvpEM2hx+++edpxPk/u11kUMXdalVSuW3+Mfk
4wXSHDcauiW7eDVBpDJOs60Cd6khPg70oXq4zvnsXoAXrS4fswAd+Ca6sOzw7M5Aa6rrwYLyx5p8
n2SgvaOySicYRdPhjC4Uz2UMoUgPPhq4VrAAyl6CbbW7HxZt/x7gddwmSETyVXTZw6prcQ0sDQ4J
5qeaOYRk01efpt8bjMwKgnwicZXC6JqF02BIvvDPZFXvks7gIE2FaxwT4rMcvqAV37FmQOUmCxCZ
j0ttVyt63k8LmYuRpxHqQm0IkUh5GQE+DKhCUk/FFYOu/oATlrKgp9lnerOkBo/9PQu3WCBUXbO9
ohlzS6kXTtiqE+Y/9Sg5fUnu4UzbKXOlw7sqW8wfmRxS807gY4z+dtYg6VahAy7swn2h/jE8E6cq
9jXToJ/kiH6vsoPbu7ZKS28KKOVb/nAMY+u7Kdj58rcDH1R7U82BvWHEySmr5wjZ8L891yPBf8Hf
rgBR3Cb+3m99gG4WIAUC/LrYQGrVhfvWgzbp+7grfsqHmpAyRmALokxUSAkSu6QDnsGOdNa42nEI
AU9FGEa8eZK9ELFt+q9DaUf88zZ1Xmf7F1cSej5rZaE2ENxodhnVLRJVKMAyBzPyGvVkNiUOr/H/
OlhIp85nIZaIgsO3h1lOzbZJLBq1r85xgVfaoQAp5aC8wjd6zb478XrV3zXeFrXzUM46cJPFzndG
Z0Ujh7xV1Im63uV836SpxhkGqldxkyA+FCxAGlJO1AUe5A8QUUktxMQO+T3Qwcajo6cx3W6UNg+M
rwX80pTolky3Z2F0MZbGZlpNYiBlRunmW1DxqKSLbNmq3L51y+1kooWwRzwFCA3F7zN59Y85/gcS
WrUm9gkCgMEsN1wEj6WcR6Xdn4wqh9EL+Sm2LkXc3gKFB44wwvbDUnD5vqQEGAn/lo0+iN8eAC9i
Q56HhkSsx89FI5bX3D/dIAQUWgH1z9BLhzzg+jlERqxc+DNHnYeQLY0NeREM0oqyd7Gi97KfVlwp
D/W+JbdaT0hq1hQjlwEP2Fp0yza+RjcovUvC7kLUuyZ4v7Qq/rEvvtT1Pb2WODNL01K5BN3EbMfH
6+p8bNsxr8nLLmqtJl/3u92CnFzVHjuZ6pIpB9WqiZF8vRzeJ9GH6x9RSGA5FD1Z+JQoxAG3tCjg
IKU/Qrd0rWiTj/7S3hkAdhSJU+Bol12Vvrv0/9oqWGd7aeYZkusJ83rtoRbz60mAyRW0DF0mf8Pe
fcfWuz+Rsof2V+2iw+14N29/B1zT1Rk/XVxfefZT1qbzG0QiByEnYaNkha9pR/sa+4wl7199dQK5
OBJrvIZOTeJOpapAq7T7e+6ir8ZYhQ8aSevFUdkJQbcRGA0gbBuly+mXQuVPPCDhAmuDFZ8fDfwG
xuWSzrbJdSAK0DGw1/fskkdJxBxzJuHxAdznTiNinDCxvAJjiPuYTF4wJMBzFJxE0FyvKVlFRZeW
eKtu/qO9pTzc/GrRf62qVA/LPMw6qITcOCzsszblZB3CRV3/z5rnq230c6BbBj0fZbDy/++RV9J/
4OcOxtMGc7kUzUJvDH2fTNguuzL2B7a2zLosuMi/n5laJnAk/qDssSQFEq/Bvvaa0s7odCNsj1hn
feYnuatAjr5LdmMXUEZeDpCaeIOl5/nFL7/n4rOcTE7r0bqH+YpfzQ==
`protect end_protected
| gpl-3.0 | c789e5c1fa230d9dbdf89d470b580832 | 0.953424 | 1.812433 | false | false | false | false |
dcliche/mdsynth | rtl/src/bit_funcs.vhd | 1 | 3,017 | --===========================================================================--
-- --
-- bit_funcs.vhd - Power2 & Log2 Funtions Package --
-- --
--===========================================================================--
--
-- File name : bit_funcs.vhd
--
-- Purpose : Implements power2 and log2 functions.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- bit_func.vhd is a VHDL functions package for calulating power2 and log2.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Revision Name Date Description
-- 0.1 John E. Kent unknown Initial version
-- 1.0 John E. Kent 30th May 2010 Added GPL Header
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package bit_funcs is
function log2(v: in natural) return natural;
function pow2(v: in natural) return natural;
end package bit_funcs;
package body bit_funcs is
function log2 (v : in natural) return natural is
variable temp, log: natural;
begin
temp := v / 2;
log := 0;
while (temp /= 0) loop
temp := temp/2;
log := log + 1;
end loop;
return log;
end function log2;
function pow2(v: in natural) return natural is
variable i: natural;
variable pown: natural;
begin
pown := 1;
for i in 0 to v loop
exit when (i=v);
pown := pown * 2;
end loop;
return pown;
end function pow2;
end package body bit_funcs;
| gpl-3.0 | 5c3379d264e8fa0d8cd498a3c201c740 | 0.472986 | 4.606107 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00621.vhd | 1 | 6,555 | -- NEED RESULT: ARCH00621: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00621.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00621: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00621: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00621: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00621
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00621(ARCH00621)
-- ENT00621_Test_Bench(ARCH00621_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00621 is
end ENT00621 ;
--
--
architecture ARCH00621 of ENT00621 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
procedure P1
(signal s_st_arr1_vector : in st_arr1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00621" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00621" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr1_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr1_vector ,
st_arr1_vector_select ,
s_st_arr1_vector_savt ,
chk_st_arr1_vector ,
s_st_arr1_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr1_vector_select select
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00621 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00621_Test_Bench is
end ENT00621_Test_Bench ;
--
--
architecture ARCH00621_Test_Bench of ENT00621_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00621 ( ARCH00621 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00621_Test_Bench ;
| gpl-3.0 | 5ab69cb61edbeafa935b7d857603b749 | 0.533791 | 3.2775 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00162.vhd | 1 | 7,617 | -- NEED RESULT: ARCH00162.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00162: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00162
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00162)
-- ENT00162_Test_Bench(ARCH00162_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00162 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00162.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00162" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00162" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00162" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00162" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00162" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00162 ;
--
entity ENT00162_Test_Bench is
end ENT00162_Test_Bench ;
--
architecture ARCH00162_Test_Bench of ENT00162_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00162 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00162_Test_Bench ;
| gpl-3.0 | 49a9a0f5263f21801a53e1aa65c87be2 | 0.472627 | 3.569353 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00126.vhd | 1 | 12,061 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00126
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00126
-- PKG00126/BODY
-- E00000(ARCH00126)
-- ENT00126_Test_Bench(ARCH00126_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00126 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00126 ;
--
package body PKG00126 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00126 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00126.all ;
architecture ARCH00126 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_r_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_r_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00126.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00126" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_r_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_r_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00126.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00126" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_r_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_r_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00126.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00126" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00126" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00126 ;
--
entity ENT00126_Test_Bench is
end ENT00126_Test_Bench ;
--
architecture ARCH00126_Test_Bench of ENT00126_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00126 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00126_Test_Bench ;
| gpl-3.0 | 602dbf388fd042a66bdb5609eca14f32 | 0.479231 | 3.319846 | false | true | false | false |
jairov4/accel-oil | solution_spartan3/impl/vhdl/nfa_accept_sample.vhd | 1 | 69,807 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
signal reg_378 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_585 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_cast_fu_390_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_cast_reg_600 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_405_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_605 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_410_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_609 : STD_LOGIC_VECTOR (15 downto 0);
signal sample_addr_1_reg_614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_fu_428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_i_reg_620 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_422_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_reg_624 : STD_LOGIC_VECTOR (63 downto 0);
signal sym_reg_629 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_1_i_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_1_i_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_reg_638 : STD_LOGIC_VECTOR (4 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bucket_index1_ph_cast_fu_444_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_448_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_i_cast_fu_452_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_i_cast_reg_658 : STD_LOGIC_VECTOR (13 downto 0);
signal j_end_phi_fu_316_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_673 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_i_reg_688 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_693 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_698 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_703 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_708 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_490_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_8_i_reg_713 : STD_LOGIC_VECTOR (13 downto 0);
signal next_buckets_0_1_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_731 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_552_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_reg_756 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_761 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_580_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_766 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_ce : STD_LOGIC;
signal i_reg_138 : STD_LOGIC_VECTOR (15 downto 0);
signal any_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal p_01_rec_reg_150 : STD_LOGIC_VECTOR (63 downto 0);
signal next_buckets_1_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_reg_172 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_182 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_194 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_207 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_220 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_231 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_242 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_269 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_282 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_293 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_303 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal any_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_336 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_fu_400_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_i_cast_fu_517_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_i_cast_fu_535_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_410_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_410_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_422_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_422_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_fu_455_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_471_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_484_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_490_p0 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_490_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_4_i_fu_510_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_9_i_fu_528_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_400_ce : STD_LOGIC;
signal grp_fu_410_ce : STD_LOGIC;
signal grp_fu_422_ce : STD_LOGIC;
signal grp_fu_471_ce : STD_LOGIC;
signal grp_fu_484_ce : STD_LOGIC;
signal grp_fu_490_ce : STD_LOGIC;
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal grp_fu_484_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_484_p10 : STD_LOGIC_VECTOR (13 downto 0);
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (5 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (13 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_348 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
p_read => grp_bitset_next_fu_348_p_read,
r_bit => grp_bitset_next_fu_348_r_bit,
r_bucket_index => grp_bitset_next_fu_348_r_bucket_index,
r_bucket => grp_bitset_next_fu_348_r_bucket,
ap_return_0 => grp_bitset_next_fu_348_ap_return_0,
ap_return_1 => grp_bitset_next_fu_348_ap_return_1,
ap_return_2 => grp_bitset_next_fu_348_ap_return_2,
ap_return_3 => grp_bitset_next_fu_348_ap_return_3,
ap_ce => grp_bitset_next_fu_348_ap_ce);
grp_nfa_get_initials_fu_360 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_360_ap_start,
ap_done => grp_nfa_get_initials_fu_360_ap_done,
ap_idle => grp_nfa_get_initials_fu_360_ap_idle,
ap_ready => grp_nfa_get_initials_fu_360_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_360_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_360_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_fu_360_ap_ce,
ap_return_0 => grp_nfa_get_initials_fu_360_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_360_ap_return_1);
grp_nfa_get_finals_fu_366 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_366_ap_start,
ap_done => grp_nfa_get_finals_fu_366_ap_done,
ap_idle => grp_nfa_get_finals_fu_366_ap_idle,
ap_ready => grp_nfa_get_finals_fu_366_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_366_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_366_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_fu_366_ap_ce,
ap_return_0 => grp_nfa_get_finals_fu_366_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_366_ap_return_1);
grp_p_bsf32_hw_fu_372 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_372_bus_r,
ap_return => grp_p_bsf32_hw_fu_372_ap_return,
ap_ce => grp_p_bsf32_hw_fu_372_ap_ce);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U17 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 17,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_400_p0,
din1 => grp_fu_400_p1,
ce => grp_fu_400_ce,
dout => grp_fu_400_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 18,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_410_p0,
din1 => grp_fu_410_p1,
ce => grp_fu_410_ce,
dout => grp_fu_410_p2);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U19 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 19,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_422_p0,
din1 => grp_fu_422_p1,
ce => grp_fu_422_ce,
dout => grp_fu_422_p2);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2
generic map (
ID => 20,
NUM_STAGE => 2,
din0_WIDTH => 6,
din1_WIDTH => 6,
dout_WIDTH => 6)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_471_p0,
din1 => grp_fu_471_p1,
ce => grp_fu_471_ce,
dout => grp_fu_471_p2);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9
generic map (
ID => 21,
NUM_STAGE => 9,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_484_p0,
din1 => grp_fu_484_p1,
ce => grp_fu_484_ce,
dout => grp_fu_484_p2);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4
generic map (
ID => 22,
NUM_STAGE => 4,
din0_WIDTH => 14,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_490_p0,
din1 => grp_fu_490_p1,
ce => grp_fu_490_ce,
dout => grp_fu_490_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_336;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_366_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st24_fsm_23 = ap_NS_fsm) and (ap_ST_st23_fsm_22 = ap_CS_fsm) and (tmp_s_reg_605 = ap_const_lv1_0))) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_366_ap_ready)) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_194 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_1;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_reg_323 assign process. --
any_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_182 assign process. --
bus_assign_reg_182_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_1_reg_162;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_0_reg_172;
end if;
end if;
end process;
-- i_reg_138 assign process. --
i_reg_138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
i_reg_138 <= i_1_reg_609;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
i_reg_138 <= ap_const_lv16_0;
end if;
end if;
end process;
-- j_bit1_reg_303 assign process. --
j_bit1_reg_303_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit1_ph_cast_fu_448_p1;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit_reg_693;
end if;
end if;
end process;
-- j_bucket1_ph_reg_207 assign process. --
j_bucket1_ph_reg_207_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket1_ph_reg_207 <= bus_assign_reg_182;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket1_ph_reg_207 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_282 assign process. --
j_bucket1_reg_282_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket1_ph_reg_207;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket_reg_703;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_220 assign process. --
j_bucket_index1_ph_reg_220_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_220 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket_index1_ph_reg_220 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_293 assign process. --
j_bucket_index1_reg_293_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index1_ph_cast_fu_444_p1;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index_reg_698;
end if;
end if;
end process;
-- j_end_ph_reg_242 assign process. --
j_end_ph_reg_242_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_end_ph_reg_242 <= ap_const_lv1_0;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_19_1_i_reg_634 = ap_const_lv1_0)))) then
j_end_ph_reg_242 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_313 assign process. --
j_end_reg_313_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_end_reg_313 <= j_end_ph_reg_242;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
j_end_reg_313 <= p_s_reg_708;
end if;
end if;
end process;
-- next_buckets_0_reg_172 assign process. --
next_buckets_0_reg_172_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_0_reg_172 <= tmp_buckets_0_3_reg_269;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_0_reg_172 <= current_buckets_0_reg_585;
end if;
end if;
end process;
-- next_buckets_1_reg_162 assign process. --
next_buckets_1_reg_162_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_1_reg_162 <= tmp_buckets_1_3_reg_256;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_1_reg_162 <= current_buckets_1_reg_590;
end if;
end if;
end process;
-- p_01_rec_reg_150 assign process. --
p_01_rec_reg_150_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
p_01_rec_reg_150 <= p_rec_reg_624;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
p_01_rec_reg_150 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_336 assign process. --
p_0_reg_336_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
p_0_reg_336 <= ap_const_lv1_0;
elsif ((ap_ST_st77_fsm_76 = ap_CS_fsm)) then
p_0_reg_336 <= tmp_2_reg_766;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_269 assign process. --
tmp_buckets_0_3_reg_269_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= ap_const_lv32_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= next_buckets_0_1_reg_731;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_256 assign process. --
tmp_buckets_1_3_reg_256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= ap_const_lv32_0;
elsif ((ap_ST_st67_fsm_66 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= next_buckets_1_1_fu_552_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st74_fsm_73 = ap_CS_fsm)) then
current_buckets_0_1_reg_751 <= current_buckets_0_1_fu_566_p2;
current_buckets_1_1_reg_756 <= current_buckets_1_1_fu_571_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
current_buckets_0_reg_585 <= grp_nfa_get_initials_fu_360_ap_return_0;
current_buckets_1_reg_590 <= grp_nfa_get_initials_fu_360_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
i_1_reg_609 <= grp_fu_410_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bit1_ph_reg_231 <= r_bit_reg_638;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then
j_bit_reg_693 <= grp_bitset_next_fu_348_ap_return_0;
j_bucket_index_reg_698 <= grp_bitset_next_fu_348_ap_return_1;
j_bucket_reg_703 <= grp_bitset_next_fu_348_ap_return_2;
p_s_reg_708 <= grp_bitset_next_fu_348_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm))) then
next_buckets_0_1_reg_731 <= next_buckets_0_1_fu_546_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
p_rec_reg_624 <= grp_fu_422_p2;
sym_reg_629 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
r_bit_reg_638 <= grp_p_bsf32_hw_fu_372_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st65_fsm_64 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm)))) then
reg_378 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
sample_addr_1_reg_614 <= grp_fu_400_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
state_reg_673 <= grp_fu_471_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
tmp_14_cast_reg_600(0) <= tmp_14_cast_fu_390_p1(0);
tmp_14_cast_reg_600(1) <= tmp_14_cast_fu_390_p1(1);
tmp_14_cast_reg_600(2) <= tmp_14_cast_fu_390_p1(2);
tmp_14_cast_reg_600(3) <= tmp_14_cast_fu_390_p1(3);
tmp_14_cast_reg_600(4) <= tmp_14_cast_fu_390_p1(4);
tmp_14_cast_reg_600(5) <= tmp_14_cast_fu_390_p1(5);
tmp_14_cast_reg_600(6) <= tmp_14_cast_fu_390_p1(6);
tmp_14_cast_reg_600(7) <= tmp_14_cast_fu_390_p1(7);
tmp_14_cast_reg_600(8) <= tmp_14_cast_fu_390_p1(8);
tmp_14_cast_reg_600(9) <= tmp_14_cast_fu_390_p1(9);
tmp_14_cast_reg_600(10) <= tmp_14_cast_fu_390_p1(10);
tmp_14_cast_reg_600(11) <= tmp_14_cast_fu_390_p1(11);
tmp_14_cast_reg_600(12) <= tmp_14_cast_fu_390_p1(12);
tmp_14_cast_reg_600(13) <= tmp_14_cast_fu_390_p1(13);
tmp_14_cast_reg_600(14) <= tmp_14_cast_fu_390_p1(14);
tmp_14_cast_reg_600(15) <= tmp_14_cast_fu_390_p1(15);
tmp_14_cast_reg_600(16) <= tmp_14_cast_fu_390_p1(16);
tmp_14_cast_reg_600(17) <= tmp_14_cast_fu_390_p1(17);
tmp_14_cast_reg_600(18) <= tmp_14_cast_fu_390_p1(18);
tmp_14_cast_reg_600(19) <= tmp_14_cast_fu_390_p1(19);
tmp_14_cast_reg_600(20) <= tmp_14_cast_fu_390_p1(20);
tmp_14_cast_reg_600(21) <= tmp_14_cast_fu_390_p1(21);
tmp_14_cast_reg_600(22) <= tmp_14_cast_fu_390_p1(22);
tmp_14_cast_reg_600(23) <= tmp_14_cast_fu_390_p1(23);
tmp_14_cast_reg_600(24) <= tmp_14_cast_fu_390_p1(24);
tmp_14_cast_reg_600(25) <= tmp_14_cast_fu_390_p1(25);
tmp_14_cast_reg_600(26) <= tmp_14_cast_fu_390_p1(26);
tmp_14_cast_reg_600(27) <= tmp_14_cast_fu_390_p1(27);
tmp_14_cast_reg_600(28) <= tmp_14_cast_fu_390_p1(28);
tmp_14_cast_reg_600(29) <= tmp_14_cast_fu_390_p1(29);
tmp_14_cast_reg_600(30) <= tmp_14_cast_fu_390_p1(30);
tmp_14_cast_reg_600(31) <= tmp_14_cast_fu_390_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then
tmp_19_1_i_reg_634 <= tmp_19_1_i_fu_434_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
tmp_19_i_reg_620 <= tmp_19_i_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st75_fsm_74 = ap_CS_fsm)) then
tmp_1_reg_761 <= tmp_1_fu_576_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st76_fsm_75 = ap_CS_fsm)) then
tmp_2_reg_766 <= tmp_2_fu_580_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st55_fsm_54 = ap_CS_fsm)) then
tmp_6_i_reg_688 <= grp_fu_484_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_7_i_cast_reg_658(0) <= tmp_7_i_cast_fu_452_p1(0);
tmp_7_i_cast_reg_658(1) <= tmp_7_i_cast_fu_452_p1(1);
tmp_7_i_cast_reg_658(2) <= tmp_7_i_cast_fu_452_p1(2);
tmp_7_i_cast_reg_658(3) <= tmp_7_i_cast_fu_452_p1(3);
tmp_7_i_cast_reg_658(4) <= tmp_7_i_cast_fu_452_p1(4);
tmp_7_i_cast_reg_658(5) <= tmp_7_i_cast_fu_452_p1(5);
tmp_7_i_cast_reg_658(6) <= tmp_7_i_cast_fu_452_p1(6);
tmp_7_i_cast_reg_658(7) <= tmp_7_i_cast_fu_452_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st59_fsm_58 = ap_CS_fsm)) then
tmp_8_i_reg_713 <= grp_fu_490_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then
tmp_buckets_0_reg_741 <= grp_nfa_get_finals_fu_366_ap_return_0;
tmp_buckets_1_reg_746 <= grp_nfa_get_finals_fu_366_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
tmp_s_reg_605 <= tmp_s_fu_405_p2;
end if;
end if;
end process;
tmp_14_cast_reg_600(63 downto 32) <= "00000000000000000000000000000000";
tmp_7_i_cast_reg_658(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_605 , tmp_19_i_reg_620 , tmp_19_1_i_reg_634 , j_end_phi_fu_316_p4 , any_phi_fu_328_p4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
if ((tmp_s_reg_605 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st68_fsm_67;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_620 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_620 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
if (not((tmp_19_1_i_reg_634 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st41_fsm_40;
end if;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st46_fsm_45;
end if;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st66_fsm_65;
else
ap_NS_fsm <= ap_ST_st65_fsm_64;
end if;
when ap_ST_st66_fsm_65 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st67_fsm_66;
else
ap_NS_fsm <= ap_ST_st66_fsm_65;
end if;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_194),2));
any_phi_fu_328_p4 <= any_reg_323;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st78_fsm_77 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_336, ap_return_preg)
begin
if ((ap_ST_st78_fsm_77 = ap_CS_fsm)) then
ap_return <= p_0_reg_336;
else
ap_return <= ap_return_preg;
end if;
end process;
current_buckets_0_1_fu_566_p2 <= (next_buckets_0_reg_172 and tmp_buckets_0_reg_741);
current_buckets_1_1_fu_571_p2 <= (next_buckets_1_reg_162 and tmp_buckets_1_reg_746);
-- grp_bitset_next_fu_348_ap_ce assign process. --
grp_bitset_next_fu_348_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_316_p4)
begin
if ((((ap_ST_st45_fsm_44 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_316_p4)) or (ap_ST_st46_fsm_45 = ap_CS_fsm) or (ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm) or (ap_ST_st48_fsm_47 = ap_CS_fsm) or (ap_ST_st49_fsm_48 = ap_CS_fsm) or (ap_ST_st50_fsm_49 = ap_CS_fsm) or (ap_ST_st51_fsm_50 = ap_CS_fsm) or (ap_ST_st52_fsm_51 = ap_CS_fsm) or (ap_ST_st53_fsm_52 = ap_CS_fsm) or (ap_ST_st54_fsm_53 = ap_CS_fsm))) then
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_1;
else
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_bitset_next_fu_348_p_read <= next_buckets_1_reg_162;
grp_bitset_next_fu_348_r_bit <= j_bit1_reg_303;
grp_bitset_next_fu_348_r_bucket <= j_bucket1_reg_282;
grp_bitset_next_fu_348_r_bucket_index <= j_bucket_index1_reg_293;
grp_fu_400_ce <= ap_const_logic_1;
grp_fu_400_p0 <= p_01_rec_reg_150;
grp_fu_400_p1 <= tmp_14_cast_reg_600;
grp_fu_410_ce <= ap_const_logic_1;
grp_fu_410_p0 <= i_reg_138;
grp_fu_410_p1 <= ap_const_lv16_1;
-- grp_fu_422_ce assign process. --
grp_fu_422_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_605)
begin
if (((ap_ST_st38_fsm_37 = ap_CS_fsm) or ((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or ((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((tmp_s_reg_605 = ap_const_lv1_0))) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm))) then
grp_fu_422_ce <= ap_const_logic_1;
else
grp_fu_422_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_422_p0 <= p_01_rec_reg_150;
grp_fu_422_p1 <= ap_const_lv64_1;
grp_fu_471_ce <= ap_const_logic_1;
grp_fu_471_p0 <= (tmp_31_fu_455_p1 & ap_const_lv5_0);
grp_fu_471_p1 <= j_bit1_reg_303(6 - 1 downto 0);
grp_fu_484_ce <= ap_const_logic_1;
grp_fu_484_p0 <= grp_fu_484_p00(8 - 1 downto 0);
grp_fu_484_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_484_p1 <= grp_fu_484_p10(6 - 1 downto 0);
grp_fu_484_p10 <= std_logic_vector(resize(unsigned(state_reg_673),14));
grp_fu_490_ce <= ap_const_logic_1;
grp_fu_490_p0 <= tmp_6_i_reg_688;
grp_fu_490_p1 <= tmp_7_i_cast_reg_658;
grp_nfa_get_finals_fu_366_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_366_ap_start <= grp_nfa_get_finals_fu_366_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_360_ap_ce <= ap_const_logic_1;
-- grp_nfa_get_initials_fu_360_ap_start assign process. --
grp_nfa_get_initials_fu_360_ap_start_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_1;
else
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_0;
end if;
end process;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
-- grp_p_bsf32_hw_fu_372_ap_ce assign process. --
grp_p_bsf32_hw_fu_372_ap_ce_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_p_bsf32_hw_fu_372_bus_r <= bus_assign_reg_182;
j_bit1_ph_cast_fu_448_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_231),8));
j_bucket_index1_ph_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_220),8));
j_end_phi_fu_316_p4 <= j_end_reg_313;
next_buckets_0_1_fu_546_p2 <= (tmp_buckets_0_3_reg_269 or reg_378);
next_buckets_1_1_fu_552_p2 <= (tmp_buckets_1_3_reg_256 or reg_378);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_4_i_cast_fu_517_p1, tmp_9_i_cast_fu_535_p1)
begin
if ((ap_ST_st61_fsm_60 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_9_i_cast_fu_535_p1(32 - 1 downto 0);
elsif ((ap_ST_st60_fsm_59 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_4_i_cast_fu_517_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st60_fsm_59 = ap_CS_fsm) or (ap_ST_st61_fsm_60 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st65_fsm_64 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st66_fsm_65 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_size;
sample_address <= sample_addr_1_reg_614;
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
tmp_14_cast_fu_390_p1 <= std_logic_vector(resize(unsigned(tmp_14),64));
tmp_19_1_i_fu_434_p2 <= "1" when (next_buckets_1_reg_162 = ap_const_lv32_0) else "0";
tmp_19_i_fu_428_p2 <= "1" when (next_buckets_0_reg_172 = ap_const_lv32_0) else "0";
tmp_1_fu_576_p2 <= (current_buckets_1_1_reg_756 or current_buckets_0_1_reg_751);
tmp_2_fu_580_p2 <= "0" when (tmp_1_reg_761 = ap_const_lv32_0) else "1";
tmp_31_fu_455_p1 <= j_bucket_index1_reg_293(1 - 1 downto 0);
tmp_4_i_cast_fu_517_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_510_p3),64));
tmp_4_i_fu_510_p3 <= (tmp_8_i_reg_713 & ap_const_lv1_0);
tmp_7_i_cast_fu_452_p1 <= std_logic_vector(resize(unsigned(sym_reg_629),14));
tmp_9_i_cast_fu_535_p1 <= std_logic_vector(resize(unsigned(tmp_9_i_fu_528_p3),64));
tmp_9_i_fu_528_p3 <= (tmp_8_i_reg_713 & ap_const_lv1_1);
tmp_s_fu_405_p2 <= "1" when (unsigned(i_reg_138) < unsigned(length_r)) else "0";
end behav;
| lgpl-3.0 | 1af4f07fcbcec2b99bb245d2358daf19 | 0.576833 | 2.744525 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_lmb_bram_wrapper.vhd | 1 | 2,902 | -------------------------------------------------------------------------------
-- system_lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of system_lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of system_lmb_bram_wrapper : entity is "yes";
end system_lmb_bram_wrapper;
architecture STRUCTURE of system_lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#1000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "virtex5"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
| lgpl-3.0 | 2dd3fd1c33a16bec784bc508f875d55b | 0.573398 | 2.946193 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_sim_pkg.vhd | 1 | 8,668 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
| lgpl-3.0 | b5866bd37f3859c71c53bb0b9a3e5902 | 0.493424 | 3.990792 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00571.vhd | 1 | 1,609 | -- NEED RESULT: ARCH00571: Package STANDARD tests passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00571
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.2 (1)
-- 14.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00571)
-- ENT00571_Test_Bench(ARCH00571_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00571 of E00000 is
constant t : time := 3 ns ;
signal z : integer := 0 ;
begin
P :
process ( z )
variable standard : integer := 2 ; -- this tests 14.2 (2)
variable n : integer := 0 ;
begin
if n = 0 then
z <= 10 after t ;
n := 1 ;
else
test_report ( "ARCH00571" ,
"Package STANDARD tests" ,
(standard = 2) and
(NOW = t) -- this tests 14.2 (1)
) ;
end if ;
end process P ;
end ARCH00571 ;
--
entity ENT00571_Test_Bench is
end ENT00571_Test_Bench ;
architecture ARCH00571_Test_Bench of ENT00571_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00571 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00571_Test_Bench ;
--
| gpl-3.0 | 37018f625f438dfe7037c68a437bc783 | 0.469857 | 3.467672 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00636.vhd | 1 | 139,322 | -- NEED RESULT: ARCH00636.P1: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P2: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P3: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P4: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P5: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P6: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P7: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P8: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P9: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P10: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P11: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P12: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P13: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P14: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P15: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P16: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636.P17: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00636: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00636
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00636)
-- ENT00636_Test_Bench(ARCH00636_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00636 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
signal s_boolean_1 : boolean
:= c_boolean_1 ;
signal s_bit_1 : bit
:= c_bit_1 ;
signal s_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal s_character_1 : character
:= c_character_1 ;
signal s_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_1 : integer
:= c_integer_1 ;
signal s_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal s_time_1 : time
:= c_time_1 ;
signal s_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal s_real_1 : real
:= c_real_1 ;
signal s_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_2 : boolean
:= c_boolean_1 ;
signal s_bit_2 : bit
:= c_bit_1 ;
signal s_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal s_character_2 : character
:= c_character_1 ;
signal s_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_2 : integer
:= c_integer_1 ;
signal s_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal s_time_2 : time
:= c_time_1 ;
signal s_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal s_real_2 : real
:= c_real_1 ;
signal s_st_real1_2 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_3 : boolean
:= c_boolean_1 ;
signal s_bit_3 : bit
:= c_bit_1 ;
signal s_severity_level_3 : severity_level
:= c_severity_level_1 ;
signal s_character_3 : character
:= c_character_1 ;
signal s_st_enum1_3 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_3 : integer
:= c_integer_1 ;
signal s_st_int1_3 : st_int1
:= c_st_int1_1 ;
signal s_time_3 : time
:= c_time_1 ;
signal s_st_phys1_3 : st_phys1
:= c_st_phys1_1 ;
signal s_real_3 : real
:= c_real_1 ;
signal s_st_real1_3 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_3 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_3 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_3 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_3 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_3 : st_arr3
:= c_st_arr3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ;
--
when 1
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 30 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 40 ns ;
--
when 3
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 100 ns ;
--
when 5
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 20 ns ,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 30 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 6
=> correct :=
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 7
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_boolean_1'ACTIVE and
s_boolean_2'ACTIVE and
s_boolean_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ;
--
when 1
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 30 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 40 ns ;
--
when 3
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 100 ns ;
--
when 5
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 20 ns ,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 30 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 6
=> correct :=
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 7
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_bit_1'ACTIVE and
s_bit_2'ACTIVE and
s_bit_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ;
--
when 1
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 30 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 40 ns ;
--
when 3
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 100 ns ;
--
when 5
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 30 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 6
=> correct :=
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 7
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_severity_level_1'ACTIVE and
s_severity_level_2'ACTIVE and
s_severity_level_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ;
--
when 1
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 30 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 40 ns ;
--
when 3
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 100 ns ;
--
when 5
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 20 ns ,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 30 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 6
=> correct :=
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 7
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_character_1'ACTIVE and
s_character_2'ACTIVE and
s_character_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 30 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 30 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_enum1_1'ACTIVE and
s_st_enum1_2'ACTIVE and
s_st_enum1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ;
--
when 1
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 30 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 40 ns ;
--
when 3
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 100 ns ;
--
when 5
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 20 ns ,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 30 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 6
=> correct :=
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 7
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_integer_1'ACTIVE and
s_integer_2'ACTIVE and
s_integer_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 30 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 30 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_int1_1'ACTIVE and
s_st_int1_2'ACTIVE and
s_st_int1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ;
--
when 1
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 30 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 40 ns ;
--
when 3
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 100 ns ;
--
when 5
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 20 ns ,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 30 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 6
=> correct :=
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 7
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_time_1'ACTIVE and
s_time_2'ACTIVE and
s_time_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 30 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 30 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_phys1_1'ACTIVE and
s_st_phys1_2'ACTIVE and
s_st_phys1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ;
--
when 1
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 30 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 40 ns ;
--
when 3
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 100 ns ;
--
when 5
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 20 ns ,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 30 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 6
=> correct :=
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 7
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_real_1'ACTIVE and
s_real_2'ACTIVE and
s_real_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 30 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 30 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_real1_1'ACTIVE and
s_st_real1_2'ACTIVE and
s_st_real1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 30 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 30 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_rec1_1'ACTIVE and
s_st_rec1_2'ACTIVE and
s_st_rec1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 30 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 30 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_rec2_1'ACTIVE and
s_st_rec2_2'ACTIVE and
s_st_rec2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 30 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 30 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_rec3_1'ACTIVE and
s_st_rec3_2'ACTIVE and
s_st_rec3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 30 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 30 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_arr1_1'ACTIVE and
s_st_arr1_2'ACTIVE and
s_st_arr1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 30 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 30 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_arr2_1'ACTIVE and
s_st_arr2_2'ACTIVE and
s_st_arr2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 30 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 30 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00636" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until s_st_arr3_1'ACTIVE and
s_st_arr3_2'ACTIVE and
s_st_arr3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00636 ;
--
entity ENT00636_Test_Bench is
end ENT00636_Test_Bench ;
--
architecture ARCH00636_Test_Bench of ENT00636_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00636 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00636_Test_Bench ;
| gpl-3.0 | fe9e0a1030d8607be86946dce09036a0 | 0.417185 | 3.825741 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00680.vhd | 1 | 2,870 | -- NEED RESULT: ARCH00680: Conversion between different integer types passed
-- NEED RESULT: ARCH00680: Conversion between from floating to integer type passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00680
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.5 (2)
-- 7.3.5 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00680)
-- ENT00680_Test_Bench(ARCH00680_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00680 of E00000 is
type int1 is range -10 to 100 ;
type real1 is range -10.0 to 100.5 ;
begin
process
variable c_int1 : int1 := -2 ;
variable c_integer : integer := 70 ;
variable v_int1 : int1 ;
variable v_integer : integer ;
--
variable c_real1_1 : real1 := -2.3 ;
variable c_real_1 : real := 70.6 ;
variable c_real1_2 : real1 := -2.7 ;
variable c_real_2 : real := 70.49 ;
variable v_real1 : real1 ;
variable v_real : real ;
variable correct : boolean := true ;
begin
v_int1 := int1 ( c_integer ) ;
correct := correct and v_int1 = 70 ;
v_integer := integer ( c_int1 ) ;
correct := correct and v_integer = -2 ;
test_report ( "ARCH00680" ,
"Conversion between different integer types" ,
correct ) ;
--
v_int1 := int1 ( c_real1_1 ) ;
correct := correct and v_int1 = -2 ;
v_int1 := int1 ( c_real1_2 ) ;
correct := correct and v_int1 = -3 ;
v_int1 := int1 ( c_real_1 ) ;
correct := correct and v_int1 = 71 ;
v_int1 := int1 ( c_real_2 ) ;
correct := correct and v_int1 = 70 ;
v_integer := integer ( c_real1_1 ) ;
correct := correct and v_integer = -2 ;
v_integer := integer ( c_real1_2 ) ;
correct := correct and v_integer = -3 ;
v_integer := integer ( c_real_1 ) ;
correct := correct and v_integer = 71 ;
v_integer := integer ( c_real_2 ) ;
correct := correct and v_integer = 70 ;
test_report ( "ARCH00680" ,
"Conversion between from floating to integer type" ,
correct ) ;
wait ;
end process ;
end ARCH00680 ;
--
entity ENT00680_Test_Bench is
end ENT00680_Test_Bench ;
architecture ARCH00680_Test_Bench of ENT00680_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00680 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00680_Test_Bench ;
--
| gpl-3.0 | 742b55701fdfee40d4e1e039c052d9a3 | 0.525087 | 3.376471 | false | true | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MC6847/mc6847t1_ntsc_plus_keith.vhd | 1 | 74,344 | -- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity mc6847t1_ntsc_plus_keith is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847t1_ntsc_plus_keith is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"00";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"38";
when x"003" => DATA <= x"44";
when x"004" => DATA <= x"04";
when x"005" => DATA <= x"34";
when x"006" => DATA <= x"4C";
when x"007" => DATA <= x"4C";
when x"008" => DATA <= x"38";
when x"009" => DATA <= x"00";
when x"00A" => DATA <= x"00";
when x"00B" => DATA <= x"00";
when x"00C" => DATA <= x"00";
when x"00D" => DATA <= x"00";
when x"00E" => DATA <= x"00";
when x"00F" => DATA <= x"00";
when x"010" => DATA <= x"00";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"10";
when x"013" => DATA <= x"28";
when x"014" => DATA <= x"44";
when x"015" => DATA <= x"44";
when x"016" => DATA <= x"7C";
when x"017" => DATA <= x"44";
when x"018" => DATA <= x"44";
when x"019" => DATA <= x"00";
when x"01A" => DATA <= x"00";
when x"01B" => DATA <= x"00";
when x"01C" => DATA <= x"00";
when x"01D" => DATA <= x"00";
when x"01E" => DATA <= x"00";
when x"01F" => DATA <= x"00";
when x"020" => DATA <= x"00";
when x"021" => DATA <= x"00";
when x"022" => DATA <= x"78";
when x"023" => DATA <= x"24";
when x"024" => DATA <= x"24";
when x"025" => DATA <= x"38";
when x"026" => DATA <= x"24";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"78";
when x"029" => DATA <= x"00";
when x"02A" => DATA <= x"00";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"00";
when x"02D" => DATA <= x"00";
when x"02E" => DATA <= x"00";
when x"02F" => DATA <= x"00";
when x"030" => DATA <= x"00";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"38";
when x"033" => DATA <= x"44";
when x"034" => DATA <= x"40";
when x"035" => DATA <= x"40";
when x"036" => DATA <= x"40";
when x"037" => DATA <= x"44";
when x"038" => DATA <= x"38";
when x"039" => DATA <= x"00";
when x"03A" => DATA <= x"00";
when x"03B" => DATA <= x"00";
when x"03C" => DATA <= x"00";
when x"03D" => DATA <= x"00";
when x"03E" => DATA <= x"00";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"00";
when x"041" => DATA <= x"00";
when x"042" => DATA <= x"78";
when x"043" => DATA <= x"24";
when x"044" => DATA <= x"24";
when x"045" => DATA <= x"24";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"24";
when x"048" => DATA <= x"78";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"00";
when x"04C" => DATA <= x"00";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"00";
when x"04F" => DATA <= x"00";
when x"050" => DATA <= x"00";
when x"051" => DATA <= x"00";
when x"052" => DATA <= x"7C";
when x"053" => DATA <= x"40";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"70";
when x"056" => DATA <= x"40";
when x"057" => DATA <= x"40";
when x"058" => DATA <= x"7C";
when x"059" => DATA <= x"00";
when x"05A" => DATA <= x"00";
when x"05B" => DATA <= x"00";
when x"05C" => DATA <= x"00";
when x"05D" => DATA <= x"00";
when x"05E" => DATA <= x"00";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"00";
when x"061" => DATA <= x"00";
when x"062" => DATA <= x"7C";
when x"063" => DATA <= x"40";
when x"064" => DATA <= x"40";
when x"065" => DATA <= x"70";
when x"066" => DATA <= x"40";
when x"067" => DATA <= x"40";
when x"068" => DATA <= x"40";
when x"069" => DATA <= x"00";
when x"06A" => DATA <= x"00";
when x"06B" => DATA <= x"00";
when x"06C" => DATA <= x"00";
when x"06D" => DATA <= x"00";
when x"06E" => DATA <= x"00";
when x"06F" => DATA <= x"00";
when x"070" => DATA <= x"00";
when x"071" => DATA <= x"00";
when x"072" => DATA <= x"38";
when x"073" => DATA <= x"44";
when x"074" => DATA <= x"40";
when x"075" => DATA <= x"40";
when x"076" => DATA <= x"4C";
when x"077" => DATA <= x"44";
when x"078" => DATA <= x"38";
when x"079" => DATA <= x"00";
when x"07A" => DATA <= x"00";
when x"07B" => DATA <= x"00";
when x"07C" => DATA <= x"00";
when x"07D" => DATA <= x"00";
when x"07E" => DATA <= x"00";
when x"07F" => DATA <= x"00";
when x"080" => DATA <= x"00";
when x"081" => DATA <= x"00";
when x"082" => DATA <= x"44";
when x"083" => DATA <= x"44";
when x"084" => DATA <= x"44";
when x"085" => DATA <= x"7C";
when x"086" => DATA <= x"44";
when x"087" => DATA <= x"44";
when x"088" => DATA <= x"44";
when x"089" => DATA <= x"00";
when x"08A" => DATA <= x"00";
when x"08B" => DATA <= x"00";
when x"08C" => DATA <= x"00";
when x"08D" => DATA <= x"00";
when x"08E" => DATA <= x"00";
when x"08F" => DATA <= x"00";
when x"090" => DATA <= x"00";
when x"091" => DATA <= x"00";
when x"092" => DATA <= x"38";
when x"093" => DATA <= x"10";
when x"094" => DATA <= x"10";
when x"095" => DATA <= x"10";
when x"096" => DATA <= x"10";
when x"097" => DATA <= x"10";
when x"098" => DATA <= x"38";
when x"099" => DATA <= x"00";
when x"09A" => DATA <= x"00";
when x"09B" => DATA <= x"00";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"00";
when x"09E" => DATA <= x"00";
when x"09F" => DATA <= x"00";
when x"0A0" => DATA <= x"00";
when x"0A1" => DATA <= x"00";
when x"0A2" => DATA <= x"04";
when x"0A3" => DATA <= x"04";
when x"0A4" => DATA <= x"04";
when x"0A5" => DATA <= x"04";
when x"0A6" => DATA <= x"04";
when x"0A7" => DATA <= x"44";
when x"0A8" => DATA <= x"38";
when x"0A9" => DATA <= x"00";
when x"0AA" => DATA <= x"00";
when x"0AB" => DATA <= x"00";
when x"0AC" => DATA <= x"00";
when x"0AD" => DATA <= x"00";
when x"0AE" => DATA <= x"00";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"00";
when x"0B1" => DATA <= x"00";
when x"0B2" => DATA <= x"44";
when x"0B3" => DATA <= x"48";
when x"0B4" => DATA <= x"50";
when x"0B5" => DATA <= x"60";
when x"0B6" => DATA <= x"50";
when x"0B7" => DATA <= x"48";
when x"0B8" => DATA <= x"44";
when x"0B9" => DATA <= x"00";
when x"0BA" => DATA <= x"00";
when x"0BB" => DATA <= x"00";
when x"0BC" => DATA <= x"00";
when x"0BD" => DATA <= x"00";
when x"0BE" => DATA <= x"00";
when x"0BF" => DATA <= x"00";
when x"0C0" => DATA <= x"00";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"40";
when x"0C3" => DATA <= x"40";
when x"0C4" => DATA <= x"40";
when x"0C5" => DATA <= x"40";
when x"0C6" => DATA <= x"40";
when x"0C7" => DATA <= x"40";
when x"0C8" => DATA <= x"7C";
when x"0C9" => DATA <= x"00";
when x"0CA" => DATA <= x"00";
when x"0CB" => DATA <= x"00";
when x"0CC" => DATA <= x"00";
when x"0CD" => DATA <= x"00";
when x"0CE" => DATA <= x"00";
when x"0CF" => DATA <= x"00";
when x"0D0" => DATA <= x"00";
when x"0D1" => DATA <= x"00";
when x"0D2" => DATA <= x"44";
when x"0D3" => DATA <= x"6C";
when x"0D4" => DATA <= x"54";
when x"0D5" => DATA <= x"54";
when x"0D6" => DATA <= x"44";
when x"0D7" => DATA <= x"44";
when x"0D8" => DATA <= x"44";
when x"0D9" => DATA <= x"00";
when x"0DA" => DATA <= x"00";
when x"0DB" => DATA <= x"00";
when x"0DC" => DATA <= x"00";
when x"0DD" => DATA <= x"00";
when x"0DE" => DATA <= x"00";
when x"0DF" => DATA <= x"00";
when x"0E0" => DATA <= x"00";
when x"0E1" => DATA <= x"00";
when x"0E2" => DATA <= x"44";
when x"0E3" => DATA <= x"44";
when x"0E4" => DATA <= x"64";
when x"0E5" => DATA <= x"54";
when x"0E6" => DATA <= x"4C";
when x"0E7" => DATA <= x"44";
when x"0E8" => DATA <= x"44";
when x"0E9" => DATA <= x"00";
when x"0EA" => DATA <= x"00";
when x"0EB" => DATA <= x"00";
when x"0EC" => DATA <= x"00";
when x"0ED" => DATA <= x"00";
when x"0EE" => DATA <= x"00";
when x"0EF" => DATA <= x"00";
when x"0F0" => DATA <= x"00";
when x"0F1" => DATA <= x"00";
when x"0F2" => DATA <= x"38";
when x"0F3" => DATA <= x"44";
when x"0F4" => DATA <= x"44";
when x"0F5" => DATA <= x"44";
when x"0F6" => DATA <= x"44";
when x"0F7" => DATA <= x"44";
when x"0F8" => DATA <= x"38";
when x"0F9" => DATA <= x"00";
when x"0FA" => DATA <= x"00";
when x"0FB" => DATA <= x"00";
when x"0FC" => DATA <= x"00";
when x"0FD" => DATA <= x"00";
when x"0FE" => DATA <= x"00";
when x"0FF" => DATA <= x"00";
when x"100" => DATA <= x"00";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"78";
when x"103" => DATA <= x"44";
when x"104" => DATA <= x"44";
when x"105" => DATA <= x"78";
when x"106" => DATA <= x"40";
when x"107" => DATA <= x"40";
when x"108" => DATA <= x"40";
when x"109" => DATA <= x"00";
when x"10A" => DATA <= x"00";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"00";
when x"10D" => DATA <= x"00";
when x"10E" => DATA <= x"00";
when x"10F" => DATA <= x"00";
when x"110" => DATA <= x"00";
when x"111" => DATA <= x"00";
when x"112" => DATA <= x"38";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"54";
when x"117" => DATA <= x"48";
when x"118" => DATA <= x"34";
when x"119" => DATA <= x"00";
when x"11A" => DATA <= x"00";
when x"11B" => DATA <= x"00";
when x"11C" => DATA <= x"00";
when x"11D" => DATA <= x"00";
when x"11E" => DATA <= x"00";
when x"11F" => DATA <= x"00";
when x"120" => DATA <= x"00";
when x"121" => DATA <= x"00";
when x"122" => DATA <= x"78";
when x"123" => DATA <= x"44";
when x"124" => DATA <= x"44";
when x"125" => DATA <= x"78";
when x"126" => DATA <= x"50";
when x"127" => DATA <= x"48";
when x"128" => DATA <= x"44";
when x"129" => DATA <= x"00";
when x"12A" => DATA <= x"00";
when x"12B" => DATA <= x"00";
when x"12C" => DATA <= x"00";
when x"12D" => DATA <= x"00";
when x"12E" => DATA <= x"00";
when x"12F" => DATA <= x"00";
when x"130" => DATA <= x"00";
when x"131" => DATA <= x"00";
when x"132" => DATA <= x"38";
when x"133" => DATA <= x"44";
when x"134" => DATA <= x"40";
when x"135" => DATA <= x"38";
when x"136" => DATA <= x"04";
when x"137" => DATA <= x"44";
when x"138" => DATA <= x"38";
when x"139" => DATA <= x"00";
when x"13A" => DATA <= x"00";
when x"13B" => DATA <= x"00";
when x"13C" => DATA <= x"00";
when x"13D" => DATA <= x"00";
when x"13E" => DATA <= x"00";
when x"13F" => DATA <= x"00";
when x"140" => DATA <= x"00";
when x"141" => DATA <= x"00";
when x"142" => DATA <= x"7C";
when x"143" => DATA <= x"10";
when x"144" => DATA <= x"10";
when x"145" => DATA <= x"10";
when x"146" => DATA <= x"10";
when x"147" => DATA <= x"10";
when x"148" => DATA <= x"10";
when x"149" => DATA <= x"00";
when x"14A" => DATA <= x"00";
when x"14B" => DATA <= x"00";
when x"14C" => DATA <= x"00";
when x"14D" => DATA <= x"00";
when x"14E" => DATA <= x"00";
when x"14F" => DATA <= x"00";
when x"150" => DATA <= x"00";
when x"151" => DATA <= x"00";
when x"152" => DATA <= x"44";
when x"153" => DATA <= x"44";
when x"154" => DATA <= x"44";
when x"155" => DATA <= x"44";
when x"156" => DATA <= x"44";
when x"157" => DATA <= x"44";
when x"158" => DATA <= x"38";
when x"159" => DATA <= x"00";
when x"15A" => DATA <= x"00";
when x"15B" => DATA <= x"00";
when x"15C" => DATA <= x"00";
when x"15D" => DATA <= x"00";
when x"15E" => DATA <= x"00";
when x"15F" => DATA <= x"00";
when x"160" => DATA <= x"00";
when x"161" => DATA <= x"00";
when x"162" => DATA <= x"44";
when x"163" => DATA <= x"44";
when x"164" => DATA <= x"44";
when x"165" => DATA <= x"28";
when x"166" => DATA <= x"28";
when x"167" => DATA <= x"10";
when x"168" => DATA <= x"10";
when x"169" => DATA <= x"00";
when x"16A" => DATA <= x"00";
when x"16B" => DATA <= x"00";
when x"16C" => DATA <= x"00";
when x"16D" => DATA <= x"00";
when x"16E" => DATA <= x"00";
when x"16F" => DATA <= x"00";
when x"170" => DATA <= x"00";
when x"171" => DATA <= x"00";
when x"172" => DATA <= x"44";
when x"173" => DATA <= x"44";
when x"174" => DATA <= x"44";
when x"175" => DATA <= x"44";
when x"176" => DATA <= x"54";
when x"177" => DATA <= x"6C";
when x"178" => DATA <= x"44";
when x"179" => DATA <= x"00";
when x"17A" => DATA <= x"00";
when x"17B" => DATA <= x"00";
when x"17C" => DATA <= x"00";
when x"17D" => DATA <= x"00";
when x"17E" => DATA <= x"00";
when x"17F" => DATA <= x"00";
when x"180" => DATA <= x"00";
when x"181" => DATA <= x"00";
when x"182" => DATA <= x"44";
when x"183" => DATA <= x"44";
when x"184" => DATA <= x"28";
when x"185" => DATA <= x"10";
when x"186" => DATA <= x"28";
when x"187" => DATA <= x"44";
when x"188" => DATA <= x"44";
when x"189" => DATA <= x"00";
when x"18A" => DATA <= x"00";
when x"18B" => DATA <= x"00";
when x"18C" => DATA <= x"00";
when x"18D" => DATA <= x"00";
when x"18E" => DATA <= x"00";
when x"18F" => DATA <= x"00";
when x"190" => DATA <= x"00";
when x"191" => DATA <= x"00";
when x"192" => DATA <= x"44";
when x"193" => DATA <= x"44";
when x"194" => DATA <= x"28";
when x"195" => DATA <= x"10";
when x"196" => DATA <= x"10";
when x"197" => DATA <= x"10";
when x"198" => DATA <= x"10";
when x"199" => DATA <= x"00";
when x"19A" => DATA <= x"00";
when x"19B" => DATA <= x"00";
when x"19C" => DATA <= x"00";
when x"19D" => DATA <= x"00";
when x"19E" => DATA <= x"00";
when x"19F" => DATA <= x"00";
when x"1A0" => DATA <= x"00";
when x"1A1" => DATA <= x"00";
when x"1A2" => DATA <= x"7C";
when x"1A3" => DATA <= x"04";
when x"1A4" => DATA <= x"08";
when x"1A5" => DATA <= x"10";
when x"1A6" => DATA <= x"20";
when x"1A7" => DATA <= x"40";
when x"1A8" => DATA <= x"7C";
when x"1A9" => DATA <= x"00";
when x"1AA" => DATA <= x"00";
when x"1AB" => DATA <= x"00";
when x"1AC" => DATA <= x"00";
when x"1AD" => DATA <= x"00";
when x"1AE" => DATA <= x"00";
when x"1AF" => DATA <= x"00";
when x"1B0" => DATA <= x"00";
when x"1B1" => DATA <= x"00";
when x"1B2" => DATA <= x"38";
when x"1B3" => DATA <= x"20";
when x"1B4" => DATA <= x"20";
when x"1B5" => DATA <= x"20";
when x"1B6" => DATA <= x"20";
when x"1B7" => DATA <= x"20";
when x"1B8" => DATA <= x"38";
when x"1B9" => DATA <= x"00";
when x"1BA" => DATA <= x"00";
when x"1BB" => DATA <= x"00";
when x"1BC" => DATA <= x"00";
when x"1BD" => DATA <= x"00";
when x"1BE" => DATA <= x"00";
when x"1BF" => DATA <= x"00";
when x"1C0" => DATA <= x"00";
when x"1C1" => DATA <= x"00";
when x"1C2" => DATA <= x"00";
when x"1C3" => DATA <= x"40";
when x"1C4" => DATA <= x"20";
when x"1C5" => DATA <= x"10";
when x"1C6" => DATA <= x"08";
when x"1C7" => DATA <= x"04";
when x"1C8" => DATA <= x"00";
when x"1C9" => DATA <= x"00";
when x"1CA" => DATA <= x"00";
when x"1CB" => DATA <= x"00";
when x"1CC" => DATA <= x"00";
when x"1CD" => DATA <= x"00";
when x"1CE" => DATA <= x"00";
when x"1CF" => DATA <= x"00";
when x"1D0" => DATA <= x"00";
when x"1D1" => DATA <= x"00";
when x"1D2" => DATA <= x"38";
when x"1D3" => DATA <= x"08";
when x"1D4" => DATA <= x"08";
when x"1D5" => DATA <= x"08";
when x"1D6" => DATA <= x"08";
when x"1D7" => DATA <= x"08";
when x"1D8" => DATA <= x"38";
when x"1D9" => DATA <= x"00";
when x"1DA" => DATA <= x"00";
when x"1DB" => DATA <= x"00";
when x"1DC" => DATA <= x"00";
when x"1DD" => DATA <= x"00";
when x"1DE" => DATA <= x"00";
when x"1DF" => DATA <= x"00";
when x"1E0" => DATA <= x"00";
when x"1E1" => DATA <= x"00";
when x"1E2" => DATA <= x"10";
when x"1E3" => DATA <= x"38";
when x"1E4" => DATA <= x"54";
when x"1E5" => DATA <= x"10";
when x"1E6" => DATA <= x"10";
when x"1E7" => DATA <= x"10";
when x"1E8" => DATA <= x"10";
when x"1E9" => DATA <= x"00";
when x"1EA" => DATA <= x"00";
when x"1EB" => DATA <= x"00";
when x"1EC" => DATA <= x"00";
when x"1ED" => DATA <= x"00";
when x"1EE" => DATA <= x"00";
when x"1EF" => DATA <= x"00";
when x"1F0" => DATA <= x"00";
when x"1F1" => DATA <= x"00";
when x"1F2" => DATA <= x"00";
when x"1F3" => DATA <= x"10";
when x"1F4" => DATA <= x"20";
when x"1F5" => DATA <= x"7C";
when x"1F6" => DATA <= x"20";
when x"1F7" => DATA <= x"10";
when x"1F8" => DATA <= x"00";
when x"1F9" => DATA <= x"00";
when x"1FA" => DATA <= x"00";
when x"1FB" => DATA <= x"00";
when x"1FC" => DATA <= x"00";
when x"1FD" => DATA <= x"00";
when x"1FE" => DATA <= x"00";
when x"1FF" => DATA <= x"00";
when x"200" => DATA <= x"00";
when x"201" => DATA <= x"00";
when x"202" => DATA <= x"00";
when x"203" => DATA <= x"00";
when x"204" => DATA <= x"00";
when x"205" => DATA <= x"00";
when x"206" => DATA <= x"00";
when x"207" => DATA <= x"00";
when x"208" => DATA <= x"00";
when x"209" => DATA <= x"00";
when x"20A" => DATA <= x"00";
when x"20B" => DATA <= x"00";
when x"20C" => DATA <= x"00";
when x"20D" => DATA <= x"00";
when x"20E" => DATA <= x"00";
when x"20F" => DATA <= x"00";
when x"210" => DATA <= x"00";
when x"211" => DATA <= x"00";
when x"212" => DATA <= x"10";
when x"213" => DATA <= x"10";
when x"214" => DATA <= x"10";
when x"215" => DATA <= x"10";
when x"216" => DATA <= x"10";
when x"217" => DATA <= x"00";
when x"218" => DATA <= x"10";
when x"219" => DATA <= x"00";
when x"21A" => DATA <= x"00";
when x"21B" => DATA <= x"00";
when x"21C" => DATA <= x"00";
when x"21D" => DATA <= x"00";
when x"21E" => DATA <= x"00";
when x"21F" => DATA <= x"00";
when x"220" => DATA <= x"00";
when x"221" => DATA <= x"00";
when x"222" => DATA <= x"28";
when x"223" => DATA <= x"28";
when x"224" => DATA <= x"28";
when x"225" => DATA <= x"00";
when x"226" => DATA <= x"00";
when x"227" => DATA <= x"00";
when x"228" => DATA <= x"00";
when x"229" => DATA <= x"00";
when x"22A" => DATA <= x"00";
when x"22B" => DATA <= x"00";
when x"22C" => DATA <= x"00";
when x"22D" => DATA <= x"00";
when x"22E" => DATA <= x"00";
when x"22F" => DATA <= x"00";
when x"230" => DATA <= x"00";
when x"231" => DATA <= x"00";
when x"232" => DATA <= x"28";
when x"233" => DATA <= x"28";
when x"234" => DATA <= x"7C";
when x"235" => DATA <= x"28";
when x"236" => DATA <= x"7C";
when x"237" => DATA <= x"28";
when x"238" => DATA <= x"28";
when x"239" => DATA <= x"00";
when x"23A" => DATA <= x"00";
when x"23B" => DATA <= x"00";
when x"23C" => DATA <= x"00";
when x"23D" => DATA <= x"00";
when x"23E" => DATA <= x"00";
when x"23F" => DATA <= x"00";
when x"240" => DATA <= x"00";
when x"241" => DATA <= x"00";
when x"242" => DATA <= x"10";
when x"243" => DATA <= x"3C";
when x"244" => DATA <= x"50";
when x"245" => DATA <= x"38";
when x"246" => DATA <= x"14";
when x"247" => DATA <= x"78";
when x"248" => DATA <= x"10";
when x"249" => DATA <= x"00";
when x"24A" => DATA <= x"00";
when x"24B" => DATA <= x"00";
when x"24C" => DATA <= x"00";
when x"24D" => DATA <= x"00";
when x"24E" => DATA <= x"00";
when x"24F" => DATA <= x"00";
when x"250" => DATA <= x"00";
when x"251" => DATA <= x"00";
when x"252" => DATA <= x"60";
when x"253" => DATA <= x"64";
when x"254" => DATA <= x"08";
when x"255" => DATA <= x"10";
when x"256" => DATA <= x"20";
when x"257" => DATA <= x"4C";
when x"258" => DATA <= x"0C";
when x"259" => DATA <= x"00";
when x"25A" => DATA <= x"00";
when x"25B" => DATA <= x"00";
when x"25C" => DATA <= x"00";
when x"25D" => DATA <= x"00";
when x"25E" => DATA <= x"00";
when x"25F" => DATA <= x"00";
when x"260" => DATA <= x"00";
when x"261" => DATA <= x"00";
when x"262" => DATA <= x"20";
when x"263" => DATA <= x"50";
when x"264" => DATA <= x"50";
when x"265" => DATA <= x"20";
when x"266" => DATA <= x"54";
when x"267" => DATA <= x"48";
when x"268" => DATA <= x"34";
when x"269" => DATA <= x"00";
when x"26A" => DATA <= x"00";
when x"26B" => DATA <= x"00";
when x"26C" => DATA <= x"00";
when x"26D" => DATA <= x"00";
when x"26E" => DATA <= x"00";
when x"26F" => DATA <= x"00";
when x"270" => DATA <= x"00";
when x"271" => DATA <= x"00";
when x"272" => DATA <= x"10";
when x"273" => DATA <= x"10";
when x"274" => DATA <= x"20";
when x"275" => DATA <= x"00";
when x"276" => DATA <= x"00";
when x"277" => DATA <= x"00";
when x"278" => DATA <= x"00";
when x"279" => DATA <= x"00";
when x"27A" => DATA <= x"00";
when x"27B" => DATA <= x"00";
when x"27C" => DATA <= x"00";
when x"27D" => DATA <= x"00";
when x"27E" => DATA <= x"00";
when x"27F" => DATA <= x"00";
when x"280" => DATA <= x"00";
when x"281" => DATA <= x"00";
when x"282" => DATA <= x"08";
when x"283" => DATA <= x"10";
when x"284" => DATA <= x"20";
when x"285" => DATA <= x"20";
when x"286" => DATA <= x"20";
when x"287" => DATA <= x"10";
when x"288" => DATA <= x"08";
when x"289" => DATA <= x"00";
when x"28A" => DATA <= x"00";
when x"28B" => DATA <= x"00";
when x"28C" => DATA <= x"00";
when x"28D" => DATA <= x"00";
when x"28E" => DATA <= x"00";
when x"28F" => DATA <= x"00";
when x"290" => DATA <= x"00";
when x"291" => DATA <= x"00";
when x"292" => DATA <= x"20";
when x"293" => DATA <= x"10";
when x"294" => DATA <= x"08";
when x"295" => DATA <= x"08";
when x"296" => DATA <= x"08";
when x"297" => DATA <= x"10";
when x"298" => DATA <= x"20";
when x"299" => DATA <= x"00";
when x"29A" => DATA <= x"00";
when x"29B" => DATA <= x"00";
when x"29C" => DATA <= x"00";
when x"29D" => DATA <= x"00";
when x"29E" => DATA <= x"00";
when x"29F" => DATA <= x"00";
when x"2A0" => DATA <= x"00";
when x"2A1" => DATA <= x"00";
when x"2A2" => DATA <= x"00";
when x"2A3" => DATA <= x"10";
when x"2A4" => DATA <= x"54";
when x"2A5" => DATA <= x"38";
when x"2A6" => DATA <= x"38";
when x"2A7" => DATA <= x"54";
when x"2A8" => DATA <= x"10";
when x"2A9" => DATA <= x"00";
when x"2AA" => DATA <= x"00";
when x"2AB" => DATA <= x"00";
when x"2AC" => DATA <= x"00";
when x"2AD" => DATA <= x"00";
when x"2AE" => DATA <= x"00";
when x"2AF" => DATA <= x"00";
when x"2B0" => DATA <= x"00";
when x"2B1" => DATA <= x"00";
when x"2B2" => DATA <= x"00";
when x"2B3" => DATA <= x"10";
when x"2B4" => DATA <= x"10";
when x"2B5" => DATA <= x"7C";
when x"2B6" => DATA <= x"10";
when x"2B7" => DATA <= x"10";
when x"2B8" => DATA <= x"00";
when x"2B9" => DATA <= x"00";
when x"2BA" => DATA <= x"00";
when x"2BB" => DATA <= x"00";
when x"2BC" => DATA <= x"00";
when x"2BD" => DATA <= x"00";
when x"2BE" => DATA <= x"00";
when x"2BF" => DATA <= x"00";
when x"2C0" => DATA <= x"00";
when x"2C1" => DATA <= x"00";
when x"2C2" => DATA <= x"00";
when x"2C3" => DATA <= x"00";
when x"2C4" => DATA <= x"00";
when x"2C5" => DATA <= x"00";
when x"2C6" => DATA <= x"00";
when x"2C7" => DATA <= x"20";
when x"2C8" => DATA <= x"20";
when x"2C9" => DATA <= x"40";
when x"2CA" => DATA <= x"00";
when x"2CB" => DATA <= x"00";
when x"2CC" => DATA <= x"00";
when x"2CD" => DATA <= x"00";
when x"2CE" => DATA <= x"00";
when x"2CF" => DATA <= x"00";
when x"2D0" => DATA <= x"00";
when x"2D1" => DATA <= x"00";
when x"2D2" => DATA <= x"00";
when x"2D3" => DATA <= x"00";
when x"2D4" => DATA <= x"00";
when x"2D5" => DATA <= x"7C";
when x"2D6" => DATA <= x"00";
when x"2D7" => DATA <= x"00";
when x"2D8" => DATA <= x"00";
when x"2D9" => DATA <= x"00";
when x"2DA" => DATA <= x"00";
when x"2DB" => DATA <= x"00";
when x"2DC" => DATA <= x"00";
when x"2DD" => DATA <= x"00";
when x"2DE" => DATA <= x"00";
when x"2DF" => DATA <= x"00";
when x"2E0" => DATA <= x"00";
when x"2E1" => DATA <= x"00";
when x"2E2" => DATA <= x"00";
when x"2E3" => DATA <= x"00";
when x"2E4" => DATA <= x"00";
when x"2E5" => DATA <= x"00";
when x"2E6" => DATA <= x"00";
when x"2E7" => DATA <= x"00";
when x"2E8" => DATA <= x"10";
when x"2E9" => DATA <= x"00";
when x"2EA" => DATA <= x"00";
when x"2EB" => DATA <= x"00";
when x"2EC" => DATA <= x"00";
when x"2ED" => DATA <= x"00";
when x"2EE" => DATA <= x"00";
when x"2EF" => DATA <= x"00";
when x"2F0" => DATA <= x"00";
when x"2F1" => DATA <= x"00";
when x"2F2" => DATA <= x"00";
when x"2F3" => DATA <= x"04";
when x"2F4" => DATA <= x"08";
when x"2F5" => DATA <= x"10";
when x"2F6" => DATA <= x"20";
when x"2F7" => DATA <= x"40";
when x"2F8" => DATA <= x"00";
when x"2F9" => DATA <= x"00";
when x"2FA" => DATA <= x"00";
when x"2FB" => DATA <= x"00";
when x"2FC" => DATA <= x"00";
when x"2FD" => DATA <= x"00";
when x"2FE" => DATA <= x"00";
when x"2FF" => DATA <= x"00";
when x"300" => DATA <= x"00";
when x"301" => DATA <= x"00";
when x"302" => DATA <= x"38";
when x"303" => DATA <= x"44";
when x"304" => DATA <= x"4C";
when x"305" => DATA <= x"54";
when x"306" => DATA <= x"64";
when x"307" => DATA <= x"44";
when x"308" => DATA <= x"38";
when x"309" => DATA <= x"00";
when x"30A" => DATA <= x"00";
when x"30B" => DATA <= x"00";
when x"30C" => DATA <= x"00";
when x"30D" => DATA <= x"00";
when x"30E" => DATA <= x"00";
when x"30F" => DATA <= x"00";
when x"310" => DATA <= x"00";
when x"311" => DATA <= x"00";
when x"312" => DATA <= x"10";
when x"313" => DATA <= x"30";
when x"314" => DATA <= x"10";
when x"315" => DATA <= x"10";
when x"316" => DATA <= x"10";
when x"317" => DATA <= x"10";
when x"318" => DATA <= x"38";
when x"319" => DATA <= x"00";
when x"31A" => DATA <= x"00";
when x"31B" => DATA <= x"00";
when x"31C" => DATA <= x"00";
when x"31D" => DATA <= x"00";
when x"31E" => DATA <= x"00";
when x"31F" => DATA <= x"00";
when x"320" => DATA <= x"00";
when x"321" => DATA <= x"00";
when x"322" => DATA <= x"38";
when x"323" => DATA <= x"44";
when x"324" => DATA <= x"04";
when x"325" => DATA <= x"38";
when x"326" => DATA <= x"40";
when x"327" => DATA <= x"40";
when x"328" => DATA <= x"7C";
when x"329" => DATA <= x"00";
when x"32A" => DATA <= x"00";
when x"32B" => DATA <= x"00";
when x"32C" => DATA <= x"00";
when x"32D" => DATA <= x"00";
when x"32E" => DATA <= x"00";
when x"32F" => DATA <= x"00";
when x"330" => DATA <= x"00";
when x"331" => DATA <= x"00";
when x"332" => DATA <= x"38";
when x"333" => DATA <= x"44";
when x"334" => DATA <= x"04";
when x"335" => DATA <= x"08";
when x"336" => DATA <= x"04";
when x"337" => DATA <= x"44";
when x"338" => DATA <= x"38";
when x"339" => DATA <= x"00";
when x"33A" => DATA <= x"00";
when x"33B" => DATA <= x"00";
when x"33C" => DATA <= x"00";
when x"33D" => DATA <= x"00";
when x"33E" => DATA <= x"00";
when x"33F" => DATA <= x"00";
when x"340" => DATA <= x"00";
when x"341" => DATA <= x"00";
when x"342" => DATA <= x"08";
when x"343" => DATA <= x"18";
when x"344" => DATA <= x"28";
when x"345" => DATA <= x"48";
when x"346" => DATA <= x"7C";
when x"347" => DATA <= x"08";
when x"348" => DATA <= x"08";
when x"349" => DATA <= x"00";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"00";
when x"34C" => DATA <= x"00";
when x"34D" => DATA <= x"00";
when x"34E" => DATA <= x"00";
when x"34F" => DATA <= x"00";
when x"350" => DATA <= x"00";
when x"351" => DATA <= x"00";
when x"352" => DATA <= x"7C";
when x"353" => DATA <= x"40";
when x"354" => DATA <= x"78";
when x"355" => DATA <= x"04";
when x"356" => DATA <= x"04";
when x"357" => DATA <= x"44";
when x"358" => DATA <= x"38";
when x"359" => DATA <= x"00";
when x"35A" => DATA <= x"00";
when x"35B" => DATA <= x"00";
when x"35C" => DATA <= x"00";
when x"35D" => DATA <= x"00";
when x"35E" => DATA <= x"00";
when x"35F" => DATA <= x"00";
when x"360" => DATA <= x"00";
when x"361" => DATA <= x"00";
when x"362" => DATA <= x"38";
when x"363" => DATA <= x"40";
when x"364" => DATA <= x"40";
when x"365" => DATA <= x"78";
when x"366" => DATA <= x"44";
when x"367" => DATA <= x"44";
when x"368" => DATA <= x"38";
when x"369" => DATA <= x"00";
when x"36A" => DATA <= x"00";
when x"36B" => DATA <= x"00";
when x"36C" => DATA <= x"00";
when x"36D" => DATA <= x"00";
when x"36E" => DATA <= x"00";
when x"36F" => DATA <= x"00";
when x"370" => DATA <= x"00";
when x"371" => DATA <= x"00";
when x"372" => DATA <= x"7C";
when x"373" => DATA <= x"04";
when x"374" => DATA <= x"08";
when x"375" => DATA <= x"10";
when x"376" => DATA <= x"20";
when x"377" => DATA <= x"40";
when x"378" => DATA <= x"40";
when x"379" => DATA <= x"00";
when x"37A" => DATA <= x"00";
when x"37B" => DATA <= x"00";
when x"37C" => DATA <= x"00";
when x"37D" => DATA <= x"00";
when x"37E" => DATA <= x"00";
when x"37F" => DATA <= x"00";
when x"380" => DATA <= x"00";
when x"381" => DATA <= x"00";
when x"382" => DATA <= x"38";
when x"383" => DATA <= x"44";
when x"384" => DATA <= x"44";
when x"385" => DATA <= x"38";
when x"386" => DATA <= x"44";
when x"387" => DATA <= x"44";
when x"388" => DATA <= x"38";
when x"389" => DATA <= x"00";
when x"38A" => DATA <= x"00";
when x"38B" => DATA <= x"00";
when x"38C" => DATA <= x"00";
when x"38D" => DATA <= x"00";
when x"38E" => DATA <= x"00";
when x"38F" => DATA <= x"00";
when x"390" => DATA <= x"00";
when x"391" => DATA <= x"00";
when x"392" => DATA <= x"38";
when x"393" => DATA <= x"44";
when x"394" => DATA <= x"44";
when x"395" => DATA <= x"3C";
when x"396" => DATA <= x"04";
when x"397" => DATA <= x"04";
when x"398" => DATA <= x"38";
when x"399" => DATA <= x"00";
when x"39A" => DATA <= x"00";
when x"39B" => DATA <= x"00";
when x"39C" => DATA <= x"00";
when x"39D" => DATA <= x"00";
when x"39E" => DATA <= x"00";
when x"39F" => DATA <= x"00";
when x"3A0" => DATA <= x"00";
when x"3A1" => DATA <= x"00";
when x"3A2" => DATA <= x"00";
when x"3A3" => DATA <= x"00";
when x"3A4" => DATA <= x"10";
when x"3A5" => DATA <= x"00";
when x"3A6" => DATA <= x"00";
when x"3A7" => DATA <= x"10";
when x"3A8" => DATA <= x"00";
when x"3A9" => DATA <= x"00";
when x"3AA" => DATA <= x"00";
when x"3AB" => DATA <= x"00";
when x"3AC" => DATA <= x"00";
when x"3AD" => DATA <= x"00";
when x"3AE" => DATA <= x"00";
when x"3AF" => DATA <= x"00";
when x"3B0" => DATA <= x"00";
when x"3B1" => DATA <= x"00";
when x"3B2" => DATA <= x"00";
when x"3B3" => DATA <= x"00";
when x"3B4" => DATA <= x"10";
when x"3B5" => DATA <= x"00";
when x"3B6" => DATA <= x"00";
when x"3B7" => DATA <= x"10";
when x"3B8" => DATA <= x"10";
when x"3B9" => DATA <= x"20";
when x"3BA" => DATA <= x"00";
when x"3BB" => DATA <= x"00";
when x"3BC" => DATA <= x"00";
when x"3BD" => DATA <= x"00";
when x"3BE" => DATA <= x"00";
when x"3BF" => DATA <= x"00";
when x"3C0" => DATA <= x"00";
when x"3C1" => DATA <= x"00";
when x"3C2" => DATA <= x"08";
when x"3C3" => DATA <= x"10";
when x"3C4" => DATA <= x"20";
when x"3C5" => DATA <= x"40";
when x"3C6" => DATA <= x"20";
when x"3C7" => DATA <= x"10";
when x"3C8" => DATA <= x"08";
when x"3C9" => DATA <= x"00";
when x"3CA" => DATA <= x"00";
when x"3CB" => DATA <= x"00";
when x"3CC" => DATA <= x"00";
when x"3CD" => DATA <= x"00";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"00";
when x"3D0" => DATA <= x"00";
when x"3D1" => DATA <= x"00";
when x"3D2" => DATA <= x"00";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"7C";
when x"3D5" => DATA <= x"00";
when x"3D6" => DATA <= x"7C";
when x"3D7" => DATA <= x"00";
when x"3D8" => DATA <= x"00";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"00";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"00";
when x"3DD" => DATA <= x"00";
when x"3DE" => DATA <= x"00";
when x"3DF" => DATA <= x"00";
when x"3E0" => DATA <= x"00";
when x"3E1" => DATA <= x"00";
when x"3E2" => DATA <= x"20";
when x"3E3" => DATA <= x"10";
when x"3E4" => DATA <= x"08";
when x"3E5" => DATA <= x"04";
when x"3E6" => DATA <= x"08";
when x"3E7" => DATA <= x"10";
when x"3E8" => DATA <= x"20";
when x"3E9" => DATA <= x"00";
when x"3EA" => DATA <= x"00";
when x"3EB" => DATA <= x"00";
when x"3EC" => DATA <= x"00";
when x"3ED" => DATA <= x"00";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"00";
when x"3F0" => DATA <= x"00";
when x"3F1" => DATA <= x"00";
when x"3F2" => DATA <= x"38";
when x"3F3" => DATA <= x"44";
when x"3F4" => DATA <= x"04";
when x"3F5" => DATA <= x"08";
when x"3F6" => DATA <= x"10";
when x"3F7" => DATA <= x"00";
when x"3F8" => DATA <= x"10";
when x"3F9" => DATA <= x"00";
when x"3FA" => DATA <= x"00";
when x"3FB" => DATA <= x"00";
when x"3FC" => DATA <= x"00";
when x"3FD" => DATA <= x"00";
when x"3FE" => DATA <= x"00";
when x"3FF" => DATA <= x"00";
when x"400" => DATA <= x"00";
when x"401" => DATA <= x"00";
when x"402" => DATA <= x"10";
when x"403" => DATA <= x"28";
when x"404" => DATA <= x"44";
when x"405" => DATA <= x"00";
when x"406" => DATA <= x"00";
when x"407" => DATA <= x"00";
when x"408" => DATA <= x"00";
when x"409" => DATA <= x"00";
when x"40A" => DATA <= x"00";
when x"40B" => DATA <= x"00";
when x"40C" => DATA <= x"00";
when x"40D" => DATA <= x"00";
when x"40E" => DATA <= x"00";
when x"40F" => DATA <= x"00";
when x"410" => DATA <= x"00";
when x"411" => DATA <= x"00";
when x"412" => DATA <= x"00";
when x"413" => DATA <= x"00";
when x"414" => DATA <= x"38";
when x"415" => DATA <= x"04";
when x"416" => DATA <= x"3C";
when x"417" => DATA <= x"44";
when x"418" => DATA <= x"3C";
when x"419" => DATA <= x"00";
when x"41A" => DATA <= x"00";
when x"41B" => DATA <= x"00";
when x"41C" => DATA <= x"00";
when x"41D" => DATA <= x"00";
when x"41E" => DATA <= x"00";
when x"41F" => DATA <= x"00";
when x"420" => DATA <= x"00";
when x"421" => DATA <= x"00";
when x"422" => DATA <= x"40";
when x"423" => DATA <= x"40";
when x"424" => DATA <= x"58";
when x"425" => DATA <= x"64";
when x"426" => DATA <= x"44";
when x"427" => DATA <= x"64";
when x"428" => DATA <= x"58";
when x"429" => DATA <= x"00";
when x"42A" => DATA <= x"00";
when x"42B" => DATA <= x"00";
when x"42C" => DATA <= x"00";
when x"42D" => DATA <= x"00";
when x"42E" => DATA <= x"00";
when x"42F" => DATA <= x"00";
when x"430" => DATA <= x"00";
when x"431" => DATA <= x"00";
when x"432" => DATA <= x"00";
when x"433" => DATA <= x"00";
when x"434" => DATA <= x"38";
when x"435" => DATA <= x"44";
when x"436" => DATA <= x"40";
when x"437" => DATA <= x"44";
when x"438" => DATA <= x"38";
when x"439" => DATA <= x"00";
when x"43A" => DATA <= x"00";
when x"43B" => DATA <= x"00";
when x"43C" => DATA <= x"00";
when x"43D" => DATA <= x"00";
when x"43E" => DATA <= x"00";
when x"43F" => DATA <= x"00";
when x"440" => DATA <= x"00";
when x"441" => DATA <= x"00";
when x"442" => DATA <= x"04";
when x"443" => DATA <= x"04";
when x"444" => DATA <= x"34";
when x"445" => DATA <= x"4C";
when x"446" => DATA <= x"44";
when x"447" => DATA <= x"4C";
when x"448" => DATA <= x"34";
when x"449" => DATA <= x"00";
when x"44A" => DATA <= x"00";
when x"44B" => DATA <= x"00";
when x"44C" => DATA <= x"00";
when x"44D" => DATA <= x"00";
when x"44E" => DATA <= x"00";
when x"44F" => DATA <= x"00";
when x"450" => DATA <= x"00";
when x"451" => DATA <= x"00";
when x"452" => DATA <= x"00";
when x"453" => DATA <= x"00";
when x"454" => DATA <= x"38";
when x"455" => DATA <= x"44";
when x"456" => DATA <= x"7C";
when x"457" => DATA <= x"40";
when x"458" => DATA <= x"38";
when x"459" => DATA <= x"00";
when x"45A" => DATA <= x"00";
when x"45B" => DATA <= x"00";
when x"45C" => DATA <= x"00";
when x"45D" => DATA <= x"00";
when x"45E" => DATA <= x"00";
when x"45F" => DATA <= x"00";
when x"460" => DATA <= x"00";
when x"461" => DATA <= x"00";
when x"462" => DATA <= x"08";
when x"463" => DATA <= x"14";
when x"464" => DATA <= x"10";
when x"465" => DATA <= x"38";
when x"466" => DATA <= x"10";
when x"467" => DATA <= x"10";
when x"468" => DATA <= x"10";
when x"469" => DATA <= x"00";
when x"46A" => DATA <= x"00";
when x"46B" => DATA <= x"00";
when x"46C" => DATA <= x"00";
when x"46D" => DATA <= x"00";
when x"46E" => DATA <= x"00";
when x"46F" => DATA <= x"00";
when x"470" => DATA <= x"00";
when x"471" => DATA <= x"00";
when x"472" => DATA <= x"00";
when x"473" => DATA <= x"00";
when x"474" => DATA <= x"34";
when x"475" => DATA <= x"4C";
when x"476" => DATA <= x"44";
when x"477" => DATA <= x"4C";
when x"478" => DATA <= x"34";
when x"479" => DATA <= x"04";
when x"47A" => DATA <= x"38";
when x"47B" => DATA <= x"00";
when x"47C" => DATA <= x"00";
when x"47D" => DATA <= x"00";
when x"47E" => DATA <= x"00";
when x"47F" => DATA <= x"00";
when x"480" => DATA <= x"00";
when x"481" => DATA <= x"00";
when x"482" => DATA <= x"40";
when x"483" => DATA <= x"40";
when x"484" => DATA <= x"58";
when x"485" => DATA <= x"64";
when x"486" => DATA <= x"44";
when x"487" => DATA <= x"44";
when x"488" => DATA <= x"44";
when x"489" => DATA <= x"00";
when x"48A" => DATA <= x"00";
when x"48B" => DATA <= x"00";
when x"48C" => DATA <= x"00";
when x"48D" => DATA <= x"00";
when x"48E" => DATA <= x"00";
when x"48F" => DATA <= x"00";
when x"490" => DATA <= x"00";
when x"491" => DATA <= x"00";
when x"492" => DATA <= x"10";
when x"493" => DATA <= x"00";
when x"494" => DATA <= x"30";
when x"495" => DATA <= x"10";
when x"496" => DATA <= x"10";
when x"497" => DATA <= x"10";
when x"498" => DATA <= x"38";
when x"499" => DATA <= x"00";
when x"49A" => DATA <= x"00";
when x"49B" => DATA <= x"00";
when x"49C" => DATA <= x"00";
when x"49D" => DATA <= x"00";
when x"49E" => DATA <= x"00";
when x"49F" => DATA <= x"00";
when x"4A0" => DATA <= x"00";
when x"4A1" => DATA <= x"00";
when x"4A2" => DATA <= x"04";
when x"4A3" => DATA <= x"00";
when x"4A4" => DATA <= x"04";
when x"4A5" => DATA <= x"04";
when x"4A6" => DATA <= x"04";
when x"4A7" => DATA <= x"04";
when x"4A8" => DATA <= x"44";
when x"4A9" => DATA <= x"38";
when x"4AA" => DATA <= x"00";
when x"4AB" => DATA <= x"00";
when x"4AC" => DATA <= x"00";
when x"4AD" => DATA <= x"00";
when x"4AE" => DATA <= x"00";
when x"4AF" => DATA <= x"00";
when x"4B0" => DATA <= x"00";
when x"4B1" => DATA <= x"00";
when x"4B2" => DATA <= x"40";
when x"4B3" => DATA <= x"40";
when x"4B4" => DATA <= x"48";
when x"4B5" => DATA <= x"50";
when x"4B6" => DATA <= x"60";
when x"4B7" => DATA <= x"50";
when x"4B8" => DATA <= x"48";
when x"4B9" => DATA <= x"00";
when x"4BA" => DATA <= x"00";
when x"4BB" => DATA <= x"00";
when x"4BC" => DATA <= x"00";
when x"4BD" => DATA <= x"00";
when x"4BE" => DATA <= x"00";
when x"4BF" => DATA <= x"00";
when x"4C0" => DATA <= x"00";
when x"4C1" => DATA <= x"00";
when x"4C2" => DATA <= x"30";
when x"4C3" => DATA <= x"10";
when x"4C4" => DATA <= x"10";
when x"4C5" => DATA <= x"10";
when x"4C6" => DATA <= x"10";
when x"4C7" => DATA <= x"10";
when x"4C8" => DATA <= x"38";
when x"4C9" => DATA <= x"00";
when x"4CA" => DATA <= x"00";
when x"4CB" => DATA <= x"00";
when x"4CC" => DATA <= x"00";
when x"4CD" => DATA <= x"00";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"00";
when x"4D0" => DATA <= x"00";
when x"4D1" => DATA <= x"00";
when x"4D2" => DATA <= x"00";
when x"4D3" => DATA <= x"00";
when x"4D4" => DATA <= x"78";
when x"4D5" => DATA <= x"54";
when x"4D6" => DATA <= x"54";
when x"4D7" => DATA <= x"54";
when x"4D8" => DATA <= x"54";
when x"4D9" => DATA <= x"00";
when x"4DA" => DATA <= x"00";
when x"4DB" => DATA <= x"00";
when x"4DC" => DATA <= x"00";
when x"4DD" => DATA <= x"00";
when x"4DE" => DATA <= x"00";
when x"4DF" => DATA <= x"00";
when x"4E0" => DATA <= x"00";
when x"4E1" => DATA <= x"00";
when x"4E2" => DATA <= x"00";
when x"4E3" => DATA <= x"00";
when x"4E4" => DATA <= x"58";
when x"4E5" => DATA <= x"64";
when x"4E6" => DATA <= x"44";
when x"4E7" => DATA <= x"44";
when x"4E8" => DATA <= x"44";
when x"4E9" => DATA <= x"00";
when x"4EA" => DATA <= x"00";
when x"4EB" => DATA <= x"00";
when x"4EC" => DATA <= x"00";
when x"4ED" => DATA <= x"00";
when x"4EE" => DATA <= x"00";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"00";
when x"4F1" => DATA <= x"00";
when x"4F2" => DATA <= x"00";
when x"4F3" => DATA <= x"00";
when x"4F4" => DATA <= x"38";
when x"4F5" => DATA <= x"44";
when x"4F6" => DATA <= x"44";
when x"4F7" => DATA <= x"44";
when x"4F8" => DATA <= x"38";
when x"4F9" => DATA <= x"00";
when x"4FA" => DATA <= x"00";
when x"4FB" => DATA <= x"00";
when x"4FC" => DATA <= x"00";
when x"4FD" => DATA <= x"00";
when x"4FE" => DATA <= x"00";
when x"4FF" => DATA <= x"00";
when x"500" => DATA <= x"00";
when x"501" => DATA <= x"00";
when x"502" => DATA <= x"00";
when x"503" => DATA <= x"00";
when x"504" => DATA <= x"78";
when x"505" => DATA <= x"44";
when x"506" => DATA <= x"44";
when x"507" => DATA <= x"44";
when x"508" => DATA <= x"78";
when x"509" => DATA <= x"40";
when x"50A" => DATA <= x"40";
when x"50B" => DATA <= x"00";
when x"50C" => DATA <= x"00";
when x"50D" => DATA <= x"00";
when x"50E" => DATA <= x"00";
when x"50F" => DATA <= x"00";
when x"510" => DATA <= x"00";
when x"511" => DATA <= x"00";
when x"512" => DATA <= x"00";
when x"513" => DATA <= x"00";
when x"514" => DATA <= x"3C";
when x"515" => DATA <= x"44";
when x"516" => DATA <= x"44";
when x"517" => DATA <= x"44";
when x"518" => DATA <= x"3C";
when x"519" => DATA <= x"04";
when x"51A" => DATA <= x"04";
when x"51B" => DATA <= x"00";
when x"51C" => DATA <= x"00";
when x"51D" => DATA <= x"00";
when x"51E" => DATA <= x"00";
when x"51F" => DATA <= x"00";
when x"520" => DATA <= x"00";
when x"521" => DATA <= x"00";
when x"522" => DATA <= x"00";
when x"523" => DATA <= x"00";
when x"524" => DATA <= x"58";
when x"525" => DATA <= x"64";
when x"526" => DATA <= x"40";
when x"527" => DATA <= x"40";
when x"528" => DATA <= x"40";
when x"529" => DATA <= x"00";
when x"52A" => DATA <= x"00";
when x"52B" => DATA <= x"00";
when x"52C" => DATA <= x"00";
when x"52D" => DATA <= x"00";
when x"52E" => DATA <= x"00";
when x"52F" => DATA <= x"00";
when x"530" => DATA <= x"00";
when x"531" => DATA <= x"00";
when x"532" => DATA <= x"00";
when x"533" => DATA <= x"00";
when x"534" => DATA <= x"3C";
when x"535" => DATA <= x"40";
when x"536" => DATA <= x"38";
when x"537" => DATA <= x"04";
when x"538" => DATA <= x"78";
when x"539" => DATA <= x"00";
when x"53A" => DATA <= x"00";
when x"53B" => DATA <= x"00";
when x"53C" => DATA <= x"00";
when x"53D" => DATA <= x"00";
when x"53E" => DATA <= x"00";
when x"53F" => DATA <= x"00";
when x"540" => DATA <= x"00";
when x"541" => DATA <= x"00";
when x"542" => DATA <= x"20";
when x"543" => DATA <= x"20";
when x"544" => DATA <= x"70";
when x"545" => DATA <= x"20";
when x"546" => DATA <= x"20";
when x"547" => DATA <= x"24";
when x"548" => DATA <= x"18";
when x"549" => DATA <= x"00";
when x"54A" => DATA <= x"00";
when x"54B" => DATA <= x"00";
when x"54C" => DATA <= x"00";
when x"54D" => DATA <= x"00";
when x"54E" => DATA <= x"00";
when x"54F" => DATA <= x"00";
when x"550" => DATA <= x"00";
when x"551" => DATA <= x"00";
when x"552" => DATA <= x"00";
when x"553" => DATA <= x"00";
when x"554" => DATA <= x"44";
when x"555" => DATA <= x"44";
when x"556" => DATA <= x"44";
when x"557" => DATA <= x"4C";
when x"558" => DATA <= x"34";
when x"559" => DATA <= x"00";
when x"55A" => DATA <= x"00";
when x"55B" => DATA <= x"00";
when x"55C" => DATA <= x"00";
when x"55D" => DATA <= x"00";
when x"55E" => DATA <= x"00";
when x"55F" => DATA <= x"00";
when x"560" => DATA <= x"00";
when x"561" => DATA <= x"00";
when x"562" => DATA <= x"00";
when x"563" => DATA <= x"00";
when x"564" => DATA <= x"44";
when x"565" => DATA <= x"44";
when x"566" => DATA <= x"44";
when x"567" => DATA <= x"28";
when x"568" => DATA <= x"10";
when x"569" => DATA <= x"00";
when x"56A" => DATA <= x"00";
when x"56B" => DATA <= x"00";
when x"56C" => DATA <= x"00";
when x"56D" => DATA <= x"00";
when x"56E" => DATA <= x"00";
when x"56F" => DATA <= x"00";
when x"570" => DATA <= x"00";
when x"571" => DATA <= x"00";
when x"572" => DATA <= x"00";
when x"573" => DATA <= x"00";
when x"574" => DATA <= x"44";
when x"575" => DATA <= x"54";
when x"576" => DATA <= x"54";
when x"577" => DATA <= x"28";
when x"578" => DATA <= x"28";
when x"579" => DATA <= x"00";
when x"57A" => DATA <= x"00";
when x"57B" => DATA <= x"00";
when x"57C" => DATA <= x"00";
when x"57D" => DATA <= x"00";
when x"57E" => DATA <= x"00";
when x"57F" => DATA <= x"00";
when x"580" => DATA <= x"00";
when x"581" => DATA <= x"00";
when x"582" => DATA <= x"00";
when x"583" => DATA <= x"00";
when x"584" => DATA <= x"44";
when x"585" => DATA <= x"28";
when x"586" => DATA <= x"10";
when x"587" => DATA <= x"28";
when x"588" => DATA <= x"44";
when x"589" => DATA <= x"00";
when x"58A" => DATA <= x"00";
when x"58B" => DATA <= x"00";
when x"58C" => DATA <= x"00";
when x"58D" => DATA <= x"00";
when x"58E" => DATA <= x"00";
when x"58F" => DATA <= x"00";
when x"590" => DATA <= x"00";
when x"591" => DATA <= x"00";
when x"592" => DATA <= x"00";
when x"593" => DATA <= x"00";
when x"594" => DATA <= x"44";
when x"595" => DATA <= x"44";
when x"596" => DATA <= x"44";
when x"597" => DATA <= x"3C";
when x"598" => DATA <= x"04";
when x"599" => DATA <= x"38";
when x"59A" => DATA <= x"00";
when x"59B" => DATA <= x"00";
when x"59C" => DATA <= x"00";
when x"59D" => DATA <= x"00";
when x"59E" => DATA <= x"00";
when x"59F" => DATA <= x"00";
when x"5A0" => DATA <= x"00";
when x"5A1" => DATA <= x"00";
when x"5A2" => DATA <= x"00";
when x"5A3" => DATA <= x"00";
when x"5A4" => DATA <= x"7C";
when x"5A5" => DATA <= x"08";
when x"5A6" => DATA <= x"10";
when x"5A7" => DATA <= x"20";
when x"5A8" => DATA <= x"7C";
when x"5A9" => DATA <= x"00";
when x"5AA" => DATA <= x"00";
when x"5AB" => DATA <= x"00";
when x"5AC" => DATA <= x"00";
when x"5AD" => DATA <= x"00";
when x"5AE" => DATA <= x"00";
when x"5AF" => DATA <= x"00";
when x"5B0" => DATA <= x"00";
when x"5B1" => DATA <= x"00";
when x"5B2" => DATA <= x"08";
when x"5B3" => DATA <= x"10";
when x"5B4" => DATA <= x"10";
when x"5B5" => DATA <= x"20";
when x"5B6" => DATA <= x"10";
when x"5B7" => DATA <= x"10";
when x"5B8" => DATA <= x"08";
when x"5B9" => DATA <= x"00";
when x"5BA" => DATA <= x"00";
when x"5BB" => DATA <= x"00";
when x"5BC" => DATA <= x"00";
when x"5BD" => DATA <= x"00";
when x"5BE" => DATA <= x"00";
when x"5BF" => DATA <= x"00";
when x"5C0" => DATA <= x"00";
when x"5C1" => DATA <= x"00";
when x"5C2" => DATA <= x"10";
when x"5C3" => DATA <= x"10";
when x"5C4" => DATA <= x"10";
when x"5C5" => DATA <= x"00";
when x"5C6" => DATA <= x"10";
when x"5C7" => DATA <= x"10";
when x"5C8" => DATA <= x"10";
when x"5C9" => DATA <= x"00";
when x"5CA" => DATA <= x"00";
when x"5CB" => DATA <= x"00";
when x"5CC" => DATA <= x"00";
when x"5CD" => DATA <= x"00";
when x"5CE" => DATA <= x"00";
when x"5CF" => DATA <= x"00";
when x"5D0" => DATA <= x"00";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"20";
when x"5D3" => DATA <= x"10";
when x"5D4" => DATA <= x"10";
when x"5D5" => DATA <= x"08";
when x"5D6" => DATA <= x"10";
when x"5D7" => DATA <= x"10";
when x"5D8" => DATA <= x"20";
when x"5D9" => DATA <= x"00";
when x"5DA" => DATA <= x"00";
when x"5DB" => DATA <= x"00";
when x"5DC" => DATA <= x"00";
when x"5DD" => DATA <= x"00";
when x"5DE" => DATA <= x"00";
when x"5DF" => DATA <= x"00";
when x"5E0" => DATA <= x"00";
when x"5E1" => DATA <= x"00";
when x"5E2" => DATA <= x"20";
when x"5E3" => DATA <= x"54";
when x"5E4" => DATA <= x"08";
when x"5E5" => DATA <= x"00";
when x"5E6" => DATA <= x"00";
when x"5E7" => DATA <= x"00";
when x"5E8" => DATA <= x"00";
when x"5E9" => DATA <= x"00";
when x"5EA" => DATA <= x"00";
when x"5EB" => DATA <= x"00";
when x"5EC" => DATA <= x"00";
when x"5ED" => DATA <= x"00";
when x"5EE" => DATA <= x"00";
when x"5EF" => DATA <= x"00";
when x"5F0" => DATA <= x"00";
when x"5F1" => DATA <= x"00";
when x"5F2" => DATA <= x"00";
when x"5F3" => DATA <= x"00";
when x"5F4" => DATA <= x"00";
when x"5F5" => DATA <= x"00";
when x"5F6" => DATA <= x"00";
when x"5F7" => DATA <= x"00";
when x"5F8" => DATA <= x"7C";
when x"5F9" => DATA <= x"00";
when x"5FA" => DATA <= x"00";
when x"5FB" => DATA <= x"00";
when x"5FC" => DATA <= x"00";
when x"5FD" => DATA <= x"00";
when x"5FE" => DATA <= x"00";
when x"5FF" => DATA <= x"00";
when x"600" => DATA <= x"00";
when x"601" => DATA <= x"00";
when x"602" => DATA <= x"00";
when x"603" => DATA <= x"00";
when x"604" => DATA <= x"00";
when x"605" => DATA <= x"00";
when x"606" => DATA <= x"00";
when x"607" => DATA <= x"00";
when x"608" => DATA <= x"00";
when x"609" => DATA <= x"00";
when x"60A" => DATA <= x"00";
when x"60B" => DATA <= x"00";
when x"60C" => DATA <= x"00";
when x"60D" => DATA <= x"00";
when x"60E" => DATA <= x"00";
when x"60F" => DATA <= x"00";
when x"610" => DATA <= x"00";
when x"611" => DATA <= x"00";
when x"612" => DATA <= x"00";
when x"613" => DATA <= x"08";
when x"614" => DATA <= x"00";
when x"615" => DATA <= x"08";
when x"616" => DATA <= x"08";
when x"617" => DATA <= x"08";
when x"618" => DATA <= x"08";
when x"619" => DATA <= x"08";
when x"61A" => DATA <= x"00";
when x"61B" => DATA <= x"00";
when x"61C" => DATA <= x"00";
when x"61D" => DATA <= x"00";
when x"61E" => DATA <= x"00";
when x"61F" => DATA <= x"00";
when x"620" => DATA <= x"00";
when x"621" => DATA <= x"00";
when x"622" => DATA <= x"00";
when x"623" => DATA <= x"00";
when x"624" => DATA <= x"08";
when x"625" => DATA <= x"1C";
when x"626" => DATA <= x"20";
when x"627" => DATA <= x"20";
when x"628" => DATA <= x"20";
when x"629" => DATA <= x"1C";
when x"62A" => DATA <= x"08";
when x"62B" => DATA <= x"00";
when x"62C" => DATA <= x"00";
when x"62D" => DATA <= x"00";
when x"62E" => DATA <= x"00";
when x"62F" => DATA <= x"00";
when x"630" => DATA <= x"00";
when x"631" => DATA <= x"00";
when x"632" => DATA <= x"00";
when x"633" => DATA <= x"0C";
when x"634" => DATA <= x"12";
when x"635" => DATA <= x"10";
when x"636" => DATA <= x"38";
when x"637" => DATA <= x"10";
when x"638" => DATA <= x"10";
when x"639" => DATA <= x"3E";
when x"63A" => DATA <= x"00";
when x"63B" => DATA <= x"00";
when x"63C" => DATA <= x"00";
when x"63D" => DATA <= x"00";
when x"63E" => DATA <= x"00";
when x"63F" => DATA <= x"00";
when x"640" => DATA <= x"00";
when x"641" => DATA <= x"00";
when x"642" => DATA <= x"00";
when x"643" => DATA <= x"00";
when x"644" => DATA <= x"00";
when x"645" => DATA <= x"22";
when x"646" => DATA <= x"1C";
when x"647" => DATA <= x"14";
when x"648" => DATA <= x"1C";
when x"649" => DATA <= x"22";
when x"64A" => DATA <= x"00";
when x"64B" => DATA <= x"00";
when x"64C" => DATA <= x"00";
when x"64D" => DATA <= x"00";
when x"64E" => DATA <= x"00";
when x"64F" => DATA <= x"00";
when x"650" => DATA <= x"00";
when x"651" => DATA <= x"00";
when x"652" => DATA <= x"00";
when x"653" => DATA <= x"22";
when x"654" => DATA <= x"14";
when x"655" => DATA <= x"08";
when x"656" => DATA <= x"3E";
when x"657" => DATA <= x"08";
when x"658" => DATA <= x"3E";
when x"659" => DATA <= x"08";
when x"65A" => DATA <= x"00";
when x"65B" => DATA <= x"00";
when x"65C" => DATA <= x"00";
when x"65D" => DATA <= x"00";
when x"65E" => DATA <= x"00";
when x"65F" => DATA <= x"00";
when x"660" => DATA <= x"00";
when x"661" => DATA <= x"00";
when x"662" => DATA <= x"00";
when x"663" => DATA <= x"08";
when x"664" => DATA <= x"08";
when x"665" => DATA <= x"08";
when x"666" => DATA <= x"00";
when x"667" => DATA <= x"08";
when x"668" => DATA <= x"08";
when x"669" => DATA <= x"08";
when x"66A" => DATA <= x"00";
when x"66B" => DATA <= x"00";
when x"66C" => DATA <= x"00";
when x"66D" => DATA <= x"00";
when x"66E" => DATA <= x"00";
when x"66F" => DATA <= x"00";
when x"670" => DATA <= x"00";
when x"671" => DATA <= x"00";
when x"672" => DATA <= x"00";
when x"673" => DATA <= x"1C";
when x"674" => DATA <= x"20";
when x"675" => DATA <= x"1C";
when x"676" => DATA <= x"22";
when x"677" => DATA <= x"1C";
when x"678" => DATA <= x"02";
when x"679" => DATA <= x"1C";
when x"67A" => DATA <= x"00";
when x"67B" => DATA <= x"00";
when x"67C" => DATA <= x"00";
when x"67D" => DATA <= x"00";
when x"67E" => DATA <= x"00";
when x"67F" => DATA <= x"00";
when x"680" => DATA <= x"14";
when x"681" => DATA <= x"14";
when x"682" => DATA <= x"00";
when x"683" => DATA <= x"00";
when x"684" => DATA <= x"00";
when x"685" => DATA <= x"00";
when x"686" => DATA <= x"00";
when x"687" => DATA <= x"00";
when x"688" => DATA <= x"00";
when x"689" => DATA <= x"00";
when x"68A" => DATA <= x"00";
when x"68B" => DATA <= x"00";
when x"68C" => DATA <= x"00";
when x"68D" => DATA <= x"00";
when x"68E" => DATA <= x"00";
when x"68F" => DATA <= x"00";
when x"690" => DATA <= x"00";
when x"691" => DATA <= x"00";
when x"692" => DATA <= x"3E";
when x"693" => DATA <= x"41";
when x"694" => DATA <= x"5D";
when x"695" => DATA <= x"51";
when x"696" => DATA <= x"51";
when x"697" => DATA <= x"5D";
when x"698" => DATA <= x"41";
when x"699" => DATA <= x"3E";
when x"69A" => DATA <= x"00";
when x"69B" => DATA <= x"00";
when x"69C" => DATA <= x"00";
when x"69D" => DATA <= x"00";
when x"69E" => DATA <= x"00";
when x"69F" => DATA <= x"00";
when x"6A0" => DATA <= x"00";
when x"6A1" => DATA <= x"00";
when x"6A2" => DATA <= x"00";
when x"6A3" => DATA <= x"1C";
when x"6A4" => DATA <= x"02";
when x"6A5" => DATA <= x"1E";
when x"6A6" => DATA <= x"22";
when x"6A7" => DATA <= x"1E";
when x"6A8" => DATA <= x"00";
when x"6A9" => DATA <= x"00";
when x"6AA" => DATA <= x"00";
when x"6AB" => DATA <= x"00";
when x"6AC" => DATA <= x"00";
when x"6AD" => DATA <= x"00";
when x"6AE" => DATA <= x"00";
when x"6AF" => DATA <= x"00";
when x"6B0" => DATA <= x"00";
when x"6B1" => DATA <= x"00";
when x"6B2" => DATA <= x"00";
when x"6B3" => DATA <= x"00";
when x"6B4" => DATA <= x"0A";
when x"6B5" => DATA <= x"14";
when x"6B6" => DATA <= x"28";
when x"6B7" => DATA <= x"14";
when x"6B8" => DATA <= x"0A";
when x"6B9" => DATA <= x"00";
when x"6BA" => DATA <= x"00";
when x"6BB" => DATA <= x"00";
when x"6BC" => DATA <= x"00";
when x"6BD" => DATA <= x"00";
when x"6BE" => DATA <= x"00";
when x"6BF" => DATA <= x"00";
when x"6C0" => DATA <= x"00";
when x"6C1" => DATA <= x"00";
when x"6C2" => DATA <= x"00";
when x"6C3" => DATA <= x"00";
when x"6C4" => DATA <= x"00";
when x"6C5" => DATA <= x"00";
when x"6C6" => DATA <= x"3E";
when x"6C7" => DATA <= x"02";
when x"6C8" => DATA <= x"02";
when x"6C9" => DATA <= x"00";
when x"6CA" => DATA <= x"00";
when x"6CB" => DATA <= x"00";
when x"6CC" => DATA <= x"00";
when x"6CD" => DATA <= x"00";
when x"6CE" => DATA <= x"00";
when x"6CF" => DATA <= x"00";
when x"6D0" => DATA <= x"00";
when x"6D1" => DATA <= x"00";
when x"6D2" => DATA <= x"00";
when x"6D3" => DATA <= x"00";
when x"6D4" => DATA <= x"00";
when x"6D5" => DATA <= x"00";
when x"6D6" => DATA <= x"3E";
when x"6D7" => DATA <= x"00";
when x"6D8" => DATA <= x"00";
when x"6D9" => DATA <= x"00";
when x"6DA" => DATA <= x"00";
when x"6DB" => DATA <= x"00";
when x"6DC" => DATA <= x"00";
when x"6DD" => DATA <= x"00";
when x"6DE" => DATA <= x"00";
when x"6DF" => DATA <= x"00";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"3E";
when x"6E3" => DATA <= x"41";
when x"6E4" => DATA <= x"5D";
when x"6E5" => DATA <= x"55";
when x"6E6" => DATA <= x"59";
when x"6E7" => DATA <= x"55";
when x"6E8" => DATA <= x"41";
when x"6E9" => DATA <= x"3E";
when x"6EA" => DATA <= x"00";
when x"6EB" => DATA <= x"00";
when x"6EC" => DATA <= x"00";
when x"6ED" => DATA <= x"00";
when x"6EE" => DATA <= x"00";
when x"6EF" => DATA <= x"00";
when x"6F0" => DATA <= x"00";
when x"6F1" => DATA <= x"00";
when x"6F2" => DATA <= x"00";
when x"6F3" => DATA <= x"7E";
when x"6F4" => DATA <= x"00";
when x"6F5" => DATA <= x"00";
when x"6F6" => DATA <= x"00";
when x"6F7" => DATA <= x"00";
when x"6F8" => DATA <= x"00";
when x"6F9" => DATA <= x"00";
when x"6FA" => DATA <= x"00";
when x"6FB" => DATA <= x"00";
when x"6FC" => DATA <= x"00";
when x"6FD" => DATA <= x"00";
when x"6FE" => DATA <= x"00";
when x"6FF" => DATA <= x"00";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"10";
when x"704" => DATA <= x"28";
when x"705" => DATA <= x"10";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"08";
when x"713" => DATA <= x"08";
when x"714" => DATA <= x"3E";
when x"715" => DATA <= x"08";
when x"716" => DATA <= x"08";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"3E";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"18";
when x"724" => DATA <= x"04";
when x"725" => DATA <= x"08";
when x"726" => DATA <= x"10";
when x"727" => DATA <= x"1C";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"18";
when x"734" => DATA <= x"04";
when x"735" => DATA <= x"18";
when x"736" => DATA <= x"04";
when x"737" => DATA <= x"18";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"04";
when x"741" => DATA <= x"08";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"12";
when x"756" => DATA <= x"12";
when x"757" => DATA <= x"12";
when x"758" => DATA <= x"12";
when x"759" => DATA <= x"1C";
when x"75A" => DATA <= x"10";
when x"75B" => DATA <= x"20";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"1A";
when x"764" => DATA <= x"2A";
when x"765" => DATA <= x"2A";
when x"766" => DATA <= x"1A";
when x"767" => DATA <= x"0A";
when x"768" => DATA <= x"0A";
when x"769" => DATA <= x"0A";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"18";
when x"777" => DATA <= x"18";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"00";
when x"783" => DATA <= x"00";
when x"784" => DATA <= x"00";
when x"785" => DATA <= x"00";
when x"786" => DATA <= x"00";
when x"787" => DATA <= x"00";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"04";
when x"78B" => DATA <= x"18";
when x"78C" => DATA <= x"00";
when x"78D" => DATA <= x"00";
when x"78E" => DATA <= x"00";
when x"78F" => DATA <= x"00";
when x"790" => DATA <= x"00";
when x"791" => DATA <= x"00";
when x"792" => DATA <= x"00";
when x"793" => DATA <= x"08";
when x"794" => DATA <= x"18";
when x"795" => DATA <= x"08";
when x"796" => DATA <= x"08";
when x"797" => DATA <= x"1C";
when x"798" => DATA <= x"00";
when x"799" => DATA <= x"00";
when x"79A" => DATA <= x"00";
when x"79B" => DATA <= x"00";
when x"79C" => DATA <= x"00";
when x"79D" => DATA <= x"00";
when x"79E" => DATA <= x"00";
when x"79F" => DATA <= x"00";
when x"7A0" => DATA <= x"00";
when x"7A1" => DATA <= x"00";
when x"7A2" => DATA <= x"00";
when x"7A3" => DATA <= x"1C";
when x"7A4" => DATA <= x"22";
when x"7A5" => DATA <= x"22";
when x"7A6" => DATA <= x"22";
when x"7A7" => DATA <= x"1C";
when x"7A8" => DATA <= x"00";
when x"7A9" => DATA <= x"00";
when x"7AA" => DATA <= x"00";
when x"7AB" => DATA <= x"00";
when x"7AC" => DATA <= x"00";
when x"7AD" => DATA <= x"00";
when x"7AE" => DATA <= x"00";
when x"7AF" => DATA <= x"00";
when x"7B0" => DATA <= x"00";
when x"7B1" => DATA <= x"00";
when x"7B2" => DATA <= x"00";
when x"7B3" => DATA <= x"00";
when x"7B4" => DATA <= x"28";
when x"7B5" => DATA <= x"14";
when x"7B6" => DATA <= x"0A";
when x"7B7" => DATA <= x"14";
when x"7B8" => DATA <= x"28";
when x"7B9" => DATA <= x"00";
when x"7BA" => DATA <= x"00";
when x"7BB" => DATA <= x"00";
when x"7BC" => DATA <= x"00";
when x"7BD" => DATA <= x"00";
when x"7BE" => DATA <= x"00";
when x"7BF" => DATA <= x"00";
when x"7C0" => DATA <= x"00";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"00";
when x"7C3" => DATA <= x"20";
when x"7C4" => DATA <= x"20";
when x"7C5" => DATA <= x"20";
when x"7C6" => DATA <= x"22";
when x"7C7" => DATA <= x"06";
when x"7C8" => DATA <= x"0E";
when x"7C9" => DATA <= x"02";
when x"7CA" => DATA <= x"00";
when x"7CB" => DATA <= x"00";
when x"7CC" => DATA <= x"00";
when x"7CD" => DATA <= x"00";
when x"7CE" => DATA <= x"00";
when x"7CF" => DATA <= x"00";
when x"7D0" => DATA <= x"00";
when x"7D1" => DATA <= x"00";
when x"7D2" => DATA <= x"00";
when x"7D3" => DATA <= x"20";
when x"7D4" => DATA <= x"20";
when x"7D5" => DATA <= x"20";
when x"7D6" => DATA <= x"2E";
when x"7D7" => DATA <= x"02";
when x"7D8" => DATA <= x"04";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"00";
when x"7DB" => DATA <= x"00";
when x"7DC" => DATA <= x"00";
when x"7DD" => DATA <= x"00";
when x"7DE" => DATA <= x"00";
when x"7DF" => DATA <= x"00";
when x"7E0" => DATA <= x"00";
when x"7E1" => DATA <= x"00";
when x"7E2" => DATA <= x"00";
when x"7E3" => DATA <= x"70";
when x"7E4" => DATA <= x"10";
when x"7E5" => DATA <= x"70";
when x"7E6" => DATA <= x"12";
when x"7E7" => DATA <= x"76";
when x"7E8" => DATA <= x"0E";
when x"7E9" => DATA <= x"02";
when x"7EA" => DATA <= x"00";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"00";
when x"7ED" => DATA <= x"00";
when x"7EE" => DATA <= x"00";
when x"7EF" => DATA <= x"00";
when x"7F0" => DATA <= x"00";
when x"7F1" => DATA <= x"00";
when x"7F2" => DATA <= x"00";
when x"7F3" => DATA <= x"08";
when x"7F4" => DATA <= x"00";
when x"7F5" => DATA <= x"08";
when x"7F6" => DATA <= x"08";
when x"7F7" => DATA <= x"10";
when x"7F8" => DATA <= x"12";
when x"7F9" => DATA <= x"0C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| apache-2.0 | 7285ef6cf5c97d8b0d45f10e48309348 | 0.418944 | 2.596989 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_4096/synth/bram_4096.vhd | 1 | 14,430 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_4096 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_4096;
ARCHITECTURE bram_4096_arch OF bram_4096 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_4096_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_4096_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_4096_arch : ARCHITECTURE IS "bram_4096,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_4096_arch: ARCHITECTURE IS "bram_4096,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_4096.mif,C_" &
"INIT_FILE=bram_4096.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DEPTH_B=" &
"4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=1,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_" &
"BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.3587 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_4096.mif",
C_INIT_FILE => "bram_4096.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 1,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.3587 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_4096_arch;
| unlicense | 5be5d26baec9cd674b54221dc62613bd | 0.62571 | 3.01946 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00695.vhd | 1 | 5,439 | -- NEED RESULT: ARCH00695: Type conversions in assoc. lists with out interface objects passed
-- NEED RESULT: ARCH00695: Type conversions in assoc. lists with out interface objects passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00695
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (1)
-- 4.3.3.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00695
-- PKG00695/BODY
-- ENT00695(ARCH00695)
-- ENT00695_Test_Bench(ARCH00695_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
package PKG00695 is
function fintegertointeger ( P : integer ) return integer ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 ;
end PKG00695 ;
--
package body PKG00695 is
function fintegertointeger ( P : integer ) return integer is
begin
if P = c_integer_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector is
begin
if P = c_integer_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer is
begin
if P = c_st_bit_vector_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 is
begin
if P = c_st_bit_vector_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector is
begin
if P = c_st_arr3_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean is
begin
if P = c_st_arr3_1 then
return c_boolean_1 ;
else
return c_boolean_2 ;
end if ;
end ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 is
begin
if P = c_boolean_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
end PKG00695 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00695.all ;
entity ENT00695 is
port (
signal s_st_arr3 : out st_arr3 ;
signal s2_integer : out integer
) ;
end ENT00695 ;
--
architecture ARCH00695 of ENT00695 is
procedure p1 (
variable v_boolean : out boolean ;
variable v2_integer : out integer
) is
variable correct : boolean := true ;
begin
v_boolean := c_boolean_2 ;
end p1 ;
begin
process
variable v_st_arr3 : st_arr3 ;
variable v2_integer : integer ;
begin
p1 (
fbooleantost_arr3
( v_boolean ) =>
v_st_arr3 ,
v2_integer =>
v2_integer
) ;
s_st_arr3 <= v_st_arr3 ;
s2_integer <= v2_integer ;
wait ;
end process ;
end ARCH00695 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00695.all ;
entity ENT00695_Test_Bench is
end ENT00695_Test_Bench ;
--
architecture ARCH00695_Test_Bench of ENT00695_Test_Bench is
begin
L1:
block
signal s_integer : integer := c_integer_1 ;
signal s2_integer : integer := c_integer_2 ;
signal toggle : boolean := false ;
component UUT
port (
signal s_st_bit_vector : out st_bit_vector ;
signal s2_integer : out integer
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00695 ( ARCH00695 )
port map (
fst_arr3tost_bit_vector
( s_st_arr3 ) =>
s_st_bit_vector ,
s2_integer =>
s2_integer
) ;
begin
toggle <= true ;
CIS1 : UUT
port map (
fst_bit_vectortointeger
( s_st_bit_vector ) =>
s_integer ,
s2_integer =>
s2_integer
) ;
process ( s2_integer, s_integer, toggle)
variable correct : boolean := true ;
begin
if toggle then
correct := correct and s_integer = c_integer_2 ;
test_report ( "ARCH00695" ,
"Type conversions in assoc. lists with out interface objects" ,
correct ) ;
end if ;
end process ;
end block L1 ;
end ARCH00695_Test_Bench ;
--
| gpl-3.0 | 54c81d736ac6e3ae40b6b5b617ea3157 | 0.523626 | 3.524951 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/DCM/DCMSID0.vhd | 1 | 2,038 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCMSID0;
architecture BEHAVIORAL of DCMSID0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 709d9bdb12ec55d50810fd40b126cf12 | 0.406281 | 4.308668 | false | false | false | false |
rauenzi/VHDL-Communications | SequenceController.vhd | 1 | 2,395 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 11/2/14
--
--Description: This is a sequence controller that uses three buttons as
-- reset, reverse and a system enable. Using the clock this sytem will
-- generate an address for a ROM. However, this can be easily
-- modified in order to create what is needed
--
--Version: 2.1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SequenceController is
Generic (NumOfSequences : integer := 8;
DesiredDisplaySpeed : integer := 100000;
InputClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Enabler : in std_logic;
Reset : in std_logic;
Reverse : in std_logic;
MemAddress : out integer := 0);
end SequenceController;
architecture Behavioral of SequenceController is
signal clkMax : integer := InputClockSpeed/DesiredDisplaySpeed;
signal clkCnt : integer := 0;
signal displayCnt : integer := 0;
signal StateEnable : std_logic;
begin
DisplaySpeed: process(ClockState)
begin
if rising_edge(ClockState) then
if Reset <= '0' then
if clkCnt = clkMax then
StateEnable <= '1';
clkCnt <= 0;
else
clkCnt<=clkCnt+1;
StateEnable <= '0';
end if;
else
clkCnt<=0;
end if;
end if;
end process DisplaySpeed;
count: process(ClockState,StateEnable,Enabler,Reverse,Reset)
begin
if Reset='1' then
displayCnt <= 0;
else
if Enabler = '1' then
if rising_edge(ClockState) AND StateEnable = '1' then
if Reverse = '0' then
if displayCnt = NumOfSequences then
displayCnt <= 0;
else
displayCnt <= displayCnt + 1;
end if;
else
if displayCnt = 0 then
displayCnt <= NumOfSequences;
else
displayCnt <= displayCnt - 1;
end if;
end if;
end if;
end if;
end if;
MemAddress<=displayCnt;
end process count;
end Behavioral;
| apache-2.0 | 4e6e658f0d0b52d1bef9e9ef222b7209 | 0.516075 | 4.641473 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/sample_buffer_if_plb_master_if.vhd | 4 | 36,941 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if_plb_master_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 | 83364d78b9eb0e17596ab8658028837b | 0.53442 | 3.319644 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00475.vhd | 1 | 2,838 | -- NEED RESULT: ARCH00475: Aggregates may have one or many element associations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00475
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2 (1)
-- 7.3.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00475)
-- ENT00475_Test_Bench(ARCH00475_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00475 of E00000 is
type rec_1 is record
f1 : integer ;
f2 : boolean ;
f3 : real ;
end record ;
type rec_2 is record
f1 : integer ;
end record ;
type arr_1 is array ( integer range <> ) of rec_1 ;
begin
process
variable v_int1 : integer := 10 ;
variable v_bool1 : boolean := true ;
variable v_real1 : real := 3.5 ;
subtype st_arr_1 is arr_1 ( 1 to 4 ) ;
subtype st_arr_2 is arr_1 ( 1 to 5 ) ;
subtype st_arr_3 is arr_1 ( 2 to 2 ) ;
variable v_arr_1 : st_arr_1 ;
variable v_arr_2 : st_arr_2 ;
variable v_arr_3 : st_arr_3 ;
variable v_rec_1, v_rec_3 : rec_1 ;
variable v_rec_2 : rec_2 ;
variable bool : boolean := true ;
begin
v_rec_1 := ( f1 => v_int1, f2 => v_bool1, f3 => v_real1 ) ;
v_rec_3 := ( 4, false, 3.3 ) ;
v_rec_2 := ( f1 => v_int1 ) ;
v_arr_1 := ( 1 => v_rec_1, 3 downto 2 => v_rec_3, others => v_rec_1 ) ;
v_arr_2 := ( 1 to 5 => v_rec_1 ) ;
v_arr_3 := ( 2 => v_rec_3 ) ;
bool := bool and v_rec_1.f1 = v_int1 ;
bool := bool and v_rec_1.f2 = v_bool1 ;
bool := bool and v_rec_1.f3 = v_real1 ;
bool := bool and v_rec_2.f1 = v_int1 ;
bool := bool and v_arr_1(1) = v_rec_1 ;
bool := bool and v_arr_1(2) = v_rec_3 ;
bool := bool and v_arr_1(3) = v_rec_3 ;
bool := bool and v_arr_1(4) = v_rec_1 ;
for i in 5 downto 1 loop
bool := bool and v_arr_2(i) = v_rec_1 ;
end loop ;
bool := bool and v_arr_3(2) = v_rec_3 ;
test_report ( "ARCH00475" ,
"Aggregates may have one or many element associations" ,
bool ) ;
wait ;
end process ;
end ARCH00475 ;
entity ENT00475_Test_Bench is
end ENT00475_Test_Bench ;
architecture ARCH00475_Test_Bench of ENT00475_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00475 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00475_Test_Bench ;
| gpl-3.0 | 8375bd57d2e6f77d511312a39a68c316 | 0.494715 | 2.974843 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00600.vhd | 1 | 2,313 | -- NEED RESULT: ARCH00600: Index ranges of variables and signals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00600
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.1.1 (1)
-- 3.2.1.1 (2)
-- 3.2.1.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00600)
-- ENT00600_Test_Bench(ARCH00600_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES; use STANDARD_TYPES.all ;
architecture ARCH00600 of E00000 is
signal s : STANDARD_TYPES.st_arr1 ; -- 3.2.1.1 (for signals)
signal t : STANDARD_TYPES.st_rec3 ; -- 3.2.1.2 (for signals)
signal u : STANDARD_TYPES.st_arr2 ; -- 3.2.1.3 (for signals)
begin
P :
process
variable a : STANDARD_TYPES.st_arr1 ; -- 3.2.1.1 (for variables)
variable b : STANDARD_TYPES.st_rec3 ; -- 3.2.1.2 (for variables)
variable c : STANDARD_TYPES.st_arr2 ; -- 3.2.1.3 (for variables)
begin
test_report ( "ARCH00600" ,
"Index ranges of variables and signals" ,
(a'left = lowb) and
(a'right = highb) and
(b.f3'left(1) = lowb) and
(b.f3'right(1) = highb) and
(b.f3'left(2) = false) and
(b.f3'right(2) = true) and
(c(lowb,false)'left = lowb) and
(c(lowb,false)'right = highb) and
(s'left = lowb) and
(s'right = highb) and
(t.f3'left(1) = lowb) and
(t.f3'right(1) = highb) and
(t.f3'left(2) = false) and
(t.f3'right(2) = true) and
(u(lowb,false)'left = lowb) and
(u(lowb,false)'right = highb)
) ;
wait;
end process P ;
end ARCH00600 ;
--
entity ENT00600_Test_Bench is
end ENT00600_Test_Bench ;
architecture ARCH00600_Test_Bench of ENT00600_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00600 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00600_Test_Bench ;
--
| gpl-3.0 | 3158b6e3a0eb0acab5bacac093ac26c2 | 0.510592 | 2.988372 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00484.vhd | 1 | 4,122 | -- NEED RESULT: ARCH00484: Function parameters of standard types or locally static size passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00484
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1 (6)
-- 2.1.1 (7)
-- 2.1.1 (9)
-- 2.1.1 (12)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00484)
-- ENT00484_Test_Bench(ARCH00484_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00484 of E00000 is
begin
P :
process
-- this will test 2.1.1 (6) and 2.1.1 (12)
function f_1 ( bi : bit ;
bv : bit_vector ; -- this tests 2.1.1 (12)
bo : boolean ;
c : character ;
i : integer ;
r : real ;
s : string ;
t : time) return integer is
variable n : integer := 0 ;
begin
if bi = '1' then
n := n + 1 ;
end if ;
if bv(2) = '0' then
n := n + 1 ;
end if ;
if bo = true then
n := n + 1 ;
end if ;
if c = '!' then
n := n + 1 ;
end if ;
if i = 100 then
n := n + 1 ;
end if ;
if r = 100.0 then
n := n + 1 ;
end if ;
if s(2) = 'a' then
n := n + 1 ;
end if ;
if t = 100 ns then
n := n + 1 ;
end if ;
return n ;
end f_1 ;
-- this will test 2.1.1 (7)
-- (the various types are in STANDARD_TYPES)
function f_2 ( t_en : t_enum1 ;
st_en : st_enum1 ;
t_in : t_int1 ;
st_in : st_int1 ;
t_ph : t_phys1 ;
st_ph : st_phys1 ;
t_re : t_real1 ;
st_re : st_real1 ) return integer is
variable n : integer := 0 ;
begin
if t_en = en2 then
n := n + 1 ;
end if ;
if st_en = en3 then
n := n + 1 ;
end if ;
if t_in = 10 then
n := n + 1 ;
end if ;
if st_in = 12 then
n := n + 1 ;
end if ;
if t_ph = phys1_3 then
n := n + 1 ;
end if ;
if st_ph = phys1_4 then
n := n + 1 ;
end if ;
if t_re = 10.0 then
n := n + 1 ;
end if ;
if st_re = 12.0 then
n := n + 1 ;
end if ;
return n ;
end f_2 ;
-- this will test 2.1.1 (9)
-- (the various types are in STANDARD_TYPES)
function f_3 ( t_ar : t_arr1 ; -- this tests 2.1.1 (12) again
st_ar : st_arr1 ;
t_r1 : t_rec1 ;
t_r3 : t_rec3 ) return integer is
variable n : integer := 0 ;
begin
if t_ar(2) = c_st_int1_1 then
n := n + 1 ;
end if ;
if st_ar(2) = c_st_int1_2 then
n := n + 1 ;
end if ;
if t_r1.f2 = c_time_1 then
n := n + 1 ;
end if ;
if t_r3.f1 = c_boolean_1 then
n := n + 1 ;
end if ;
return n ;
end f_3 ;
variable b_vect : bit_vector (0 to 2) ;
begin
b_vect(0) := '0' ;
b_vect(1) := '1' ;
b_vect(2) := '0' ;
test_report ( "ARCH00484" ,
"Function parameters of standard types or locally static size" ,
(f_1('1', b_vect, true, '!', 100, 100.0, "cat", 100 ns) = 8) and
(f_2(en2, en3, 10, 12, phys1_3, phys1_4, 10.0, 12.0) = 8) and
(f_3(c_st_arr1_1, c_st_arr1_2, c_t_rec1_1, c_t_rec3_1) = 4)
) ;
wait ;
end process P ;
end ARCH00484 ;
entity ENT00484_Test_Bench is
end ENT00484_Test_Bench ;
architecture ARCH00484_Test_Bench of ENT00484_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00484 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00484_Test_Bench ;
| gpl-3.0 | 48ee0d9008123155eb71b2017e8a37da | 0.426007 | 3.057864 | false | true | false | false |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if.vhd | 2 | 21,298 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_initials_buckets_if OF nfa_initials_buckets_if IS
component nfa_initials_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_initials_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_initials_buckets_if_req_fifo: component nfa_initials_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_initials_buckets_if_rsp_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_initials_buckets_if_rd_fifo: component nfa_initials_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_initials_buckets_if_rd_user_fifo: component nfa_initials_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_initials_buckets_if;
| lgpl-3.0 | 4cc2377880a2f72bbd6957f829b25f81 | 0.577331 | 3.092942 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00361.vhd | 1 | 6,226 | -- NEED RESULT: ARCH00361.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00361: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00361: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00361
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00361(ARCH00361)
-- ENT00361_Test_Bench(ARCH00361_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00361 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00361 ;
--
--
architecture ARCH00361 of ENT00361 is
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00361.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_vector_select <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr1_vector_select <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00361" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00361" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00361" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_vector_savt <= transport Std.Standard.Now ;
chk_st_arr1_vector <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_vector_cnt <= transport s_st_arr1_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr1_vector_select select
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00361 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00361_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00361_Test_Bench ;
--
--
architecture ARCH00361_Test_Bench of ENT00361_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00361 ( ARCH00361 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00361_Test_Bench ;
| gpl-3.0 | cf5fa7a86c4690a4a736019e544d6b36 | 0.527465 | 3.283755 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd | 1 | 45,036 | ------------------------------------------------------------------------------
-- C:/Users/JairoAndres/Documents/Vivado/oil_plainc_hls/impl/impl_test_pcie/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "virtex5" ;
C_DEVICE : string := "5vlx50t";
C_PACKAGE : string := "ff1136";
C_SPEEDGRADE : string := "-1";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component dcm_module is
generic (
C_DFS_FREQUENCY_MODE : string := "LOW";
C_DLL_FREQUENCY_MODE : string := "LOW";
C_DUTY_CYCLE_CORRECTION : boolean := true;
C_CLKIN_DIVIDE_BY_2 : boolean := false;
C_CLK_FEEDBACK : string := "1X";
C_CLKOUT_PHASE_SHIFT : string := "NONE";
C_DSS_MODE : string := "NONE";
C_STARTUP_WAIT : boolean := false;
C_PHASE_SHIFT : integer := 0;
C_CLKFX_MULTIPLY : integer := 4;
C_CLKFX_DIVIDE : integer := 1;
C_CLKDV_DIVIDE : real := 2.0;
C_CLKIN_PERIOD : real := 41.6666666;
C_DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
C_CLKIN_BUF : boolean := false;
C_CLKFB_BUF : boolean := false;
C_CLK0_BUF : boolean := false;
C_CLK90_BUF : boolean := false;
C_CLK180_BUF : boolean := false;
C_CLK270_BUF : boolean := false;
C_CLKDV_BUF : boolean := false;
C_CLK2X_BUF : boolean := false;
C_CLK2X180_BUF : boolean := false;
C_CLKFX_BUF : boolean := false;
C_CLKFX180_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
RST : in std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector(7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic
);
end component;
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : DCM0 wrapper
signal SIG_DCM0_RST : std_logic;
signal SIG_DCM0_CLKIN : std_logic;
signal SIG_DCM0_CLKFB : std_logic;
signal SIG_DCM0_PSEN : std_logic;
signal SIG_DCM0_PSINCDEC : std_logic;
signal SIG_DCM0_PSCLK : std_logic;
signal SIG_DCM0_DSSEN : std_logic;
signal SIG_DCM0_CLK0 : std_logic;
signal SIG_DCM0_CLK90 : std_logic;
signal SIG_DCM0_CLK180 : std_logic;
signal SIG_DCM0_CLK270 : std_logic;
signal SIG_DCM0_CLKDV : std_logic;
signal SIG_DCM0_CLKDV180 : std_logic;
signal SIG_DCM0_CLK2X : std_logic;
signal SIG_DCM0_CLK2X180 : std_logic;
signal SIG_DCM0_CLKFX : std_logic;
signal SIG_DCM0_CLKFX180 : std_logic;
signal SIG_DCM0_STATUS : std_logic;
signal SIG_DCM0_LOCKED : std_logic;
signal SIG_DCM0_PSDONE : std_logic;
signal SIG_DCM0_CLK0_BUF : std_logic;
signal SIG_DCM0_CLK90_BUF : std_logic;
signal SIG_DCM0_CLK180_BUF : std_logic;
signal SIG_DCM0_CLK270_BUF : std_logic;
signal SIG_DCM0_CLKDV_BUF : std_logic;
signal SIG_DCM0_CLKDV180_BUF : std_logic;
signal SIG_DCM0_CLK2X_BUF : std_logic;
signal SIG_DCM0_CLK2X180_BUF : std_logic;
signal SIG_DCM0_CLKFX_BUF : std_logic;
signal SIG_DCM0_CLKFX180_BUF : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
-- DCM0 wrapper
DCM0_INST : dcm_module
generic map (
C_DFS_FREQUENCY_MODE => "LOW",
C_DLL_FREQUENCY_MODE => "HIGH",
C_DUTY_CYCLE_CORRECTION => true,
C_CLKIN_DIVIDE_BY_2 => false,
C_CLK_FEEDBACK => "1X",
C_CLKOUT_PHASE_SHIFT => "NONE",
C_DSS_MODE => "NONE",
C_STARTUP_WAIT => false,
C_PHASE_SHIFT => 0,
C_CLKFX_MULTIPLY => 4,
C_CLKFX_DIVIDE => 1,
C_CLKDV_DIVIDE => 2.0,
C_CLKIN_PERIOD => 8.000000,
C_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_CLKIN_BUF => false,
C_CLKFB_BUF => false,
C_CLK0_BUF => false,
C_CLK90_BUF => false,
C_CLK180_BUF => false,
C_CLK270_BUF => false,
C_CLKDV_BUF => false,
C_CLK2X_BUF => false,
C_CLK2X180_BUF => false,
C_CLKFX_BUF => false,
C_CLKFX180_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
RST => SIG_DCM0_RST,
CLKIN => SIG_DCM0_CLKIN,
CLKFB => SIG_DCM0_CLKFB,
PSEN => SIG_DCM0_PSEN,
PSINCDEC => SIG_DCM0_PSINCDEC,
PSCLK => SIG_DCM0_PSCLK,
DSSEN => net_gnd0,
CLK0 => SIG_DCM0_CLK0,
CLK90 => SIG_DCM0_CLK90,
CLK180 => open,
CLK270 => SIG_DCM0_CLK270,
CLKDV => SIG_DCM0_CLKDV,
CLK2X => SIG_DCM0_CLK2X,
CLK2X180 => open,
CLKFX => SIG_DCM0_CLKFX,
CLKFX180 => open,
STATUS => open,
LOCKED => SIG_DCM0_LOCKED,
PSDONE => SIG_DCM0_PSDONE
);
-- wrapper of clkout : CLK0 and clkinv : CLK180
DCM0_CLK0_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK0,
O => SIG_DCM0_CLK0_BUF
);
SIG_DCM0_CLK180 <= NOT SIG_DCM0_CLK0;
SIG_DCM0_CLK180_BUF <= NOT SIG_DCM0_CLK0_BUF;
-- wrapper of clkout : CLK2X and clkinv : CLK2X180
SIG_DCM0_CLK2X_BUF <= SIG_DCM0_CLK2X;
SIG_DCM0_CLK2X180 <= NOT SIG_DCM0_CLK2X;
SIG_DCM0_CLK2X180_BUF <= NOT SIG_DCM0_CLK2X_BUF;
-- wrapper of clkout : CLKDV and clkinv : CLKDV180
SIG_DCM0_CLKDV_BUF <= SIG_DCM0_CLKDV;
SIG_DCM0_CLKDV180 <= NOT SIG_DCM0_CLKDV;
SIG_DCM0_CLKDV180_BUF <= NOT SIG_DCM0_CLKDV_BUF;
-- wrapper of clkout : CLKFX and clkinv : CLKFX180
SIG_DCM0_CLKFX_BUF <= SIG_DCM0_CLKFX;
SIG_DCM0_CLKFX180 <= NOT SIG_DCM0_CLKFX;
SIG_DCM0_CLKFX180_BUF <= NOT SIG_DCM0_CLKFX_BUF;
DCM0_CLK90_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK90,
O => SIG_DCM0_CLK90_BUF
);
DCM0_CLK270_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK270,
O => SIG_DCM0_CLK270_BUF
);
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 10,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 8,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 90.0000,
C_CLKOUT1_DIVIDE => 8,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0000,
C_CLKOUT2_DIVIDE => 5,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0000,
C_CLKOUT3_DIVIDE => 16,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0000,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
PLL0_CLKOUT1_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT1,
O => SIG_PLL0_CLKOUT1_BUF
);
-- wrapper of clkout : CLKOUT2
PLL0_CLKOUT2_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT2,
O => SIG_PLL0_CLKOUT2_BUF
);
-- wrapper of clkout : CLKOUT3
PLL0_CLKOUT3_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT3,
O => SIG_PLL0_CLKOUT3_BUF
);
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
-- DCM0 CLKIN
SIG_DCM0_CLKIN <= SIG_PLL0_CLKOUT1_BUF;
-- DCM0 CLKFB
SIG_DCM0_CLKFB <= CLKFBIN;
-- DCM0 RST
SIG_DCM0_RST <= SIG_PLL0_LOCKED;
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= SIG_PLL0_CLKOUT1_BUF;
CLKOUT2 <= SIG_PLL0_CLKOUT2_BUF;
CLKOUT3 <= SIG_PLL0_CLKOUT3_BUF;
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
CLKFBOUT <= SIG_DCM0_CLK0_BUF;
-- CLKGEN LOCKED
LOCKED <= SIG_DCM0_LOCKED and SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = virtex5
-- C_DEVICE = 5vlx50t
-- C_PACKAGE = ff1136
-- C_SPEEDGRADE = -1
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 125000000
-- C_CLKOUT0_PHASE = 90
-- C_CLKOUT0_GROUP = PLL0
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 125000000
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = PLL0
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 200000000
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 62500000
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = PLL0
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 125000000
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 125000000
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = PLL0
-- C_CLKOUT1_PORT = CLKOUT1B
-- C_CLKOUT2_MODULE = PLL0
-- C_CLKOUT2_PORT = CLKOUT2B
-- C_CLKOUT3_MODULE = PLL0
-- C_CLKOUT3_PORT = CLKOUT3B
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = DCM0
-- C_CLKFBOUT_PORT = CLK0B
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "HIGH"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 8.000000
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = TRUE
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 0
-- C_DCM0_FAMILY = "virtex5"
-- C_DCM0_CLKIN_MODULE = PLL0
-- C_DCM0_CLKIN_PORT = CLKOUT1B
-- C_DCM0_CLKFB_MODULE = CLKGEN
-- C_DCM0_CLKFB_PORT = CLKFBIN
-- C_DCM0_RST_MODULE = PLL0
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "virtex5"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "virtex5"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "virtex5"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 10
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 8
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 90.0000
-- C_PLL0_CLKOUT1_DIVIDE = 8
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0000
-- C_PLL0_CLKOUT2_DIVIDE = 5
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0000
-- C_PLL0_CLKOUT3_DIVIDE = 16
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0000
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = TRUE
-- C_PLL0_CLKOUT2_BUF = TRUE
-- C_PLL0_CLKOUT3_BUF = TRUE
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 0
-- C_PLL0_FAMILY = "virtex5"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "virtex5"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "virtex5"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "virtex5"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "virtex5"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "virtex5"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
| lgpl-3.0 | a7cff8216a1e6c6e5ef8739504f6cd3c | 0.54341 | 3.007011 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00166.vhd | 1 | 8,651 | -- NEED RESULT: ARCH00166.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: Inertial semantics check on a signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: Inertial semantics check on a signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00166: Inertial semantics check on a signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00166
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00166(ARCH00166)
-- ENT00166_Test_Bench(ARCH00166_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00166 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal Chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00166.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00166" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00166" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00166" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00166" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00166" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
--
end ENT00166 ;
--
architecture ARCH00166 of ENT00166 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1_vector,
counter,
correct,
savtime,
Chk_st_arr1_vector
) ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00166 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00166_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00166_Test_Bench ;
--
architecture ARCH00166_Test_Bench of ENT00166_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00166 ( ARCH00166 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00166_Test_Bench ;
| gpl-3.0 | ef853d0e0ab91dc950003338e57af00f | 0.514507 | 3.465946 | false | true | false | false |
rauenzi/VHDL-Communications | top_level.vhd | 1 | 6,220 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 1/22/15
--
--
--Version: 1.2
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all; -- add to do arithmetic operations
use IEEE.std_logic_arith.all; -- add to do arithmetic operations
entity top_level is
Generic (constant SequenceDisplaySpeed : integer := 1; -- 1 Hz
constant RefreshSpeed : integer := 1000; -- 1 KHz
constant sequenceCount : integer := 8;
constant BoardClock : integer := 100000000;
constant buttonMax: std_logic_vector(15 downto 0) := X"FFFF";
constant baud : integer := 9600;
constant SPIspeed : integer :=250000); -- 1KHz, 1Hz
-- Generic (constant SequenceDisplaySpeed : integer := 1000;
-- constant RefreshSpeed : integer := 100000;
-- constant BoardClock : integer := 100000000;
-- constant sequenceCount : integer := 8;
-- constant buttonMax: std_logic_vector(15 downto 0) := X"0002";
-- constant baud : integer := 2000000;
-- constant SPIspeed : integer :=2000000);
----The above lines are used for simulation and chipscope.
Port ( clk : in std_logic;
reset : in std_logic;
reverse : in std_logic;
enabler : in std_logic;
DispVector : out std_logic_vector(7 downto 0);
SegVector : out std_logic_vector(7 downto 0);
oRx : out std_logic;
oSCK : out std_logic;
oSS : out std_logic;
oMOSI : out std_logic;
i2c_sda : inout std_logic;
i2c_scl : inout std_logic);
end top_level;
architecture Behavioral of top_level is
component BoardDisplay is
Generic (RefreshRate : integer := 1000;
ClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Data : in std_logic_vector(15 downto 0);
DisplayVector : out std_logic_vector(7 downto 0);
SegmentVector : out std_logic_vector(7 downto 0));
end component BoardDisplay;
component SequenceController is
Generic (NumOfSequences : integer := 8;
DesiredDisplaySpeed : integer := 100000;
InputClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Enabler : in std_logic;
Reset : in std_logic;
Reverse : in std_logic;
MemAddress : out integer := 0);
end component SequenceController;
component Serial_TTL_display is
Generic (BaudSpeed : integer :=9600;
Boardspeed : integer :=100000000);
Port ( Clock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
RX : out STD_LOGIC);
end component Serial_TTL_display;
component btn_debounce_toggle is
GENERIC (
CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
Port ( BTN_I : in STD_LOGIC;
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC;
TOGGLE_O : out STD_LOGIC);
end component btn_debounce_toggle;
-- SequenceStorage should be a Xilinx single port ROM IP-Core
COMPONENT SequenceStorage
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
component SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end component SPI_display;
component i2c_controller is
Port ( Clock : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
oSDA : inout STD_LOGIC;
oSCL : inout STD_LOGIC);
end component i2c_controller;
signal resetDebounce, enablerToggle, reverseToggle : std_logic;
signal DataFromRom : std_logic_vector(15 downto 0);
signal DataAddress : integer;
signal DataAddressToRom : std_logic_vector(3 downto 0);
signal notReverseToggle : std_logic;
signal high : std_logic := '1';
begin
notReverseToggle <= NOT reverseToggle;
DataAddressToRom <= std_logic_vector(to_unsigned(DataAddress,4));
Reset_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reset,CLK=>clk,BTN_O=>resetDebounce,TOGGLE_O=>OPEN);
Enabler_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>enabler,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>enablerToggle);
Reverse_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reverse,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>reverseToggle);
SequenceControl: SequenceController
Generic map (NumOfSequences=>sequenceCount,
DesiredDisplaySpeed=>SequenceDisplaySpeed,
InputClockSpeed=>BoardClock)
Port map (ClockState=>clk,
Enabler=>enablerToggle,
Reset=>resetDebounce,
Reverse=> notReverseToggle,
MemAddress=>DataAddress);
BoardController: BoardDisplay
generic map (RefreshRate=>RefreshSpeed,
ClockSpeed=>BoardClock)
port map ( ClockState=>clk,
Data=>DataFromRom,
DisplayVector=>DispVector,
SegmentVector=>SegVector);
TTL: Serial_TTL_display
generic map (BaudSpeed=>baud,
Boardspeed=>BoardClock)
Port map ( Clock=>clk,
Data=>DataFromRom,
RX=>oRx);
MainRom: SequenceStorage
PORT MAP (
clka => clk,
addra => DataAddressToRom,
douta => DataFromRom
);
SPI: SPI_display
generic map (BoardClockSpeed=>BoardClock,
SCKSpeed=>SPIspeed)
Port map ( BoardClock=>clk,
Data=>DataFromRom,
SCK=>oSCK,
SS=>oSS,
MOSI=>oMOSI
);
I2C: i2c_controller
Port map ( Clock=>clk,
dataIn=>DataFromRom,
oSDA=>i2c_sda,
oSCL=>i2c_scl);
end Behavioral;
| apache-2.0 | 4e4985ee313266516f7dd7642aeda926 | 0.603698 | 3.997429 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00332.vhd | 1 | 3,631 | -- NEED RESULT: ARCH00332.Check_s6: Concurrent signal assignment may have a label passed
-- NEED RESULT: ARCH00332.Check_s5: Concurrent signal assignment need not have a label passed
-- NEED RESULT: ARCH00332.Check_s4: Concurrent signal assignment may have a label passed
-- NEED RESULT: ARCH00332.Check_s3: Concurrent signal assignment need not have a label passed
-- NEED RESULT: ARCH00332.Check_s2: Concurrent signal assignment may have a label passed
-- NEED RESULT: ARCH00332.Check_s1: Concurrent signal assignment need not have a label passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00332
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00332)
-- ENT00332_Test_Bench(ARCH00332_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00332 of E00000 is
type T is array ( Integer range <> ) of integer ;
subtype T_range is Integer range 1 to 6 ;
subtype TA is T ( T_range ) ;
signal s : TA := (others => 0) ;
subtype st_integer is integer range 0 to 7 ;
alias s1 : st_integer is s(1) ;
alias s2 : st_integer is s(2) ;
alias s3 : st_integer is s(3) ;
alias s4 : st_integer is s(4) ;
alias s5 : st_integer is s(5) ;
alias s6 : st_integer is s(6) ;
signal IntSig : Integer := 1 ;
begin
A_Label : s1 <= transport 1 after 10 ns ;
s2 <= transport 2 after 10 ns ;
B_Label : s3 <= transport 3 after 10 ns when true else 1 ;
s4 <= transport 4 after 10 ns when true else 1 ;
C_Label : with IntSig select
s5 <= transport 5 after 10 ns when 1,
1 when others ;
with IntSig select
s6 <= transport 6 after 10 ns when 1,
1 when others ;
g1: for i in Integer range 1 to 6 generate
L :
block
function To_Char ( P : T_Range ) return Character is
begin
case P is
when 1 =>
return '1' ;
when 2 =>
return '2' ;
when 3 =>
return '3' ;
when 4 =>
return '4' ;
when 5 =>
return '5' ;
when 6 =>
return '6' ;
when others =>
test_report ( "ARCH00332.To_Char" ,
"Illegal input parameter" ,
False ) ;
end case ;
end To_Char ;
begin
process
begin
wait on s(i) for 11 ns ;
if (i mod 2) = 0 then
test_report ( "ARCH00332.Check_s" & To_Char(i) ,
"Concurrent signal assignment may have a label" ,
s(i) = i ) ;
else
test_report ( "ARCH00332.Check_s" & To_Char(i) ,
"Concurrent signal assignment need not have a label" ,
s(i) = i ) ;
end if ;
wait ;
end process ;
end block L ;
end generate ;
end ARCH00332 ;
entity ENT00332_Test_Bench is
end ENT00332_Test_Bench ;
architecture ARCH00332_Test_Bench of ENT00332_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00332 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00332_Test_Bench ;
| gpl-3.0 | fcb325e6d75494b090f6e8f644dae155 | 0.530157 | 3.587945 | false | true | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/40c681daa8c49851/bram_1024_2_sim_netlist.vhdl | 1 | 52,972 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_2_sim_netlist.vhdl
-- Design : bram_1024_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001F0000001B00000017000000130000000F0000000B0000000700000003",
INIT_01 => X"0000011F0000011B00000117000001130000010F0000010B0000010700000103",
INIT_02 => X"0000021F0000021B00000217000002130000020F0000020B0000020700000203",
INIT_03 => X"0000031F0000031B00000317000003130000030F0000030B0000030700000303",
INIT_04 => X"0000041F0000041B00000417000004130000040F0000040B0000040700000403",
INIT_05 => X"0000051F0000051B00000517000005130000050F0000050B0000050700000503",
INIT_06 => X"0000061F0000061B00000617000006130000060F0000060B0000060700000603",
INIT_07 => X"0000071F0000071B00000717000007130000070F0000070B0000070700000703",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_1024_2,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 93027166ff1b349a23e8b587cb8194f4 | 0.70643 | 3.441752 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/impl/vhdl/sample_iterator_get_offset.vhd | 1 | 42,907 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_begin_addr_reg_135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_147 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_8_reg_167 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_ce : STD_LOGIC;
signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4
generic map (
ID => 0,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_116_p0,
din1 => grp_fu_116_p1,
ce => grp_fu_116_ce,
dout => grp_fu_116_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_125_p0,
din1 => grp_fu_125_p1,
ce => grp_fu_125_ce,
dout => grp_fu_125_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0) <= indices_begin_addr_reg_135(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1) <= indices_begin_addr_reg_135(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2) <= indices_begin_addr_reg_135(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3) <= indices_begin_addr_reg_135(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4) <= indices_begin_addr_reg_135(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5) <= indices_begin_addr_reg_135(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6) <= indices_begin_addr_reg_135(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7) <= indices_begin_addr_reg_135(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8) <= indices_begin_addr_reg_135(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9) <= indices_begin_addr_reg_135(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10) <= indices_begin_addr_reg_135(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11) <= indices_begin_addr_reg_135(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12) <= indices_begin_addr_reg_135(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13) <= indices_begin_addr_reg_135(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14) <= indices_begin_addr_reg_135(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15) <= indices_begin_addr_reg_135(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_130 <= i_sample;
indices_begin_addr_reg_135(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0);
indices_begin_addr_reg_135(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1);
indices_begin_addr_reg_135(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2);
indices_begin_addr_reg_135(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3);
indices_begin_addr_reg_135(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4);
indices_begin_addr_reg_135(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5);
indices_begin_addr_reg_135(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6);
indices_begin_addr_reg_135(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7);
indices_begin_addr_reg_135(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8);
indices_begin_addr_reg_135(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9);
indices_begin_addr_reg_135(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10);
indices_begin_addr_reg_135(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11);
indices_begin_addr_reg_135(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12);
indices_begin_addr_reg_135(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13);
indices_begin_addr_reg_135(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14);
indices_begin_addr_reg_135(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_162 <= indices_begin_datain;
tmp_8_reg_167 <= grp_fu_116_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_147 <= indices_stride_datain;
end if;
end if;
end process;
indices_begin_addr_reg_135(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it9 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it17, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= grp_fu_125_p2;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_116_ce assign process. --
grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_116_ce <= ap_const_logic_1;
else
grp_fu_116_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0);
grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5),24));
grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0);
grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_147),24));
-- grp_fu_125_ce assign process. --
grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_125_ce <= ap_const_logic_1;
else
grp_fu_125_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_8_reg_167),32));
grp_fu_125_p1 <= indices_begin_addr_read_reg_162;
indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0);
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | e0c4baed60266c32b423940399d1bc5f | 0.616939 | 2.635403 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00227.vhd | 1 | 11,727 | -- NEED RESULT: ENT00227.P00227: Associated scalar inout ports with static subtypes passed
-- NEED RESULT: ENT00227: Associated scalar inout ports with static subtypes passed
-- NEED RESULT: ENT00227.P00227: Associated scalar inout ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00227
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00227(ARCH00227)
-- ENT00227_Test_Bench(ARCH00227_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00227 is
port (
toggle : inout switch := down;
i_boolean_1, i_boolean_2 : inout boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : inout bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : inout severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : inout character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : inout t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : inout st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : inout integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : inout t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : inout st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : inout time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : inout t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : inout st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : inout real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : inout t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : inout st_real1
:= c_st_real1_1
) ;
begin
end ENT00227 ;
--
architecture ARCH00227 of ENT00227 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
--
test_report ( "ENT00227" ,
"Associated scalar inout ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
wait ;
end process ;
end ARCH00227 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00227_Test_Bench is
end ENT00227_Test_Bench ;
--
architecture ARCH00227_Test_Bench of ENT00227_Test_Bench is
begin
L1:
block
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
component UUT
port (
toggle : inout switch ;
i_boolean_1, i_boolean_2 : inout boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : inout bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : inout severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : inout character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : inout t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : inout st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : inout integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : inout t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : inout st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : inout time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : inout t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : inout st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : inout real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : inout t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : inout st_real1
:= c_st_real1_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00227 ( ARCH00227 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
P00227 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
end if ;
--
test_report ( "ENT00227.P00227" ,
"Associated scalar inout ports with static subtypes",
correct) ;
end process P00227 ;
end block L1 ;
end ARCH00227_Test_Bench ;
| gpl-3.0 | cf863bc619473e8033501b6515f2a23a | 0.444018 | 3.059483 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_indices_samples.vhd | 1 | 28,953 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_indices_samples is
generic (
constant TV_IN : STRING (1 to 76) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
constant TV_OUT : STRING (1 to 81) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_indices_samples.dat";
constant DATA_WIDTH : INTEGER := 16;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_indices_samples;
architecture behav of AESL_autobus_indices_samples is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | c4e07820928d04ff8fed316a54d10cef | 0.431527 | 3.804599 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_nfa_forward_buckets.vhd | 1 | 28,973 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_nfa_forward_buckets is
generic (
constant TV_IN : STRING (1 to 80) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_forward_buckets.dat";
constant TV_OUT : STRING (1 to 85) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_nfa_forward_buckets.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_nfa_forward_buckets;
architecture behav of AESL_autobus_nfa_forward_buckets is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | d832e535ed6cd09b84205f38bbc830e6 | 0.431747 | 3.797248 | false | false | false | false |
dcliche/mdsynth | rtl/src/cpu09.vhd | 1 | 168,607 | --===========================================================================--
-- --
-- Synthesizable 6809 instruction compatible VHDL CPU core --
-- --
--===========================================================================--
--
-- File name : cpu09.vhd
--
-- Entity name : cpu09
--
-- Purpose : 6809 instruction compatible CPU core written in VHDL
-- Not cycle compatible with the original 6809 CPU
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.14 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
-- Version 1.15 - 25th Feb 2007 - John Kent
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
-- Changed sensitivity lists.
--
-- Version 1.16 - 5th February 2008 - John Kent
-- FIRQ interrupts should take priority over IRQ Interrupts.
-- This presumably means they should be tested for before IRQ
-- when they happen concurrently.
--
-- Version 1.17 - 18th February 2008 - John Kent
-- NMI in CWAI should mask IRQ and FIRQ interrupts
--
-- Version 1.18 - 21st February 2008 - John Kent
-- Removed default register settings in each case statement
-- and placed them at the beginning of the state sequencer.
-- Modified the SYNC instruction so that the interrupt vector(iv)
-- is not set unless an unmasked FIRQ or IRQ is received.
--
-- Version 1.19 - 25th February 2008 - John Kent
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
-- Enumerated separate states for MASKI and MASKIF states
-- Removed code on BSR/JSR in fetch cycle
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu09 is
port (
clk : in std_logic;
rst : in std_logic;
vma : out std_logic;
addr : out std_logic_vector(15 downto 0);
rw : out std_logic;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
irq : in std_logic;
firq : in std_logic;
nmi : in std_logic;
halt : in std_logic;
hold : in std_logic
);
end cpu09;
architecture rtl of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, error_state,
--
andcc_state, orcc_state,
tfr_state, exg_state, exg1_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_nmiirq_state, int_firq_state,
int_entire_state, int_fast_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_dp_state,
int_accb_state, int_acca_state,
int_cc_state,
int_cwai_state,
int_maski_state, int_maskif_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state );
type stack_type is array(2 downto 0) of state_type;
type st_type is (idle_st, push_st, pull_st );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type iv_type is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left );
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal dp: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal up: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal nmi_enable: std_logic;
signal state: state_type;
signal next_state: state_type;
signal saved_state: state_type;
signal return_state: state_type;
signal state_stack: stack_type;
signal st_ctrl: st_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal dp_ctrl: dp_type;
signal sp_ctrl: sp_type;
signal up_ctrl: up_type;
signal iv_ctrl: iv_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
signal nmi_ctrl: nmi_type;
begin
----------------------------------
--
-- State machine stack
--
----------------------------------
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
-- return_state, fetch_state )
state_stack_proc: process( clk, state_stack )
begin
if clk'event and clk = '0' then
if hold= '1' then
state_stack(0) <= state_stack(0);
state_stack(1) <= state_stack(1);
state_stack(2) <= state_stack(2);
else
case st_ctrl is
when idle_st =>
state_stack(0) <= state_stack(0);
state_stack(1) <= state_stack(1);
state_stack(2) <= state_stack(2);
when push_st =>
state_stack(0) <= return_state;
state_stack(1) <= state_stack(0);
state_stack(2) <= state_stack(1);
when pull_st =>
state_stack(0) <= state_stack(1);
state_stack(1) <= state_stack(2);
state_stack(2) <= fetch_state;
when others =>
state_stack(0) <= state_stack(0);
state_stack(1) <= state_stack(1);
state_stack(2) <= state_stack(2);
end case;
end if;
end if;
saved_state <= state_stack(0);
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
pc_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
pc <= pc;
else
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others =>
-- when latch_pc =>
pc <= pc;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
ea_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
ea <= ea;
else
case ea_ctrl is
when reset_ea =>
ea <= "0000000000000000";
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
-- when latch_ea =>
ea <= ea;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
acca_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
acca <= acca;
else
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
-- when latch_acca =>
acca <= acca;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
accb_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
accb <= accb;
else
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
-- when latch_accb =>
accb <= accb;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
ix_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
xreg <= xreg;
else
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
iy_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
yreg <= yreg;
else
case iy_ctrl is
when reset_iy =>
yreg <= "0000000000000000";
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
-- when latch_iy =>
yreg <= yreg;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
sp_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
sp <= sp;
nmi_enable <= nmi_enable;
else
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
nmi_enable <= nmi_enable;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others =>
-- when latch_sp =>
sp <= sp;
nmi_enable <= nmi_enable;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
up_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
up <= up;
else
case up_ctrl is
when reset_up =>
up <= "0000000000000000";
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others =>
-- when latch_up =>
up <= up;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
md_reg : process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
md <= md;
else
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
-- when latch_md =>
md <= md;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
cc_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
cc <= cc;
else
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
-- when latch_cc =>
cc <= cc;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
dp_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
dp <= dp;
else
case dp_ctrl is
when reset_dp =>
dp <= "00000000";
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others =>
-- when latch_dp =>
dp <= dp;
end case;
end if;
end if;
end process;
----------------------------------
--
-- interrupt vector
--
----------------------------------
--iv_mux: process( clk, iv_ctrl, hold, iv )
iv_mux: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
iv <= iv;
else
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when resv_iv =>
iv <= RESV_VEC;
when others =>
iv <= iv;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
op_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
op_code <= op_code;
else
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others =>
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
pre_reg: process( clk )
begin
if clk'event and clk = '0' then
if hold= '1' then
pre_code <= pre_code;
else
case pre_ctrl is
when reset_pre =>
pre_code <= "00000000";
when fetch_pre =>
pre_code <= data_in;
when others =>
-- when latch_pre =>
pre_code <= pre_code;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
--change_state: process( clk, rst, state, hold, next_state )
change_state: process( clk )
begin
if clk'event and clk = '0' then
if rst = '1' then
state <= reset_state;
else
if hold = '1' then
state <= state;
else
state <= next_state;
end if;
end if;
end if;
end process;
-- output
------------------------------------
--
-- Nmi register
--
------------------------------------
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
nmi_reg: process( clk )
begin
if clk'event and clk='0' then
if hold = '1' then
nmi_ack <= nmi_ack;
else
case nmi_ctrl is
when set_nmi =>
nmi_ack <= '1';
when reset_nmi =>
nmi_ack <= '0';
when others =>
-- when latch_nmi =>
nmi_ack <= nmi_ack;
end case;
end if;
end if;
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
nmi_handler : process( rst, clk )
begin
if rst='1' then
nmi_req <= '0';
elsif clk'event and clk='0' then
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
begin
case addr_ctrl is
when idle_ad =>
vma <= '0';
addr <= "1111111111111111";
rw <= '1';
when fetch_ad =>
vma <= '1';
addr <= pc;
rw <= '1';
when read_ad =>
vma <= '1';
addr <= ea;
rw <= '1';
when write_ad =>
vma <= '1';
addr <= ea;
rw <= '0';
when pushs_ad =>
vma <= '1';
addr <= sp;
rw <= '0';
when pulls_ad =>
vma <= '1';
addr <= sp;
rw <= '1';
when pushu_ad =>
vma <= '1';
addr <= up;
rw <= '0';
when pullu_ad =>
vma <= '1';
addr <= up;
rw <= '1';
when int_hi_ad =>
vma <= '1';
addr <= "111111111111" & iv & "0";
rw <= '1';
when int_lo_ad =>
vma <= '1';
addr <= "111111111111" & iv & "1";
rw <= '1';
when others =>
vma <= '0';
addr <= "1111111111111111";
rw <= '1';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
begin
case dout_ctrl is
when cc_dout => -- condition code register
data_out <= cc;
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when dp_dout => -- direct page register
data_out <= dp;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when up_lo_dout => -- U stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- U stack pointer
data_out <= up(15 downto 8);
when sp_lo_dout => -- S stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- S stack pointer
data_out <= sp(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, md, acca, accb, ea )
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= "00000000" & md(7 downto 0);
else
right <= "11111111" & md(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
if (cc(CBIT) = '0') then
if( cc(HBIT) = '1' ) then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if( left(7 downto 4) <= 8 ) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if ( cc(HBIT) = '1' )then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, saved_state,
op_code, pre_code,
cc, ea, md, iv,
irq, firq, nmi_req, nmi_ack, halt )
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
-- Registers preserved
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
-- ALU Idle
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- Bus idle
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
-- Next State Fetch
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
cc_ctrl <= reset_cc;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
dp_ctrl <= reset_dp;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
up_ctrl <= reset_up;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
-- Fetch op code
addr_ctrl <= fetch_ad;
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
end case;
when "1101" => -- bsr / jsr
null;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
up_ctrl <= load_up;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when others =>
null;
end case;
if halt = '1' then
iv_ctrl <= reset_iv;
next_state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= int_nmiirq_state;
-- service maskable interrupts
else
--
-- nmi request is not cleared until nmi input goes low
--
if(nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
end if;
--
-- FIRQ & IRQ are level sensitive
--
if (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firq_state;
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_nmiirq_state;
else
-- Advance the PC to fetch next instruction byte
iv_ctrl <= reset_iv; -- default to reset
pc_ctrl <= incr_pc;
next_state <= decode1_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
-- advance the PC
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
when "1001" => -- daa
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
next_state <= fetch_state;
when "1010" => -- orcc
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= orcc_state;
when "1100" => -- andcc
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= andcc_state;
when "1101" => -- sex
-- have sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
next_state <= fetch_state;
when "1110" => -- exg
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= exg_state;
when "1111" => -- tfr
-- increment the pc
pc_ctrl <= incr_pc;
-- call transfer as a subroutine
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= tfr_state;
when others =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
-- advance PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
-- advance PC
pc_ctrl <= incr_pc;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= pull_return_hi_state;
--
-- add accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
ix_ctrl <= load_ix;
next_state <= fetch_state;
when "1011" => -- rti
next_state <= rti_cc_state;
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= reset_iv;
-- increment pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= int_entire_state; -- set entire flag
next_state <= andcc_state;
when "1101" => -- mul
next_state <= mul_state;
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi_iv;
next_state <= int_entire_state;
when others =>
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
-- increment PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= extended_state;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
next_state <= dual_op_write8_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= dual_op_write16_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1111" => -- stx >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
next_state <= dual_op_write8_state;
when "1101" => -- std direct
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when others =>
null;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
next_state <= int_entire_state;
when others =>
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
next_state <= dual_op_read16_state;
when "1111" => -- sty <
next_state <= dual_op_write16_state;
when others =>
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
next_state <= dual_op_read16_state;
when "1111" => -- sts <
next_state <= dual_op_write16_state;
when others =>
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
next_state <= fetch_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
next_state <= int_entire_state;
when others =>
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when others =>
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
next_state <= fetch_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= single_op_exec_state;
when single_op_exec_state =>
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1011" => -- undefined
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when others =>
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the high byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
st_ctrl <= pull_st;
next_state <= saved_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
--
-- decode indexing mode
--
if md(7) = '0' then
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
st_ctrl <= pull_st;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr1_state;
when "0001" => -- ,R++
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
st_ctrl <= pull_st;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0111" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index8_state;
when "1001" => -- offset16,R
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index16_state;
when "1010" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
--
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel16_state;
when "1110" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when others =>
-- when "1111" => -- [,address]
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
st_ctrl <= pull_st;
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
-- return to previous state
st_ctrl <= pull_st;
next_state <= saved_state;
when lea_state => -- here on load effective address
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
when "0001" => -- leay
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when "0010" => -- leas
sp_ctrl <= load_sp;
when "0011" => -- leau
up_ctrl <= load_up;
when others =>
null;
end case;
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
-- Test condition for branch
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
null;
end case;
else
cond_true := (1 = 1); -- lbra, lbsr, bsr
end if;
if cond_true then
pc_ctrl <= load_pc;
end if;
next_state <= fetch_state;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write PC low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- write pc hi bytes
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
st_ctrl <= pull_st;
next_state <= saved_state;
when pull_return_hi_state =>
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= pull_st;
next_state <= saved_state;
when andcc_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
--
st_ctrl <= pull_st;
next_state <= saved_state;
when orcc_state =>
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
--
st_ctrl <= pull_st;
next_state <= saved_state;
when tfr_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
--
st_ctrl <= pull_st;
next_state <= saved_state;
when exg_state =>
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
-- call tranfer microcode
st_ctrl <= push_st;
return_state <= exg1_state;
next_state <= tfr_state;
when exg1_state =>
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
next_state <= fetch_state;
when mul_state =>
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
md_ctrl <= load_md;
next_state <= mulea_state;
when mulea_state =>
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
ea_ctrl <= load_ea;
next_state <= muld_state;
when muld_state =>
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
next_state <= mul0_state;
when mul0_state =>
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul1_state;
when mul1_state =>
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul2_state;
when mul2_state =>
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul3_state;
when mul3_state =>
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul4_state;
when mul4_state =>
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul5_state;
when mul5_state =>
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul6_state;
when mul6_state =>
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul7_state;
when mul7_state =>
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
-- idle address
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshs_pch_state;
when pshs_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= pshs_uph_state;
when pshs_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- idle sp
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= puls_upl_state;
when puls_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshu_pch_state;
when pshu_pch_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write sp low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
next_state <= pshu_sph_state;
when pshu_sph_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write dp
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- idle up
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- idle UP
-- idle bus
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
next_state <= rti_accb_state;
when rti_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
next_state <= rti_dp_state;
when rti_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_uph_state;
when rti_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= rti_upl_state;
when rti_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
next_state <= rti_pch_state;
when rti_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
next_state <= fetch_state;
--
-- here on IRQ or NMI interrupt
-- pre decrement the sp
-- Idle bus cycle
--
when int_nmiirq_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
next_state <= int_entire_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_entire_state =>
-- set entire flag
alu_ctrl <= alu_see;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
--
-- here on FIRQ interrupt
-- pre decrement the sp
-- Idle bus cycle
--
when int_firq_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
next_state <= int_fast_state;
--
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_fast_state =>
-- clear entire flag
alu_ctrl <= alu_cle;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
when int_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= int_uph_state;
when int_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_dp_state;
when int_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
case iv is
when NMI_VEC =>
next_state <= int_maskif_state;
when SWI_VEC =>
next_state <= int_maskif_state;
when FIRQ_VEC =>
next_state <= int_maskif_state;
when IRQ_VEC =>
next_state <= int_maski_state;
when SWI2_VEC =>
next_state <= vect_hi_state;
when SWI3_VEC =>
next_state <= vect_hi_state;
when others =>
if op_code = "00111100" then -- CWAI
next_state <= int_cwai_state;
else
next_state <= rti_cc_state; -- spurious interrupt, do a RTI
end if;
end case;
--
-- wait here for an inteerupt
--
when int_cwai_state =>
if (nmi_req = '1') and (nmi_ack='0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= int_maskif_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
end if;
--
-- FIRQ is level sensitive
--
if (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_maskif_state;
--
-- IRQ is level sensitive
--
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_maski_state;
else
iv_ctrl <= reset_iv;
next_state <= int_cwai_state;
end if;
end if;
when int_maski_state =>
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
when int_maskif_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
if (nmi_req = '1') and (nmi_ack='0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= int_nmiirq_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
end if;
--
-- FIRQ is level sensitive
--
if (firq = '1') then
if (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firq_state;
else
iv_ctrl <= reset_iv;
next_state <= fetch_state;
end if;
--
-- IRQ is level sensitive
--
elsif (irq = '1') then
if (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_nmiirq_state;
else
iv_ctrl <= reset_iv;
next_state <= fetch_state;
end if;
else
iv_ctrl <= reset_iv;
next_state <= sync_state;
end if;
end if;
when halt_state =>
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
when others => -- halt on undefine states
next_state <= error_state;
end case;
end process;
end rtl;
| gpl-3.0 | d23201b2c01485b29c76e403c26c50d4 | 0.470597 | 3.507604 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00461.vhd | 1 | 8,591 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00461
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.5 (2)
-- 7.2.5 (5)
-- 7.2.5 (6)
-- 7.2.5 (7)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00461
-- ENT00461(ARCH00461)
-- ENT00461_Test_Bench(ARCH00461_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
package PKG00461 is
-- integer definitions
subtype st_integer is integer range -2 ** 15 to 2 ** 20 ;
constant c_integer_1 : integer := 10 ;
constant c_integer_2 : integer := -7 ;
constant c_st_integer_1 : st_integer := 5 ;
constant c_st_integer_2 : st_integer := -4 ;
-- integer
type t_real is range -2.0E20 to 2.0E20 ;
subtype st_real is t_real range -2.0E15 to 2.0E20 ;
constant c_real_1 : real := 10.5 ;
constant c_real_2 : real := -7.3 ;
constant c_t_real_1 : t_real := 5.0 ;
constant c_t_real_2 : t_real := -3.5 ;
constant c_st_real_1 : st_real := 5.9 ;
constant c_st_real_2 : st_real := -4.1 ;
constant acceptable_error : real := 0.001 ;
constant t_acceptable_error : t_real := 0.001 ;
end PKG00461 ;
use WORK.STANDARD_TYPES ;
use WORK.PKG00461.ALL ;
entity ENT00461 is
generic (
i_integer_1 : integer := c_integer_1 ;
i_integer_2 : integer := c_integer_2 ;
i_st_integer_1 : st_integer := c_st_integer_1 ;
i_st_integer_2 : st_integer := c_st_integer_2 ;
i_real_1 : real := c_real_1 ;
i_real_2 : real := c_real_2 ;
i_t_real_1 : t_real := c_t_real_1 ;
i_t_real_2 : t_real := c_t_real_2 ;
i_st_real_1 : st_real := c_st_real_1 ;
i_st_real_2 : st_real := c_st_real_2
) ;
constant c2_real_1 : real :=
i_real_1 ** i_st_integer_1 ;
constant c2_real_2 : real :=
i_real_2 ** i_integer_1 ;
constant c2_real_3 : real :=
i_real_1 ** i_integer_2 ;
constant c2_real_4 : real :=
i_real_2 ** i_st_integer_2 ;
constant c2_t_real_1 : t_real :=
i_t_real_1 ** i_st_integer_1 ;
constant c2_t_real_2 : t_real :=
c_t_real_2 ** i_integer_1 ;
constant c2_t_real_3 : t_real :=
i_t_real_1 ** i_integer_2 ;
constant c2_t_real_4 : t_real :=
i_t_real_2 ** c_integer_2 ;
constant c2_st_real_1 : st_real :=
i_st_real_1 ** i_st_integer_1 ;
constant c2_st_real_2 : st_real :=
c_t_real_2 ** i_integer_1 ;
constant c2_st_real_3 : st_real :=
i_st_real_1 ** i_integer_2 ;
constant c2_st_real_4 : st_real :=
i_st_real_2 ** c_st_integer_2 ;
end ENT00461 ;
architecture ARCH00461 of ENT00461 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_real_1, v2_real_1 : real := i_real_1 ;
variable v_real_2, v2_real_2 : real := i_real_2 ;
variable v2_real_3, v2_real_4 : real ;
variable v_t_real_1, v2_t_real_1 : t_real := i_t_real_1 ;
variable v_t_real_2, v2_t_real_2 : t_real := i_t_real_2 ;
variable v2_t_real_3, v2_t_real_4 : t_real ;
variable v_st_real_1, v2_st_real_1 : st_real := i_st_real_1 ;
variable v_st_real_2, v2_st_real_2 : st_real := i_st_real_2 ;
variable v2_st_real_3, v2_st_real_4 : st_real ;
variable v_integer_1 : integer := i_integer_1 ;
variable v_integer_2 : integer := i_integer_2 ;
variable v_st_integer_1 : st_integer := i_st_integer_1 ;
variable v_st_integer_2 : st_integer := i_st_integer_2 ;
--
begin
-- static expression
case bool is
when (
abs ((c_real_1 ** c_st_integer_1 - 127628.1562)
/ (c_real_1 ** c_st_integer_1)) < acceptable_error and
abs ((c_real_2 ** c_integer_1 - 429762582.9)
/ (c_real_2 ** c_integer_1)) < acceptable_error and
abs ((c_real_1 ** c_integer_2 - 7.107E-8)
/ (c_real_1 ** c_integer_2)) < acceptable_error and
abs ((c_real_2 ** c_st_integer_2 - 3.52134E-4)
/ (c_real_2 ** c_st_integer_2)) < acceptable_error and
abs ((c_t_real_1 ** c_st_integer_1 - 3125.0)
/ (c_t_real_1 ** c_st_integer_1)) < t_acceptable_error and
abs ((c_t_real_2 ** c_integer_1 - 275854.74)
/ (c_t_real_2 ** c_integer_1)) < t_acceptable_error and
abs ((c_t_real_1 ** c_integer_2 - 1.28E-5)
/ (c_t_real_1 ** c_integer_2)) < t_acceptable_error and
abs ((c_t_real_2 ** c_integer_2 - (-1.554E-4))
/ (c_t_real_2 ** c_integer_2)) < t_acceptable_error and
abs ((c_st_real_1 ** c_st_integer_1 - 7.14924E3)
/ (c_st_real_1 ** c_st_integer_1)) < t_acceptable_error and
abs ((c_t_real_2 ** c_integer_1 - 2.7585473E5)
/ (c_t_real_2 ** c_integer_1)) < t_acceptable_error and
abs ((c_st_real_1 ** c_integer_2 - 4.0182E-6)
/ (c_st_real_1 ** c_integer_2)) < t_acceptable_error and
abs ((c_st_real_2 ** c_st_integer_2 - 3.539E-3)
/ (c_st_real_2 ** c_st_integer_2)) < t_acceptable_error
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct :=
abs ((c2_real_1 - 127628.1562) / c2_real_1) < acceptable_error and
abs ((c2_real_2 - 429762582.9) / c2_real_2) < acceptable_error and
abs ((c2_real_3 - 7.107E-8) / c2_real_3) < acceptable_error and
abs ((c2_real_4 - 3.52134E-4) / c2_real_4) < acceptable_error and
abs ((c2_t_real_1 - 3125.0) / c2_t_real_1) < t_acceptable_error and
abs ((c2_t_real_2 - 275854.74) / c2_t_real_1) < t_acceptable_error and
abs ((c2_t_real_3 - 1.28E-5) / c2_t_real_1) < t_acceptable_error and
abs ((c2_t_real_4 - (-1.554E-4)) / c2_t_real_1) < t_acceptable_error and
abs ((c2_st_real_1 - 7.14924E3) / c2_st_real_1) < t_acceptable_error and
abs ((c2_st_real_2 - 2.7585473E5) / c2_st_real_1) < t_acceptable_error and
abs ((c2_st_real_3 - 4.0182E-6) / c2_st_real_1) < t_acceptable_error and
abs ((c2_st_real_4 - 3.539E-3) / c2_st_real_1) < t_acceptable_error ;
-- dynamic expression
v2_real_1 :=
i_real_1 ** i_st_integer_1 ;
v2_real_2 :=
i_real_2 ** i_integer_1 ;
v2_real_3 :=
i_real_1 ** i_integer_2 ;
v2_real_4 :=
i_real_2 ** i_st_integer_2 ;
v2_t_real_1 :=
i_t_real_1 ** i_st_integer_1 ;
v2_t_real_2 :=
c_t_real_2 ** i_integer_1 ;
v2_t_real_3 :=
i_t_real_1 ** i_integer_2 ;
v2_t_real_4 :=
i_t_real_2 ** c_integer_2 ;
v2_st_real_1 :=
i_st_real_1 ** i_st_integer_1 ;
v2_st_real_2 :=
c_t_real_2 ** i_integer_1 ;
v2_st_real_3 :=
i_st_real_1 ** i_integer_2 ;
v2_st_real_4 :=
i_st_real_2 ** c_st_integer_2 ;
dyn_correct :=
abs ((v2_real_1 - 127628.1562) / v2_real_1) < acceptable_error and
abs ((v2_real_2 - 429762582.9) / v2_real_2) < acceptable_error and
abs ((v2_real_3 - 7.107E-8) / v2_real_3) < acceptable_error and
abs ((v2_real_4 - 3.52134E-4) / v2_real_4) < acceptable_error and
abs ((v2_t_real_1 - 3125.0) / v2_t_real_1) < t_acceptable_error and
abs ((v2_t_real_2 - 275854.74) / v2_t_real_1) < t_acceptable_error and
abs ((v2_t_real_3 - 1.28E-5) / v2_t_real_1) < t_acceptable_error and
abs ((v2_t_real_4 - (-1.554E-4)) / v2_t_real_1) < t_acceptable_error and
abs ((v2_st_real_1 - 7.14924E3) / v2_st_real_1) < t_acceptable_error and
abs ((v2_st_real_2 - 2.7585473E5) / v2_st_real_1) < t_acceptable_error and
abs ((v2_st_real_3 - 4.0182E-6) / v2_st_real_1) < t_acceptable_error and
abs ((v2_st_real_4 - 3.539E-3) / v2_st_real_1) < t_acceptable_error ;
STANDARD_TYPES.test_report ( "ARCH00461" ,
"** predefined for real base and integer exponent" ,
dyn_correct and cons_correct and gen_correct ) ;
wait ;
end process ;
end ARCH00461 ;
entity ENT00461_Test_Bench is
end ENT00461_Test_Bench ;
architecture ARCH00461_Test_Bench of ENT00461_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00461 ( ARCH00461 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00461_Test_Bench ;
| gpl-3.0 | 322c411e36d55494083063124dd0b449 | 0.536375 | 2.58843 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/sine_rom.vhd | 1 | 5,813 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: sine_rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY sine_rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END sine_rom;
ARCHITECTURE SYN OF sine_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "sine128.mif",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "sine128.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "sine128.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sine_rom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| apache-2.0 | 90f7d88dad13e5691c562ade359a4eb0 | 0.6556 | 3.610559 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_ilmb_cntlr_wrapper.vhd | 1 | 18,331 | -------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00003FFF",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 | 5b5beea171fbca0a5aa492f17738e19b | 0.615078 | 2.93296 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000017.vhd | 1 | 3,964 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00014_Test_Bench is
end ENT00014_Test_Bench;
architecture ARCH00014_Test_Bench of ENT00014_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type TimeVector is array (integer range <>) of time;
signal t : TimeVector(1 to 24);
begin
t(13) <= bv'Last_active;
t(14) <= ra'Last_active;
t(15) <= r'Last_active;
t(16) <= ea'Last_active;
t(17) <= e'Last_active;
t(18) <= I_sa'Last_active;
t(19) <= I_baa'Last_active;
t(20) <= I_saa'Last_active;
t(21) <= b1'Last_active;
t(22) <= b2'Last_active;
t(23) <= clk'Last_active;
t(24) <= clk2'Last_active;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00014_Test_Bench ; | gpl-3.0 | a2f8091a53c4e38e7c511e6bb55bc051 | 0.543391 | 2.439385 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/numeric_bit.vhdl | 1 | 90,179 | -- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
variable TOPBIT_assigned : boolean := false;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' and not TOPBIT_assigned then
TOPBIT := J;
TOPBIT_assigned := true;
end if;
-- оригинальный код с не поддержанным пока exit
-- if DENOM(J)='1' then
-- TOPBIT := J;
-- exit;
-- end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
| gpl-3.0 | 35c825e0d771276f0286cbf5964a4fc3 | 0.566698 | 3.922759 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00405.vhd | 1 | 22,007 | -- NEED RESULT: ARCH00405.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00405.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00405.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00405: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00405
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00405(ARCH00405)
-- ENT00405_Test_Bench(ARCH00405_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00405 is
end ENT00405 ;
--
--
architecture ARCH00405 of ENT00405 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec2_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_rec2_vector_select : select_type := 1 ;
signal st_rec3_vector_select : select_type := 1 ;
--
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(lowb).f2'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(lowb).f2 after 10 ns,
c_st_rec1_vector_1(lowb).f2 after 20 ns
when 1,
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when 2,
--
c_st_rec1_vector_1(lowb).f2 after 5 ns
when 3,
--
c_st_rec1_vector_1(lowb).f2 after 100 ns
when 4,
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_vector_1(lowb).f2 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_vector_cnt is
when 0
=> null ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_vector_select <= transport 2 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec2_vector_select <= transport 3 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 4 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 5 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_vector_savt <= transport Std.Standard.Now ;
chk_st_rec2_vector <= transport s_st_rec2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ;
wait until (not s_st_rec2_vector(lowb).f2'Quiet) and
(s_st_rec2_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_rec2_vector_select select
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(lowb).f2 after 10 ns,
c_st_rec2_vector_1(lowb).f2 after 20 ns
when 1,
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when 2,
--
c_st_rec2_vector_1(lowb).f2 after 5 ns
when 3,
--
c_st_rec2_vector_1(lowb).f2 after 100 ns
when 4,
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_vector_1(lowb).f2 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_vector_cnt is
when 0
=> null ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_vector_select <= transport 2 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec3_vector_select <= transport 3 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 4 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 5 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00405" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_vector_savt <= transport Std.Standard.Now ;
chk_st_rec3_vector <= transport s_st_rec3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ;
wait until (not s_st_rec3_vector(highb).f3'Quiet) and
(s_st_rec3_vector_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_rec3_vector_select select
s_st_rec3_vector(highb).f3 <=
c_st_rec3_vector_2(highb).f3 after 10 ns,
c_st_rec3_vector_1(highb).f3 after 20 ns
when 1,
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when 2,
--
c_st_rec3_vector_1(highb).f3 after 5 ns
when 3,
--
c_st_rec3_vector_1(highb).f3 after 100 ns
when 4,
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_vector_1(highb).f3 after 40 ns when 6 ;
--
end ARCH00405 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00405_Test_Bench is
end ENT00405_Test_Bench ;
--
--
architecture ARCH00405_Test_Bench of ENT00405_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00405 ( ARCH00405 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00405_Test_Bench ;
| gpl-3.0 | 690731496d5733056196ac0f6fece806 | 0.507748 | 3.275826 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00362.vhd | 1 | 6,253 | -- NEED RESULT: ARCH00362.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00362: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00362: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00362
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00362(ARCH00362)
-- ENT00362_Test_Bench(ARCH00362_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00362 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00362 ;
--
--
architecture ARCH00362 of ENT00362 is
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00362.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_vector_select <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr1_vector_select <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00362" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00362" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00362" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_vector_savt <= transport Std.Standard.Now ;
chk_st_arr1_vector <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_vector_cnt <= transport s_st_arr1_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when st_arr1_vector_select = 1 else
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when st_arr1_vector_select = 2 else
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
end ARCH00362 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00362_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00362_Test_Bench ;
--
--
architecture ARCH00362_Test_Bench of ENT00362_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00362 ( ARCH00362 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00362_Test_Bench ;
| gpl-3.0 | 51cca7ab2d3607566fe450d960295fd6 | 0.527587 | 3.229855 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00169.vhd | 1 | 20,008 | -- NEED RESULT: ARCH00169.P1: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00169.P2: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169.P3: Multi inertial transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00169: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00169: One inertial transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00169: Inertial semantics check on a signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00169
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00169(ARCH00169)
-- ENT00169_Test_Bench(ARCH00169_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00169 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_rec3_vector(lowb).f2 <=
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00169" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00169 ;
--
architecture ARCH00169 of ENT00169 is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00169 ;
--
entity ENT00169_Test_Bench is
end ENT00169_Test_Bench ;
--
architecture ARCH00169_Test_Bench of ENT00169_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00169 ( ARCH00169 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00169_Test_Bench ;
| gpl-3.0 | a864b0997b42f97e14634677f3d45f0b | 0.527589 | 3.650429 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00136.vhd | 1 | 86,764 | -- NEED RESULT: ARCH00136.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00136
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00136(ARCH00136)
-- ENT00136_Test_Bench(ARCH00136_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00136 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_boolean : inout boolean ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_boolean : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= -- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_bit : inout bit ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_bit : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_1 after 100 ns ;
--
when 5
=> correct :=
s_bit = c_bit_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 6
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= -- Last transaction above is marked
c_bit_1 after 40 ns ;
--
when 7
=> correct :=
s_bit = c_bit_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_severity_level : inout severity_level ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_severity_level : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= -- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_character : inout character ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_character : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_1 after 100 ns ;
--
when 5
=> correct :=
s_character = c_character_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 6
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= -- Last transaction above is marked
c_character_1 after 40 ns ;
--
when 7
=> correct :=
s_character = c_character_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1 : inout st_enum1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= -- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_integer : inout integer ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_integer : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_1 after 100 ns ;
--
when 5
=> correct :=
s_integer = c_integer_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 6
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= -- Last transaction above is marked
c_integer_1 after 40 ns ;
--
when 7
=> correct :=
s_integer = c_integer_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1 : inout st_int1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= -- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_time : inout time ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_time : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_1 after 100 ns ;
--
when 5
=> correct :=
s_time = c_time_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 6
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= -- Last transaction above is marked
c_time_1 after 40 ns ;
--
when 7
=> correct :=
s_time = c_time_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1 : inout st_phys1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= -- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_real : inout real ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_real : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_1 after 100 ns ;
--
when 5
=> correct :=
s_real = c_real_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 6
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= -- Last transaction above is marked
c_real_1 after 40 ns ;
--
when 7
=> correct :=
s_real = c_real_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1 : inout st_real1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= -- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= -- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= -- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= -- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1 : inout st_arr1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= -- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2 : inout st_arr2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= -- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3 : inout st_arr3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= -- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00136" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00136 ;
--
architecture ARCH00136 of ENT00136 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_boolean,
counter,
correct,
savtime,
chk_boolean
) ;
wait until (not s_boolean'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_bit,
counter,
correct,
savtime,
chk_bit
) ;
wait until (not s_bit'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_severity_level,
counter,
correct,
savtime,
chk_severity_level
) ;
wait until (not s_severity_level'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_character,
counter,
correct,
savtime,
chk_character
) ;
wait until (not s_character'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1,
counter,
correct,
savtime,
chk_st_enum1
) ;
wait until (not s_st_enum1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_integer,
counter,
correct,
savtime,
chk_integer
) ;
wait until (not s_integer'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1,
counter,
correct,
savtime,
chk_st_int1
) ;
wait until (not s_st_int1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_time,
counter,
correct,
savtime,
chk_time
) ;
wait until (not s_time'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1,
counter,
correct,
savtime,
chk_st_phys1
) ;
wait until (not s_st_phys1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_real,
counter,
correct,
savtime,
chk_real
) ;
wait until (not s_real'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1,
counter,
correct,
savtime,
chk_st_real1
) ;
wait until (not s_st_real1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1,
counter,
correct,
savtime,
chk_st_arr1
) ;
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2,
counter,
correct,
savtime,
chk_st_arr2
) ;
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3,
counter,
correct,
savtime,
chk_st_arr3
) ;
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00136 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00136_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00136_Test_Bench ;
--
architecture ARCH00136_Test_Bench of ENT00136_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00136 ( ARCH00136 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00136_Test_Bench ;
| gpl-3.0 | 020cfbc945d485e6a7be1a456ac2b008 | 0.488901 | 4.02132 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00060.vhd | 1 | 5,092 | -- NEED RESULT: ARCH00060.P1: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P2: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P3: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P4: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P5: Body of 'for' loop is executed once for each value in the discrete range passed
-- NEED RESULT: ARCH00060.P6: Body of 'for' loop is executed once for each value in the discrete range passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00060
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00060)
-- ENT00060_Test_Bench(ARCH00060_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00060 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in boolean loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00060.P1" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in bit loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(bit'Pos (bit'High) -
bit'Pos (bit'Low) + 1) ;
test_report ( "ARCH00060.P2" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in severity_level loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(severity_level'Pos (severity_level'High) -
severity_level'Pos (severity_level'Low) + 1) ;
test_report ( "ARCH00060.P3" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in character loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(character'Pos (character'High) -
character'Pos (character'Low) + 1) ;
test_report ( "ARCH00060.P4" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P4 ;
--
P5 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in st_enum1 loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(st_enum1'Pos (st_enum1'High) -
st_enum1'Pos (st_enum1'Low) + 1) ;
test_report ( "ARCH00060.P5" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P5 ;
--
P6 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in st_int1 loop
counter := counter + 1 ;
end loop L1 ;
correct := counter =
(st_int1'Pos (st_int1'High) -
st_int1'Pos (st_int1'Low) + 1) ;
test_report ( "ARCH00060.P6" ,
"Body of 'for' loop is executed once " &
"for each value in the discrete range",
correct ) ;
--
end process P6 ;
--
--
end ARCH00060 ;
--
entity ENT00060_Test_Bench is
end ENT00060_Test_Bench ;
--
architecture ARCH00060_Test_Bench of ENT00060_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00060 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00060_Test_Bench ;
| gpl-3.0 | 329d386fc78ec72f588858f14a92217c | 0.5163 | 3.8605 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00228.vhd | 1 | 11,101 | -- NEED RESULT: ENT00228.P00228: Associated composite inout ports with static subtypes passed
-- NEED RESULT: ENT00228: Associated composite inout ports with static subtypes passed
-- NEED RESULT: ENT00228.P00228: Associated composite inout ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00228
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00228(ARCH00228)
-- ENT00228_Test_Bench(ARCH00228_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00228 is
port (
toggle : inout switch := down;
i_bit_vector_1, i_bit_vector_2 : inout bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : inout string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : inout t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : inout st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : inout t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : inout st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : inout t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : inout st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : inout t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : inout st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : inout t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : inout st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : inout t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : inout st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00228 ;
--
architecture ARCH00228 of ENT00228 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00228" ,
"Associated composite inout ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end ARCH00228 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00228_Test_Bench is
end ENT00228_Test_Bench ;
--
architecture ARCH00228_Test_Bench of ENT00228_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
toggle : inout switch ;
i_bit_vector_1, i_bit_vector_2 : inout bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : inout string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : inout t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : inout st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : inout t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : inout st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : inout t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : inout st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : inout t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : inout st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : inout t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : inout st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : inout t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : inout st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00228 ( ARCH00228 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
P00228 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00228.P00228" ,
"Associated composite inout ports with static subtypes",
correct) ;
end process P00228 ;
end block L1 ;
end ARCH00228_Test_Bench ;
| gpl-3.0 | ef29000c209bd4bbaed9505af6d7aa6b | 0.432754 | 2.783601 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00692.vhd | 1 | 27,976 | -- NEED RESULT: ARCH00692: Allocators with static composite qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00692
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (3)
-- 7.3.6 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00692)
-- ENT00692_Test_Bench(ARCH00692_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
--
architecture ARCH00692 of E00000 is
procedure p1 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
va_bit_vector_1 := new st_bit_vector ' (c_st_bit_vector_1) ;
va_string_1 := new st_string ' (c_st_string_1) ;
va_t_rec1_1 := new st_rec1 ' (c_st_rec1_1) ;
va_st_rec1_1 := new st_rec1 ' (c_st_rec1_1) ;
va_t_rec2_1 := new st_rec2 ' (c_st_rec2_1) ;
va_st_rec2_1 := new st_rec2 ' (c_st_rec2_1) ;
va_t_rec3_1 := new st_rec3 ' (c_st_rec3_1) ;
va_st_rec3_1 := new st_rec3 ' (c_st_rec3_1) ;
va_t_arr1_1 := new st_arr1 ' (c_st_arr1_1) ;
va_st_arr1_1 := new st_arr1 ' (c_st_arr1_1) ;
va_t_arr2_1 := new st_arr2 ' (c_st_arr2_1) ;
va_st_arr2_1 := new st_arr2 ' (c_st_arr2_1) ;
va_t_arr3_1 := new st_arr3 ' (c_st_arr3_1) ;
va_st_arr3_1 := new st_arr3 ' (c_st_arr3_1) ;
correct := correct and
va_bit_vector_1.all = c_st_bit_vector_1 ;
correct := correct and
va_string_1.all = c_st_string_1 ;
correct := correct and
va_t_rec1_1.all = c_st_rec1_1 ;
correct := correct and
va_st_rec1_1.all = c_st_rec1_1 ;
correct := correct and
va_t_rec2_1.all = c_st_rec2_1 ;
correct := correct and
va_st_rec2_1.all = c_st_rec2_1 ;
correct := correct and
va_t_rec3_1.all = c_st_rec3_1 ;
correct := correct and
va_st_rec3_1.all = c_st_rec3_1 ;
correct := correct and
va_t_arr1_1.all = c_st_arr1_1 ;
correct := correct and
va_st_arr1_1.all = c_st_arr1_1 ;
correct := correct and
va_t_arr2_1.all = c_st_arr2_1 ;
correct := correct and
va_st_arr2_1.all = c_st_arr2_1 ;
correct := correct and
va_t_arr3_1.all = c_st_arr3_1 ;
correct := correct and
va_st_arr3_1.all = c_st_arr3_1 ;
test_report ( "ARCH00692" ,
"Allocators with static composite qualified expression" ,
correct) ;
end p1 ;
begin
process
begin
p1 ;
wait ;
end process ;
end ARCH00692 ;
--
entity ENT00692_Test_Bench is
end ENT00692_Test_Bench ;
--
architecture ARCH00692_Test_Bench of ENT00692_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00692 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00692_Test_Bench ;
| gpl-3.0 | 67f739782eb8f0096338f7351db7a839 | 0.534101 | 3.182346 | false | false | false | false |
grwlf/vsim | vhdl/assign1.vhd | 1 | 462 | entity main is
end entity main;
architecture main of main is
constant CYCLES : integer := 1000;
signal clk : integer := 0;
signal s : integer;
begin
main: process(clk)
variable a : integer;
begin
a := 1;
s <= 1;
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
| gpl-3.0 | 838a1143bf8d57963e221934cc0088bf | 0.634199 | 3.164384 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00148.vhd | 1 | 111,181 | -- NEED RESULT: ARCH00148.P1: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P2: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P3: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P4: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P5: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P6: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P7: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P8: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P9: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P10: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P11: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P12: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P13: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P14: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P15: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P16: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148.P17: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00148: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00148
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00148(ARCH00148)
-- ENT00148_Test_Bench(ARCH00148_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00148 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00148" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00148 ;
--
architecture ARCH00148 of ENT00148 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00148 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00148_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00148_Test_Bench ;
--
architecture ARCH00148_Test_Bench of ENT00148_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00148 ( ARCH00148 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00148_Test_Bench ;
| gpl-3.0 | f678665d50a32028e1f0834b18769d80 | 0.520305 | 3.596228 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_finals_buckets_if_ap_fifo.vhd | 2 | 2,841 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | 0af469162f0c262dfe388ee4d4108134 | 0.495248 | 3.637644 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00266.vhd | 1 | 2,926 | -- NEED RESULT: ARCH00266: Configuration declarations may or may not have matching ending name passed
-- NEED RESULT: ARCH00266: Configuration declarations need not have configuration declarative items passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00266
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3 (1)
-- 1.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00266(ARCH00266)
-- ENT00266_1(ARCH00266_1)
-- CONF00266
-- CONF00266_1
-- ENT00266_Test_Bench(ARCH00266_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00266 is
generic ( g3 : integer ) ;
port ( s3 : out integer ) ;
end ENT00266 ;
architecture ARCH00266 of ENT00266 is
component COMP1
end component ;
begin
C1 : COMP1;
end ARCH00266 ;
entity ENT00266_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00266_1 ;
architecture ARCH00266_1 of ENT00266_1 is
begin
s1 <= g1 ;
end ARCH00266_1 ;
configuration CONF00266 of WORK.ENT00266 is
for ARCH00266
for C1 : COMP1
use entity WORK.ENT00266_1 ( ARCH00266_1 )
generic map ( g3 )
port map ( s3 ) ;
end for ;
end for ;
end CONF00266 ;
configuration CONF00266_1 of WORK.ENT00266 is
for ARCH00266
for C1 : COMP1
use entity WORK.ENT00266_1 ( ARCH00266_1 )
generic map ( g3 )
port map ( s3 ) ;
end for ;
end for ;
end ;
use WORK.STANDARD_TYPES.all ;
entity ENT00266_Test_Bench is
end ENT00266_Test_Bench ;
architecture ARCH00266_Test_Bench of ENT00266_Test_Bench is
begin
L1:
block
constant c1 : integer := 5 ;
constant c2 : integer := 5 ;
signal s1, s2 : integer ;
component UUT
end component ;
for CIS1 : UUT use configuration WORK.CONF00266
generic map ( c1 )
port map ( s1 ) ;
for CIS2 : UUT use configuration WORK.CONF00266_1
generic map ( c2 )
port map ( s2 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
P00266 :
process ( s1, s2 )
begin
if s1 = c1 and s2 = c2 then
test_report ( "ARCH00266" ,
"Configuration declarations may or may not have"
& " matching ending name" ,
true ) ;
test_report ( "ARCH00266" ,
"Configuration declarations need not have"
& " configuration declarative items" ,
true ) ;
end if ;
end process P00266 ;
end block L1 ;
end ARCH00266_Test_Bench ;
| gpl-3.0 | c224cc358ffccd1bf5d41cf825e4fda2 | 0.537252 | 3.438308 | false | true | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MINIUART/miniuart.vhd | 1 | 8,131 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : MiniUart.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
-------------------------------------------------------------------------------
-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
-- Wishbone compatable.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MINIUART is
generic (
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- Wishbone signals
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O : out std_logic; -- Tx RS232 Line
RxD_PAD_I : in std_logic; -- Rx RS232 Line
ESC_O : out std_logic;
BREAK_O : out std_logic);
end MINIUART;
-- Architecture for UART for synthesis
architecture Behaviour of MINIUART is
component Counter
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
Count : in std_logic_vector (15 downto 0); -- Count revolution
O : out std_logic); -- Output
end component;
component RxUnit
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0)); -- Byte received
end component;
component TxUnit
port (
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component;
signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
signal RxData1 : std_logic_vector(7 downto 0);
signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
signal SReg : std_logic_vector(1 downto 0); -- Status register
signal CReg : std_logic_vector(7 downto 2); -- Control register
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
signal RxAv : std_logic; -- Data Received
signal TxBusy : std_logic; -- Transmiter Busy
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0 : std_logic; -- gnd signal
signal Sig1 : std_logic; -- vcc signal
signal Divisor : std_logic_vector(15 downto 0); -- Baud Rate
begin
sig0 <= '0';
sig1 <= '1';
Uart_Rxrate : Counter -- Baud Rate adjust
port map (BR_CLK_I, sig0, sig1, Divisor, EnabRx);
Uart_Txrate : Counter -- 4 Divider for Tx
port map (BR_CLK_I, Sig0, EnabRx, std_logic_vector(to_unsigned(4, 16)), EnabTx);
Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
IntTx_O <= not TxBusy;
IntRx_O <= RxAv;
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
-- 16MHz x 1M = 64ms
-- ESCctrl: process(WB_CLK_I)
-- variable count : unsigned(19 downto 0);
-- begin
-- if Rising_Edge(WB_CLK_I) then
-- if (WB_RST_I = '1') then
-- ESC_O <= '1';
-- count := (others => '0');
-- elsif RxData = X"1B" then
-- ESC_O <= '0';
-- count := (others => '1');
-- elsif count > 0 then
-- count := count - 1;
-- else
-- ESC_O <= '1';
-- end if;
-- end if;
-- end process;
BREAKctrl: process(WB_CLK_I)
variable count : unsigned(7 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
RxData1 <= RxData;
if (WB_RST_I = '1') then
BREAK_O <= '1';
count := (others => '0');
elsif RxData1 /= X"1A" and RxData = X"1A" and CReg(7) = '1' then
BREAK_O <= '0';
count := (others => '1');
elsif count > 0 then
count := count - 1;
else
BREAK_O <= '1';
end if;
end if;
end process;
ESC_O <= '0' when RxData = X"1B" and CReg(6) = '1' else '1';
-- Implements WishBone data exchange.
-- Clocked on rising edge. Synchronous Reset RST_I
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
variable StatM : std_logic_vector(4 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
if (WB_RST_I = '1') then
ReadA <= '0';
LoadA <= '0';
Divisor <= std_logic_vector(to_unsigned(MainClockSpeed / 4 / DefaultBaud, 16));
CReg(7 downto 2) <= "000000";
else
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
TxData <= WB_DAT_I;
LoadA <= '1'; -- Load signal
else LoadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
ReadA <= '1'; -- Read signal
else ReadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "01") then -- Write Control
CReg <= WB_DAT_I(7 downto 2);
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "10") then -- Write Divisor Low
Divisor(7 downto 0) <= WB_DAT_I;
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "11") then -- Write Divisor High
Divisor(15 downto 8) <= WB_DAT_I;
end if;
end if;
end if;
end process;
WB_ACK_O <= WB_STB_I;
WB_DAT_O <=
RxData when WB_ADR_I = "00" else -- Read Byte from Rx
CReg & SReg when WB_ADR_I = "01" else -- Read Control/Status Reg
Divisor(7 downto 0) when WB_ADR_I = "10" else -- Read Divisor Low
Divisor(15 downto 8) when WB_ADR_I = "11" else -- Read Divisor Low
"00000000";
end Behaviour;
| apache-2.0 | 6cefe4de6ba955e390fb93a7bcac9f03 | 0.499201 | 3.533681 | false | false | false | false |
wsoltys/AtomFpga | src/Atomic_top.vhd | 1 | 6,684 | --------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Atomic_top.vhf
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: Atomic_top
--Device: spartan3A
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Atomic_top is
port (clk_25M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
CE1 : out std_logic;
RAMWRn : out std_logic;
RAMOEn : out std_logic;
RamA : out std_logic_vector (15 downto 0);
RamD : inout std_logic_vector (15 downto 0);
audiol : out std_logic;
audioR : out std_logic;
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic);
end Atomic_top;
architecture behavioral of Atomic_top is
component dcm2
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component dcm3
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component InternalROM
port (
CLK : in std_logic;
ADDR : in std_logic_vector(16 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end component;
component Atomic_core
generic (
CImplSDDOS : boolean;
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
clk_vga : in std_logic;
clk_16M00 : in std_logic;
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERSTn : in std_logic;
IRSTn : out std_logic;
SDMISO : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
RamCE : out std_logic;
RomCE : out std_logic;
Phi2 : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (16 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout: in std_logic_vector (7 downto 0);
audiol : out std_logic;
audioR : out std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end component;
signal clk_12M58 : std_logic;
signal clk_16M00 : std_logic;
signal clk_32M00 : std_logic;
signal Phi2 : std_logic;
signal RomDout : std_logic_vector (7 downto 0);
signal RamCE : std_logic;
signal RomCE : std_logic;
signal ExternA : std_logic_vector (16 downto 0);
signal ExternWE : std_logic;
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
begin
inst_dcm2 : dcm2 port map(
CLKIN_IN => clk_25M00,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_dcm3 : dcm3 port map (
CLKIN_IN => clk_16M00,
CLK0_OUT => clk_32M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
rom_c000_ffff : InternalROM port map(
CLK => clk_16M00,
ADDR => ExternA,
DATA => RomDout
);
inst_Atomic_core : Atomic_core
generic map (
CImplSDDOS => true,
CImplGraphicsExt => false,
CImplSoftChar => false,
CImplSID => true,
CImplVGA80x40 => false,
CImplHWScrolling => false,
CImplMouse => false,
CImplUart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clk_25M00,
clk_16M00 => clk_16M00,
clk_32M00 => clk_32M00,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
ERSTn => ERSTn,
IRSTn => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
RamCE => RamCE,
RomCE => RomCE,
Phi2 => Phi2,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
audiol => audiol,
audioR => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => '1',
uart_TxD => open,
LED1 => open,
LED2 => open
);
CE1 <= not RAMCE;
RAMWRn <= not (ExternWE and Phi2);
RAMOEn <= not RAMCE;
RamD <= ExternDin & ExternDin when ExternWE = '1' else "ZZZZZZZZZZZZZZZZ";
ExternDout <= RamD(7 downto 0) when RamCE = '1' else
RomDout when RomCE = '1' else
"11110001";
RamA <= '0' & ExternA(14 downto 0);
end behavioral;
| apache-2.0 | c599b1a45ea1d2ebe4fa33741ff95c77 | 0.463046 | 3.680617 | false | false | false | false |
KaskMartin/Digiloogika_ALU | ALU_FPGA/toplevel.vhd | 1 | 3,598 | ----------------------------------------------------------------------------------
-- Home assignement in "Digitaalloogika ja -süsteemid" (http://priit.ati.ttu.ee/?page_id=2320)
-- ALU FPGA synthesis on Playground FPGA
-- (Playground FPGA toplevel module by Keijo Lass, Priit Ruberg)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity toplevel is
port(
clk: in std_logic; --clock in, 100MHz
JA: in std_logic_vector(7 downto 0); --JA port input
JB: in std_logic_vector(7 downto 0); --JB port input
JC: in std_logic_vector(7 downto 0); --JC port input
JD: in std_logic_vector(7 downto 0); --JD port input
LED: out std_logic_vector(7 downto 0)); --LEDs
end toplevel;
architecture RTL of toplevel is
--the component for PORTER is created
component PORTER is
Port(JA_P: in std_logic_vector(7 downto 0); --JA port input
JB_P: in std_logic_vector(7 downto 0); --JB port input
JC_P: in std_logic_vector(7 downto 0); --JC port input
-- JD_P: in std_logic_vector(7 downto 0); --JD port input
LED_P: out std_logic_vector(7 downto 0); --LEDs
a : out STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : out STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : out STD_LOGIC_VECTOR (1 downto 0);
o : in STD_LOGIC_VECTOR (3 downto 0));
end component;
--the component for first function is created
component func1 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for second function is created
component func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for third function is created
component func3 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for forth function is created
component func4 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for mux is created
component mux is
Port (m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F2_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F3_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F4_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
m_o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
signal a, b, o : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal op : STD_LOGIC_VECTOR (1 downto 0):="00";
signal F1_out, F2_out, F3_out, F4_out : STD_LOGIC_VECTOR (3 downto 0):="0000";
begin --beginning of the architecture
--components are port mapped according to workinstructions: http://priit.ati.ttu.ee/?page_id=2320
PO : PORTER port map (JA_P => JA,
JB_P => JB,
JC_P => JC,
-- JD_P => JD,
LED_P => LED,
a => a,
b => b,
op => op,
o => o);
F1 : func1 port map (a => a,
b => b ,
o => F1_out);
F2 : func2 port map (a => a,
o => F2_out);
F3 : func3 port map (a => a,
b => b ,
o => F3_out);
F4 : func4 port map (a => a,
b => b,
o => F4_out);
MUX_tl : mux port map (m_op => op,
F1_in => F1_out,
F2_in => F2_out,
F3_in => F3_out,
F4_in => F4_out,
m_o => o);
end RTL; | mit | 13dd3dd61b800e00b2b61310326eddbf | 0.579767 | 2.939542 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/impl/vhdl/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.vhd | 3 | 9,512 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 | b00d2b8649c943f98334cd22b683960b | 0.608705 | 2.867651 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00386.vhd | 1 | 70,428 | -- NEED RESULT: ARCH00386.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00386: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00386
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00386(ARCH00386)
-- ENT00386_Test_Bench(ARCH00386_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386 is
end ENT00386 ;
--
--
architecture ARCH00386 of ENT00386 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00386" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1(highb,false) after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1(highb,false) after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns ;
--
end ARCH00386 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00386_Test_Bench is
end ENT00386_Test_Bench ;
--
--
architecture ARCH00386_Test_Bench of ENT00386_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00386 ( ARCH00386 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00386_Test_Bench ;
| gpl-3.0 | ee6a2368f0909c0231183aecd1986e21 | 0.514497 | 3.504578 | false | false | false | false |
jairov4/accel-oil | solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9.vhd | 2 | 3,336 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0 is
signal tmp_product : std_logic_vector(24 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(24 - 1 downto 0);
signal a_reg : std_logic_vector(16 - 1 downto 0);
signal b_reg : std_logic_vector(8 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(24 - 1 downto 0);
signal buff1 : std_logic_vector(24 - 1 downto 0);
signal buff2 : std_logic_vector(24 - 1 downto 0);
signal buff3 : std_logic_vector(24 - 1 downto 0);
signal buff4 : std_logic_vector(24 - 1 downto 0);
signal buff5 : std_logic_vector(24 - 1 downto 0);
signal buff6 : std_logic_vector(24 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff6;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 24));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9 is
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0_U : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | e181b5beeb92b7748433ed414368dfb1 | 0.555755 | 3.270588 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00533.vhd | 1 | 1,761 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00533
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (2)
-- 14.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00533)
-- ENT00533_Test_Bench(ARCH00533_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00533 of E00000 is
begin
P :
process
type ary is array ( integer range <> ) of integer ;
subtype st_ary is ary (1 to 10) ;
type rec is record
a,b : integer ;
end record ;
subtype st_rec is rec ;
attribute ary_attr : integer ;
attribute ary_attr of ary : type is 10 ;
attribute rec_attr : integer ;
attribute rec_attr of rec : type is 20 ;
begin
test_report ( "ARCH00533" ,
"Base attribute" ,
(ary'ary_attr = 10) and
(rec'rec_attr = 20) and
(t_enum1'base'leftof(en2) = en1) and
(st_enum1'rightof(en2) = en1) and
(st_enum1'base'leftof(en2) = en1) and
(t_int1'base'rightof(-1) = 0) and
(st_int1'base'leftof(1) = 0)
) ;
wait ;
end process P ;
end ARCH00533 ;
--
entity ENT00533_Test_Bench is
end ENT00533_Test_Bench ;
architecture ARCH00533_Test_Bench of ENT00533_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00533 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00533_Test_Bench ;
--
| gpl-3.0 | 1a27f28ef91be101faf37bf7df75b002 | 0.521863 | 3.267161 | false | true | false | false |
grwlf/vsim | vhdl_ct/WORK/standard_types.vhd | 1 | 30,020 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- standard entity
--
entity e00000 is
end entity e00000;
--
package standard_types is
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
function bf_boolean(to_resolve : boolean_vector) return boolean ;
subtype rboolean is bf_boolean boolean ;
function bf_bit(to_resolve : bit_vector) return bit ;
--
subtype rbit is bf_bit bit ;
--
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level ;
--
subtype rseverity_level is bf_severity_level severity_level ;
function bf_character(to_resolve : string) return character ;
--
subtype rcharacter is bf_character character ;
--
function bf_enum1(to_resolve : enum1_vector) return st_enum1 ;
--
subtype rst_enum1 is bf_enum1 st_enum1 ;
--
function bf_integer(to_resolve : integer_vector) return integer ;
--
subtype rinteger is bf_integer integer ;
--
function bf_int1(to_resolve : int1_vector) return st_int1 ;
--
subtype rst_int1 is bf_int1 st_int1 ;
--
function bf_time(to_resolve : time_vector) return time ;
--
subtype rtime is bf_time time ;
--
function bf_phys1(to_resolve : phys1_vector) return st_phys1 ;
--
subtype rst_phys1 is bf_phys1 st_phys1 ;
--
function bf_real(to_resolve : real_vector) return real ;
--
subtype rreal is bf_real real ;
--
function bf_real1(to_resolve : real1_vector) return st_real1 ;
--
subtype rst_real1 is bf_real1 st_real1 ;
--
function bf_rec1(to_resolve : rec1_vector) return st_rec1 ;
--
subtype rst_rec1 is bf_rec1 st_rec1 ;
--
function bf_rec2(to_resolve : rec2_vector) return st_rec2 ;
--
subtype rst_rec2 is bf_rec2 st_rec2 ;
--
function bf_arr1(to_resolve : arr1_vector) return st_arr1 ;
--
subtype rst_arr1 is bf_arr1 st_arr1 ;
--
function bf_arr2(to_resolve : arr2_vector) return st_arr2 ;
--
subtype rst_arr2 is bf_arr2 st_arr2 ;
--
function bf_rec3(to_resolve : rec3_vector) return st_rec3 ;
--
subtype rst_rec3 is bf_rec3 st_rec3 ;
--
function bf_arr3(to_resolve : arr3_vector) return st_arr3 ;
--
subtype rst_arr3 is bf_arr3 st_arr3 ;
--
constant d_boolean : boolean := boolean'left ;
constant d_bit : bit := bit'left ;
constant d_severity_level : severity_level := severity_level'left ;
constant d_character : character := character'left ;
constant d_t_enum1 : t_enum1 := t_enum1'left ;
constant d_st_enum1 : st_enum1 := st_enum1'left ;
constant d_integer : integer := integer'left ;
constant d_t_int1 : t_int1 := t_int1'left ;
constant d_st_int1 : st_int1 := st_int1'left ;
constant d_time : time := time'left ;
constant d_t_phys1 : t_phys1 := t_phys1'left ;
constant d_st_phys1 : st_phys1 := st_phys1'left ;
constant d_real : real := real'left ;
constant d_t_real1 : t_real1 := t_real1'left ;
constant d_st_real1 : st_real1 := st_real1'left ;
constant d_st_bit_vector : st_bit_vector :=
(others => bit'left) ;
constant d_st_string : st_string :=
(others => character'left) ;
constant d_t_rec1 : t_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_st_rec1 : st_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_t_rec2 : t_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_rec2 : st_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_arr1 : st_arr1 :=
(others => st_int1'left) ;
constant d_st_arr2 : st_arr2 :=
(others => (others => d_st_arr1) ) ;
constant d_t_rec3 : t_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_rec3 : st_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_arr3 : st_arr3 :=
(others => (others => d_st_rec3) ) ;
-- file types
type f_boolean is file of boolean ;
type f_bit is file of bit ;
type f_character is file of character ;
type f_integer is file of integer ;
type f_time is file of time ;
type f_real is file of real ;
-- with constraints
type f_st_enum1 is file of st_enum1 ;
type f_st_int1 is file of st_int1 ;
type f_st_phys1 is file of st_phys1 ;
type f_st_rec1 is file of st_rec1 ;
type f_st_rec2 is file of st_rec2 ;
type f_st_arr1 is file of st_arr1 ;
--
-- without constraints
type f_enum1 is file of t_enum1 ;
type f_int1 is file of t_int1 ;
type f_phys1 is file of t_phys1 ;
type f_rec1 is file of t_rec1 ;
type f_rec2 is file of t_rec2 ;
type f_arr1 is file of t_arr1 ;
--
-- access types
type a_boolean is access boolean ;
type a_bit is access bit ;
type a_severity_level is access severity_level ;
type a_character is access character ;
type a_t_enum1 is access t_enum1 ;
type a_st_enum1 is access st_enum1 ;
type a_integer is access integer ;
type a_t_int1 is access t_int1 ;
type a_st_int1 is access st_int1 ;
type a_time is access time ;
type a_t_phys1 is access t_phys1 ;
type a_st_phys1 is access st_phys1 ;
type a_real is access real ;
type a_t_real1 is access t_real1 ;
type a_st_real1 is access st_real1 ;
type a_bit_vector is access bit_vector ;
type a_string is access string ;
type a_t_rec1 is access t_rec1 ;
type a_st_rec1 is access st_rec1 ;
type a_t_rec2 is access t_rec2 ;
type a_st_rec2 is access st_rec2 ;
type a_t_rec3 is access t_rec3 ;
type a_st_rec3 is access st_rec3 ;
type a_t_arr1 is access t_arr1 ;
type a_st_arr1 is access st_arr1 ;
type a_t_arr2 is access t_arr2 ;
type a_st_arr2 is access st_arr2 ;
type a_t_arr3 is access t_arr3 ;
type a_st_arr3 is access st_arr3 ;
type a_st_boolean_vector is access st_boolean_vector ;
type a_st_bit_vector is access st_bit_vector ;
type a_st_severity_level_vector is access st_severity_level_vector ;
type a_st_string is access st_string ;
type a_st_enum1_vector is access st_enum1_vector ;
type a_st_integer_vector is access st_integer_vector ;
type a_st_int1_vector is access st_int1_vector ;
type a_st_time_vector is access st_time_vector ;
type a_st_phys1_vector is access st_phys1_vector ;
type a_st_real_vector is access st_real_vector ;
type a_st_real1_vector is access st_real1_vector ;
type a_st_rec1_vector is access st_rec1_vector ;
type a_st_rec2_vector is access st_rec2_vector ;
type a_st_arr1_vector is access st_arr1_vector ;
type a_st_arr2_vector is access st_arr2_vector ;
type a_st_rec3_vector is access st_rec3_vector ;
type a_st_arr3_vector is access st_arr3_vector ;
--
signal s_rboolean : rboolean := c_boolean_1 ;
signal s_rbit : rbit := c_bit_1 ;
signal s_rseverity_level : rseverity_level := c_severity_level_1 ;
signal s_rcharacter : rcharacter := c_character_1 ;
signal s_rst_enum1 : rst_enum1 := c_st_enum1_1 ;
signal s_rinteger : rinteger := c_integer_1 ;
signal s_rst_int1 : rst_int1 := c_st_int1_1 ;
signal s_rtime : rtime := c_time_1 ;
signal s_rst_phys1 : rst_phys1 := c_st_phys1_1 ;
signal s_rreal : rreal := c_real_1 ;
signal s_rst_real1 : rst_real1 := c_st_real1_1 ;
signal s_rst_rec1 : rst_rec1 := c_st_rec1_1 ;
signal s_rst_rec2 : rst_rec2 := c_st_rec2_1 ;
signal s_rst_arr1 : rst_arr1 := c_st_arr1_1 ;
signal s_rst_arr2 : rst_arr2 := c_st_arr2_1 ;
signal s_rst_rec3 : rst_rec3 := c_st_rec3_1 ;
signal s_rst_arr3 : rst_arr3 := c_st_arr3_1 ;
--
--
procedure print ( message : string ) ;
--
procedure test_report( design_unit : string ;
message : string ;
condition : boolean ) ;
--
type switch is (up, down) ;
signal toggle : switch := down ;
end standard_types ;
--
--
package body standard_types is
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
--
procedure print ( message : string ) is
begin
assert false
report message
severity note ;
end print ;
--
procedure test_report( design_unit : string ;
message : string ;
condition : boolean ) is
begin
if condition then
print ( design_unit & ": " & message & " passed" ) ;
else
print ( design_unit & ": " & message & " failed" ) ;
end if ;
end test_report ;
--
end standard_types ;
| gpl-3.0 | c9b5e2cdb57d2977d2c319128d777d43 | 0.586909 | 3.09708 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00646.vhd | 1 | 2,728 | -- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of an entity passed
-- NEED RESULT: ARCH00646: The keyword 'Signal' is optional in a signal declaration for a formal port of a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00646
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00646(ARCH00646)
-- ENT00646_Test_Bench(ARCH00646_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646 is
port ( G1 : in integer := 0 ;
signal G2, G3, G4 : in integer := 3 ) ;
end ENT00646 ;
--
architecture ARCH00646 of ENT00646 is
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
wait ;
end process ;
L1 :
block
port ( BG1 : in integer := 0 ;
signal BG2, BG3, BG4 : in integer := 3 ) ;
port map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00646" ,
"The keyword 'Signal' is optional in a "&
"signal declaration for a formal port of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00646 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00646_Test_Bench is
end ENT00646_Test_Bench ;
architecture ARCH00646_Test_Bench of ENT00646_Test_Bench is
begin
L1:
block
component UUT
port ( CG1 : in integer ;
signal CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00646 ( ARCH00646 )
port map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
signal S1 : integer := 1 ;
signal S2 : integer := 2 ;
signal S4 : integer := 4 ;
begin
CIS1 : UUT
port map ( S1, S2, S4 );
end block L1 ;
end ARCH00646_Test_Bench ;
--
| gpl-3.0 | f14cc8f460aae7981d08305d58884e97 | 0.46261 | 3.696477 | false | true | false | false |
dcliche/mdsynth | rtl/src/pia_timer.vhd | 1 | 15,664 | --===========================================================================--
-- --
-- pia_timer.vhd - Synthesizable Parallel Interface Adapter with Timer --
-- --
--===========================================================================--
--
-- File name : pia_timer.vhd
--
-- Entity name : pia_timer
--
-- Purpose : Implements 2 x 8 bit parallel I/O ports
-- with 8 bit presetable counter.
-- Port A Data = output connected to presettable counter input
-- Port B Data = input connected to counter output
-- Used with Digilent Spartan 3E starter board
-- to implement a single step trace function.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
-- unisim.vcomponents
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Register Memory Map
--
-- Base + $00 - Port A Data & Direction register
-- Base + $01 - Port A Control register
-- Base + $02 - Port B Data & Direction Direction Register
-- Base + $03 - Port B Control Register
--
-- Copyright (C) 2004 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Description
-- 0.0 John Kent 1st May 2004 Initial version developed from ioport.vhd
--
-- 1.0 John Kent 22nd April 2006 Removed I/O ports and hard wired a binary
-- down counter. Port A is the preset output.
-- Port B is the timer count input.
-- CA1 & CB1 are interrupt inputs
-- CA2 is the counter load (active low)
-- CB2 is the counter reset (active high)
-- It may be necessary to offset the counter
-- to compensate for differences in cpu cycle
-- times between FPGA and real 6809 systems.
--
-- 1.1 John Kent 24th May 2006 Modified counter to subtract one from preset
-- so FPGA version of the CMC_BUG monitor is
-- compatible with the reference design.
--
-- 1.2 John Kent 30th May 2010 Revised header and added updated GPL
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data & Direction register
-- IO + $01 - Port A Control register
-- IO + $02 - Port B Data & Direction Direction Register
-- IO + $03 - Port B Control Register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pia_timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irqa : out std_logic;
irqb : out std_logic
);
end;
architecture pia_arch of pia_timer is
signal pa : std_logic_vector(7 downto 0);
signal porta_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal porta_ctrl : std_logic_vector(5 downto 0);
signal porta_read : std_logic;
signal pb : std_logic_vector(7 downto 0);
signal portb_ddr : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portb_ctrl : std_logic_vector(5 downto 0);
signal portb_read : std_logic;
signal portb_write : std_logic;
signal ca1 : std_logic;
signal ca1_del : std_logic;
signal ca1_rise : std_logic;
signal ca1_fall : std_logic;
signal ca1_edge : std_logic;
signal irqa1 : std_logic := '0';
signal ca2 : std_logic;
signal ca2_del : std_logic;
signal ca2_rise : std_logic;
signal ca2_fall : std_logic;
signal ca2_edge : std_logic;
signal irqa2 : std_logic := '0';
signal ca2_out : std_logic;
signal cb1 : std_logic;
signal cb1_del : std_logic;
signal cb1_rise : std_logic;
signal cb1_fall : std_logic;
signal cb1_edge : std_logic;
signal irqb1 : std_logic := '0';
signal cb2 : std_logic;
signal cb2_del : std_logic;
signal cb2_rise : std_logic;
signal cb2_fall : std_logic;
signal cb2_edge : std_logic;
signal irqb2 : std_logic := '0';
signal cb2_out : std_logic;
-- 74193 down counter
signal timer : std_logic_vector(7 downto 0);
begin
--------------------------------
--
-- read I/O port
--
--------------------------------
pia_read : process( addr, cs,
irqa1, irqa2, irqb1, irqb2,
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
pa, pb )
variable count : integer;
begin
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= pa(count);
end if;
porta_read <= cs;
end if;
end loop;
portb_read <= '0';
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= pb(count);
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
when others =>
null;
end case;
end process;
---------------------------------
--
-- Write I/O ports
--
---------------------------------
pia_write : process( clk, rst, addr, cs, rw, data_in,
porta_ctrl, portb_ctrl,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
porta_ddr, portb_ddr )
begin
if rst = '1' then
porta_ddr <= "00000000";
porta_data <= "00000000";
porta_ctrl <= "000000";
portb_ddr <= "00000000";
portb_data <= "00000000";
portb_ctrl <= "000000";
portb_write <= '0';
elsif clk'event and clk = '1' then
if cs = '1' and rw = '0' then
case addr is
when "00" =>
if porta_ctrl(2) = '0' then
porta_ddr <= data_in;
porta_data <= porta_data;
else
porta_ddr <= porta_ddr;
porta_data <= data_in;
end if;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "01" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= data_in(5 downto 0);
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "10" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
if portb_ctrl(2) = '0' then
portb_ddr <= data_in;
portb_data <= portb_data;
portb_write <= '0';
else
portb_ddr <= portb_ddr;
portb_data <= data_in;
portb_write <= '1';
end if;
portb_ctrl <= portb_ctrl;
when "11" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= data_in(5 downto 0);
portb_write <= '0';
when others =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end case;
else
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_data <= portb_data;
portb_ddr <= portb_ddr;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end if;
end if;
end process;
---------------------------------
--
-- CA1 Edge detect
--
---------------------------------
ca1_input : process( clk, rst, ca1, ca1_del,
ca1_rise, ca1_fall, ca1_edge,
irqa1, porta_ctrl, porta_read )
begin
if rst = '1' then
ca1_del <= '0';
ca1_rise <= '0';
ca1_fall <= '0';
ca1_edge <= '0';
irqa1 <= '0';
elsif clk'event and clk = '0' then
ca1_del <= ca1;
ca1_rise <= (not ca1_del) and ca1;
ca1_fall <= ca1_del and (not ca1);
if ca1_edge = '1' then
irqa1 <= '1';
elsif porta_read = '1' then
irqa1 <= '0';
else
irqa1 <= irqa1;
end if;
end if;
if porta_ctrl(1) = '0' then
ca1_edge <= ca1_fall;
else
ca1_edge <= ca1_rise;
end if;
end process;
---------------------------------
--
-- CA2 Edge detect
--
---------------------------------
ca2_input : process( clk, rst, ca2, ca2_del,
ca2_rise, ca2_fall, ca2_edge,
irqa2, porta_ctrl, porta_read )
begin
if rst = '1' then
ca2_del <= '0';
ca2_rise <= '0';
ca2_fall <= '0';
ca2_edge <= '0';
irqa2 <= '0';
elsif clk'event and clk = '0' then
ca2_del <= ca2;
ca2_rise <= (not ca2_del) and ca2;
ca2_fall <= ca2_del and (not ca2);
if porta_ctrl(5) = '0' and ca2_edge = '1' then
irqa2 <= '1';
elsif porta_read = '1' then
irqa2 <= '0';
else
irqa2 <= irqa2;
end if;
end if;
if porta_ctrl(4) = '0' then
ca2_edge <= ca2_fall;
else
ca2_edge <= ca2_rise;
end if;
end process;
---------------------------------
--
-- CA2 output control
--
---------------------------------
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
begin
if rst='1' then
ca2_out <= '0';
elsif clk'event and clk='0' then
case porta_ctrl(5 downto 3) is
when "100" => -- read PA clears, CA1 edge sets
if porta_read = '1' then
ca2_out <= '0';
elsif ca1_edge = '1' then
ca2_out <= '1';
else
ca2_out <= ca2_out;
end if;
when "101" => -- read PA clears, E sets
ca2_out <= not porta_read;
when "110" => -- set low
ca2_out <= '0';
when "111" => -- set high
ca2_out <= '1';
when others => -- no change
ca2_out <= ca2_out;
end case;
end if;
end process;
---------------------------------
--
-- CB1 Edge detect
--
---------------------------------
cb1_input : process( clk, rst, cb1, cb1_del,
cb1_rise, cb1_fall, cb1_edge,
irqb1, portb_ctrl, portb_read )
begin
if rst = '1' then
cb1_del <= '0';
cb1_rise <= '0';
cb1_fall <= '0';
cb1_edge <= '0';
irqb1 <= '0';
elsif clk'event and clk = '0' then
cb1_del <= cb1;
cb1_rise <= (not cb1_del) and cb1;
cb1_fall <= cb1_del and (not cb1);
if cb1_edge = '1' then
irqb1 <= '1';
elsif portb_read = '1' then
irqb1 <= '0';
else
irqb1 <= irqb1;
end if;
end if;
if portb_ctrl(1) = '0' then
cb1_edge <= cb1_fall;
else
cb1_edge <= cb1_rise;
end if;
end process;
---------------------------------
--
-- CB2 Edge detect
--
---------------------------------
cb2_input : process( clk, rst, cb2, cb2_del,
cb2_rise, cb2_fall, cb2_edge,
irqb2, portb_ctrl, portb_read )
begin
if rst = '1' then
cb2_del <= '0';
cb2_rise <= '0';
cb2_fall <= '0';
cb2_edge <= '0';
irqb2 <= '0';
elsif clk'event and clk = '0' then
cb2_del <= cb2;
cb2_rise <= (not cb2_del) and cb2;
cb2_fall <= cb2_del and (not cb2);
if portb_ctrl(5) = '0' and cb2_edge = '1' then
irqb2 <= '1';
elsif portb_read = '1' then
irqb2 <= '0';
else
irqb2 <= irqb2;
end if;
end if;
if portb_ctrl(4) = '0' then
cb2_edge <= cb2_fall;
else
cb2_edge <= cb2_rise;
end if;
end process;
---------------------------------
--
-- CB2 output control
--
---------------------------------
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
begin
if rst='1' then
cb2_out <= '0';
elsif clk'event and clk='0' then
case portb_ctrl(5 downto 3) is
when "100" => -- write PB clears, CA1 edge sets
if portb_write = '1' then
cb2_out <= '0';
elsif cb1_edge = '1' then
cb2_out <= '1';
else
cb2_out <= cb2_out;
end if;
when "101" => -- write PB clears, E sets
cb2_out <= not portb_write;
when "110" => -- set low
cb2_out <= '0';
when "111" => -- set high
cb2_out <= '1';
when others => -- no change
cb2_out <= cb2_out;
end case;
end if;
end process;
---------------------------------
--
-- IRQ control
--
---------------------------------
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
begin
irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
end process;
---------------------------------
--
-- 2 x 74193 binary down counter
--
---------------------------------
--
-- On the reference 6809 board,
-- RTI takes one more clock cycle than System09
-- So subtract 1 from the porta_data preset value.
-- 11th July 2006 John Kent
-- RTI in CPU09 has been extended by one bus cycle
-- so remove the subtract by one offset on porta_data
--
pia_counter : process( clk, timer, porta_data, ca2_out, cb2_out)
begin
if cb2_out = '1' then
timer <= "00000000";
elsif ca2_out = '0' then
-- timer <= porta_data - "00000001";
timer <= porta_data;
elsif clk'event and clk='1' then
timer <= timer - "00000001";
end if;
pa <= "00000000";
pb <= timer;
ca1 <= timer(7);
cb1 <= timer(7);
ca2 <= '0';
cb2 <= '0';
end process;
end pia_arch;
| gpl-3.0 | d1e197226ae450f170cfd21b70e744bc | 0.492531 | 3.387543 | false | false | false | false |
wsoltys/AtomFpga | mist/mist_pll.vhd | 1 | 18,112 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: mist_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY mist_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END mist_pll;
ARCHITECTURE SYN OF mist_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 32,
clk0_phase_shift => "0",
clk1_divide_by => 1080,
clk1_duty_cycle => 50,
clk1_multiply_by => 1007,
clk1_phase_shift => "0",
clk2_divide_by => 2250,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=mist_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.174999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.012000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.01200000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "mist_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1080"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2250"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| apache-2.0 | 2b40ac0960bdcdb5823d23c45b4e9546 | 0.700144 | 3.285326 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_mb_plb_wrapper.vhd | 1 | 14,560 | -------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 6,
C_PLBV46_NUM_SLAVES => 12,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| lgpl-3.0 | 89ff05814e2c66fe2204f200f537a635 | 0.610783 | 3.042206 | false | false | false | false |
KaskMartin/Digiloogika_ALU | ALU/toplevel.vhdl | 1 | 2,278 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU is --do not change entity, it must match testbench component
Port ( a , b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : in STD_LOGIC_VECTOR (1 downto 0); --2 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end ALU;
architecture toplevel of ALU is
--the component for first function is created
component func1 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for second function is created
component func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for third function is created
component func3 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for forth function is created
component func4 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for mux is created
component mux is
Port (m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F2_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F3_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F4_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
m_o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
signal F1_out, F2_out, F3_out, F4_out : STD_LOGIC_VECTOR (3 downto 0):="0000";
begin --beginning of the architecture
--components are port mapped according to workinstructions: http://priit.ati.ttu.ee/?page_id=2320
F1 : func1 port map (a => a,
b => b ,
o => F1_out);
F2 : func2 port map (a => a,
o => F2_out);
F3 : func3 port map (a => a,
b => b ,
o => F3_out);
F4 : func4 port map (a => a,
b => b,
o => F4_out);
MUX_tl : mux port map (m_op => op,
F1_in => F1_out,
F2_in => F2_out,
F3_in => F3_out,
F4_in => F4_out,
m_o => o);
end toplevel; | mit | 9a4817d6bebf5ae91d29922f1331b4f1 | 0.608428 | 2.928021 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/indices_if_ap_fifo.vhd | 2 | 2,819 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of indices_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | f7bbb97db9fd348632097bd0df98d55a | 0.492728 | 3.675359 | false | false | false | false |
dcliche/mdsynth | rtl/src/keymap_rom_slice.vhd | 1 | 4,915 | --===========================================================================--
-- --
-- Synthesizable PS/2 Keyboard Key map ROM --
-- --
--===========================================================================--
--
-- File name : keymap_rom_slice.vhd
--
-- Entity name : keymap_rom
--
-- Purpose : PS/2 key code look up table for PS/2 Keyboard
-- Converts 7 bit key code to ASCII
-- Address bit 8 = Shift
-- Address bit 7 = CAPS Lock
-- Address bits 6 - 0 = Key code
-- Data bits 6 - 0 = ASCII code
-- Using constant array look up.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-- Uses : None
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Copyright (C) 2004 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2004-10-18 John Kent Initial version
--
-- 0.2 2007-01-28 John Kent Made entity compatible with block RAM versions
--
-- 0.3 2007-02-03 John Kent Initialized with bit_vector
--
-- 0.4 2010-06-17 John Kent Updated header and added GPL
-- Renamed data_in and data_out signals
--
--
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keymap_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end keymap_rom;
architecture rtl of keymap_rom is
type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
constant rom_data : rom_array :=
(
x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
);
signal rom_out : std_logic_vector(255 downto 0);
begin
process( addr, rom_out )
begin
rom_out <= rom_data(conv_integer(addr(8 downto 5)));
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
end process;
end architecture rtl;
| gpl-3.0 | 161c744d5b003f181ea2ffaf5202e947 | 0.569888 | 3.913217 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00476.vhd | 1 | 3,459 | -- NEED RESULT: ARCH00476: Functions can return user defined types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00476
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (8)
-- 2.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00476)
-- ENT00476_Test_Bench(ARCH00476_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
-- The various types are taken from GENERIC_STANDARD_TYPES without the
-- explicit qualifier, as is the resolution function bf_rec3.
--
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00476 of GENERIC_STANDARD_TYPES is
function t_enum1_func ( i : integer ) return t_enum1 is
begin
return t_enum1'val(i) ;
end t_enum1_func ;
function st_enum1_func ( i : integer ) return st_enum1 is
begin
return st_enum1'val(i) ;
end st_enum1_func ;
function t_int1_func ( i : t_int1 ) return t_int1 is
begin
return i + 1 ;
end t_int1_func ;
function st_int1_func ( i : st_int1 ) return st_int1 is
begin
return i + 1 ;
end st_int1_func ;
function t_phys1_func ( i : integer ) return t_phys1 is
begin
return i * phys1_2;
end t_phys1_func ;
function st_phys1_func ( i : integer ) return st_phys1 is
begin
return i * phys1_2;
end st_phys1_func ;
function t_real1_func ( r : t_real1 ) return t_real1 is
begin
return r + 1.0;
end t_real1_func ;
function st_real1_func ( r : st_real1 ) return st_real1 is
begin
return r + 1.0;
end st_real1_func ;
function t_rec1_func ( r : real ) return t_rec1 is
variable rec : t_rec1 ;
begin
rec.f1 := lowb_i2 ;
rec.f2 := 0 ns ;
rec.f3 := true ;
rec.f4 := r + 1.0 ;
return rec ;
end t_rec1_func ;
function st_arr1_func ( i : integer ) return st_arr1 is
variable arr : st_arr1 ;
begin
for j in lowb to highb loop
arr(j) := t_int1(i + j);
end loop ;
return arr ;
end st_arr1_func ;
begin
P :
process
variable vec : rec3_vector (1 to 3) ;
begin
test_report ( "ARCH00476" ,
"Functions can return user defined types" ,
(t_enum1_func(1) = en2) and
(st_enum1_func(1) = en2) and
(t_int1_func(10) = 11 ) and
(st_int1_func(10) = 11 ) and
(t_phys1_func(2) = 2 phys1_2 ) and
(st_phys1_func(2) = 2 phys1_2 ) and
(t_real1_func(10.0) = 11.0 ) and
(st_real1_func(10.0) = 11.0 ) and
(t_rec1_func(10.0).f4 = 11.0 )
) ;
wait ;
end process P ;
end ARCH00476 ;
entity ENT00476_Test_Bench is
end ENT00476_Test_Bench ;
architecture ARCH00476_Test_Bench of ENT00476_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00476 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00476_Test_Bench ;
| gpl-3.0 | e5afd17f0814f1776e7ec11cef000a32 | 0.515756 | 3.190959 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00597.vhd | 1 | 2,172 | -- NEED RESULT: ARCH00597: Overloading context test -- rule 3 passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00597
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.5 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00597
-- ENT00597_Test_Bench(ARCH00597_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00597 is
constant B : boolean := true ;
constant C : real := 10.0 ;
signal S : integer ;
end PKG00597 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00597_Test_Bench is
type T is record
A : bit ;
B : Time ;
C : Integer ;
end record ;
signal PKG00597 : T := ('1',0 ns,1) ;
end ENT00597_Test_Bench ;
use WORK.all ;
use WORK.PKG00597;
architecture ARCH00597_Test_Bench of ENT00597_Test_Bench is
begin
WORK.PKG00597.S <= -- signal S in package PKG00597
transport 2
after PKG00597.B ; -- field B in signal PKG00597
PKG00597.A <= -- field A in signal PKG00597
transport '0' ;
g1:
if WORK.PKG00597.B -- constant B in PKG00597
generate
process
variable sum : real := 0.0 ;
variable first : boolean := true ;
begin
if first then
first := false ;
else
for i in PKG00597.C to PKG00597.C loop -- field C in signal PKG00597
sum := sum + WORK.PKG00597.C ; -- Constant C in pkg PKG00597
end loop ;
test_report ( "ARCH00597" ,
"Overloading context test -- rule 3" ,
(sum = 10.0) and
(WORK.PKG00597.S = 2) and
(PKG00597.A = '0') ) ;
wait ;
end if ;
wait on WORK.PKG00597.S ;
end process ;
end generate ;
end ARCH00597_Test_Bench ;
--
| gpl-3.0 | 9b9d6d43535c5369e632901c71fbc07b | 0.483886 | 3.4752 | false | true | false | false |
grwlf/vsim | vhdl/assign2.vhd | 1 | 44,391 | -- 1000 variable assigns in a process. GHC fails to compile on this one
entity main is
end entity main;
architecture arch of main is
signal clk : integer := 0;
constant CYCLES : integer := 1000;
begin
main: process(clk)
--{{{
variable a0001 : integer;
variable a0002 : integer;
variable a0003 : integer;
variable a0004 : integer;
variable a0005 : integer;
variable a0006 : integer;
variable a0007 : integer;
variable a0008 : integer;
variable a0009 : integer;
variable a0010 : integer;
variable a0011 : integer;
variable a0012 : integer;
variable a0013 : integer;
variable a0014 : integer;
variable a0015 : integer;
variable a0016 : integer;
variable a0017 : integer;
variable a0018 : integer;
variable a0019 : integer;
variable a0020 : integer;
variable a0021 : integer;
variable a0022 : integer;
variable a0023 : integer;
variable a0024 : integer;
variable a0025 : integer;
variable a0026 : integer;
variable a0027 : integer;
variable a0028 : integer;
variable a0029 : integer;
variable a0030 : integer;
variable a0031 : integer;
variable a0032 : integer;
variable a0033 : integer;
variable a0034 : integer;
variable a0035 : integer;
variable a0036 : integer;
variable a0037 : integer;
variable a0038 : integer;
variable a0039 : integer;
variable a0040 : integer;
variable a0041 : integer;
variable a0042 : integer;
variable a0043 : integer;
variable a0044 : integer;
variable a0045 : integer;
variable a0046 : integer;
variable a0047 : integer;
variable a0048 : integer;
variable a0049 : integer;
variable a0050 : integer;
variable a0051 : integer;
variable a0052 : integer;
variable a0053 : integer;
variable a0054 : integer;
variable a0055 : integer;
variable a0056 : integer;
variable a0057 : integer;
variable a0058 : integer;
variable a0059 : integer;
variable a0060 : integer;
variable a0061 : integer;
variable a0062 : integer;
variable a0063 : integer;
variable a0064 : integer;
variable a0065 : integer;
variable a0066 : integer;
variable a0067 : integer;
variable a0068 : integer;
variable a0069 : integer;
variable a0070 : integer;
variable a0071 : integer;
variable a0072 : integer;
variable a0073 : integer;
variable a0074 : integer;
variable a0075 : integer;
variable a0076 : integer;
variable a0077 : integer;
variable a0078 : integer;
variable a0079 : integer;
variable a0080 : integer;
variable a0081 : integer;
variable a0082 : integer;
variable a0083 : integer;
variable a0084 : integer;
variable a0085 : integer;
variable a0086 : integer;
variable a0087 : integer;
variable a0088 : integer;
variable a0089 : integer;
variable a0090 : integer;
variable a0091 : integer;
variable a0092 : integer;
variable a0093 : integer;
variable a0094 : integer;
variable a0095 : integer;
variable a0096 : integer;
variable a0097 : integer;
variable a0098 : integer;
variable a0099 : integer;
variable a0100 : integer;
variable a0101 : integer;
variable a0102 : integer;
variable a0103 : integer;
variable a0104 : integer;
variable a0105 : integer;
variable a0106 : integer;
variable a0107 : integer;
variable a0108 : integer;
variable a0109 : integer;
variable a0110 : integer;
variable a0111 : integer;
variable a0112 : integer;
variable a0113 : integer;
variable a0114 : integer;
variable a0115 : integer;
variable a0116 : integer;
variable a0117 : integer;
variable a0118 : integer;
variable a0119 : integer;
variable a0120 : integer;
variable a0121 : integer;
variable a0122 : integer;
variable a0123 : integer;
variable a0124 : integer;
variable a0125 : integer;
variable a0126 : integer;
variable a0127 : integer;
variable a0128 : integer;
variable a0129 : integer;
variable a0130 : integer;
variable a0131 : integer;
variable a0132 : integer;
variable a0133 : integer;
variable a0134 : integer;
variable a0135 : integer;
variable a0136 : integer;
variable a0137 : integer;
variable a0138 : integer;
variable a0139 : integer;
variable a0140 : integer;
variable a0141 : integer;
variable a0142 : integer;
variable a0143 : integer;
variable a0144 : integer;
variable a0145 : integer;
variable a0146 : integer;
variable a0147 : integer;
variable a0148 : integer;
variable a0149 : integer;
variable a0150 : integer;
variable a0151 : integer;
variable a0152 : integer;
variable a0153 : integer;
variable a0154 : integer;
variable a0155 : integer;
variable a0156 : integer;
variable a0157 : integer;
variable a0158 : integer;
variable a0159 : integer;
variable a0160 : integer;
variable a0161 : integer;
variable a0162 : integer;
variable a0163 : integer;
variable a0164 : integer;
variable a0165 : integer;
variable a0166 : integer;
variable a0167 : integer;
variable a0168 : integer;
variable a0169 : integer;
variable a0170 : integer;
variable a0171 : integer;
variable a0172 : integer;
variable a0173 : integer;
variable a0174 : integer;
variable a0175 : integer;
variable a0176 : integer;
variable a0177 : integer;
variable a0178 : integer;
variable a0179 : integer;
variable a0180 : integer;
variable a0181 : integer;
variable a0182 : integer;
variable a0183 : integer;
variable a0184 : integer;
variable a0185 : integer;
variable a0186 : integer;
variable a0187 : integer;
variable a0188 : integer;
variable a0189 : integer;
variable a0190 : integer;
variable a0191 : integer;
variable a0192 : integer;
variable a0193 : integer;
variable a0194 : integer;
variable a0195 : integer;
variable a0196 : integer;
variable a0197 : integer;
variable a0198 : integer;
variable a0199 : integer;
variable a0200 : integer;
variable a0201 : integer;
variable a0202 : integer;
variable a0203 : integer;
variable a0204 : integer;
variable a0205 : integer;
variable a0206 : integer;
variable a0207 : integer;
variable a0208 : integer;
variable a0209 : integer;
variable a0210 : integer;
variable a0211 : integer;
variable a0212 : integer;
variable a0213 : integer;
variable a0214 : integer;
variable a0215 : integer;
variable a0216 : integer;
variable a0217 : integer;
variable a0218 : integer;
variable a0219 : integer;
variable a0220 : integer;
variable a0221 : integer;
variable a0222 : integer;
variable a0223 : integer;
variable a0224 : integer;
variable a0225 : integer;
variable a0226 : integer;
variable a0227 : integer;
variable a0228 : integer;
variable a0229 : integer;
variable a0230 : integer;
variable a0231 : integer;
variable a0232 : integer;
variable a0233 : integer;
variable a0234 : integer;
variable a0235 : integer;
variable a0236 : integer;
variable a0237 : integer;
variable a0238 : integer;
variable a0239 : integer;
variable a0240 : integer;
variable a0241 : integer;
variable a0242 : integer;
variable a0243 : integer;
variable a0244 : integer;
variable a0245 : integer;
variable a0246 : integer;
variable a0247 : integer;
variable a0248 : integer;
variable a0249 : integer;
variable a0250 : integer;
variable a0251 : integer;
variable a0252 : integer;
variable a0253 : integer;
variable a0254 : integer;
variable a0255 : integer;
variable a0256 : integer;
variable a0257 : integer;
variable a0258 : integer;
variable a0259 : integer;
variable a0260 : integer;
variable a0261 : integer;
variable a0262 : integer;
variable a0263 : integer;
variable a0264 : integer;
variable a0265 : integer;
variable a0266 : integer;
variable a0267 : integer;
variable a0268 : integer;
variable a0269 : integer;
variable a0270 : integer;
variable a0271 : integer;
variable a0272 : integer;
variable a0273 : integer;
variable a0274 : integer;
variable a0275 : integer;
variable a0276 : integer;
variable a0277 : integer;
variable a0278 : integer;
variable a0279 : integer;
variable a0280 : integer;
variable a0281 : integer;
variable a0282 : integer;
variable a0283 : integer;
variable a0284 : integer;
variable a0285 : integer;
variable a0286 : integer;
variable a0287 : integer;
variable a0288 : integer;
variable a0289 : integer;
variable a0290 : integer;
variable a0291 : integer;
variable a0292 : integer;
variable a0293 : integer;
variable a0294 : integer;
variable a0295 : integer;
variable a0296 : integer;
variable a0297 : integer;
variable a0298 : integer;
variable a0299 : integer;
variable a0300 : integer;
variable a0301 : integer;
variable a0302 : integer;
variable a0303 : integer;
variable a0304 : integer;
variable a0305 : integer;
variable a0306 : integer;
variable a0307 : integer;
variable a0308 : integer;
variable a0309 : integer;
variable a0310 : integer;
variable a0311 : integer;
variable a0312 : integer;
variable a0313 : integer;
variable a0314 : integer;
variable a0315 : integer;
variable a0316 : integer;
variable a0317 : integer;
variable a0318 : integer;
variable a0319 : integer;
variable a0320 : integer;
variable a0321 : integer;
variable a0322 : integer;
variable a0323 : integer;
variable a0324 : integer;
variable a0325 : integer;
variable a0326 : integer;
variable a0327 : integer;
variable a0328 : integer;
variable a0329 : integer;
variable a0330 : integer;
variable a0331 : integer;
variable a0332 : integer;
variable a0333 : integer;
variable a0334 : integer;
variable a0335 : integer;
variable a0336 : integer;
variable a0337 : integer;
variable a0338 : integer;
variable a0339 : integer;
variable a0340 : integer;
variable a0341 : integer;
variable a0342 : integer;
variable a0343 : integer;
variable a0344 : integer;
variable a0345 : integer;
variable a0346 : integer;
variable a0347 : integer;
variable a0348 : integer;
variable a0349 : integer;
variable a0350 : integer;
variable a0351 : integer;
variable a0352 : integer;
variable a0353 : integer;
variable a0354 : integer;
variable a0355 : integer;
variable a0356 : integer;
variable a0357 : integer;
variable a0358 : integer;
variable a0359 : integer;
variable a0360 : integer;
variable a0361 : integer;
variable a0362 : integer;
variable a0363 : integer;
variable a0364 : integer;
variable a0365 : integer;
variable a0366 : integer;
variable a0367 : integer;
variable a0368 : integer;
variable a0369 : integer;
variable a0370 : integer;
variable a0371 : integer;
variable a0372 : integer;
variable a0373 : integer;
variable a0374 : integer;
variable a0375 : integer;
variable a0376 : integer;
variable a0377 : integer;
variable a0378 : integer;
variable a0379 : integer;
variable a0380 : integer;
variable a0381 : integer;
variable a0382 : integer;
variable a0383 : integer;
variable a0384 : integer;
variable a0385 : integer;
variable a0386 : integer;
variable a0387 : integer;
variable a0388 : integer;
variable a0389 : integer;
variable a0390 : integer;
variable a0391 : integer;
variable a0392 : integer;
variable a0393 : integer;
variable a0394 : integer;
variable a0395 : integer;
variable a0396 : integer;
variable a0397 : integer;
variable a0398 : integer;
variable a0399 : integer;
variable a0400 : integer;
variable a0401 : integer;
variable a0402 : integer;
variable a0403 : integer;
variable a0404 : integer;
variable a0405 : integer;
variable a0406 : integer;
variable a0407 : integer;
variable a0408 : integer;
variable a0409 : integer;
variable a0410 : integer;
variable a0411 : integer;
variable a0412 : integer;
variable a0413 : integer;
variable a0414 : integer;
variable a0415 : integer;
variable a0416 : integer;
variable a0417 : integer;
variable a0418 : integer;
variable a0419 : integer;
variable a0420 : integer;
variable a0421 : integer;
variable a0422 : integer;
variable a0423 : integer;
variable a0424 : integer;
variable a0425 : integer;
variable a0426 : integer;
variable a0427 : integer;
variable a0428 : integer;
variable a0429 : integer;
variable a0430 : integer;
variable a0431 : integer;
variable a0432 : integer;
variable a0433 : integer;
variable a0434 : integer;
variable a0435 : integer;
variable a0436 : integer;
variable a0437 : integer;
variable a0438 : integer;
variable a0439 : integer;
variable a0440 : integer;
variable a0441 : integer;
variable a0442 : integer;
variable a0443 : integer;
variable a0444 : integer;
variable a0445 : integer;
variable a0446 : integer;
variable a0447 : integer;
variable a0448 : integer;
variable a0449 : integer;
variable a0450 : integer;
variable a0451 : integer;
variable a0452 : integer;
variable a0453 : integer;
variable a0454 : integer;
variable a0455 : integer;
variable a0456 : integer;
variable a0457 : integer;
variable a0458 : integer;
variable a0459 : integer;
variable a0460 : integer;
variable a0461 : integer;
variable a0462 : integer;
variable a0463 : integer;
variable a0464 : integer;
variable a0465 : integer;
variable a0466 : integer;
variable a0467 : integer;
variable a0468 : integer;
variable a0469 : integer;
variable a0470 : integer;
variable a0471 : integer;
variable a0472 : integer;
variable a0473 : integer;
variable a0474 : integer;
variable a0475 : integer;
variable a0476 : integer;
variable a0477 : integer;
variable a0478 : integer;
variable a0479 : integer;
variable a0480 : integer;
variable a0481 : integer;
variable a0482 : integer;
variable a0483 : integer;
variable a0484 : integer;
variable a0485 : integer;
variable a0486 : integer;
variable a0487 : integer;
variable a0488 : integer;
variable a0489 : integer;
variable a0490 : integer;
variable a0491 : integer;
variable a0492 : integer;
variable a0493 : integer;
variable a0494 : integer;
variable a0495 : integer;
variable a0496 : integer;
variable a0497 : integer;
variable a0498 : integer;
variable a0499 : integer;
variable a0500 : integer;
variable a0501 : integer;
variable a0502 : integer;
variable a0503 : integer;
variable a0504 : integer;
variable a0505 : integer;
variable a0506 : integer;
variable a0507 : integer;
variable a0508 : integer;
variable a0509 : integer;
variable a0510 : integer;
variable a0511 : integer;
variable a0512 : integer;
variable a0513 : integer;
variable a0514 : integer;
variable a0515 : integer;
variable a0516 : integer;
variable a0517 : integer;
variable a0518 : integer;
variable a0519 : integer;
variable a0520 : integer;
variable a0521 : integer;
variable a0522 : integer;
variable a0523 : integer;
variable a0524 : integer;
variable a0525 : integer;
variable a0526 : integer;
variable a0527 : integer;
variable a0528 : integer;
variable a0529 : integer;
variable a0530 : integer;
variable a0531 : integer;
variable a0532 : integer;
variable a0533 : integer;
variable a0534 : integer;
variable a0535 : integer;
variable a0536 : integer;
variable a0537 : integer;
variable a0538 : integer;
variable a0539 : integer;
variable a0540 : integer;
variable a0541 : integer;
variable a0542 : integer;
variable a0543 : integer;
variable a0544 : integer;
variable a0545 : integer;
variable a0546 : integer;
variable a0547 : integer;
variable a0548 : integer;
variable a0549 : integer;
variable a0550 : integer;
variable a0551 : integer;
variable a0552 : integer;
variable a0553 : integer;
variable a0554 : integer;
variable a0555 : integer;
variable a0556 : integer;
variable a0557 : integer;
variable a0558 : integer;
variable a0559 : integer;
variable a0560 : integer;
variable a0561 : integer;
variable a0562 : integer;
variable a0563 : integer;
variable a0564 : integer;
variable a0565 : integer;
variable a0566 : integer;
variable a0567 : integer;
variable a0568 : integer;
variable a0569 : integer;
variable a0570 : integer;
variable a0571 : integer;
variable a0572 : integer;
variable a0573 : integer;
variable a0574 : integer;
variable a0575 : integer;
variable a0576 : integer;
variable a0577 : integer;
variable a0578 : integer;
variable a0579 : integer;
variable a0580 : integer;
variable a0581 : integer;
variable a0582 : integer;
variable a0583 : integer;
variable a0584 : integer;
variable a0585 : integer;
variable a0586 : integer;
variable a0587 : integer;
variable a0588 : integer;
variable a0589 : integer;
variable a0590 : integer;
variable a0591 : integer;
variable a0592 : integer;
variable a0593 : integer;
variable a0594 : integer;
variable a0595 : integer;
variable a0596 : integer;
variable a0597 : integer;
variable a0598 : integer;
variable a0599 : integer;
variable a0600 : integer;
variable a0601 : integer;
variable a0602 : integer;
variable a0603 : integer;
variable a0604 : integer;
variable a0605 : integer;
variable a0606 : integer;
variable a0607 : integer;
variable a0608 : integer;
variable a0609 : integer;
variable a0610 : integer;
variable a0611 : integer;
variable a0612 : integer;
variable a0613 : integer;
variable a0614 : integer;
variable a0615 : integer;
variable a0616 : integer;
variable a0617 : integer;
variable a0618 : integer;
variable a0619 : integer;
variable a0620 : integer;
variable a0621 : integer;
variable a0622 : integer;
variable a0623 : integer;
variable a0624 : integer;
variable a0625 : integer;
variable a0626 : integer;
variable a0627 : integer;
variable a0628 : integer;
variable a0629 : integer;
variable a0630 : integer;
variable a0631 : integer;
variable a0632 : integer;
variable a0633 : integer;
variable a0634 : integer;
variable a0635 : integer;
variable a0636 : integer;
variable a0637 : integer;
variable a0638 : integer;
variable a0639 : integer;
variable a0640 : integer;
variable a0641 : integer;
variable a0642 : integer;
variable a0643 : integer;
variable a0644 : integer;
variable a0645 : integer;
variable a0646 : integer;
variable a0647 : integer;
variable a0648 : integer;
variable a0649 : integer;
variable a0650 : integer;
variable a0651 : integer;
variable a0652 : integer;
variable a0653 : integer;
variable a0654 : integer;
variable a0655 : integer;
variable a0656 : integer;
variable a0657 : integer;
variable a0658 : integer;
variable a0659 : integer;
variable a0660 : integer;
variable a0661 : integer;
variable a0662 : integer;
variable a0663 : integer;
variable a0664 : integer;
variable a0665 : integer;
variable a0666 : integer;
variable a0667 : integer;
variable a0668 : integer;
variable a0669 : integer;
variable a0670 : integer;
variable a0671 : integer;
variable a0672 : integer;
variable a0673 : integer;
variable a0674 : integer;
variable a0675 : integer;
variable a0676 : integer;
variable a0677 : integer;
variable a0678 : integer;
variable a0679 : integer;
variable a0680 : integer;
variable a0681 : integer;
variable a0682 : integer;
variable a0683 : integer;
variable a0684 : integer;
variable a0685 : integer;
variable a0686 : integer;
variable a0687 : integer;
variable a0688 : integer;
variable a0689 : integer;
variable a0690 : integer;
variable a0691 : integer;
variable a0692 : integer;
variable a0693 : integer;
variable a0694 : integer;
variable a0695 : integer;
variable a0696 : integer;
variable a0697 : integer;
variable a0698 : integer;
variable a0699 : integer;
variable a0700 : integer;
variable a0701 : integer;
variable a0702 : integer;
variable a0703 : integer;
variable a0704 : integer;
variable a0705 : integer;
variable a0706 : integer;
variable a0707 : integer;
variable a0708 : integer;
variable a0709 : integer;
variable a0710 : integer;
variable a0711 : integer;
variable a0712 : integer;
variable a0713 : integer;
variable a0714 : integer;
variable a0715 : integer;
variable a0716 : integer;
variable a0717 : integer;
variable a0718 : integer;
variable a0719 : integer;
variable a0720 : integer;
variable a0721 : integer;
variable a0722 : integer;
variable a0723 : integer;
variable a0724 : integer;
variable a0725 : integer;
variable a0726 : integer;
variable a0727 : integer;
variable a0728 : integer;
variable a0729 : integer;
variable a0730 : integer;
variable a0731 : integer;
variable a0732 : integer;
variable a0733 : integer;
variable a0734 : integer;
variable a0735 : integer;
variable a0736 : integer;
variable a0737 : integer;
variable a0738 : integer;
variable a0739 : integer;
variable a0740 : integer;
variable a0741 : integer;
variable a0742 : integer;
variable a0743 : integer;
variable a0744 : integer;
variable a0745 : integer;
variable a0746 : integer;
variable a0747 : integer;
variable a0748 : integer;
variable a0749 : integer;
variable a0750 : integer;
variable a0751 : integer;
variable a0752 : integer;
variable a0753 : integer;
variable a0754 : integer;
variable a0755 : integer;
variable a0756 : integer;
variable a0757 : integer;
variable a0758 : integer;
variable a0759 : integer;
variable a0760 : integer;
variable a0761 : integer;
variable a0762 : integer;
variable a0763 : integer;
variable a0764 : integer;
variable a0765 : integer;
variable a0766 : integer;
variable a0767 : integer;
variable a0768 : integer;
variable a0769 : integer;
variable a0770 : integer;
variable a0771 : integer;
variable a0772 : integer;
variable a0773 : integer;
variable a0774 : integer;
variable a0775 : integer;
variable a0776 : integer;
variable a0777 : integer;
variable a0778 : integer;
variable a0779 : integer;
variable a0780 : integer;
variable a0781 : integer;
variable a0782 : integer;
variable a0783 : integer;
variable a0784 : integer;
variable a0785 : integer;
variable a0786 : integer;
variable a0787 : integer;
variable a0788 : integer;
variable a0789 : integer;
variable a0790 : integer;
variable a0791 : integer;
variable a0792 : integer;
variable a0793 : integer;
variable a0794 : integer;
variable a0795 : integer;
variable a0796 : integer;
variable a0797 : integer;
variable a0798 : integer;
variable a0799 : integer;
variable a0800 : integer;
variable a0801 : integer;
variable a0802 : integer;
variable a0803 : integer;
variable a0804 : integer;
variable a0805 : integer;
variable a0806 : integer;
variable a0807 : integer;
variable a0808 : integer;
variable a0809 : integer;
variable a0810 : integer;
variable a0811 : integer;
variable a0812 : integer;
variable a0813 : integer;
variable a0814 : integer;
variable a0815 : integer;
variable a0816 : integer;
variable a0817 : integer;
variable a0818 : integer;
variable a0819 : integer;
variable a0820 : integer;
variable a0821 : integer;
variable a0822 : integer;
variable a0823 : integer;
variable a0824 : integer;
variable a0825 : integer;
variable a0826 : integer;
variable a0827 : integer;
variable a0828 : integer;
variable a0829 : integer;
variable a0830 : integer;
variable a0831 : integer;
variable a0832 : integer;
variable a0833 : integer;
variable a0834 : integer;
variable a0835 : integer;
variable a0836 : integer;
variable a0837 : integer;
variable a0838 : integer;
variable a0839 : integer;
variable a0840 : integer;
variable a0841 : integer;
variable a0842 : integer;
variable a0843 : integer;
variable a0844 : integer;
variable a0845 : integer;
variable a0846 : integer;
variable a0847 : integer;
variable a0848 : integer;
variable a0849 : integer;
variable a0850 : integer;
variable a0851 : integer;
variable a0852 : integer;
variable a0853 : integer;
variable a0854 : integer;
variable a0855 : integer;
variable a0856 : integer;
variable a0857 : integer;
variable a0858 : integer;
variable a0859 : integer;
variable a0860 : integer;
variable a0861 : integer;
variable a0862 : integer;
variable a0863 : integer;
variable a0864 : integer;
variable a0865 : integer;
variable a0866 : integer;
variable a0867 : integer;
variable a0868 : integer;
variable a0869 : integer;
variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0001 := 1;
a0002 := 2;
a0003 := 3;
a0004 := 4;
a0005 := 5;
a0006 := 6;
a0007 := 7;
a0008 := 8;
a0009 := 9;
a0010 := 10;
a0011 := 11;
a0012 := 12;
a0013 := 13;
a0014 := 14;
a0015 := 15;
a0016 := 16;
a0017 := 17;
a0018 := 18;
a0019 := 19;
a0020 := 20;
a0021 := 21;
a0022 := 22;
a0023 := 23;
a0024 := 24;
a0025 := 25;
a0026 := 26;
a0027 := 27;
a0028 := 28;
a0029 := 29;
a0030 := 30;
a0031 := 31;
a0032 := 32;
a0033 := 33;
a0034 := 34;
a0035 := 35;
a0036 := 36;
a0037 := 37;
a0038 := 38;
a0039 := 39;
a0040 := 40;
a0041 := 41;
a0042 := 42;
a0043 := 43;
a0044 := 44;
a0045 := 45;
a0046 := 46;
a0047 := 47;
a0048 := 48;
a0049 := 49;
a0050 := 50;
a0051 := 51;
a0052 := 52;
a0053 := 53;
a0054 := 54;
a0055 := 55;
a0056 := 56;
a0057 := 57;
a0058 := 58;
a0059 := 59;
a0060 := 60;
a0061 := 61;
a0062 := 62;
a0063 := 63;
a0064 := 64;
a0065 := 65;
a0066 := 66;
a0067 := 67;
a0068 := 68;
a0069 := 69;
a0070 := 70;
a0071 := 71;
a0072 := 72;
a0073 := 73;
a0074 := 74;
a0075 := 75;
a0076 := 76;
a0077 := 77;
a0078 := 78;
a0079 := 79;
a0080 := 80;
a0081 := 81;
a0082 := 82;
a0083 := 83;
a0084 := 84;
a0085 := 85;
a0086 := 86;
a0087 := 87;
a0088 := 88;
a0089 := 89;
a0090 := 90;
a0091 := 91;
a0092 := 92;
a0093 := 93;
a0094 := 94;
a0095 := 95;
a0096 := 96;
a0097 := 97;
a0098 := 98;
a0099 := 99;
a0100 := 100;
a0101 := 101;
a0102 := 102;
a0103 := 103;
a0104 := 104;
a0105 := 105;
a0106 := 106;
a0107 := 107;
a0108 := 108;
a0109 := 109;
a0110 := 110;
a0111 := 111;
a0112 := 112;
a0113 := 113;
a0114 := 114;
a0115 := 115;
a0116 := 116;
a0117 := 117;
a0118 := 118;
a0119 := 119;
a0120 := 120;
a0121 := 121;
a0122 := 122;
a0123 := 123;
a0124 := 124;
a0125 := 125;
a0126 := 126;
a0127 := 127;
a0128 := 128;
a0129 := 129;
a0130 := 130;
a0131 := 131;
a0132 := 132;
a0133 := 133;
a0134 := 134;
a0135 := 135;
a0136 := 136;
a0137 := 137;
a0138 := 138;
a0139 := 139;
a0140 := 140;
a0141 := 141;
a0142 := 142;
a0143 := 143;
a0144 := 144;
a0145 := 145;
a0146 := 146;
a0147 := 147;
a0148 := 148;
a0149 := 149;
a0150 := 150;
a0151 := 151;
a0152 := 152;
a0153 := 153;
a0154 := 154;
a0155 := 155;
a0156 := 156;
a0157 := 157;
a0158 := 158;
a0159 := 159;
a0160 := 160;
a0161 := 161;
a0162 := 162;
a0163 := 163;
a0164 := 164;
a0165 := 165;
a0166 := 166;
a0167 := 167;
a0168 := 168;
a0169 := 169;
a0170 := 170;
a0171 := 171;
a0172 := 172;
a0173 := 173;
a0174 := 174;
a0175 := 175;
a0176 := 176;
a0177 := 177;
a0178 := 178;
a0179 := 179;
a0180 := 180;
a0181 := 181;
a0182 := 182;
a0183 := 183;
a0184 := 184;
a0185 := 185;
a0186 := 186;
a0187 := 187;
a0188 := 188;
a0189 := 189;
a0190 := 190;
a0191 := 191;
a0192 := 192;
a0193 := 193;
a0194 := 194;
a0195 := 195;
a0196 := 196;
a0197 := 197;
a0198 := 198;
a0199 := 199;
a0200 := 200;
a0201 := 201;
a0202 := 202;
a0203 := 203;
a0204 := 204;
a0205 := 205;
a0206 := 206;
a0207 := 207;
a0208 := 208;
a0209 := 209;
a0210 := 210;
a0211 := 211;
a0212 := 212;
a0213 := 213;
a0214 := 214;
a0215 := 215;
a0216 := 216;
a0217 := 217;
a0218 := 218;
a0219 := 219;
a0220 := 220;
a0221 := 221;
a0222 := 222;
a0223 := 223;
a0224 := 224;
a0225 := 225;
a0226 := 226;
a0227 := 227;
a0228 := 228;
a0229 := 229;
a0230 := 230;
a0231 := 231;
a0232 := 232;
a0233 := 233;
a0234 := 234;
a0235 := 235;
a0236 := 236;
a0237 := 237;
a0238 := 238;
a0239 := 239;
a0240 := 240;
a0241 := 241;
a0242 := 242;
a0243 := 243;
a0244 := 244;
a0245 := 245;
a0246 := 246;
a0247 := 247;
a0248 := 248;
a0249 := 249;
a0250 := 250;
a0251 := 251;
a0252 := 252;
a0253 := 253;
a0254 := 254;
a0255 := 255;
a0256 := 256;
a0257 := 257;
a0258 := 258;
a0259 := 259;
a0260 := 260;
a0261 := 261;
a0262 := 262;
a0263 := 263;
a0264 := 264;
a0265 := 265;
a0266 := 266;
a0267 := 267;
a0268 := 268;
a0269 := 269;
a0270 := 270;
a0271 := 271;
a0272 := 272;
a0273 := 273;
a0274 := 274;
a0275 := 275;
a0276 := 276;
a0277 := 277;
a0278 := 278;
a0279 := 279;
a0280 := 280;
a0281 := 281;
a0282 := 282;
a0283 := 283;
a0284 := 284;
a0285 := 285;
a0286 := 286;
a0287 := 287;
a0288 := 288;
a0289 := 289;
a0290 := 290;
a0291 := 291;
a0292 := 292;
a0293 := 293;
a0294 := 294;
a0295 := 295;
a0296 := 296;
a0297 := 297;
a0298 := 298;
a0299 := 299;
a0300 := 300;
a0301 := 301;
a0302 := 302;
a0303 := 303;
a0304 := 304;
a0305 := 305;
a0306 := 306;
a0307 := 307;
a0308 := 308;
a0309 := 309;
a0310 := 310;
a0311 := 311;
a0312 := 312;
a0313 := 313;
a0314 := 314;
a0315 := 315;
a0316 := 316;
a0317 := 317;
a0318 := 318;
a0319 := 319;
a0320 := 320;
a0321 := 321;
a0322 := 322;
a0323 := 323;
a0324 := 324;
a0325 := 325;
a0326 := 326;
a0327 := 327;
a0328 := 328;
a0329 := 329;
a0330 := 330;
a0331 := 331;
a0332 := 332;
a0333 := 333;
a0334 := 334;
a0335 := 335;
a0336 := 336;
a0337 := 337;
a0338 := 338;
a0339 := 339;
a0340 := 340;
a0341 := 341;
a0342 := 342;
a0343 := 343;
a0344 := 344;
a0345 := 345;
a0346 := 346;
a0347 := 347;
a0348 := 348;
a0349 := 349;
a0350 := 350;
a0351 := 351;
a0352 := 352;
a0353 := 353;
a0354 := 354;
a0355 := 355;
a0356 := 356;
a0357 := 357;
a0358 := 358;
a0359 := 359;
a0360 := 360;
a0361 := 361;
a0362 := 362;
a0363 := 363;
a0364 := 364;
a0365 := 365;
a0366 := 366;
a0367 := 367;
a0368 := 368;
a0369 := 369;
a0370 := 370;
a0371 := 371;
a0372 := 372;
a0373 := 373;
a0374 := 374;
a0375 := 375;
a0376 := 376;
a0377 := 377;
a0378 := 378;
a0379 := 379;
a0380 := 380;
a0381 := 381;
a0382 := 382;
a0383 := 383;
a0384 := 384;
a0385 := 385;
a0386 := 386;
a0387 := 387;
a0388 := 388;
a0389 := 389;
a0390 := 390;
a0391 := 391;
a0392 := 392;
a0393 := 393;
a0394 := 394;
a0395 := 395;
a0396 := 396;
a0397 := 397;
a0398 := 398;
a0399 := 399;
a0400 := 400;
a0401 := 401;
a0402 := 402;
a0403 := 403;
a0404 := 404;
a0405 := 405;
a0406 := 406;
a0407 := 407;
a0408 := 408;
a0409 := 409;
a0410 := 410;
a0411 := 411;
a0412 := 412;
a0413 := 413;
a0414 := 414;
a0415 := 415;
a0416 := 416;
a0417 := 417;
a0418 := 418;
a0419 := 419;
a0420 := 420;
a0421 := 421;
a0422 := 422;
a0423 := 423;
a0424 := 424;
a0425 := 425;
a0426 := 426;
a0427 := 427;
a0428 := 428;
a0429 := 429;
a0430 := 430;
a0431 := 431;
a0432 := 432;
a0433 := 433;
a0434 := 434;
a0435 := 435;
a0436 := 436;
a0437 := 437;
a0438 := 438;
a0439 := 439;
a0440 := 440;
a0441 := 441;
a0442 := 442;
a0443 := 443;
a0444 := 444;
a0445 := 445;
a0446 := 446;
a0447 := 447;
a0448 := 448;
a0449 := 449;
a0450 := 450;
a0451 := 451;
a0452 := 452;
a0453 := 453;
a0454 := 454;
a0455 := 455;
a0456 := 456;
a0457 := 457;
a0458 := 458;
a0459 := 459;
a0460 := 460;
a0461 := 461;
a0462 := 462;
a0463 := 463;
a0464 := 464;
a0465 := 465;
a0466 := 466;
a0467 := 467;
a0468 := 468;
a0469 := 469;
a0470 := 470;
a0471 := 471;
a0472 := 472;
a0473 := 473;
a0474 := 474;
a0475 := 475;
a0476 := 476;
a0477 := 477;
a0478 := 478;
a0479 := 479;
a0480 := 480;
a0481 := 481;
a0482 := 482;
a0483 := 483;
a0484 := 484;
a0485 := 485;
a0486 := 486;
a0487 := 487;
a0488 := 488;
a0489 := 489;
a0490 := 490;
a0491 := 491;
a0492 := 492;
a0493 := 493;
a0494 := 494;
a0495 := 495;
a0496 := 496;
a0497 := 497;
a0498 := 498;
a0499 := 499;
a0500 := 500;
a0501 := 501;
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
| gpl-3.0 | 54672dbde7526862d98cc415b0fadc3f | 0.635647 | 2.78908 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/p_bsf32_hw.vhd | 1 | 35,948 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (5 downto 0) );
end;
architecture behav of p_bsf32_hw is
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv6_1F : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
signal p_s_phi_fu_139_p62 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_fu_245_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_249_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_257_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_265_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_273_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_281_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_289_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_297_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_313_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_321_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_329_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_337_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_345_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_353_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_361_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_369_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_377_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_385_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_393_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_401_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_409_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_417_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_425_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_433_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_441_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_449_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_457_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_465_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_473_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_481_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal UnifiedRetVal_phi_fu_237_p4 : STD_LOGIC_VECTOR (5 downto 0);
signal p_cast_cast_fu_489_p1 : STD_LOGIC_VECTOR (5 downto 0);
begin
-- UnifiedRetVal_phi_fu_237_p4 assign process. --
UnifiedRetVal_phi_fu_237_p4_assign_proc : process(tmp_fu_245_p1, tmp_5_fu_249_p3, tmp_6_fu_257_p3, tmp_7_fu_265_p3, tmp_8_fu_273_p3, tmp_9_fu_281_p3, tmp_10_fu_289_p3, tmp_11_fu_297_p3, tmp_12_fu_305_p3, tmp_13_fu_313_p3, tmp_14_fu_321_p3, tmp_15_fu_329_p3, tmp_16_fu_337_p3, tmp_17_fu_345_p3, tmp_18_fu_353_p3, tmp_19_fu_361_p3, tmp_20_fu_369_p3, tmp_21_fu_377_p3, tmp_22_fu_385_p3, tmp_23_fu_393_p3, tmp_24_fu_401_p3, tmp_25_fu_409_p3, tmp_26_fu_417_p3, tmp_27_fu_425_p3, tmp_28_fu_433_p3, tmp_29_fu_441_p3, tmp_30_fu_449_p3, tmp_31_fu_457_p3, tmp_32_fu_465_p3, tmp_33_fu_473_p3, tmp_34_fu_481_p3, p_cast_cast_fu_489_p1)
begin
if ((not((tmp_fu_245_p1 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_5_fu_249_p3)) or not((ap_const_lv1_0 = tmp_6_fu_257_p3)) or not((ap_const_lv1_0 = tmp_7_fu_265_p3)) or not((ap_const_lv1_0 = tmp_8_fu_273_p3)) or not((ap_const_lv1_0 = tmp_9_fu_281_p3)) or not((ap_const_lv1_0 = tmp_10_fu_289_p3)) or not((ap_const_lv1_0 = tmp_11_fu_297_p3)) or not((ap_const_lv1_0 = tmp_12_fu_305_p3)) or not((ap_const_lv1_0 = tmp_13_fu_313_p3)) or not((ap_const_lv1_0 = tmp_14_fu_321_p3)) or not((ap_const_lv1_0 = tmp_15_fu_329_p3)) or not((ap_const_lv1_0 = tmp_16_fu_337_p3)) or not((ap_const_lv1_0 = tmp_17_fu_345_p3)) or not((ap_const_lv1_0 = tmp_18_fu_353_p3)) or not((ap_const_lv1_0 = tmp_19_fu_361_p3)) or not((ap_const_lv1_0 = tmp_20_fu_369_p3)) or not((ap_const_lv1_0 = tmp_21_fu_377_p3)) or not((ap_const_lv1_0 = tmp_22_fu_385_p3)) or not((ap_const_lv1_0 = tmp_23_fu_393_p3)) or not((ap_const_lv1_0 = tmp_24_fu_401_p3)) or not((ap_const_lv1_0 = tmp_25_fu_409_p3)) or not((ap_const_lv1_0 = tmp_26_fu_417_p3)) or not((ap_const_lv1_0 = tmp_27_fu_425_p3)) or not((ap_const_lv1_0 = tmp_28_fu_433_p3)) or not((ap_const_lv1_0 = tmp_29_fu_441_p3)) or not((ap_const_lv1_0 = tmp_30_fu_449_p3)) or not((ap_const_lv1_0 = tmp_31_fu_457_p3)) or not((ap_const_lv1_0 = tmp_32_fu_465_p3)) or not((ap_const_lv1_0 = tmp_33_fu_473_p3)) or not((ap_const_lv1_0 = tmp_34_fu_481_p3)))) then
UnifiedRetVal_phi_fu_237_p4 <= p_cast_cast_fu_489_p1;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and (ap_const_lv1_0 = tmp_30_fu_449_p3) and (ap_const_lv1_0 = tmp_31_fu_457_p3) and (ap_const_lv1_0 = tmp_32_fu_465_p3) and (ap_const_lv1_0 = tmp_33_fu_473_p3) and (ap_const_lv1_0 = tmp_34_fu_481_p3))) then
UnifiedRetVal_phi_fu_237_p4 <= ap_const_lv6_1F;
else
UnifiedRetVal_phi_fu_237_p4 <= "XXXXXX";
end if;
end process;
ap_return <= UnifiedRetVal_phi_fu_237_p4;
p_cast_cast_fu_489_p1 <= std_logic_vector(resize(unsigned(p_s_phi_fu_139_p62),6));
-- p_s_phi_fu_139_p62 assign process. --
p_s_phi_fu_139_p62_assign_proc : process(tmp_fu_245_p1, tmp_5_fu_249_p3, tmp_6_fu_257_p3, tmp_7_fu_265_p3, tmp_8_fu_273_p3, tmp_9_fu_281_p3, tmp_10_fu_289_p3, tmp_11_fu_297_p3, tmp_12_fu_305_p3, tmp_13_fu_313_p3, tmp_14_fu_321_p3, tmp_15_fu_329_p3, tmp_16_fu_337_p3, tmp_17_fu_345_p3, tmp_18_fu_353_p3, tmp_19_fu_361_p3, tmp_20_fu_369_p3, tmp_21_fu_377_p3, tmp_22_fu_385_p3, tmp_23_fu_393_p3, tmp_24_fu_401_p3, tmp_25_fu_409_p3, tmp_26_fu_417_p3, tmp_27_fu_425_p3, tmp_28_fu_433_p3, tmp_29_fu_441_p3, tmp_30_fu_449_p3, tmp_31_fu_457_p3, tmp_32_fu_465_p3, tmp_33_fu_473_p3, tmp_34_fu_481_p3)
begin
if (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and (ap_const_lv1_0 = tmp_30_fu_449_p3) and (ap_const_lv1_0 = tmp_31_fu_457_p3) and (ap_const_lv1_0 = tmp_32_fu_465_p3) and (ap_const_lv1_0 = tmp_33_fu_473_p3) and not((ap_const_lv1_0 = tmp_34_fu_481_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1E;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and (ap_const_lv1_0 = tmp_30_fu_449_p3) and (ap_const_lv1_0 = tmp_31_fu_457_p3) and (ap_const_lv1_0 = tmp_32_fu_465_p3) and not((ap_const_lv1_0 = tmp_33_fu_473_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1D;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and (ap_const_lv1_0 = tmp_30_fu_449_p3) and (ap_const_lv1_0 = tmp_31_fu_457_p3) and not((ap_const_lv1_0 = tmp_32_fu_465_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1C;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and (ap_const_lv1_0 = tmp_30_fu_449_p3) and not((ap_const_lv1_0 = tmp_31_fu_457_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1B;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and (ap_const_lv1_0 = tmp_29_fu_441_p3) and not((ap_const_lv1_0 = tmp_30_fu_449_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1A;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and (ap_const_lv1_0 = tmp_28_fu_433_p3) and not((ap_const_lv1_0 = tmp_29_fu_441_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_19;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and (ap_const_lv1_0 = tmp_27_fu_425_p3) and not((ap_const_lv1_0 = tmp_28_fu_433_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_18;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and (ap_const_lv1_0 = tmp_26_fu_417_p3) and not((ap_const_lv1_0 = tmp_27_fu_425_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_17;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and (ap_const_lv1_0 = tmp_25_fu_409_p3) and not((ap_const_lv1_0 = tmp_26_fu_417_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_16;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and (ap_const_lv1_0 = tmp_24_fu_401_p3) and not((ap_const_lv1_0 = tmp_25_fu_409_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_15;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and (ap_const_lv1_0 = tmp_23_fu_393_p3) and not((ap_const_lv1_0 = tmp_24_fu_401_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_14;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and (ap_const_lv1_0 = tmp_22_fu_385_p3) and not((ap_const_lv1_0 = tmp_23_fu_393_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_13;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and (ap_const_lv1_0 = tmp_21_fu_377_p3) and not((ap_const_lv1_0 = tmp_22_fu_385_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_12;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and (ap_const_lv1_0 = tmp_20_fu_369_p3) and not((ap_const_lv1_0 = tmp_21_fu_377_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_11;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and (ap_const_lv1_0 = tmp_19_fu_361_p3) and not((ap_const_lv1_0 = tmp_20_fu_369_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_10;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and (ap_const_lv1_0 = tmp_18_fu_353_p3) and not((ap_const_lv1_0 = tmp_19_fu_361_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_F;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and (ap_const_lv1_0 = tmp_17_fu_345_p3) and not((ap_const_lv1_0 = tmp_18_fu_353_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_E;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and (ap_const_lv1_0 = tmp_16_fu_337_p3) and not((ap_const_lv1_0 = tmp_17_fu_345_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_D;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and (ap_const_lv1_0 = tmp_15_fu_329_p3) and not((ap_const_lv1_0 = tmp_16_fu_337_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_C;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and (ap_const_lv1_0 = tmp_14_fu_321_p3) and not((ap_const_lv1_0 = tmp_15_fu_329_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_B;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and (ap_const_lv1_0 = tmp_13_fu_313_p3) and not((ap_const_lv1_0 = tmp_14_fu_321_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_A;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and (ap_const_lv1_0 = tmp_12_fu_305_p3) and not((ap_const_lv1_0 = tmp_13_fu_313_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_9;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and (ap_const_lv1_0 = tmp_11_fu_297_p3) and not((ap_const_lv1_0 = tmp_12_fu_305_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_8;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and (ap_const_lv1_0 = tmp_10_fu_289_p3) and not((ap_const_lv1_0 = tmp_11_fu_297_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_7;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and (ap_const_lv1_0 = tmp_9_fu_281_p3) and not((ap_const_lv1_0 = tmp_10_fu_289_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_6;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and (ap_const_lv1_0 = tmp_8_fu_273_p3) and not((ap_const_lv1_0 = tmp_9_fu_281_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_5;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and (ap_const_lv1_0 = tmp_7_fu_265_p3) and not((ap_const_lv1_0 = tmp_8_fu_273_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_4;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and (ap_const_lv1_0 = tmp_6_fu_257_p3) and not((ap_const_lv1_0 = tmp_7_fu_265_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_3;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_5_fu_249_p3) and not((ap_const_lv1_0 = tmp_6_fu_257_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_2;
elsif (((tmp_fu_245_p1 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_5_fu_249_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1;
elsif (not((tmp_fu_245_p1 = ap_const_lv1_0))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_0;
else
p_s_phi_fu_139_p62 <= "XXXXX";
end if;
end process;
tmp_10_fu_289_p3 <= bus_r(6 downto 6);
tmp_11_fu_297_p3 <= bus_r(7 downto 7);
tmp_12_fu_305_p3 <= bus_r(8 downto 8);
tmp_13_fu_313_p3 <= bus_r(9 downto 9);
tmp_14_fu_321_p3 <= bus_r(10 downto 10);
tmp_15_fu_329_p3 <= bus_r(11 downto 11);
tmp_16_fu_337_p3 <= bus_r(12 downto 12);
tmp_17_fu_345_p3 <= bus_r(13 downto 13);
tmp_18_fu_353_p3 <= bus_r(14 downto 14);
tmp_19_fu_361_p3 <= bus_r(15 downto 15);
tmp_20_fu_369_p3 <= bus_r(16 downto 16);
tmp_21_fu_377_p3 <= bus_r(17 downto 17);
tmp_22_fu_385_p3 <= bus_r(18 downto 18);
tmp_23_fu_393_p3 <= bus_r(19 downto 19);
tmp_24_fu_401_p3 <= bus_r(20 downto 20);
tmp_25_fu_409_p3 <= bus_r(21 downto 21);
tmp_26_fu_417_p3 <= bus_r(22 downto 22);
tmp_27_fu_425_p3 <= bus_r(23 downto 23);
tmp_28_fu_433_p3 <= bus_r(24 downto 24);
tmp_29_fu_441_p3 <= bus_r(25 downto 25);
tmp_30_fu_449_p3 <= bus_r(26 downto 26);
tmp_31_fu_457_p3 <= bus_r(27 downto 27);
tmp_32_fu_465_p3 <= bus_r(28 downto 28);
tmp_33_fu_473_p3 <= bus_r(29 downto 29);
tmp_34_fu_481_p3 <= bus_r(30 downto 30);
tmp_5_fu_249_p3 <= bus_r(1 downto 1);
tmp_6_fu_257_p3 <= bus_r(2 downto 2);
tmp_7_fu_265_p3 <= bus_r(3 downto 3);
tmp_8_fu_273_p3 <= bus_r(4 downto 4);
tmp_9_fu_281_p3 <= bus_r(5 downto 5);
tmp_fu_245_p1 <= bus_r(1 - 1 downto 0);
end behav;
| lgpl-3.0 | 4f94ae07d7fe3308678648532b275fc4 | 0.635807 | 2.092311 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000018.vhd | 1 | 3,947 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00015_Test_Bench is
end ENT00015_Test_Bench;
architecture ARCH00015_Test_Bench of ENT00015_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type TimeVector is array (integer range <>) of time;
signal t : TimeVector(1 to 24);
begin
t(1) <= bv'Last_event;
t(2) <= ra'Last_event;
t(3) <= r'Last_event;
t(4) <= ea'Last_event;
t(5) <= e'Last_event;
t(6) <= I_sa'Last_event;
t(7) <= I_baa'Last_event;
t(8) <= I_saa'Last_event;
t(9) <= b1'Last_event;
t(10) <= b2'Last_event;
t(11) <= clk'Last_event;
t(12) <= clk2'Last_event;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00015_Test_Bench ; | gpl-3.0 | 2c5f17d75ed898c0fa16552a52f2bc13 | 0.54041 | 2.428923 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/synopsys/std_logic_misc.vhdl | 1 | 33,614 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
| gpl-3.0 | d319c29260a8c444aaaa67555fcf1e79 | 0.409204 | 3.385778 | false | false | false | false |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd | 1 | 3,464 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Tue Apr 18 23:07:59 2017
--Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| unlicense | 269efeb9ca26f708554e74c31e2be6f6 | 0.589203 | 3.065487 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00540.vhd | 1 | 4,193 | -- NEED RESULT: ARCH00540: Attributes for multi-dimensional arrays passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00540
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (12)
-- 14.1 (14)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00540)
-- ENT00540_Test_Bench(ARCH00540_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
-- 18-JAN-1988 - remove function calls as prefixes of predefined attributes
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00540 of E00000 is
begin
P :
process
type tt_arr2 is array (lowb to highb, false to true) of st_arr1;
variable a : st_arr2 ;
function f return st_arr2 is
variable x : st_arr2 ;
begin
return x ;
end f ;
subtype a_range_1 is integer range a'range ;
subtype a_range_2 is boolean range a'range(2) ;
-- subtype f_range_1 is integer range f'range ;
-- subtype f_range_2 is boolean range f'range(2) ;
subtype s_range_1 is integer range st_arr2'range ;
subtype s_range_2 is boolean range st_arr2'range(2) ;
subtype t_range_1 is integer range tt_arr2'range ;
subtype t_range_2 is boolean range tt_arr2'range(2) ;
subtype a_reverse_range_1 is integer range a'reverse_range ;
subtype a_reverse_range_2 is boolean range a'reverse_range(2) ;
-- subtype f_reverse_range_1 is integer range f'reverse_range ;
-- subtype f_reverse_range_2 is boolean range f'reverse_range(2) ;
subtype s_reverse_range_1 is integer range st_arr2'reverse_range ;
subtype s_reverse_range_2 is boolean range st_arr2'reverse_range(2) ;
subtype t_reverse_range_1 is integer range tt_arr2'reverse_range ;
subtype t_reverse_range_2 is boolean range tt_arr2'reverse_range(2) ;
begin
test_report ( "ARCH00540" ,
"Attributes for multi-dimensional arrays" ,
-- these test 14.1 (12)
(a'left(2) = false) and
(a'right(2) = true) and
(a'low(2) = false) and
(a'high(2) = true) and
(a_range_2'left = false) and
(a_reverse_range_2'left = true) and
(a'length(2) = 2) and
-- (f'left(2) = false) and
-- (f'right(2) = true) and
-- (f'low(2) = false) and
-- (f'high(2) = true) and
-- (f_range_2'left = false) and
-- (f_reverse_range_2'left = true) and
-- (f'length(2) = 2) and
(tt_arr2'left(2) = false) and
(tt_arr2'right(2) = true) and
(tt_arr2'low(2) = false) and
(tt_arr2'high(2) = true) and
(t_range_2'left = false) and
(t_reverse_range_2'left = true) and
(tt_arr2'length(2) = 2) and
(st_arr2'left(2) = false) and
(st_arr2'right(2) = true) and
(st_arr2'low(2) = false) and
(st_arr2'high(2) = true) and
(s_range_2'left = false) and
(s_reverse_range_2'left = true) and
(st_arr2'length(2) = 2) and
-- these test 14.1 (14)
(a_range_1'left = lowb) and
(a_reverse_range_1'left = highb) and
(a'length = highb-lowb+1) and
-- (f_range_1'left = lowb) and
-- (f_reverse_range_1'left = highb) and
-- (f'length = highb-lowb+1) and
(t_range_1'left = lowb) and
(t_reverse_range_1'left = highb) and
(tt_arr2'length = highb-lowb+1) and
(s_range_1'left = lowb) and
(s_reverse_range_1'left = highb) and
(st_arr2'length = highb-lowb+1)
) ;
wait ;
end process P ;
end ARCH00540 ;
--
entity ENT00540_Test_Bench is
end ENT00540_Test_Bench ;
architecture ARCH00540_Test_Bench of ENT00540_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00540 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00540_Test_Bench ;
--
| gpl-3.0 | 7707d90ceaad2e304569b944c5cc7742 | 0.550918 | 3.003582 | false | true | false | false |
jairov4/accel-oil | solution_spartan6/impl/vhdl/nfa_accept_sample.vhd | 1 | 68,992 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_36 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
signal reg_378 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_585 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_cast_fu_390_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_36_cast_reg_600 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_405_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_605 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_410_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_609 : STD_LOGIC_VECTOR (15 downto 0);
signal sample_addr_1_reg_614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_fu_428_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_i_reg_620 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_422_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_reg_624 : STD_LOGIC_VECTOR (63 downto 0);
signal sym_reg_629 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_1_i_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_1_i_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_reg_638 : STD_LOGIC_VECTOR (4 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bucket_index1_ph_cast_fu_444_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_448_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_i_cast_fu_452_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_19_i_cast_reg_658 : STD_LOGIC_VECTOR (13 downto 0);
signal j_end_phi_fu_316_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_673 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_18_i_reg_688 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_490_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_20_i_reg_693 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_711 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_716 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_721 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_726 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_1_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_731 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_552_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_reg_756 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_761 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_580_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_766 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_348_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_348_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_348_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_360_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_360_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_366_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_366_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_372_ap_ce : STD_LOGIC;
signal i_reg_138 : STD_LOGIC_VECTOR (15 downto 0);
signal any_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal p_01_rec_reg_150 : STD_LOGIC_VECTOR (63 downto 0);
signal next_buckets_1_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_reg_172 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_182 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_194 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_207 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_220 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_231 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_242 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_269 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_282 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_293 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_303 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal any_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_336 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal grp_nfa_get_finals_fu_366_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_fu_400_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_i_cast_fu_501_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_i_cast_fu_519_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_400_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_410_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_410_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_422_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_422_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_fu_455_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_471_p0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_471_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_484_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_484_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_490_p0 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_490_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_i_fu_494_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_7_i_fu_512_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_400_ce : STD_LOGIC;
signal grp_fu_410_ce : STD_LOGIC;
signal grp_fu_422_ce : STD_LOGIC;
signal grp_fu_471_ce : STD_LOGIC;
signal grp_fu_484_ce : STD_LOGIC;
signal grp_fu_490_ce : STD_LOGIC;
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal grp_fu_484_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_484_p10 : STD_LOGIC_VECTOR (13 downto 0);
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (5 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (13 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_348 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
p_read => grp_bitset_next_fu_348_p_read,
r_bit => grp_bitset_next_fu_348_r_bit,
r_bucket_index => grp_bitset_next_fu_348_r_bucket_index,
r_bucket => grp_bitset_next_fu_348_r_bucket,
ap_return_0 => grp_bitset_next_fu_348_ap_return_0,
ap_return_1 => grp_bitset_next_fu_348_ap_return_1,
ap_return_2 => grp_bitset_next_fu_348_ap_return_2,
ap_return_3 => grp_bitset_next_fu_348_ap_return_3,
ap_ce => grp_bitset_next_fu_348_ap_ce);
grp_nfa_get_initials_fu_360 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_360_ap_start,
ap_done => grp_nfa_get_initials_fu_360_ap_done,
ap_idle => grp_nfa_get_initials_fu_360_ap_idle,
ap_ready => grp_nfa_get_initials_fu_360_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_360_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_360_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_fu_360_ap_ce,
ap_return_0 => grp_nfa_get_initials_fu_360_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_360_ap_return_1);
grp_nfa_get_finals_fu_366 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_366_ap_start,
ap_done => grp_nfa_get_finals_fu_366_ap_done,
ap_idle => grp_nfa_get_finals_fu_366_ap_idle,
ap_ready => grp_nfa_get_finals_fu_366_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_366_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_366_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_fu_366_ap_ce,
ap_return_0 => grp_nfa_get_finals_fu_366_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_366_ap_return_1);
grp_p_bsf32_hw_fu_372 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_372_bus_r,
ap_return => grp_p_bsf32_hw_fu_372_ap_return,
ap_ce => grp_p_bsf32_hw_fu_372_ap_ce);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U17 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 17,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_400_p0,
din1 => grp_fu_400_p1,
ce => grp_fu_400_ce,
dout => grp_fu_400_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 18,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_410_p0,
din1 => grp_fu_410_p1,
ce => grp_fu_410_ce,
dout => grp_fu_410_p2);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_U19 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16
generic map (
ID => 19,
NUM_STAGE => 16,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_422_p0,
din1 => grp_fu_422_p1,
ce => grp_fu_422_ce,
dout => grp_fu_422_p2);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2
generic map (
ID => 20,
NUM_STAGE => 2,
din0_WIDTH => 6,
din1_WIDTH => 6,
dout_WIDTH => 6)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_471_p0,
din1 => grp_fu_471_p1,
ce => grp_fu_471_ce,
dout => grp_fu_471_p2);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4
generic map (
ID => 21,
NUM_STAGE => 4,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_484_p0,
din1 => grp_fu_484_p1,
ce => grp_fu_484_ce,
dout => grp_fu_484_p2);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4
generic map (
ID => 22,
NUM_STAGE => 4,
din0_WIDTH => 14,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_490_p0,
din1 => grp_fu_490_p1,
ce => grp_fu_490_ce,
dout => grp_fu_490_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_336;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_366_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st24_fsm_23 = ap_NS_fsm) and (ap_ST_st23_fsm_22 = ap_CS_fsm) and (tmp_s_reg_605 = ap_const_lv1_0))) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_366_ap_ready)) then
grp_nfa_get_finals_fu_366_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_194 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_2_1_i_reg_634 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_1;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_620 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_194 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_reg_323 assign process. --
any_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_0;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
any_reg_323 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_182 assign process. --
bus_assign_reg_182_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st40_fsm_39 = ap_CS_fsm) and (tmp_2_1_i_reg_634 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_1_reg_162;
elsif (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_620 = ap_const_lv1_0))) then
bus_assign_reg_182 <= next_buckets_0_reg_172;
end if;
end if;
end process;
-- i_reg_138 assign process. --
i_reg_138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
i_reg_138 <= i_1_reg_609;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
i_reg_138 <= ap_const_lv16_0;
end if;
end if;
end process;
-- j_bit1_reg_303 assign process. --
j_bit1_reg_303_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit1_ph_cast_fu_448_p1;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
j_bit1_reg_303 <= j_bit_reg_711;
end if;
end if;
end process;
-- j_bucket1_ph_reg_207 assign process. --
j_bucket1_ph_reg_207_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket1_ph_reg_207 <= bus_assign_reg_182;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_2_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket1_ph_reg_207 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_282 assign process. --
j_bucket1_reg_282_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket1_ph_reg_207;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
j_bucket1_reg_282 <= j_bucket_reg_721;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_220 assign process. --
j_bucket_index1_ph_reg_220_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_220 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_2_1_i_reg_634 = ap_const_lv1_0)))) then
j_bucket_index1_ph_reg_220 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_293 assign process. --
j_bucket_index1_reg_293_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index1_ph_cast_fu_444_p1;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
j_bucket_index1_reg_293 <= j_bucket_index_reg_716;
end if;
end if;
end process;
-- j_end_ph_reg_242 assign process. --
j_end_ph_reg_242_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_end_ph_reg_242 <= ap_const_lv1_0;
elsif (((ap_ST_st40_fsm_39 = ap_CS_fsm) and not((tmp_2_1_i_reg_634 = ap_const_lv1_0)))) then
j_end_ph_reg_242 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_313 assign process. --
j_end_reg_313_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
j_end_reg_313 <= j_end_ph_reg_242;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
j_end_reg_313 <= p_s_reg_726;
end if;
end if;
end process;
-- next_buckets_0_reg_172 assign process. --
next_buckets_0_reg_172_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_0_reg_172 <= tmp_buckets_0_3_reg_269;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_0_reg_172 <= current_buckets_0_reg_585;
end if;
end if;
end process;
-- next_buckets_1_reg_162 assign process. --
next_buckets_1_reg_162_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
next_buckets_1_reg_162 <= tmp_buckets_1_3_reg_256;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_1_reg_162 <= current_buckets_1_reg_590;
end if;
end if;
end process;
-- p_01_rec_reg_150 assign process. --
p_01_rec_reg_150_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
p_01_rec_reg_150 <= p_rec_reg_624;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
p_01_rec_reg_150 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_336 assign process. --
p_0_reg_336_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
p_0_reg_336 <= ap_const_lv1_0;
elsif ((ap_ST_st72_fsm_71 = ap_CS_fsm)) then
p_0_reg_336 <= tmp_2_reg_766;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_269 assign process. --
tmp_buckets_0_3_reg_269_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= ap_const_lv32_0;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_269 <= next_buckets_0_1_reg_731;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_256 assign process. --
tmp_buckets_1_3_reg_256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= ap_const_lv32_0;
elsif ((ap_ST_st62_fsm_61 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_256 <= next_buckets_1_1_fu_552_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st69_fsm_68 = ap_CS_fsm)) then
current_buckets_0_1_reg_751 <= current_buckets_0_1_fu_566_p2;
current_buckets_1_1_reg_756 <= current_buckets_1_1_fu_571_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
current_buckets_0_reg_585 <= grp_nfa_get_initials_fu_360_ap_return_0;
current_buckets_1_reg_590 <= grp_nfa_get_initials_fu_360_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
i_1_reg_609 <= grp_fu_410_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
j_bit1_ph_reg_231 <= r_bit_reg_638;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then
j_bit_reg_711 <= grp_bitset_next_fu_348_ap_return_0;
j_bucket_index_reg_716 <= grp_bitset_next_fu_348_ap_return_1;
j_bucket_reg_721 <= grp_bitset_next_fu_348_ap_return_2;
p_s_reg_726 <= grp_bitset_next_fu_348_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm))) then
next_buckets_0_1_reg_731 <= next_buckets_0_1_fu_546_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
p_rec_reg_624 <= grp_fu_422_p2;
sym_reg_629 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
r_bit_reg_638 <= grp_p_bsf32_hw_fu_372_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st60_fsm_59 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm)))) then
reg_378 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
sample_addr_1_reg_614 <= grp_fu_400_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
state_reg_673 <= grp_fu_471_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st50_fsm_49 = ap_CS_fsm)) then
tmp_18_i_reg_688 <= grp_fu_484_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
tmp_19_i_cast_reg_658(0) <= tmp_19_i_cast_fu_452_p1(0);
tmp_19_i_cast_reg_658(1) <= tmp_19_i_cast_fu_452_p1(1);
tmp_19_i_cast_reg_658(2) <= tmp_19_i_cast_fu_452_p1(2);
tmp_19_i_cast_reg_658(3) <= tmp_19_i_cast_fu_452_p1(3);
tmp_19_i_cast_reg_658(4) <= tmp_19_i_cast_fu_452_p1(4);
tmp_19_i_cast_reg_658(5) <= tmp_19_i_cast_fu_452_p1(5);
tmp_19_i_cast_reg_658(6) <= tmp_19_i_cast_fu_452_p1(6);
tmp_19_i_cast_reg_658(7) <= tmp_19_i_cast_fu_452_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st70_fsm_69 = ap_CS_fsm)) then
tmp_1_reg_761 <= tmp_1_fu_576_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st54_fsm_53 = ap_CS_fsm)) then
tmp_20_i_reg_693 <= grp_fu_490_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_2_i_reg_620 = ap_const_lv1_0)))) then
tmp_2_1_i_reg_634 <= tmp_2_1_i_fu_434_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
tmp_2_i_reg_620 <= tmp_2_i_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st71_fsm_70 = ap_CS_fsm)) then
tmp_2_reg_766 <= tmp_2_fu_580_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
tmp_36_cast_reg_600(0) <= tmp_36_cast_fu_390_p1(0);
tmp_36_cast_reg_600(1) <= tmp_36_cast_fu_390_p1(1);
tmp_36_cast_reg_600(2) <= tmp_36_cast_fu_390_p1(2);
tmp_36_cast_reg_600(3) <= tmp_36_cast_fu_390_p1(3);
tmp_36_cast_reg_600(4) <= tmp_36_cast_fu_390_p1(4);
tmp_36_cast_reg_600(5) <= tmp_36_cast_fu_390_p1(5);
tmp_36_cast_reg_600(6) <= tmp_36_cast_fu_390_p1(6);
tmp_36_cast_reg_600(7) <= tmp_36_cast_fu_390_p1(7);
tmp_36_cast_reg_600(8) <= tmp_36_cast_fu_390_p1(8);
tmp_36_cast_reg_600(9) <= tmp_36_cast_fu_390_p1(9);
tmp_36_cast_reg_600(10) <= tmp_36_cast_fu_390_p1(10);
tmp_36_cast_reg_600(11) <= tmp_36_cast_fu_390_p1(11);
tmp_36_cast_reg_600(12) <= tmp_36_cast_fu_390_p1(12);
tmp_36_cast_reg_600(13) <= tmp_36_cast_fu_390_p1(13);
tmp_36_cast_reg_600(14) <= tmp_36_cast_fu_390_p1(14);
tmp_36_cast_reg_600(15) <= tmp_36_cast_fu_390_p1(15);
tmp_36_cast_reg_600(16) <= tmp_36_cast_fu_390_p1(16);
tmp_36_cast_reg_600(17) <= tmp_36_cast_fu_390_p1(17);
tmp_36_cast_reg_600(18) <= tmp_36_cast_fu_390_p1(18);
tmp_36_cast_reg_600(19) <= tmp_36_cast_fu_390_p1(19);
tmp_36_cast_reg_600(20) <= tmp_36_cast_fu_390_p1(20);
tmp_36_cast_reg_600(21) <= tmp_36_cast_fu_390_p1(21);
tmp_36_cast_reg_600(22) <= tmp_36_cast_fu_390_p1(22);
tmp_36_cast_reg_600(23) <= tmp_36_cast_fu_390_p1(23);
tmp_36_cast_reg_600(24) <= tmp_36_cast_fu_390_p1(24);
tmp_36_cast_reg_600(25) <= tmp_36_cast_fu_390_p1(25);
tmp_36_cast_reg_600(26) <= tmp_36_cast_fu_390_p1(26);
tmp_36_cast_reg_600(27) <= tmp_36_cast_fu_390_p1(27);
tmp_36_cast_reg_600(28) <= tmp_36_cast_fu_390_p1(28);
tmp_36_cast_reg_600(29) <= tmp_36_cast_fu_390_p1(29);
tmp_36_cast_reg_600(30) <= tmp_36_cast_fu_390_p1(30);
tmp_36_cast_reg_600(31) <= tmp_36_cast_fu_390_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st68_fsm_67 = ap_CS_fsm)) then
tmp_buckets_0_reg_741 <= grp_nfa_get_finals_fu_366_ap_return_0;
tmp_buckets_1_reg_746 <= grp_nfa_get_finals_fu_366_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
tmp_s_reg_605 <= tmp_s_fu_405_p2;
end if;
end if;
end process;
tmp_36_cast_reg_600(63 downto 32) <= "00000000000000000000000000000000";
tmp_19_i_cast_reg_658(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_605 , tmp_2_i_reg_620 , tmp_2_1_i_reg_634 , j_end_phi_fu_316_p4 , any_phi_fu_328_p4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
if ((tmp_s_reg_605 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st63_fsm_62;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_620 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_2_i_reg_620 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
if (not((tmp_2_1_i_reg_634 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st41_fsm_40;
end if;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and not((ap_const_lv1_0 = any_phi_fu_328_p4)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_316_p4)) and (ap_const_lv1_0 = any_phi_fu_328_p4))) then
ap_NS_fsm <= ap_ST_st73_fsm_72;
else
ap_NS_fsm <= ap_ST_st46_fsm_45;
end if;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st61_fsm_60;
else
ap_NS_fsm <= ap_ST_st60_fsm_59;
end if;
when ap_ST_st61_fsm_60 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st62_fsm_61;
else
ap_NS_fsm <= ap_ST_st61_fsm_60;
end if;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_194),2));
any_phi_fu_328_p4 <= any_reg_323;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st73_fsm_72 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_336, ap_return_preg)
begin
if ((ap_ST_st73_fsm_72 = ap_CS_fsm)) then
ap_return <= p_0_reg_336;
else
ap_return <= ap_return_preg;
end if;
end process;
current_buckets_0_1_fu_566_p2 <= (next_buckets_0_reg_172 and tmp_buckets_0_reg_741);
current_buckets_1_1_fu_571_p2 <= (next_buckets_1_reg_162 and tmp_buckets_1_reg_746);
-- grp_bitset_next_fu_348_ap_ce assign process. --
grp_bitset_next_fu_348_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_316_p4)
begin
if ((((ap_ST_st45_fsm_44 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_316_p4)) or (ap_ST_st46_fsm_45 = ap_CS_fsm) or (ap_ST_st47_fsm_46 = ap_CS_fsm) or (ap_ST_st50_fsm_49 = ap_CS_fsm) or (ap_ST_st54_fsm_53 = ap_CS_fsm) or (ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm) or (ap_ST_st48_fsm_47 = ap_CS_fsm) or (ap_ST_st49_fsm_48 = ap_CS_fsm) or (ap_ST_st51_fsm_50 = ap_CS_fsm) or (ap_ST_st52_fsm_51 = ap_CS_fsm) or (ap_ST_st53_fsm_52 = ap_CS_fsm))) then
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_1;
else
grp_bitset_next_fu_348_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_bitset_next_fu_348_p_read <= next_buckets_1_reg_162;
grp_bitset_next_fu_348_r_bit <= j_bit1_reg_303;
grp_bitset_next_fu_348_r_bucket <= j_bucket1_reg_282;
grp_bitset_next_fu_348_r_bucket_index <= j_bucket_index1_reg_293;
grp_fu_400_ce <= ap_const_logic_1;
grp_fu_400_p0 <= p_01_rec_reg_150;
grp_fu_400_p1 <= tmp_36_cast_reg_600;
grp_fu_410_ce <= ap_const_logic_1;
grp_fu_410_p0 <= i_reg_138;
grp_fu_410_p1 <= ap_const_lv16_1;
-- grp_fu_422_ce assign process. --
grp_fu_422_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_605)
begin
if (((ap_ST_st38_fsm_37 = ap_CS_fsm) or ((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or ((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((tmp_s_reg_605 = ap_const_lv1_0))) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm))) then
grp_fu_422_ce <= ap_const_logic_1;
else
grp_fu_422_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_422_p0 <= p_01_rec_reg_150;
grp_fu_422_p1 <= ap_const_lv64_1;
grp_fu_471_ce <= ap_const_logic_1;
grp_fu_471_p0 <= (tmp_31_fu_455_p1 & ap_const_lv5_0);
grp_fu_471_p1 <= j_bit1_reg_303(6 - 1 downto 0);
grp_fu_484_ce <= ap_const_logic_1;
grp_fu_484_p0 <= grp_fu_484_p00(8 - 1 downto 0);
grp_fu_484_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_484_p1 <= grp_fu_484_p10(6 - 1 downto 0);
grp_fu_484_p10 <= std_logic_vector(resize(unsigned(state_reg_673),14));
grp_fu_490_ce <= ap_const_logic_1;
grp_fu_490_p0 <= tmp_18_i_reg_688;
grp_fu_490_p1 <= tmp_19_i_cast_reg_658;
grp_nfa_get_finals_fu_366_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_366_ap_start <= grp_nfa_get_finals_fu_366_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_360_ap_ce <= ap_const_logic_1;
-- grp_nfa_get_initials_fu_360_ap_start assign process. --
grp_nfa_get_initials_fu_360_ap_start_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_1;
else
grp_nfa_get_initials_fu_360_ap_start <= ap_const_logic_0;
end if;
end process;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
-- grp_p_bsf32_hw_fu_372_ap_ce assign process. --
grp_p_bsf32_hw_fu_372_ap_ce_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st42_fsm_41 = ap_CS_fsm) or (ap_ST_st41_fsm_40 = ap_CS_fsm))) then
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_372_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_p_bsf32_hw_fu_372_bus_r <= bus_assign_reg_182;
j_bit1_ph_cast_fu_448_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_231),8));
j_bucket_index1_ph_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_220),8));
j_end_phi_fu_316_p4 <= j_end_reg_313;
next_buckets_0_1_fu_546_p2 <= (tmp_buckets_0_3_reg_269 or reg_378);
next_buckets_1_1_fu_552_p2 <= (tmp_buckets_1_3_reg_256 or reg_378);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_366_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_6_i_cast_fu_501_p1, tmp_7_i_cast_fu_519_p1)
begin
if ((ap_ST_st56_fsm_55 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_7_i_cast_fu_519_p1(32 - 1 downto 0);
elsif ((ap_ST_st55_fsm_54 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_6_i_cast_fu_501_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st55_fsm_54 = ap_CS_fsm) or (ap_ST_st56_fsm_55 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st60_fsm_59 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st61_fsm_60 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_360_nfa_initials_buckets_size;
sample_address <= sample_addr_1_reg_614;
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
tmp_19_i_cast_fu_452_p1 <= std_logic_vector(resize(unsigned(sym_reg_629),14));
tmp_1_fu_576_p2 <= (current_buckets_1_1_reg_756 or current_buckets_0_1_reg_751);
tmp_2_1_i_fu_434_p2 <= "1" when (next_buckets_1_reg_162 = ap_const_lv32_0) else "0";
tmp_2_fu_580_p2 <= "0" when (tmp_1_reg_761 = ap_const_lv32_0) else "1";
tmp_2_i_fu_428_p2 <= "1" when (next_buckets_0_reg_172 = ap_const_lv32_0) else "0";
tmp_31_fu_455_p1 <= j_bucket_index1_reg_293(1 - 1 downto 0);
tmp_36_cast_fu_390_p1 <= std_logic_vector(resize(unsigned(tmp_36),64));
tmp_6_i_cast_fu_501_p1 <= std_logic_vector(resize(unsigned(tmp_6_i_fu_494_p3),64));
tmp_6_i_fu_494_p3 <= (tmp_20_i_reg_693 & ap_const_lv1_0);
tmp_7_i_cast_fu_519_p1 <= std_logic_vector(resize(unsigned(tmp_7_i_fu_512_p3),64));
tmp_7_i_fu_512_p3 <= (tmp_20_i_reg_693 & ap_const_lv1_1);
tmp_s_fu_405_p2 <= "1" when (unsigned(i_reg_138) < unsigned(length_r)) else "0";
end behav;
| lgpl-3.0 | bb303e96694934923bef4ec571d12277 | 0.577415 | 2.743766 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00477.vhd | 1 | 2,438 | -- NEED RESULT: ARCH00477: Functions can return dynamically sized objects passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00477
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00477)
-- ENT00477_Test_Bench(ARCH00477_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
-- 11-DEC-1989 - GDT: added parameter "n" to function record_func to
-- eliminate global reference.
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00477 of E00000 is
function array_func ( n,x : integer ) return t_arr1 is
variable a : t_arr1 (lowb to n) ;
begin
for i in lowb to n loop
a(i) := st_int1 ( x + i ) ;
end loop ;
return a;
end array_func ;
procedure proc ( n : in integer ;
b : out boolean ;
x : out integer ) is
type rec is record
bo : boolean ;
a : t_arr1 (lowb to n) ;
end record ;
variable rr : rec ;
function record_func ( k,n : integer ) return rec is
variable r : rec ;
begin
r.bo := true ;
for i in lowb to n loop
r.a(i) := st_int1 ( k + i ) ;
end loop ;
return r;
end record_func ;
begin
rr := record_func(13, n) ;
b := rr.bo ;
x := integer ( rr.a(n-1) ) ;
end proc ;
begin
P :
process
variable b : boolean;
variable x : integer;
begin
proc (10, b, x) ;
test_report ( "ARCH00477" ,
"Functions can return dynamically sized objects" ,
(b = true) and
(x = 13+10-1) and
(array_func(10,15) (9) = 15+9)
) ;
wait ;
end process P ;
end ARCH00477 ;
entity ENT00477_Test_Bench is
end ENT00477_Test_Bench ;
architecture ARCH00477_Test_Bench of ENT00477_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00477 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00477_Test_Bench ;
| gpl-3.0 | 63114877f0f45a65e73209f77f0093d8 | 0.486874 | 3.438646 | false | true | false | false |
wsoltys/AtomFpga | src/AVR8/Memory/XPM8Kx16.vhd | 1 | 28,504 | --************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;
| apache-2.0 | 772dc0a123a5c30ad11774d00d20a3bf | 0.599319 | 2.364692 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_2.vhd | 4 | 4,750 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity dictionary_2 is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_2;
architecture Behavioral of dictionary_2 is
signal wr_addr_shift : std_logic_vector(11 downto 0);
signal search_completed_i : std_logic;
signal full : std_logic;
signal wr_addr : std_logic_vector(11 downto 0);
signal wr_addr_block0 : std_logic_vector(11 downto 0);
signal wr_addr_block1 : std_logic_vector(11 downto 0);
signal block0_wr_en : std_logic;
signal block0_prefix : std_logic_vector(10 downto 0);
signal block0_prefix_shift : std_logic_vector(11 downto 0);
signal block0_entry_found : std_logic;
signal block0_search_completed : std_logic;
signal block1_wr_en : std_logic;
signal block1_prefix : std_logic_vector(10 downto 0);
signal block1_entry_found : std_logic;
signal block1_search_completed : std_logic;
signal halt_search : std_logic;
begin
wr_addr_shift(11 downto 1) <= wr_addr(10 downto 0);
wr_addr_shift(0) <= '0';
block0_prefix_shift(11 downto 1) <= block0_prefix;
block0_prefix_shift(0) <= '0';
--Combines all signals from blocks
search_completed <= search_completed_i;
process(clk,rst)
begin
if rst = '1' then
block1_wr_en <= '0';
block0_wr_en <= '0';
search_completed_i <= '0';
entry_found <= '0';
prefix <= x"000";
elsif rising_edge(clk) then
block1_wr_en <= not wr_addr(0) and wr_en;
block0_wr_en <= wr_addr(0) and wr_en;
search_completed_i <= block0_search_completed or block1_search_completed;
entry_found <= block0_entry_found or block1_entry_found;
if block0_entry_found = '1' then
if block0_prefix_shift = x"000" then
prefix <= x"001";
else
prefix <= std_logic_vector(unsigned(block0_prefix_shift)-to_unsigned(1,12));
end if;
elsif block1_entry_found = '1' then
prefix(11 downto 1) <= block1_prefix;
prefix(0) <= '0';
end if;
end if;
end process;
U_BLOCK_0 : entity work.dictionary_block_2
generic map (block_num => 0)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
halt_search => search_completed_i,
wr_en => block0_wr_en,
wr_addr => wr_addr(11 downto 1),
wr_entry => wr_entry,
prefix => block0_prefix,
entry_found => block0_entry_found,
search_completed => block0_search_completed);
U_BLOCK_1 : entity work.dictionary_block_2
generic map (block_num => 1)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => block1_wr_en,
wr_addr => wr_addr(11 downto 1),
wr_entry => wr_entry,
halt_search => search_completed_i,
prefix => block1_prefix,
entry_found => block1_entry_found,
search_completed => block1_search_completed);
--write proc
dictionary_full <= full;
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(254,12));
wr_addr_block0 <= std_logic_vector(to_unsigned(127,12));
wr_addr_block1 <= std_logic_vector(to_unsigned(127,12));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,12)+unsigned(wr_addr));
wr_addr_block0 <= std_logic_vector(unsigned(wr_addr_shift)-to_unsigned(1,12));
wr_addr_block1 <= wr_addr_shift;
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(11) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense | 20bef15209d92e6a65a270e5e0f06766 | 0.537474 | 3.685027 | false | false | false | false |
grwlf/vsim | vhdl_ct/WORK/generic_standard_types.vhd | 1 | 28,221 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
entity GENERIC_STANDARD_TYPES is
generic ( lowb : integer := 1 ;
highb : integer := 10 ;
lowb_i2 : integer := 0 ;
highb_i2 : integer := 1000 ;
lowb_p : integer := -100 ;
highb_p : integer := 10000 ;
lowb_r : real := 0.0 ;
highb_r : real := 1000.0 ) ;
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
function bf_boolean(to_resolve : boolean_vector) return boolean ;
subtype rboolean is bf_boolean boolean ;
function bf_bit(to_resolve : bit_vector) return bit ;
--
subtype rbit is bf_bit bit ;
--
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level ;
--
subtype rseverity_level is bf_severity_level severity_level ;
function bf_character(to_resolve : string) return character ;
--
subtype rcharacter is bf_character character ;
--
function bf_enum1(to_resolve : enum1_vector) return st_enum1 ;
--
subtype rst_enum1 is bf_enum1 st_enum1 ;
--
function bf_integer(to_resolve : integer_vector) return integer ;
--
subtype rinteger is bf_integer integer ;
--
function bf_int1(to_resolve : int1_vector) return st_int1 ;
--
subtype rst_int1 is bf_int1 st_int1 ;
--
function bf_time(to_resolve : time_vector) return time ;
--
subtype rtime is bf_time time ;
--
function bf_phys1(to_resolve : phys1_vector) return st_phys1 ;
--
subtype rst_phys1 is bf_phys1 st_phys1 ;
--
function bf_real(to_resolve : real_vector) return real ;
--
subtype rreal is bf_real real ;
--
function bf_real1(to_resolve : real1_vector) return st_real1 ;
--
subtype rst_real1 is bf_real1 st_real1 ;
--
function bf_rec1(to_resolve : rec1_vector) return st_rec1 ;
--
subtype rst_rec1 is bf_rec1 st_rec1 ;
--
function bf_rec2(to_resolve : rec2_vector) return st_rec2 ;
--
subtype rst_rec2 is bf_rec2 st_rec2 ;
--
function bf_arr1(to_resolve : arr1_vector) return st_arr1 ;
--
subtype rst_arr1 is bf_arr1 st_arr1 ;
--
function bf_arr2(to_resolve : arr2_vector) return st_arr2 ;
--
subtype rst_arr2 is bf_arr2 st_arr2 ;
--
function bf_rec3(to_resolve : rec3_vector) return st_rec3 ;
--
subtype rst_rec3 is bf_rec3 st_rec3 ;
--
function bf_arr3(to_resolve : arr3_vector) return st_arr3 ;
--
subtype rst_arr3 is bf_arr3 st_arr3 ;
--
constant d_boolean : boolean := boolean'left ;
constant d_bit : bit := bit'left ;
constant d_severity_level : severity_level := severity_level'left ;
constant d_character : character := character'left ;
constant d_t_enum1 : t_enum1 := t_enum1'left ;
constant d_st_enum1 : st_enum1 := st_enum1'left ;
constant d_integer : integer := integer'left ;
constant d_t_int1 : t_int1 := t_int1'left ;
constant d_st_int1 : st_int1 := st_int1'left ;
constant d_time : time := time'left ;
constant d_t_phys1 : t_phys1 := t_phys1'left ;
constant d_st_phys1 : st_phys1 := st_phys1'left ;
constant d_real : real := real'left ;
constant d_t_real1 : t_real1 := t_real1'left ;
constant d_st_real1 : st_real1 := st_real1'left ;
constant d_st_bit_vector : st_bit_vector :=
(others => bit'left) ;
constant d_st_string : st_string :=
(others => character'left) ;
constant d_t_rec1 : t_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_st_rec1 : st_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_t_rec2 : t_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_rec2 : st_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_arr1 : st_arr1 :=
(others => st_int1'left) ;
constant d_st_arr2 : st_arr2 :=
(others => (others => d_st_arr1) ) ;
constant d_t_rec3 : t_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_rec3 : st_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_arr3 : st_arr3 :=
(others => (others => d_st_rec3) ) ;
-- file types
type f_boolean is file of boolean ;
type f_bit is file of bit ;
type f_character is file of character ;
type f_integer is file of integer ;
type f_time is file of time ;
type f_real is file of real ;
-- with constraints
type f_st_enum1 is file of st_enum1 ;
type f_st_int1 is file of st_int1 ;
type f_st_phys1 is file of st_phys1 ;
type f_st_rec1 is file of st_rec1 ;
type f_st_rec2 is file of st_rec2 ;
type f_st_arr1 is file of st_arr1 ;
--
-- without constraints
type f_enum1 is file of t_enum1 ;
type f_int1 is file of t_int1 ;
type f_phys1 is file of t_phys1 ;
type f_rec1 is file of t_rec1 ;
type f_rec2 is file of t_rec2 ;
type f_arr1 is file of t_arr1 ;
--
-- access types
type a_boolean is access boolean ;
type a_bit is access bit ;
type a_severity_level is access severity_level ;
type a_character is access character ;
type a_t_enum1 is access t_enum1 ;
type a_st_enum1 is access st_enum1 ;
type a_integer is access integer ;
type a_t_int1 is access t_int1 ;
type a_st_int1 is access st_int1 ;
type a_time is access time ;
type a_t_phys1 is access t_phys1 ;
type a_st_phys1 is access st_phys1 ;
type a_real is access real ;
type a_t_real1 is access t_real1 ;
type a_st_real1 is access st_real1 ;
type a_bit_vector is access bit_vector ;
type a_string is access string ;
type a_t_rec1 is access t_rec1 ;
type a_st_rec1 is access st_rec1 ;
type a_t_rec2 is access t_rec2 ;
type a_st_rec2 is access st_rec2 ;
type a_t_rec3 is access t_rec3 ;
type a_st_rec3 is access st_rec3 ;
type a_t_arr1 is access t_arr1 ;
type a_st_arr1 is access st_arr1 ;
type a_t_arr2 is access t_arr2 ;
type a_st_arr2 is access st_arr2 ;
type a_t_arr3 is access t_arr3 ;
type a_st_arr3 is access st_arr3 ;
type a_st_boolean_vector is access st_boolean_vector ;
type a_st_bit_vector is access st_bit_vector ;
type a_st_severity_level_vector is access st_severity_level_vector ;
type a_st_string is access st_string ;
type a_st_enum1_vector is access st_enum1_vector ;
type a_st_integer_vector is access st_integer_vector ;
type a_st_int1_vector is access st_int1_vector ;
type a_st_time_vector is access st_time_vector ;
type a_st_phys1_vector is access st_phys1_vector ;
type a_st_real_vector is access st_real_vector ;
type a_st_real1_vector is access st_real1_vector ;
type a_st_rec1_vector is access st_rec1_vector ;
type a_st_rec2_vector is access st_rec2_vector ;
type a_st_arr1_vector is access st_arr1_vector ;
type a_st_arr2_vector is access st_arr2_vector ;
type a_st_rec3_vector is access st_rec3_vector ;
type a_st_arr3_vector is access st_arr3_vector ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
end GENERIC_STANDARD_TYPES ;
| gpl-3.0 | 4757d7883a38519d10aa709b5999afed | 0.585911 | 3.10462 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00678.vhd | 1 | 2,636 | -- NEED RESULT: ARCH00678: Subelements of signals are signals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00678
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (3)
-- 4.3.1.2 (4)
-- 4.3.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00678
-- PKG00678/BODY
-- E00000(ARCH00678)
-- ENT00678_Test_Bench(ARCH00678_Test_Bench)
--
-- REVISION HISTORY:
--
-- 1-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
package PKG00678 is
function bf2_arr3 ( to_resolve : arr3_vector ) return st_arr3 ;
subtype rst2_arr3 is bf2_arr3 st_arr3 ;
end PKG00678 ;
package body PKG00678 is
function bf2_arr3 ( to_resolve : arr3_vector ) return st_arr3 is
begin
return to_resolve(to_resolve'left) ;
end bf2_arr3 ;
end PKG00678 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00678.all ;
architecture ARCH00678 of E00000 is
signal s_arr3 : rst2_arr3 ;
signal toggle : boolean := false ;
begin
process
variable v_int : integer := lowb ;
begin
s_arr3 <= c_st_arr3_1 ;
s_arr3(v_int, false).f1 <= true ;
s_arr3(v_int, false).f3(lowb, true)(v_int) <= st_int1 (lowb+10) ;
toggle <= true ;
wait;
end process ;
process
begin
s_arr3 <= c_st_arr3_1 ;
s_arr3(lowb, false).f1 <= true ;
s_arr3(lowb, false).f3(lowb, true)(lowb) <= st_int1 (lowb + 11) ;
wait;
end process ;
process (toggle)
variable v_arr3_1, v_arr3_2 : st_arr3 := c_st_arr3_1 ;
begin
if toggle then
v_arr3_1(lowb, false).f1 := true ;
v_arr3_2(lowb, false).f1 := true ;
v_arr3_1(lowb, false).f3(lowb, true)(lowb) := st_int1 (lowb + 10) ;
v_arr3_2(lowb, false).f3(lowb, true)(lowb) := st_int1 (lowb + 11) ;
test_report ( "ARCH00678" ,
"Subelements of signals are signals" ,
v_arr3_1 = s_arr3 or v_arr3_2 = s_arr3 ) ;
end if ;
end process ;
end ARCH00678 ;
--
entity ENT00678_Test_Bench is
end ENT00678_Test_Bench ;
architecture ARCH00678_Test_Bench of ENT00678_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00678 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00678_Test_Bench ;
--
| gpl-3.0 | 10e5cd45b1e16f0892f7e24eb40559f8 | 0.533005 | 2.919158 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_1024_1/synth/bram_1024_1.vhd | 4 | 14,457 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_1;
ARCHITECTURE bram_1024_1_arch OF bram_1024_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_1_arch : ARCHITECTURE IS "bram_1024_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_1_arch: ARCHITECTURE IS "bram_1024_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_1.mi" &
"f,C_INIT_FILE=bram_1024_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_1.mif",
C_INIT_FILE => "bram_1024_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_1_arch;
| unlicense | 56966ec38b91277c57e8a1502bd186a3 | 0.625372 | 3.002492 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00220.vhd | 1 | 5,208 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00220
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00220(ARCH00220)
-- ENT00220_Test_Bench(ARCH00220_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00220 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00220 ;
--
--
architecture ARCH00220 of ENT00220 is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(2)(1 to 2) <= transport
c_st_arr1_vector_2(2)(1 to 2) after 10 ns ;
wait until s_st_arr1_vector(2)(1 to 2) =
c_st_arr1_vector_2(2)(1 to 2) ;
Test_Report (
"ENT00220",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(2)(1 to 2) =
c_st_arr1_vector_2(2)(1 to 2) )) ;
--
when 1
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(G)(G-1 to G) <= transport
c_st_arr1_vector_2(G)(G-1 to G) after 10 ns ;
wait until s_st_arr1_vector(G)(G-1 to G) =
c_st_arr1_vector_2(G)(G-1 to G) ;
Test_Report (
"ENT00220",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(G)(G-1 to G) =
c_st_arr1_vector_2(G)(G-1 to G) )) ;
--
when 2
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(CG)(CG-1 to CG) <= transport
c_st_arr1_vector_2(CG)(CG-1 to CG) after 10 ns ;
wait until s_st_arr1_vector(CG)(CG-1 to CG) =
c_st_arr1_vector_2(CG)(CG-1 to CG) ;
Test_Report (
"ENT00220",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG)(CG-1 to CG) =
c_st_arr1_vector_2(CG)(CG-1 to CG) )) ;
--
when 3
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) <= transport
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) after 10 ns ;
wait until s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) ;
Test_Report (
"ENT00220",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_arr1_vector
, counter
, correct
, savtime
, chk_st_arr1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_arr1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00220 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00220_Test_Bench is
end ENT00220_Test_Bench ;
--
--
architecture ARCH00220_Test_Bench of ENT00220_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00220 ( ARCH00220 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00220_Test_Bench ;
| gpl-3.0 | 51efeba39a20be477b47af1ac6baae09 | 0.496928 | 3.32567 | false | true | false | false |
rauenzi/VHDL-Communications | SPI_display.vhd | 1 | 4,598 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/30/14
--Last Modified: 11/2/14
--
--Description: This takes in 16 bit data and displays them on an external display
-- using GPIO and SPI communication.
--
--Version: 1.1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end SPI_display;
architecture Behavioral of SPI_display is
signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;
signal clkCnt : integer := 0;
signal StateClock : std_logic :='0';
type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,
state10,state11,state12,state13,state14,state15,state16,state17,state18);
signal currentState : state_type :=state0;
signal nextState : state_type;
signal dataSection : std_logic_vector(7 downto 0);
signal byteChoice: integer :=0;
signal byteMax: integer :=8;
begin
ClkEnable : process(BoardClock)
begin
if rising_edge(BoardClock) then
if clkCnt = clkMax then
StateClock <= '1';
clkCnt <= 0;
else
clkCnt<=clkCnt+1;
StateClock <= '0';
end if;
end if;
end process ClkEnable;
StateChange: process (BoardClock,StateClock)
begin
if (rising_edge(BoardClock) and StateClock='1') then
if currentState = state18 then
if byteChoice = byteMax then
byteChoice <= byteChoice-3;
else
byteChoice<=byteChoice+1;
end if;
end if;
currentState <= nextState;
end if;
end process StateChange;
States: process(currentState)
begin
case currentState is
when state0=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
when state1=>
SCK<='0';
SS<='0';
MOSI<=dataSection(7);
nextState<=state2;
when state2=>
SCK<='1';
SS<='0';
MOSI<=dataSection(7);
nextState<=state3;
when state3=>
SCK<='0';
SS<='0';
MOSI<=dataSection(6);
nextState<=state4;
when state4=>
SCK<='1';
SS<='0';
MOSI<=dataSection(6);
nextState<=state5;
when state5=>
SCK<='0';
SS<='0';
MOSI<=dataSection(5);
nextState<=state6;
when state6=>
SCK<='1';
SS<='0';
MOSI<=dataSection(5);
nextState<=state7;
when state7=>
SCK<='0';
SS<='0';
MOSI<=dataSection(4);
nextState<=state8;
when state8=>
SCK<='1';
SS<='0';
MOSI<=dataSection(4);
nextState<=state9;
when state9=>
SCK<='0';
SS<='0';
MOSI<=dataSection(3);
nextState<=state10;
when state10=>
SCK<='1';
SS<='0';
MOSI<=dataSection(3);
nextState<=state11;
when state11=>
SCK<='0';
SS<='0';
MOSI<=dataSection(2);
nextState<=state12;
when state12=>
SCK<='1';
SS<='0';
MOSI<=dataSection(2);
nextState<=state13;
when state13=>
SCK<='0';
SS<='0';
MOSI<=dataSection(1);
nextState<=state14;
when state14=>
SCK<='1';
SS<='0';
MOSI<=dataSection(1);
nextState<=state15;
when state15=>
SCK<='0';
SS<='0';
MOSI<=dataSection(0);
nextState<=state16;
when state16=>
SCK<='1';
SS<='0';
MOSI<=dataSection(0);
nextState<=state17;
when state17=>
SCK<='0';
SS<='0';
MOSI<=datasection(0);
nextState<=state18;
when state18=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
end case;
end process States;
ByteSelection: process(byteChoice)
begin
case byteChoice is
when 0 => dataSection<=x"76";
when 1 => dataSection<=x"76";
when 2 => dataSection<=x"76";
when 3 => dataSection<=x"76";
when 4 => dataSection<=x"76";
when 5 => dataSection <=x"0" & Data(15 downto 12);
when 6 => dataSection <=x"0" & Data(11 downto 8);
when 7 => dataSection <=x"0" & Data(7 downto 4);
when 8 => dataSection <=x"0" & Data(3 downto 0);
when others => dataSection <="11111111";
end case;
end process ByteSelection;
end Behavioral;
| apache-2.0 | de7c7e85e63468ce83e4e3c872184c5d | 0.542192 | 3.696141 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/synopsys/std_logic_misc-body.vhdl | 5 | 27,647 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
| gpl-3.0 | 3cd4274e5179900de04cb7f02d15f7f4 | 0.382682 | 3.265651 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.