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jdryg/tis100cpu | cpu_1x3_tb.vhd | 1 | 1,319 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_1x3_tb IS
END cpu_1x3_tb;
ARCHITECTURE behavior OF cpu_1x3_tb IS
-- Component Declaration
component cpu_1x3 is
generic (
PROGRAM_00 : string := "input.prg";
PROGRAM_01 : string := "passthrough.prg";
PROGRAM_02 : string := "output.prg");
port (
I_clk : in std_logic;
I_reset : in std_logic);
end component;
-- Inputs
signal I_clk : std_logic := '0';
signal I_reset : std_logic := '0';
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Component Instantiation
uut: cpu_1x3
generic map (
PROGRAM_00 => "F:\Projects\MyStuff\TIS100\Assembler\input.prg",
PROGRAM_01 => "F:\Projects\MyStuff\TIS100\Assembler\double.prg",
PROGRAM_02 => "F:\Projects\MyStuff\TIS100\Assembler\output.prg")
PORT MAP(
I_clk => I_clk,
I_reset => I_reset);
-- Clock process definitions
I_clk_process: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
I_reset <= '1';
wait for I_clk_period;
I_reset <= '0';
wait;
end process;
END;
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`protect end_protected
| apache-2.0 | 2e504ceee786e9a827b797116bbf69fe | 0.946107 | 1.835805 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/checkbit_handler.vhd | 1 | 22,877 | -------------------------------------------------------------------------------
-- $Id: checkbit_handler.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_LUT6: if (C_USE_LUT6) generate
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
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`protect end_protected
| apache-2.0 | 2bef657413a03c3e80df4e289e8788d2 | 0.943807 | 1.849531 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/TOPENT_TEMPLATE.vhd | 2 | 4,989 | library ieee;
use ieee.std_logic_1164.all;
use work.CONSTANTS.all;
entity TOP_ENTITY is
port(
clock : in std_logic;
reset : in std_logic;
data : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address : in std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : in std_logic;
R_enable : in std_logic;
generic_enable : in std_logic;
interrupt : out std_logic
);
end TOP_ENTITY;
architecture STRUCTURAL of TOP_ENTITY is
component DATA_BUFFER is
port(
rst : in std_logic;
row_0 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- First line of the buffer. Must be read constantly by the ip manager
--PORT_0
data_cpu : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address_cpu : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_CPU : in std_logic;
RE_CPU : in std_logic;
GE_CPU : in std_logic;
--PORT_1
data_in_ip : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_out_ip : out std_logic_vector (DATA_WIDTH-1 downto 0);
address_ip : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_IP : in std_logic;
RE_IP : in std_logic;
GE_IP : in std_logic
);
end component DATA_BUFFER;
--COMPONENTS HERE--
signal row_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_in_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_out_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal address_ip : std_logic_vector (ADD_WIDTH-1 downto 0);
signal WE_IP : std_logic;
signal RE_IP : std_logic;
signal GE_IP : std_logic;
signal data_in_IPs : data_array;
signal data_out_IPs : data_array;
signal add_IPs : add_array;
signal W_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal R_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal generic_en_IPs : std_logic_vector(0 to NUM_IPS-1);
signal enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal ack_IPs : std_logic_vector(0 to NUM_IPS-1);
signal interrupt_IPs : std_logic_vector(0 to NUM_IPS-1);
begin
data_buff: DATA_BUFFER
port map( rst => reset,
row_0 => row_0,
--PORT_0
data_cpu => data,
address_cpu => address,
WE_CPU => W_enable,
RE_CPU => R_enable,
GE_CPU => generic_enable,
--PORT_1
data_in_ip => data_in_ip,
data_out_ip => data_out_ip,
address_ip => address_ip,
WE_IP => WE_IP,
RE_IP => RE_IP,
GE_IP => GE_IP);
--HERE MANAGER--
ip_man: IP_MANAGER
port map( clk => clock,
rst => reset,
data_in => data_in_ip,
data_out => data_out_ip,
add => address_ip,
W_enable => WE_IP,
R_enable => RE_IP,
generic_en => GE_IP,
interrupt => interrupt,
row_0 => row_0,
data_in_IPs => data_in_IPs,
data_out_IPs => data_out_IPs,
add_IPs => add_IPs,
W_enable_IPs => W_enable_IPs,
R_enable_IPs => R_enable_IPs,
generic_en_IPs => generic_en_IPs,
enable_IPs => enable_IPs,
ack_IPs => ack_IPs,
interrupt_IPs => interrupt_IPs);
--HERE IPs--
ip_0: IP_DUMMY
port map( clk => clock,
rst => reset,
data_in => data_in_IPs(0),
data_out => data_out_IPs(0),
address => add_IPs(0),
W_enable => W_enable_IPs(0),
R_enable => R_enable_IPs(0),
generic_en => generic_en_IPs(0),
enable => enable_IPs(0),
ack => ack_IPs(0),
interrupt => interrupt_IPs(0));
ip_1: entity work.IP_ADDER
port map( clk => clock,
rst => reset,
data_in => data_in_IPs(1),
data_out => data_out_IPs(1),
address => add_IPs(1),
W_enable => W_enable_IPs(1),
R_enable => R_enable_IPs(1),
generic_en => generic_en_IPs(1),
enable => enable_IPs(1),
ack => ack_IPs(1),
interrupt => interrupt_IPs(1));
ip_2: entity work.IP_DUMMY
port map( clk => clock,
rst => reset,
data_in => data_in_IPs(2),
data_out => data_out_IPs(2),
address => add_IPs(2),
W_enable => W_enable_IPs(2),
R_enable => R_enable_IPs(2),
generic_en => generic_en_IPs(2),
enable => enable_IPs(2),
ack => ack_IPs(2),
interrupt => interrupt_IPs(2));
ip_3: entity work.IP_DUMMY
port map( clk => clock,
rst => reset,
data_in => data_in_IPs(3),
data_out => data_out_IPs(3),
address => add_IPs(3),
W_enable => W_enable_IPs(3),
R_enable => R_enable_IPs(3),
generic_en => generic_en_IPs(3),
enable => enable_IPs(3),
ack => ack_IPs(3),
interrupt => interrupt_IPs(3));
end architecture; | lgpl-3.0 | 9118f0e5556fd0eefebff8d20797bf5d | 0.528964 | 2.618898 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_encryption_monte_carlo_testbench_256bits.vhd | 1 | 11,627 | -- Twofish_ecb_encryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench256 is
end ecb_encryption_monte_carlo_testbench256;
architecture ecb_encryption256_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round256
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_encryption_circuit: twofish_encryption_round256
port map (
in1_ter256 => to_round(127 downto 96),
in2_ter256 => to_round(95 downto 64),
in3_ter256 => to_round(63 downto 32),
in4_ter256 => to_round(31 downto 0),
in_Sfirst_ter256 => Sfirst,
in_Ssecond_ter256 => Ssecond,
in_Sthird_ter256 => Sthird,
in_Sfourth_ter256 => Sfourth,
in_key_up_ter256 => key_up,
in_key_down_ter256 => key_down,
out1_ter256 => to_encr_reg128(127 downto 96),
out2_ter256 => to_encr_reg128(95 downto 64),
out3_ter256 => to_encr_reg128(63 downto 32),
out4_ter256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption256_monte_carlo_testbench_arch;
| gpl-2.0 | c4907d1cfaccc515fe739f0b109f9a08 | 0.652963 | 2.731266 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/div_unit_gti.vhd | 1 | 32,395 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| apache-2.0 | 8c1efe25e5854c8588a2c4242dda2aed | 0.945455 | 1.824454 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/test_divider.vhd | 1 | 1,122 | use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_divider is
end;
architecture test_divider of test_divider is
component c_divider
generic(width : INTEGER ; const :INTEGER
);
port(Input: in std_logic_vector((width - 1) downto 0);
Output : out std_logic_vector((width - 1) downto 0));
end component;
for all : c_divider use entity WORK.c_divider(behavior);
signal Input: std_logic_vector(3 downto 0);
signal Output : std_logic_vector(3 downto 0);
file S_IN : TEXT is out "c_divider_beh.out";
begin
divider_1 : c_divider
generic map(4,2)
port map(Input, Output);
test_process : process
begin
Input <= "1010";
wait for 50 ns;
Input <= "0101";
wait for 50 ns;
Input <= "0110";
wait for 50 ns;
Input <= "0000";
wait for 50 ns;
Input <= "0000";
wait for 50 ns;
Input <= "0101";
wait for 50 ns;
Input <= "1111";
wait for 50 ns;
Input <= "1001";
wait for 50 ns;
Input <= "1110";
wait for 50 ns;
wait;
end process test_process;
end test_divider;
| mit | feb608946bdbeff0f86de3973253810b | 0.601604 | 3.252174 | false | true | false | false |
freecores/twofish | vhdl/twofish_ecb_decryption_monte_carlo_testbench_256bits.vhd | 1 | 11,646 | -- Twofish_ecb_decryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_decryption_monte_carlo_testbench256 is
end ecb_decryption_monte_carlo_testbench256;
architecture ecb_decryption256_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round256
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_decryption_circuit: twofish_decryption_round256
port map (
in1_tdr256 => to_round(127 downto 96),
in2_tdr256 => to_round(95 downto 64),
in3_tdr256 => to_round(63 downto 32),
in4_tdr256 => to_round(31 downto 0),
in_Sfirst_tdr256 => Sfirst,
in_Ssecond_tdr256 => Ssecond,
in_Sthird_tdr256 => Sthird,
in_Sfourth_tdr256 => Sfourth,
in_key_up_tdr256 => key_up,
in_key_down_tdr256 => key_down,
out1_tdr256 => to_encr_reg128(127 downto 96),
out2_tdr256 => to_encr_reg128(95 downto 64),
out3_tdr256 => to_encr_reg128(63 downto 32),
out4_tdr256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_decryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_decryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_decryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Decryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process ecb_dmc_proc;
end ecb_decryption256_monte_carlo_testbench_arch;
| gpl-2.0 | e1303155e9b3dc23f54933e5d1d9f4fa | 0.6531 | 2.73252 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/metaheurísticas/mpegmv_ibea.vhd | 1 | 2,766 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_ibea_entity;
ARCHITECTURE mpegmv_ibea_description OF mpegmv_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register1 + 5;
register4 := input4 * 6;
register2 := register2 + 8;
WHEN "00000011" =>
register1 := register4 + register1;
register4 := input5 * 9;
WHEN "00000100" =>
register1 := register4 + register1;
register4 := input6 * 10;
register5 := input7 * 11;
register2 := register3 + register2;
WHEN "00000101" =>
register3 := input8 * 12;
register5 := register5 + 14;
register6 := input9 * 15;
register1 := ((NOT register1) + 1) XOR register1;
register2 := register4 + register2;
WHEN "00000110" =>
register3 := register3 + 19;
register4 := input10 * 20;
register7 := input11 * 21;
WHEN "00000111" =>
register4 := register4 + register5;
register5 := input12 * 22;
output1 <= register7 + register3;
WHEN "00001000" =>
register3 := register5 + 25;
register4 := register6 + register4;
register5 := input13 * 26;
register2 := ((NOT register2) + 1) XOR register2;
register6 := input14 * 29;
WHEN "00001001" =>
register3 := register6 + register3;
output2 <= register1(0 TO 1) & register4(0 TO 2);
WHEN "00001010" =>
register1 := register5 + register3;
WHEN "00001011" =>
output3 <= register2(0 TO 1) & register1(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_ibea_description; | gpl-3.0 | 6ee73b1049e8831f42712d9a0b327634 | 0.655098 | 3.066519 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/metaheurísticas/mesahb_spea2.vhd | 1 | 1,948 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:13)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_spea2_entity;
ARCHITECTURE mesahb_spea2_description OF mesahb_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
output1 <= input2 + 2;
WHEN "00000010" =>
register1 := register1 + 4;
register2 := input3 * 5;
WHEN "00000011" =>
register1 := register1 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register2 := ((NOT register2) + 1) XOR register2;
register3 := input4 * 14;
WHEN "00000101" =>
register2 := register3 * register2;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00000110" =>
register1 := register1 * 18;
WHEN "00000111" =>
register3 := input5 * 19;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := register3 + 21;
WHEN "00001001" =>
register2 := register2 * 23;
WHEN "00001010" =>
register2 := register2 + 25;
WHEN "00001011" =>
output2 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_spea2_description; | gpl-3.0 | 2ad7539ae3c85542b2fd9adc9dcbd53b | 0.652977 | 3.010819 | false | false | false | false |
marceloboeira/vhdl-examples | 006-ULA/test/ula_tb.vhd | 1 | 2,237 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ULA_tb is
end ULA_tb;
architecture behavior of ULA_tb is
component ULA
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
S : in std_logic_vector(1 downto 0);
O : out std_logic_vector(7 downto 0));
end component;
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal S : std_logic_vector(1 downto 0) := (others => '0');
signal O : std_logic_vector(7 downto 0);
begin
uut: ULA port map(A, B, S, O);
adding : process
begin
S <= "00";
-- 0 && 0 = 0
A <= conv_std_logic_vector(0, 8);
B <= conv_std_logic_vector(0, 8);
wait for 10 ns;
-- 0 && 1 = 0
A <= conv_std_logic_vector(0, 8);
B <= conv_std_logic_vector(1, 8);
wait for 10 ns;
-- 0 && 1 = 0
A <= conv_std_logic_vector(0, 8);
B <= conv_std_logic_vector(1, 8);
wait for 10 ns;
-- 1 && 1 = 1
A <= conv_std_logic_vector(1, 8);
B <= conv_std_logic_vector(1, 8);
wait for 10 ns;
S <= "01";
-- 0 || 0 = 0
A <= conv_std_logic_vector(0, 8);
B <= conv_std_logic_vector(0, 8);
wait for 10 ns;
-- 1 || 0 = 1
A <= conv_std_logic_vector(1, 8);
B <= conv_std_logic_vector(0, 8);
wait for 10 ns;
-- 0 || 1 = 1
A <= conv_std_logic_vector(0, 8);
B <= conv_std_logic_vector(1, 8);
wait for 10 ns;
-- 1 || 1 = 1
A <= conv_std_logic_vector(1, 8);
B <= conv_std_logic_vector(1, 8);
wait for 10 ns;
S <= "10";
-- 10 + 20 = 30
A <= conv_std_logic_vector(10, 8);
B <= conv_std_logic_vector(20, 8);
wait for 10 ns;
-- 32 + 13 = 45
A <= conv_std_logic_vector(32, 8);
B <= conv_std_logic_vector(13, 8);
wait for 10 ns;
S <= "11";
-- 30 - 20 = 10
A <= conv_std_logic_vector(30, 8);
B <= conv_std_logic_vector(20, 8);
wait for 10 ns;
-- 33 - 11 = 22
A <= conv_std_logic_vector(33, 8);
B <= conv_std_logic_vector(11, 8);
wait for 10 ns;
wait;
end process;
end;
| mit | 97a3cc2363bdefd5891b79146884bdac | 0.518105 | 2.875321 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/coregen_comp_defs.vhd | 1 | 52,734 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and FIFO Generator when XST elaborated the client core
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-- |
-- |--- XilinxCoreLib.fifo_generator_v9_2
-- |--- XilinxCoreLib.fifo_generator_v9_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v7_1
-- |--- XilinxCoreLib.blk_mem_gen_v7_3
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/01/2008 Initial Version
--
-- DET 2/01/2008 for proc_common_v4_0
-- ~~~~~~
-- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create
-- this file.
-- - Changed instance of sync fifo to use new wrapper file that will adapt
-- to FIFO Generator primitive.
-- - Replaced "edk_generatecore" with "generatecore" utility call
-- - Removed the CAM component
-- ^^^^^^
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 4.3
-- - Added Block Memory Generator Component Version 2.7
-- ^^^^^^
--
-- MSH 2/26/2009 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 5.1
-- - Added Block Memory Generator Component Version 3.1
-- ^^^^^^
--
-- DET 3/2/2009 for EDK 11.1
-- ~~~~~~
-- - Added new Parameters and ports for Fifo Generatore 5.1.
-- ^^^^^^
--
-- DET 3/30/2009 EDK 11.2
-- ~~~~~~
-- - Had to reorder parameter list of FIFO Generator 4.3 component to match
-- the corresponding Verilog model due to NCSIM positional order
-- dependancy of parameters in vhdl/verilog use case.
-- ^^^^^^
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Added fifo_generator_v5_2
-- ^^^^^^
--
-- DET 2/9/2010 For EDK 12.1
-- ~~~~~~
-- - Added fifo_generator_v5_3
-- - Added blk_mem_gen_v3_3
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Added fifo_generator_v6_1
-- - Added blk_mem_gen_v4_1
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 10/04/2010 EDK 13.1
-- ~~~~~~
-- - Added fifo_generator_v7_3
-- - Added blk_mem_gen_v5_2
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Replaced fifo_generator v7.3 with v8.1
-- - Added blk_mem_gen_v6_1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Removed blk_mem_gen v6_1
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- - Update to use blk_mem_gen_v6_2
-- - Remove out of date components.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the component decalarion
-- ^^^^^^
--
-- DET 3/7/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR596052
-- - Added removed fifo generator and Blk Mem Gen components back into
-- coregen_comp_defs.
-- ^^^^^^
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
PACKAGE coregen_comp_defs IS
--------------------------------------------------------
-- Declare general attributes used in this file
-- for defining each component being used with
-- the generatecore utility
attribute box_type: string;
attribute GENERATOR_DEFAULT: string;
-------------------------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v12_0
-- The Component declaration for fifo_generator_v12_0 pulled from the
-- Coregen version of
-- file: fifo_generator_v12_0_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V10.0 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v12_0
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex6";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3
C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
backup : in std_logic := '0';
backup_marker : in std_logic := '0';
clk : in std_logic := '0';
rst : in std_logic := '0';
srst : in std_logic := '0';
wr_clk : in std_logic := '0';
wr_rst : in std_logic := '0';
rd_clk : in std_logic := '0';
rd_rst : in std_logic := '0';
din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
rd_en : in std_logic := '0';
-- optional inputs
prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
int_clk : in std_logic := '0';
injectdbiterr : in std_logic := '0';
injectsbiterr : in std_logic := '0';
sleep : in std_logic := '0';
dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0');
full : out std_logic := '0';
almost_full : out std_logic := '0';
wr_ack : out std_logic := '0';
overflow : out std_logic := '0';
empty : out std_logic := '1';
almost_empty : out std_logic := '1';
valid : out std_logic := '0';
underflow : out std_logic := '0';
data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
prog_full : out std_logic := '0';
prog_empty : out std_logic := '1';
sbiterr : out std_logic := '0';
dbiterr : out std_logic := '0';
wr_rst_busy : out std_logic := '0';
rd_rst_busy : out std_logic := '0';
-- axi global signal
m_aclk : in std_logic := '0';
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1
m_aclk_en : in std_logic := '0';
s_aclk_en : in std_logic := '0';
-- axi full/lite slave write channel (write side)
s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic := '0';
s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic := '0';
s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_bvalid : out std_logic := '0';
s_axi_bready : in std_logic := '0';
-- axi full/lite master write channel (read side)
m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_awvalid : out std_logic := '0';
m_axi_awready : in std_logic := '0';
m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
m_axi_wlast : out std_logic := '0';
m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_wvalid : out std_logic := '0';
m_axi_wready : in std_logic := '0';
m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_bvalid : in std_logic := '0';
m_axi_bready : out std_logic := '0';
-- axi full/lite slave read channel (write side)
s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic := '0';
s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_rlast : out std_logic := '0';
s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_rvalid : out std_logic := '0';
s_axi_rready : in std_logic := '0';
-- axi full/lite master read channel (read side)
m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_arvalid : out std_logic := '0';
m_axi_arready : in std_logic := '0';
m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_rlast : in std_logic := '0';
m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_rvalid : in std_logic := '0';
m_axi_rready : out std_logic := '0';
-- axi streaming slave signals (write side)
s_axis_tvalid : in std_logic := '0';
s_axis_tready : out std_logic := '0';
s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
s_axis_tlast : in std_logic := '0';
s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi streaming master signals (read side)
m_axis_tvalid : out std_logic := '0';
m_axis_tready : in std_logic := '0';
m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
m_axis_tlast : out std_logic := '0';
m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi full/lite write address channel signals
axi_aw_injectsbiterr : in std_logic := '0';
axi_aw_injectdbiterr : in std_logic := '0';
axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_sbiterr : out std_logic := '0';
axi_aw_dbiterr : out std_logic := '0';
axi_aw_overflow : out std_logic := '0';
axi_aw_underflow : out std_logic := '0';
axi_aw_prog_full : out std_logic := '0';
axi_aw_prog_empty : out std_logic := '1';
-- axi_aw_almost_full : out std_logic := '0';
-- axi_aw_almost_empty : out std_logic := '1';
-- axi full/lite write data channel signals
axi_w_injectsbiterr : in std_logic := '0';
axi_w_injectdbiterr : in std_logic := '0';
axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_sbiterr : out std_logic := '0';
axi_w_dbiterr : out std_logic := '0';
axi_w_overflow : out std_logic := '0';
axi_w_underflow : out std_logic := '0';
axi_w_prog_full : out std_logic := '0';
axi_w_prog_empty : out std_logic := '1';
-- axi_w_almost_full : out std_logic := '0';
-- axi_w_almost_empty : out std_logic := '1';
-- axi full/lite write response channel signals
axi_b_injectsbiterr : in std_logic := '0';
axi_b_injectdbiterr : in std_logic := '0';
axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_sbiterr : out std_logic := '0';
axi_b_dbiterr : out std_logic := '0';
axi_b_overflow : out std_logic := '0';
axi_b_underflow : out std_logic := '0';
axi_b_prog_full : out std_logic := '0';
axi_b_prog_empty : out std_logic := '1';
-- axi_b_almost_full : out std_logic := '0';
-- axi_b_almost_empty : out std_logic := '1';
-- axi full/lite read address channel signals
axi_ar_injectsbiterr : in std_logic := '0';
axi_ar_injectdbiterr : in std_logic := '0';
axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_sbiterr : out std_logic := '0';
axi_ar_dbiterr : out std_logic := '0';
axi_ar_overflow : out std_logic := '0';
axi_ar_underflow : out std_logic := '0';
axi_ar_prog_full : out std_logic := '0';
axi_ar_prog_empty : out std_logic := '1';
-- axi_ar_almost_full : out std_logic := '0';
-- axi_ar_almost_empty : out std_logic := '1';
-- axi full/lite read data channel signals
axi_r_injectsbiterr : in std_logic := '0';
axi_r_injectdbiterr : in std_logic := '0';
axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_sbiterr : out std_logic := '0';
axi_r_dbiterr : out std_logic := '0';
axi_r_overflow : out std_logic := '0';
axi_r_underflow : out std_logic := '0';
axi_r_prog_full : out std_logic := '0';
axi_r_prog_empty : out std_logic := '1';
-- axi_r_almost_full : out std_logic := '0';
-- axi_r_almost_empty : out std_logic := '1';
-- axi streaming fifo related signals
axis_injectsbiterr : in std_logic := '0';
axis_injectdbiterr : in std_logic := '0';
axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_sbiterr : out std_logic := '0';
axis_dbiterr : out std_logic := '0';
axis_overflow : out std_logic := '0';
axis_underflow : out std_logic := '0';
axis_prog_full : out std_logic := '0';
axis_prog_empty : out std_logic := '1'
-- axis_almost_full : out std_logic := '0';
-- axis_almost_empty : out std_logic := '1'
);
END COMPONENT;
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_2
-- Component declaration for blk_mem_gen_v8_2 pulled from the
-- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib
-- file: blk_mem_gen_v8_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC"; -- Removed in version v8_2
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC := '0';
DBITERR : OUT STD_LOGIC := '0';
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC := '0';
SLEEP : IN STD_LOGIC := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC := '0';
S_AXI_DBITERR : OUT STD_LOGIC := '0';
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT; --blk_mem_gen_v8_1
-- The following tells XST that blk_mem_gen_v8_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
-- ATTRIBUTE box_type OF blk_mem_gen_v8_1 : COMPONENT IS "black_box";
-- ATTRIBUTE generator_default OF blk_mem_gen_v8_1 : COMPONENT IS
-- "generatecore com.xilinx.ip.blk_mem_gen_v8_1.blk_mem_gen_v8_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
END coregen_comp_defs;
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`protect end_protected
| apache-2.0 | 3de5e45feee6a7321a04bec70d175379 | 0.952485 | 1.817355 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/metaheurísticas/mesahb_wsga.vhd | 1 | 2,046 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_wsga_entity;
ARCHITECTURE mesahb_wsga_description OF mesahb_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register2 := register2 + 4;
output1 <= input3 + 5;
register1 := register1 + 7;
WHEN "00000011" =>
register2 := register2 * 9;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00000100" =>
register2 := register2 + 13;
register3 := input4 * 14;
WHEN "00000101" =>
register2 := ((NOT register2) + 1) XOR register2;
register3 := register3 + 18;
register4 := input5 * 19;
WHEN "00000110" =>
register3 := register3 * 21;
register1 := register4 * register1;
register2 := register2 * 23;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register3 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_wsga_description; | gpl-3.0 | 291e40cd0c67f253a797a469ee5644c3 | 0.675953 | 3.206897 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/lfsr.vhd | 1 | 1,030 | -- This is a 16 bit Linear Feedback Shift Register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity LFSR16 is
port(
CLK : in std_logic;
RESET : in std_logic;
LD : in std_logic;
EN : in std_logic;
DIN : in std_logic_vector (0 to 15);
PRN : out std_logic_vector (0 to 15);
ZERO_D : out std_logic);
end LFSR16;
architecture RTL of LFSR16 is
signal t_prn : std_logic_vector(0 to 15);
begin
-- Continuous assignments :
PRN <= t_prn;
ZERO_D <= '1' when (t_prn = "0000000000000000") else '0';
-- LFSR process :
process(CLK,RESET)
begin
if RESET='1' then
t_prn <= "0000000000000001"; -- load 1 at reset
elsif rising_edge (CLK) then
if (LD = '1') then -- load a new seed when ld is active
t_prn <= DIN;
elsif (EN = '1') then -- shift when enabled
t_prn(0) <= t_prn(15) xor t_prn(4) xor t_prn(2) xor t_prn(1);
t_prn(1 to 15) <= t_prn(0 to 14);
end if;
end if;
end process;
end RTL;
| lgpl-3.0 | a29b8506a173b83bdd1b4335e0171eb6 | 0.58932 | 3.093093 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/shared_ram_ivar.vhd | 1 | 8,750 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
| apache-2.0 | 5f00f5952d772caa4a838fa02eda9322 | 0.481029 | 4.758021 | false | false | false | false |
sils1297/HWPrak14 | i2c_master_byte_ctrl.vhd | 1 | 12,702 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
--
-- $Date: 2004-02-18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
--report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural; | agpl-3.0 | ca9a13b47d079d2c9d6707fece41b985 | 0.45914 | 3.861964 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_logic_pkt_fifo.vhd | 5 | 44,022 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | 68e4d544f3e32fa715f6a51e70dc8cf0 | 0.948594 | 1.829372 | false | false | false | false |
BBN-Q/APS2-Comms | src/tcp_axi_dma.vhd | 1 | 11,632 | -- Bridge from TCP receive and send streams to an AXI memory map
-- Also can route packets to/from CPLD interface
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity TCP_AXI_DMA is
port (
clk : in std_logic;
rst : in std_logic;
---TCP receive
rx_tdata : in std_logic_vector(31 downto 0);
rx_tvalid : in std_logic;
rx_tready : out std_logic;
rx_tlast : in std_logic;
--TCP send channels
tx_write_resp_tdata : out std_logic_vector(31 downto 0);
tx_write_resp_tvalid : out std_logic;
tx_write_resp_tlast : out std_logic;
tx_write_resp_tready : in std_logic;
tx_read_resp_tdata : out std_logic_vector(31 downto 0);
tx_read_resp_tvalid : out std_logic;
tx_read_resp_tlast : out std_logic;
tx_read_resp_tready : in std_logic;
--DataMover interfaces
MM2S_CMD_tdata : out std_logic_vector( 71 downto 0 );
MM2S_CMD_tready : in std_logic;
MM2S_CMD_tvalid : out std_logic;
MM2S_tdata : in std_logic_vector( 31 downto 0 );
MM2S_tkeep : in std_logic_vector( 3 downto 0 );
MM2S_tlast : in std_logic;
MM2S_tready : out std_logic;
MM2S_tvalid : in std_logic;
MM2S_STS_tdata : in std_logic_vector( 7 downto 0 );
MM2S_STS_tkeep : in std_logic_vector( 0 to 0 );
MM2S_STS_tlast : in std_logic;
MM2S_STS_tready : out std_logic;
MM2S_STS_tvalid : in std_logic;
S2MM_CMD_tdata : out std_logic_vector( 71 downto 0 );
S2MM_CMD_tready : in std_logic;
S2MM_CMD_tvalid : out std_logic;
S2MM_tdata : out std_logic_vector( 31 downto 0 );
S2MM_tkeep : out std_logic_vector( 3 downto 0 );
S2MM_tlast : out std_logic;
S2MM_tready : in std_logic;
S2MM_tvalid : out std_logic;
S2MM_STS_tdata : in std_logic_vector( 7 downto 0 );
S2MM_STS_tkeep : in std_logic_vector( 0 to 0 );
S2MM_STS_tlast : in std_logic;
S2MM_STS_tready : out std_logic;
S2MM_STS_tvalid : in std_logic
);
end entity;
architecture arch of TCP_AXI_DMA is
--Annoying internal signals for Vivado's crummy VHDL support
signal rx_tready_int : std_logic;
signal tx_write_resp_tvalid_int : std_logic;
signal tx_read_resp_tvalid_int : std_logic;
type DataMoverCmd_t is record
rsvd : std_logic_vector(3 downto 0) ;
tag : std_logic_vector(3 downto 0) ;
addr : std_logic_vector(31 downto 0) ;
drr : std_logic;
eof : std_logic;
dsa : std_logic_vector(5 downto 0) ;
axiType : std_logic;
btt : std_logic_vector(22 downto 0) ;
end record;
signal mover_cmd : DataMoverCmd_t := (rsvd => (others => '0'), tag => (others => '0'), addr => (others => '0'), drr => '0', eof => '1', dsa => (others => '0'), axiType => '1', btt => (others => '0'));
function movercmd2slv(cmd : DataMoverCmd_t) return std_logic_vector is
variable slvOut : std_logic_vector(71 downto 0) ;
begin
slvOut := cmd.rsvd & cmd.tag & cmd.addr & cmd.drr & cmd.eof & cmd.dsa & cmd.axiType & cmd.btt;
return slvOut;
end movercmd2slv;
type main_state_t is (IDLE, LATCH_CONTROL, LATCH_ADDR, ISSUE_DMA_READ_CMD, ISSUE_DMA_WRITE_CMD, WAIT_FOR_LAST);
signal main_state : main_state_t;
type mm2s_data_state_t is (IDLE, WRITE_CMD, WRITE_ADDR, WAIT_FOR_LAST);
signal mm2s_data_state : mm2s_data_state_t;
type s2mm_status_state_t is (IDLE, CHECK_ACK_NEEDED, WRITE_CMD, WRITE_ADDR, DRIVE_READY);
signal s2mm_status_state : s2mm_status_state_t;
signal write_cmd_in_tdata : std_logic_vector(63 downto 0) := (others => '0');
signal write_cmd_in_tvalid, write_cmd_in_tready, write_cmd_in_tlast : std_logic := '0';
signal write_cmd_out_tdata : std_logic_vector(63 downto 0) := (others => '0');
signal write_cmd_out_tvalid, write_cmd_out_tready, write_cmd_out_tlast : std_logic := '0';
signal write_cmd_fifo_count : std_logic_vector(4 downto 0);
signal read_cmd_in_tdata : std_logic_vector(63 downto 0) := (others => '0');
signal read_cmd_in_tvalid, read_cmd_in_tready, read_cmd_in_tlast : std_logic := '0';
signal read_cmd_out_tdata : std_logic_vector(63 downto 0) := (others => '0');
signal read_cmd_out_tvalid, read_cmd_out_tready, read_cmd_out_tlast : std_logic := '0';
signal read_cmd_fifo_count : std_logic_vector(4 downto 0);
begin
--Irritatingly Vivado simulator doesn't support VHDL-2008 so need extra signal to read out port
rx_tready <= rx_tready_int;
tx_write_resp_tvalid <= tx_write_resp_tvalid_int;
tx_read_resp_tvalid <= tx_read_resp_tvalid_int;
main : process(clk)
variable cmd : std_logic_vector(31 downto 0);
variable addr : std_logic_vector(31 downto 0);
alias cmd_rw : std_logic is cmd(28);
variable accepted_tcp_data : boolean;
begin
if rising_edge(clk) then
if rst = '1' then
main_state <= IDLE;
else
accepted_tcp_data := rx_tvalid = '1' and rx_tready_int = '1';
write_cmd_in_tdata <= cmd & addr;
write_cmd_in_tvalid <= '0';
write_cmd_in_tlast <= '0';
read_cmd_in_tdata <= cmd & addr;
read_cmd_in_tvalid <= '0';
read_cmd_in_tlast <= '0';
case( main_state ) is
when IDLE =>
--Use tx_valid to indicate start of packet
if rx_tvalid = '1' then
main_state <= LATCH_CONTROL;
end if;
when LATCH_CONTROL =>
cmd := rx_tdata;
mover_cmd.btt <= b"00000" & cmd(15 downto 0) & b"00";
mover_cmd.tag <= cmd(27 downto 24);
if accepted_tcp_data then
main_state <= LATCH_ADDR;
end if;
when LATCH_ADDR =>
addr := rx_tdata;
mover_cmd.addr <= addr;
if accepted_tcp_data then
if cmd_rw = '1' then
main_state <= ISSUE_DMA_READ_CMD;
else
main_state <= ISSUE_DMA_WRITE_CMD;
end if;
end if;
when ISSUE_DMA_WRITE_CMD =>
if S2MM_tready = '1' then
--Should probably also check cmd FIFO isn't full
write_cmd_in_tvalid <= '1';
write_cmd_in_tlast <= '1';
main_state <= WAIT_FOR_LAST;
end if;
when ISSUE_DMA_READ_CMD =>
if MM2S_CMD_tready = '1' then
--Should probably also check cmd FIFO isn't full
read_cmd_in_tvalid <= '1';
read_cmd_in_tlast <= '1';
main_state <= IDLE;
end if;
when WAIT_FOR_LAST =>
if accepted_tcp_data and rx_tlast = '1' then
main_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
--Combinational signals
S2MM_tkeep <= "1111"; --Assume 4 byte boundaries for now
S2MM_tdata <= rx_tdata;
S2MM_tvalid <= rx_tvalid when (main_state = WAIT_FOR_LAST) else '0';
S2MM_tlast <= rx_tlast;
--hold ready high for latching control and address otherwise let stream handle
with main_state select rx_tready_int <=
S2MM_tready when WAIT_FOR_LAST,
'1' when LATCH_CONTROL | LATCH_ADDR,
'0' when others;
--We only have one source of mover commands so wire both S2MM and MM2S to the same command
S2MM_CMD_tdata <= movercmd2slv(mover_cmd);
MM2S_CMD_tdata <= movercmd2slv(mover_cmd);
--just use the valid to choose between S2MM and MM2S
S2MM_CMD_tvalid <= '1' when (main_state = ISSUE_DMA_WRITE_CMD) else '0';
MM2S_CMD_tvalid <= '1' when (main_state = ISSUE_DMA_READ_CMD) else '0';
-- FIFOs to store read/write commands waiting for status or read responses
write_cmd_fifo: axis_srl_fifo
generic map (
DATA_WIDTH => 64,
DEPTH => 16
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => write_cmd_in_tdata,
input_axis_tvalid => write_cmd_in_tvalid,
input_axis_tready => write_cmd_in_tready,
input_axis_tlast => write_cmd_in_tlast,
input_axis_tuser => '0',
output_axis_tdata => write_cmd_out_tdata,
output_axis_tvalid => write_cmd_out_tvalid,
output_axis_tready => write_cmd_out_tready,
output_axis_tlast => write_cmd_out_tlast,
output_axis_tuser => open,
count => write_cmd_fifo_count
);
read_cmd_fifo: axis_srl_fifo
generic map (
DATA_WIDTH => 64,
DEPTH => 16
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => read_cmd_in_tdata,
input_axis_tvalid => read_cmd_in_tvalid,
input_axis_tready => read_cmd_in_tready,
input_axis_tlast => read_cmd_in_tlast,
input_axis_tuser => '0',
output_axis_tdata => read_cmd_out_tdata,
output_axis_tvalid => read_cmd_out_tvalid,
output_axis_tready => read_cmd_out_tready,
output_axis_tlast => read_cmd_out_tlast,
output_axis_tuser => open,
count => read_cmd_fifo_count
);
--read data receiver
mm2s_data_receiver : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mm2s_data_state <= IDLE;
read_cmd_out_tready <= '0';
else
read_cmd_out_tready <= '0';
case( mm2s_data_state ) is
when IDLE =>
--wait for cmd fifo valid to signal command has been issued
if read_cmd_out_tvalid = '1' then
mm2s_data_state <= WRITE_CMD;
end if;
when WRITE_CMD =>
if tx_read_resp_tready = '1' then
mm2s_data_state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if tx_read_resp_tready = '1' then
mm2s_data_state <= WAIT_FOR_LAST;
read_cmd_out_tready <= '1';
end if;
when WAIT_FOR_LAST =>
--wait for tlast from MM2S
--TODO also check status is not error and if error zero pad response and then send error packet
if MM2S_tlast = '1' and tx_read_resp_tready = '1' then
mm2s_data_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
--combinationally mux in MM2S stream
MM2S_tready <= tx_read_resp_tready when mm2s_data_state = WAIT_FOR_LAST else '0';
with mm2s_data_state select tx_read_resp_tdata <=
read_cmd_out_tdata(63 downto 32) when WRITE_CMD,
read_cmd_out_tdata(31 downto 0) when WRITE_ADDR,
MM2S_tdata when others;
with mm2s_data_state select tx_read_resp_tvalid_int <=
MM2S_tvalid when WAIT_FOR_LAST,
'1' when WRITE_CMD | WRITE_ADDR,
'0' when others;
with mm2s_data_state select tx_read_resp_tlast <=
MM2S_tlast when WAIT_FOR_LAST,
'0' when others;
--TODO: read in process and send error codes
MM2S_STS_tready <= '1';
s2mm_status_receiver : process(clk)
variable status : std_logic_vector(7 downto 0);
alias status_ok : std_logic is status(7);
variable cmd : std_logic_vector(31 downto 0);
alias ack_req : std_logic is cmd(31);
begin
if rising_edge(clk) then
if rst = '1' then
s2mm_status_state <= IDLE;
else
cmd := write_cmd_out_tdata(63 downto 32);
case( s2mm_status_state ) is
when IDLE =>
status := S2MM_STS_tdata;
if S2MM_STS_tvalid = '1' and write_cmd_out_tvalid = '1' then
s2mm_status_state <= CHECK_ACK_NEEDED;
end if;
when CHECK_ACK_NEEDED =>
--check whether there was an error or if we want an acknowledge
if status_ok = '0' or ack_req = '1' then
s2mm_status_state <= WRITE_CMD;
else
s2mm_status_state <= DRIVE_READY;
end if;
when WRITE_CMD =>
if tx_write_resp_tready = '1' then
s2mm_status_state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if tx_write_resp_tready = '1' then
s2mm_status_state <= DRIVE_READY;
end if;
when DRIVE_READY =>
s2mm_status_state <= IDLE;
end case;
end if;
end if;
end process;
--combinational AXIS signals
with s2mm_status_state select tx_write_resp_tvalid_int <=
'1' when WRITE_CMD | WRITE_ADDR,
'0' when others;
tx_write_resp_tlast <= '1' when s2mm_status_state = WRITE_ADDR else '0';
--content of an ACK:
-- (ACK SEQ SEL R/W CMD<3:0>) (DATAMOVER STATUS<7:0>) CNT<15:0>
-- ADDRESS<31:0>
with s2mm_status_state select tx_write_resp_tdata <=
write_cmd_out_tdata(63 downto 56) & S2MM_STS_tdata & write_cmd_out_tdata(47 downto 32) when WRITE_CMD,
write_cmd_out_tdata(31 downto 0) when WRITE_ADDR,
(others => '0') when others;
S2MM_STS_tready <= '1' when s2mm_status_state = DRIVE_READY else '0';
write_cmd_out_tready <= '1' when s2mm_status_state = DRIVE_READY else '0';
end architecture;
| mpl-2.0 | a07b5d9005adb721fac370b0d071d178 | 0.65913 | 2.748582 | false | false | false | false |
rcls/sdr | vhdl/quadfir.vhd | 1 | 4,231 | -- Configurable FIR operating on 4 round robin multiplexed channels.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity quadfir is
generic(acc_width : integer;
out_width : integer;
differentiate : boolean;
index_sample_strobe : integer;
index_out_strobe : integer;
index_pc_reset : integer;
index_read_reset : integer;
index_mac_accum : integer;
program_size : integer;
program : program_t);
port(d : in signed18;
d_last : in std_logic;
q : out signed(out_width - 1 downto 0);
q_strobe : out std_logic; -- Asserted on the first cycle with new data.
q_last : out std_logic; -- Asserted when output is last channel (3).
clk : in std_logic);
end quadfir;
architecture behavioural of quadfir is
-- Layout of the command word:
-- 18 bits multiplier.
-- 1 bit in sample strobe.
-- 1 bit out strobe.
-- 1 bit pc reset.
-- 1 bit read reset.
-- 1 bit mac accumulate/reset control.
subtype program_counter_t is integer range 0 to program_size - 1;
signal command : command_t := (others => '0');
--type buff_t is array(0 to 1023) of signed18;
type buff_t is array(0 to 2047) of signed18;
signal buff : buff_t := (others => "00" & x"0000");
signal pc : program_counter_t;
constant pointer_size : integer := 11;
subtype pointer_t is unsigned(pointer_size-1 downto 0);
signal write_pointer : pointer_t := (others => '0');
signal read_pointer : pointer_t := (others=> '0');
-- Unpacked command.
signal coef_1 : signed18;
signal sample_strobe : std_logic;
signal out_strobe : std_logic;
signal pc_reset : std_logic := '0';
signal read_reset : std_logic;
signal mac_accum : std_logic;
signal mac_accum_1 : std_logic;
signal mac_accum_2 : std_logic;
signal accumulator : signed(acc_width-1 downto 0);
signal data_1 : signed18;
signal data_2 : signed18;
signal data_3 : signed18;
signal coef_2 : signed18;
signal diff : signed18;
signal product : signed36;
begin
process
variable acc_addend : signed(acc_width - 1 downto 0);
variable rp_addend : pointer_t;
variable rp_increment : integer;
variable write_pointer_corrected : pointer_t;
variable diff_out : signed18;
begin
wait until rising_edge(clk);
command <= program(pc);
if pc_reset = '1' then
pc <= 0;
else
pc <= pc + 1;
end if;
-- Unpack the command.
coef_1 <= signed(command(17 downto 0));
sample_strobe <= command(index_sample_strobe);
out_strobe <= command(index_out_strobe);
pc_reset <= command(index_pc_reset);
read_reset <= command(index_read_reset);
mac_accum <= command(index_mac_accum);
-- Input processing...
if sample_strobe = '1' then
buff(to_integer(write_pointer)) <= d;
write_pointer_corrected := write_pointer;
if d_last = '1' then
write_pointer_corrected(1 downto 0) := "11";
end if;
write_pointer <= write_pointer_corrected + 1;
end if;
-- DSP input buffering.
data_1 <= buff(to_integer(read_pointer));
data_2 <= data_1;
data_3 <= data_2;
coef_2 <= coef_1;
mac_accum_1 <= mac_accum;
if differentiate then
diff <= data_2 - data_3;
diff_out := diff;
else
diff_out := data_2;
end if;
-- dsp
product <= diff_out * coef_2;
if mac_accum_1 = '0' then
acc_addend := (others => '0');
else
acc_addend := accumulator;
end if;
accumulator <= acc_addend + product;
if out_strobe = '1' then
q <= accumulator(acc_width - 1 downto acc_width - out_width);
-- Channel will have already advanced on output.
q_last <= b2s(read_pointer(1 downto 0) = "00");
end if;
q_strobe <= out_strobe;
-- buff pointer update.
if read_reset = '1' then
rp_addend := write_pointer(pointer_size-1 downto 2) &
(read_pointer(1 downto 0) + 1);
rp_increment := 64;
else
rp_addend := read_pointer;
rp_increment := 4;
end if;
read_pointer <= rp_addend + rp_increment;
end process;
end behavioural;
| gpl-3.0 | 16501bdd5d0fb9155491aaadf337039d | 0.61073 | 3.517041 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_wr_demux.vhd | 1 | 32,014 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
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-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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-- Xilinx products are not designed or intended to be fail-
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-- (individually and collectively, "Critical
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_wr_demux.vhd
--
-- Description:
-- This file implements the AXI Master Burst Write Strobe De-Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXi DataMover v2_00_a axi_datamover_wr_demux.vhd
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32
);
port (
-- AXI MMap Data Channel Input -------------------------------
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- data input
-- AXI Master Stream -----------------------------------
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0);
--De-Mux strb output
-- Command Calculator Interface --------------------------
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0)
-- The next command start address LSbs to use for the read data
-- mux (only used if Stream data width is less than the MMap Data
-- Width).
);
end entity axi_master_burst_wr_demux;
architecture implementation of axi_master_burst_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
-- coverage off
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
-- coverage on
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
-- coverage off
when 16 =>
var_sel_ls_index := 1;
-- coverage on
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
-- coverage off
when others =>
var_sel_ls_index := 0;
-- coverage on
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
end implementation;
| apache-2.0 | 754aac910778a4f9e3c9a3e0911f99f5 | 0.432654 | 4.873497 | false | false | false | false |
BBN-Q/APS2-Comms | test/tcp_demux_tb.vhd | 1 | 8,906 | -- Testbench for tcp_demux
--
-- * memory write/read
-- * to cpld with tready deasserting
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tcp_demux_tb is
end;
architecture bench of tcp_demux_tb is
signal clk : std_logic := '0';
signal clk_tcp : std_logic := '0';
signal rst : std_logic := '0';
signal rst_tcp : std_logic := '0';
signal tcp_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_tvalid : std_logic := '0';
signal tcp_rx_tready : std_logic := '0';
signal memory_rx_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal memory_rx_tvalid : std_logic := '0';
signal memory_rx_tready : std_logic := '1';
signal memory_rx_tlast : std_logic := '0';
signal cpld_rx_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal cpld_rx_tvalid : std_logic := '0';
signal cpld_rx_tready : std_logic := '0';
signal cpld_rx_tlast : std_logic := '0';
constant clock_period : time := 10 ns;
constant clock_tcp_period : time := 8 ns;
signal stop_the_clocks : boolean;
type TestBenchState_t is (RESET, TO_MEMORY_WRITE, TO_MEMORY_READ, TO_CPLD_SHORT, TO_CPLD_LONG);
signal testBench_state : TestBenchState_t;
signal checking_finished : boolean := false;
begin
uut : entity work.tcp_demux
port map (
clk => clk,
rst => rst,
clk_tcp => clk_tcp,
rst_tcp => rst_tcp,
tcp_rx_tdata => tcp_rx_tdata,
tcp_rx_tvalid => tcp_rx_tvalid,
tcp_rx_tready => tcp_rx_tready,
memory_rx_tdata => memory_rx_tdata,
memory_rx_tvalid => memory_rx_tvalid,
memory_rx_tready => memory_rx_tready,
memory_rx_tlast => memory_rx_tlast,
cpld_rx_tdata => cpld_rx_tdata,
cpld_rx_tvalid => cpld_rx_tvalid,
cpld_rx_tready => cpld_rx_tready,
cpld_rx_tlast => cpld_rx_tlast
);
clk <= not clk after clock_period / 2 when not stop_the_clocks;
clk_tcp <= not clk_tcp after clock_tcp_period / 2 when not stop_the_clocks;
--CPLD goes into axis adapter so can take data only every 1/4 clock cycles
cpld_rx_tready_drive: process
begin
while true loop
cpld_rx_tready <= '1';
wait until rising_edge(clk) and cpld_rx_tvalid = '1';
cpld_rx_tready <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
end loop;
end process;
stimulus: process
type byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
variable cmd : byte_array(0 to 3);
variable addr : byte_array(0 to 3);
variable cnt : natural;
begin
wait until rising_edge(clk_tcp);
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
wait until rising_edge(clk_tcp);
rst_tcp <= '0';
wait until rising_edge(clk);
rst <= '0';
wait for 100ns;
wait until rising_edge(clk_tcp);
testBench_state <= TO_MEMORY_WRITE;
tcp_rx_tvalid <= '1';
--command word
cmd := (x"00", x"00", x"00", x"04");
for ct in 0 to 3 loop
tcp_rx_tdata <= cmd(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--address
addr := (x"c0", x"00", x"00", x"00");
for ct in 0 to 3 loop
tcp_rx_tdata <= addr(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--data payload
for ct in 1 to 16 loop
tcp_rx_tdata <= std_logic_vector(to_unsigned(ct, 8));
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
tcp_rx_tvalid <= '0';
wait until rising_edge(clk) and memory_rx_tlast = '1';
testBench_state <= TO_MEMORY_READ;
tcp_rx_tvalid <= '1';
--command word
cmd := (x"10", x"00", x"00", x"ff");
for ct in 0 to 3 loop
tcp_rx_tdata <= cmd(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--address
addr := (x"c0", x"00", x"00", x"00");
for ct in 0 to 3 loop
tcp_rx_tdata <= addr(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
tcp_rx_tvalid <= '0';
wait until rising_edge(clk) and memory_rx_tlast = '1';
testBench_state <= TO_CPLD_SHORT;
tcp_rx_tvalid <= '1';
--command word
cmd := (x"20", x"00", x"00", x"00");
for ct in 0 to 3 loop
tcp_rx_tdata <= cmd(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--address
addr := (x"ba", x"ad", x"a5", x"55");
for ct in 0 to 3 loop
tcp_rx_tdata <= addr(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
tcp_rx_tvalid <= '0';
wait until rising_edge(clk_tcp) and cpld_rx_tlast = '1';
testBench_state <= TO_CPLD_LONG;
tcp_rx_tvalid <= '1';
--command word
cmd := (x"25", x"00", x"01", x"00");
for ct in 0 to 3 loop
tcp_rx_tdata <= cmd(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--address
addr := (x"ba", x"ad", x"a5", x"55");
for ct in 0 to 3 loop
tcp_rx_tdata <= addr(ct);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--data payload
cnt := 0;
while cnt < 1024 loop
tcp_rx_tdata <= std_logic_vector(to_unsigned(cnt, 8));
tcp_rx_tvalid <= '1';
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
cnt := cnt + 1;
end loop;
tcp_rx_tvalid <= '0';
wait until rising_edge(clk) and cpld_rx_tlast = '1' for 3us;
wait for 100 ns;
assert checking_finished report "Checking process failed to finish";
stop_the_clocks <= true;
end process;
------------------------------------------------------------------------------------------------
checking : process
type array_slv32_t is array(natural range <>) of std_logic_vector(31 downto 0);
variable tmp : array_slv32_t(0 to 5);
variable tmp_slv32 : std_logic_vector(31 downto 0);
begin
--First thing is packet to memory
tmp(0 to 1) := (x"00000004", x"c0000000");
for ct in 0 to 3 loop
for ct2 in 0 to 3 loop
tmp(2+ct)(31 - 8*ct2 downto 24 - 8*ct2) := std_logic_vector(to_unsigned(ct*4+ct2+1, 8));
end loop;
end loop;
for ct in 0 to tmp'high loop
wait until rising_edge(clk) and memory_rx_tvalid = '1';
assert cpld_rx_tvalid = '0' report "cpld valid line asserted when it should not have";
assert memory_rx_tdata = tmp(ct) report "Packet to memory failed to arrive as expected.";
if ct = tmp'high then
assert memory_rx_tlast = '1' report "Packet to memory tlast failed to assert correctly";
else
assert memory_rx_tlast = '0' report "Packet to memory tlast failed to assert correctly";
end if;
end loop;
--Then read request to memory
tmp(0 to 1) := (x"100000ff", x"c0000000");
for ct in 0 to 1 loop
wait until rising_edge(clk) and memory_rx_tvalid = '1';
assert cpld_rx_tvalid = '0' report "cpld valid line asserted when it should not have";
assert memory_rx_tdata = tmp(ct) report "Packet to memory failed to arrive as expected.";
if ct = 1 then
assert memory_rx_tlast = '1' report "Packet to memory tlast failed to assert correctly";
else
assert memory_rx_tlast = '0' report "Packet to memory tlast failed to assert correctly";
end if;
end loop;
--Then short command only to CPLD
tmp(0 to 1) := (x"20000000", x"baada555");
for ct in 0 to 1 loop
wait until rising_edge(clk) and cpld_rx_tvalid = '1' and cpld_rx_tready = '1';
assert memory_rx_tvalid = '0' report "memory valid line asserted when it should not have";
assert cpld_rx_tdata = tmp(ct) report "Packet cmd and addr to cpld failed to arrive as expected.";
if ct = 1 then
assert cpld_rx_tlast = '1' report "Packet to cpld tlast failed to assert correctly";
else
assert cpld_rx_tlast = '0' report "Packet to cpld tlast failed to assert correctly";
end if;
end loop;
--Then longer packet to CPLD
tmp(0 to 1) := (x"25000100", x"baada555");
for ct in 0 to 1 loop
wait until rising_edge(clk) and cpld_rx_tvalid = '1' and cpld_rx_tready = '1';
assert memory_rx_tvalid = '0' report "memory valid line asserted when it should not have";
assert cpld_rx_tdata = tmp(ct) report "Packet cmd and addr to cpld failed to arrive as expected.";
end loop;
for ct in 0 to 255 loop
wait until rising_edge(clk) and cpld_rx_tvalid = '1' and cpld_rx_tready = '1';
for ct2 in 0 to 3 loop
tmp_slv32(31 - 8*ct2 downto 24 - 8*ct2) := std_logic_vector(to_unsigned(ct*4+ct2, 8));
end loop;
assert cpld_rx_tdata = tmp_slv32 report "Packet to cpld failed to arrive as expected: " & integer'image(to_integer(unsigned(tmp_slv32)));
if ct = 255 then
assert cpld_rx_tlast = '1' report "Packet to cpld tlast failed to assert correctly";
else
assert cpld_rx_tlast = '0' report "Packet to cpld tlast failed to assert correctly";
end if;
end loop;
checking_finished <= true;
wait;
end process;
end;
| mpl-2.0 | ea6f1e098a6980c5c92e444dc1763d06 | 0.625196 | 3.045828 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_vk_testbench_256bits.vhd | 1 | 10,614 | -- Twofish_ecb_vk_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE KEY KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity vk_testbench256 is
end vk_testbench256;
architecture vk_encryption256_testbench_arch of vk_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round256
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_vk_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_vk_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 256) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_encryption_circuit: twofish_encryption_round256
port map (
in1_ter256 => to_round(127 downto 96),
in2_ter256 => to_round(95 downto 64),
in3_ter256 => to_round(63 downto 32),
in4_ter256 => to_round(31 downto 0),
in_Sfirst_ter256 => Sfirst,
in_Ssecond_ter256 => Ssecond,
in_Sthird_ter256 => Sthird,
in_Sfourth_ter256 => Sfourth,
in_key_up_ter256 => key_up,
in_key_down_ter256 => key_down,
out1_ter256 => to_encr_reg128(127 downto 96),
out2_ter256 => to_encr_reg128(95 downto 64),
out3_ter256 => to_encr_reg128(63 downto 32),
out4_ter256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
vk_proc: process
variable key_f, -- key input from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter : integer range 1 to 257 := 1; -- counts the encryptions
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption
begin
-- plaintext stays fixed to zero
input_data <= (others => '0');
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Variable Key Known Answer Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process vk_proc;
end vk_encryption256_testbench_arch;
| gpl-2.0 | f15bcf955d6a1abdfc2004cf4555109d | 0.650085 | 2.687769 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_and.vhd | 1 | 9,849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
B4F38xvg9o6MfvtcNoRvP8x8cSXEp8i1ELCfm1Q9WTMDHr3da+0D2qdz0TusQWqYQIp81Gh6lJcQ
lvHP7a5WXg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Y2p8uUgm+zh6L3BAgWFeiVoAmLERMKWWv/TXIFDNA0pUOVoN4Pd2JlxiMJJ1Ah7Ts0HlruRGNqZT
ikA7tCxdHBqN6udkfcf2/Fno5XnmnEq3Qi5APasxXizwlcZJgCzBvjRvuWyODmxHCncnHACDofUW
zb9RzyF3k8iz3isKhFI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YKDX9mSdzIx1gI3u6QeG2Q/kWjg9Eln/B1yOoGESJfmn8o4m4rZ6PqCc9UZbiCo3r3APV6s1BuXz
Gam0oKMAzHdwwRUcu1xohagQ4wyBcURy85nNjI7F6FQxJqs+mmgjdcHF0t+fU7oRVYivLog8VnfR
bU10cfHIbFTpw5O9kwiU25Izg7c+1nMECfGp3Z4RuXdNE1BeZm+fxHDVb+5VT/ktUwO+QPirbPF4
goTEvcJT+Hlss6HMLfAPFLFU5mFD+CeKabusbOjAb0BODZXJUEwshzR/8xOgCifhUt8UrR5iMkUm
3hslv9uUukWpdjhUho2B3W5Oc/4IfVYDttx3XQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bxMxQWGxuKONgjcyL09El42cTTff1jrO65R3vZ9eWww6LeXFSeF3I5HTf6huDy5UVFRO/7q1ac79
Tj0kh+s4DYZd96EHI798OurAB96i+QaBwVkUP1BVIr8u04RZL+RcseAUa3iNKanfP8TpkTZrBr4P
AoNwVg06IosYNlKKxsU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| apache-2.0 | de65ca9fcf6d41839beefdbe5376c33f | 0.922429 | 1.881735 | false | false | false | false |
rhexsel/xinu-cMIPS | xinu/zSrc/tb_cMIPS.vhd | 1 | 39,547 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity tb_cMIPS is
end tb_cMIPS;
architecture TB of tb_cMIPS is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component fake_FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component fake_FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component io_addr_decode is
port (clk : in std_logic;
rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component simul_ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component simul_ROM;
component fpga_ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component fpga_ROM;
component simul_RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component simul_RAM;
component fpga_RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component fpga_RAM;
component fake_I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component fake_I_CACHE;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component fake_D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component fake_D_CACHE;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
signal clock_50mhz, clk,clkin : std_logic;
signal clk4x,clk4x0, clk4x180, clk2x : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in, phi2_dlyd : std_logic;
signal rst,ic_reset,a_rst1,a_rst2,a_rst3, cpu_reset : std_logic;
signal a_reset, async_reset : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic := '1';
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal cpu_xfer, mem_xfer, dev_select, dev_select_ram, dev_select_io : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out : reg32;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal start_remota : std_logic;
signal bit_rt : reg3;
-- Macnica development board's peripherals
signal disp0,disp1 : reg8; -- 7 segment displays
signal keys : reg12; -- 12key telephone keyboard
signal switches : reg4; -- 4 switches
signal led_r, led_g, led_b : std_logic; -- RGB leds
signal LCD_DATA : std_logic_vector(7 downto 0); -- LCD data bus
signal LCD_RS, LCD_RW, LCD_EN, LCD_BLON : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
begin -- TB
pll : mf_altpll port map (areset => a_reset, inclk0 => clock_50mhz,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => a_reset, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk2x <= '0';
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize reset
a_rst1 <= a_reset or rst;
U_SYNC_RESET1: FFD port map (clk, a_rst2, '1', a_rst1, rst);
U_SYNC_RESET2: FFD port map (clk, a_reset, '1', '1', a_rst2);
async_reset <= rst and ic_reset;
U_SYNC_RESET3: FFD port map (clk, rst, '1', async_reset, a_rst3);
U_SYNC_RESET4: FFD port map (clk, rst, '1', a_rst3, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait;
io_wait <= '1'; -- io_lcd_wait and io_fpu_wait;
not_waiting <= (inst_wait and data_wait); -- and io_wait);
-- irq <= b"000000"; -- NO interrupt requests
irq <= uart_irq & counter_irq & b"0000"; -- uart+counter interrupts
-- irq <= counter_irq & b"00000"; -- counter interrupts
nmi <= '0'; -- input port to TB
U_CORE: core port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
U_I_CACHE: fake_i_cache -- or i_cache
-- U_I_CACHE: i_cache -- or fake_i_cache
-- U_I_CACHE: i_cache_fpga -- or FPGA implementation
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: simul_ROM generic map ("prog.bin")
-- U_ROM: fpga_ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
U_IO_ADDR_DEC: io_addr_decode
port map (phi0, rst, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel,io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
dev_select <= dev_select_io or dev_select_ram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
stdin_d_out when b"0100",
read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
(others => 'X') when others;
U_D_CACHE: fake_d_cache -- or d_cache
-- U_D_CACHE: d_cache -- or fake_d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_RAM: simul_RAM generic map ("data.bin", "dump.data")
-- U_RAM: fpga_RAM generic map ("data.bin", "dump.data")
port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
U_from_stdin: from_stdin
port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
U_read_inp: read_data_file generic map ("input.data")
port map (rst,clk, io_read_sel, wr, d_addr,read_d_out, cpu_xfer);
U_write_out: write_data_file generic map ("output.data")
port map (rst,clk, io_write_sel, wr, d_addr,cpu_data, cpu_xfer, dump_ram);
U_print_data: print_data
port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1);
keys <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
switches <= b"0000";
U_read_keys: read_keys
generic map (6) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, keys, switches);
led_r <= keybd_d_out(0);
led_g <= keybd_d_out(1);
led_b <= keybd_d_out(2);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_blon);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(2), cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- uncoment next line for loop back, comment out previous line
-- uart_txd, uart_txd, uart_rts, uart_cts, uart_irq, bit_rt);
uart_cts <= '1';
start_remota <= '0', '1' after 200*CLOCK_PER;
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, start_remota, uart_txd, uart_rxd, bit_rt);
-- U_FPU: fake_FPU
U_FPU: FPU
port map (rst,clk, io_FPU_sel,io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data,fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
U_clock: process -- simulate external clock
begin
clock_50mhz <= '1';
wait for CLOCK_PER / 2;
clock_50mhz <= '0';
wait for CLOCK_PER / 2;
end process; -- -------------------------------------------------------
-- simulate reset switch bounces
a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture TB;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
constant HI_ADDR : integer := HI_SEL_BITS;
constant LO_ADDR : integer := log2_ceil(INST_BASE_ADDR + INST_MEM_SZ);
constant PREFIX : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'0');
signal in_range : boolean;
begin
in_range <= (addr(HI_ADDR downto LO_ADDR) = PREFIX);
aVal <= '0' when ( cpu_i_aVal = '0' and rst = '1' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and rst = '1'
and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant RAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant RAM_ADDR_RANGE : natural :=
(to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_DATA_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant RAM_ADDR_TOP : natural := RAM_ADDR_BOTTOM + RAM_ADDR_RANGE;
begin
-- in_range <= ( rst = '1'
-- and ((addr and a_mask) = x_DATA_BASE_ADDR)
-- and ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- this works only for small RAMS
-- in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
-- =
-- x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
RAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
RAM_ADDR_TOP)
);
aVal <= '0' when (rst = '1' and cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert true -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
signal in_range, io_in_range : boolean;
begin
in_range <= ( rst = '1' and
((addr and a_mask) = x_DATA_BASE_ADDR) and
((addr and r_mask) = x_DATA_BASE_ADDR) );
io_in_range <= ( (rst = '1') and ((addr and x_mask) = x_IO_BASE_ADDR) );
d_busError <= '0' when ( (rst = '1') and (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert true -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
assert true -- cpu_d_aVal = '1' and io_busError
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (clk,rst : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- telephone keyboard (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant HI_SEL_ADDR : integer := LO_SEL_ADDR + (IO_MAX_NUM_DEVS - 1);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
dev <= to_integer(signed(addr(HI_SEL_ADDR downto LO_SEL_ADDR)));
aVal <= '0' when ( cpu_d_aVal = '0' and rst = '1' and not_waiting = '1' and
in_range ) else '1';
U_decode: process(clk, aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_signed(is_print, 4));
print_sel <= aVal or clk;
when 1 => dev_sel := std_logic_vector(to_signed(is_stdout, 4));
stdout_sel <= aVal or clk;
when 2 => dev_sel := std_logic_vector(to_signed(is_stdin, 4));
stdin_sel <= aVal or clk;
when 3 => dev_sel := std_logic_vector(to_signed(is_read, 4));
read_sel <= aVal or clk;
when 4 => dev_sel := std_logic_vector(to_signed(is_write, 4));
write_sel <= aVal or clk;
when 5 => dev_sel := std_logic_vector(to_signed(is_count, 4));
counter_sel <= aVal;
when 6 => dev_sel := std_logic_vector(to_signed(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_signed(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_signed(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_signed(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_signed(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_signed(is_lcd, 4));
lcd_sel <= aVal;
when others => dev_sel := std_logic_vector(to_signed(is_noise, 4));
end case;
-- assert false report "IO_addr "& SLV32HEX(addr);--DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_signed(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- --------------------------------------------------------------
configuration CFG_TB of TB_CMIPS is
for TB
end for;
end configuration CFG_TB;
-- --------------------------------------------------------------
| gpl-3.0 | 3bfec112fabd81a632c6ece8bfb32e9a | 0.531418 | 3.26107 | false | false | false | false |
rcls/sdr | vhdl/blinkoflow.vhd | 1 | 1,083 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity blinkoflow is
generic (data_bits : integer := 14;
mon_bits : integer := 4;
count_bits : integer := 25);
port (d : in signed(data_bits - 1 downto 0);
good : out std_logic;
bad : out std_logic;
clk : in std_logic);
end blinkoflow;
architecture blinkoflow of blinkoflow is
signal counter : unsigned (count_bits - 1 downto 0);
signal oflow : boolean;
constant twiddle : signed(data_bits - 1 downto 0) := (
data_bits - 1 => '1', others => '0');
begin
process
variable ud : signed(data_bits - 1 downto 0);
begin
wait until rising_edge(clk);
good <= counter(count_bits - 1);
bad <= not counter(count_bits - 1);
ud := d xor twiddle;
oflow <= ud(data_bits - 1 downto data_bits - mon_bits + 1)
= ud(data_bits - 2 downto data_bits - mon_bits);
if oflow then
counter <= (others => '0');
elsif counter(count_bits - 1) = '0' then
counter <= counter + 1;
end if;
end process;
end blinkoflow;
| gpl-3.0 | b987dd13faae42155126ff543796fd4a | 0.601108 | 3.384375 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/cdc_sync.vhd | 1 | 25,145 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute DONT_TOUCH : STRING;
attribute DONT_TOUCH of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
s_out_d5 <= '0';
s_out_d6 <= '0';
s_out_d7 <= '0';
scndry_out <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
s_out_d5 <= s_out_d4;
s_out_d6 <= s_out_d5;
s_out_d7 <= s_out_d6;
scndry_out <= s_out_re;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= s_out_d2 xor s_out_d3;
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= s_out_d3 xor s_out_d4;
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= s_out_d4 xor s_out_d5;
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= s_out_d5 xor s_out_d6;
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= s_out_d6 xor s_out_d7;
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_bus_d1_cdc_from <= (others => '0');
else
p_level_in_bus_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_bus_d1_cdc_to <= (others => '0');
s_level_out_bus_d2 <= (others => '0');
s_level_out_bus_d3 <= (others => '0');
s_level_out_bus_d4 <= (others => '0');
s_level_out_bus_d5 <= (others => '0');
s_level_out_bus_d6 <= (others => '0');
else
s_level_out_bus_d1_cdc_to <= p_level_in_bus_int;
s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
s_level_out_bus_d3 <= s_level_out_bus_d2;
s_level_out_bus_d4 <= s_level_out_bus_d3;
s_level_out_bus_d5 <= s_level_out_bus_d4;
s_level_out_bus_d6 <= s_level_out_bus_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
p_level_out_d3 <= '0';
p_level_out_d4 <= '0';
p_level_out_d5 <= '0';
p_level_out_d6 <= '0';
p_level_out_d7 <= '0';
prmry_ack <= '0';
else
p_level_out_d1_cdc_to <= scndry_out_int;
p_level_out_d2 <= p_level_out_d1_cdc_to;
p_level_out_d3 <= p_level_out_d2;
p_level_out_d4 <= p_level_out_d3;
p_level_out_d5 <= p_level_out_d4;
p_level_out_d6 <= p_level_out_d5;
p_level_out_d7 <= p_level_out_d6;
prmry_ack <= prmry_pulse_ack;
end if;
end if;
end process CROSS_PLEVEL_SCNDRY2PRMRY;
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| apache-2.0 | ea67ed61c9e4d8128c8d9904d08043b2 | 0.473136 | 3.652673 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/9-MESA-FP/asap-alap-random/mesafp_asap.vhd | 1 | 4,540 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END mesafp_asap_entity;
ARCHITECTURE mesafp_asap_description OF mesafp_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 * 11;
register12 := input12 + 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 * 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 * 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
WHEN "00000010" =>
register1 := register1 + 23;
register2 := register21 + register2;
register3 := register17 + register3;
register4 := register4 + 25;
register5 := register5 + 27;
register6 := register19 + register6;
register7 := register7 + 29;
register8 := register8 + 31;
register9 := register15 + register9;
register10 := register10 + register12;
register12 := register13 + 33;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register20 + register2;
register3 := register16 + register3;
register5 := ((NOT register5) + 1) XOR register5;
register6 := register18 + register6;
register9 := register14 + register9;
register10 := register11 + register10;
WHEN "00000100" =>
IF (register5 = 38 or register1 = 38) THEN
output1 <= register5;
ELSE
output1 <= "00110";
END IF;
register1 := ((NOT register2) + 1) XOR register2;
register2 := ((NOT register3) + 1) XOR register3;
register3 := ((NOT register6) + 1) XOR register6;
register5 := ((NOT register9) + 1) XOR register9;
register6 := ((NOT register10) + 1) XOR register10;
WHEN "00000101" =>
output2 <= register1(0 TO 1) & register4(0 TO 2);
register1 := register6 / 2;
WHEN "00000110" =>
register3 := register1 * register3;
register2 := register1 * register2;
register1 := register1 * register5;
WHEN "00000111" =>
output3 <= register3(0 TO 1) & register8(0 TO 2);
output4 <= register2(0 TO 1) & register7(0 TO 2);
output5 <= register1(0 TO 1) & register12(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesafp_asap_description; | gpl-3.0 | 1c2d7a4677f55b10b629bf7e3342a75a | 0.662115 | 3.15936 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/register_file_bit.vhd | 1 | 18,065 | `protect begin_protected
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| apache-2.0 | 23c36eabd7095307a87b119d16f809aa | 0.939219 | 1.859496 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/asap-alap-random/fir1_asap.vhd | 1 | 4,249 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:19:26)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_asap_entity;
ARCHITECTURE fir1_asap_description OF fir1_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register22: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
register5 := input5 and input5;
register6 := input6 and input6;
register7 := input7 and input7;
register8 := input8 and input8;
register9 := input9 and input9;
register10 := input10 and input10;
register11 := input11 and input11;
register12 := input12 and input12;
register13 := input13 and input13;
register14 := input14 and input14;
register15 := input15 and input15;
register16 := input16 and input16;
register17 := input17 and input17;
register18 := input18 and input18;
register19 := input19 and input19;
register20 := input20 and input20;
register21 := input21 and input21;
register22 := input22 and input22;
WHEN "00000010" =>
register1 := register1 * register9;
register2 := register2 * register21;
register3 := register3 * register17;
register4 := register4 * register20;
register5 := register5 * register22;
register6 := register6 * register10;
register7 := register7 * register12;
register8 := register14 * register8;
register9 := register11 * register19;
register10 := register13 * register15;
register11 := register16 * register18;
WHEN "00000011" =>
register2 := register8 + register2;
register3 := register11 + register3;
register6 := register7 + register6;
WHEN "00000100" =>
register1 := register6 + register1;
WHEN "00000101" =>
register1 := register4 + register1;
WHEN "00000110" =>
register1 := register2 + register1;
WHEN "00000111" =>
register1 := register1 + register5;
WHEN "00001000" =>
register1 := register3 + register1;
WHEN "00001001" =>
register1 := register1 + register10;
WHEN "00001010" =>
register1 := register9 + register1;
WHEN "00001011" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_asap_description; | gpl-3.0 | 6ed55feb8db88950df24404c17ad07aa | 0.688397 | 3.291247 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_pf_sshft.vhd | 5 | 20,160 | `protect begin_protected
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`protect end_protected
| apache-2.0 | cba260ff375eb48001d2a7208649fbff | 0.941518 | 1.845816 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/ram.vhd | 1 | 14,075 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- To simplify (and accelerate) internal address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address that is larger the RAM capacity. Otherwise, the
-- base must be subtracted from the address on every reference,
-- which means having an adder in the critical path. Bad idea.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM for synthesis; NON-initialized, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity RAM is
generic (LOAD_FILE_NAME : string := "data.bin";
DUMP_FILE_NAME : string := "dump.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
strobe : in std_logic; -- active in '1'
addr : in reg32;
data_inp : in reg32;
data_out : out reg32;
byte_sel : in reg4;
dump_ram : in std_logic); -- dump RAM contents
-- simulation version
constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
-- FPGA version
constant N_WORDS : natural := 8192;
constant ADDRS_BITS : natural := log2_ceil(N_WORDS);
subtype ram_address is integer range 0 to N_WORDS-1;
subtype ram_addr_bits is std_logic_vector(ADDRS_BITS-1 downto 0);
end entity RAM;
architecture rtl of RAM is
component mf_ram1port
generic (N_WORDS : integer; ADDRS_BITS : integer);
port (address : in std_logic_vector (ADDRS_BITS-1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector (7 downto 0);
wren : in std_logic;
q : out std_logic_vector (7 downto 0));
end component mf_ram1port;
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
signal we0,we1,we2,we3 : std_logic := '0';
signal di,do : reg32;
signal r_addr : ram_address := 0;
signal r_address : ram_addr_bits;
signal waiting, enable : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel);
-- CPU acesses are word-addressed; RAM is byte-addressed, 4-bytes wide
r_addr <= to_integer( unsigned(addr( (ADDRS_BITS-1+2) downto 2 ) ) );
r_address <= addr( ADDRS_BITS-1+2 downto 2 );
U_ram0: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(7 downto 0), we0, do(7 downto 0));
U_ram1: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(15 downto 8), we1, do(15 downto 8));
U_ram2: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(23 downto 16), we2, do(23 downto 16));
U_ram3: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(31 downto 24), we3, do(31 downto 24));
accessRAM: process(sel, strobe, wr, r_addr, byte_sel, data_inp, do)
begin
if sel = '0' then
if wr = '0' then -- WRITE to MEM
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramWR index out of bounds: " & natural'image(r_addr)
severity failure;
case byte_sel is -- partial word stores
when b"1111" => -- SW
we3 <= '1';
we2 <= '1';
we1 <= '1';
we0 <= '1';
di <= data_inp;
when b"1100" => -- SH, upper
we3 <= '1';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 16) <= data_inp(15 downto 0);
di(15 downto 0) <= (others => 'X');
when b"0011" => -- SH. lower
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '1';
di(15 downto 0) <= data_inp(15 downto 0);
di(31 downto 16) <= (others => 'X');
when b"0001" => -- SB
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '1';
di(7 downto 0) <= data_inp(7 downto 0);
di(31 downto 8) <= (others => 'X');
when b"0010" =>
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '0';
di(31 downto 16) <= (others => 'X');
di(15 downto 8) <= data_inp(7 downto 0);
di(7 downto 0) <= (others => 'X');
when b"0100" =>
we3 <= '0';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= (others => 'X');
di(23 downto 16) <= data_inp(7 downto 0);
di(15 downto 0) <= (others => 'X');
when b"1000" =>
we3 <= '1';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= data_inp(7 downto 0);
di(23 downto 0) <= (others => 'X');
when others =>
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
end case;
assert TRUE report "ramWR["& natural'image(r_addr) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
data_out <= (others => 'X');
else -- READ from MEM, wr /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramRD index out of bounds: " & natural'image(r_addr)
severity failure;
-- byte/half selection done at CPU
data_out(31 downto 24) <= do(31 downto 24);
data_out(23 downto 16) <= do(23 downto 16);
data_out(15 downto 8) <= do(15 downto 8);
data_out(7 downto 0) <= do(7 downto 0);
assert TRUE report "ramRD["& natural'image(r_addr) &"] "
& SLV32HEX(do) &" bySel="& SLV2STR(byte_sel); -- DEBUG
end if; -- wr
else -- sel /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
data_out <= (others => 'X');
end if;
end process accessRAM;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of RAM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
signal wait_counter, ram_current : integer;
subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
subtype word is std_logic_vector(7 downto 0);
type storage_array is
array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
signal storage : storage_array;
signal enable, waiting, do_wait : std_logic;
begin -- simulation
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel); -- and not(waiting);
accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
variable u_addr : t_address;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable datum: integer;
variable s_datum: signed(31 downto 0);
file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
variable d : reg32 := (others => 'X');
variable val, i : integer;
begin
if rst = '0' then -- reset, read-in binary initialized data
index := 0; -- byte indexed
for i in 0 to (DATA_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, datum);
s_datum := to_signed(datum, 32);
assert TRUE report "ramINIT["& natural'image(index*4)&"]= " &
SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
index := index + 4;
end if;
end loop;
data_out <= (others=>'X');
else -- (rst = '1'), normal operation
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
if sel = '0' and wr = '0' and rising_edge(strobe) then
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramWR index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- SW
storage(index+3) <= data_inp(31 downto 24);
storage(index+2) <= data_inp(23 downto 16);
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"1100" | b"0011" => -- SH
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
storage(index+0) <= data_inp(7 downto 0);
when others => null;
end case;
assert TRUE report "ramWR["& natural'image(index) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
end if; -- is write?
if sel = '0' and wr = '1' then
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramRD index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- LW
d(31 downto 24) := storage(index+3);
d(23 downto 16) := storage(index+2);
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"1100" => -- LH top-half
d(31 downto 24) := storage(index+1);
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"0011" => -- LH bottom-half
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"0001" => -- LB top byte
d(31 downto 8) := (others => 'X');
d(7 downto 0) := storage(index+0);
when b"0010" => -- LB mid-top byte
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+0);
d(7 downto 0) := (others => 'X');
when b"0100" => -- LB mid-bot byte
d(31 downto 24) := (others => 'X');
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"1000" => -- LB bottom byte
d(31 downto 24) := storage(index+0);
d(23 downto 0) := (others => 'X');
when others => d := (others => 'X');
end case;
assert TRUE report "ramRD["& natural'image(index) &"] "
& SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
elsif rising_edge(dump_ram) then
i := 0;
while i < DATA_MEM_SZ-4 loop
d(31 downto 24) := storage(i+3);
d(23 downto 16) := storage(i+2);
d(15 downto 8) := storage(i+1);
d(7 downto 0) := storage(i+0);
write( dump_file, to_integer(signed(d)) );
i := i+4;
end loop; -- i
else
d := (others=>'X');
end if; -- is read?
data_out <= d;
end if; -- is reset?
end process accessRAM; -- ---------------------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | cde9998affcf60ee47f42d0b8280207c | 0.484689 | 3.643541 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_muxcy.vhd | 15 | 10,538 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| apache-2.0 | c01c7d56158778ccfc2947fc4751d731 | 0.403302 | 5.018095 | false | false | false | false |
freecores/twofish | vhdl/twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd | 1 | 11,468 | -- Twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench192 is
end cbc_decryption_monte_carlo_testbench192;
architecture cbc_decryption192_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round192
port (
in1_tdr192,
in2_tdr192,
in3_tdr192,
in4_tdr192,
in_Sfirst_tdr192,
in_Ssecond_tdr192,
in_Sthird_tdr192,
in_key_up_tdr192,
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
out1_tdr192,
out2_tdr192,
out3_tdr192,
out4_tdr192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_192bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_decryption_circuit: twofish_decryption_round192
port map (
in1_tdr192 => to_round(127 downto 96),
in2_tdr192 => to_round(95 downto 64),
in3_tdr192 => to_round(63 downto 32),
in4_tdr192 => to_round(31 downto 0),
in_Sfirst_tdr192 => Sfirst,
in_Ssecond_tdr192 => Ssecond,
in_Sthird_tdr192 => Sthird,
in_key_up_tdr192 => key_up,
in_key_down_tdr192 => key_down,
out1_tdr192 => to_encr_reg128(127 downto 96),
out2_tdr192 => to_encr_reg128(95 downto 64),
out3_tdr192 => to_encr_reg128(63 downto 32),
out4_tdr192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption192_monte_carlo_testbench_arch;
| gpl-2.0 | 913c5860735e36abf3802aaa573d7754 | 0.645448 | 2.69645 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_skid2mm_buf.vhd | 1 | 18,117 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_skid2mm_buf.vhd
-- |
-- |- axi_master_burst_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $10/19/2009$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamover_skid2axi_buf.vhd
-- ^^^^^^
--
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- -- Per CR593362
-- - Removed resets from the data path of the Skid and Output registers.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_wr_demux;
-------------------------------------------------------------------------------
entity axi_master_burst_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 256 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 256 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
--------------------------------------------------------------------------
-- System Ports
--------------------------------------------------------------------------
aclk : In std_logic ; -- clock
arst : In std_logic ; -- reset
--------------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side )
--------------------------------------------------------------------------
s_addr_lsb : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); -- Demuxing Control
s_valid : In std_logic ; -- AXI4 Stream Like
s_ready : Out std_logic ; -- AXI4 Stream Like
s_data : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); -- AXI4 Stream Like
s_strb : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream Like
s_last : In std_logic ; -- AXI4 Stream Like
--------------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side)
--------------------------------------------------------------------------
m_valid : Out std_logic ; -- AXI4 Stream Like
m_ready : In std_logic ; -- AXI4 Stream Like
m_data : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); -- AXI4 Stream Like
m_strb : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream Like
m_last : Out std_logic -- AXI4 Stream Like
);
end entity axi_master_burst_skid2mm_buf;
architecture implementation of axi_master_burst_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_mirror_data_out;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else s_strb;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else s_last;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (aclk)
begin
if (aclk'event and aclk = '1') then
sig_reset_reg <= arst;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: s_ready_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
s_ready_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process s_ready_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: m_valid_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
m_valid_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process m_valid_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= s_last;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_master_burst_v2_0.axi_master_burst_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => s_strb ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => s_addr_lsb
);
end implementation;
| apache-2.0 | 506fe0940f854fe878d1e165e7bf67dd | 0.483524 | 4.39413 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leko/g25.vhd | 1 | 12,422 | -- Xilinx XPort Language Converter, Version 4.1 (110)
--
-- ABEL Design Source: C:\home\kirill\xillinx\testing.abl
-- VHDL Design Output: testing.vhd
-- Created 02-Sep-2005 12:24 PM
--
-- Copyright (c) 2005, Xilinx, Inc. All Rights Reserved.
-- Xilinx Inc makes no warranty, expressed or implied, with respect to
-- the operation and/or functionality of the converted output files.
--
-- ee200 assignment 1
Library IEEE;
use IEEE.std_logic_1164.all;
entity testing is
Port (
A40, A39, A73: buffer std_logic;
A299, A265, A298: in std_logic;
A105: buffer std_logic;
A202, A201: in std_logic;
A43, A8, A41: buffer std_logic;
A269, A232, A170: in std_logic;
A106: buffer std_logic;
A166: in std_logic;
A76: buffer std_logic;
A234, A236, A167: in std_logic;
A109, A140: buffer std_logic;
A300: in std_logic;
A42: buffer std_logic;
A203, A267: in std_logic;
A108: buffer std_logic;
A235, A233: in std_logic;
A74: buffer std_logic;
A301, A168: in std_logic;
A138, A7, A139, A142, A6: buffer std_logic;
A268: in std_logic;
A141, A10, A72: buffer std_logic;
A200: in std_logic;
A75: buffer std_logic;
A169: in std_logic;
A107, A9: buffer std_logic;
A266, A302, A199: in std_logic
);
end testing;
architecture testing_behav of testing is
signal A165, A12, A137, A188, A270, A317, A314, A61, A258, A119, A66, A220,
A309, A230, A112, A295, A69, A310, A121, A325, A284, A91, A93, A257,
A34, A195, A160, A57, A321, A173, A281, A186, A89, A179, A48, A239,
A13, A120, A253, A23, A154, A50, A211, A190, A206, A175, A16, A68,
A38, A17, A225, A44, A129, A244, A85, A131, A192, A104, A273, A254,
A113, A223, A243, A4, A96, A101, A311, A318, A117, A124, A78, A147,
A324, A216, A161, A259, A31, A56, A315, A97, A231, A128, A278, A178,
A3, A22, A60, A198, A250, A26, A100, A306, A287, A261, A171, A227,
A94, A59, A82, A288, A172, A246, A185, A151, A155, A132, A30, A35,
A183, A224, A79, A189, A328, A14, A323, A116, A293, A65, A320, A207,
A88, A193, A305, A249, A327, A237, A215, A219, A277, A176, A53, A18,
A296, A125, A294, A228, A47, A280, A25, A217, A102, A205, A46, A67,
A5, A255, A251, A204, A272, A222, A64, A98, A95, A164, A135, A285,
A70, A149, A32, A312, A81, A49, A275, A248, A208, A123, A282, A289,
A146, A177, A159, A2, A118, A90, A297, A182, A242, A110, A152, A283,
A197, A83, A319, A307, A36, A241, A264, A326, A63, A260, A194, A144,
A330, A163, A212, A158, A291, A114, A133, A51, A229, A304, A29, A316,
A87, A28, A62, A54, A33, A276, A290, A322, A303, A145, A184, A111,
A274, A214, A58, A20, A226, A126, A245, A80, A86, A196, A52, A313,
A143, A218, A103, A209, A156, A11, A174, A187, A115, A71, A240, A256,
A92, A1, A247, A292, A150, A210, A134, A238, A162, A286, A329, A148,
A252, A213, A45, A21, A27, A127, A221, A99, A153, A263, A191, A19,
A37, A77, A24, A157, A279, A181, A55, A15, A271, A84, A262, A308,
A122, A180, A136, A130: std_logic;
begin
-- Start of original equations
A198 <= A176 and A191;
A197 <= (not A176) and (not A198);
A196 <= A176 or A191;
A195 <= (not A169) or (not A170);
A194 <= A176 or A191;
A193 <= (not A192) and (not A176);
A192 <= A176 and A191;
A191 <= (not A167) or (not A168);
A190 <= A168 and A180;
A189 <= A169 or A176;
A188 <= A169 or A170;
A187 <= (not A197) or (not A196);
A186 <= A195 and A188;
A185 <= ((not A169) and A176) or (A169 and (not A176));
A184 <= (not A193) or (not A194);
A183 <= (A168 and A180) or ((not A168) and (not A180));
A182 <= A190 or A167;
A181 <= A187 and A168;
A180 <= A189 and A188;
A179 <= A184 and A168;
A178 <= A186 and A185;
A177 <= ((not A178) and A168) or (A178 and (not A168));
A176 <= ((not A166) and A167) or (A166 and (not A167));
A175 <= A176 and A183;
A174 <= A176 and A182;
A173 <= A181 or A180;
A172 <= A179 or A178;
A171 <= A177 and A176;
A204 <= A210 and A209;
A205 <= A212 or A211;
A206 <= A214 or A213;
A207 <= A209 and A215;
A208 <= A209 and A216;
A209 <= ((not A199) and A200) or (A199 and (not A200));
A210 <= ((not A211) and A201) or (A211 and (not A201));
A211 <= A219 and A218;
A212 <= A217 and A201;
A213 <= A222 and A221;
A214 <= A220 and A201;
A215 <= A223 or A200;
A216 <= (A201 and A213) or ((not A201) and (not A213));
A217 <= (not A226) or (not A227);
A218 <= ((not A202) and A209) or (A202 and (not A209));
A219 <= A228 and A221;
A220 <= (not A230) or (not A229);
A221 <= A202 or A203;
A222 <= A202 or A209;
A223 <= A201 and A213;
A224 <= (not A200) or (not A201);
A225 <= A209 and A224;
A226 <= (not A225) and (not A209);
A227 <= A209 or A224;
A228 <= (not A202) or (not A203);
A229 <= A209 or A224;
A230 <= (not A209) and (not A231);
A231 <= A209 and A224;
A237 <= A243 and A242;
A238 <= A245 or A244;
A239 <= A247 or A246;
A240 <= A242 and A248;
A241 <= A242 and A249;
A242 <= ((not A232) and A233) or (A232 and (not A233));
A243 <= ((not A244) and A234) or (A244 and (not A234));
A244 <= A252 and A251;
A245 <= A250 and A234;
A246 <= A255 and A254;
A247 <= A253 and A234;
A248 <= A256 or A233;
A249 <= (A234 and A246) or ((not A234) and (not A246));
A250 <= (not A259) or (not A260);
A251 <= ((not A235) and A242) or (A235 and (not A242));
A252 <= A261 and A254;
A253 <= (not A263) or (not A262);
A254 <= A235 or A236;
A255 <= A235 or A242;
A256 <= A234 and A246;
A257 <= (not A233) or (not A234);
A258 <= A242 and A257;
A259 <= (not A258) and (not A242);
A260 <= A242 or A257;
A261 <= (not A235) or (not A236);
A262 <= A242 or A257;
A263 <= (not A235) or A235;
A264 <= A242 and A257;
A270 <= A276 and A275;
A271 <= A278 or A277;
A272 <= A280 or A279;
A273 <= A275 and A281;
A274 <= A275 and A282;
A275 <= ((not A265) and A266) or (A265 and (not A266));
A276 <= ((not A277) and A267) or (A277 and (not A267));
A277 <= A285 and A284;
A278 <= A283 and A267;
A279 <= A288 and A287;
A280 <= A286 and A267;
A281 <= A289 or A266;
A282 <= (A267 and A279) or ((not A267) and (not A279));
A283 <= (not A292) or (not A293);
A284 <= ((not A268) and A275) or (A268 and (not A275));
A285 <= A294 and A287;
A286 <= (not A296) or (not A295);
A287 <= A268 or A269;
A288 <= A268 or A275;
A289 <= A267 and A279;
A290 <= (not A266) or (not A267);
A291 <= A275 and A290;
A292 <= (not A291) and (not A275);
A293 <= A275 or A290;
A294 <= (not A268) or (not A269);
A295 <= A275 or A290;
A296 <= (not A275) and (not A297);
A297 <= A275 and A290;
A303 <= A309 and A308;
A304 <= A311 or A310;
A305 <= A313 or A312;
A306 <= A308 and A314;
A307 <= A308 and A315;
A308 <= ((not A298) and A299) or (A298 and (not A299));
A309 <= ((not A310) and A300) or (A310 and (not A300));
A310 <= A318 and A317;
A311 <= A316 and A300;
A312 <= A321 and A320;
A313 <= A319 and A300;
A314 <= A322 or A299;
A315 <= (A300 and A312) or ((not A300) and (not A312));
A316 <= (not A325) or (not A326);
A317 <= ((not A301) and A308) or (A301 and (not A308));
A318 <= A327 and A320;
A319 <= (not A329) or (not A328);
A320 <= A301 or A302;
A321 <= A301 or A308;
A322 <= A300 and A312;
A323 <= (not A299) or (not A300);
A324 <= A308 and A323;
A325 <= (not A324) and (not A308);
A326 <= A308 or A323;
A327 <= (not A301) or (not A302);
A328 <= A308 or A323;
A329 <= (not A308) and (not A330);
A330 <= A308 and A323;
A165 <= A143 and A158;
A164 <= (not A143) and (not A165);
A163 <= A143 or A158;
A162 <= (not A136) or (not A137);
A161 <= A143 or A158;
A160 <= (not A159) and (not A143);
A159 <= A143 and A158;
A158 <= (not A134) or (not A135);
A157 <= A135 and A147;
A156 <= A136 or A143;
A155 <= A136 or A137;
A154 <= (not A164) or (not A163);
A153 <= A162 and A155;
A152 <= ((not A136) and A143) or (A136 and (not A143));
A151 <= (not A160) or (not A161);
A150 <= (A135 and A147) or ((not A135) and (not A147));
A149 <= A157 or A134;
A148 <= A154 and A135;
A147 <= A156 and A155;
A146 <= A151 and A135;
A145 <= A153 and A152;
A144 <= ((not A145) and A135) or (A145 and (not A135));
A143 <= ((not A133) and A134) or (A133 and (not A134));
A142 <= A143 and A150;
A141 <= A143 and A149;
A140 <= A148 or A147;
A139 <= A146 or A145;
A138 <= A144 and A143;
A137 <= A307;
A136 <= A274;
A135 <= A241;
A134 <= A208;
A133 <= A171;
A132 <= A110 and A125;
A131 <= (not A110) and (not A132);
A130 <= A110 or A125;
A129 <= (not A103) or (not A104);
A128 <= A110 or A125;
A127 <= (not A126) and (not A110);
A126 <= A110 and A125;
A125 <= (not A101) or (not A102);
A124 <= A102 and A114;
A123 <= A103 or A110;
A122 <= A103 or A104;
A121 <= (not A131) or (not A130);
A120 <= A129 and A122;
A119 <= ((not A103) and A110) or (A103 and (not A110));
A118 <= (not A127) or (not A128);
A117 <= (A102 and A114) or ((not A102) and (not A114));
A116 <= A124 or A101;
A115 <= A121 and A102;
A114 <= A123 and A122;
A113 <= A118 and A102;
A112 <= A120 and A119;
A111 <= ((not A112) and A102) or (A112 and (not A102));
A110 <= ((not A100) and A101) or (A100 and (not A101));
A109 <= A110 and A117;
A108 <= A110 and A116;
A107 <= A115 or A114;
A106 <= A113 or A112;
A105 <= A111 and A110;
A104 <= A306;
A103 <= A273;
A102 <= A240;
A101 <= A207;
A100 <= A172;
A99 <= A77 and A92;
A98 <= (not A77) and (not A99);
A97 <= A77 or A92;
A96 <= (not A70) or (not A71);
A95 <= A77 or A92;
A94 <= (not A93) and (not A77);
A93 <= A77 and A92;
A92 <= (not A68) or (not A69);
A91 <= A69 and A81;
A90 <= A70 or A77;
A89 <= A70 or A71;
A88 <= (not A98) or (not A97);
A87 <= A96 and A89;
A86 <= ((not A70) and A77) or (A70 and (not A77));
A85 <= (not A94) or (not A95);
A84 <= (A69 and A81) or ((not A69) and (not A81));
A83 <= A91 or A68;
A82 <= A88 and A69;
A81 <= A90 and A89;
A80 <= A85 and A69;
A79 <= A87 and A86;
A78 <= ((not A79) and A69) or (A79 and (not A69));
A77 <= ((not A67) and A68) or (A67 and (not A68));
A76 <= A77 and A84;
A75 <= A77 and A83;
A74 <= A82 or A81;
A73 <= A80 or A79;
A72 <= A78 and A77;
A71 <= A305;
A70 <= A272;
A69 <= A239;
A68 <= A206;
A67 <= A173;
A66 <= A44 and A59;
A65 <= (not A44) and (not A66);
A64 <= A44 or A59;
A63 <= (not A37) or (not A38);
A62 <= A44 or A59;
A61 <= (not A60) and (not A44);
A60 <= A44 and A59;
A59 <= (not A35) or (not A36);
A58 <= A36 and A48;
A57 <= A37 or A44;
A56 <= A37 or A38;
A55 <= (not A65) or (not A64);
A54 <= A63 and A56;
A53 <= ((not A37) and A44) or (A37 and (not A44));
A52 <= (not A61) or (not A62);
A51 <= (A36 and A48) or ((not A36) and (not A48));
A50 <= A58 or A35;
A49 <= A55 and A36;
A48 <= A57 and A56;
A47 <= A52 and A36;
A46 <= A54 and A53;
A45 <= ((not A46) and A36) or (A46 and (not A36));
A44 <= ((not A34) and A35) or (A34 and (not A35));
A43 <= A44 and A51;
A42 <= A44 and A50;
A41 <= A49 or A48;
A40 <= A47 or A46;
A39 <= A45 and A44;
A38 <= A304;
A37 <= A271;
A36 <= A238;
A35 <= A205;
A34 <= A174;
A1 <= A303;
A2 <= A270;
A3 <= A237;
A4 <= A204;
A5 <= A175;
A6 <= A12 and A11;
A7 <= A14 or A13;
A8 <= A16 or A15;
A9 <= A11 and A17;
A10 <= A11 and A18;
A11 <= ((not A1) and A2) or (A1 and (not A2));
A12 <= ((not A13) and A3) or (A13 and (not A3));
A13 <= A21 and A20;
A14 <= A19 and A3;
A15 <= A24 and A23;
A16 <= A22 and A3;
A17 <= A25 or A2;
A18 <= (A3 and A15) or ((not A3) and (not A15));
A19 <= (not A28) or (not A29);
A20 <= ((not A4) and A11) or (A4 and (not A11));
A21 <= A30 and A23;
A22 <= (not A32) or (not A31);
A23 <= A4 or A5;
A24 <= A4 or A11;
A25 <= A3 and A15;
A26 <= (not A2) or (not A3);
A27 <= A11 and A26;
A28 <= (not A27) and (not A11);
A29 <= A11 or A26;
A30 <= (not A4) or (not A5);
A31 <= A11 or A26;
A32 <= (not A11) and (not A33);
A33 <= A11 and A26;
end testing_behav;
| gpl-3.0 | 8b385e5f0123e99c13377e69a10748e4 | 0.568507 | 2.418143 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_gate_f.vhd | 15 | 9,178 | -------------------------------------------------------------------------------
-- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate_f.vhd
--
-- Description: OR gates. The width of each OR gate (C_OR_WIDTH)
-- and the number of or gates (C_BUS_WIDTH) are
-- parameterizable.
--
-- Y(j) <= A(j) OR A(C_BUS_WIDTH+j)
-- OR A(2*C_BUS_WIDTH+j)
-- ...
-- OR A((C_OR_WIDTH-1)*C_BUS_WIDTH+j),
--
-- for 0 <= j < C_BUS_WIDTH
--
-- If C_FAMILY is set (or left defaulted) to "nofamily"
-- then the implementation will be by synthesis inference.
-- Otherwise, a structural implementation optimized to
-- C_FAMILY may be generated, depending on whether
-- C_FAMILY supports the needed primtives.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate_f.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2006-12-11
-- ^^^^^^
-- First Version, derived from or_gate by BLT
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate_f is
generic (
C_OR_WIDTH : natural := 17;
C_BUS_WIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate_f;
architecture imp of or_gate_f is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity proc_common_v4_0.or_muxcy_f
generic map (
C_NUM_BITS => C_OR_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end architecture imp;
| apache-2.0 | 776aeaa197770ce50e49426f38ee9a0d | 0.405971 | 5.147504 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_tlb.vhd | 1 | 28,978 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 600e3ded605dca78ca84e935ce1d3811 | 0.94589 | 1.84585 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/exception_registers_gti.vhd | 1 | 31,248 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | 55c582a9c8f5ac08eadc5cb9e80d8e0c | 0.945276 | 1.837469 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/dc_ss_fwft.vhd | 5 | 9,156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
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`protect end_protected
| apache-2.0 | 47025be63baf4ac7e82c6210651b3782 | 0.923547 | 1.900768 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/asap-alap-random/arf_alap.vhd | 1 | 2,483 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:37)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_alap_entity;
ARCHITECTURE arf_alap_description OF arf_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := register4 + register3;
WHEN "00000011" =>
register1 := register1 + 6;
register2 := register2 + 8;
WHEN "00000100" =>
register3 := register1 * 10;
register4 := register2 * 12;
register1 := register1 * 14;
register2 := register2 * 16;
WHEN "00000101" =>
register3 := register4 + register3;
register1 := register2 + register1;
WHEN "00000110" =>
register2 := register3 * 18;
register4 := register1 * 20;
register5 := input5 * 21;
register6 := input6 * 22;
register3 := register3 * 24;
register1 := register1 * 26;
register7 := input7 * 27;
register8 := input8 * 28;
WHEN "00000111" =>
register2 := register4 + register2;
register4 := register6 + register5;
register1 := register1 + register3;
register3 := register8 + register7;
WHEN "00001000" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_alap_description; | gpl-3.0 | 59a9df8a30e34a1e3b1ee4bdb93bdfab | 0.659686 | 3.107635 | false | false | false | false |
freecores/twofish | vhdl/twofish.vhd | 1 | 183,136 | -- Twofish.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
-- description : this file includes all the components necessary to perform symmetric encryption
-- with the twofish 128 bit block cipher. Within there are four main parts of the file.
-- the first part is the twofish crypto primitives which are independent of the key
-- input length, the second part is the 128 bit key input components, the third part
-- is the 192 bit key components and finaly the 256 bit key input components
--
-- ====================================================== --
-- ====================================================== --
-- --
-- first part: key input independent component primitives --
-- --
-- ====================================================== --
-- ====================================================== --
--
-- q0
--
library ieee;
Use ieee.std_logic_1164.all;
entity q0 is
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end q0;
architecture q0_arch of q0 is
-- declaring internal signals
signal a0,b0,
a1,b1,
a2,b2,
a3,b3,
a4,b4 : std_logic_vector(3 downto 0);
signal b0_ror4,
a0_times_8,
b2_ror4,
a2_times_8 : std_logic_vector(3 downto 0);
-- beginning of the architecture description
begin
-- little endian
b0 <= in_q0(3 downto 0);
a0 <= in_q0(7 downto 4);
a1 <= a0 XOR b0;
-- signal b0 is ror4'ed by 1 bit
b0_ror4(2 downto 0) <= b0(3 downto 1);
b0_ror4(3) <= b0(0);
-- 8*a0 = 2^3*a0= a0 << 3
a0_times_8(2 downto 0) <= (others => '0');
a0_times_8(3) <= a0(0);
b1 <= a0 XOR b0_ror4 XOR a0_times_8;
--
-- t0 table
--
with a1 select
a2 <= "1000" when "0000", -- 8
"0001" when "0001", -- 1
"0111" when "0010", -- 7
"1101" when "0011", -- D
"0110" when "0100", -- 6
"1111" when "0101", -- F
"0011" when "0110", -- 3
"0010" when "0111", -- 2
"0000" when "1000", -- 0
"1011" when "1001", -- B
"0101" when "1010", -- 5
"1001" when "1011", -- 9
"1110" when "1100", -- E
"1100" when "1101", -- C
"1010" when "1110", -- A
"0100" when others; -- 4
--
-- t1 table
--
with b1 select
b2 <= "1110" when "0000", -- E
"1100" when "0001", -- C
"1011" when "0010", -- B
"1000" when "0011", -- 8
"0001" when "0100", -- 1
"0010" when "0101", -- 2
"0011" when "0110", -- 3
"0101" when "0111", -- 5
"1111" when "1000", -- F
"0100" when "1001", -- 4
"1010" when "1010", -- A
"0110" when "1011", -- 6
"0111" when "1100", -- 7
"0000" when "1101", -- 0
"1001" when "1110", -- 9
"1101" when others; -- D
a3 <= a2 XOR b2;
-- signal b2 is ror4'ed by 1 bit
b2_ror4(2 downto 0) <= b2(3 downto 1);
b2_ror4(3) <= b2(0);
-- 8*a2 = 2^3*a2=a2<<3
a2_times_8(2 downto 0) <= (others => '0');
a2_times_8(3) <= a2(0);
b3 <= a2 XOR b2_ror4 XOR a2_times_8;
--
-- t0 table
--
with a3 select
a4 <= "1011" when "0000", -- B
"1010" when "0001", -- A
"0101" when "0010", -- 5
"1110" when "0011", -- E
"0110" when "0100", -- 6
"1101" when "0101", -- D
"1001" when "0110", -- 9
"0000" when "0111", -- 0
"1100" when "1000", -- C
"1000" when "1001", -- 8
"1111" when "1010", -- F
"0011" when "1011", -- 3
"0010" when "1100", -- 2
"0100" when "1101", -- 4
"0111" when "1110", -- 7
"0001" when others; -- 1
--
-- t1 table
--
with b3 select
b4 <= "1101" when "0000", -- D
"0111" when "0001", -- 7
"1111" when "0010", -- F
"0100" when "0011", -- 4
"0001" when "0100", -- 1
"0010" when "0101", -- 2
"0110" when "0110", -- 6
"1110" when "0111", -- E
"1001" when "1000", -- 9
"1011" when "1001", -- B
"0011" when "1010", -- 3
"0000" when "1011", -- 0
"1000" when "1100", -- 8
"0101" when "1101", -- 5
"1100" when "1110", -- C
"1010" when others; -- A
-- the output of q0
out_q0 <= b4 & a4;
end q0_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- q1
--
library ieee;
Use ieee.std_logic_1164.all;
entity q1 is
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end q1;
-- architecture description
architecture q1_arch of q1 is
-- declaring the internal signals
signal a0,b0,
a1,b1,
a2,b2,
a3,b3,
a4,b4 : std_logic_vector(3 downto 0);
signal b0_ror4,
a0_times_8,
b2_ror4,
a2_times_8 : std_logic_vector(3 downto 0);
-- begin the architecture description
begin
-- little endian
b0 <= in_q1(3 downto 0);
a0 <= in_q1(7 downto 4);
a1 <= a0 XOR b0;
-- signal b0 is ror4'ed by 1 bit
b0_ror4(2 downto 0) <= b0(3 downto 1);
b0_ror4(3) <= b0(0);
-- 8*a0 = 2^3*a0=a0<<3
a0_times_8(2 downto 0) <= (others => '0');
a0_times_8(3) <= a0(0);
b1 <= a0 XOR b0_ror4 XOR a0_times_8;
--
-- t0 table
--
with a1 select
a2 <= "0010" when "0000", -- 2
"1000" when "0001", -- 8
"1011" when "0010", -- b
"1101" when "0011", -- d
"1111" when "0100", -- f
"0111" when "0101", -- 7
"0110" when "0110", -- 6
"1110" when "0111", -- e
"0011" when "1000", -- 3
"0001" when "1001", -- 1
"1001" when "1010", -- 9
"0100" when "1011", -- 4
"0000" when "1100", -- 0
"1010" when "1101", -- a
"1100" when "1110", -- c
"0101" when others; -- 5
--
-- t1 table
--
with b1 select
b2 <= "0001" when "0000", -- 1
"1110" when "0001", -- e
"0010" when "0010", -- 2
"1011" when "0011", -- b
"0100" when "0100", -- 4
"1100" when "0101", -- c
"0011" when "0110", -- 3
"0111" when "0111", -- 7
"0110" when "1000", -- 6
"1101" when "1001", -- d
"1010" when "1010", -- a
"0101" when "1011", -- 5
"1111" when "1100", -- f
"1001" when "1101", -- 9
"0000" when "1110", -- 0
"1000" when others; -- 8
a3 <= a2 XOR b2;
-- signal b2 is ror4'ed by 1 bit
b2_ror4(2 downto 0) <= b2(3 downto 1);
b2_ror4(3) <= b2(0);
-- 8*a2 = 2^3*a2=a2<<3
a2_times_8(2 downto 0) <= (others => '0');
a2_times_8(3) <= a2(0);
b3 <= a2 XOR b2_ror4 XOR a2_times_8;
--
-- t0 table
--
with a3 select
a4 <= "0100" when "0000", -- 4
"1100" when "0001", -- c
"0111" when "0010", -- 7
"0101" when "0011", -- 5
"0001" when "0100", -- 1
"0110" when "0101", -- 6
"1001" when "0110", -- 9
"1010" when "0111", -- a
"0000" when "1000", -- 0
"1110" when "1001", -- e
"1101" when "1010", -- d
"1000" when "1011", -- 8
"0010" when "1100", -- 2
"1011" when "1101", -- b
"0011" when "1110", -- 3
"1111" when others; -- f
--
-- t1 table
--
with b3 select
b4 <= "1011" when "0000", -- b
"1001" when "0001", -- 9
"0101" when "0010", -- 5
"0001" when "0011", -- 1
"1100" when "0100", -- c
"0011" when "0101", -- 3
"1101" when "0110", -- d
"1110" when "0111", -- e
"0110" when "1000", -- 6
"0100" when "1001", -- 4
"0111" when "1010", -- 7
"1111" when "1011", -- f
"0010" when "1100", -- 2
"0000" when "1101", -- 0
"1000" when "1110", -- 8
"1010" when others; -- a
-- output of q1
out_q1 <= b4 & a4;
end q1_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- ef multiplier
--
library ieee;
use ieee.std_logic_1164.all;
entity mul_ef is
port (
in_ef : in std_logic_vector(7 downto 0);
out_ef : out std_logic_vector(7 downto 0)
);
end mul_ef;
architecture mul_ef_arch of mul_ef is
begin
out_ef(0) <= in_ef(2) XOR in_ef(1) XOR in_ef(0);
out_ef(1) <= in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0);
out_ef(2) <= in_ef(4) XOR in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0);
out_ef(3) <= in_ef(5) XOR in_ef(4) XOR in_ef(3) XOR in_ef(0);
out_ef(4) <= in_ef(6) XOR in_ef(5) XOR in_ef(4) XOR in_ef(1);
out_ef(5) <= in_ef(7) XOR in_ef(6) XOR in_ef(5) XOR in_ef(1) XOR in_ef(0);
out_ef(6) <= in_ef(7) XOR in_ef(6) XOR in_ef(0);
out_ef(7) <= in_ef(7) XOR in_ef(1) XOR in_ef(0);
end mul_ef_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- 5b multiplier
--
library ieee;
use ieee.std_logic_1164.all;
entity mul_5b is
port (
in_5b : in std_logic_vector(7 downto 0);
out_5b : out std_logic_vector(7 downto 0)
);
end mul_5b;
architecture mul_5b_arch of mul_5b is
begin
out_5b(0) <= in_5b(2) XOR in_5b(0);
out_5b(1) <= in_5b(3) XOR in_5b(1) XOR in_5b(0);
out_5b(2) <= in_5b(4) XOR in_5b(2) XOR in_5b(1);
out_5b(3) <= in_5b(5) XOR in_5b(3) XOR in_5b(0);
out_5b(4) <= in_5b(6) XOR in_5b(4) XOR in_5b(1) XOR in_5b(0);
out_5b(5) <= in_5b(7) XOR in_5b(5) XOR in_5b(1);
out_5b(6) <= in_5b(6) XOR in_5b(0);
out_5b(7) <= in_5b(7) XOR in_5b(1);
end mul_5b_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- mds
--
library ieee;
use ieee.std_logic_1164.all;
entity mds is
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end mds;
-- architecture description of mds component
architecture mds_arch of mds is
-- we declare the multiplier by ef
component mul_ef
port (
in_ef : in std_logic_vector(7 downto 0);
out_ef : out std_logic_vector(7 downto 0)
);
end component;
-- we declare the multiplier by 5b
component mul_5b
port (
in_5b : in std_logic_vector(7 downto 0);
out_5b : out std_logic_vector(7 downto 0)
);
end component;
-- we declare the multiplier's outputs
signal y0_ef, y0_5b,
y1_ef, y1_5b,
y2_ef, y2_5b,
y3_ef, y3_5b : std_logic_vector(7 downto 0);
begin
-- we perform the signal multiplication
y0_times_ef: mul_ef
port map (
in_ef => y0,
out_ef => y0_ef
);
y0_times_5b: mul_5b
port map (
in_5b => y0,
out_5b => y0_5b
);
y1_times_ef: mul_ef
port map (
in_ef => y1,
out_ef => y1_ef
);
y1_times_5b: mul_5b
port map (
in_5b => y1,
out_5b => y1_5b
);
y2_times_ef: mul_ef
port map (
in_ef => y2,
out_ef => y2_ef
);
y2_times_5b: mul_5b
port map (
in_5b => y2,
out_5b => y2_5b
);
y3_times_ef: mul_ef
port map (
in_ef => y3,
out_ef => y3_ef
);
y3_times_5b: mul_5b
port map (
in_5b => y3,
out_5b => y3_5b
);
-- we perform the addition of the partial results in order to receive
-- the table output
-- z0 = y0*01 + y1*ef + y2*5b + y3*5b , opoy + bazoyme XOR
z0 <= y0 XOR y1_ef XOR y2_5b XOR y3_5b;
-- z1 = y0*5b + y1*ef + y2*ef + y3*01
z1 <= y0_5b XOR y1_ef XOR y2_ef XOR y3;
-- z2 = y0*ef + y1*5b + y2*01 +y3*ef
z2 <= y0_ef XOR y1_5b XOR y2 XOR y3_ef;
-- z3 = y0*ef + y1*01 + y2*ef + y3*5b
z3 <= y0_ef XOR y1 XOR y2_ef XOR y3_5b;
end mds_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- 1 bit adder
--
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end adder;
architecture adder_arch of adder is
begin
out_adder <= in_carry_adder XOR in1_adder XOR in2_adder;
out_carry_adder <= (in_carry_adder AND (in1_adder XOR in2_adder)) OR (in1_adder AND in2_adder);
end adder_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- pht
--
library ieee;
use ieee.std_logic_1164.all;
entity pht is
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end pht;
-- architecture description
architecture pht_arch of pht is
-- we declare internal signals
signal intermediate_carry1,
intermediate_carry2,
to_upper_out : std_logic_vector(31 downto 0);
signal zero : std_logic;
component adder
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end component;
begin
-- initializing zero signal
zero <= '0';
-- instantiating the upper adder of 32 bits
up_adder: for i in 0 to 31 generate
adder_one: if (i=0) generate
the_adder: adder
port map (
in1_adder => up_in_pht(0),
in2_adder => down_in_pht(0),
in_carry_adder => zero,
out_adder => to_upper_out(0),
out_carry_adder => intermediate_carry1(0)
);
end generate adder_one;
rest_adders: if (i>0) generate
next_adder: adder
port map (
in1_adder => up_in_pht(i),
in2_adder => down_in_pht(i),
in_carry_adder => intermediate_carry1(i-1),
out_adder => to_upper_out(i),
out_carry_adder => intermediate_carry1(i)
);
end generate rest_adders;
end generate up_adder;
intermediate_carry1(31) <= '0';
-- receiving the upper pht output
up_out_pht <= to_upper_out;
-- instantiating the lower adder of 32 bits
down_adder: for i in 0 to 31 generate
adder_one_1: if (i=0) generate
the_adder_1: adder
port map (
in1_adder => down_in_pht(0),
in2_adder => to_upper_out(0),
in_carry_adder => zero,
out_adder => down_out_pht(0),
out_carry_adder => intermediate_carry2(0)
);
end generate adder_one_1;
rest_adders_1: if (i>0) generate
next_adder_1: adder
port map (
in1_adder => down_in_pht(i),
in2_adder => to_upper_out(i),
in_carry_adder => intermediate_carry2(i-1),
out_adder => down_out_pht(i),
out_carry_adder => intermediate_carry2(i)
);
end generate rest_adders_1;
end generate down_adder;
intermediate_carry2(31) <= '0';
end pht_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 01
--
library ieee;
use ieee.std_logic_1164.all;
entity mul01 is
port (
in_mul01 : in std_logic_vector(7 downto 0);
out_mul01 : out std_logic_vector(7 downto 0)
);
end mul01;
architecture mul01_arch of mul01 is
begin
out_mul01 <= in_mul01;
end mul01_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by a4
--
library ieee;
use ieee.std_logic_1164.all;
entity mula4 is
port (
in_mula4 : in std_logic_vector(7 downto 0);
out_mula4 : out std_logic_vector(7 downto 0)
);
end mula4;
architecture mula4_arch of mula4 is
begin
out_mula4(0) <= in_mula4(7) xor in_mula4(1);
out_mula4(1) <= in_mula4(2);
out_mula4(2) <= in_mula4(7) xor in_mula4(3) xor in_mula4(1) xor in_mula4(0);
out_mula4(3) <= in_mula4(7) xor in_mula4(4) xor in_mula4(2);
out_mula4(4) <= in_mula4(5) xor in_mula4(3);
out_mula4(5) <= in_mula4(6) xor in_mula4(4) xor in_mula4(0);
out_mula4(6) <= in_mula4(5);
out_mula4(7) <= in_mula4(6) xor in_mula4(0);
end mula4_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 55
--
library ieee;
use ieee.std_logic_1164.all;
entity mul55 is
port (
in_mul55 : in std_logic_vector(7 downto 0);
out_mul55 : out std_logic_vector(7 downto 0)
);
end mul55;
architecture mul55_arch of mul55 is
begin
out_mul55(0) <= in_mul55(7) xor in_mul55(6) xor in_mul55(2) xor in_mul55(0);
out_mul55(1) <= in_mul55(7) xor in_mul55(3) xor in_mul55(1);
out_mul55(2) <= in_mul55(7) xor in_mul55(6) xor in_mul55(4) xor in_mul55(0);
out_mul55(3) <= in_mul55(6) xor in_mul55(5) xor in_mul55(2) xor in_mul55(1);
out_mul55(4) <= in_mul55(7) xor in_mul55(6) xor in_mul55(3) xor in_mul55(2) xor in_mul55(0);
out_mul55(5) <= in_mul55(7) xor in_mul55(4) xor in_mul55(3) xor in_mul55(1);
out_mul55(6) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(4) xor in_mul55(0);
out_mul55(7) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(1);
end mul55_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 87
--
library ieee;
use ieee.std_logic_1164.all;
entity mul87 is
port (
in_mul87 : in std_logic_vector(7 downto 0);
out_mul87 : out std_logic_vector(7 downto 0)
);
end mul87;
architecture mul87_arch of mul87 is
begin
out_mul87(0) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1) xor in_mul87(0);
out_mul87(1) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(1) xor in_mul87(0);
out_mul87(2) <= in_mul87(2) xor in_mul87(0);
out_mul87(3) <= in_mul87(7) xor in_mul87(5);
out_mul87(4) <= in_mul87(6);
out_mul87(5) <= in_mul87(7);
out_mul87(6) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1);
out_mul87(7) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(0);
end mul87_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 5a
--
library ieee;
use ieee.std_logic_1164.all;
entity mul5a is
port (
in_mul5a : in std_logic_vector(7 downto 0);
out_mul5a : out std_logic_vector(7 downto 0)
);
end mul5a;
architecture mul5a_arch of mul5a is
begin
out_mul5a(0) <= in_mul5a(7) xor in_mul5a(5) xor in_mul5a(2);
out_mul5a(1) <= in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);
out_mul5a(2) <= in_mul5a(5) xor in_mul5a(4) xor in_mul5a(2) xor in_mul5a(1);
out_mul5a(3) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);
out_mul5a(4) <= in_mul5a(7) xor in_mul5a(4) xor in_mul5a(1) xor in_mul5a(0);
out_mul5a(5) <= in_mul5a(5) xor in_mul5a(2) xor in_mul5a(1);
out_mul5a(6) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(5) xor in_mul5a(3) xor in_mul5a(0);
out_mul5a(7) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(4) xor in_mul5a(1);
end mul5a_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 58
--
library ieee;
use ieee.std_logic_1164.all;
entity mul58 is
port (
in_mul58 : in std_logic_vector(7 downto 0);
out_mul58 : out std_logic_vector(7 downto 0)
);
end mul58;
architecture mul58_arch of mul58 is
begin
out_mul58(0) <= in_mul58(5) xor in_mul58(2);
out_mul58(1) <= in_mul58(6) xor in_mul58(3);
out_mul58(2) <= in_mul58(7) xor in_mul58(5) xor in_mul58(4) xor in_mul58(2);
out_mul58(3) <= in_mul58(6) xor in_mul58(3) xor in_mul58(2) xor in_mul58(0);
out_mul58(4) <= in_mul58(7) xor in_mul58(4) xor in_mul58(3) xor in_mul58(1) xor in_mul58(0);
out_mul58(5) <= in_mul58(5) xor in_mul58(4) xor in_mul58(2) xor in_mul58(1);
out_mul58(6) <= in_mul58(6) xor in_mul58(3) xor in_mul58(0);
out_mul58(7) <= in_mul58(7) xor in_mul58(4) xor in_mul58(1);
end mul58_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by db
--
library ieee;
use ieee.std_logic_1164.all;
entity muldb is
port (
in_muldb : in std_logic_vector(7 downto 0);
out_muldb : out std_logic_vector(7 downto 0)
);
end muldb;
architecture muldb_arch of muldb is
begin
out_muldb(0) <= in_muldb(7) xor in_muldb(6) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
out_muldb(1) <= in_muldb(7) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
out_muldb(2) <= in_muldb(7) xor in_muldb(6) xor in_muldb(5) xor in_muldb(4);
out_muldb(3) <= in_muldb(5) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
out_muldb(4) <= in_muldb(6) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
out_muldb(5) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1);
out_muldb(6) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(1) xor in_muldb(0);
out_muldb(7) <= in_muldb(6) xor in_muldb(5) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
end muldb_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 9e
--
library ieee;
use ieee.std_logic_1164.all;
entity mul9e is
port (
in_mul9e : in std_logic_vector(7 downto 0);
out_mul9e : out std_logic_vector(7 downto 0)
);
end mul9e;
architecture mul9e_arch of mul9e is
begin
out_mul9e(0) <= in_mul9e(6) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(1);
out_mul9e(1) <= in_mul9e(7) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(0);
out_mul9e(2) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(0);
out_mul9e(3) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(0);
out_mul9e(4) <= in_mul9e(6) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(1) xor in_mul9e(0);
out_mul9e(5) <= in_mul9e(7) xor in_mul9e(6) xor in_mul9e(5) xor in_mul9e(2) xor in_mul9e(1);
out_mul9e(6) <= in_mul9e(7) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(1);
out_mul9e(7) <= in_mul9e(5) xor in_mul9e(3) xor in_mul9e(2) xor in_mul9e(0);
end mul9e_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 56
--
library ieee;
use ieee.std_logic_1164.all;
entity mul56 is
port (
in_mul56 : in std_logic_vector(7 downto 0);
out_mul56 : out std_logic_vector(7 downto 0)
);
end mul56;
architecture mul56_arch of mul56 is
begin
out_mul56(0) <= in_mul56(6) xor in_mul56(2);
out_mul56(1) <= in_mul56(7) xor in_mul56(3) xor in_mul56(0);
out_mul56(2) <= in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(1) xor in_mul56(0);
out_mul56(3) <= in_mul56(7) xor in_mul56(6) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1);
out_mul56(4) <= in_mul56(7) xor in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(0);
out_mul56(5) <= in_mul56(7) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1);
out_mul56(6) <= in_mul56(4) xor in_mul56(0);
out_mul56(7) <= in_mul56(5) xor in_mul56(1);
end mul56_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 82
--
library ieee;
use ieee.std_logic_1164.all;
entity mul82 is
port (
in_mul82 : in std_logic_vector(7 downto 0);
out_mul82 : out std_logic_vector(7 downto 0)
);
end mul82;
architecture mul82_arch of mul82 is
begin
out_mul82(0) <= in_mul82(7) xor in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1);
out_mul82(1) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0);
out_mul82(2) <= in_mul82(6);
out_mul82(3) <= in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1);
out_mul82(4) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2);
out_mul82(5) <= in_mul82(7) xor in_mul82(5) xor in_mul82(3);
out_mul82(6) <= in_mul82(7) xor in_mul82(5) xor in_mul82(4) xor in_mul82(3) xor in_mul82(1);
out_mul82(7) <= in_mul82(6) xor in_mul82(5) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0);
end mul82_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by f3
--
library ieee;
use ieee.std_logic_1164.all;
entity mulf3 is
port (
in_mulf3 : in std_logic_vector(7 downto 0);
out_mulf3 : out std_logic_vector(7 downto 0)
);
end mulf3;
architecture mulf3_arch of mulf3 is
begin
out_mulf3(0) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0);
out_mulf3(1) <= in_mulf3(7) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0);
out_mulf3(2) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3);
out_mulf3(3) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(2) xor in_mulf3(1);
out_mulf3(4) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(0);
out_mulf3(5) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3) xor in_mulf3(1) xor in_mulf3(0);
out_mulf3(6) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(0);
out_mulf3(7) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(1) xor in_mulf3(0);
end mulf3_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 1e
--
library ieee;
use ieee.std_logic_1164.all;
entity mul1e is
port (
in_mul1e : in std_logic_vector(7 downto 0);
out_mul1e : out std_logic_vector(7 downto 0)
);
end mul1e;
architecture mul1e_arch of mul1e is
begin
out_mul1e(0) <= in_mul1e(5) xor in_mul1e(4);
out_mul1e(1) <= in_mul1e(6) xor in_mul1e(5) xor in_mul1e(0);
out_mul1e(2) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(5) xor in_mul1e(4) xor in_mul1e(1) xor in_mul1e(0);
out_mul1e(3) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(4) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0);
out_mul1e(4) <= in_mul1e(7) xor in_mul1e(5) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0);
out_mul1e(5) <= in_mul1e(6) xor in_mul1e(4) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1);
out_mul1e(6) <= in_mul1e(7) xor in_mul1e(3) xor in_mul1e(2);
out_mul1e(7) <= in_mul1e(4) xor in_mul1e(3);
end mul1e_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by c6
--
library ieee;
use ieee.std_logic_1164.all;
entity mulc6 is
port (
in_mulc6 : in std_logic_vector(7 downto 0);
out_mulc6 : out std_logic_vector(7 downto 0)
);
end mulc6;
architecture mulc6_arch of mulc6 is
begin
out_mulc6(0) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1);
out_mulc6(1) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(0);
out_mulc6(2) <= in_mulc6(7) xor in_mulc6(2) xor in_mulc6(0);
out_mulc6(3) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(2);
out_mulc6(4) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(3);
out_mulc6(5) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4);
out_mulc6(6) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0);
out_mulc6(7) <= in_mulc6(7) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0);
end mulc6_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 68
--
library ieee;
use ieee.std_logic_1164.all;
entity mul68 is
port (
in_mul68 : in std_logic_vector(7 downto 0);
out_mul68 : out std_logic_vector(7 downto 0)
);
end mul68;
architecture mul68_arch of mul68 is
begin
out_mul68(0) <= in_mul68(7) xor in_mul68(6) xor in_mul68(4) xor in_mul68(3) xor in_mul68(2);
out_mul68(1) <= in_mul68(7) xor in_mul68(5) xor in_mul68(4) xor in_mul68(3);
out_mul68(2) <= in_mul68(7) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2);
out_mul68(3) <= in_mul68(7) xor in_mul68(2) xor in_mul68(0);
out_mul68(4) <= in_mul68(3) xor in_mul68(1);
out_mul68(5) <= in_mul68(4) xor in_mul68(2) xor in_mul68(0);
out_mul68(6) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(4) xor in_mul68(2) xor in_mul68(1) xor in_mul68(0);
out_mul68(7) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2) xor in_mul68(1);
end mul68_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by e5
--
library ieee;
use ieee.std_logic_1164.all;
entity mule5 is
port (
in_mule5 : in std_logic_vector(7 downto 0);
out_mule5 : out std_logic_vector(7 downto 0)
);
end mule5;
architecture mule5_arch of mule5 is
begin
out_mule5(0) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(1) xor in_mule5(0);
out_mule5(1) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(2) xor in_mule5(1);
out_mule5(2) <= in_mule5(3) xor in_mule5(1) xor in_mule5(0);
out_mule5(3) <= in_mule5(6);
out_mule5(4) <= in_mule5(7);
out_mule5(5) <= in_mule5(0);
out_mule5(6) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(0);
out_mule5(7) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(1) xor in_mule5(0);
end mule5_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 02
--
library ieee;
use ieee.std_logic_1164.all;
entity mul02 is
port (
in_mul02 : in std_logic_vector(7 downto 0);
out_mul02 : out std_logic_vector(7 downto 0)
);
end mul02;
architecture mul02_arch of mul02 is
begin
out_mul02(0) <= in_mul02(7);
out_mul02(1) <= in_mul02(0);
out_mul02(2) <= in_mul02(7) xor in_mul02(1);
out_mul02(3) <= in_mul02(7) xor in_mul02(2);
out_mul02(4) <= in_mul02(3);
out_mul02(5) <= in_mul02(4);
out_mul02(6) <= in_mul02(7) xor in_mul02(5);
out_mul02(7) <= in_mul02(6);
end mul02_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by a1
--
library ieee;
use ieee.std_logic_1164.all;
entity mula1 is
port (
in_mula1 : in std_logic_vector(7 downto 0);
out_mula1 : out std_logic_vector(7 downto 0)
);
end mula1;
architecture mula1_arch of mula1 is
begin
out_mula1(0) <= in_mula1(7) xor in_mula1(6) xor in_mula1(1) xor in_mula1(0);
out_mula1(1) <= in_mula1(7) xor in_mula1(2) xor in_mula1(1);
out_mula1(2) <= in_mula1(7) xor in_mula1(6) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1);
out_mula1(3) <= in_mula1(6) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1);
out_mula1(4) <= in_mula1(7) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2);
out_mula1(5) <= in_mula1(6) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(0);
out_mula1(6) <= in_mula1(5) xor in_mula1(4);
out_mula1(7) <= in_mula1(6) xor in_mula1(5) xor in_mula1(0);
end mula1_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by fc
--
library ieee;
use ieee.std_logic_1164.all;
entity mulfc is
port (
in_mulfc : in std_logic_vector(7 downto 0);
out_mulfc : out std_logic_vector(7 downto 0)
);
end mulfc;
architecture mulfc_arch of mulfc is
begin
out_mulfc(0) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1);
out_mulfc(1) <= in_mulfc(6) xor in_mulfc(3) xor in_mulfc(2);
out_mulfc(2) <= in_mulfc(5) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0);
out_mulfc(3) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(0);
out_mulfc(4) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0);
out_mulfc(5) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0);
out_mulfc(6) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(3) xor in_mulfc(0);
out_mulfc(7) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0);
end mulfc_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by c1
--
library ieee;
use ieee.std_logic_1164.all;
entity mulc1 is
port (
in_mulc1 : in std_logic_vector(7 downto 0);
out_mulc1 : out std_logic_vector(7 downto 0)
);
end mulc1;
architecture mulc1_arch of mulc1 is
begin
out_mulc1(0) <= in_mulc1(7) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
out_mulc1(1) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1);
out_mulc1(2) <= in_mulc1(6) xor in_mulc1(1);
out_mulc1(3) <= in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(1);
out_mulc1(4) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(2);
out_mulc1(5) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3);
out_mulc1(6) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
out_mulc1(7) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
end mulc1_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 47
--
library ieee;
use ieee.std_logic_1164.all;
entity mul47 is
port (
in_mul47 : in std_logic_vector(7 downto 0);
out_mul47 : out std_logic_vector(7 downto 0)
);
end mul47;
architecture mul47_arch of mul47 is
begin
out_mul47(0) <= in_mul47(4) xor in_mul47(2) xor in_mul47(0);
out_mul47(1) <= in_mul47(5) xor in_mul47(3) xor in_mul47(1) xor in_mul47(0);
out_mul47(2) <= in_mul47(6) xor in_mul47(1) xor in_mul47(0);
out_mul47(3) <= in_mul47(7) xor in_mul47(4) xor in_mul47(1);
out_mul47(4) <= in_mul47(5) xor in_mul47(2);
out_mul47(5) <= in_mul47(6) xor in_mul47(3);
out_mul47(6) <= in_mul47(7) xor in_mul47(2) xor in_mul47(0);
out_mul47(7) <= in_mul47(3) xor in_mul47(1);
end mul47_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by ae
--
library ieee;
use ieee.std_logic_1164.all;
entity mulae is
port (
in_mulae : in std_logic_vector(7 downto 0);
out_mulae : out std_logic_vector(7 downto 0)
);
end mulae;
architecture mulae_arch of mulae is
begin
out_mulae(0) <= in_mulae(7) xor in_mulae(5) xor in_mulae(1);
out_mulae(1) <= in_mulae(6) xor in_mulae(2) xor in_mulae(0);
out_mulae(2) <= in_mulae(5) xor in_mulae(3) xor in_mulae(0);
out_mulae(3) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(4) xor in_mulae(0);
out_mulae(4) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(1);
out_mulae(5) <= in_mulae(7) xor in_mulae(6) xor in_mulae(2) xor in_mulae(0);
out_mulae(6) <= in_mulae(5) xor in_mulae(3);
out_mulae(7) <= in_mulae(6) xor in_mulae(4) xor in_mulae(0);
end mulae_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 3d
--
library ieee;
use ieee.std_logic_1164.all;
entity mul3d is
port (
in_mul3d : in std_logic_vector(7 downto 0);
out_mul3d : out std_logic_vector(7 downto 0)
);
end mul3d;
architecture mul3d_arch of mul3d is
begin
out_mul3d(0) <= in_mul3d(4) xor in_mul3d(3) xor in_mul3d(0);
out_mul3d(1) <= in_mul3d(5) xor in_mul3d(4) xor in_mul3d(1);
out_mul3d(2) <= in_mul3d(6) xor in_mul3d(5) xor in_mul3d(4) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(0);
out_mul3d(3) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(5) xor in_mul3d(1) xor in_mul3d(0);
out_mul3d(4) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0);
out_mul3d(5) <= in_mul3d(7) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0);
out_mul3d(6) <= in_mul3d(2) xor in_mul3d(1);
out_mul3d(7) <= in_mul3d(3) xor in_mul3d(2);
end mul3d_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 19
--
library ieee;
use ieee.std_logic_1164.all;
entity mul19 is
port (
in_mul19 : in std_logic_vector(7 downto 0);
out_mul19 : out std_logic_vector(7 downto 0)
);
end mul19;
architecture mul19_arch of mul19 is
begin
out_mul19(0) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(0);
out_mul19(1) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(1);
out_mul19(2) <= in_mul19(5) xor in_mul19(4) xor in_mul19(2);
out_mul19(3) <= in_mul19(7) xor in_mul19(4) xor in_mul19(3) xor in_mul19(0);
out_mul19(4) <= in_mul19(5) xor in_mul19(4) xor in_mul19(1) xor in_mul19(0);
out_mul19(5) <= in_mul19(6) xor in_mul19(5) xor in_mul19(2) xor in_mul19(1);
out_mul19(6) <= in_mul19(5) xor in_mul19(4) xor in_mul19(3) xor in_mul19(2);
out_mul19(7) <= in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(3);
end mul19_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- multiplier by 03
--
library ieee;
use ieee.std_logic_1164.all;
entity mul03 is
port (
in_mul03 : in std_logic_vector(7 downto 0);
out_mul03 : out std_logic_vector(7 downto 0)
);
end mul03;
architecture mul03_arch of mul03 is
begin
out_mul03(0) <= in_mul03(7) xor in_mul03(0);
out_mul03(1) <= in_mul03(1) xor in_mul03(0);
out_mul03(2) <= in_mul03(7) xor in_mul03(2) xor in_mul03(1);
out_mul03(3) <= in_mul03(7) xor in_mul03(3) xor in_mul03(2);
out_mul03(4) <= in_mul03(4) xor in_mul03(3);
out_mul03(5) <= in_mul03(5) xor in_mul03(4);
out_mul03(6) <= in_mul03(7) xor in_mul03(6) xor in_mul03(5);
out_mul03(7) <= in_mul03(7) xor in_mul03(6);
end mul03_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish data input is the component
-- that transforms the data input to the
-- first round to the wanted form as is
-- described in the twofish prototype
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_data_input is
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end twofish_data_input;
architecture twofish_data_input_arch of twofish_data_input is
-- we declare internal signals
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6,
byte7, byte8, byte9,
byte10, byte11, byte12,
byte13, byte14, byte15 : std_logic_vector(7 downto 0);
signal P0, P1, P2, P3 : std_logic_vector(31 downto 0);
begin
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte15 <= in_tdi(7 downto 0);
byte14 <= in_tdi(15 downto 8);
byte13 <= in_tdi(23 downto 16);
byte12 <= in_tdi(31 downto 24);
byte11 <= in_tdi(39 downto 32);
byte10 <= in_tdi(47 downto 40);
byte9 <= in_tdi(55 downto 48);
byte8 <= in_tdi(63 downto 56);
byte7 <= in_tdi(71 downto 64);
byte6 <= in_tdi(79 downto 72);
byte5 <= in_tdi(87 downto 80);
byte4 <= in_tdi(95 downto 88);
byte3 <= in_tdi(103 downto 96);
byte2 <= in_tdi(111 downto 104);
byte1 <= in_tdi(119 downto 112);
byte0 <= in_tdi(127 downto 120);
-- we rearrange the bytes and send them to exit
P0 <= byte3 & byte2 & byte1 & byte0;
P1 <= byte7 & byte6 & byte5 & byte4;
P2 <= byte11 & byte10 & byte9 & byte8;
P3 <= byte15 & byte14 & byte13 & byte12;
out_tdi <= P0 & P1 & P2 & P3;
end twofish_data_input_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish data output is the component
-- that transforms the data output from the
-- 16th round to the wanted form as is
-- described in the twofish prototype
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_data_output is
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end twofish_data_output;
architecture twofish_data_output_arch of twofish_data_output is
-- we declare internal signals
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6,
byte7, byte8, byte9,
byte10, byte11, byte12,
byte13, byte14, byte15 : std_logic_vector(7 downto 0);
signal C0, C1, C2, C3 : std_logic_vector(31 downto 0);
begin
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte15 <= in_tdo(7 downto 0);
byte14 <= in_tdo(15 downto 8);
byte13 <= in_tdo(23 downto 16);
byte12 <= in_tdo(31 downto 24);
byte11 <= in_tdo(39 downto 32);
byte10 <= in_tdo(47 downto 40);
byte9 <= in_tdo(55 downto 48);
byte8 <= in_tdo(63 downto 56);
byte7 <= in_tdo(71 downto 64);
byte6 <= in_tdo(79 downto 72);
byte5 <= in_tdo(87 downto 80);
byte4 <= in_tdo(95 downto 88);
byte3 <= in_tdo(103 downto 96);
byte2 <= in_tdo(111 downto 104);
byte1 <= in_tdo(119 downto 112);
byte0 <= in_tdo(127 downto 120);
-- we rearrange the bytes and send them to exit
C0 <= byte3 & byte2 & byte1 & byte0;
C1 <= byte7 & byte6 & byte5 & byte4;
C2 <= byte11 & byte10 & byte9 & byte8;
C3 <= byte15 & byte14 & byte13 & byte12;
out_tdo <= C0 & C1 & C2 & C3;
end twofish_data_output_arch;
-- =======-======================================= --
-- =============================================== --
-- --
-- second part: 128 key input dependent components --
-- --
-- =============================================== --
-- =============================================== --
--
-- reed solomon for 128bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity reed_solomon128 is
port (
in_rs128 : in std_logic_vector(127 downto 0);
out_Sfirst_rs128,
out_Ssecond_rs128 : out std_logic_vector(31 downto 0)
);
end reed_solomon128;
architecture rs_128_arch of reed_solomon128 is
-- declaring all components necessary for reed solomon
-- 01
component mul01
port (
in_mul01 : in std_logic_vector(7 downto 0);
out_mul01 : out std_logic_vector(7 downto 0)
);
end component;
-- a4
component mula4
port (
in_mula4 : in std_logic_vector(7 downto 0);
out_mula4 : out std_logic_vector(7 downto 0)
);
end component;
-- 55
component mul55
port (
in_mul55 : in std_logic_vector(7 downto 0);
out_mul55 : out std_logic_vector(7 downto 0)
);
end component;
-- 87
component mul87
port (
in_mul87 : in std_logic_vector(7 downto 0);
out_mul87 : out std_logic_vector(7 downto 0)
);
end component;
-- 5a
component mul5a
port (
in_mul5a : in std_logic_vector(7 downto 0);
out_mul5a : out std_logic_vector(7 downto 0)
);
end component;
-- 58
component mul58
port (
in_mul58 : in std_logic_vector(7 downto 0);
out_mul58 : out std_logic_vector(7 downto 0)
);
end component;
-- db
component muldb
port (
in_muldb : in std_logic_vector(7 downto 0);
out_muldb : out std_logic_vector(7 downto 0)
);
end component;
-- 9e
component mul9e
port (
in_mul9e : in std_logic_vector(7 downto 0);
out_mul9e : out std_logic_vector(7 downto 0)
);
end component;
-- 56
component mul56
port (
in_mul56 : in std_logic_vector(7 downto 0);
out_mul56 : out std_logic_vector(7 downto 0)
);
end component;
-- 82
component mul82
port (
in_mul82 : in std_logic_vector(7 downto 0);
out_mul82 : out std_logic_vector(7 downto 0)
);
end component;
-- f3
component mulf3
port (
in_mulf3 : in std_logic_vector(7 downto 0);
out_mulf3 : out std_logic_vector(7 downto 0)
);
end component;
-- 1e
component mul1e
port (
in_mul1e : in std_logic_vector(7 downto 0);
out_mul1e : out std_logic_vector(7 downto 0)
);
end component;
-- c6
component mulc6
port (
in_mulc6 : in std_logic_vector(7 downto 0);
out_mulc6 : out std_logic_vector(7 downto 0)
);
end component;
-- 68
component mul68
port (
in_mul68 : in std_logic_vector(7 downto 0);
out_mul68 : out std_logic_vector(7 downto 0)
);
end component;
-- e5
component mule5
port (
in_mule5 : in std_logic_vector(7 downto 0);
out_mule5 : out std_logic_vector(7 downto 0)
);
end component;
-- 02
component mul02
port (
in_mul02 : in std_logic_vector(7 downto 0);
out_mul02 : out std_logic_vector(7 downto 0)
);
end component;
-- a1
component mula1
port (
in_mula1 : in std_logic_vector(7 downto 0);
out_mula1 : out std_logic_vector(7 downto 0)
);
end component;
-- fc
component mulfc
port (
in_mulfc : in std_logic_vector(7 downto 0);
out_mulfc : out std_logic_vector(7 downto 0)
);
end component;
-- c1
component mulc1
port (
in_mulc1 : in std_logic_vector(7 downto 0);
out_mulc1 : out std_logic_vector(7 downto 0)
);
end component;
-- 47
component mul47
port (
in_mul47 : in std_logic_vector(7 downto 0);
out_mul47 : out std_logic_vector(7 downto 0)
);
end component;
-- ae
component mulae
port (
in_mulae : in std_logic_vector(7 downto 0);
out_mulae : out std_logic_vector(7 downto 0)
);
end component;
-- 3d
component mul3d
port (
in_mul3d : in std_logic_vector(7 downto 0);
out_mul3d : out std_logic_vector(7 downto 0)
);
end component;
-- 19
component mul19
port (
in_mul19 : in std_logic_vector(7 downto 0);
out_mul19 : out std_logic_vector(7 downto 0)
);
end component;
-- 03
component mul03
port (
in_mul03 : in std_logic_vector(7 downto 0);
out_mul03 : out std_logic_vector(7 downto 0)
);
end component;
-- declaring internal signals
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15 : std_logic_vector(7 downto 0);
signal s00,s01,s02,s03,s10,s11,s12,s13 : std_logic_vector(7 downto 0);
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- first, we separate the input to the respective m
-- for s1,j j=0..3
m0 <= in_rs128(7 downto 0);
m1 <= in_rs128(15 downto 8);
m2 <= in_rs128(23 downto 16);
m3 <= in_rs128(31 downto 24);
m4 <= in_rs128(39 downto 32);
m5 <= in_rs128(47 downto 40);
m6 <= in_rs128(55 downto 48);
m7 <= in_rs128(63 downto 56);
-- for s0,j j=0..3
m8 <= in_rs128(71 downto 64);
m9 <= in_rs128(79 downto 72);
m10 <= in_rs128(87 downto 80);
m11 <= in_rs128(95 downto 88);
m12 <= in_rs128(103 downto 96);
m13 <= in_rs128(111 downto 104);
m14 <= in_rs128(119 downto 112);
m15 <= in_rs128(127 downto 120);
-- after separating signals, we drive them to multipliers
-- the first line of m0..7 forms s00
m0_with_01: mul01
port map (
in_mul01 => m0,
out_mul01 => m0_01
);
m1_with_a4: mula4
port map (
in_mula4 => m1,
out_mula4 => m1_a4
);
m2_with_55: mul55
port map (
in_mul55 => m2,
out_mul55 => m2_55
);
m3_with_87: mul87
port map (
in_mul87 => m3,
out_mul87 => m3_87
);
m4_with_5a: mul5a
port map (
in_mul5a => m4,
out_mul5a => m4_5a
);
m5_with_58: mul58
port map (
in_mul58 => m5,
out_mul58 => m5_58
);
m6_with_db: muldb
port map (
in_muldb => m6,
out_muldb => m6_db
);
m7_with_9e: mul9e
port map (
in_mul9e => m7,
out_mul9e => m7_9e
);
-- the second row creates s01
m0_with_a4: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4
);
m1_with_56: mul56
port map (
in_mul56 => m1,
out_mul56 => m1_56
);
m2_with_82: mul82
port map (
in_mul82 => m2,
out_mul82 => m2_82
);
m3_with_f3: mulf3
port map (
in_mulf3 => m3,
out_mulf3 => m3_f3
);
m4_with_1e: mul1e
port map (
in_mul1e => m4,
out_mul1e => m4_1e
);
m5_with_c6: mulc6
port map (
in_mulc6 => m5,
out_mulc6 => m5_c6
);
m6_with_68: mul68
port map (
in_mul68 => m6,
out_mul68 => m6_68
);
m7_with_e5: mule5
port map (
in_mule5 => m7,
out_mule5 => m7_e5
);
-- the third row creates s02
m0_with_02: mul02
port map (
in_mul02 => m0,
out_mul02 => m0_02
);
m1_with_a1: mula1
port map (
in_mula1 => m1,
out_mula1 => m1_a1
);
m2_with_fc: mulfc
port map (
in_mulfc => m2,
out_mulfc => m2_fc
);
m3_with_c1: mulc1
port map (
in_mulc1 => m3,
out_mulc1 => m3_c1
);
m4_with_47: mul47
port map (
in_mul47 => m4,
out_mul47 => m4_47
);
m5_with_ae: mulae
port map (
in_mulae => m5,
out_mulae => m5_ae
);
m6_with_3d: mul3d
port map (
in_mul3d => m6,
out_mul3d => m6_3d
);
m7_with_19: mul19
port map (
in_mul19 => m7,
out_mul19 => m7_19
);
-- the fourth row creates s03
m0_with_a4_1: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4_1
);
m1_with_55: mul55
port map (
in_mul55 => m1,
out_mul55 => m1_55
);
m2_with_87: mul87
port map (
in_mul87 => m2,
out_mul87 => m2_87
);
m3_with_5a: mul5a
port map (
in_mul5a => m3,
out_mul5a => m3_5a
);
m4_with_58: mul58
port map (
in_mul58 => m4,
out_mul58 => m4_58
);
m5_with_db: muldb
port map (
in_muldb => m5,
out_muldb => m5_db
);
m6_with_9e: mul9e
port map (
in_mul9e => m6,
out_mul9e => m6_9e
);
m7_with_03: mul03
port map (
in_mul03 => m7,
out_mul03 => m7_03
);
-- we create the s1,j j=0..3
-- the first row of m0..7 creates the s10
m8_with_01: mul01
port map (
in_mul01 => m8,
out_mul01 => m8_01
);
m9_with_a4: mula4
port map (
in_mula4 => m9,
out_mula4 => m9_a4
);
m10_with_55: mul55
port map (
in_mul55 => m10,
out_mul55 => m10_55
);
m11_with_87: mul87
port map (
in_mul87 => m11,
out_mul87 => m11_87
);
m12_with_5a: mul5a
port map (
in_mul5a => m12,
out_mul5a => m12_5a
);
m13_with_58: mul58
port map (
in_mul58 => m13,
out_mul58 => m13_58
);
m14_with_db: muldb
port map (
in_muldb => m14,
out_muldb => m14_db
);
m15_with_9e: mul9e
port map (
in_mul9e => m15,
out_mul9e => m15_9e
);
-- the second row creates s11
m8_with_a4: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4
);
m9_with_56: mul56
port map (
in_mul56 => m9,
out_mul56 => m9_56
);
m10_with_82: mul82
port map (
in_mul82 => m10,
out_mul82 => m10_82
);
m11_with_f3: mulf3
port map (
in_mulf3 => m11,
out_mulf3 => m11_f3
);
m12_with_1e: mul1e
port map (
in_mul1e => m12,
out_mul1e => m12_1e
);
m13_with_c6: mulc6
port map (
in_mulc6 => m13,
out_mulc6 => m13_c6
);
m14_with_68: mul68
port map (
in_mul68 => m14,
out_mul68 => m14_68
);
m15_with_e5: mule5
port map (
in_mule5 => m15,
out_mule5 => m15_e5
);
-- the third row creates s12
m8_with_02: mul02
port map (
in_mul02 => m8,
out_mul02 => m8_02
);
m9_with_a1: mula1
port map (
in_mula1 => m9,
out_mula1 => m9_a1
);
m10_with_fc: mulfc
port map (
in_mulfc => m10,
out_mulfc => m10_fc
);
m11_with_c1: mulc1
port map (
in_mulc1 => m11,
out_mulc1 => m11_c1
);
m12_with_47: mul47
port map (
in_mul47 => m12,
out_mul47 => m12_47
);
m13_with_ae: mulae
port map (
in_mulae => m13,
out_mulae => m13_ae
);
m14_with_3d: mul3d
port map (
in_mul3d => m14,
out_mul3d => m14_3d
);
m15_with_19: mul19
port map (
in_mul19 => m15,
out_mul19 => m15_19
);
-- the fourth row creates s13
m8_with_a4_1: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4_1
);
m9_with_55: mul55
port map (
in_mul55 => m9,
out_mul55 => m9_55
);
m10_with_87: mul87
port map (
in_mul87 => m10,
out_mul87 => m10_87
);
m11_with_5a: mul5a
port map (
in_mul5a => m11,
out_mul5a => m11_5a
);
m12_with_58: mul58
port map (
in_mul58 => m12,
out_mul58 => m12_58
);
m13_with_db: muldb
port map (
in_muldb => m13,
out_muldb => m13_db
);
m14_with_9e: mul9e
port map (
in_mul9e => m14,
out_mul9e => m14_9e
);
m15_with_03: mul03
port map (
in_mul03 => m15,
out_mul03 => m15_03
);
-- after getting the results from multipliers
-- we combine them in order to get the additions
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
-- after creating s0,j j=0...3 we form the S0
-- little endian
out_Sfirst_rs128 <= s03 & s02 & s01 & s00;
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
-- after creating s1,j j=0...3 we form the S1
-- little endian
out_Ssecond_rs128 <= s13 & s12 & s11 & s10;
end rs_128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- h function for 128 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity h_128 is
port (
in_h128 : in std_logic_vector(7 downto 0);
Mfirst_h128,
Msecond_h128 : in std_logic_vector(31 downto 0);
out_h128 : out std_logic_vector(31 downto 0)
);
end h_128;
architecture h128_arch of h_128 is
-- we declare internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
to_mds : std_logic_vector(31 downto 0);
-- we declare all components needed
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q0_1: q0
port map (
in_q0 => in_h128,
out_q0 => from_first_row(7 downto 0)
);
first_q1_1: q1
port map (
in_q1 => in_h128,
out_q1 => from_first_row(15 downto 8)
);
first_q0_2: q0
port map (
in_q0 => in_h128,
out_q0 => from_first_row(23 downto 16)
);
first_q1_2: q1
port map (
in_q1 => in_h128,
out_q1 => from_first_row(31 downto 24)
);
-- we perform the XOR of the results of the first row
-- with first M of h (Mfist_h128)
to_second_row <= from_first_row XOR Mfirst_h128;
-- second row of q
second_q0_1: q0
port map (
in_q0 => to_second_row(7 downto 0),
out_q0 => from_second_row(7 downto 0)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(15 downto 8),
out_q0 => from_second_row(15 downto 8)
);
second_q1_1: q1
port map (
in_q1 => to_second_row(23 downto 16),
out_q1 => from_second_row(23 downto 16)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(31 downto 24),
out_q1 => from_second_row(31 downto 24)
);
-- we perform the second XOR
to_third_row <= from_second_row XOR Msecond_h128;
-- the third row of q
third_q1_1: q1
port map (
in_q1 => to_third_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
third_q0_1: q0
port map (
in_q0 => to_third_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_h128(7 downto 0),
z1 => out_h128(15 downto 8),
z2 => out_h128(23 downto 16),
z3 => out_h128(31 downto 24)
);
end h128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- g function for 128 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity g_128 is
port (
in_g128,
in_S0_g128,
in_S1_g128 : in std_logic_vector(31 downto 0);
out_g128 : out std_logic_vector(31 downto 0)
);
end g_128;
architecture g128_arch of g_128 is
-- we declare the internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
to_mds : std_logic_vector(31 downto 0);
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q0_1: q0
port map (
in_q0 => in_g128(7 downto 0),
out_q0 => from_first_row(7 downto 0)
);
first_q1_1: q1
port map (
in_q1 => in_g128(15 downto 8),
out_q1 => from_first_row(15 downto 8)
);
first_q0_2: q0
port map (
in_q0 => in_g128(23 downto 16),
out_q0 => from_first_row(23 downto 16)
);
first_q1_2: q1
port map (
in_q1 => in_g128(31 downto 24),
out_q1 => from_first_row(31 downto 24)
);
-- we XOR the result of the first row
-- with the S0
to_second_row <= from_first_row XOR in_S0_g128;
-- second row of q
second_q0_1: q0
port map (
in_q0 => to_second_row(7 downto 0),
out_q0 => from_second_row(7 downto 0)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(15 downto 8),
out_q0 => from_second_row(15 downto 8)
);
second_q1_1: q1
port map (
in_q1 => to_second_row(23 downto 16),
out_q1 => from_second_row(23 downto 16)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(31 downto 24),
out_q1 => from_second_row(31 downto 24)
);
-- we perform the XOR
to_third_row <= from_second_row XOR in_S1_g128;
-- third row of q
third_q1_1: q1
port map (
in_q1 => to_third_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
third_q0_1: q0
port map (
in_q0 => to_third_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_g128(7 downto 0),
z1 => out_g128(15 downto 8),
z2 => out_g128(23 downto 16),
z3 => out_g128(31 downto 24)
);
end g128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- f function with 128 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity f_128 is
port (
up_in_f128,
low_in_f128,
S0_in_f128,
S1_in_f128,
up_key_f128,
low_key_f128 : in std_logic_vector(31 downto 0);
up_out_f128,
low_out_f128 : out std_logic_vector(31 downto 0)
);
end f_128;
architecture f128_arch of f_128 is
-- we declare the internal signals
signal from_shift_8,
to_up_pht,
to_low_pht,
to_up_key,
to_low_key,
intermediate_carry1,
intermediate_carry2 : std_logic_vector(31 downto 0);
signal zero : std_logic;
component g_128
port (
in_g128,
in_S0_g128,
in_S1_g128 : in std_logic_vector(31 downto 0);
out_g128 : out std_logic_vector(31 downto 0)
);
end component;
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component adder
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end component;
-- begin architecture description
begin
-- we initialize zero
zero <= '0';
-- upper g_128
upper_g128: g_128
port map (
in_g128 => up_in_f128,
in_S0_g128 => S0_in_f128,
in_S1_g128 => S1_in_f128,
out_g128 => to_up_pht
);
-- left rotation by 8
from_shift_8(31 downto 8) <= low_in_f128(23 downto 0);
from_shift_8(7 downto 0) <= low_in_f128(31 downto 24);
-- lower g128
lower_g128: g_128
port map (
in_g128 => from_shift_8,
in_S0_g128 => S0_in_f128,
in_S1_g128 => S1_in_f128,
out_g128 => to_low_pht
);
-- pht
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => to_low_pht,
up_out_pht => to_up_key,
down_out_pht => to_low_key
);
-- upper adder of 32 bits
up_adder: for i in 0 to 31 generate
first: if (i=0) generate
the_adder: adder
port map (
in1_adder => to_up_key(0),
in2_adder => up_key_f128(0),
in_carry_adder => zero,
out_adder => up_out_f128(0),
out_carry_adder => intermediate_carry1(0)
);
end generate first;
the_rest: if (i>0) generate
the_adders: adder
port map (
in1_adder => to_up_key(i),
in2_adder => up_key_f128(i),
in_carry_adder => intermediate_carry1(i-1),
out_adder => up_out_f128(i),
out_carry_adder => intermediate_carry1(i)
);
end generate the_rest;
end generate up_adder;
-- lower adder of 32 bits
low_adder: for i in 0 to 31 generate
first1: if (i=0) generate
the_adder1:adder
port map (
in1_adder => to_low_key(0),
in2_adder => low_key_f128(0),
in_carry_adder => zero,
out_adder => low_out_f128(0),
out_carry_adder => intermediate_carry2(0)
);
end generate first1;
the_rest1: if (i>0) generate
the_adders1: adder
port map (
in1_adder => to_low_key(i),
in2_adder => low_key_f128(i),
in_carry_adder => intermediate_carry2(i-1),
out_adder => low_out_f128(i),
out_carry_adder => intermediate_carry2(i)
);
end generate the_rest1;
end generate low_adder;
end f128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish key scheduler for 128 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_keysched128 is
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end twofish_keysched128;
architecture twofish_keysched128_arch of twofish_keysched128 is
-- we declare internal signals
signal to_up_pht,
to_shift_8,
from_shift_8,
to_shift_9,
M0, M1, M2, M3 : std_logic_vector(31 downto 0);
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6, byte7,
byte8, byte9, byte10, byte11,
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_128
port (
in_h128 : in std_logic_vector(7 downto 0);
Mfirst_h128,
Msecond_h128 : in std_logic_vector(31 downto 0);
out_h128 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte15 <= in_key_tk128(7 downto 0);
byte14 <= in_key_tk128(15 downto 8);
byte13 <= in_key_tk128(23 downto 16);
byte12 <= in_key_tk128(31 downto 24);
byte11 <= in_key_tk128(39 downto 32);
byte10 <= in_key_tk128(47 downto 40);
byte9 <= in_key_tk128(55 downto 48);
byte8 <= in_key_tk128(63 downto 56);
byte7 <= in_key_tk128(71 downto 64);
byte6 <= in_key_tk128(79 downto 72);
byte5 <= in_key_tk128(87 downto 80);
byte4 <= in_key_tk128(95 downto 88);
byte3 <= in_key_tk128(103 downto 96);
byte2 <= in_key_tk128(111 downto 104);
byte1 <= in_key_tk128(119 downto 112);
byte0 <= in_key_tk128(127 downto 120);
-- we form the M{0..3}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
-- upper h
upper_h: h_128
port map (
in_h128 => even_in_tk128,
Mfirst_h128 => M2,
Msecond_h128 => M0,
out_h128 => to_up_pht
);
-- lower h
lower_h: h_128
port map (
in_h128 => odd_in_tk128,
Mfirst_h128 => M3,
Msecond_h128 => M1,
out_h128 => to_shift_8
);
-- left rotate by 8
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
-- pht transformation
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => from_shift_8,
up_out_pht => out_key_up_tk128,
down_out_pht => to_shift_9
);
-- left rotate by 9
out_key_down_tk128(31 downto 9) <= to_shift_9(22 downto 0);
out_key_down_tk128(8 downto 0) <= to_shift_9(31 downto 23);
end twofish_keysched128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish S key component for 128 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_S128 is
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end twofish_S128;
architecture twofish_S128_arch of twofish_S128 is
-- we declare the components to be used
component reed_solomon128
port (
in_rs128 : in std_logic_vector(127 downto 0);
out_Sfirst_rs128,
out_Ssecond_rs128 : out std_logic_vector(31 downto 0)
);
end component;
signal twofish_key : std_logic_vector(127 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- splitting the input
byte15 <= in_key_ts128(7 downto 0);
byte14 <= in_key_ts128(15 downto 8);
byte13 <= in_key_ts128(23 downto 16);
byte12 <= in_key_ts128(31 downto 24);
byte11 <= in_key_ts128(39 downto 32);
byte10 <= in_key_ts128(47 downto 40);
byte9 <= in_key_ts128(55 downto 48);
byte8 <= in_key_ts128(63 downto 56);
byte7 <= in_key_ts128(71 downto 64);
byte6 <= in_key_ts128(79 downto 72);
byte5 <= in_key_ts128(87 downto 80);
byte4 <= in_key_ts128(95 downto 88);
byte3 <= in_key_ts128(103 downto 96);
byte2 <= in_key_ts128(111 downto 104);
byte1 <= in_key_ts128(119 downto 112);
byte0 <= in_key_ts128(127 downto 120);
-- forming the key
twofish_key <= byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
-- the keys S0,1
produce_S0_S1: reed_solomon128
port map (
in_rs128 => twofish_key,
out_Sfirst_rs128 => out_Sfirst_ts128,
out_Ssecond_rs128 => out_Ssecond_ts128
);
end twofish_S128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish whitening key scheduler for 128 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_whit_keysched128 is
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end twofish_whit_keysched128;
architecture twofish_whit_keysched128_arch of twofish_whit_keysched128 is
-- we declare internal signals
signal to_up_pht_1,
to_shift_8_1,
from_shift_8_1,
to_shift_9_1,
to_up_pht_2,
to_shift_8_2,
from_shift_8_2,
to_shift_9_2,
to_up_pht_3,
to_shift_8_3,
from_shift_8_3,
to_shift_9_3,
to_up_pht_4,
to_shift_8_4,
from_shift_8_4,
to_shift_9_4,
M0, M1, M2, M3 : std_logic_vector(31 downto 0);
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6, byte7,
byte8, byte9, byte10, byte11,
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0);
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_128
port (
in_h128 : in std_logic_vector(7 downto 0);
Mfirst_h128,
Msecond_h128 : in std_logic_vector(31 downto 0);
out_h128 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we produce the first eight numbers
zero <= "00000000";
one <= "00000001";
two <= "00000010";
three <= "00000011";
four <= "00000100";
five <= "00000101";
six <= "00000110";
seven <= "00000111";
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte15 <= in_key_twk128(7 downto 0);
byte14 <= in_key_twk128(15 downto 8);
byte13 <= in_key_twk128(23 downto 16);
byte12 <= in_key_twk128(31 downto 24);
byte11 <= in_key_twk128(39 downto 32);
byte10 <= in_key_twk128(47 downto 40);
byte9 <= in_key_twk128(55 downto 48);
byte8 <= in_key_twk128(63 downto 56);
byte7 <= in_key_twk128(71 downto 64);
byte6 <= in_key_twk128(79 downto 72);
byte5 <= in_key_twk128(87 downto 80);
byte4 <= in_key_twk128(95 downto 88);
byte3 <= in_key_twk128(103 downto 96);
byte2 <= in_key_twk128(111 downto 104);
byte1 <= in_key_twk128(119 downto 112);
byte0 <= in_key_twk128(127 downto 120);
-- we form the M{0..3}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
-- we produce the keys for the whitening steps
-- keys K0,1
-- upper h
upper_h1: h_128
port map (
in_h128 => zero,
Mfirst_h128 => M2,
Msecond_h128 => M0,
out_h128 => to_up_pht_1
);
-- lower h
lower_h1: h_128
port map (
in_h128 => one,
Mfirst_h128 => M3,
Msecond_h128 => M1,
out_h128 => to_shift_8_1
);
-- left rotate by 8
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
-- pht transformation
pht_transform1: pht
port map (
up_in_pht => to_up_pht_1,
down_in_pht => from_shift_8_1,
up_out_pht => out_K0_twk128,
down_out_pht => to_shift_9_1
);
-- left rotate by 9
out_K1_twk128(31 downto 9) <= to_shift_9_1(22 downto 0);
out_K1_twk128(8 downto 0) <= to_shift_9_1(31 downto 23);
-- keys K2,3
-- upper h
upper_h2: h_128
port map (
in_h128 => two,
Mfirst_h128 => M2,
Msecond_h128 => M0,
out_h128 => to_up_pht_2
);
-- lower h
lower_h2: h_128
port map (
in_h128 => three,
Mfirst_h128 => M3,
Msecond_h128 => M1,
out_h128 => to_shift_8_2
);
-- left rotate by 8
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
-- pht transformation
pht_transform2: pht
port map (
up_in_pht => to_up_pht_2,
down_in_pht => from_shift_8_2,
up_out_pht => out_K2_twk128,
down_out_pht => to_shift_9_2
);
-- left rotate by 9
out_K3_twk128(31 downto 9) <= to_shift_9_2(22 downto 0);
out_K3_twk128(8 downto 0) <= to_shift_9_2(31 downto 23);
-- keys K4,5
-- upper h
upper_h3: h_128
port map (
in_h128 => four,
Mfirst_h128 => M2,
Msecond_h128 => M0,
out_h128 => to_up_pht_3
);
-- lower h
lower_h3: h_128
port map (
in_h128 => five,
Mfirst_h128 => M3,
Msecond_h128 => M1,
out_h128 => to_shift_8_3
);
-- left rotate by 8
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
-- pht transformation
pht_transform3: pht
port map (
up_in_pht => to_up_pht_3,
down_in_pht => from_shift_8_3,
up_out_pht => out_K4_twk128,
down_out_pht => to_shift_9_3
);
-- left rotate by 9
out_K5_twk128(31 downto 9) <= to_shift_9_3(22 downto 0);
out_K5_twk128(8 downto 0) <= to_shift_9_3(31 downto 23);
-- keys K6,7
-- upper h
upper_h4: h_128
port map (
in_h128 => six,
Mfirst_h128 => M2,
Msecond_h128 => M0,
out_h128 => to_up_pht_4
);
-- lower h
lower_h4: h_128
port map (
in_h128 => seven,
Mfirst_h128 => M3,
Msecond_h128 => M1,
out_h128 => to_shift_8_4
);
-- left rotate by 8
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
-- pht transformation
pht_transform4: pht
port map (
up_in_pht => to_up_pht_4,
down_in_pht => from_shift_8_4,
up_out_pht => out_K6_twk128,
down_out_pht => to_shift_9_4
);
-- left rotate by 9
out_K7_twk128(31 downto 9) <= to_shift_9_4(22 downto 0);
out_K7_twk128(8 downto 0) <= to_shift_9_4(31 downto 23);
end twofish_whit_keysched128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish encryption round with 128 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_encryption_round128 is
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end twofish_encryption_round128;
architecture twofish_encryption_round128_arch of twofish_encryption_round128 is
-- we declare internal signals
signal to_left_shift,
from_right_shift,
to_xor_with3,
to_xor_with4 : std_logic_vector(31 downto 0);
component f_128
port (
up_in_f128,
low_in_f128,
S0_in_f128,
S1_in_f128,
up_key_f128,
low_key_f128 : in std_logic_vector(31 downto 0);
up_out_f128,
low_out_f128 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we declare f_128
function_f: f_128
port map (
up_in_f128 => in1_ter128,
low_in_f128 => in2_ter128,
S0_in_f128 => in_Sfirst_ter128,
S1_in_f128 => in_Ssecond_ter128,
up_key_f128 => in_key_up_ter128,
low_key_f128 => in_key_down_ter128,
up_out_f128 => to_xor_with3,
low_out_f128 => to_xor_with4
);
-- we perform the exchange
-- in1_ter128 -> out3_ter128
-- in2_ter128 -> out4_ter128
-- in3_ter128 -> out1_ter128
-- in4_ter128 -> out2_ter128
-- we perform the left xor between the upper f function and
-- the third input (input 3)
to_left_shift <= to_xor_with3 XOR in3_ter128;
-- we perform the left side rotation to the right by 1 and
-- we perform the exchange too
out1_ter128(30 downto 0) <= to_left_shift(31 downto 1);
out1_ter128(31) <= to_left_shift(0);
-- we perform the right side rotation to the left by 1
from_right_shift(0) <= in4_ter128(31);
from_right_shift(31 downto 1) <= in4_ter128(30 downto 0);
-- we perform the right xor between the lower f function and
-- the fourth input (input 4)
out2_ter128 <= from_right_shift XOR to_xor_with4;
-- we perform the last exchanges
out3_ter128 <= in1_ter128;
out4_ter128 <= in2_ter128;
end twofish_encryption_round128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish decryption round with 128 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_decryption_round128 is
port (
in1_tdr128,
in2_tdr128,
in3_tdr128,
in4_tdr128,
in_Sfirst_tdr128,
in_Ssecond_tdr128,
in_key_up_tdr128,
in_key_down_tdr128 : in std_logic_vector(31 downto 0);
out1_tdr128,
out2_tdr128,
out3_tdr128,
out4_tdr128 : out std_logic_vector(31 downto 0)
);
end twofish_decryption_round128;
architecture twofish_decryption_round128_arch of twofish_decryption_round128 is
signal to_xor_with3,
to_xor_with4,
to_xor_with_up_f,
from_xor_with_down_f : std_logic_vector(31 downto 0);
component f_128
port (
up_in_f128,
low_in_f128,
S0_in_f128,
S1_in_f128,
up_key_f128,
low_key_f128 : in std_logic_vector(31 downto 0);
up_out_f128,
low_out_f128 : out std_logic_vector(31 downto 0)
);
end component;
begin
-- we instantiate f function
function_f: f_128
port map (
up_in_f128 => in1_tdr128,
low_in_f128 => in2_tdr128,
S0_in_f128 => in_Sfirst_tdr128,
S1_in_f128 => in_Ssecond_tdr128,
up_key_f128 => in_key_up_tdr128,
low_key_f128 => in_key_down_tdr128,
up_out_f128 => to_xor_with3,
low_out_f128 => to_xor_with4
);
-- output 1: input3 with upper f
-- we first rotate the input3 by 1 bit leftwise
to_xor_with_up_f(0) <= in3_tdr128(31);
to_xor_with_up_f(31 downto 1) <= in3_tdr128(30 downto 0);
-- we perform the XOR with the upper output of f and the result
-- is ouput 1
out1_tdr128 <= to_xor_with_up_f XOR to_xor_with3;
-- output 2: input4 with lower f
-- we perform the XOR with the lower output of f
from_xor_with_down_f <= in4_tdr128 XOR to_xor_with4;
-- we perform the rotation by 1 bit rightwise and the result
-- is output2
out2_tdr128(31) <= from_xor_with_down_f(0);
out2_tdr128(30 downto 0) <= from_xor_with_down_f(31 downto 1);
-- we assign outputs 3 and 4
out3_tdr128 <= in1_tdr128;
out4_tdr128 <= in2_tdr128;
end twofish_decryption_round128_arch;
-- ============================================== --
-- ============================================== --
-- --
-- third part: 192 key input dependent components --
-- --
-- ============================================== --
-- ============================================== --
--
-- reed solomon for 192bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity reed_solomon192 is
port (
in_rs192 : in std_logic_vector(191 downto 0);
out_Sfirst_rs192,
out_Ssecond_rs192,
out_Sthird_rs192 : out std_logic_vector(31 downto 0)
);
end reed_solomon192;
architecture rs_192_arch of reed_solomon192 is
-- declaring all components necessary for reed solomon
-- 01
component mul01
port (
in_mul01 : in std_logic_vector(7 downto 0);
out_mul01 : out std_logic_vector(7 downto 0)
);
end component;
-- a4
component mula4
port (
in_mula4 : in std_logic_vector(7 downto 0);
out_mula4 : out std_logic_vector(7 downto 0)
);
end component;
-- 55
component mul55
port (
in_mul55 : in std_logic_vector(7 downto 0);
out_mul55 : out std_logic_vector(7 downto 0)
);
end component;
-- 87
component mul87
port (
in_mul87 : in std_logic_vector(7 downto 0);
out_mul87 : out std_logic_vector(7 downto 0)
);
end component;
-- 5a
component mul5a
port (
in_mul5a : in std_logic_vector(7 downto 0);
out_mul5a : out std_logic_vector(7 downto 0)
);
end component;
-- 58
component mul58
port (
in_mul58 : in std_logic_vector(7 downto 0);
out_mul58 : out std_logic_vector(7 downto 0)
);
end component;
-- db
component muldb
port (
in_muldb : in std_logic_vector(7 downto 0);
out_muldb : out std_logic_vector(7 downto 0)
);
end component;
-- 9e
component mul9e
port (
in_mul9e : in std_logic_vector(7 downto 0);
out_mul9e : out std_logic_vector(7 downto 0)
);
end component;
-- 56
component mul56
port (
in_mul56 : in std_logic_vector(7 downto 0);
out_mul56 : out std_logic_vector(7 downto 0)
);
end component;
-- 82
component mul82
port (
in_mul82 : in std_logic_vector(7 downto 0);
out_mul82 : out std_logic_vector(7 downto 0)
);
end component;
-- f3
component mulf3
port (
in_mulf3 : in std_logic_vector(7 downto 0);
out_mulf3 : out std_logic_vector(7 downto 0)
);
end component;
-- 1e
component mul1e
port (
in_mul1e : in std_logic_vector(7 downto 0);
out_mul1e : out std_logic_vector(7 downto 0)
);
end component;
-- c6
component mulc6
port (
in_mulc6 : in std_logic_vector(7 downto 0);
out_mulc6 : out std_logic_vector(7 downto 0)
);
end component;
-- 68
component mul68
port (
in_mul68 : in std_logic_vector(7 downto 0);
out_mul68 : out std_logic_vector(7 downto 0)
);
end component;
-- e5
component mule5
port (
in_mule5 : in std_logic_vector(7 downto 0);
out_mule5 : out std_logic_vector(7 downto 0)
);
end component;
-- 02
component mul02
port (
in_mul02 : in std_logic_vector(7 downto 0);
out_mul02 : out std_logic_vector(7 downto 0)
);
end component;
-- a1
component mula1
port (
in_mula1 : in std_logic_vector(7 downto 0);
out_mula1 : out std_logic_vector(7 downto 0)
);
end component;
-- fc
component mulfc
port (
in_mulfc : in std_logic_vector(7 downto 0);
out_mulfc : out std_logic_vector(7 downto 0)
);
end component;
-- c1
component mulc1
port (
in_mulc1 : in std_logic_vector(7 downto 0);
out_mulc1 : out std_logic_vector(7 downto 0)
);
end component;
-- 47
component mul47
port (
in_mul47 : in std_logic_vector(7 downto 0);
out_mul47 : out std_logic_vector(7 downto 0)
);
end component;
-- ae
component mulae
port (
in_mulae : in std_logic_vector(7 downto 0);
out_mulae : out std_logic_vector(7 downto 0)
);
end component;
-- 3d
component mul3d
port (
in_mul3d : in std_logic_vector(7 downto 0);
out_mul3d : out std_logic_vector(7 downto 0)
);
end component;
-- 19
component mul19
port (
in_mul19 : in std_logic_vector(7 downto 0);
out_mul19 : out std_logic_vector(7 downto 0)
);
end component;
-- 03
component mul03
port (
in_mul03 : in std_logic_vector(7 downto 0);
out_mul03 : out std_logic_vector(7 downto 0)
);
end component;
-- declaring internal signals
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,
m16, m17, m18, m19, m20, m21, m22, m23 : std_logic_vector(7 downto 0);
signal s00,s01,s02,s03,s10,s11,s12,s13, s20, s21, s22, s23 : std_logic_vector(7 downto 0);
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
signal m16_01,m17_a4,m18_55,m19_87,m20_5a,m21_58,m22_db,m23_9e,
m16_a4,m17_56,m18_82,m19_f3,m20_1e,m21_c6,m22_68,m23_e5,
m16_02,m17_a1,m18_fc,m19_c1,m20_47,m21_ae,m22_3d,m23_19,
m16_a4_1,m17_55,m18_87,m19_5a,m20_58,m21_db,m22_9e,m23_03 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- first, we separate the input to the respective m
-- for s0j j=0..3
m0 <= in_rs192(7 downto 0);
m1 <= in_rs192(15 downto 8);
m2 <= in_rs192(23 downto 16);
m3 <= in_rs192(31 downto 24);
m4 <= in_rs192(39 downto 32);
m5 <= in_rs192(47 downto 40);
m6 <= in_rs192(55 downto 48);
m7 <= in_rs192(63 downto 56);
-- for s1j j=0..3
m8 <= in_rs192(71 downto 64);
m9 <= in_rs192(79 downto 72);
m10 <= in_rs192(87 downto 80);
m11 <= in_rs192(95 downto 88);
m12 <= in_rs192(103 downto 96);
m13 <= in_rs192(111 downto 104);
m14 <= in_rs192(119 downto 112);
m15 <= in_rs192(127 downto 120);
-- for s2j j=0..3
m16 <= in_rs192(135 downto 128);
m17 <= in_rs192(143 downto 136);
m18 <= in_rs192(151 downto 144);
m19 <= in_rs192(159 downto 152);
m20 <= in_rs192(167 downto 160);
m21 <= in_rs192(175 downto 168);
m22 <= in_rs192(183 downto 176);
m23 <= in_rs192(191 downto 184);
-- after separating signals, we drive them to multipliers
-- the first line of m0..7 forms s00
m0_with_01: mul01
port map (
in_mul01 => m0,
out_mul01 => m0_01
);
m1_with_a4: mula4
port map (
in_mula4 => m1,
out_mula4 => m1_a4
);
m2_with_55: mul55
port map (
in_mul55 => m2,
out_mul55 => m2_55
);
m3_with_87: mul87
port map (
in_mul87 => m3,
out_mul87 => m3_87
);
m4_with_5a: mul5a
port map (
in_mul5a => m4,
out_mul5a => m4_5a
);
m5_with_58: mul58
port map (
in_mul58 => m5,
out_mul58 => m5_58
);
m6_with_db: muldb
port map (
in_muldb => m6,
out_muldb => m6_db
);
m7_with_9e: mul9e
port map (
in_mul9e => m7,
out_mul9e => m7_9e
);
-- the second row creates s01
m0_with_a4: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4
);
m1_with_56: mul56
port map (
in_mul56 => m1,
out_mul56 => m1_56
);
m2_with_82: mul82
port map (
in_mul82 => m2,
out_mul82 => m2_82
);
m3_with_f3: mulf3
port map (
in_mulf3 => m3,
out_mulf3 => m3_f3
);
m4_with_1e: mul1e
port map (
in_mul1e => m4,
out_mul1e => m4_1e
);
m5_with_c6: mulc6
port map (
in_mulc6 => m5,
out_mulc6 => m5_c6
);
m6_with_68: mul68
port map (
in_mul68 => m6,
out_mul68 => m6_68
);
m7_with_e5: mule5
port map (
in_mule5 => m7,
out_mule5 => m7_e5
);
-- the third row creates s02
m0_with_02: mul02
port map (
in_mul02 => m0,
out_mul02 => m0_02
);
m1_with_a1: mula1
port map (
in_mula1 => m1,
out_mula1 => m1_a1
);
m2_with_fc: mulfc
port map (
in_mulfc => m2,
out_mulfc => m2_fc
);
m3_with_c1: mulc1
port map (
in_mulc1 => m3,
out_mulc1 => m3_c1
);
m4_with_47: mul47
port map (
in_mul47 => m4,
out_mul47 => m4_47
);
m5_with_ae: mulae
port map (
in_mulae => m5,
out_mulae => m5_ae
);
m6_with_3d: mul3d
port map (
in_mul3d => m6,
out_mul3d => m6_3d
);
m7_with_19: mul19
port map (
in_mul19 => m7,
out_mul19 => m7_19
);
-- the fourth row creates s03
m0_with_a4_1: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4_1
);
m1_with_55: mul55
port map (
in_mul55 => m1,
out_mul55 => m1_55
);
m2_with_87: mul87
port map (
in_mul87 => m2,
out_mul87 => m2_87
);
m3_with_5a: mul5a
port map (
in_mul5a => m3,
out_mul5a => m3_5a
);
m4_with_58: mul58
port map (
in_mul58 => m4,
out_mul58 => m4_58
);
m5_with_db: muldb
port map (
in_muldb => m5,
out_muldb => m5_db
);
m6_with_9e: mul9e
port map (
in_mul9e => m6,
out_mul9e => m6_9e
);
m7_with_03: mul03
port map (
in_mul03 => m7,
out_mul03 => m7_03
);
-- we create the s1,j j=0..3
-- the first row of m8..15 creates the s10
m8_with_01: mul01
port map (
in_mul01 => m8,
out_mul01 => m8_01
);
m9_with_a4: mula4
port map (
in_mula4 => m9,
out_mula4 => m9_a4
);
m10_with_55: mul55
port map (
in_mul55 => m10,
out_mul55 => m10_55
);
m11_with_87: mul87
port map (
in_mul87 => m11,
out_mul87 => m11_87
);
m12_with_5a: mul5a
port map (
in_mul5a => m12,
out_mul5a => m12_5a
);
m13_with_58: mul58
port map (
in_mul58 => m13,
out_mul58 => m13_58
);
m14_with_db: muldb
port map (
in_muldb => m14,
out_muldb => m14_db
);
m15_with_9e: mul9e
port map (
in_mul9e => m15,
out_mul9e => m15_9e
);
-- the second row creates s11
m8_with_a4: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4
);
m9_with_56: mul56
port map (
in_mul56 => m9,
out_mul56 => m9_56
);
m10_with_82: mul82
port map (
in_mul82 => m10,
out_mul82 => m10_82
);
m11_with_f3: mulf3
port map (
in_mulf3 => m11,
out_mulf3 => m11_f3
);
m12_with_1e: mul1e
port map (
in_mul1e => m12,
out_mul1e => m12_1e
);
m13_with_c6: mulc6
port map (
in_mulc6 => m13,
out_mulc6 => m13_c6
);
m14_with_68: mul68
port map (
in_mul68 => m14,
out_mul68 => m14_68
);
m15_with_e5: mule5
port map (
in_mule5 => m15,
out_mule5 => m15_e5
);
-- the third row creates s12
m8_with_02: mul02
port map (
in_mul02 => m8,
out_mul02 => m8_02
);
m9_with_a1: mula1
port map (
in_mula1 => m9,
out_mula1 => m9_a1
);
m10_with_fc: mulfc
port map (
in_mulfc => m10,
out_mulfc => m10_fc
);
m11_with_c1: mulc1
port map (
in_mulc1 => m11,
out_mulc1 => m11_c1
);
m12_with_47: mul47
port map (
in_mul47 => m12,
out_mul47 => m12_47
);
m13_with_ae: mulae
port map (
in_mulae => m13,
out_mulae => m13_ae
);
m14_with_3d: mul3d
port map (
in_mul3d => m14,
out_mul3d => m14_3d
);
m15_with_19: mul19
port map (
in_mul19 => m15,
out_mul19 => m15_19
);
-- the fourth row creates s13
m8_with_a4_1: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4_1
);
m9_with_55: mul55
port map (
in_mul55 => m9,
out_mul55 => m9_55
);
m10_with_87: mul87
port map (
in_mul87 => m10,
out_mul87 => m10_87
);
m11_with_5a: mul5a
port map (
in_mul5a => m11,
out_mul5a => m11_5a
);
m12_with_58: mul58
port map (
in_mul58 => m12,
out_mul58 => m12_58
);
m13_with_db: muldb
port map (
in_muldb => m13,
out_muldb => m13_db
);
m14_with_9e: mul9e
port map (
in_mul9e => m14,
out_mul9e => m14_9e
);
m15_with_03: mul03
port map (
in_mul03 => m15,
out_mul03 => m15_03
);
-- we create the s2,j j=0..3
-- the first row of m16..23 creates the s20
m16_with_01: mul01
port map (
in_mul01 => m16,
out_mul01 => m16_01
);
m17_with_a4: mula4
port map (
in_mula4 => m17,
out_mula4 => m17_a4
);
m18_with_55: mul55
port map (
in_mul55 => m18,
out_mul55 => m18_55
);
m19_with_87: mul87
port map (
in_mul87 => m19,
out_mul87 => m19_87
);
m20_with_5a: mul5a
port map (
in_mul5a => m20,
out_mul5a => m20_5a
);
m21_with_58: mul58
port map (
in_mul58 => m21,
out_mul58 => m21_58
);
m22_with_db: muldb
port map (
in_muldb => m22,
out_muldb => m22_db
);
m23_with_9e: mul9e
port map (
in_mul9e => m23,
out_mul9e => m23_9e
);
-- the second row creates s21
m16_with_a4: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4
);
m17_with_56: mul56
port map (
in_mul56 => m17,
out_mul56 => m17_56
);
m18_with_82: mul82
port map (
in_mul82 => m18,
out_mul82 => m18_82
);
m19_with_f3: mulf3
port map (
in_mulf3 => m19,
out_mulf3 => m19_f3
);
m20_with_1e: mul1e
port map (
in_mul1e => m20,
out_mul1e => m20_1e
);
m21_with_c6: mulc6
port map (
in_mulc6 => m21,
out_mulc6 => m21_c6
);
m22_with_68: mul68
port map (
in_mul68 => m22,
out_mul68 => m22_68
);
m23_with_e5: mule5
port map (
in_mule5 => m23,
out_mule5 => m23_e5
);
-- the third row creates s22
m16_with_02: mul02
port map (
in_mul02 => m16,
out_mul02 => m16_02
);
m17_with_a1: mula1
port map (
in_mula1 => m17,
out_mula1 => m17_a1
);
m18_with_fc: mulfc
port map (
in_mulfc => m18,
out_mulfc => m18_fc
);
m19_with_c1: mulc1
port map (
in_mulc1 => m19,
out_mulc1 => m19_c1
);
m20_with_47: mul47
port map (
in_mul47 => m20,
out_mul47 => m20_47
);
m21_with_ae: mulae
port map (
in_mulae => m21,
out_mulae => m21_ae
);
m22_with_3d: mul3d
port map (
in_mul3d => m22,
out_mul3d => m22_3d
);
m23_with_19: mul19
port map (
in_mul19 => m23,
out_mul19 => m23_19
);
-- the fourth row creates s23
m16_with_a4_1: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4_1
);
m17_with_55: mul55
port map (
in_mul55 => m17,
out_mul55 => m17_55
);
m18_with_87: mul87
port map (
in_mul87 => m18,
out_mul87 => m18_87
);
m19_with_5a: mul5a
port map (
in_mul5a => m19,
out_mul5a => m19_5a
);
m20_with_58: mul58
port map (
in_mul58 => m20,
out_mul58 => m20_58
);
m21_with_db: muldb
port map (
in_muldb => m21,
out_muldb => m21_db
);
m22_with_9e: mul9e
port map (
in_mul9e => m22,
out_mul9e => m22_9e
);
m23_with_03: mul03
port map (
in_mul03 => m23,
out_mul03 => m23_03
);
-- after getting the results from multipliers
-- we combine them in order to get the additions
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
-- after creating s0,j j=0...3 we form the S0
-- little endian
out_Sfirst_rs192 <= s03 & s02 & s01 & s00;
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
-- after creating s1,j j=0...3 we form the S1
-- little endian
out_Ssecond_rs192 <= s13 & s12 & s11 & s10;
s20 <= m16_01 XOR m17_a4 XOR m18_55 XOR m19_87 XOR m20_5a XOR m21_58 XOR m22_db XOR m23_9e;
s21 <= m16_a4 XOR m17_56 XOR m18_82 XOR m19_f3 XOR m20_1e XOR m21_c6 XOR m22_68 XOR m23_e5;
s22 <= m16_02 XOR m17_a1 XOR m18_fc XOR m19_c1 XOR m20_47 XOR m21_ae XOR m22_3d XOR m23_19;
s23 <= m16_a4_1 XOR m17_55 XOR m18_87 XOR m19_5a XOR m20_58 XOR m21_db XOR m22_9e XOR m23_03;
-- after creating s2j j=0...3 we form the S2
-- little endian
out_Sthird_rs192 <= s23 & s22 & s21 & s20;
end rs_192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- h function for 192 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity h_192 is
port (
in_h192 : in std_logic_vector(7 downto 0);
Mfirst_h192,
Msecond_h192,
Mthird_h192 : in std_logic_vector(31 downto 0);
out_h192 : out std_logic_vector(31 downto 0)
);
end h_192;
architecture h192_arch of h_192 is
-- we declare internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
to_mds : std_logic_vector(31 downto 0);
-- we declare all components needed
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_h192,
out_q1 => from_first_row(7 downto 0)
);
first_q1_2: q1
port map (
in_q1 => in_h192,
out_q1 => from_first_row(15 downto 8)
);
first_q0_1: q0
port map (
in_q0 => in_h192,
out_q0 => from_first_row(23 downto 16)
);
first_q0_2: q0
port map (
in_q0 => in_h192,
out_q0 => from_first_row(31 downto 24)
);
-- we perform the XOR of the results of the first row
-- with first M of h (Mfirst_h128)
to_second_row <= from_first_row XOR Mfirst_h192;
-- second row of q
second_q0_1: q0
port map (
in_q0 => to_second_row(7 downto 0),
out_q0 => from_second_row(7 downto 0)
);
second_q1_1: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(31 downto 24),
out_q1 => from_second_row(31 downto 24)
);
-- we perform the XOR of the results of the second row
-- with second M of h (Msecond_h128)
to_third_row <= from_second_row XOR Msecond_h192;
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(15 downto 8),
out_q0 => from_third_row(15 downto 8)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(23 downto 16),
out_q1 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
-- we perform the third XOR
to_fourth_row <= from_third_row XOR Mthird_h192;
-- the fourth row of q
fourth_q1_1: q1
port map (
in_q1 => to_fourth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_h192(7 downto 0),
z1 => out_h192(15 downto 8),
z2 => out_h192(23 downto 16),
z3 => out_h192(31 downto 24)
);
end h192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- g function for 192 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity g_192 is
port (
in_g192,
in_S0_g192,
in_S1_g192,
in_S2_g192 : in std_logic_vector(31 downto 0);
out_g192 : out std_logic_vector(31 downto 0)
);
end g_192;
architecture g192_arch of g_192 is
-- we declare the internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
to_mds : std_logic_vector(31 downto 0);
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_g192(7 downto 0),
out_q1 => from_first_row(7 downto 0)
);
first_q1_2: q1
port map (
in_q1 => in_g192(15 downto 8),
out_q1 => from_first_row(15 downto 8)
);
first_q0_1: q0
port map (
in_q0 => in_g192(23 downto 16),
out_q0 => from_first_row(23 downto 16)
);
first_q0_2: q0
port map (
in_q0 => in_g192(31 downto 24),
out_q0 => from_first_row(31 downto 24)
);
-- we XOR the result of the first row
-- with the S0
to_second_row <= from_first_row XOR in_S0_g192;
-- second row of q
second_q0_1: q0
port map (
in_q0 => to_second_row(7 downto 0),
out_q0 => from_second_row(7 downto 0)
);
second_q1_1: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(31 downto 24),
out_q1 => from_second_row(31 downto 24)
);
-- we perform the XOR
to_third_row <= from_second_row XOR in_S1_g192;
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(15 downto 8),
out_q0 => from_third_row(15 downto 8)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(23 downto 16),
out_q1 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
-- we perform the XOR
to_fourth_row <= from_third_row XOR in_S2_g192;
-- fourth row of q
fourth_q1_1: q1
port map (
in_q1=> to_fourth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_g192(7 downto 0),
z1 => out_g192(15 downto 8),
z2 => out_g192(23 downto 16),
z3 => out_g192(31 downto 24)
);
end g192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- f function with 192 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity f_192 is
port (
up_in_f192,
low_in_f192,
S0_in_f192,
S1_in_f192,
S2_in_f192,
up_key_f192,
low_key_f192 : in std_logic_vector(31 downto 0);
up_out_f192,
low_out_f192 : out std_logic_vector(31 downto 0)
);
end f_192;
architecture f192_arch of f_192 is
-- we declare the internal signals
signal from_shift_8,
to_up_pht,
to_low_pht,
to_up_key,
to_low_key,
intermediate_carry1,
intermediate_carry2 : std_logic_vector(31 downto 0);
signal zero : std_logic;
component g_192
port (
in_g192,
in_S0_g192,
in_S1_g192,
in_S2_g192 : in std_logic_vector(31 downto 0);
out_g192 : out std_logic_vector(31 downto 0)
);
end component;
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component adder
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end component;
-- begin architecture description
begin
-- we initialize zero
zero <= '0';
-- upper g_192
upper_g192: g_192
port map (
in_g192 => up_in_f192,
in_S0_g192 => S0_in_f192,
in_S1_g192 => S1_in_f192,
in_S2_g192 => S2_in_f192,
out_g192 => to_up_pht
);
-- left rotation by 8
from_shift_8(31 downto 8) <= low_in_f192(23 downto 0);
from_shift_8(7 downto 0) <= low_in_f192(31 downto 24);
-- lower g192
lower_g192: g_192
port map (
in_g192 => from_shift_8,
in_S0_g192 => S0_in_f192,
in_S1_g192 => S1_in_f192,
in_S2_g192 => S2_in_f192,
out_g192 => to_low_pht
);
-- pht
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => to_low_pht,
up_out_pht => to_up_key,
down_out_pht => to_low_key
);
-- upper adder of 32 bits
up_adder: for i in 0 to 31 generate
first: if (i=0) generate
the_adder: adder
port map (
in1_adder => to_up_key(0),
in2_adder => up_key_f192(0),
in_carry_adder => zero,
out_adder => up_out_f192(0),
out_carry_adder => intermediate_carry1(0)
);
end generate first;
the_rest: if (i>0) generate
the_adders: adder
port map (
in1_adder => to_up_key(i),
in2_adder => up_key_f192(i),
in_carry_adder => intermediate_carry1(i-1),
out_adder => up_out_f192(i),
out_carry_adder => intermediate_carry1(i)
);
end generate the_rest;
end generate up_adder;
-- lower adder of 32 bits
low_adder: for i in 0 to 31 generate
first1: if (i=0) generate
the_adder1:adder
port map (
in1_adder => to_low_key(0),
in2_adder => low_key_f192(0),
in_carry_adder => zero,
out_adder => low_out_f192(0),
out_carry_adder => intermediate_carry2(0)
);
end generate first1;
the_rest1: if (i>0) generate
the_adders1: adder
port map (
in1_adder => to_low_key(i),
in2_adder => low_key_f192(i),
in_carry_adder => intermediate_carry2(i-1),
out_adder => low_out_f192(i),
out_carry_adder => intermediate_carry2(i)
);
end generate the_rest1;
end generate low_adder;
end f192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish key scheduler for 192 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_keysched192 is
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end twofish_keysched192;
architecture twofish_keysched192_arch of twofish_keysched192 is
-- we declare internal signals
signal to_up_pht,
to_shift_8,
from_shift_8,
to_shift_9,
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0);
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6, byte7,
byte8, byte9, byte10, byte11,
byte12, byte13, byte14, byte15,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_192
port (
in_h192 : in std_logic_vector(7 downto 0);
Mfirst_h192,
Msecond_h192,
Mthird_h192 : in std_logic_vector(31 downto 0);
out_h192 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte23 <= in_key_tk192(7 downto 0);
byte22 <= in_key_tk192(15 downto 8);
byte21 <= in_key_tk192(23 downto 16);
byte20 <= in_key_tk192(31 downto 24);
byte19 <= in_key_tk192(39 downto 32);
byte18 <= in_key_tk192(47 downto 40);
byte17 <= in_key_tk192(55 downto 48);
byte16 <= in_key_tk192(63 downto 56);
byte15 <= in_key_tk192(71 downto 64);
byte14 <= in_key_tk192(79 downto 72);
byte13 <= in_key_tk192(87 downto 80);
byte12 <= in_key_tk192(95 downto 88);
byte11 <= in_key_tk192(103 downto 96);
byte10 <= in_key_tk192(111 downto 104);
byte9 <= in_key_tk192(119 downto 112);
byte8 <= in_key_tk192(127 downto 120);
byte7 <= in_key_tk192(135 downto 128);
byte6 <= in_key_tk192(143 downto 136);
byte5 <= in_key_tk192(151 downto 144);
byte4 <= in_key_tk192(159 downto 152);
byte3 <= in_key_tk192(167 downto 160);
byte2 <= in_key_tk192(175 downto 168);
byte1 <= in_key_tk192(183 downto 176);
byte0 <= in_key_tk192(191 downto 184);
-- we form the M{0..5}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
-- upper h
upper_h: h_192
port map (
in_h192 => even_in_tk192,
Mfirst_h192 => M4,
Msecond_h192 => M2,
Mthird_h192 => M0,
out_h192 => to_up_pht
);
-- lower h
lower_h: h_192
port map (
in_h192 => odd_in_tk192,
Mfirst_h192 => M5,
Msecond_h192 => M3,
Mthird_h192 => M1,
out_h192 => to_shift_8
);
-- left rotate by 8
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
-- pht transformation
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => from_shift_8,
up_out_pht => out_key_up_tk192,
down_out_pht => to_shift_9
);
-- left rotate by 9
out_key_down_tk192(31 downto 9) <= to_shift_9(22 downto 0);
out_key_down_tk192(8 downto 0) <= to_shift_9(31 downto 23);
end twofish_keysched192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish S key component for 192 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_S192 is
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end twofish_S192;
architecture twofish_S192_arch of twofish_S192 is
-- we declare the components to be used
component reed_solomon192
port (
in_rs192 : in std_logic_vector(191 downto 0);
out_Sfirst_rs192,
out_Ssecond_rs192,
out_Sthird_rs192 : out std_logic_vector(31 downto 0)
);
end component;
signal twofish_key : std_logic_vector(191 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- splitting the input
byte23 <= in_key_ts192(7 downto 0);
byte22 <= in_key_ts192(15 downto 8);
byte21 <= in_key_ts192(23 downto 16);
byte20 <= in_key_ts192(31 downto 24);
byte19 <= in_key_ts192(39 downto 32);
byte18 <= in_key_ts192(47 downto 40);
byte17 <= in_key_ts192(55 downto 48);
byte16 <= in_key_ts192(63 downto 56);
byte15 <= in_key_ts192(71 downto 64);
byte14 <= in_key_ts192(79 downto 72);
byte13 <= in_key_ts192(87 downto 80);
byte12 <= in_key_ts192(95 downto 88);
byte11 <= in_key_ts192(103 downto 96);
byte10 <= in_key_ts192(111 downto 104);
byte9 <= in_key_ts192(119 downto 112);
byte8 <= in_key_ts192(127 downto 120);
byte7 <= in_key_ts192(135 downto 128);
byte6 <= in_key_ts192(143 downto 136);
byte5 <= in_key_ts192(151 downto 144);
byte4 <= in_key_ts192(159 downto 152);
byte3 <= in_key_ts192(167 downto 160);
byte2 <= in_key_ts192(175 downto 168);
byte1 <= in_key_ts192(183 downto 176);
byte0 <= in_key_ts192(191 downto 184);
-- forming the key
twofish_key <= byte23 & byte22 & byte21 & byte20 & byte19 & byte18 & byte17 & byte16 &
byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
-- the keys S0,1,2
produce_S0_S1_S2: reed_solomon192
port map (
in_rs192 => twofish_key,
out_Sfirst_rs192 => out_Sfirst_ts192,
out_Ssecond_rs192 => out_Ssecond_ts192,
out_Sthird_rs192 => out_Sthird_ts192
);
end twofish_S192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish whitening key scheduler for 192 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_whit_keysched192 is
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end twofish_whit_keysched192;
architecture twofish_whit_keysched192_arch of twofish_whit_keysched192 is
-- we declare internal signals
signal to_up_pht_1,
to_shift_8_1,
from_shift_8_1,
to_shift_9_1,
to_up_pht_2,
to_shift_8_2,
from_shift_8_2,
to_shift_9_2,
to_up_pht_3,
to_shift_8_3,
from_shift_8_3,
to_shift_9_3,
to_up_pht_4,
to_shift_8_4,
from_shift_8_4,
to_shift_9_4,
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0);
signal byte0, byte1, byte2, byte3,
byte4, byte5, byte6, byte7,
byte8, byte9, byte10, byte11,
byte12, byte13, byte14, byte15,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_192
port (
in_h192 : in std_logic_vector(7 downto 0);
Mfirst_h192,
Msecond_h192,
Mthird_h192 : in std_logic_vector(31 downto 0);
out_h192 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we produce the first eight numbers
zero <= "00000000";
one <= "00000001";
two <= "00000010";
three <= "00000011";
four <= "00000100";
five <= "00000101";
six <= "00000110";
seven <= "00000111";
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte23 <= in_key_twk192(7 downto 0);
byte22 <= in_key_twk192(15 downto 8);
byte21 <= in_key_twk192(23 downto 16);
byte20 <= in_key_twk192(31 downto 24);
byte19 <= in_key_twk192(39 downto 32);
byte18 <= in_key_twk192(47 downto 40);
byte17 <= in_key_twk192(55 downto 48);
byte16 <= in_key_twk192(63 downto 56);
byte15 <= in_key_twk192(71 downto 64);
byte14 <= in_key_twk192(79 downto 72);
byte13 <= in_key_twk192(87 downto 80);
byte12 <= in_key_twk192(95 downto 88);
byte11 <= in_key_twk192(103 downto 96);
byte10 <= in_key_twk192(111 downto 104);
byte9 <= in_key_twk192(119 downto 112);
byte8 <= in_key_twk192(127 downto 120);
byte7 <= in_key_twk192(135 downto 128);
byte6 <= in_key_twk192(143 downto 136);
byte5 <= in_key_twk192(151 downto 144);
byte4 <= in_key_twk192(159 downto 152);
byte3 <= in_key_twk192(167 downto 160);
byte2 <= in_key_twk192(175 downto 168);
byte1 <= in_key_twk192(183 downto 176);
byte0 <= in_key_twk192(191 downto 184);
-- we form the M{0..5}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
-- we produce the keys for the whitening steps
-- keys K0,1
-- upper h
upper_h1: h_192
port map (
in_h192 => zero,
Mfirst_h192 => M4,
Msecond_h192 => M2,
Mthird_h192 => M0,
out_h192 => to_up_pht_1
);
-- lower h
lower_h1: h_192
port map (
in_h192 => one,
Mfirst_h192 => M5,
Msecond_h192 => M3,
Mthird_h192 => M1,
out_h192 => to_shift_8_1
);
-- left rotate by 8
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
-- pht transformation
pht_transform1: pht
port map (
up_in_pht => to_up_pht_1,
down_in_pht => from_shift_8_1,
up_out_pht => out_K0_twk192,
down_out_pht => to_shift_9_1
);
-- left rotate by 9
out_K1_twk192(31 downto 9) <= to_shift_9_1(22 downto 0);
out_K1_twk192(8 downto 0) <= to_shift_9_1(31 downto 23);
-- keys K2,3
-- upper h
upper_h2: h_192
port map (
in_h192 => two,
Mfirst_h192 => M4,
Msecond_h192 => M2,
Mthird_h192 => M0,
out_h192 => to_up_pht_2
);
-- lower h
lower_h2: h_192
port map (
in_h192 => three,
Mfirst_h192 => M5,
Msecond_h192 => M3,
Mthird_h192 => M1,
out_h192 => to_shift_8_2
);
-- left rotate by 8
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
-- pht transformation
pht_transform2: pht
port map (
up_in_pht => to_up_pht_2,
down_in_pht => from_shift_8_2,
up_out_pht => out_K2_twk192,
down_out_pht => to_shift_9_2
);
-- left rotate by 9
out_K3_twk192(31 downto 9) <= to_shift_9_2(22 downto 0);
out_K3_twk192(8 downto 0) <= to_shift_9_2(31 downto 23);
-- keys K4,5
-- upper h
upper_h3: h_192
port map (
in_h192 => four,
Mfirst_h192 => M4,
Msecond_h192 => M2,
Mthird_h192 => M0,
out_h192 => to_up_pht_3
);
-- lower h
lower_h3: h_192
port map (
in_h192 => five,
Mfirst_h192 => M5,
Msecond_h192 => M3,
Mthird_h192 => M1,
out_h192 => to_shift_8_3
);
-- left rotate by 8
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
-- pht transformation
pht_transform3: pht
port map (
up_in_pht => to_up_pht_3,
down_in_pht => from_shift_8_3,
up_out_pht => out_K4_twk192,
down_out_pht => to_shift_9_3
);
-- left rotate by 9
out_K5_twk192(31 downto 9) <= to_shift_9_3(22 downto 0);
out_K5_twk192(8 downto 0) <= to_shift_9_3(31 downto 23);
-- keys K6,7
-- upper h
upper_h4: h_192
port map (
in_h192 => six,
Mfirst_h192 => M4,
Msecond_h192 => M2,
Mthird_h192 => M0,
out_h192 => to_up_pht_4
);
-- lower h
lower_h4: h_192
port map (
in_h192 => seven,
Mfirst_h192 => M5,
Msecond_h192 => M3,
Mthird_h192 => M1,
out_h192 => to_shift_8_4
);
-- left rotate by 8
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
-- pht transformation
pht_transform4: pht
port map (
up_in_pht => to_up_pht_4,
down_in_pht => from_shift_8_4,
up_out_pht => out_K6_twk192,
down_out_pht => to_shift_9_4
);
-- left rotate by 9
out_K7_twk192(31 downto 9) <= to_shift_9_4(22 downto 0);
out_K7_twk192(8 downto 0) <= to_shift_9_4(31 downto 23);
end twofish_whit_keysched192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish encryption round with 192 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_encryption_round192 is
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end twofish_encryption_round192;
architecture twofish_encryption_round192_arch of twofish_encryption_round192 is
-- we declare internal signals
signal to_left_shift,
from_right_shift,
to_xor_with3,
to_xor_with4 : std_logic_vector(31 downto 0);
component f_192
port (
up_in_f192,
low_in_f192,
S0_in_f192,
S1_in_f192,
S2_in_f192,
up_key_f192,
low_key_f192 : in std_logic_vector(31 downto 0);
up_out_f192,
low_out_f192 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we declare f_192
function_f: f_192
port map (
up_in_f192 => in1_ter192,
low_in_f192 => in2_ter192,
S0_in_f192 => in_Sfirst_ter192,
S1_in_f192 => in_Ssecond_ter192,
S2_in_f192 => in_Sthird_ter192,
up_key_f192 => in_key_up_ter192,
low_key_f192 => in_key_down_ter192,
up_out_f192 => to_xor_with3,
low_out_f192 => to_xor_with4
);
-- we perform the exchange
-- in1_ter128 -> out3_ter128
-- in2_ter128 -> out4_ter128
-- in3_ter128 -> out1_ter128
-- in4_ter128 -> out2_ter128
-- we perform the left xor between the upper f function and
-- the third input (input 3)
to_left_shift <= to_xor_with3 XOR in3_ter192;
-- we perform the left side rotation to the right by 1 and
-- we perform the exchange too
out1_ter192(30 downto 0) <= to_left_shift(31 downto 1);
out1_ter192(31) <= to_left_shift(0);
-- we perform the right side rotation to the left by 1
from_right_shift(0) <= in4_ter192(31);
from_right_shift(31 downto 1) <= in4_ter192(30 downto 0);
-- we perform the right xor between the lower f function and
-- the fourth input (input 4)
out2_ter192 <= from_right_shift XOR to_xor_with4;
-- we perform the last exchanges
out3_ter192 <= in1_ter192;
out4_ter192 <= in2_ter192;
end twofish_encryption_round192_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish decryption round with 192 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_decryption_round192 is
port (
in1_tdr192,
in2_tdr192,
in3_tdr192,
in4_tdr192,
in_Sfirst_tdr192,
in_Ssecond_tdr192,
in_Sthird_tdr192,
in_key_up_tdr192,
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
out1_tdr192,
out2_tdr192,
out3_tdr192,
out4_tdr192 : out std_logic_vector(31 downto 0)
);
end twofish_decryption_round192;
architecture twofish_decryption_round192_arch of twofish_decryption_round192 is
signal to_xor_with3,
to_xor_with4,
to_xor_with_up_f,
from_xor_with_down_f : std_logic_vector(31 downto 0);
component f_192
port (
up_in_f192,
low_in_f192,
S0_in_f192,
S1_in_f192,
S2_in_f192,
up_key_f192,
low_key_f192 : in std_logic_vector(31 downto 0);
up_out_f192,
low_out_f192 : out std_logic_vector(31 downto 0)
);
end component;
begin
-- we instantiate f function
function_f: f_192
port map (
up_in_f192 => in1_tdr192,
low_in_f192 => in2_tdr192,
S0_in_f192 => in_Sfirst_tdr192,
S1_in_f192 => in_Ssecond_tdr192,
S2_in_f192 => in_Sthird_tdr192,
up_key_f192 => in_key_up_tdr192,
low_key_f192 => in_key_down_tdr192,
up_out_f192 => to_xor_with3,
low_out_f192 => to_xor_with4
);
-- output 1: input3 with upper f
-- we first rotate the input3 by 1 bit leftwise
to_xor_with_up_f(0) <= in3_tdr192(31);
to_xor_with_up_f(31 downto 1) <= in3_tdr192(30 downto 0);
-- we perform the XOR with the upper output of f and the result
-- is ouput 1
out1_tdr192 <= to_xor_with_up_f XOR to_xor_with3;
-- output 2: input4 with lower f
-- we perform the XOR with the lower output of f
from_xor_with_down_f <= in4_tdr192 XOR to_xor_with4;
-- we perform the rotation by 1 bit rightwise and the result
-- is output2
out2_tdr192(31) <= from_xor_with_down_f(0);
out2_tdr192(30 downto 0) <= from_xor_with_down_f(31 downto 1);
-- we assign outputs 3 and 4
out3_tdr192 <= in1_tdr192;
out4_tdr192 <= in2_tdr192;
end twofish_decryption_round192_arch;
-- =============================================== --
-- =============================================== --
-- --
-- fourth part: 256 key input dependent components --
-- --
-- =============================================== --
-- =============================================== --
--
-- reed solomon for 256bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity reed_solomon256 is
port (
in_rs256 : in std_logic_vector(255 downto 0);
out_Sfirst_rs256,
out_Ssecond_rs256,
out_Sthird_rs256,
out_Sfourth_rs256 : out std_logic_vector(31 downto 0)
);
end reed_solomon256;
architecture rs_256_arch of reed_solomon256 is
-- declaring all components necessary for reed solomon
-- 01
component mul01
port (
in_mul01 : in std_logic_vector(7 downto 0);
out_mul01 : out std_logic_vector(7 downto 0)
);
end component;
-- a4
component mula4
port (
in_mula4 : in std_logic_vector(7 downto 0);
out_mula4 : out std_logic_vector(7 downto 0)
);
end component;
-- 55
component mul55
port (
in_mul55 : in std_logic_vector(7 downto 0);
out_mul55 : out std_logic_vector(7 downto 0)
);
end component;
-- 87
component mul87
port (
in_mul87 : in std_logic_vector(7 downto 0);
out_mul87 : out std_logic_vector(7 downto 0)
);
end component;
-- 5a
component mul5a
port (
in_mul5a : in std_logic_vector(7 downto 0);
out_mul5a : out std_logic_vector(7 downto 0)
);
end component;
-- 58
component mul58
port (
in_mul58 : in std_logic_vector(7 downto 0);
out_mul58 : out std_logic_vector(7 downto 0)
);
end component;
-- db
component muldb
port (
in_muldb : in std_logic_vector(7 downto 0);
out_muldb : out std_logic_vector(7 downto 0)
);
end component;
-- 9e
component mul9e
port (
in_mul9e : in std_logic_vector(7 downto 0);
out_mul9e : out std_logic_vector(7 downto 0)
);
end component;
-- 56
component mul56
port (
in_mul56 : in std_logic_vector(7 downto 0);
out_mul56 : out std_logic_vector(7 downto 0)
);
end component;
-- 82
component mul82
port (
in_mul82 : in std_logic_vector(7 downto 0);
out_mul82 : out std_logic_vector(7 downto 0)
);
end component;
-- f3
component mulf3
port (
in_mulf3 : in std_logic_vector(7 downto 0);
out_mulf3 : out std_logic_vector(7 downto 0)
);
end component;
-- 1e
component mul1e
port (
in_mul1e : in std_logic_vector(7 downto 0);
out_mul1e : out std_logic_vector(7 downto 0)
);
end component;
-- c6
component mulc6
port (
in_mulc6 : in std_logic_vector(7 downto 0);
out_mulc6 : out std_logic_vector(7 downto 0)
);
end component;
-- 68
component mul68
port (
in_mul68 : in std_logic_vector(7 downto 0);
out_mul68 : out std_logic_vector(7 downto 0)
);
end component;
-- e5
component mule5
port (
in_mule5 : in std_logic_vector(7 downto 0);
out_mule5 : out std_logic_vector(7 downto 0)
);
end component;
-- 02
component mul02
port (
in_mul02 : in std_logic_vector(7 downto 0);
out_mul02 : out std_logic_vector(7 downto 0)
);
end component;
-- a1
component mula1
port (
in_mula1 : in std_logic_vector(7 downto 0);
out_mula1 : out std_logic_vector(7 downto 0)
);
end component;
-- fc
component mulfc
port (
in_mulfc : in std_logic_vector(7 downto 0);
out_mulfc : out std_logic_vector(7 downto 0)
);
end component;
-- c1
component mulc1
port (
in_mulc1 : in std_logic_vector(7 downto 0);
out_mulc1 : out std_logic_vector(7 downto 0)
);
end component;
-- 47
component mul47
port (
in_mul47 : in std_logic_vector(7 downto 0);
out_mul47 : out std_logic_vector(7 downto 0)
);
end component;
-- ae
component mulae
port (
in_mulae : in std_logic_vector(7 downto 0);
out_mulae : out std_logic_vector(7 downto 0)
);
end component;
-- 3d
component mul3d
port (
in_mul3d : in std_logic_vector(7 downto 0);
out_mul3d : out std_logic_vector(7 downto 0)
);
end component;
-- 19
component mul19
port (
in_mul19 : in std_logic_vector(7 downto 0);
out_mul19 : out std_logic_vector(7 downto 0)
);
end component;
-- 03
component mul03
port (
in_mul03 : in std_logic_vector(7 downto 0);
out_mul03 : out std_logic_vector(7 downto 0)
);
end component;
-- declaring internal signals
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,
m16, m17, m18, m19, m20, m21, m22, m23, m24, m25, m26, m27, m28, m29, m30, m31 : std_logic_vector(7 downto 0);
signal s00,s01,s02,s03,s10,s11,s12,s13, s20, s21, s22, s23, s30, s31, s32, s33 : std_logic_vector(7 downto 0);
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
signal m16_01,m17_a4,m18_55,m19_87,m20_5a,m21_58,m22_db,m23_9e,
m16_a4,m17_56,m18_82,m19_f3,m20_1e,m21_c6,m22_68,m23_e5,
m16_02,m17_a1,m18_fc,m19_c1,m20_47,m21_ae,m22_3d,m23_19,
m16_a4_1,m17_55,m18_87,m19_5a,m20_58,m21_db,m22_9e,m23_03 : std_logic_vector(7 downto 0);
signal m24_01,m25_a4,m26_55,m27_87,m28_5a,m29_58,m30_db,m31_9e,
m24_a4,m25_56,m26_82,m27_f3,m28_1e,m29_c6,m30_68,m31_e5,
m24_02,m25_a1,m26_fc,m27_c1,m28_47,m29_ae,m30_3d,m31_19,
m24_a4_1,m25_55,m26_87,m27_5a,m28_58,m29_db,m30_9e,m31_03 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- first, we separate the input to the respective m
-- for s0j j=0..3
m0 <= in_rs256(7 downto 0);
m1 <= in_rs256(15 downto 8);
m2 <= in_rs256(23 downto 16);
m3 <= in_rs256(31 downto 24);
m4 <= in_rs256(39 downto 32);
m5 <= in_rs256(47 downto 40);
m6 <= in_rs256(55 downto 48);
m7 <= in_rs256(63 downto 56);
-- for s1j j=0..3
m8 <= in_rs256(71 downto 64);
m9 <= in_rs256(79 downto 72);
m10 <= in_rs256(87 downto 80);
m11 <= in_rs256(95 downto 88);
m12 <= in_rs256(103 downto 96);
m13 <= in_rs256(111 downto 104);
m14 <= in_rs256(119 downto 112);
m15 <= in_rs256(127 downto 120);
-- for s2j j=0..3
m16 <= in_rs256(135 downto 128);
m17 <= in_rs256(143 downto 136);
m18 <= in_rs256(151 downto 144);
m19 <= in_rs256(159 downto 152);
m20 <= in_rs256(167 downto 160);
m21 <= in_rs256(175 downto 168);
m22 <= in_rs256(183 downto 176);
m23 <= in_rs256(191 downto 184);
-- for s3j j=0..3
m24 <= in_rs256(199 downto 192);
m25 <= in_rs256(207 downto 200);
m26 <= in_rs256(215 downto 208);
m27 <= in_rs256(223 downto 216);
m28 <= in_rs256(231 downto 224);
m29 <= in_rs256(239 downto 232);
m30 <= in_rs256(247 downto 240);
m31 <= in_rs256(255 downto 248);
-- after separating signals, we drive them to multipliers
-- the first line of m0..7 forms s00
m0_with_01: mul01
port map (
in_mul01 => m0,
out_mul01 => m0_01
);
m1_with_a4: mula4
port map (
in_mula4 => m1,
out_mula4 => m1_a4
);
m2_with_55: mul55
port map (
in_mul55 => m2,
out_mul55 => m2_55
);
m3_with_87: mul87
port map (
in_mul87 => m3,
out_mul87 => m3_87
);
m4_with_5a: mul5a
port map (
in_mul5a => m4,
out_mul5a => m4_5a
);
m5_with_58: mul58
port map (
in_mul58 => m5,
out_mul58 => m5_58
);
m6_with_db: muldb
port map (
in_muldb => m6,
out_muldb => m6_db
);
m7_with_9e: mul9e
port map (
in_mul9e => m7,
out_mul9e => m7_9e
);
-- the second row creates s01
m0_with_a4: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4
);
m1_with_56: mul56
port map (
in_mul56 => m1,
out_mul56 => m1_56
);
m2_with_82: mul82
port map (
in_mul82 => m2,
out_mul82 => m2_82
);
m3_with_f3: mulf3
port map (
in_mulf3 => m3,
out_mulf3 => m3_f3
);
m4_with_1e: mul1e
port map (
in_mul1e => m4,
out_mul1e => m4_1e
);
m5_with_c6: mulc6
port map (
in_mulc6 => m5,
out_mulc6 => m5_c6
);
m6_with_68: mul68
port map (
in_mul68 => m6,
out_mul68 => m6_68
);
m7_with_e5: mule5
port map (
in_mule5 => m7,
out_mule5 => m7_e5
);
-- the third row creates s02
m0_with_02: mul02
port map (
in_mul02 => m0,
out_mul02 => m0_02
);
m1_with_a1: mula1
port map (
in_mula1 => m1,
out_mula1 => m1_a1
);
m2_with_fc: mulfc
port map (
in_mulfc => m2,
out_mulfc => m2_fc
);
m3_with_c1: mulc1
port map (
in_mulc1 => m3,
out_mulc1 => m3_c1
);
m4_with_47: mul47
port map (
in_mul47 => m4,
out_mul47 => m4_47
);
m5_with_ae: mulae
port map (
in_mulae => m5,
out_mulae => m5_ae
);
m6_with_3d: mul3d
port map (
in_mul3d => m6,
out_mul3d => m6_3d
);
m7_with_19: mul19
port map (
in_mul19 => m7,
out_mul19 => m7_19
);
-- the fourth row creates s03
m0_with_a4_1: mula4
port map (
in_mula4 => m0,
out_mula4 => m0_a4_1
);
m1_with_55: mul55
port map (
in_mul55 => m1,
out_mul55 => m1_55
);
m2_with_87: mul87
port map (
in_mul87 => m2,
out_mul87 => m2_87
);
m3_with_5a: mul5a
port map (
in_mul5a => m3,
out_mul5a => m3_5a
);
m4_with_58: mul58
port map (
in_mul58 => m4,
out_mul58 => m4_58
);
m5_with_db: muldb
port map (
in_muldb => m5,
out_muldb => m5_db
);
m6_with_9e: mul9e
port map (
in_mul9e => m6,
out_mul9e => m6_9e
);
m7_with_03: mul03
port map (
in_mul03 => m7,
out_mul03 => m7_03
);
-- we create the s1,j j=0..3
-- the first row of m8..15 creates the s10
m8_with_01: mul01
port map (
in_mul01 => m8,
out_mul01 => m8_01
);
m9_with_a4: mula4
port map (
in_mula4 => m9,
out_mula4 => m9_a4
);
m10_with_55: mul55
port map (
in_mul55 => m10,
out_mul55 => m10_55
);
m11_with_87: mul87
port map (
in_mul87 => m11,
out_mul87 => m11_87
);
m12_with_5a: mul5a
port map (
in_mul5a => m12,
out_mul5a => m12_5a
);
m13_with_58: mul58
port map (
in_mul58 => m13,
out_mul58 => m13_58
);
m14_with_db: muldb
port map (
in_muldb => m14,
out_muldb => m14_db
);
m15_with_9e: mul9e
port map (
in_mul9e => m15,
out_mul9e => m15_9e
);
-- the second row creates s11
m8_with_a4: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4
);
m9_with_56: mul56
port map (
in_mul56 => m9,
out_mul56 => m9_56
);
m10_with_82: mul82
port map (
in_mul82 => m10,
out_mul82 => m10_82
);
m11_with_f3: mulf3
port map (
in_mulf3 => m11,
out_mulf3 => m11_f3
);
m12_with_1e: mul1e
port map (
in_mul1e => m12,
out_mul1e => m12_1e
);
m13_with_c6: mulc6
port map (
in_mulc6 => m13,
out_mulc6 => m13_c6
);
m14_with_68: mul68
port map (
in_mul68 => m14,
out_mul68 => m14_68
);
m15_with_e5: mule5
port map (
in_mule5 => m15,
out_mule5 => m15_e5
);
-- the third row creates s12
m8_with_02: mul02
port map (
in_mul02 => m8,
out_mul02 => m8_02
);
m9_with_a1: mula1
port map (
in_mula1 => m9,
out_mula1 => m9_a1
);
m10_with_fc: mulfc
port map (
in_mulfc => m10,
out_mulfc => m10_fc
);
m11_with_c1: mulc1
port map (
in_mulc1 => m11,
out_mulc1 => m11_c1
);
m12_with_47: mul47
port map (
in_mul47 => m12,
out_mul47 => m12_47
);
m13_with_ae: mulae
port map (
in_mulae => m13,
out_mulae => m13_ae
);
m14_with_3d: mul3d
port map (
in_mul3d => m14,
out_mul3d => m14_3d
);
m15_with_19: mul19
port map (
in_mul19 => m15,
out_mul19 => m15_19
);
-- the fourth row creates s13
m8_with_a4_1: mula4
port map (
in_mula4 => m8,
out_mula4 => m8_a4_1
);
m9_with_55: mul55
port map (
in_mul55 => m9,
out_mul55 => m9_55
);
m10_with_87: mul87
port map (
in_mul87 => m10,
out_mul87 => m10_87
);
m11_with_5a: mul5a
port map (
in_mul5a => m11,
out_mul5a => m11_5a
);
m12_with_58: mul58
port map (
in_mul58 => m12,
out_mul58 => m12_58
);
m13_with_db: muldb
port map (
in_muldb => m13,
out_muldb => m13_db
);
m14_with_9e: mul9e
port map (
in_mul9e => m14,
out_mul9e => m14_9e
);
m15_with_03: mul03
port map (
in_mul03 => m15,
out_mul03 => m15_03
);
-- we create the s2,j j=0..3
-- the first row of m16..23 creates the s20
m16_with_01: mul01
port map (
in_mul01 => m16,
out_mul01 => m16_01
);
m17_with_a4: mula4
port map (
in_mula4 => m17,
out_mula4 => m17_a4
);
m18_with_55: mul55
port map (
in_mul55 => m18,
out_mul55 => m18_55
);
m19_with_87: mul87
port map (
in_mul87 => m19,
out_mul87 => m19_87
);
m20_with_5a: mul5a
port map (
in_mul5a => m20,
out_mul5a => m20_5a
);
m21_with_58: mul58
port map (
in_mul58 => m21,
out_mul58 => m21_58
);
m22_with_db: muldb
port map (
in_muldb => m22,
out_muldb => m22_db
);
m23_with_9e: mul9e
port map (
in_mul9e => m23,
out_mul9e => m23_9e
);
-- the second row creates s21
m16_with_a4: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4
);
m17_with_56: mul56
port map (
in_mul56 => m17,
out_mul56 => m17_56
);
m18_with_82: mul82
port map (
in_mul82 => m18,
out_mul82 => m18_82
);
m19_with_f3: mulf3
port map (
in_mulf3 => m19,
out_mulf3 => m19_f3
);
m20_with_1e: mul1e
port map (
in_mul1e => m20,
out_mul1e => m20_1e
);
m21_with_c6: mulc6
port map (
in_mulc6 => m21,
out_mulc6 => m21_c6
);
m22_with_68: mul68
port map (
in_mul68 => m22,
out_mul68 => m22_68
);
m23_with_e5: mule5
port map (
in_mule5 => m23,
out_mule5 => m23_e5
);
-- the third row creates s22
m16_with_02: mul02
port map (
in_mul02 => m16,
out_mul02 => m16_02
);
m17_with_a1: mula1
port map (
in_mula1 => m17,
out_mula1 => m17_a1
);
m18_with_fc: mulfc
port map (
in_mulfc => m18,
out_mulfc => m18_fc
);
m19_with_c1: mulc1
port map (
in_mulc1 => m19,
out_mulc1 => m19_c1
);
m20_with_47: mul47
port map (
in_mul47 => m20,
out_mul47 => m20_47
);
m21_with_ae: mulae
port map (
in_mulae => m21,
out_mulae => m21_ae
);
m22_with_3d: mul3d
port map (
in_mul3d => m22,
out_mul3d => m22_3d
);
m23_with_19: mul19
port map (
in_mul19 => m23,
out_mul19 => m23_19
);
-- the fourth row creates s23
m16_with_a4_1: mula4
port map (
in_mula4 => m16,
out_mula4 => m16_a4_1
);
m17_with_55: mul55
port map (
in_mul55 => m17,
out_mul55 => m17_55
);
m18_with_87: mul87
port map (
in_mul87 => m18,
out_mul87 => m18_87
);
m19_with_5a: mul5a
port map (
in_mul5a => m19,
out_mul5a => m19_5a
);
m20_with_58: mul58
port map (
in_mul58 => m20,
out_mul58 => m20_58
);
m21_with_db: muldb
port map (
in_muldb => m21,
out_muldb => m21_db
);
m22_with_9e: mul9e
port map (
in_mul9e => m22,
out_mul9e => m22_9e
);
m23_with_03: mul03
port map (
in_mul03 => m23,
out_mul03 => m23_03
);
-- we create the s3j j=0..3
-- the first row of m24..31 creates the s30
m24_with_01: mul01
port map (
in_mul01 => m24,
out_mul01 => m24_01
);
m25_with_a4: mula4
port map (
in_mula4 => m25,
out_mula4 => m25_a4
);
m26_with_55: mul55
port map (
in_mul55 => m26,
out_mul55 => m26_55
);
m27_with_87: mul87
port map (
in_mul87 => m27,
out_mul87 => m27_87
);
m28_with_5a: mul5a
port map (
in_mul5a => m28,
out_mul5a => m28_5a
);
m29_with_58: mul58
port map (
in_mul58 => m29,
out_mul58 => m29_58
);
m30_with_db: muldb
port map (
in_muldb => m30,
out_muldb => m30_db
);
m31_with_9e: mul9e
port map (
in_mul9e => m31,
out_mul9e => m31_9e
);
-- the second row creates s31
m24_with_a4: mula4
port map (
in_mula4 => m24,
out_mula4 => m24_a4
);
m25_with_56: mul56
port map (
in_mul56 => m25,
out_mul56 => m25_56
);
m26_with_82: mul82
port map (
in_mul82 => m26,
out_mul82 => m26_82
);
m27_with_f3: mulf3
port map (
in_mulf3 => m27,
out_mulf3 => m27_f3
);
m28_with_1e: mul1e
port map (
in_mul1e => m28,
out_mul1e => m28_1e
);
m29_with_c6: mulc6
port map (
in_mulc6 => m29,
out_mulc6 => m29_c6
);
m30_with_68: mul68
port map (
in_mul68 => m30,
out_mul68 => m30_68
);
m31_with_e5: mule5
port map (
in_mule5 => m31,
out_mule5 => m31_e5
);
-- the third row creates s32
m24_with_02: mul02
port map (
in_mul02 => m24,
out_mul02 => m24_02
);
m25_with_a1: mula1
port map (
in_mula1 => m25,
out_mula1 => m25_a1
);
m26_with_fc: mulfc
port map (
in_mulfc => m26,
out_mulfc => m26_fc
);
m27_with_c1: mulc1
port map (
in_mulc1 => m27,
out_mulc1 => m27_c1
);
m28_with_47: mul47
port map (
in_mul47 => m28,
out_mul47 => m28_47
);
m29_with_ae: mulae
port map (
in_mulae => m29,
out_mulae => m29_ae
);
m30_with_3d: mul3d
port map (
in_mul3d => m30,
out_mul3d => m30_3d
);
m31_with_19: mul19
port map (
in_mul19 => m31,
out_mul19 => m31_19
);
-- the fourth row creates s33
m24_with_a4_1: mula4
port map (
in_mula4 => m24,
out_mula4 => m24_a4_1
);
m25_with_55: mul55
port map (
in_mul55 => m25,
out_mul55 => m25_55
);
m26_with_87: mul87
port map (
in_mul87 => m26,
out_mul87 => m26_87
);
m27_with_5a: mul5a
port map (
in_mul5a => m27,
out_mul5a => m27_5a
);
m28_with_58: mul58
port map (
in_mul58 => m28,
out_mul58 => m28_58
);
m29_with_db: muldb
port map (
in_muldb => m29,
out_muldb => m29_db
);
m30_with_9e: mul9e
port map (
in_mul9e => m30,
out_mul9e => m30_9e
);
m31_with_03: mul03
port map (
in_mul03 => m31,
out_mul03 => m31_03
);
-- after getting the results from multipliers
-- we combine them in order to get the additions
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
-- after creating s0,j j=0...3 we form the S0
-- little endian
out_Sfirst_rs256 <= s03 & s02 & s01 & s00;
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
-- after creating s1,j j=0...3 we form the S1
-- little endian
out_Ssecond_rs256 <= s13 & s12 & s11 & s10;
s20 <= m16_01 XOR m17_a4 XOR m18_55 XOR m19_87 XOR m20_5a XOR m21_58 XOR m22_db XOR m23_9e;
s21 <= m16_a4 XOR m17_56 XOR m18_82 XOR m19_f3 XOR m20_1e XOR m21_c6 XOR m22_68 XOR m23_e5;
s22 <= m16_02 XOR m17_a1 XOR m18_fc XOR m19_c1 XOR m20_47 XOR m21_ae XOR m22_3d XOR m23_19;
s23 <= m16_a4_1 XOR m17_55 XOR m18_87 XOR m19_5a XOR m20_58 XOR m21_db XOR m22_9e XOR m23_03;
-- after creating s2j j=0...3 we form the S2
-- little endian
out_Sthird_rs256 <= s23 & s22 & s21 & s20;
s30 <= m24_01 XOR m25_a4 XOR m26_55 XOR m27_87 XOR m28_5a XOR m29_58 XOR m30_db XOR m31_9e;
s31 <= m24_a4 XOR m25_56 XOR m26_82 XOR m27_f3 XOR m28_1e XOR m29_c6 XOR m30_68 XOR m31_e5;
s32 <= m24_02 XOR m25_a1 XOR m26_fc XOR m27_c1 XOR m28_47 XOR m29_ae XOR m30_3d XOR m31_19;
s33 <= m24_a4_1 XOR m25_55 XOR m26_87 XOR m27_5a XOR m28_58 XOR m29_db XOR m30_9e XOR m31_03;
-- after creating s3j j=0...3 we form the S3
-- little endian
out_Sfourth_rs256 <= s33 & s32 & s31 & s30;
end rs_256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- h function for 256 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity h_256 is
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end h_256;
architecture h256_arch of h_256 is
-- we declare internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
from_fourth_row,
to_fifth_row,
to_mds : std_logic_vector(31 downto 0);
-- we declare all components needed
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_h256,
out_q1 => from_first_row(7 downto 0)
);
first_q0_1: q0
port map (
in_q0 => in_h256,
out_q0 => from_first_row(15 downto 8)
);
first_q0_2: q0
port map (
in_q0 => in_h256,
out_q0 => from_first_row(23 downto 16)
);
first_q1_2: q1
port map (
in_q1 => in_h256,
out_q1 => from_first_row(31 downto 24)
);
-- we perform the XOR of the results of the first row
-- with first M of h (Mfirst_h256)
to_second_row <= from_first_row XOR Mfirst_h256;
-- second row of q
second_q1_1: q1
port map (
in_q1 => to_second_row(7 downto 0),
out_q1 => from_second_row(7 downto 0)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
second_q0_1: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(31 downto 24),
out_q0 => from_second_row(31 downto 24)
);
-- we perform the XOR of the results of the second row
-- with second M of h (Msecond_h256)
to_third_row <= from_second_row XOR Msecond_h256;
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(15 downto 8),
out_q1 => from_third_row(15 downto 8)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(23 downto 16),
out_q0 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
-- we perform the XOR of the results of the third row
-- with third M of h (Mthird_h256)
to_fourth_row <= from_third_row XOR Mthird_h256;
-- fourth row of q
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(7 downto 0),
out_q0 => from_fourth_row(7 downto 0)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => from_fourth_row(15 downto 8)
);
fourth_q1_1: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => from_fourth_row(23 downto 16)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(31 downto 24),
out_q1 => from_fourth_row(31 downto 24)
);
-- we perform the fourth XOR
to_fifth_row <= from_fourth_row XOR Mfourth_h256;
-- the fifth row of q
fifth_q1_1: q1
port map (
in_q1 => to_fifth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fifth_q0_1: q0
port map (
in_q0 => to_fifth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fifth_q1_2: q1
port map (
in_q1 => to_fifth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fifth_q0_2: q0
port map (
in_q0 => to_fifth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_h256(7 downto 0),
z1 => out_h256(15 downto 8),
z2 => out_h256(23 downto 16),
z3 => out_h256(31 downto 24)
);
end h256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- g function for 256 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity g_256 is
port (
in_g256,
in_S0_g256,
in_S1_g256,
in_S2_g256,
in_S3_g256 : in std_logic_vector(31 downto 0);
out_g256 : out std_logic_vector(31 downto 0)
);
end g_256;
architecture g256_arch of g_256 is
-- we declare the internal signals
signal from_first_row,
to_second_row,
from_second_row,
to_third_row,
from_third_row,
to_fourth_row,
from_fourth_row,
to_fifth_row,
to_mds : std_logic_vector(31 downto 0);
component q0
port (
in_q0 : in std_logic_vector(7 downto 0);
out_q0 : out std_logic_vector(7 downto 0)
);
end component;
component q1
port (
in_q1 : in std_logic_vector(7 downto 0);
out_q1 : out std_logic_vector(7 downto 0)
);
end component;
component mds
port (
y0,
y1,
y2,
y3 : in std_logic_vector(7 downto 0);
z0,
z1,
z2,
z3 : out std_logic_vector(7 downto 0)
);
end component;
-- begin architecture description
begin
-- first row of q
first_q1_1: q1
port map (
in_q1 => in_g256(7 downto 0),
out_q1 => from_first_row(7 downto 0)
);
first_q0_1: q0
port map (
in_q0 => in_g256(15 downto 8),
out_q0 => from_first_row(15 downto 8)
);
first_q0_2: q0
port map (
in_q0 => in_g256(23 downto 16),
out_q0 => from_first_row(23 downto 16)
);
first_q1_2: q1
port map (
in_q1 => in_g256(31 downto 24),
out_q1 => from_first_row(31 downto 24)
);
-- we perform the XOR of the results of the first row
-- with S0
to_second_row <= from_first_row XOR in_S0_g256;
-- second row of q
second_q1_1: q1
port map (
in_q1 => to_second_row(7 downto 0),
out_q1 => from_second_row(7 downto 0)
);
second_q1_2: q1
port map (
in_q1 => to_second_row(15 downto 8),
out_q1 => from_second_row(15 downto 8)
);
second_q0_1: q0
port map (
in_q0 => to_second_row(23 downto 16),
out_q0 => from_second_row(23 downto 16)
);
second_q0_2: q0
port map (
in_q0 => to_second_row(31 downto 24),
out_q0 => from_second_row(31 downto 24)
);
-- we perform the XOR of the results of the second row
-- with S1
to_third_row <= from_second_row XOR in_S1_g256;
-- third row of q
third_q0_1: q0
port map (
in_q0 => to_third_row(7 downto 0),
out_q0 => from_third_row(7 downto 0)
);
third_q1_1: q1
port map (
in_q1 => to_third_row(15 downto 8),
out_q1 => from_third_row(15 downto 8)
);
third_q0_2: q0
port map (
in_q0 => to_third_row(23 downto 16),
out_q0 => from_third_row(23 downto 16)
);
third_q1_2: q1
port map (
in_q1 => to_third_row(31 downto 24),
out_q1 => from_third_row(31 downto 24)
);
-- we perform the XOR of the results of the third row
-- with S2
to_fourth_row <= from_third_row XOR in_S2_g256;
-- fourth row of q
fourth_q0_1: q0
port map (
in_q0 => to_fourth_row(7 downto 0),
out_q0 => from_fourth_row(7 downto 0)
);
fourth_q0_2: q0
port map (
in_q0 => to_fourth_row(15 downto 8),
out_q0 => from_fourth_row(15 downto 8)
);
fourth_q1_1: q1
port map (
in_q1 => to_fourth_row(23 downto 16),
out_q1 => from_fourth_row(23 downto 16)
);
fourth_q1_2: q1
port map (
in_q1 => to_fourth_row(31 downto 24),
out_q1 => from_fourth_row(31 downto 24)
);
-- we perform the fourth XOR
to_fifth_row <= from_fourth_row XOR in_S3_g256;
-- the fifth row of q
fifth_q1_1: q1
port map (
in_q1 => to_fifth_row(7 downto 0),
out_q1 => to_mds(7 downto 0)
);
fifth_q0_1: q0
port map (
in_q0 => to_fifth_row(15 downto 8),
out_q0 => to_mds(15 downto 8)
);
fifth_q1_2: q1
port map (
in_q1 => to_fifth_row(23 downto 16),
out_q1 => to_mds(23 downto 16)
);
fifth_q0_2: q0
port map (
in_q0 => to_fifth_row(31 downto 24),
out_q0 => to_mds(31 downto 24)
);
-- mds table
mds_table: mds
port map (
y0 => to_mds(7 downto 0),
y1 => to_mds(15 downto 8),
y2 => to_mds(23 downto 16),
y3 => to_mds(31 downto 24),
z0 => out_g256(7 downto 0),
z1 => out_g256(15 downto 8),
z2 => out_g256(23 downto 16),
z3 => out_g256(31 downto 24)
);
end g256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- f function with 256 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity f_256 is
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end f_256;
architecture f256_arch of f_256 is
-- we declare the internal signals
signal from_shift_8,
to_up_pht,
to_low_pht,
to_up_key,
to_low_key,
intermediate_carry1,
intermediate_carry2 : std_logic_vector(31 downto 0);
signal zero : std_logic;
component g_256
port (
in_g256,
in_S0_g256,
in_S1_g256,
in_S2_g256,
in_S3_g256 : in std_logic_vector(31 downto 0);
out_g256 : out std_logic_vector(31 downto 0)
);
end component;
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component adder
port (
in1_adder,
in2_adder,
in_carry_adder : in std_logic;
out_adder,
out_carry_adder : out std_logic
);
end component;
-- begin architecture description
begin
-- we initialize zero
zero <= '0';
-- upper g_256
upper_g256: g_256
port map (
in_g256 => up_in_f256,
in_S0_g256 => S0_in_f256,
in_S1_g256 => S1_in_f256,
in_S2_g256 => S2_in_f256,
in_S3_g256 => S3_in_f256,
out_g256 => to_up_pht
);
-- left rotation by 8
from_shift_8(31 downto 8) <= low_in_f256(23 downto 0);
from_shift_8(7 downto 0) <= low_in_f256(31 downto 24);
-- lower g256
lower_g256: g_256
port map (
in_g256 => from_shift_8,
in_S0_g256 => S0_in_f256,
in_S1_g256 => S1_in_f256,
in_S2_g256 => S2_in_f256,
in_S3_g256 => S3_in_f256,
out_g256 => to_low_pht
);
-- pht
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => to_low_pht,
up_out_pht => to_up_key,
down_out_pht => to_low_key
);
-- upper adder of 32 bits
up_adder: for i in 0 to 31 generate
first: if (i=0) generate
the_adder: adder
port map (
in1_adder => to_up_key(0),
in2_adder => up_key_f256(0),
in_carry_adder => zero,
out_adder => up_out_f256(0),
out_carry_adder => intermediate_carry1(0)
);
end generate first;
the_rest: if (i>0) generate
the_adders: adder
port map (
in1_adder => to_up_key(i),
in2_adder => up_key_f256(i),
in_carry_adder => intermediate_carry1(i-1),
out_adder => up_out_f256(i),
out_carry_adder => intermediate_carry1(i)
);
end generate the_rest;
end generate up_adder;
-- lower adder of 32 bits
low_adder: for i in 0 to 31 generate
first1: if (i=0) generate
the_adder1:adder
port map (
in1_adder => to_low_key(0),
in2_adder => low_key_f256(0),
in_carry_adder => zero,
out_adder => low_out_f256(0),
out_carry_adder => intermediate_carry2(0)
);
end generate first1;
the_rest1: if (i>0) generate
the_adders1: adder
port map (
in1_adder => to_low_key(i),
in2_adder => low_key_f256(i),
in_carry_adder => intermediate_carry2(i-1),
out_adder => low_out_f256(i),
out_carry_adder => intermediate_carry2(i)
);
end generate the_rest1;
end generate low_adder;
end f256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish key scheduler for 256 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_keysched256 is
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end twofish_keysched256;
architecture twofish_keysched256_arch of twofish_keysched256 is
-- we declare internal signals
signal to_up_pht,
to_shift_8,
from_shift_8,
to_shift_9,
M0, M1, M2, M3, M4, M5, M6, M7 : std_logic_vector(31 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_256
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we assign the input signal to the respective
-- bytes as is described in the prototype
-- splitting the input
byte31 <= in_key_tk256(7 downto 0);
byte30 <= in_key_tk256(15 downto 8);
byte29 <= in_key_tk256(23 downto 16);
byte28 <= in_key_tk256(31 downto 24);
byte27 <= in_key_tk256(39 downto 32);
byte26 <= in_key_tk256(47 downto 40);
byte25 <= in_key_tk256(55 downto 48);
byte24 <= in_key_tk256(63 downto 56);
byte23 <= in_key_tk256(71 downto 64);
byte22 <= in_key_tk256(79 downto 72);
byte21 <= in_key_tk256(87 downto 80);
byte20 <= in_key_tk256(95 downto 88);
byte19 <= in_key_tk256(103 downto 96);
byte18 <= in_key_tk256(111 downto 104);
byte17 <= in_key_tk256(119 downto 112);
byte16 <= in_key_tk256(127 downto 120);
byte15 <= in_key_tk256(135 downto 128);
byte14 <= in_key_tk256(143 downto 136);
byte13 <= in_key_tk256(151 downto 144);
byte12 <= in_key_tk256(159 downto 152);
byte11 <= in_key_tk256(167 downto 160);
byte10 <= in_key_tk256(175 downto 168);
byte9 <= in_key_tk256(183 downto 176);
byte8 <= in_key_tk256(191 downto 184);
byte7 <= in_key_tk256(199 downto 192);
byte6 <= in_key_tk256(207 downto 200);
byte5 <= in_key_tk256(215 downto 208);
byte4 <= in_key_tk256(223 downto 216);
byte3 <= in_key_tk256(231 downto 224);
byte2 <= in_key_tk256(239 downto 232);
byte1 <= in_key_tk256(247 downto 240);
byte0 <= in_key_tk256(255 downto 248);
-- we form the M{0..7}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
M6 <= byte27 & byte26 & byte25 & byte24;
M7 <= byte31 & byte30 & byte29 & byte28;
-- upper h
upper_h: h_256
port map (
in_h256 => even_in_tk256,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht
);
-- lower h
lower_h: h_256
port map (
in_h256 => odd_in_tk256,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8
);
-- left rotate by 8
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
-- pht transformation
pht_transform: pht
port map (
up_in_pht => to_up_pht,
down_in_pht => from_shift_8,
up_out_pht => out_key_up_tk256,
down_out_pht => to_shift_9
);
-- left rotate by 9
out_key_down_tk256(31 downto 9) <= to_shift_9(22 downto 0);
out_key_down_tk256(8 downto 0) <= to_shift_9(31 downto 23);
end twofish_keysched256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish S key component for 256 bits key
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_S256 is
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end twofish_S256;
architecture twofish_S256_arch of twofish_S256 is
-- we declare the components to be used
component reed_solomon256
port (
in_rs256 : in std_logic_vector(255 downto 0);
out_Sfirst_rs256,
out_Ssecond_rs256,
out_Sthird_rs256,
out_Sfourth_rs256 : out std_logic_vector(31 downto 0)
);
end component;
signal twofish_key : std_logic_vector(255 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
-- begin architecture description
begin
-- splitting the input
byte31 <= in_key_ts256(7 downto 0);
byte30 <= in_key_ts256(15 downto 8);
byte29 <= in_key_ts256(23 downto 16);
byte28 <= in_key_ts256(31 downto 24);
byte27 <= in_key_ts256(39 downto 32);
byte26 <= in_key_ts256(47 downto 40);
byte25 <= in_key_ts256(55 downto 48);
byte24 <= in_key_ts256(63 downto 56);
byte23 <= in_key_ts256(71 downto 64);
byte22 <= in_key_ts256(79 downto 72);
byte21 <= in_key_ts256(87 downto 80);
byte20 <= in_key_ts256(95 downto 88);
byte19 <= in_key_ts256(103 downto 96);
byte18 <= in_key_ts256(111 downto 104);
byte17 <= in_key_ts256(119 downto 112);
byte16 <= in_key_ts256(127 downto 120);
byte15 <= in_key_ts256(135 downto 128);
byte14 <= in_key_ts256(143 downto 136);
byte13 <= in_key_ts256(151 downto 144);
byte12 <= in_key_ts256(159 downto 152);
byte11 <= in_key_ts256(167 downto 160);
byte10 <= in_key_ts256(175 downto 168);
byte9 <= in_key_ts256(183 downto 176);
byte8 <= in_key_ts256(191 downto 184);
byte7 <= in_key_ts256(199 downto 192);
byte6 <= in_key_ts256(207 downto 200);
byte5 <= in_key_ts256(215 downto 208);
byte4 <= in_key_ts256(223 downto 216);
byte3 <= in_key_ts256(231 downto 224);
byte2 <= in_key_ts256(239 downto 232);
byte1 <= in_key_ts256(247 downto 240);
byte0 <= in_key_ts256(255 downto 248);
-- forming the key
twofish_key <= byte31 & byte30 & byte29 & byte28 & byte27 & byte26 & byte25 & byte24 &
byte23 & byte22 & byte21 & byte20 & byte19 & byte18 & byte17 & byte16 &
byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
-- the keys S0,1,2,3
produce_S0_S1_S2_S3: reed_solomon256
port map (
in_rs256 => twofish_key,
out_Sfirst_rs256 => out_Sfirst_ts256,
out_Ssecond_rs256 => out_Ssecond_ts256,
out_Sthird_rs256 => out_Sthird_ts256,
out_Sfourth_rs256 => out_Sfourth_ts256
);
end twofish_S256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish whitening key scheduler for 256 bits key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_whit_keysched256 is
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end twofish_whit_keysched256;
architecture twofish_whit_keysched256_arch of twofish_whit_keysched256 is
-- we declare internal signals
signal to_up_pht_1,
to_shift_8_1,
from_shift_8_1,
to_shift_9_1,
to_up_pht_2,
to_shift_8_2,
from_shift_8_2,
to_shift_9_2,
to_up_pht_3,
to_shift_8_3,
from_shift_8_3,
to_shift_9_3,
to_up_pht_4,
to_shift_8_4,
from_shift_8_4,
to_shift_9_4,
M0, M1, M2, M3, M4, M5, M6, M7 : std_logic_vector(31 downto 0);
signal byte15, byte14, byte13, byte12, byte11, byte10,
byte9, byte8, byte7, byte6, byte5, byte4,
byte3, byte2, byte1, byte0,
byte16, byte17, byte18, byte19,
byte20, byte21, byte22, byte23,
byte24, byte25, byte26, byte27,
byte28, byte29, byte30, byte31 : std_logic_vector(7 downto 0);
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
-- we declare the components to be used
component pht
port (
up_in_pht,
down_in_pht : in std_logic_vector(31 downto 0);
up_out_pht,
down_out_pht : out std_logic_vector(31 downto 0)
);
end component;
component h_256
port (
in_h256 : in std_logic_vector(7 downto 0);
Mfirst_h256,
Msecond_h256,
Mthird_h256,
Mfourth_h256 : in std_logic_vector(31 downto 0);
out_h256 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we produce the first eight numbers
zero <= "00000000";
one <= "00000001";
two <= "00000010";
three <= "00000011";
four <= "00000100";
five <= "00000101";
six <= "00000110";
seven <= "00000111";
-- we assign the input signal to the respective
-- bytes as is described in the prototype
byte31 <= in_key_twk256(7 downto 0);
byte30 <= in_key_twk256(15 downto 8);
byte29 <= in_key_twk256(23 downto 16);
byte28 <= in_key_twk256(31 downto 24);
byte27 <= in_key_twk256(39 downto 32);
byte26 <= in_key_twk256(47 downto 40);
byte25 <= in_key_twk256(55 downto 48);
byte24 <= in_key_twk256(63 downto 56);
byte23 <= in_key_twk256(71 downto 64);
byte22 <= in_key_twk256(79 downto 72);
byte21 <= in_key_twk256(87 downto 80);
byte20 <= in_key_twk256(95 downto 88);
byte19 <= in_key_twk256(103 downto 96);
byte18 <= in_key_twk256(111 downto 104);
byte17 <= in_key_twk256(119 downto 112);
byte16 <= in_key_twk256(127 downto 120);
byte15 <= in_key_twk256(135 downto 128);
byte14 <= in_key_twk256(143 downto 136);
byte13 <= in_key_twk256(151 downto 144);
byte12 <= in_key_twk256(159 downto 152);
byte11 <= in_key_twk256(167 downto 160);
byte10 <= in_key_twk256(175 downto 168);
byte9 <= in_key_twk256(183 downto 176);
byte8 <= in_key_twk256(191 downto 184);
byte7 <= in_key_twk256(199 downto 192);
byte6 <= in_key_twk256(207 downto 200);
byte5 <= in_key_twk256(215 downto 208);
byte4 <= in_key_twk256(223 downto 216);
byte3 <= in_key_twk256(231 downto 224);
byte2 <= in_key_twk256(239 downto 232);
byte1 <= in_key_twk256(247 downto 240);
byte0 <= in_key_twk256(255 downto 248);
-- we form the M{0..7}
M0 <= byte3 & byte2 & byte1 & byte0;
M1 <= byte7 & byte6 & byte5 & byte4;
M2 <= byte11 & byte10 & byte9 & byte8;
M3 <= byte15 & byte14 & byte13 & byte12;
M4 <= byte19 & byte18 & byte17 & byte16;
M5 <= byte23 & byte22 & byte21 & byte20;
M6 <= byte27 & byte26 & byte25 & byte24;
M7 <= byte31 & byte30 & byte29 & byte28;
-- we produce the keys for the whitening steps
-- keys K0,1
-- upper h
upper_h1: h_256
port map (
in_h256 => zero,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_1
);
-- lower h
lower_h1: h_256
port map (
in_h256 => one,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_1
);
-- left rotate by 8
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
-- pht transformation
pht_transform1: pht
port map (
up_in_pht => to_up_pht_1,
down_in_pht => from_shift_8_1,
up_out_pht => out_K0_twk256,
down_out_pht => to_shift_9_1
);
-- left rotate by 9
out_K1_twk256(31 downto 9) <= to_shift_9_1(22 downto 0);
out_K1_twk256(8 downto 0) <= to_shift_9_1(31 downto 23);
-- keys K2,3
-- upper h
upper_h2: h_256
port map (
in_h256 => two,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_2
);
-- lower h
lower_h2: h_256
port map (
in_h256 => three,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_2
);
-- left rotate by 8
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
-- pht transformation
pht_transform2: pht
port map (
up_in_pht => to_up_pht_2,
down_in_pht => from_shift_8_2,
up_out_pht => out_K2_twk256,
down_out_pht => to_shift_9_2
);
-- left rotate by 9
out_K3_twk256(31 downto 9) <= to_shift_9_2(22 downto 0);
out_K3_twk256(8 downto 0) <= to_shift_9_2(31 downto 23);
-- keys K4,5
-- upper h
upper_h3: h_256
port map (
in_h256 => four,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_3
);
-- lower h
lower_h3: h_256
port map (
in_h256 => five,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_3
);
-- left rotate by 8
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
-- pht transformation
pht_transform3: pht
port map (
up_in_pht => to_up_pht_3,
down_in_pht => from_shift_8_3,
up_out_pht => out_K4_twk256,
down_out_pht => to_shift_9_3
);
-- left rotate by 9
out_K5_twk256(31 downto 9) <= to_shift_9_3(22 downto 0);
out_K5_twk256(8 downto 0) <= to_shift_9_3(31 downto 23);
-- keys K6,7
-- upper h
upper_h4: h_256
port map (
in_h256 => six,
Mfirst_h256 => M6,
Msecond_h256 => M4,
Mthird_h256 => M2,
Mfourth_h256 => M0,
out_h256 => to_up_pht_4
);
-- lower h
lower_h4: h_256
port map (
in_h256 => seven,
Mfirst_h256 => M7,
Msecond_h256 => M5,
Mthird_h256 => M3,
Mfourth_h256 => M1,
out_h256 => to_shift_8_4
);
-- left rotate by 8
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
-- pht transformation
pht_transform4: pht
port map (
up_in_pht => to_up_pht_4,
down_in_pht => from_shift_8_4,
up_out_pht => out_K6_twk256,
down_out_pht => to_shift_9_4
);
-- left rotate by 9
out_K7_twk256(31 downto 9) <= to_shift_9_4(22 downto 0);
out_K7_twk256(8 downto 0) <= to_shift_9_4(31 downto 23);
end twofish_whit_keysched256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish encryption round with 256 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_encryption_round256 is
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end twofish_encryption_round256;
architecture twofish_encryption_round256_arch of twofish_encryption_round256 is
-- we declare internal signals
signal to_left_shift,
from_right_shift,
to_xor_with3,
to_xor_with4 : std_logic_vector(31 downto 0);
component f_256
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end component;
-- begin architecture description
begin
-- we declare f_256
function_f: f_256
port map (
up_in_f256 => in1_ter256,
low_in_f256 => in2_ter256,
S0_in_f256 => in_Sfirst_ter256,
S1_in_f256 => in_Ssecond_ter256,
S2_in_f256 => in_Sthird_ter256,
S3_in_f256 => in_Sfourth_ter256,
up_key_f256 => in_key_up_ter256,
low_key_f256 => in_key_down_ter256,
up_out_f256 => to_xor_with3,
low_out_f256 => to_xor_with4
);
-- we perform the exchange
-- in1_ter256 -> out3_ter256
-- in2_ter256 -> out4_ter256
-- in3_ter256 -> out1_ter256
-- in4_ter256 -> out2_ter256
-- we perform the left xor between the upper f function and
-- the third input (input 3)
to_left_shift <= to_xor_with3 XOR in3_ter256;
-- we perform the left side rotation to the right by 1 and
-- we perform the exchange too
out1_ter256(30 downto 0) <= to_left_shift(31 downto 1);
out1_ter256(31) <= to_left_shift(0);
-- we perform the right side rotation to the left by 1
from_right_shift(0) <= in4_ter256(31);
from_right_shift(31 downto 1) <= in4_ter256(30 downto 0);
-- we perform the right xor between the lower f function and
-- the fourth input (input 4)
out2_ter256 <= from_right_shift XOR to_xor_with4;
-- we perform the last exchanges
out3_ter256 <= in1_ter256;
out4_ter256 <= in2_ter256;
end twofish_encryption_round256_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- twofish decryption round with 256 bit key input
--
library ieee;
use ieee.std_logic_1164.all;
entity twofish_decryption_round256 is
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end twofish_decryption_round256;
architecture twofish_decryption_round256_arch of twofish_decryption_round256 is
signal to_xor_with3,
to_xor_with4,
to_xor_with_up_f,
from_xor_with_down_f : std_logic_vector(31 downto 0);
component f_256
port (
up_in_f256,
low_in_f256,
S0_in_f256,
S1_in_f256,
S2_in_f256,
S3_in_f256,
up_key_f256,
low_key_f256 : in std_logic_vector(31 downto 0);
up_out_f256,
low_out_f256 : out std_logic_vector(31 downto 0)
);
end component;
begin
-- we instantiate f function
function_f: f_256
port map (
up_in_f256 => in1_tdr256,
low_in_f256 => in2_tdr256,
S0_in_f256 => in_Sfirst_tdr256,
S1_in_f256 => in_Ssecond_tdr256,
S2_in_f256 => in_Sthird_tdr256,
S3_in_f256 => in_Sfourth_tdr256,
up_key_f256 => in_key_up_tdr256,
low_key_f256 => in_key_down_tdr256,
up_out_f256 => to_xor_with3,
low_out_f256 => to_xor_with4
);
-- output 1: input3 with upper f
-- we first rotate the input3 by 1 bit leftwise
to_xor_with_up_f(0) <= in3_tdr256(31);
to_xor_with_up_f(31 downto 1) <= in3_tdr256(30 downto 0);
-- we perform the XOR with the upper output of f and the result
-- is ouput 1
out1_tdr256 <= to_xor_with_up_f XOR to_xor_with3;
-- output 2: input4 with lower f
-- we perform the XOR with the lower output of f
from_xor_with_down_f <= in4_tdr256 XOR to_xor_with4;
-- we perform the rotation by 1 bit rightwise and the result
-- is output2
out2_tdr256(31) <= from_xor_with_down_f(0);
out2_tdr256(30 downto 0) <= from_xor_with_down_f(31 downto 1);
-- we assign outputs 3 and 4
out3_tdr256 <= in1_tdr256;
out4_tdr256 <= in2_tdr256;
end twofish_decryption_round256_arch;
| gpl-2.0 | 5fa6a5fe18f9a09c548e6e4435d46e31 | 0.563887 | 2.376384 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_skid_buf.vhd | 1 | 21,110 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_skid_buf.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamover_skid_buf.vhd
-- ^^^^^^
--
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- -- Per CR593362
-- - Removed resets from the data path of the Skid and Output registers.
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 512 := 32
-- Width of the Stream Data bus (in bits)
);
port (
---------------------------------------------------------------------------
-- System Ports
---------------------------------------------------------------------------
aclk : In std_logic ; -- Clock input
arst : In std_logic ; -- Reset input
---------------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse)
---------------------------------------------------------------------------
skid_stop : In std_logic ; -- Stop Control
---------------------------------------------------------------------------
-- Slave Side (Stream Data Input)
---------------------------------------------------------------------------
s_valid : In std_logic ; -- AXI4 Slave Stream
s_ready : Out std_logic ; -- AXI4 Slave Stream
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- AXI4 Slave Stream
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0);-- AXI4 Slave Stream
s_last : In std_logic ; -- AXI4 Slave Stream
---------------------------------------------------------------------------
-- Master Side (Stream Data Output
---------------------------------------------------------------------------
m_valid : Out std_logic ; -- AXI4 Master Stream
m_ready : In std_logic ; -- AXI4 Master Stream
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- AXI4 Master Stream
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- AXI4 Master Stream
m_last : Out std_logic -- AXI4 Master Stream
);
end entity axi_master_burst_skid_buf;
architecture implementation of axi_master_burst_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (aclk)
begin
if (aclk'event and aclk = '1') then
sig_reset_reg <= arst;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the skid register for the
-- Skid Buffer Data signals. Note that reset has been removed
-- to reduce route of resets for very wide data buses.
--
-------------------------------------------------------------
SKID_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the skid registers for the
-- Skid Buffer control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the output register for the
-- Skid Buffer Data signals. Note that reset has been removed
-- to reduce route of resets for very wide data buses.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_mvalid_stop_reg = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
-- coverage off
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_sready_stop_reg <= '0';
-- coverage off
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_mvalid_stop_reg <= '0';
-- coverage off
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| apache-2.0 | 44a17c096a742ebe2c47917e4bc271aa | 0.467314 | 4.50972 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl16_fifo.vhd | 15 | 13,201 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_adder;
use proc_common_v4_0.pf_counter_top;
use proc_common_v4_0.pf_occ_counter_top;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity proc_common_v4_0.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity proc_common_v4_0.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity proc_common_v4_0.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| apache-2.0 | c76435d451814b99a1d3271f7136d171 | 0.457465 | 4.41505 | false | false | false | false |
rcls/sdr | vhdl/multifilter.vhd | 1 | 2,749 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
-- Multiplex streams through the filter (currently four). One sample is
-- processed every four clock cycles, i.e., each stream gets 1 every
-- 16 cycles. The provider of the data should have carried out the second order
-- summation; we do the second order differencing. We output
-- x(t)-x(t-236)-x(t-244)+x(t-480)
-- with a latency of four (?) clock cycles, and t incrementing once every 4
-- cycles.
--
-- Phase 0: acc = -x(t-59*4), start load x(t-120*4), output prev,
-- Phase 1: acc -= x(t-61*4), start load x(t).
-- Phase 2: acc += x(t-120*4), start load x(t-59*4+"+1").
-- Phase 3: acc += x(t), start load x(t-61*4+"+1").
-- Phase 0, index += 120*4.
-- Phase 1, index += "+1"-59*4
-- Phase 2, index += -2*4
-- Phase 3, index += -59*4
-- Note that the "+1" is +1 mod 4, but is either +5 or +1, choosen so that
-- floor(t/4) increments, so that the total increment over 16 cycles is +16.
-- We store 1 sample per cycle. In phase 0, make sure that the store pointer
-- is not conflicting with the read pointer.
entity multifilter is
port (dd : in four_mf_signed;
qq : out mf_signed;
qq_last : out std_logic;
Clk : in std_logic);
end;
architecture multifilter of multifilter is
subtype index_t is unsigned9;
type ram_t is array(0 to 511) of mf_signed;
signal ram : ram_t;
signal rambuf : mf_signed;
signal ramout : mf_signed;
signal index, windex : index_t;
signal data : mf_signed;
alias phase : unsigned2 is windex(1 downto 0);
alias switch : std_logic is index(0);
signal acc : mf_signed;
attribute keep of rambuf : signal is "true";
begin
process
begin
wait until rising_edge(clk);
rambuf <= ram(to_integer(index));
ramout <= rambuf;
phase <= phase + 1;
ram(to_integer(windex)) <= data;
case phase is
when "00" =>
qq <= acc;
-- The index has already advanced, so we are outputing the last
-- channel (3) when the index is on channel 0.
qq_last <= b2s(index(1 downto 0) = "00");
index(8 downto 2) <= index(8 downto 2) + 120;
windex(8 downto 2) <= index(8 downto 2);
acc <= -ramout;
data <= dd(1);
when "01" =>
index(8 downto 2) <= index(8 downto 2) - 59 + 1;
index(1 downto 0) <= index(1 downto 0) + 1;
acc <= acc - ramout;
data <= dd(2);
when "10" =>
index(8 downto 2) <= index(8 downto 2) - 2;
acc <= acc + ramout;
data <= dd(3);
when others => -- "11"
index(8 downto 2) <= index(8 downto 2) - 59;
acc <= acc + ramout;
data <= dd(0);
end case;
end process;
end multifilter;
| gpl-3.0 | 71f043b903858d14c7b1f651cd959c13 | 0.602401 | 3.1854 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_top_v6.vhd | 5 | 52,905 | `protect begin_protected
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`protect key_block
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td8zI3B0cA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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PKRjDpHeJeFLxfpAkPo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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F0wZ7hvMbQHoQpFHp7E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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utTL7KxYKEy+2SzcXba2pWK0oH+GTNkedg2TSg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| apache-2.0 | 026afbb4eefcca68df1dd6c0b6068c1c | 0.948795 | 1.812622 | false | false | false | false |
sandrosalvato94/System-Design-Project | Tmp/TopLevelEntity.vhd | 1 | 4,804 | library ieee;
use ieee.std_logic_1164.all;
use work.CONSTANTS.all;
entity TOP_ENTITY is
port(
clock : in std_logic;
reset : in std_logic;
data : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address : in std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : in std_logic;
R_enable : in std_logic;
generic_enable : in std_logic;
interrupt : out std_logic
);
end TOP_ENTITY;
architecture STRUCTURAL of TOP_ENTITY is
component DATA_BUFFER is
port(
rst : in std_logic;
row_0 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- First line of the buffer. Must be read constantly by the ip manager
--PORT_0
data_cpu : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address_cpu : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_CPU : in std_logic;
RE_CPU : in std_logic;
GE_CPU : in std_logic;
--PORT_1
data_in_ip : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_out_ip : out std_logic_vector (DATA_WIDTH-1 downto 0);
address_ip : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_IP : in std_logic;
RE_IP : in std_logic;
GE_IP : in std_logic
);
end component DATA_BUFFER;
component ip_manager is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(data_width-1 downto 0);
data_out : in std_logic_vector(data_width-1 downto 0);
add : out std_logic_vector(add_width-1 downto 0);
w_enable : out std_logic;
r_enable : out std_logic;
generic_en : out std_logic;
interrupt : out std_logic;
row_0 : in std_logic_vector(data_width-1 downto 0);
data_in_ips : in data_array;
data_out_ips : out data_array;
add_ips : in add_array;
w_enable_ips : in std_logic_vector(0 to num_ips-1);
r_enable_ips : in std_logic_vector(0 to num_ips-1);
generic_en_ips : in std_logic_vector(0 to num_ips-1);
enable_ips : out std_logic_vector(0 to num_ips-1);
ack_ips : out std_logic_vector(0 to num_ips-1);
interrupt_ips : in std_logic_vector(0 to num_ips-1));
end component ip_manager;
component ip_adder is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(data_width-1 downto 0);
data_out : in std_logic_vector(data_width-1 downto 0);
address : out std_logic_vector(add_width-1 downto 0);
w_enable : out std_logic;
r_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic);
end component ip_adder;
signal row_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_in_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_out_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal address_ip : std_logic_vector (ADD_WIDTH-1 downto 0);
signal WE_IP : std_logic;
signal RE_IP : std_logic;
signal GE_IP : std_logic;
signal data_in_IPs : data_array;
signal data_out_IPs : data_array;
signal add_IPs : add_array;
signal W_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal R_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal generic_en_IPs : std_logic_vector(0 to NUM_IPS-1);
signal enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal ack_IPs : std_logic_vector(0 to NUM_IPS-1);
signal interrupt_IPs : std_logic_vector(0 to NUM_IPS-1);
begin
data_buff: DATA_BUFFER
port map( rst => reset,
row_0 => row_0,
--PORT_0
data_cpu => data,
address_cpu => address,
WE_CPU => W_enable,
RE_CPU => R_enable,
GE_CPU => generic_enable,
--PORT_1
data_in_ip => data_in_ip,
data_out_ip => data_out_ip,
address_ip => address_ip,
WE_IP => WE_IP,
RE_IP => RE_IP,
GE_IP => GE_IP);
ip_man: ip_manager
port map( clk => clock,
rst => reset,
data_in => data_in_ip,
data_out => data_out_ip,
add => address_ip,
W_enable => WE_IP,
R_enable => RE_IP,
generic_en => GE_IP,
interrupt => interrupt,
row_0 => row_0,
data_in_IPs => data_in_IPs,
data_out_IPs => data_out_IPs,
add_IPs => add_IPs,
W_enable_IPs => W_enable_IPs,
R_enable_IPs => R_enable_IPs,
generic_en_IPs => generic_en_IPs,
enable_IPs => enable_IPs,
ack_IPs => ack_IPs,
interrupt_IPs => interrupt_IPs);
mapIP_0: IP_Adder
PORT MAP(
clk => clock,
rst => reset,
data_in => data_in_IPs(0),
data_out => data_out_IPs(0),
address => add_IPs(0),
W_enable => W_enable_IPs(0),
R_enable => R_enable_IPs(0),
generic_en => generic_en_IPs(0),
enable => enable_IPs(0),
ack => ack_IPs(0),
interrupt => interrupt_IPs(0));
end architecture; | lgpl-3.0 | e4ef55f2d46b9bcdcaea52456fed5884 | 0.600749 | 2.562133 | false | false | false | false |
BBN-Q/APS2-Comms | src/tcp_mux.vhd | 1 | 4,021 | -- Mux streams going to tcp tx: memory write/read response, CPLD tx
-- Cross to the tcp clock
-- Adapt to 8bit wide data path
-- Byte-swaping as necessary
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity tcp_mux is
port (
clk : in std_logic;
rst : in std_logic;
clk_tcp : in std_logic;
rst_tcp : in std_logic;
--memory write/read streams
memory_tx_write_resp_tdata : in std_logic_vector(31 downto 0);
memory_tx_write_resp_tvalid : in std_logic;
memory_tx_write_resp_tlast : in std_logic;
memory_tx_write_resp_tready : out std_logic;
memory_tx_read_resp_tdata : in std_logic_vector(31 downto 0);
memory_tx_read_resp_tvalid : in std_logic;
memory_tx_read_resp_tlast : in std_logic;
memory_tx_read_resp_tready : out std_logic;
--CPLD tx stream
cpld_tx_tdata : in std_logic_vector(31 downto 0);
cpld_tx_tvalid : in std_logic;
cpld_tx_tready : out std_logic;
cpld_tx_tlast : in std_logic;
--TCP tx stream
tcp_tx_tdata : out std_logic_vector(7 downto 0);
tcp_tx_tvalid : out std_logic;
tcp_tx_tready : in std_logic
);
end entity;
architecture arch of tcp_mux is
signal muxed_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal muxed_tvalid, muxed_tlast, muxed_tready : std_logic := '0';
signal muxed_tcp_clk_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal muxed_tcp_clk_tvalid, muxed_tcp_clk_tlast, muxed_tcp_clk_tready : std_logic := '0';
begin
--Mux together all the streams
mux_inst : axis_arb_mux_3
generic map (
DATA_WIDTH => 32,
ARB_TYPE => "ROUND_ROBIN",
LSB_PRIORITY => "HIGH"
)
port map (
clk => clk,
rst => rst,
input_0_axis_tdata => memory_tx_read_resp_tdata,
input_0_axis_tvalid => memory_tx_read_resp_tvalid,
input_0_axis_tready => memory_tx_read_resp_tready,
input_0_axis_tlast => memory_tx_read_resp_tlast,
input_0_axis_tuser => '0',
input_1_axis_tdata => memory_tx_write_resp_tdata,
input_1_axis_tvalid => memory_tx_write_resp_tvalid,
input_1_axis_tready => memory_tx_write_resp_tready,
input_1_axis_tlast => memory_tx_write_resp_tlast,
input_1_axis_tuser => '0',
input_2_axis_tdata => cpld_tx_tdata,
input_2_axis_tvalid => cpld_tx_tvalid,
input_2_axis_tready => cpld_tx_tready,
input_2_axis_tlast => cpld_tx_tlast,
input_2_axis_tuser => '0',
output_axis_tdata => muxed_tdata,
output_axis_tvalid => muxed_tvalid,
output_axis_tready => muxed_tready,
output_axis_tlast => muxed_tlast,
output_axis_tuser => open
);
--Cross to the tcp clock domain
axi2tcp_fifo_inst : axis_async_fifo
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
async_rst => rst,
input_clk => clk,
input_axis_tdata => muxed_tdata,
input_axis_tvalid => muxed_tvalid,
input_axis_tready => muxed_tready,
input_axis_tlast => muxed_tlast,
input_axis_tuser => '0',
output_clk => clk_tcp,
output_axis_tdata => muxed_tcp_clk_tdata,
output_axis_tvalid => muxed_tcp_clk_tvalid,
output_axis_tready => muxed_tcp_clk_tready,
output_axis_tlast => muxed_tcp_clk_tlast,
output_axis_tuser => open
);
--Convert down to the byte wide data path
to_8bit_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 32,
INPUT_KEEP_WIDTH => 4,
OUTPUT_DATA_WIDTH => 8,
OUTPUT_KEEP_WIDTH => 1
)
port map (
clk => clk_tcp,
rst => rst_tcp,
input_axis_tdata => byte_swap(muxed_tcp_clk_tdata),
input_axis_tkeep => (others => '1'),
input_axis_tvalid => muxed_tcp_clk_tvalid,
input_axis_tready => muxed_tcp_clk_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_axis_tdata => tcp_tx_tdata,
output_axis_tkeep => open,
output_axis_tvalid => tcp_tx_tvalid,
output_axis_tready => tcp_tx_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
end architecture;
| mpl-2.0 | 1f7e4079b0dac5971f8bc05f676cc9b0 | 0.654066 | 2.811888 | false | false | false | false |
rcls/sdr | vhdl/bandpass.vhd | 1 | 19,917 | -- Filter given by a fifth order polynomial:
-- plot 10 * log ((sin(x*pi*65/80) * sin(x*pi*74/80) * sin(x*pi*87/80) * sin(x*pi*99/80) * sin(x*pi*106/80) * 80 * 80 * 80 * 80 * 80 / 65 / 74 / 87 / 99 / 106 / pi / pi / pi / pi / pi / x / x / x / x / x)**2) /log(10)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity bandpass is
port(adc_data : in signed14;
freq, gain : in unsigned8;
out_r, out_i : out signed15;
strobe : out std_logic;
clk : in std_logic);
end bandpass;
architecture bandpass of bandpass is
constant state_max : integer := 79;
signal state : integer range 0 to state_max;
signal phase : unsigned9 := "0" & x"00";
alias shift : unsigned(3 downto 0) is gain(5 downto 2);
-- Select part of trig. rom.
alias table_select : unsigned2 is gain(1 downto 0);
alias enable : std_logic is gain(7);
-- Accumulator widths minus one...
constant width1 : integer := 52;
constant width2 : integer := 39;
constant width3 : integer := 30;
constant width4 : integer := 22;
constant width5 : integer := 14;
-- Differencer width minus one...
constant diffw : integer := 14;
-- Type used for arithmetic in the differencers.
subtype wordd is signed(diffw downto 0);
type wordd_array is array (natural range <>) of wordd;
constant zero : wordd := (others => '0');
signal cos, sin, cos_1, sin_1, cos_2, sin_2 : signed16;
signal cos_neg : boolean;
signal sin_neg : boolean;
signal cos_neg_1 : boolean;
signal sin_neg_1 : boolean;
signal cos_neg_2 : boolean;
signal sin_neg_2 : boolean;
signal cos_neg_3 : boolean;
signal sin_neg_3 : boolean;
signal cos_neg_4 : boolean;
signal sin_neg_4 : boolean;
signal adc_r0 : signed18;
signal adc_i0 : signed18;
constant wprod : integer := 33;
signal prod_r : signed(wprod downto 0);
signal prod_i : signed(wprod downto 0);
signal prod1_r : signed(wprod downto 0);
signal prod1_i : signed(wprod downto 0);
-- The multiplier can absorb two levels of registers; but we want to keep
-- the second level in fabric to be as close as possible to the big adders.
attribute keep of prod_r : signal is "true";
attribute keep of prod_i : signal is "true";
signal acc1_r : signed(width1 downto 0);
signal acc1_i : signed(width1 downto 0);
signal acc2_r : signed(width2 downto 0);
signal acc2_i : signed(width2 downto 0);
signal acc3_r : signed(width3 downto 0);
signal acc3_i : signed(width3 downto 0);
signal acc4_r : signed(width4 downto 0);
signal acc4_i : signed(width4 downto 0);
signal acc5_r : signed(width5 downto 0);
signal acc5_i : signed(width5 downto 0);
signal shift1_r : signed(diffw + 3 downto 0);
signal shift1_i : signed(diffw + 3 downto 0);
signal shift2_r : signed(diffw downto 0);
signal shift2_i : signed(diffw downto 0);
signal flt_r : wordd_array(0 to 5);
signal flt_i : wordd_array(0 to 5);
subtype opcode_t is std_logic_vector(1 downto 0);
constant op_pass : opcode_t := "00";
constant op_add : opcode_t := "10";
constant op_shift : opcode_t := "11";
type opcodes_t is array (natural range <>) of opcode_t;
signal op : opcodes_t(0 to 5);
signal op1 : opcodes_t(0 to 5);
attribute keep of op : signal is "true";
function shift_or_add(acc : wordd; prev : wordd; adc : wordd;
o : opcode_t; i : integer) return wordd is
variable addend1 : wordd;
variable addend2 : wordd;
variable sum : wordd;
begin
if o(0) = '1' then
addend1 := prev;
addend2 := zero;
else
addend1 := acc;
addend2 := adc;
end if;
if i mod 2 = 0 then
sum := addend1 - addend2;
else
sum := addend1 + addend2;
end if;
return sum;
end shift_or_add;
-- The cos table is 4 tables of 160 entries. We store half a cycle, negated.
-- This means that +1 never occurs and we can use the full negative range.
type signed16_array is array (natural range <>) of signed16;
signal cos_table : signed16_array(0 to 1023) := (
-- Scale = 19484.
x"b3e4", x"b3e8", x"b3f3", x"b406", x"b420", x"0000", x"0000", x"0000",
x"b442", x"b46b", x"b49c", x"b4d4", x"b513", x"0000", x"0000", x"0000",
x"b55a", x"b5a9", x"b5fe", x"b65b", x"b6c0", x"0000", x"0000", x"0000",
x"b72b", x"b79e", x"b817", x"b898", x"b920", x"0000", x"0000", x"0000",
x"b9af", x"ba45", x"bae2", x"bb85", x"bc30", x"0000", x"0000", x"0000",
x"bce1", x"bd98", x"be57", x"bf1b", x"bfe6", x"0000", x"0000", x"0000",
x"c0b8", x"c18f", x"c26d", x"c351", x"c43b", x"0000", x"0000", x"0000",
x"c52b", x"c620", x"c71c", x"c81c", x"c923", x"0000", x"0000", x"0000",
x"ca2f", x"cb40", x"cc56", x"cd72", x"ce92", x"0000", x"0000", x"0000",
x"cfb8", x"d0e2", x"d210", x"d344", x"d47b", x"0000", x"0000", x"0000",
x"d5b7", x"d6f7", x"d83c", x"d984", x"dad0", x"0000", x"0000", x"0000",
x"dc1f", x"dd72", x"dec9", x"e023", x"e180", x"0000", x"0000", x"0000",
x"e2e0", x"e443", x"e5a8", x"e710", x"e87b", x"0000", x"0000", x"0000",
x"e9e8", x"eb57", x"ecc8", x"ee3c", x"efb0", x"0000", x"0000", x"0000",
x"f127", x"f29f", x"f418", x"f592", x"f70e", x"0000", x"0000", x"0000",
x"f88a", x"fa07", x"fb85", x"fd03", x"fe81", x"0000", x"0000", x"0000",
x"0000", x"017f", x"02fd", x"047b", x"05f9", x"0000", x"0000", x"0000",
x"0776", x"08f2", x"0a6e", x"0be8", x"0d61", x"0000", x"0000", x"0000",
x"0ed9", x"1050", x"11c4", x"1338", x"14a9", x"0000", x"0000", x"0000",
x"1618", x"1785", x"18f0", x"1a58", x"1bbd", x"0000", x"0000", x"0000",
x"1d20", x"1e80", x"1fdd", x"2137", x"228e", x"0000", x"0000", x"0000",
x"23e1", x"2530", x"267c", x"27c4", x"2909", x"0000", x"0000", x"0000",
x"2a49", x"2b85", x"2cbc", x"2df0", x"2f1e", x"0000", x"0000", x"0000",
x"3048", x"316e", x"328e", x"33aa", x"34c0", x"0000", x"0000", x"0000",
x"35d1", x"36dd", x"37e4", x"38e4", x"39e0", x"0000", x"0000", x"0000",
x"3ad5", x"3bc5", x"3caf", x"3d93", x"3e71", x"0000", x"0000", x"0000",
x"3f48", x"401a", x"40e5", x"41a9", x"4268", x"0000", x"0000", x"0000",
x"431f", x"43d0", x"447b", x"451e", x"45bb", x"0000", x"0000", x"0000",
x"4651", x"46e0", x"4768", x"47e9", x"4862", x"0000", x"0000", x"0000",
x"48d5", x"4940", x"49a5", x"4a02", x"4a57", x"0000", x"0000", x"0000",
x"4aa6", x"4aed", x"4b2c", x"4b64", x"4b95", x"0000", x"0000", x"0000",
x"4bbe", x"4be0", x"4bfa", x"4c0d", x"4c18", x"0000", x"0000", x"0000",
-- Scale = 23170.5.
x"a57e", x"a582", x"a58f", x"a5a6", x"a5c5", x"0000", x"0000", x"0000",
x"a5ed", x"a61e", x"a658", x"a69b", x"a6e6", x"0000", x"0000", x"0000",
x"a73b", x"a798", x"a7fe", x"a86c", x"a8e3", x"0000", x"0000", x"0000",
x"a963", x"a9ec", x"aa7c", x"ab16", x"abb7", x"0000", x"0000", x"0000",
x"ac61", x"ad13", x"adce", x"ae90", x"af5b", x"0000", x"0000", x"0000",
x"b02d", x"b108", x"b1ea", x"b2d4", x"b3c5", x"0000", x"0000", x"0000",
x"b4be", x"b5bf", x"b6c7", x"b7d6", x"b8ec", x"0000", x"0000", x"0000",
x"ba09", x"bb2d", x"bc58", x"bd89", x"bec1", x"0000", x"0000", x"0000",
x"c000", x"c145", x"c290", x"c3e1", x"c538", x"0000", x"0000", x"0000",
x"c695", x"c7f7", x"c95f", x"cacd", x"cc3f", x"0000", x"0000", x"0000",
x"cdb7", x"cf34", x"d0b5", x"d23c", x"d3c6", x"0000", x"0000", x"0000",
x"d556", x"d6e9", x"d880", x"da1b", x"dbba", x"0000", x"0000", x"0000",
x"dd5d", x"df03", x"e0ac", x"e259", x"e408", x"0000", x"0000", x"0000",
x"e5ba", x"e76f", x"e926", x"eadf", x"ec9a", x"0000", x"0000", x"0000",
x"ee58", x"f017", x"f1d7", x"f399", x"f55d", x"0000", x"0000", x"0000",
x"f721", x"f8e6", x"faac", x"fc72", x"fe39", x"0000", x"0000", x"0000",
x"0000", x"01c7", x"038e", x"0554", x"071a", x"0000", x"0000", x"0000",
x"08df", x"0aa3", x"0c67", x"0e29", x"0fe9", x"0000", x"0000", x"0000",
x"11a8", x"1366", x"1521", x"16da", x"1891", x"0000", x"0000", x"0000",
x"1a46", x"1bf8", x"1da7", x"1f54", x"20fd", x"0000", x"0000", x"0000",
x"22a3", x"2446", x"25e5", x"2780", x"2917", x"0000", x"0000", x"0000",
x"2aaa", x"2c3a", x"2dc4", x"2f4b", x"30cc", x"0000", x"0000", x"0000",
x"3249", x"33c1", x"3533", x"36a1", x"3809", x"0000", x"0000", x"0000",
x"396b", x"3ac8", x"3c1f", x"3d70", x"3ebb", x"0000", x"0000", x"0000",
x"4000", x"413f", x"4277", x"43a8", x"44d3", x"0000", x"0000", x"0000",
x"45f7", x"4714", x"482a", x"4939", x"4a41", x"0000", x"0000", x"0000",
x"4b42", x"4c3b", x"4d2c", x"4e16", x"4ef8", x"0000", x"0000", x"0000",
x"4fd3", x"50a5", x"5170", x"5232", x"52ed", x"0000", x"0000", x"0000",
x"539f", x"5449", x"54ea", x"5584", x"5614", x"0000", x"0000", x"0000",
x"569d", x"571d", x"5794", x"5802", x"5868", x"0000", x"0000", x"0000",
x"58c5", x"591a", x"5965", x"59a8", x"59e2", x"0000", x"0000", x"0000",
x"5a13", x"5a3b", x"5a5a", x"5a71", x"5a7e", x"0000", x"0000", x"0000",
-- Scale = 27554.5.
x"945e", x"9463", x"9473", x"948d", x"94b2", x"0000", x"0000", x"0000",
x"94e2", x"951d", x"9561", x"95b1", x"960b", x"0000", x"0000", x"0000",
x"966f", x"96de", x"9757", x"97da", x"9868", x"0000", x"0000", x"0000",
x"9900", x"99a2", x"9a4e", x"9b05", x"9bc5", x"0000", x"0000", x"0000",
x"9c8f", x"9d63", x"9e41", x"9f28", x"a019", x"0000", x"0000", x"0000",
x"a113", x"a217", x"a324", x"a43a", x"a559", x"0000", x"0000", x"0000",
x"a681", x"a7b2", x"a8ec", x"aa2e", x"ab79", x"0000", x"0000", x"0000",
x"accc", x"ae27", x"af8b", x"b0f6", x"b269", x"0000", x"0000", x"0000",
x"b3e4", x"b566", x"b6f0", x"b881", x"ba19", x"0000", x"0000", x"0000",
x"bbb8", x"bd5d", x"bf09", x"c0bc", x"c275", x"0000", x"0000", x"0000",
x"c434", x"c5f8", x"c7c3", x"c993", x"cb68", x"0000", x"0000", x"0000",
x"cd43", x"cf23", x"d107", x"d2f0", x"d4de", x"0000", x"0000", x"0000",
x"d6cf", x"d8c5", x"dabf", x"dcbc", x"debd", x"0000", x"0000", x"0000",
x"e0c1", x"e2c9", x"e4d3", x"e6e0", x"e8ef", x"0000", x"0000", x"0000",
x"eb00", x"ed14", x"ef2a", x"f141", x"f359", x"0000", x"0000", x"0000",
x"f573", x"f78e", x"f9aa", x"fbc6", x"fde3", x"0000", x"0000", x"0000",
x"0000", x"021d", x"043a", x"0656", x"0872", x"0000", x"0000", x"0000",
x"0a8d", x"0ca7", x"0ebf", x"10d6", x"12ec", x"0000", x"0000", x"0000",
x"1500", x"1711", x"1920", x"1b2d", x"1d37", x"0000", x"0000", x"0000",
x"1f3f", x"2143", x"2344", x"2541", x"273b", x"0000", x"0000", x"0000",
x"2931", x"2b22", x"2d10", x"2ef9", x"30dd", x"0000", x"0000", x"0000",
x"32bd", x"3498", x"366d", x"383d", x"3a08", x"0000", x"0000", x"0000",
x"3bcc", x"3d8b", x"3f44", x"40f7", x"42a3", x"0000", x"0000", x"0000",
x"4448", x"45e7", x"477f", x"4910", x"4a9a", x"0000", x"0000", x"0000",
x"4c1c", x"4d97", x"4f0a", x"5075", x"51d9", x"0000", x"0000", x"0000",
x"5334", x"5487", x"55d2", x"5714", x"584e", x"0000", x"0000", x"0000",
x"597f", x"5aa7", x"5bc6", x"5cdc", x"5de9", x"0000", x"0000", x"0000",
x"5eed", x"5fe7", x"60d8", x"61bf", x"629d", x"0000", x"0000", x"0000",
x"6371", x"643b", x"64fb", x"65b2", x"665e", x"0000", x"0000", x"0000",
x"6700", x"6798", x"6826", x"68a9", x"6922", x"0000", x"0000", x"0000",
x"6991", x"69f5", x"6a4f", x"6a9f", x"6ae3", x"0000", x"0000", x"0000",
x"6b1e", x"6b4e", x"6b73", x"6b8d", x"6b9d", x"0000", x"0000", x"0000",
-- Scale = 32768.
x"8000", x"8006", x"8019", x"8039", x"8065", x"0000", x"0000", x"0000",
x"809e", x"80e3", x"8135", x"8193", x"81fe", x"0000", x"0000", x"0000",
x"8276", x"82f9", x"8389", x"8426", x"84ce", x"0000", x"0000", x"0000",
x"8583", x"8644", x"8711", x"87e9", x"88ce", x"0000", x"0000", x"0000",
x"89be", x"8aba", x"8bc2", x"8cd5", x"8df3", x"0000", x"0000", x"0000",
x"8f1d", x"9052", x"9192", x"92dd", x"9432", x"0000", x"0000", x"0000",
x"9592", x"96fd", x"9872", x"99f1", x"9b7b", x"0000", x"0000", x"0000",
x"9d0e", x"9eab", x"a052", x"a202", x"a3bb", x"0000", x"0000", x"0000",
x"a57e", x"a749", x"a91d", x"aafa", x"acdf", x"0000", x"0000", x"0000",
x"aecc", x"b0c2", x"b2bf", x"b4c3", x"b6d0", x"0000", x"0000", x"0000",
x"b8e3", x"bafe", x"bd1f", x"bf47", x"c175", x"0000", x"0000", x"0000",
x"c3a9", x"c5e4", x"c824", x"ca69", x"ccb4", x"0000", x"0000", x"0000",
x"cf04", x"d159", x"d3b2", x"d610", x"d872", x"0000", x"0000", x"0000",
x"dad8", x"dd41", x"dfae", x"e21e", x"e492", x"0000", x"0000", x"0000",
x"e707", x"e980", x"ebfa", x"ee76", x"f0f5", x"0000", x"0000", x"0000",
x"f374", x"f5f5", x"f877", x"fafa", x"fd7d", x"0000", x"0000", x"0000",
x"0000", x"0283", x"0506", x"0789", x"0a0b", x"0000", x"0000", x"0000",
x"0c8c", x"0f0b", x"118a", x"1406", x"1680", x"0000", x"0000", x"0000",
x"18f9", x"1b6e", x"1de2", x"2052", x"22bf", x"0000", x"0000", x"0000",
x"2528", x"278e", x"29f0", x"2c4e", x"2ea7", x"0000", x"0000", x"0000",
x"30fc", x"334c", x"3597", x"37dc", x"3a1c", x"0000", x"0000", x"0000",
x"3c57", x"3e8b", x"40b9", x"42e1", x"4502", x"0000", x"0000", x"0000",
x"471d", x"4930", x"4b3d", x"4d41", x"4f3e", x"0000", x"0000", x"0000",
x"5134", x"5321", x"5506", x"56e3", x"58b7", x"0000", x"0000", x"0000",
x"5a82", x"5c45", x"5dfe", x"5fae", x"6155", x"0000", x"0000", x"0000",
x"62f2", x"6485", x"660f", x"678e", x"6903", x"0000", x"0000", x"0000",
x"6a6e", x"6bce", x"6d23", x"6e6e", x"6fae", x"0000", x"0000", x"0000",
x"70e3", x"720d", x"732b", x"743e", x"7546", x"0000", x"0000", x"0000",
x"7642", x"7732", x"7817", x"78ef", x"79bc", x"0000", x"0000", x"0000",
x"7a7d", x"7b32", x"7bda", x"7c77", x"7d07", x"0000", x"0000", x"0000",
x"7d8a", x"7e02", x"7e6d", x"7ecb", x"7f1d", x"0000", x"0000", x"0000",
x"7f62", x"7f9b", x"7fc7", x"7fe7", x"7ffa", x"0000", x"0000", x"0000"
);
begin
process
begin
-- A little bit of logic outside the enable: reseting the state counter
-- and the output strobe. This makes sure the strobe does not get stuck
-- high while we're disabled.
wait until rising_edge(clk);
if state = state_max then
state <= 0;
strobe <= '1';
else
state <= state + 1;
strobe <= '0';
end if;
end process;
process
variable sprod_r, sprod_i : signed(wprod downto 0);
variable shift0_r : signed(diffw + 11 downto 0);
variable shift0_i : signed(diffw + 11 downto 0);
begin
wait until rising_edge(clk) and enable = '1';
phase <= addmod320(phase, '0' & freq);
-- We actually use -cos(phase) + i sin(phase).
cos <= cos_table(to_integer(table_select & phase(7 downto 0)));
sin <= cos_table(to_integer(table_select & phase(7 downto 0)
xor "0010000000"));
cos_neg <= phase(8) = '1';
sin_neg <= phase(8) /= phase(7);
if shift(2) = '1' then
adc_r0 <= adc_data & "0000";
adc_i0 <= adc_data & "0000";
else
adc_r0 <= (others => adc_data(13));
adc_i0 <= (others => adc_data(13));
adc_r0(13 downto 0) <= adc_data;
adc_i0(13 downto 0) <= adc_data;
end if;
cos_1 <= cos;
sin_1 <= sin;
cos_neg_1 <= cos_neg;
sin_neg_1 <= sin_neg;
cos_2 <= cos_1;
sin_2 <= sin_1;
cos_neg_2 <= cos_neg_1;
sin_neg_2 <= sin_neg_1;
prod_r <= adc_r0 * cos_2;
prod_i <= adc_i0 * sin_2;
cos_neg_3 <= cos_neg_2;
sin_neg_3 <= sin_neg_2;
prod1_r <= prod_r;
prod1_i <= prod_i;
cos_neg_4 <= cos_neg_3;
sin_neg_4 <= sin_neg_3;
if shift(3) = '1' then
sprod_r := prod1_r;
sprod_i := prod1_i;
else
sprod_r := (others => prod1_r(wprod));
sprod_i := (others => prod1_i(wprod));
sprod_r(wprod - 8 downto 0) := prod1_r(wprod downto 8);
sprod_i(wprod - 8 downto 0) := prod1_i(wprod downto 8);
end if;
if cos_neg_4 then
acc1_r <= acc1_r - sprod_r;
else
acc1_r <= acc1_r + sprod_r;
end if;
if sin_neg_4 then
acc1_i <= acc1_i - sprod_i;
else
acc1_i <= acc1_i + sprod_i;
end if;
acc2_r <= acc2_r + take(acc1_r(width1 downto width1 - width2 - 2),
2, shift and x"2");
acc2_i <= acc2_i + take(acc1_i(width1 downto width1 - width2 - 2),
2, shift and x"2");
acc3_r <= acc3_r + take(acc2_r(width2 downto width2 - width3 - 1),
1, shift and x"1");
acc3_i <= acc3_i + take(acc2_i(width2 downto width2 - width3 - 1),
1, shift and x"1");
acc4_r <= acc4_r + acc3_r(width3 downto width3 - width4);
acc4_i <= acc4_i + acc3_i(width3 downto width3 - width4);
acc5_r <= acc5_r + acc4_r(width4 downto width4 - width5);
acc5_i <= acc5_i + acc4_i(width4 downto width4 - width5);
for i in 0 to 5 loop
op(i) <= op_pass;
end loop;
case state is
when 0 => op(2) <= op_add; -- 160 = 2*80 + 0 = 21 +65 +74
when 6 => op(1) <= op_add; -- 86 = 1*80 + 6 = 21 +65
when 7 => op(3) <= op_add; -- 247 = 3*80 + 7 = 21 +65 +74 +87
when 13 => op(2) <= op_add; -- 173 = 2*80 +13 = 21 +65 +87
when 15 => op(1) <= op_add; -- 95 = 1*80 +15 = 21 +74
when 19 => op(3) <= op_add; -- 259 = 3*80 +19 = 21 +65 +74 +99
when 21 => op(0) <= op_add; -- 21 = 0*80 +21 = 21
when 22 => op(2) <= op_add; -- 182 = 2*80 +22 = 21 +74 +87
when 25 => op(2) <= op_add; -- 185 = 2*80 +25 = 21 +65 +99
when 26 => op(3) <= op_add; -- 266 = 3*80 +26 = 21 +65 +74 +106
op(4) <= op_add; -- 346 = 4*80 +26 = 21 +65 +74 +87 +99
when 28 => op(1) <= op_add; -- 108 = 1*80 +28 = 21 +87
when 32 => op(2) <= op_add; -- 192 = 2*80 +32 = 21 +65 +106
op(3) <= op_add; -- 272 = 3*80 +32 = 21 +65 +87 +99
when 33 => op(4) <= op_add; -- 353 = 4*80 +33 = 21 +65 +74 +87 +106
when 34 => op(2) <= op_add; -- 194 = 2*80 +34 = 21 +74 +99
when 39 => op(3) <= op_add; -- 279 = 3*80 +39 = 21 +65 +87 +106
when 40 => op(1) <= op_add; -- 120 = 1*80 +40 = 21 +99
when 41 => op(2) <= op_add; -- 201 = 2*80 +41 = 21 +74 +106
op(3) <= op_add; -- 281 = 3*80 +41 = 21 +74 +87 +99
when 45 => op(4) <= op_add; -- 365 = 4*80 +45 = 21 +65 +74 +99 +106
when 47 => op(1) <= op_add; -- 127 = 1*80 +47 = 21 +106
op(2) <= op_add; -- 207 = 2*80 +47 = 21 +87 +99
when 48 => op(3) <= op_add; -- 288 = 3*80 +48 = 21 +74 +87 +106
when 51 => op(3) <= op_add; -- 291 = 3*80 +51 = 21 +65 +99 +106
when 52 => op(5) <= op_add; -- 452 = 5*80 +52 = 21 +65 +74 +87 +99 +106
when 54 => op(2) <= op_add; -- 214 = 2*80 +54 = 21 +87 +106
when 58 => op(4) <= op_add; -- 378 = 4*80 +58 = 21 +65 +87 +99 +106
when 60 => op(3) <= op_add; -- 300 = 3*80 +60 = 21 +74 +99 +106
when 66 => op(2) <= op_add; -- 226 = 2*80 +66 = 21 +99 +106
when 67 => op(4) <= op_add; -- 387 = 4*80 +67 = 21 +74 +87 +99 +106
when 73 => op(3) <= op_add; -- 313 = 3*80 +73 = 21 +87 +99 +106
when 78 =>
for i in 0 to 5 loop
op(i) <= op_shift;
end loop;
when others =>
end case;
op1 <= op;
if op1(0)(1) = '1' then
flt_r(0) <= shift_or_add(flt_r(0), zero, acc5_r, op1(0), 0);
flt_i(0) <= shift_or_add(flt_i(0), zero, acc5_i, op1(0), 0);
end if;
for i in 1 to 5 loop
if op1(i)(1) = '1' then
flt_r(i) <= shift_or_add(flt_r(i), flt_r(i-1), acc5_r, op1(i), i);
flt_i(i) <= shift_or_add(flt_i(i), flt_i(i-1), acc5_i, op1(i), i);
end if;
end loop;
if state = state_max then
out_r <= flt_r(5)(diffw downto diffw - 14);
out_i <= flt_i(5)(diffw downto diffw - 14);
end if;
end process;
end bandpass;
| gpl-3.0 | 3a09fe272fb6cdf4531d60034cd40525 | 0.53487 | 2.257907 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/IPManager_HardwareGroup.vhd | 2 | 5,201 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_MANAGER is
port(
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector (DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector (DATA_WIDTH-1 downto 0);
add : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
interrupt : out std_logic;
row_0 : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_in_IPs : in data_array;
data_out_IPs : out data_array;
add_IPs : in add_array;
W_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
R_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
generic_en_IPs : in std_logic_vector(0 to NUM_IPS-1);
enable_IPs : out std_logic_vector(0 to NUM_IPS-1);
ack_IPs : out std_logic_vector(0 to NUM_IPS-1);
interrupt_IPs : in std_logic_vector(0 to NUM_IPS-1)
);
end IP_MANAGER;
architecture BEHAVIOURAL of IP_MANAGER is
begin
-- PROC_1 manages the behavior of the IPMANAGER.
PROC_1: process (clk, rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
enable_IPs <= (others => '0');
ack_IPs <= (others => '0');
interrupt <= '0';
elsif Clk'event and Clk = '1' then -- rising clock edge
-- NOT configuration mode:
if (conv_integer(row_0(IPADD_POS downto 0)) /= 0 ) then
-- Assuring that only one IPs is enable in case the cpu decides to change the IP core without properly ending the transaction
enable_IPs <= (others => '0');
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
ack_IPs <= (others => '0');
-- Releasing interrupt:
if (row_0(INT_POS) = '1' AND row_0(BE_POS) = '1' )then
interrupt <= '0';
ack_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
end if;
-- Begin ( or continue ) transaction:
if row_0(BE_POS) = '1' then
enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
data_in <= data_in_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
data_out_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= data_out ;
add <= add_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
W_enable <= W_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
R_enable <= R_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
generic_en <= generic_en_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
-- Interrupt mode:
-- If some IPs raise the interrupt and there is no current transaction
elsif (row_0(BE_POS) = '0' and conv_integer(interrupt_IPs) /= 0 ) then
for I in (NUM_IPS-1) downto 0 loop -- scan from the lower priority IP to the higher (this avoid to insert a break statement, that is not synthesizable)
if (interrupt_IPs(I) = '1') then -- check if it rises the interrupt signal and the transaction with the Master is ended
--Write in row_0 the address of the ip with the highest priority
add <= (others => '0');
data_in <= row_0(DATA_WIDTH-1 downto 12) & conv_std_logic_vector(I+1, IPADD_POS+1);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
-- Signal the cpu that one interrupt request must be served
interrupt <= '1';
end if;
end loop;
end if;
---- TODO : Future feature
---- Manager configuration mode:
-- else
end if;
end if;
end process PROC_1;
end architecture; | lgpl-3.0 | 5b127e9f248464134d4eef648095e3f2 | 0.443761 | 3.884242 | false | false | false | false |
jdryg/tis100cpu | node_port_readdec.vhd | 1 | 1,001 | -- Added these lines on rev. 42 in order to remove the commit message saying that
-- there is a bug in the implementation, since the bug has been fixed in the same rev.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity node_port_readdec is
Port ( I_clk : in STD_LOGIC;
I_portID : in STD_LOGIC_VECTOR (2 downto 0);
I_readEnable : in STD_LOGIC;
O_readEnableUp : out STD_LOGIC;
O_readEnableDown : out STD_LOGIC;
O_readEnableLeft : out STD_LOGIC;
O_readEnableRight : out STD_LOGIC);
end node_port_readdec;
-- NOTE: The architecture below doesn't support ANY or LAST ports.
architecture Behavioral of node_port_readdec is
begin
O_readEnableUp <= I_readEnable when I_portID = "000" else '0';
O_readEnableDown <= I_readEnable when I_portID = "001" else '0';
O_readEnableLeft <= I_readEnable when I_portID = "010" else '0';
O_readEnableRight <= I_readEnable when I_portID = "011" else '0';
end Behavioral;
| mit | 22458d72832d8baa207aa5281ea12715 | 0.663337 | 3.39322 | false | false | false | false |
jdryg/tis100cpu | reg_tb.vhd | 1 | 1,479 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY reg_tb IS
END reg_tb;
ARCHITECTURE behavior OF reg_tb IS
constant REG_WIDTH: integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg
GENERIC(WIDTH : integer := REG_WIDTH);
PORT(
I_clk : IN std_logic;
I_reset : IN std_logic;
I_dataIn : IN std_logic_vector(WIDTH-1 downto 0);
O_dataOut : OUT std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
--Inputs
signal I_clk : std_logic := '0';
signal I_reset : std_logic := '0';
signal I_dataIn : std_logic_vector(REG_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal O_dataOut : std_logic_vector(REG_WIDTH-1 downto 0);
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg PORT MAP (
I_clk => I_clk,
I_reset => I_reset,
I_dataIn => I_dataIn,
O_dataOut => O_dataOut
);
-- Clock process definitions
I_clk_process :process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
I_reset <= '1';
wait for I_clk_period;
I_reset <= '0';
I_dataIn <= X"0010";
wait for I_clk_period;
assert O_dataOut = X"0010" report "Wrong output." severity error;
wait;
end process;
END;
| mit | 32b4ed3c08c6f87e3c9773f8a106e0f9 | 0.584855 | 3.346154 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_dc_as.vhd | 5 | 10,866 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6304)
`protect data_block
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| apache-2.0 | 054b70258b8742e9c856b6f7bb4a7103 | 0.926744 | 1.888425 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/vec_mux.vhd | 1 | 10,822 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| apache-2.0 | aa7eb77ea0ff0543a5a4f88f27426904 | 0.926816 | 1.899596 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/SDcard.vhd | 2 | 42,425 | --**********************************************************************
-- Copyright (c) 2012-2014 by XESS Corp <http://www.xess.com>.
-- All rights reserved.
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3.0 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library. If not, see
-- <http://www.gnu.org/licenses/>.
--**********************************************************************
--*********************************************************************
-- SD MEMORY CARD INTERFACE
--
-- Reads/writes a single or multiple blocks of data to/from an SD Flash card.
--
-- Based on XESS by by Steven J. Merrifield, June 2008:
-- http : //stevenmerrifield.com/tools/sd.vhd
--
-- Most of what I learned about interfacing to SD/SDHC cards came from here:
-- http://elm-chan.org/docs/mmc/mmc_e.html
--
-- OPERATION
--
-- Set-up:
-- First of all, you have to give the controller a clock signal on the clk_i
-- input with a higher frequency than the serial clock sent to the SD card
-- through the sclk_o output. You can set generic parameters for the
-- controller to tell it the master clock frequency (100 MHz), the SCLK
-- frequency for initialization (400 KHz), the SCLK frequency for normal
-- operation (25MHz), the size of data sectors in the Flash memory (512bytes),
-- and the type of card (either SD or SDHC). I typically use a 100 MHz
-- clock if I'm running an SD card with a 25 Mbps serial data stream.
--
-- Initialize it:
-- Pulsing the reset_i input high and then bringing it low again will make
-- the controller initialize the SD card so it will XESS in SPI mode.
-- Basically, it sends the card the commands CMD0, CMD8 and then ACMD41 (which
-- is CMD55 followed by CMD41). The busy_o output will be high during the
-- initialization and will go low once it is done.
--
-- After the initialization command sequence, the SD card will send back an R1
-- response byte. If only the IDLE bit of the R1 response is set, then the
-- controller will repeatedly re-try the ACMD41 command while busy_o remains
-- high.
--
-- If any other bit of the R1 response is set, then an error occurred. The
-- controller will stall, lower busy_o, and output the R1 response code on the
-- error_o bus. You'll have to pulse reset_i to unfreeze the controller.
--
-- If the R1 response is all zeroes (i.e., no errors occurred during the
-- initialization), then the controller will lower busy_o and wait for a
-- read or write operation from the host. The controller will only accept new
-- operations when busy_o is low.
--
-- Write data:
-- To write a data block to the SD card, the address of a block is placed
-- on the addr_i input bus and the wr_i input is raised. The address and
-- write strobe can be removed once busy_o goes high to indicate the write
-- operation is underway. The data to be written to the SD card is passed as
-- follows:
--
-- 1. The controller requests a byte of data by raising the hndShk_o output.
-- 2. The host applies the next byte to the data_i input bus and raises the
-- hndShk_i input.
-- 3. The controller accepts the byte and lowers the hndShk_o output.
-- 4. The host lowers the hndShk_i input.
--
-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the
-- data block are passed from the host to the controller. Once all the data
-- is passed, the sector on the SD card will be written and the busy_o output
-- will be lowered.
--
-- Read data:
-- To read a block of data from the SD card, the address of a block is
-- placed on the addr_i input bus and the rd_i input is raised. The address
-- and read strobe can be removed once busy_o goes high to indicate the read
-- operation is underway. The data read from the SD card is passed to the
-- host as follows:
--
-- 1. The controller raises the hndShk_o output when the next data byte
-- is available.
-- 2. The host reads the byte from the data_o output bus and raises the
-- hndShk_i input.
-- 3. The controller lowers the hndShk_o output.
-- 4. The host lowers the hndShk_i input.
--
-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the
-- data block are passed from the controller to the host. Once all the data
-- is read, the busy_o output will be lowered.
--
-- Handle errors:
-- If an error is detected during either a read or write operation, then the
-- controller will stall, lower busy_o, and output an error code on the
-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. That
-- may seem a bit excessive, but it does guarantee that you can't ignore any
-- errors that occur.
--
-- TODO:
--
-- * Implement multi-block read and write commands.
-- * Allow host to send/receive SPI commands/data directly to
-- the SD card through the controller.
-- *********************************************************************
------------------------------------------------------------------------------
-- Commonly-used functions and constants.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package CommonPckg is
-- constant YES : std_logic := '1';
-- constant NO : std_logic := '0';
-- constant HI : std_logic := '1';
-- constant LO : std_logic := '0';
-- constant ONE : std_logic := '1';
-- constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- FPGA chip families.
type FpgaFamily_t is (SPARTAN3A_E, SPARTAN6_E);
-- XESS FPGA boards.
type XessBoard_t is (XULA_E, XULA2_E);
-- Convert a Boolean to a std_logic.
function BooleanToStdLogic(b : in boolean) return std_logic;
-- Find the base-2 logarithm of a number.
function Log2(v : in natural) return natural;
-- Select one of two integers based on a Boolean.
function IntSelect(s : in boolean; a : in integer; b : in integer) return integer;
-- Select one of two reals based on a Boolean.
function RealSelect(s : in boolean; a : in real; b : in real) return real;
-- Convert a binary number to a graycode number.
function BinaryToGray(b : in std_logic_vector) return std_logic_vector;
-- Convert a graycode number to a binary number.
function GrayToBinary(g : in std_logic_vector) return std_logic_vector;
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body CommonPckg is
-- Convert a Boolean to a std_logic.
function BooleanToStdLogic(b : in boolean) return std_logic is
variable s : std_logic;
begin
if b then
s := '1';
else
s := '0';
end if;
return s;
end function BooleanToStdLogic;
-- Find the base 2 logarithm of a number.
function Log2(v : in natural) return natural is
variable n : natural;
variable logn : natural;
begin
n := 1;
for i in 0 to 128 loop
logn := i;
exit when (n >= v);
n := n * 2;
end loop;
return logn;
end function Log2;
-- Select one of two integers based on a Boolean.
function IntSelect(s : in boolean; a : in integer; b : in integer) return integer is
begin
if s then
return a;
else
return b;
end if;
return a;
end function IntSelect;
-- Select one of two reals based on a Boolean.
function RealSelect(s : in boolean; a : in real; b : in real) return real is
begin
if s then
return a;
else
return b;
end if;
return a;
end function RealSelect;
-- Convert a binary number to a graycode number.
function BinaryToGray(b : in std_logic_vector) return std_logic_vector is
variable g : std_logic_vector(b'range);
begin
for i in b'low to b'high-1 loop
g(i) := b(i) xor b(i+1);
end loop;
g(b'high) := b(b'high);
return g;
end function BinaryToGray;
-- Convert a graycode number to a binary number.
function GrayToBinary(g : in std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(g'range);
begin
b(b'high) := g(b'high);
for i in g'high-1 downto g'low loop
b(i) := b(i+1) xor g(i);
end loop;
return b;
end function GrayToBinary;
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
end package body;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.CommonPckg.all;
use work.p_wires.all;
package SdCardPckg is
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
component SdCardCtrl is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO; -- Serial data input from SD card.
state : out std_logic_vector(4 downto 0) -- state debugging only
);
end component;
end package;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.CommonPckg.all;
use work.SdCardPckg.all;
use work.p_wires.all;
entity SdCardCtrl is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO; -- Serial data input from SD card.
state : out std_logic_vector(4 downto 0) -- state debugging only
);
end entity;
architecture rtl of SdCardCtrl is
signal sclk_r : std_logic := ZERO; -- Register output drives SD card clock.
signal hndShk_r : std_logic := NO; -- Register output drives handshake output to host.
signal sd_state_dbg : integer:= 0; -- debugging only
begin
process(clk_i) -- FSM process for the SD card controller.
type FsmState_t is ( -- States of the SD card controller FSM.
START_INIT, -- 0 Send initialization clock pulses to the deselected SD card.
SEND_CMD0, -- 1 Put the SD card in the IDLE state.
CHK_CMD0_RESPONSE, -- 2 Check card's R1 response to the CMD0.
SEND_CMD8, -- 3 This command is needed to initialize SDHC cards.
GET_CMD8_RESPONSE, -- 4 Get the R7 response to CMD8.
SEND_CMD55, -- 5 Send CMD55 to the SD card.
SEND_CMD41, -- 6 Send CMD41 to the SD card.
CHK_ACMD41_RESPONSE, -- 7 Check if the SD card has left the IDLE state.
WAIT_FOR_HOST_RW, -- 8 Wait for the host to issue a read or write command.
RD_BLK, -- 9 Read a block of data from the SD card.
WR_BLK, -- 10 Write a block of data to the SD card.
WR_WAIT, -- 11 Wait for SD card to finish writing the data block.
START_TX, -- 12 Start sending command/data.
TX_BITS, -- 13 Shift out remaining command/data bits.
GET_CMD_RESPONSE, -- 14 Get the R1 response of the SD card to a command.
RX_BITS, -- 15 Receive response/data from the SD card.
DESELECT, -- 16 De-select the SD card and send some clock pulses (Must enter with sclk at zero.)
PULSE_SCLK, -- 17 Issue some clock pulses. (Must enter with sclk at zero.)
REPORT_ERROR -- 18 Report error and stall until reset.
);
attribute SYN_ENCODING of FsmState_t : type is "safe";
variable state_v : FsmState_t := START_INIT; -- Current state of the FSM.
variable rtnState_v : FsmState_t; -- State FSM returns to when FSM subroutine completes.
-- Timing constants based on the master clock frequency and the SPI SCLK frequencies.
constant CLKS_PER_INIT_SCLK_C : real := FREQ_G / INIT_SPI_FREQ_G;
constant CLKS_PER_SCLK_C : real := FREQ_G / SPI_FREQ_G;
constant MAX_CLKS_PER_SCLK_C : real := realmax(CLKS_PER_INIT_SCLK_C, CLKS_PER_SCLK_C);
constant MAX_CLKS_PER_SCLK_PHASE_C : natural := integer(round(MAX_CLKS_PER_SCLK_C / 2.0));
constant INIT_SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_INIT_SCLK_C / 2.0));
constant SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_SCLK_C / 2.0));
constant DELAY_BETWEEN_BLOCK_RW_C : natural := SCLK_PHASE_PERIOD_C;
-- Registers for generating slow SPI SCLK from the faster master clock.
variable clkDivider_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Holds the SCLK period.
variable sclkPhaseTimer_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Counts down to zero, then SCLK toggles.
constant NUM_INIT_CLKS_C : natural := 160; -- Number of initialization clocks to SD card.
variable bitCnt_v : natural range 0 to NUM_INIT_CLKS_C; -- Tx/Rx bit counter.
constant CRC_SZ_C : natural := 2; -- Number of CRC bytes for read/write blocks.
-- When reading blocks of data, get 0xFE + [DATA_BLOCK] + [CRC].
constant RD_BLK_SZ_C : natural := 1 + BLOCK_SIZE_G + CRC_SZ_C;
-- When writing blocks of data, send 0xFF + 0xFE + [DATA BLOCK] + [CRC] then receive response byte.
constant WR_BLK_SZ_C : natural := 1 + 1 + BLOCK_SIZE_G + CRC_SZ_C + 1;
variable byteCnt_v : natural range 0 to IntMax(WR_BLK_SZ_C, RD_BLK_SZ_C); -- Tx/Rx byte counter.
-- Command bytes for various SD card operations.
subtype Cmd_t is std_logic_vector(7 downto 0);
constant CMD0_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 0, Cmd_t'length));
constant CMD8_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 8, Cmd_t'length));
constant CMD55_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 55, Cmd_t'length));
constant CMD41_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 41, Cmd_t'length));
constant READ_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 17, Cmd_t'length));
constant WRITE_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 24, Cmd_t'length));
-- Except for CMD0 and CMD8, SD card ops don't need a CRC, so use a fake one for that slot in the command.
constant FAKE_CRC_C : std_logic_vector(7 downto 0) := x"FF";
variable addr_v : unsigned(addr_i'range); -- Address of current block for R/W operations.
-- Maximum Tx to SD card consists of command + address + CRC. Data Tx is just a single byte.
variable tx_v : std_logic_vector(CMD0_C'length + addr_v'length + FAKE_CRC_C'length - 1 downto 0); -- Data/command to SD card.
alias txCmd_v is tx_v; -- Command transmission shift register.
alias txData_v is tx_v(tx_v'high downto tx_v'high - data_i'length + 1); -- Data byte transmission shift register.
variable rx_v : std_logic_vector(data_i'range); -- Data/response byte received from SD card.
-- Various response codes.
subtype Response_t is std_logic_vector(rx_v'range);
constant ACTIVE_NO_ERRORS_C : Response_t := "00000000"; -- Normal R1 code after initialization.
constant IDLE_NO_ERRORS_C : Response_t := "00000001"; -- Normal R1 code after CMD0.
constant DATA_ACCEPTED_C : Response_t := "---00101"; -- SD card accepts data block from host.
constant DATA_REJ_CRC_C : Response_t := "---01011"; -- SD card rejects data block from host due to CRC error.
constant DATA_REJ_WERR_C : Response_t := "---01101"; -- SD card rejects data block from host due to write error.
-- Various tokens.
subtype Token_t is std_logic_vector(rx_v'range);
constant NO_TOKEN_C : Token_t := x"FF"; -- Received before the SD card responds to a block read command.
constant START_TOKEN_C : Token_t := x"FE"; -- Starting byte preceding a data block.
-- Flags that are set/cleared to affect the operation of the FSM.
variable getCmdResponse_v : boolean; -- When true, get R1 response to command sent to SD card.
variable rtnData_v : boolean; -- When true, signal to host when a data byte arrives from SD card.
variable doDeselect_v : boolean; -- When true, de-select SD card after a command is issued.
begin
sd_state_dbg <= FsmState_t'pos(state_v); -- debugging only
state <= std_logic_vector(to_unsigned(sd_state_dbg, 5));
if rising_edge(clk_i) then
if reset_i = YES then -- Perform a reset.
state_v := START_INIT; -- Send the FSM to the initialization entry-point.
sclkPhaseTimer_v := 0; -- Don't delay the initialization right after reset.
busy_o <= YES; -- Busy while the SD card interface is being initialized.
elsif sclkPhaseTimer_v /= 0 then
-- Setting the clock phase timer to a non-zero value delays any further actions
-- and generates the slower SPI clock from the faster master clock.
sclkPhaseTimer_v := sclkPhaseTimer_v - 1;
-- Clock phase timer has reached zero, so check handshaking sync. between host and controller.
-- Handshaking lets the host control the flow of data to/from the SD card controller.
-- Handshaking between the SD card controller and the host proceeds as follows:
-- 1: Controller raises its handshake and waits.
-- 2: Host sees controller handshake and raises its handshake in acknowledgement.
-- 3: Controller sees host handshake acknowledgement and lowers its handshake.
-- 4: Host sees controller lower its handshake and removes its handshake.
--
-- Handshaking is bypassed when the controller FSM is initializing the SD card.
elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = LO then
null; -- Waiting for the host to acknowledge handshake.
elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = HI then
txData_v := data_i; -- Get any data passed from the host.
hndShk_r <= LO; -- The host acknowledged, so lower the controller handshake.
elsif state_v /= START_INIT and hndShk_r = LO and hndShk_i = HI then
null; -- Waiting for the host to lower its handshake.
elsif (state_v = START_INIT) or (hndShk_r = LO and hndShk_i = LO) then
-- Both handshakes are low, so the controller operations can proceed.
busy_o <= YES; -- Busy by default. Only false when waiting for R/W from host or stalled by error.
case state_v is
when START_INIT => -- Deselect the SD card and send it a bunch of clock pulses with MOSI high.
error_o <= (others => ZERO); -- Clear error flags.
clkDivider_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- Use slow SPI clock freq during init.
sclkPhaseTimer_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- and set the duration of the next clock phase.
sclk_r <= LO; -- Start with low clock to the SD card.
hndShk_r <= LO; -- Initialize handshake signal.
addr_v := (others => ZERO); -- Initialize address.
rtnData_v := false; -- No data is returned to host during initialization.
bitCnt_v := NUM_INIT_CLKS_C; -- Generate this many clock pulses.
state_v := DESELECT; -- De-select the SD card and pulse SCLK.
rtnState_v := SEND_CMD0; -- Then go to this state after the clock pulses are done.
when SEND_CMD0 => -- Put the SD card in the IDLE state.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD0_C & x"00000000" & x"95"; -- 0x95 is the correct CRC for this command.
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := CHK_CMD0_RESPONSE; -- Then check the response to the command.
when CHK_CMD0_RESPONSE => -- Check card's R1 response to the CMD0.
if rx_v = IDLE_NO_ERRORS_C then
state_v := SEND_CMD8; -- Continue init if SD card is in IDLE state with no errors
else
state_v := SEND_CMD0; -- Otherwise, try CMD0 again.
end if;
when SEND_CMD8 => -- This command is needed to initialize SDHC cards.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD8_C & x"000001aa" & x"87"; -- 0x87 is the correct CRC for this command.
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := false; -- Don't de-select, need to get the R7 response sent from the SD card.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := GET_CMD8_RESPONSE; -- Then go to this state after the command is sent.
when GET_CMD8_RESPONSE => -- Get the R7 response to CMD8.
cs_bo <= LO; -- The SD card should already be enabled, but let's be explicit.
bitCnt_v := 31; -- Four bytes (32 bits) in R7 response.
getCmdResponse_v := false; -- Not sending a command that generates a response.
doDeselect_v := true; -- De-select card to end the command after getting the four bytes.
state_v := RX_BITS; -- Go to FSM subroutine to get the R7 response.
rtnState_v := SEND_CMD55; -- Then go here (we don't care what the actual R7 response is).
when SEND_CMD55 => -- Send CMD55 as preamble of ACMD41 initialization command.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD55_C & x"00000000" & FAKE_CRC_C;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := SEND_CMD41; -- Then go to this state after the command is sent.
when SEND_CMD41 => -- Send the SD card the initialization command.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD41_C & x"40000000" & FAKE_CRC_C;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := CHK_ACMD41_RESPONSE; -- Then check the response to the command.
when CHK_ACMD41_RESPONSE =>
-- The CMD55, CMD41 sequence should cause the SD card to leave the IDLE state
-- and become ready for SPI read/write operations. If still IDLE, then repeat the CMD55, CMD41 sequence.
-- If one of the R1 error flags is set, then report the error and stall.
if rx_v = ACTIVE_NO_ERRORS_C then -- Not IDLE, no errors.
state_v := WAIT_FOR_HOST_RW; -- Start processing R/W commands from the host.
elsif rx_v = IDLE_NO_ERRORS_C then -- Still IDLE but no errors.
state_v := SEND_CMD55; -- Repeat the CMD55, CMD41 sequence.
else -- Some error occurred.
state_v := REPORT_ERROR; -- Report the error and stall.
end if;
when WAIT_FOR_HOST_RW => -- Wait for the host to read or write a block of data from the SD card.
clkDivider_v := SCLK_PHASE_PERIOD_C - 1; -- Set SPI clock frequency for normal operation.
getCmdResponse_v := true; -- Get R1 response to any commands issued to the SD card.
if rd_i = YES then -- send READ command and address to the SD card.
cs_bo <= LO; -- Enable the SD card.
if continue_i = YES then -- Multi-block read. Use stored address.
if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing,
addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address.
else -- SDHC cards use block-addressing,
addr_v := addr_v + 1; -- so just increment current block address.
end if;
txCmd_v := READ_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C;
else -- Single-block read.
txCmd_v := READ_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host.
addr_v := unsigned(addr_i); -- Store address for multi-block operations.
end if;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
byteCnt_v := RD_BLK_SZ_C;
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := RD_BLK; -- Then go to this state to read the data block.
elsif wr_i = YES then -- send WRITE command and address to the SD card.
cs_bo <= LO; -- Enable the SD card.
if continue_i = YES then -- Multi-block write. Use stored address.
if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing,
addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address.
else -- SDHC cards use block-addressing,
addr_v := addr_v + 1; -- so just increment current block address.
end if;
txCmd_v := WRITE_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C;
else -- Single-block write.
txCmd_v := WRITE_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host.
addr_v := unsigned(addr_i); -- Store address for multi-block operations.
end if;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
byteCnt_v := WR_BLK_SZ_C; -- Set number of bytes to write.
state_v := START_TX; -- Go to this FSM subroutine to send the command
rtnState_v := WR_BLK; -- then go to this state to write the data block.
else -- Do nothing and wait for command from host.
cs_bo <= HI; -- Deselect the SD card.
busy_o <= NO; -- SD card interface is waiting for R/W from host, so it's not busy.
state_v := WAIT_FOR_HOST_RW; -- Keep waiting for command from host.
end if;
when RD_BLK => -- Read a block of data from the SD card.
-- Some default values for these...
rtnData_v := false; -- Data is only returned to host in one place.
bitCnt_v := rx_v'length - 1; -- Receiving byte-sized data.
state_v := RX_BITS; -- Call the bit receiver routine.
rtnState_v := RD_BLK; -- Return here when done receiving a byte.
if byteCnt_v = RD_BLK_SZ_C then -- Initial read to prime the pump.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = RD_BLK_SZ_C -1 then -- Then look for the data block start token.
if rx_v = NO_TOKEN_C then -- Receiving 0xFF means the card hasn't responded yet. Keep trying.
null;
elsif rx_v = START_TOKEN_C then
rtnData_v := true; -- Found the start token, so now start returning data byes to the host.
byteCnt_v := byteCnt_v - 1;
else -- Getting anything else means something strange has happened.
state_v := REPORT_ERROR;
end if;
elsif byteCnt_v >= 3 then -- Now bytes of data from the SD card are received.
rtnData_v := true; -- Return this data to the host.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = 2 then -- Receive the 1st CRC byte at the end of the data block.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = 1 then -- Receive the 2nd
byteCnt_v := byteCnt_v - 1;
else -- Reading is done, so deselect the SD card.
sclk_r <= LO;
bitCnt_v := 2;
state_v := DESELECT;
rtnState_v := WAIT_FOR_HOST_RW;
end if;
when WR_BLK => -- Write a block of data to the SD card.
-- Some default values for these...
getCmdResponse_v := false; -- Sending data bytes so there's no command response from SD card.
bitCnt_v := txData_v'length; -- Transmitting byte-sized data.
state_v := START_TX; -- Call the bit transmitter routine.
rtnState_v := WR_BLK; -- Return here when done transmitting a byte.
if byteCnt_v = WR_BLK_SZ_C then
txData_v := NO_TOKEN_C; -- Hold MOSI high for one byte before data block goes out.
elsif byteCnt_v = WR_BLK_SZ_C - 1 then -- Send start token.
txData_v := START_TOKEN_C; -- Starting token for data block.
elsif byteCnt_v >= 4 then -- Now send bytes in the data block.
hndShk_r <= HI; -- Signal host to provide data.
-- The transmit shift register is loaded with data from host in the handshaking section above.
elsif byteCnt_v = 3 or byteCnt_v = 2 then -- Send two phony CRC bytes at end of packet.
txData_v := FAKE_CRC_C;
elsif byteCnt_v = 1 then
bitCnt_v := rx_v'length - 1;
state_v := RX_BITS; -- Get response of SD card to the write operation.
rtnState_v := WR_WAIT;
else -- Check received response byte.
if std_match(rx_v, DATA_ACCEPTED_C) then -- Data block was accepted.
state_v := WR_WAIT; -- Wait for the SD card to finish writing the data into Flash.
else -- Data block was rejected.
error_o(15 downto 8) <= rx_v;
state_v := REPORT_ERROR; -- Report the error.
end if;
end if;
byteCnt_v := byteCnt_v - 1;
when WR_WAIT => -- Wait for SD card to finish writing the data block.
-- The SD card will pull MISO low while it is busy, and raise it when it is done.
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
if sclk_r = HI and miso_i = HI then -- Data block has been written, so deselect the SD card.
bitCnt_v := 2;
state_v := DESELECT;
rtnState_v := WAIT_FOR_HOST_RW;
end if;
when START_TX =>
-- Start sending command/data by lowering SCLK and outputing MSB of command/data
-- so it has plenty of setup before the rising edge of SCLK.
sclk_r <= LO; -- Lower the SCLK (although it should already be low).
sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the low SCLK.
mosi_o <= tx_v(tx_v'high); -- Output MSB of command/data.
tx_v := tx_v(tx_v'high-1 downto 0) & ONE; -- Shift command/data register by one bit.
bitCnt_v := bitCnt_v - 1; -- The first bit has been sent, so decrement bit counter.
state_v := TX_BITS; -- Go here to shift out the rest of the command/data bits.
when TX_BITS => -- Shift out remaining command/data bits and (possibly) get response from SD card.
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
if sclk_r = HI then
-- SCLK is going to be flipped from high to low, so output the next command/data bit
-- so it can setup while SCLK is low.
if bitCnt_v /= 0 then -- Keep sending bits until the bit counter hits zero.
mosi_o <= tx_v(tx_v'high);
tx_v := tx_v(tx_v'high-1 downto 0) & ONE;
bitCnt_v := bitCnt_v - 1;
else
if getCmdResponse_v then
state_v := GET_CMD_RESPONSE; -- Get a response to the command from the SD card.
bitCnt_v := Response_t'length - 1; -- Length of the expected response.
else
state_v := rtnState_v; -- Return to calling state (no need to get a response).
sclkPhaseTimer_v := 0; -- Clear timer so next SPI op can begin ASAP with SCLK low.
end if;
end if;
end if;
when GET_CMD_RESPONSE => -- Get the response of the SD card to a command.
if sclk_r = HI and miso_i = LO then -- MISO will be held high by SD card until 1st bit
-- of R1 response, which is 0.
rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; -- Shift in the MSB bit of the response.
bitCnt_v := bitCnt_v - 1;
state_v := RX_BITS; -- Now receive the reset of the response.
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when RX_BITS => -- Receive bits from the SD card.
if sclk_r = HI then -- Bits enter after the rising edge of SCLK.
rx_v := rx_v(rx_v'high-1 downto 0) & miso_i;
if bitCnt_v /= 0 then -- More bits left to receive.
bitCnt_v := bitCnt_v - 1;
else -- Last bit has been received.
if rtnData_v then -- Send the received data to the host.
data_o <= rx_v; -- Output received data to the host.
hndShk_r <= HI; -- Signal to the host that the data is ready.
end if;
if doDeselect_v then
bitCnt_v := 1;
state_v := DESELECT; -- De-select SD card before returning.
else
state_v := rtnState_v; -- Otherwise, return to calling state without de-selecting.
end if;
end if;
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when DESELECT => -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.)
doDeselect_v := false; -- Once the de-select is done, clear the flag that caused it.
cs_bo <= HI; -- De-select the SD card.
mosi_o <= HI; -- Keep the data input of the SD card pulled high.
state_v := PULSE_SCLK; -- Pulse the clock so the SD card will see the de-select.
sclk_r <= LO; -- Clock is set low so the next rising edge will see the new CS and MOSI
sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the next clock phase.
when PULSE_SCLK => -- Issue some clock pulses. (Must enter with sclk at zero.)
if sclk_r = HI then
if bitCnt_v /= 0 then
bitCnt_v := bitCnt_v - 1;
else -- Return to the calling routine when the pulse counter reaches zero.
state_v := rtnState_v;
end if;
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when REPORT_ERROR => -- Report the error code and stall here until a reset occurs.
error_o(rx_v'range) <= rx_v; -- Output the SD card response as the error code.
busy_o <= NO; -- Not busy.
when others =>
state_v := START_INIT;
end case;
end if;
end if;
end process;
sclk_o <= sclk_r; -- Output the generated SPI clock for the SD card.
hndShk_o <= hndShk_r; -- Output the generated handshake to the host.
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SdCardCtrl is
begin
data_o <= (others => 'X'); -- Data read from block.
busy_o <= LO; -- High when controller is busy performing some operation.
cs_bo <= HI; -- Active-low chip-select.
sclk_o <= LO; -- Serial clock to SD card.
mosi_o <= HI; -- Serial data output to SD card.
state <= (others => 'X'); -- state debugging only
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | cd144013bbfa78dcbcc872ae935ba768 | 0.573318 | 3.926423 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/Mux5x1.vhd | 1 | 833 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux5x1 is
generic (N : integer := 16);
port (B : in std_logic_vector(N-1 downto 0);
C : in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(N-1 downto 0);
E : in std_logic_vector(N-1 downto 0);
sel : in std_logic_vector(2 downto 0);
O : out std_logic_vector(N-1 downto 0)
);
end Mux5x1;
architecture Behavioral of Mux5x1 is
constant S : std_logic_vector(N-1 downto 0) := (others => '0');
begin
process(B, C, D, E, sel)
begin
case sel is
when "000" => -- 0
O <= S;
when "001" => -- +A
O <= B;
when "010" => -- -A
O <= C;
when "011" => -- +2A
O <= D;
when "100" => -- -2A
O <= E;
when others =>
O <= (others => '0');
end case;
end process;
end Behavioral;
| lgpl-3.0 | 8c9570c938f96741ca94df038b89c68e | 0.527011 | 2.644444 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/51a8c173/hdl/src/vhdl/upcnt_n.vhd | 7 | 7,208 | -------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
| apache-2.0 | 2e7c50de5f0c7cceadf967c41714842d | 0.410794 | 5.27672 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_tbl_testbench_192bits.vhd | 1 | 10,562 | -- Twofish_ecb_tbl_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tbl_testbench192 is
end tbl_testbench192;
architecture tbl_encryption192_testbench_arch of tbl_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round192
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_tbl_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_tbl_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 50) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_encryption_circuit: twofish_encryption_round192
port map (
in1_ter192 => to_round(127 downto 96),
in2_ter192 => to_round(95 downto 64),
in3_ter192 => to_round(63 downto 32),
in4_ter192 => to_round(31 downto 0),
in_Sfirst_ter192 => Sfirst,
in_Ssecond_ter192 => Ssecond,
in_Sthird_ter192 => Sthird,
in_key_up_ter192 => key_up,
in_key_down_ter192 => key_down,
out1_ter192 => to_encr_reg128(127 downto 96),
out2_ter192 => to_encr_reg128(95 downto 64),
out3_ter192 => to_encr_reg128(63 downto 32),
out4_ter192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
tbl_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable counter : integer range 1 to 50 := 1;
variable round : integer range 0 to 16 := 0;
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(pt_f,input_data);
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Tables Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process tbl_proc;
end tbl_encryption192_testbench_arch;
| gpl-2.0 | 8c4b955e8950c9d3f8fed4d3d7419b4f | 0.648646 | 2.682753 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/14-MESA-IA/asap-alap-random/mesaia_asap.vhd | 1 | 9,734 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:53:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 30);
output1, output2, output3, output4: OUT unsigned(0 TO 31));
END mesaia_asap_entity;
ARCHITECTURE mesaia_asap_description OF mesaia_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register15: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register16: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register17: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register18: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register19: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register20: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register21: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register22: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register23: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register24: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register25: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register26: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register27: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register28: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register29: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register30: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register31: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register32: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register33: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register34: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register35: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register36: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register37: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register38: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register39: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register40: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register41: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register42: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register43: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register44: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register45: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register46: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register47: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register48: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 + 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
register25 := input25 * 25;
register26 := input26 * 26;
register27 := input27 * 27;
register28 := input28 * 28;
register29 := input29 + 29;
register30 := input30 * 30;
register31 := input31 * 31;
register32 := input32 + 32;
register33 := input33 * 33;
register34 := input34 * 34;
register35 := input35 * 35;
register36 := input36 + 36;
register37 := input37 * 37;
register38 := input38 * 38;
register39 := input39 + 39;
register40 := input40 * 40;
register41 := input41 * 41;
register42 := input42 * 42;
register43 := input43 + 43;
register44 := input44 * 44;
register45 := input45 + 45;
register46 := input46 + 46;
register47 := input47 * 47;
register48 := input48 + 48;
WHEN "00000010" =>
register1 := register24 + register1;
register2 := register2 + register32;
register3 := register3 + register39;
register5 := register38 + register5;
register6 := register10 + register6;
register7 := register40 + register7;
register9 := register9 + register48;
register10 := register22 + register11;
register11 := register12 + register45;
register12 := register14 + register36;
register14 := register27 + register15;
register15 := register17 + register43;
register17 := register28 + register18;
register18 := register19 + register23;
register19 := register34 + register29;
register22 := register44 + register46;
WHEN "00000011" =>
register1 := register25 + register1;
register2 := register33 + register2;
register3 := register4 + register3;
register4 := register37 + register5;
register5 := register30 + register6;
register6 := register41 + register7;
register7 := register8 + register9;
register8 := register21 + register10;
register9 := register31 + register11;
register10 := register13 + register12;
register11 := register26 + register14;
register12 := register16 + register15;
register13 := register42 + register17;
register14 := register20 + register18;
register15 := register35 + register19;
register16 := register47 + register22;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register6 := ((NOT register6) + 1) XOR register6;
register7 := ((NOT register7) + 1) XOR register7;
register8 := ((NOT register8) + 1) XOR register8;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000101" =>
register1 := register6 - register1;
register4 := register16 - register4;
register6 := register7 - register12;
register7 := register13 - register14;
WHEN "00000110" =>
register1 := register1 * 74;
register4 := register4 * 76;
register6 := register6 * 78;
register7 := register7 * 80;
WHEN "00000111" =>
register1 := register15 + register1;
register3 := register3 + register4;
register4 := register11 + register6;
register6 := register8 + register7;
WHEN "00001000" =>
output1 <= register1(0 TO 14) & register9(0 TO 15);
output2 <= register3(0 TO 14) & register5(0 TO 15);
output3 <= register4(0 TO 14) & register2(0 TO 15);
output4 <= register6(0 TO 14) & register10(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_asap_description; | gpl-3.0 | 69a9f71415adda7993344116d8612cc3 | 0.715944 | 3.796412 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/fifo_generator_top_bi_sim.vhd | 5 | 28,804 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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dwu+/i7zNaTdGyATccZTvAjQLzFaSsUFyUaE8a8uHZ4M
`protect end_protected
| apache-2.0 | 78b9c4d88422b0c1fcfee5184496b2b9 | 0.943168 | 1.847002 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/Instr_decoder.vhd | 1 | 4,995 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Instr_decoder is
Port ( instruction : in STD_LOGIC_VECTOR (31 downto 0);
index : out STD_LOGIC_VECTOR (5 downto 0)
);
end Instr_decoder;
architecture Behavioral of Instr_decoder is
--OP_SPECIAL, "100000", ADD
--OP_NORMAL , "001000", ADDI
--OP_NORMAL , "001001", ADDIU
--OP_SPECIAL, "100001", ADDU
--OP_SPECIAL, "100100", AND
--OP_NORMAL , "001100", ANDI
--OP_NORMAL , "000100", BEQ
--OP_REGIMM , "000001", BGEZ
--OP_REGIMM , "010001", BGEZAL
--OP_NORMAL , "000111", BGTZ
--OP_NORMAL , "000110", BLEZ
--OP_REGIMM , "000000", BLTZ
--OP_REGIMM , "010000", BLTZAL
--OP_NORMAL , "000101", BNE
--OP_SPECIAL, "001101", BREAK
--OP_COP0 , "000001", COP0
--OP_NORMAL , "000010", J
--OP_NORMAL , "000011", JAL
--OP_SPECIAL, "001001", JALR
--OP_SPECIAL, "001000", JR
--OP_NORMAL , "001111", LUI
--OP_NORMAL , "100011", LW
--OP_NORMAL , "110000", LWC0
--OP_COP0 , "000000", MFC0
--OP_SPECIAL, "010000", MFHI
--OP_SPECIAL, "010010", MFLO
--OP_COP0 , "000100", MTC0
--OP_SPECIAL, "010001", MTHI
--OP_SPECIAL, "010011", MTLO
--OP_SPECIAL, "011000", MULT
--OP_SPECIAL, "011001", MULT
--OP_SPECIAL, "100111", NOR
--OP_SPECIAL, "100101", OR
--OP_NORMAL , "001101", ORI
--OP_SPECIAL, "000000", SLL
--OP_SPECIAL, "000100", SLLV
--OP_SPECIAL, "101010", SLT
--OP_NORMAL , "001010", SLTI
--OP_NORMAL , "001011", SLTIU
--OP_SPECIAL, "101011", SLTU
--OP_SPECIAL, "000011", SRA
--OP_SPECIAL, "000111", SRAV
--OP_SPECIAL, "000010", SRL
--OP_SPECIAL, "000110", SRLV
--OP_SPECIAL, "100010", SUB
--OP_SPECIAL, "100011", SUBU
--OP_NORMAL , "101011", SW
--OP_NORMAL , "111000", SWC0
--OP_SPECIAL, "001100", SYSC
--OP_SPECIAL, "100110", XOR
--OP_NORMAL , "001110", XORI
begin
process(instruction)
begin
case instruction(31 downto 26) is
when "000000" => --SPECIAL MODE
case instruction(5 downto 0) is
when "000000" => index <= "100010";
when "000010" => index <= "101010";
when "000011" => index <= "101000";
when "000100" => index <= "100011";
when "000110" => index <= "101011";
when "000111" => index <= "101001";
when "001000" => index <= "010011";
when "001001" => index <= "010010";
when "001100" => index <= "110000";
when "001101" => index <= "001110";
when "010000" => index <= "011000";
when "010001" => index <= "011011";
when "010010" => index <= "011001";
when "010011" => index <= "011100";
when "011000" => index <= "011101";
when "011001" => index <= "011110";
when "100000" => index <= "000000";
when "100001" => index <= "000011";
when "100010" => index <= "101100";
when "100011" => index <= "101101";
when "100100" => index <= "000100";
when "100101" => index <= "100000";
when "100110" => index <= "110001";
when "100111" => index <= "011111";
when "101010" => index <= "100100";
when "101011" => index <= "100111";
when others => index <= "111111";
end case;
-- op_code <= instruction(5 downto 0);
when "000001" => --REGIMM MODE
case '0' & instruction(20 downto 16) is
when "000000" => index <= "100010";
when "000001" => index <= "101010";
when "010000" => index <= "101000";
when "010001" => index <= "100011";
when others => index <= "111111";
end case;
-- op_code <= '0' & instruction(20 downto 16);
when "010000" => --COP0 MODE
case '0' & instruction(25 downto 21) is
when "000000" => index <= "010111";
when "000001" => index <= "001111";
when "000100" => index <= "011010";
when others => index <= "111111";
end case;
-- op_code <= '0' & instruction(25 downto 21);
when others => --NORMAL MODE
case instruction(31 downto 26)is
when "000010" => index <= "010000";
when "000011" => index <= "010001";
when "000100" => index <= "000110";
when "000101" => index <= "001101";
when "000110" => index <= "001010";
when "000111" => index <= "001001";
when "001000" => index <= "000001";
when "001001" => index <= "000010";
when "001010" => index <= "100101";
when "001011" => index <= "100110";
when "001100" => index <= "000101";
when "001101" => index <= "100001";
when "001110" => index <= "110010";
when "001111" => index <= "010100";
when "100011" => index <= "010101";
when "101011" => index <= "101110";
when "110000" => index <= "010110";
when "111000" => index <= "101111";
when others => index <= "111111";
end case;
-- op_code <= instruction(31 downto 26);
end case;
end process;
end Behavioral;
| lgpl-3.0 | 74610db8a41874e1c8d5daa0cae402bc | 0.532332 | 2.566804 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/test_c_signal.vhd | 1 | 2,486 | use Std.Textio.all;
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
LIBRARY WORK;
use WORK.ALL;
entity test_Signal is end;
architecture test_Signal of test_Signal is
component C_Signal
generic (width : INTEGER := 4);
port (Input : in std_logic_Vector((width - 1) downto 0);
Store, Update, Clear, clock : in std_logic;
Output : out std_logic_Vector((width + 1) downto 0));
end component;
for all : C_Signal use entity Work.C_Signal(Behavior);
signal INPUT : std_logic_vector(3 downto 0) ;
signal OUTPUT : std_logic_vector(5 downto 0) ;
signal CLEAR : std_logic ;
signal clock : std_logic ;
signal STORE : std_logic ;
signal UPDATE : std_logic ;
begin
Signal1 : C_Signal generic map (4)
port map( Clear => CLEAR , clock => clock, input(3) => INPUT(3),input(2) => INPUT(2),input(1) => INPUT(1),input(0) => INPUT(0), output(5)=>output(5),output(4)=>output(4),output(3) => OUTPUT(3),output(2) => OUTPUT(2),output(1) => OUTPUT(1),output(0) => OUTPUT(0), Store => STORE, Update => UPDATE);
test_process : process
begin
clear <= '0';
clock <= '1';
store <= '1';
update <= '0';
input <= "1001";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '0';
update <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '0';
update <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '1';
update <= '1';
input <= "1111";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '1';
clock <= '1';
store <= '1';
update <= '1';
input <= "1111";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
wait;
------------ end checking --------------
end process test_process ;
end test_Signal;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
| mit | f8640eba75e6b78eb2dbc4fb36ef4e80 | 0.41794 | 4.095552 | false | true | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_ibea.vhd | 1 | 2,968 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_ibea_entity;
ARCHITECTURE mpegmv_ibea_description OF mpegmv_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register1 + 5;
register4 := input4 * 6;
register2 := register2 + 8;
WHEN "00000011" =>
register1 := register4 + register1;
register4 := input5 * 9;
WHEN "00000100" =>
register1 := register4 + register1;
register4 := input6 * 10;
register5 := input7 * 11;
register2 := register3 + register2;
WHEN "00000101" =>
register3 := input8 * 12;
register5 := register5 + 14;
register6 := input9 * 15;
register1 := ((NOT register1) + 1) XOR register1;
register2 := register4 + register2;
WHEN "00000110" =>
register3 := register3 + 19;
register4 := input10 * 20;
register7 := input11 * 21;
WHEN "00000111" =>
register4 := register4 + register5;
register5 := input12 * 22;
output1 <= register7 + register3;
WHEN "00001000" =>
register3 := register5 + 25;
register4 := register6 + register4;
register5 := input13 * 26;
register2 := ((NOT register2) + 1) XOR register2;
register6 := input14 * 29;
WHEN "00001001" =>
register3 := register6 + register3;
output2 <= register1(0 TO 15) & register4(0 TO 15);
WHEN "00001010" =>
register1 := register5 + register3;
WHEN "00001011" =>
output3 <= register2(0 TO 15) & register1(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_ibea_description; | gpl-3.0 | 98a40ec94bec1ef29d2891cfb9455fe0 | 0.678571 | 3.290466 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_des.vhd | 1 | 2,075 | ---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity input is
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
clear, clock, s_tart : IN std_logic;
finish : OUT std_logic
);
end input;
architecture rtl2 of input is
component input_controller
port
(
clock, reset, s_tart : IN std_logic;
finish : OUT std_logic;
control_out : OUT std_logic_vector(0 to 18)
);
end component;
for all : input_controller use entity work.input_controller(moore);
component input_dp
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl : IN std_logic_vector(0 to 18);
clear, clock : IN std_logic
);
end component;
for all : input_dp use entity work.input_dp(rtl1);
signal sig_con_out : std_logic_vector(0 to 18);
begin
inputcon : input_controller
port map
(
clock => clock,
s_tart => s_tart,
reset => clear,
finish => finish,
control_out => sig_con_out
);
inputdp : input_dp
port map
(
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
h => h,
i => i,
ctrl(0) => sig_con_out(0),
ctrl(1) => sig_con_out(1),
ctrl(2) => sig_con_out(2),
ctrl(3) => sig_con_out(3),
ctrl(4) => sig_con_out(4),
ctrl(5) => sig_con_out(5),
ctrl(6) => sig_con_out(6),
ctrl(7) => sig_con_out(7),
ctrl(8) => sig_con_out(8),
ctrl(9) => sig_con_out(9),
ctrl(10) => sig_con_out(10),
ctrl(11) => sig_con_out(11),
ctrl(12) => sig_con_out(12),
ctrl(13) => sig_con_out(13),
ctrl(14) => sig_con_out(14),
ctrl(15) => sig_con_out(15),
ctrl(16) => sig_con_out(16),
ctrl(17) => sig_con_out(17),
ctrl(18) => sig_con_out(18),
clock => clock,
clear => clear
);
end rtl2;
| mit | 59c1e0a20147892a909163e5a5b728d1 | 0.517108 | 2.48503 | false | false | false | false |
rcls/sdr | vhdl/go.vhd | 1 | 17,393 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.all;
use work.defs.all;
entity go is
port(adc_p : in unsigned7;
adc_n : in unsigned7;
adc_clk_p : out std_logic;
adc_clk_n : out std_logic;
adc_reclk_p : in std_logic;
adc_reclk_n : in std_logic;
adc_sen : out std_logic := '0';
adc_sdata : out std_logic := '0';
adc_sclk : out std_logic := '0';
adc_reset : out std_logic := '1';
audio_scki, audio_lrck, audio_data, audio_bck : out std_logic;
audio_pd_inv, audio_demp : out std_logic;
usb_d : inout unsigned8;
usb_c : inout unsigned8;
flash_cs_inv, flash_sclk, flash_si : out std_logic;
flash_so : in std_logic;
cpu_ssirx : out std_logic;
cpu_ssitx : in std_logic;
cpu_ssiclk : in std_logic;
cpu_ssifss : in std_logic;
header_16 : out std_logic;
spartan_m0 : in std_logic;
spartan_m1 : in std_logic;
led : out unsigned8;
clkin125 : in std_logic;
clkin125_en : out std_logic);
end go;
architecture go of go is
signal xx, yy : four_mf_signed;
signal xx_mf, yy_mf : mf_signed;
signal xx_buf, yy_buf : signed36;
signal xx_buf_last, yy_buf_last, xx_mf_last, yy_mf_last : std_logic;
signal packet : unsigned(31 downto 0);
-- Generated clock for delivery to ADC.
signal adc_clk : std_logic;
signal adc_clk_neg : std_logic;
signal adc_clk_250 : std_logic;
signal adc_clk_neg_250 : std_logic;
signal adc_clk_200 : std_logic;
signal adc_clk_neg_200 : std_logic;
signal adc_clk_fb : std_logic;
-- Received clk from ADC.
signal adc_reclk_b : std_logic;
signal adc_reclk : std_logic;
signal adc_reclk_diff : std_logic;
-- Regenerated reclk.
signal clk_main : std_logic;
signal clk_main_neg : std_logic;
signal clku_main : std_logic;
signal clku_main_neg : std_logic;
signal clk_main_fb : std_logic;
signal clkin125_b : std_logic;
signal clk_50m : std_logic;
signal clku_50m : std_logic;
signal adc_ddr : unsigned7;
signal adc_data, adc_data_c, adc_data_b : signed14;
attribute keep of adc_data_c : signal is "true";
signal phase : unsigned18;
signal phase_strobe, phase_last : std_logic;
signal ir_data : signed18;
signal ir_strobe : std_logic;
signal ir_last : std_logic;
signal usb_xmit, usb_last : std_logic;
signal usb_xmit_length : integer range 0 to 5;
signal usb_xmit_overrun : std_logic;
signal usb_nRXFb, usb_nTXEb : std_logic := '1';
signal usb_nRXF, usb_nTXE : std_logic := '1';
signal xmit_SIWU : std_logic;
attribute keep of usb_nRXFb, usb_nTXEb : signal is "true";
signal low_data : signed32;
signal low_strobe : std_logic;
signal low_last : std_logic;
signal out_data : signed32;
signal out_last : std_logic;
-- The configuration loaded via the CPU.
constant config_bytes : integer := 28;
signal config : unsigned(config_bytes * 8 - 1 downto 0);
signal conf_strobe, conf_strobe2, conf_strobe3, conf_strobe_fast :
unsigned(config_bytes - 1 downto 0);
alias to_usb_data : unsigned8 is config(7 downto 0);
alias adc_control : unsigned8 is config(15 downto 8);
-- Control for data in to USB host.
alias xmit_control : unsigned8 is config(23 downto 16);
-- Channel to select from time-multiplexed data.
alias xmit_channel : unsigned2 is xmit_control(1 downto 0);
-- Data source.
alias xmit_source : unsigned3 is xmit_control(4 downto 2);
-- Strobe SIWU to push data through to host.
alias xmit_low_latency : std_logic is xmit_control(7);
-- Ignore the TX handshake and shovel data at 12.5 MB/s.
alias xmit_turbo : std_logic is xmit_control(6);
alias flash_control : unsigned8 is config(31 downto 24);
alias clock_select : std_logic is flash_control(7);
alias burst_start : std_logic is flash_control(6);
alias bandpass_freq : unsigned8 is config(39 downto 32);
alias bandpass_gain : unsigned8 is config(47 downto 40);
signal bandpass_strobe : std_logic := '0';
signal bandpass_r, bandpass_i : signed15;
alias sampler_rate : unsigned8 is config(55 downto 48);
alias sampler_decay : unsigned16 is config(71 downto 56);
signal sampler_data : signed15;
signal sampler_strobe : std_logic;
alias pll_decay : unsigned8 is config(79 downto 72);
alias audio_channel : unsigned8 is config(87 downto 80);
signal usb_byte_in : unsigned8;
signal usb_byte_in_strobe, usb_byte_in_strobe2 : std_logic;
signal burst_data : signed15;
signal burst_strobe : std_logic;
signal led_off : unsigned8 := x"fe";
signal usbd_out : unsigned8;
signal usb_oe_n : std_logic;
attribute S : string;
attribute S of usb_c : signal is "yes";
attribute S of led : signal is "yes";
attribute pullup : string;
attribute pullup of spartan_m0, spartan_m1 : signal is "TRUE";
alias clk_main_locked : std_logic is led_off(1);
alias adc_clk_locked : std_logic is led_off(2);
-- spi conf stuff.
constant spi_data_bytes : integer := 44;
signal spi_data : unsigned(spi_data_bytes * 8 - 1 downto 0) :=
(others => '0');
signal spi_data_ack : unsigned(spi_data_bytes - 1 downto 0) :=
(others => '0');
signal usb_read_ok : std_logic := '1';
alias spied_flash : unsigned8 is spi_data(31 downto 24);
alias spied_pll_freq : unsigned(31 downto 0) is spi_data(287 downto 256);
alias spied_pll_error : unsigned(31 downto 0) is spi_data(319 downto 288);
alias spied_pll_level : unsigned(31 downto 0) is spi_data(351 downto 320);
alias spied_pll_strobe : std_logic is spi_data_ack(43);
signal pll_phasor : unsigned18;
signal cpu_ssifss2, cpu_ssitx2, cpu_ssiclk2 : std_logic := '1';
signal cpu_ssifss3, cpu_ssitx3, cpu_ssiclk3 : std_logic := '1';
attribute keep of cpu_ssifss2, cpu_ssitx2, cpu_ssiclk2 : signal is "true";
signal xy_strobe, xy_last : std_logic;
signal xy_data : unsigned(30 downto 0);
constant X40 : unsigned(39 downto 0) := (others => 'X');
begin
usb_d <= usbd_out when usb_oe_n = '0' else "ZZZZZZZZ";
usb_c(7 downto 5) <= "ZZZ";
usb_c(0) <= 'Z'; -- nRXF.
usb_c(1) <= 'Z'; -- nTXE.
-- SIWU can be strobed either by the USBIO unit, or manually.
usb_c(4) <= xmit_SIWU and not (xmit_low_latency and xmit_turbo);
clkin125_en <= '1';
audio_pd_inv <= '1';
audio_demp <= '0';
adc_sen <= adc_control(0);
adc_sdata <= adc_control(1);
adc_sclk <= adc_control(2);
adc_reset <= adc_control(3);
flash_si <= flash_control(0);
flash_cs_inv <= flash_control(1);
flash_sclk <= flash_control(2);
led_control: for i in 0 to 7 generate
led(i) <= '0' when led_off(i) = '0' else 'Z';
end generate;
led_off(5) <= not usb_xmit_overrun or xmit_turbo;
led_off(6) <= spartan_m0;
led_off(7) <= not spartan_m1;
spi : entity spiconf
generic map(
config_bytes, spi_data_bytes,
x"55642576" & x"0067d567" & x"005ed289" &
X40 & x"00" & x"0b" & x"0000" & x"ff" & x"0000"
& x"0f" & x"98" & x"09" & x"00")
port map(cpu_ssifss3, cpu_ssitx3, cpu_ssirx, cpu_ssiclk3,
cpu_ssifss, cpu_ssitx,
spi_data, spi_data_ack, config, conf_strobe, clk_50m);
-- Byte zero is usb data to spi. Byte 3 is flash data to spi.
spi_data(23 downto 8) <= config(23 downto 8);
spi_data(87 downto 32) <= config(87 downto 32);
spi_data(223 downto 128) <= config(223 downto 128);
process
begin
wait until rising_edge(clk_50m);
spied_flash(0) <= flash_so;
if usb_byte_in_strobe = '1' then
spi_data(7 downto 0) <= usb_byte_in;
elsif spi_data_ack(0) = '1' and usb_byte_in_strobe2 = '0' then
spi_data(7 downto 0) <= x"00";
end if;
if usb_byte_in_strobe = '0' and spi_data(7 downto 0) = x"00" then
usb_read_ok <= '1';
else
usb_read_ok <= '0';
end if;
usb_byte_in_strobe2 <= usb_byte_in_strobe;
conf_strobe2 <= conf_strobe;
end process;
process
begin
wait until rising_edge(clk_main);
conf_strobe3 <= conf_strobe2;
conf_strobe_fast <= conf_strobe2 and not conf_strobe3;
end process;
blinky : entity blinkoflow port map(adc_data_b, led_off(4), open, clk_main);
dc0: entity downconvert port map (
adc_data_b, config(159 downto 152), xx(0), yy(0),
config(151 downto 128), clk_main);
dc1: entity downconvert port map (
adc_data_b, config(191 downto 184), xx(1), yy(1),
config(183 downto 160), clk_main);
dcpll : entity downconvertpll
port map(adc_data_b, config(215 downto 192), config(223 downto 216),
pll_decay(3 downto 0),
conf_strobe_fast(26), xx(2), yy(2), pll_phasor,
spied_pll_freq, spied_pll_error, spied_pll_level, spied_pll_strobe,
clk_main);
xfilter: entity multifilter port map(xx, xx_mf, xx_mf_last, clk_main);
yfilter: entity multifilter port map(yy, yy_mf, yy_mf_last, clk_main);
xcheby: entity quadcheby port map(
xx_mf, xx_buf, xx_mf_last, xx_buf_last, clk_main);
ycheby: entity quadcheby port map(
yy_mf, yy_buf, yy_mf_last, yy_buf_last, clk_main);
ph: entity phasedetect
port map(xx_buf, yy_buf, xx_buf_last,
phase, phase_strobe, phase_last, pll_phasor, clk_main);
irf: entity irfir
generic map (acc_width => 36, out_width => 18)
port map(phase, phase_last, ir_data, ir_strobe, ir_last, clk_main);
lf: entity lowfir
generic map (acc_width => 37, out_width => 32)
port map(ir_data, ir_last, low_data, low_strobe, low_last, clk_main);
demph: entity quaddemph generic map (32, 40, 32, 1)
port map (low_data, low_strobe, low_last,
out_data, out_last, clk_main);
au: entity audio generic map (bits_per_sample => 32)
port map (out_data, out_data, audio_channel(1 downto 0), out_last,
audio_scki, audio_lrck, audio_data, audio_bck, clk_main);
bp : entity bandpass port map (
adc_data_b, bandpass_freq, bandpass_gain,
bandpass_r, bandpass_i, bandpass_strobe, clk_main);
brst : entity burst port map (
adc_data_b, burst_start, burst_data, burst_strobe, clk_main);
smplr : entity sampler port map (
adc_data_b, sampler_decay, sampler_rate, sampler_data, sampler_strobe,
clk_main);
cpuclock : entity clockgen port map (
header_16, spi_data(121 downto 112), clk_main, clk_main_neg, clk_50m);
process
begin
wait until rising_edge(clk_main);
adc_data_c <= adc_data xor "10" & x"000";
adc_data_b <= adc_data_c;
packet <= (others => 'X');
case xmit_source is
when "000" =>
packet(17 downto 0) <= unsigned(ir_data);
packet(22 downto 18) <= "00000";
packet(23) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor ir_strobe;
usb_last <= ir_last;
usb_xmit_length <= 3;
when "001" =>
packet(14 downto 0) <= unsigned(sampler_data);
packet(15) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor sampler_strobe;
usb_last <= '1';
usb_xmit_length <= 2;
when "010" =>
packet(30 downto 0) <= xy_data;
packet(31) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor xy_strobe;
usb_last <= xy_last;
usb_xmit_length <= 4;
when "011" =>
packet(17 downto 0) <= phase;
packet(22 downto 18) <= "00000";
packet(23) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor phase_strobe;
usb_last <= phase_last;
usb_xmit_length <= 3;
when "100" =>
packet(14 downto 0) <= unsigned(bandpass_r);
packet(15) <= '0';
packet(30 downto 16) <= unsigned(bandpass_i);
packet(31) <= usb_xmit_overrun;
usb_xmit_length <= 4;
usb_xmit <= usb_xmit xor bandpass_strobe;
usb_last <= '1';
when "101" =>
packet(14 downto 0) <= unsigned(burst_data);
packet(15) <= usb_xmit_overrun;
usb_xmit_length <= 2;
usb_xmit <= burst_strobe;
usb_last <= '1';
when "110" =>
packet(7 downto 0) <= to_usb_data;
usb_xmit <= usb_xmit xor conf_strobe_fast(0);
usb_last <= '1';
usb_xmit_length <= 1;
when others =>
usb_xmit_length <= 0;
usb_last <= '1';
usb_xmit <= usb_xmit xor ir_strobe;
end case;
end process;
usb: entity usbio
generic map(4)
port map(usbd_in => usb_d, usbd_out => usbd_out, usb_oe_n => usb_oe_n,
usb_nRXF => usb_nRXF, usb_nTXE => usb_nTXE,
usb_nRD => usb_c(2), usb_nWR => usb_c(3),
usb_SIWU => xmit_SIWU, read_ok => usb_read_ok,
byte_in => usb_byte_in, byte_in_strobe => usb_byte_in_strobe,
tx_overrun => usb_xmit_overrun,
packet => packet,
xmit => usb_xmit, last => usb_last,
xmit_channel => xmit_channel, xmit_length => usb_xmit_length,
low_latency => xmit_low_latency, turbo => xmit_turbo,
clk => clk_50m);
process
begin
wait until rising_edge(clk_main_neg);
usb_nRXFb <= usb_c(0);
usb_nTXEb <= usb_c(1);
end process;
process
begin
wait until falling_edge(clk_50m);
usb_nRXF <= usb_nRXFb;
usb_nTXE <= usb_nTXEb;
end process;
process
begin
wait until rising_edge(clk_main);
cpu_ssifss2 <= cpu_ssifss;
cpu_ssitx2 <= cpu_ssitx;
cpu_ssiclk2 <= cpu_ssiclk;
cpu_ssifss3 <= cpu_ssifss2;
cpu_ssitx3 <= cpu_ssitx2;
cpu_ssiclk3 <= cpu_ssiclk2;
if xx_buf_last /= yy_buf_last then
led_off(3) <= '0';
end if;
end process;
-- Every 20 cycles pick up a multifilter output. phase_strobe is a
-- convenient strobe for that.
process
begin
wait until rising_edge(clk_main);
if phase_strobe = '1' then
case pll_decay(5 downto 4) is
when "00" =>
xy_data(30 downto 0) <= unsigned(xx_buf(35 downto 5));
when "01" =>
xy_data(30 downto 0) <= unsigned(yy_buf(35 downto 5));
when others =>
xy_data(14 downto 0) <= unsigned(xx_buf(35 downto 21));
xy_data(15) <= '0';
xy_data(30 downto 16) <= unsigned(yy_buf(35 downto 21));
end case;
xy_last <= xx_buf_last;
end if;
xy_strobe <= phase_strobe;
end process;
-- DDR input from ADC.
adc_input: for i in 0 to 6 generate
adc_in: ibufds generic map (diff_term => true)
port map (I => adc_n(i), IB => adc_p(i), O => adc_ddr(i));
adc_ddr_expand: IDDR2
generic map (ddr_alignment => "C0")
port map (C0 => clk_main, C1 => clk_main_neg,
CE => '1',
D => adc_ddr(i),
Q0 => adc_data(i*2+1), Q1 => adc_data(i*2));
end generate;
-- Clk input from ADC. The ADC drives the data as even on P-falling followed
-- by odd on P-rising.
adc_reclk_in: IBUFGDS
generic map (diff_term => true)
port map(I => adc_reclk_n, IB => adc_reclk_p, O => adc_reclk_b);
-- Are these needed? Do we need to tie them together?
adc_reclk_buf: BUFIO2
port map(I => adc_reclk_b, DIVCLK => adc_reclk,
IOCLK => open, SERDESSTROBE => open);
adc_reclkfb: BUFIO2FB port map(I => clk_main_neg, O => clk_main_fb);
-- Pseudo differential drive of clock to ADC.
adc_clk_ddr_p : oddr2
port map (D0 => '1', D1 => '0', C0 => adc_clk, C1 => adc_clk_neg,
Q => adc_clk_p);
adc_clk_ddr_n : oddr2
port map (D0 => '0', D1 => '1', C0 => adc_clk, C1 => adc_clk_neg,
Q => adc_clk_n);
-- Regenerate the clock from the ADC.
-- We run the PLL oscillator at 1000MHz, i.e., 4 times the input clock.
clk_main_pll : PLL_BASE
generic map(
CLK_FEEDBACK => "CLKOUT0",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 1,
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 4, CLKOUT1_PHASE => 180.0,
CLKOUT2_DIVIDE => 20, CLKOUT2_PHASE => 36.0,
CLKIN_PERIOD => 4.0)
port map(
-- Output clocks
CLKFBIN => clk_main_fb,
CLKOUT0 => clku_main_neg, CLKOUT1 => clku_main, CLKOUT2 => clku_50m,
RST => '0', LOCKED => clk_main_locked,
CLKIN => adc_reclk);
clk_main_bufg : BUFG port map(I => clku_main, O => clk_main);
clk_main_neg_bufg : BUFG port map(I => clku_main_neg, O => clk_main_neg);
clk_50m_bufg : BUFG port map(I => clku_50m, O => clk_50m);
clkin125_bufg : bufg port map(I => clkin125, O => clkin125_b);
-- Generate the clock to the ADC. We run the PLL oscillator at 1000MHz, (8
-- times the input clock), and then generate a 250MHz output.
adc_clk_pll : PLL_BASE
generic map(
BANDWIDTH => "LOW",
CLK_FEEDBACK => "CLKFBOUT",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 8,
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 4, CLKOUT1_PHASE => 180.000,
CLKOUT2_DIVIDE => 5,
CLKOUT3_DIVIDE => 5, CLKOUT3_PHASE => 180.000,
CLKIN_PERIOD => 8.0)
port map(
-- Output clocks
CLKFBIN => adc_clk_fb, CLKFBOUT => adc_clk_fb,
CLKOUT0 => adc_clk_250,CLKOUT1 => adc_clk_neg_250,
CLKOUT2 => adc_clk_200,CLKOUT3 => adc_clk_neg_200,
RST => '0', LOCKED => adc_clk_locked,
CLKIN => clkin125_b);
adc_clk_bufg : BUFGMUX port map (
I0 => adc_clk_250, I1 => adc_clk_200, S => clock_select, O => adc_clk);
adc_clk_neg_bufg : BUFGMUX port map (
I0 => adc_clk_neg_250, I1 => adc_clk_neg_200,
S => clock_select, O => adc_clk_neg);
end go;
| gpl-3.0 | 20e9266f92b19d072e1f29b5341d82c0 | 0.607313 | 3.073511 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_counter.vhd | 15 | 9,203 | -------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
| apache-2.0 | 383a03abdd2765b46443fe8790467dec | 0.403673 | 5.129877 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_nsga2.vhd | 1 | 2,973 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:30:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_nsga2_entity;
ARCHITECTURE ewf_nsga2_description OF ewf_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
WHEN "00001000" =>
register3 := register3 * 12;
register4 := register4 + register5;
register6 := register1 + register6;
WHEN "00001001" =>
register1 := register1 + register6;
output1 <= register6 + register4;
WHEN "00001010" =>
register1 := register1 * 15;
register3 := register2 + register3;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register5 + register3;
WHEN "00001111" =>
register2 := register2 + 22;
WHEN "00010000" =>
register3 := register2 * 24;
WHEN "00010001" =>
register3 := register3 + 26;
WHEN "00010010" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010011" =>
register2 := register1 + 31;
WHEN "00010100" =>
register2 := register2 * 33;
WHEN "00010101" =>
output4 <= register1 + register2;
register1 := register6 + register1;
WHEN "00010110" =>
register1 := register1 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_nsga2_description; | gpl-3.0 | 867b9974979d867563631b32d4ea492b | 0.645812 | 3.146032 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/i2c.vhd | 1 | 11,526 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchronous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
--report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural; | agpl-3.0 | 2d1f5197abb54d544cc0947a901be1bb | 0.452629 | 3.899188 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_status_flags_sshft.vhd | 5 | 23,122 | `protect begin_protected
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| apache-2.0 | 957c81ecbe949776d5550f2effb19961 | 0.943128 | 1.847838 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10,255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
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`protect end_protected
| apache-2.0 | 3d45969fcecfcbc9ee780e658123fb61 | 0.938617 | 1.851666 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/asap-alap-random/fir2_random.vhd | 1 | 3,650 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:43:58)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_random_entity;
ARCHITECTURE fir2_random_description OF fir2_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
register3 := not input3 or input3;
register4 := not input4 or input4;
register5 := not input5 or input5;
register6 := not input6 or input6;
register7 := not input7 or input7;
register8 := not input8 or input8;
register9 := not input9 or input9;
register10 := not input10 or input10;
WHEN "00000010" =>
register11 := not input11 or input11;
register12 := not input12 or input12;
register13 := not input13 or input13;
register14 := not input14 or input14;
register2 := register5 + register2;
WHEN "00000011" =>
register2 := register2 * 16;
register5 := register9 + register7;
register7 := not input15 or input15;
register1 := register13 + register1;
register9 := not input16 or input16;
register6 := register14 + register6;
WHEN "00000100" =>
register6 := register6 * 20;
register5 := register5 * 22;
register3 := register3 + register8;
register4 := register4 + register12;
register7 := register10 + register7;
WHEN "00000101" =>
register3 := register3 * 24;
register4 := register4 * 26;
register8 := register11 + register9;
WHEN "00000110" =>
register7 := register7 * 28;
register8 := register8 * 30;
WHEN "00000111" =>
register1 := register1 * 32;
register5 := register8 + register5;
WHEN "00001000" =>
register5 := register7 + register5;
WHEN "00001001" =>
register4 := register4 + register5;
WHEN "00001010" =>
register4 := register6 + register4;
WHEN "00001011" =>
register3 := register3 + register4;
WHEN "00001100" =>
register1 := register1 + register3;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_random_description; | gpl-3.0 | 9556bf7ae0b1413fb0a90f2a0c8a5a53 | 0.675068 | 3.241563 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/FSM.vhd | 1 | 2,103 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port (
clk : in std_logic;
out_val: out unsigned(7 downto 0);
user_reset : in std_logic;
-- everything below is the interface to the i2c driver
start,
stop,
read,
write,
ack_in : out std_logic;
din : out std_logic_vector(7 downto 0);
dout : in std_logic_vector(7 downto 0);
cmd_ack : in std_logic -- command done
);
end FSM;
architecture moore of FSM is
type StateType is (S1, S2, S3, S4);
signal currentState, nextState: StateType;
signal dout_save: unsigned(7 downto 0) := "00000000";
begin
transition : process(currentState, cmd_ack, dout)
begin
nextState <= currentState;
case currentState is
when S1 =>
if cmd_ack = '1' then
nextState <= S2;
end if;
when S2 =>
if cmd_ack = '1' then
nextState <= S3;
end if;
when S3 =>
if cmd_ack = '1' then
nextState <= S4;
end if;
when S4 =>
if cmd_ack = '1' then
nextState <= S1;
end if;
end case;
end process;
stateMemory : process(clk)
begin
if rising_edge(clk) then
if currentState = S4 and cmd_ack = '1' then
dout_save <= unsigned(dout);
end if;
if user_reset = '1' then
currentState <= S1;
else
currentState <= nextState;
end if;
end if;
end process;
outputs : process(currentState, dout_save)
begin
case currentState is
when S1 =>
start <= '1';
stop <= '0';
ack_in <= '0';
din <= "10010000";
write <= '1';
read <= '0';
when S2 =>
stop <= '0';
start <= '0';
ack_in <= '0';
din <= "10001100";
write <= '1';
read <= '0';
when S3 =>
start <= '1';
stop <= '0';
ack_in <= '0';
din <= "10010001";
write <= '1';
read <= '0';
when S4 =>
stop <= '1';
start <= '0';
din <= "00000000";
ack_in <= '1';
write <= '0';
read <= '1';
end case;
out_val <= dout_save;
end process;
end moore;
| agpl-3.0 | 535bf55d9e135c1710d233094e306f83 | 0.526866 | 3.021552 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/sdram.vhd | 2 | 18,231 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
--
-- design premise: banks are not interleaved; BA0,BA1 are MS address bits
--
-- TODO:
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
-- constant RESET_INTERVAL : integer := 5000; -- reset after 100us = 5.000*20n
-- constant REFRESH_INTERVAL : integer := 704;-- do a refresh every 704 cycles
constant RESET_INTERVAL : integer := 5; -- reset after 100us = 5.000*20n
constant REFRESH_INTERVAL : integer := 7;-- do a refresh every 704 cycles
subtype cmd_index is integer range 0 to 13;
constant cDSL : cmd_index := 0;
constant cNOP : cmd_index := 1;
constant cBST : cmd_index := 2;
constant cRD : cmd_index := 3;
constant cRDA : cmd_index := 4;
constant cWR : cmd_index := 5;
constant cWRA : cmd_index := 6;
constant cACT : cmd_index := 7;
constant cPRE : cmd_index := 8;
constant cPALL : cmd_index := 9;
constant cREF : cmd_index := 10;
constant cSELF : cmd_index := 11;
constant cMRS : cmd_index := 12;
constant cinv : cmd_index := 13;
type t_cmd_type is record
cmd: cmd_index;
cs: std_logic;
ras: std_logic;
cas: std_logic;
we: std_logic;
a10: std_logic;
end record;
type t_cmd_mem is array (0 to 12) of t_cmd_type;
end entity SDRAM_controller;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- real SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simple of SDRAM_controller is
constant cmd_table : t_cmd_mem := ( -- page 9
-- cmd cs ras cas we a10
(cDSL, '1','1','1','1','1'), -- DESL device deselect
(cNOP, '0','1','1','1','1'), -- NOP no operation
(cBST, '0','1','1','0','1'), -- BST burst stop
(cRD, '0','1','0','1','0'), -- RD read
(cRDA, '0','1','0','1','1'), -- RDA read with auto precharge
(cWR, '0','1','0','0','0'), -- WR write
(cWRA, '0','1','0','0','1'), -- WR write with auto precharge
(cACT, '0','0','1','1','1'), -- ACT bank activate
(cPRE, '0','0','1','0','0'), -- PRE precharge selected bank
(cPALL,'0','0','1','0','1'), -- PALL precharge all banks
(cREF, '0','0','0','1','1'), -- REF CBR auto-refresh
(cSELF,'0','0','0','1','1'), -- SELF self-refresh
(cMRS, '0','0','0','0','0') -- MRS mode register set
);
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
-- state machine
type ctrl_state is
(st_noreset, -- 0
st_in0, st_in1, st_ipre, st_in2, -- 4
st_aref1, st_1n0, st_1n1, st_1n2, st_1n3, st_1n4, st_1n5, -- 11
st_aref2, st_2n0, st_2n1, st_2n2, st_2n3, st_2n4, st_2n5, -- 18
st_aref3, st_3n0, st_3n1, st_3n2, st_3n3, st_3n4, st_3n5, -- 25
st_aref4, st_4n0, st_4n1, st_4n2, st_4n3, st_4n4, st_4n5, -- 32
st_lmr, st_ln0, st_ln1, -- 35
st_pall, st_pn0, st_pn1, -- 38
st_refr, st_rn0, st_rn1, st_rn2, st_rn3, st_rn4, st_rn5, -- 45
st_idle2, -- 46
st_act, st_an0, st_an1, -- 49
st_rdcol, st_rdn0, st_rd_done, -- 52
st_wrcol, -- 53
st_idle); -- 54
signal curr_st, next_st : ctrl_state;
signal ctrl_dbg_st, cmd_dbg : integer; -- for debugging only
signal reset_done, same_row, do_refresh, refresh_done : boolean := FALSE;
signal is_accs, is_rd, is_wr : boolean := FALSE;
signal addr : reg26;
signal row_bits, last_row : reg13;
signal col_bits : reg10;
signal rwo_bits : reg13;
signal ld_old : std_logic;
signal command : t_cmd_type;
signal doit : cmd_index;
signal wait1, wait2, waiting : std_logic;
begin -- simple
U_WAIT_ON_READS: wait_states generic map (1)
port map (rst, clk, sel, wait1);
U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
rdy <= not BOOL2SL((sel = '0') and
((wait1 = '1') or (wait2 = '1') or (waiting = '1')));
is_accs <= (sel = '0');
is_rd <= (sel = '0') and (wr = '1');
is_wr <= (sel = '0') and (wr = '0');
command <= cmd_table(doit);
scs <= command.cs;
ras <= command.ras;
cas <= command.cas;
we <= command.we;
cmd_dbg <= command.cmd; -- DEBUG only
saddr(10) <= addr(10) when command.cmd = cACT else
command.a10;
saddr(9 downto 0) <= b"1000100000" when command.cmd = cMRS else
addr(9 downto 0);
U_address: registerN generic map (26, b"00"&x"000000")
port map (clk2x, rst, sel, haddr, addr);
row_bits <= addr(23 downto 11);
col_bits <= addr(10 downto 1);
ba0 <= addr(24);
ba1 <= addr(25);
ld_old <= sel and not(BOOL2SL(same_row));
U_last_row: registerN generic map (13, '1'&x"fff")
port map (clk2x, rst, ld_old, haddr(23 downto 11), last_row);
-- same_row <= (last_row = row_bits) and (command.cmd /= cPALL);
same_row <= FALSE;
-- this state machine contols the SDRAM interface -----------------------
U_CTRL_st_reg: process(rst,clk2x)
begin
if rst = '0' then
curr_st <= st_noreset;
elsif rising_edge(clk2x) then
curr_st <= next_st;
end if;
end process U_CTRL_st_reg; ----------------------------------------------
ctrl_dbg_st <= integer(ctrl_state'pos(curr_st)); -- for debugging
U_CTRL_st_transitions: process(curr_st, reset_done, do_refresh, -------
same_row, is_accs, is_rd, is_wr)
begin
case curr_st is
-- WAIT FOR POWER-ON RESET TO COMPLETE
when st_noreset => -- 0
if reset_done then
next_st <= st_in0;
else
next_st <= st_noreset;
end if;
-- INITIALIZATION SEQUENCE
when st_in0 => -- 1 nop
next_st <= st_in1;
when st_in1 => -- 2 nop
next_st <= st_ipre;
when st_ipre => -- 3 precharge all banks
next_st <= st_in2;
when st_in2 => -- 4 nop
next_st <= st_aref1;
when st_aref1 => -- 5 auto refresh 1 + 60ns delay
next_st <= st_1n0;
when st_1n0 => -- 6 nop
next_st <= st_1n1;
when st_1n1 => -- 7 nop
next_st <= st_1n2;
when st_1n2 => -- 8 nop
next_st <= st_1n3;
when st_1n3 => -- 9 nop
next_st <= st_1n4;
when st_1n4 => -- 10 nop
next_st <= st_1n5;
when st_1n5 => -- 11 nop
next_st <= st_aref2;
when st_aref2 => -- 12 auto refresh 2 + 60ns delay
next_st <= st_2n0;
when st_2n0 => -- 13 nop
next_st <= st_2n1;
when st_2n1 => -- 14 nop
next_st <= st_2n2;
when st_2n2 => -- 15 nop
next_st <= st_2n3;
when st_2n3 => -- 16 nop
next_st <= st_2n4;
when st_2n4 => -- 17 nop
next_st <= st_2n5;
when st_2n5 => -- 18 nop
next_st <= st_aref3;
when st_aref3 => -- 19 auto refresh 3 + 60ns delay
next_st <= st_3n0;
when st_3n0 => -- 20 nop
next_st <= st_3n1;
when st_3n1 => -- 21 nop
next_st <= st_3n2;
when st_3n2 => -- 22 nop
next_st <= st_3n3;
when st_3n3 => -- 23 nop
next_st <= st_3n4;
when st_3n4 => -- 24 nop
next_st <= st_3n5;
when st_3n5 => -- 25 nop
next_st <= st_aref4;
when st_aref4 => -- 26 auto refresh 4 + 60ns delay
next_st <= st_4n0;
when st_4n0 => -- 27 nop
next_st <= st_4n1;
when st_4n1 => -- 28 nop
next_st <= st_4n2;
when st_4n2 => -- 29 nop
next_st <= st_4n3;
when st_4n3 => -- 30 nop
next_st <= st_4n4;
when st_4n4 => -- 31 nop
next_st <= st_4n5;
when st_4n5 => -- 32 nop
next_st <= st_lmr;
when st_lmr => -- 33 load mode register + 2 nops
next_st <= st_ln0;
when st_ln0 => -- 34 nop
next_st <= st_ln1;
when st_ln1 => -- 35 nop
next_st <= st_idle;
-- AUTO-REFRESH SEQUENCE
when st_pall => -- 36 precharge all banks + 2 nops
next_st <= st_pn0;
when st_pn0 => -- 37 nop
next_st <= st_pn1;
when st_pn1 => -- 38 nop
next_st <= st_refr;
when st_refr => -- 39 auto refresh + 60ns delay
next_st <= st_rn0;
when st_rn0 => -- 40 nop
next_st <= st_rn1;
when st_rn1 => -- 41 nop
next_st <= st_rn2;
when st_rn2 => -- 42 nop
next_st <= st_rn3;
when st_rn3 => -- 43 nop
next_st <= st_rn4;
when st_rn4 => -- 44 nop
next_st <= st_rn5;
when st_rn5 => -- 45 nop; sameRow was cleared
next_st <= st_idle2;
when st_idle2 => -- 46
if is_accs then -- is post-refresh access, activate row
next_st <= st_act;
else
next_st <= st_idle2;
end if;
-- ACTIVATE NEW ROW
when st_act => -- 47 activate row + 2 nops
next_st <= st_an0;
when st_an0 => -- 48 nop
next_st <= st_an1;
when st_an1 => -- 49 nop
if is_rd then
next_st <= st_rdcol; -- access is a read, set column
else
next_st <= st_wrcol; -- access is a write, set column
end if;
-- READ FROM COLUMN
when st_rdcol => -- 50 set column for RD + 2 nops
next_st <= st_rdn0;
when st_rdn0 => -- 51 nop
next_st <= st_rd_done;
when st_rd_done => -- 52 nop
if do_refresh then
next_st <= st_pall; -- go to refresh sequence
else
next_st <= st_idle; -- wait for next access to same row
end if;
-- WRITE TO COLUMN
when st_wrcol => -- 53 set column for WR
if do_refresh then
next_st <= st_pall; -- go to refresh sequence
else
next_st <= st_idle; -- wait for next access to same row
end if;
when st_idle => -- 54
if is_accs and not(same_row) then
next_st <= st_act;
elsif is_rd then
next_st <= st_rdcol;
elsif is_wr then
next_st <= st_wrcol;
else
next_st <= st_idle;
end if;
when others =>
assert false report "CTRL stateMachine broken"
& integer'image(ctrl_state'pos(curr_st)) severity failure;
end case;
end process U_CTRL_st_transitions; ---------------------------
U_CTRL_outputs: process(curr_st) ------------------------------
begin
case curr_st is
when st_rdcol =>
doit <= cRD; -- read from column
when st_wrcol =>
doit <= cWR; -- write to column
when st_ipre | st_pall =>
doit <= cPALL; -- precharge all banks
when st_aref1 | st_aref2 | st_aref3 | st_aref4 =>
doit <= cREF; -- auto-refresh
when st_lmr =>
doit <= cMRS; -- load mode register
when st_act =>
doit <= cACT; -- activate row
when others =>
doit <= cNOP;
end case;
end process U_CTRL_outputs; ----------------------------------
U_CTRL_waiting: process(curr_st) ------------------------------
begin
case curr_st is
when st_rdcol | st_rdn0 =>
waiting <= '0'; -- read from column
when st_wrcol =>
waiting <= '0'; -- write to column
when st_ipre | st_pall =>
waiting <= '0'; -- precharge all banks
when st_aref1 | st_aref2 | st_aref3 | st_aref4 =>
waiting <= '0'; -- auto-refresh
when st_lmr =>
waiting <= '0'; -- load mode register
when st_act | st_an0 | st_an1 =>
waiting <= '0'; -- activate row
when others =>
waiting <= '1';
end case;
end process U_CTRL_waiting; -----------------------------------
-- do a refresh in less than 7,8us (8192 in 64ms @ 100MHz)
U_do_refresh: process (rst, clk2x, refresh_done)
variable cnt : integer range 0 to 1023:= 0;
begin
if rst = '0' then
do_refresh <= FALSE;
cnt := 0;
elsif rising_edge(clk2x) then
if cnt > REFRESH_INTERVAL then
if refresh_done then
do_refresh <= FALSE;
cnt := 0;
else
do_refresh <= TRUE; -- add some hysteresis
if cnt = 1023 then
cnt := 0;
else
cnt := cnt + 1; -- to accomodate slow commands
end if;
end if;
else
do_refresh <= FALSE;
cnt := cnt + 1;
end if;
end if;
end process U_do_refresh;
-- do wait for 100us after reset
U_rst_100us: process(rst, clk2x)
variable cnt : integer range 0 to (8*1024 - 1):= 0;
begin
if rst = '0' then
reset_done <= FALSE;
cnt := 0;
elsif rising_edge(clk2x) then
if cnt >= RESET_INTERVAL then -- 100us elapsed
reset_done <= TRUE;
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end process U_rst_100us;
end simple;
-- ---------------------------------------------------------------------
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDRAM_controller is
begin
rdy <= '1';
hDout <= (others => 'X');
cke <= '1';
scs <= '1';
ras <= '1';
cas <= '1';
we <= '1';
dqm0 <= '1';
dqm1 <= '1';
ba0 <= '1';
ba1 <= '1';
saddr <= (others => 'X');
sdata <= (others => 'X');
end architecture fake;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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H9WgxeWFotZ7PLH43P6z0A==
`protect end_protected
| apache-2.0 | 6f065890308d34e2b784cb42cc1c06b6 | 0.939453 | 1.843906 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_spea2.vhd | 1 | 1,628 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_spea2_entity;
ARCHITECTURE hal_spea2_description OF hal_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_spea2_description; | gpl-3.0 | df10e868133e9c3b19b68beb33385d61 | 0.672604 | 3.10687 | false | false | false | false |
jdryg/tis100cpu | instruction_decoder.vhd | 1 | 2,794 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity instruction_decoder is
Port ( I_instr : in STD_LOGIC_VECTOR (31 downto 0);
O_dst : out STD_LOGIC_VECTOR (2 downto 0);
O_srcA : out STD_LOGIC_VECTOR (2 downto 0);
O_srcB : out STD_LOGIC_VECTOR (1 downto 0);
O_imm : out STD_LOGIC_VECTOR (15 downto 0);
O_aluOp: out STD_LOGIC_VECTOR (2 downto 0);
O_srcA_isPort : out STD_LOGIC;
O_dst_isPort : out STD_LOGIC;
O_enableWrite : out STD_LOGIC;
O_containsIMM : out STD_LOGIC;
O_isJmp : out STD_LOGIC;
O_jmpCondition : out STD_LOGIC_VECTOR (2 downto 0);
O_isSWP : out STD_LOGIC;
O_isLastInstr : out STD_LOGIC);
end instruction_decoder;
architecture Behavioral of instruction_decoder is
begin
decode_proc: process (I_instr) begin
O_containsIMM <= I_instr(31);
O_dst <= I_instr(25 downto 23);
O_srcA <= I_instr(22 downto 20);
O_srcB <= I_instr(19 downto 18);
O_imm <= I_instr(15 downto 0);
O_isLastInstr <= I_instr(16);
-- Default values for the rest of the signals
O_aluOp <= "000";
O_srcA_isPort <= '0';
O_dst_isPort <= '0';
O_enableWrite <= '0';
O_isJmp <= '0';
O_jmpCondition <= "111";
O_isSWP <= '0';
-- Depending on the instruction type, set the correct outputs.
if (I_instr(30 downto 29) = "00") then
-- Arithmetic instructions
O_enableWrite <= '1';
case I_instr(28 downto 26) is
when "000" => O_aluOp <= "000";
when "001" => O_aluOp <= "001";
when "010" => O_aluOp <= "010";
when others => O_aluOp <= "000";
end case;
-- Special case of SWP instruction
if(I_instr(28 downto 26) = "100") then
O_isSWP <= '1';
end if;
-- The rest of the outputs get their default value.
elsif (I_instr (30 downto 29) = "01") then
-- Port instruction
O_enableWrite <= '1';
if (I_instr(28 downto 26) = "000") then
-- ADD reg, port, reg/imm
O_srcA_isPort <= '1';
elsif (I_instr(28 downto 26) = "001") then
-- ADD port, reg, reg/imm
O_dst_isPort <= '1';
elsif (I_instr(28 downto 26) = "010") then
-- ADD port, port, reg/imm
O_srcA_isPort <= '1';
O_dst_isPort <= '1';
elsif (I_instr(28 downto 26) = "011") then
-- ISUB reg, port, reg/imm
O_srcA_isPort <= '1';
O_aluOp <= "100";
end if;
elsif (I_instr (30 downto 29) = "10") then
-- Jxx instruction
O_isJmp <= '1';
O_jmpCondition <= I_instr(28 downto 26);
O_aluOp <= "011"; -- Set Less Than
end if;
end process;
end Behavioral;
| mit | e8cb0c96a52d4db94c5076819cdd4eb5 | 0.533644 | 3.264019 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_signal.vhd | 1 | 1,482 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_signal is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
store, update, clear, clock : in std_logic;
output : out std_logic_vector((width + 1) downto 0)
);
end c_signal;
architecture behavior of c_signal is
begin
P0 : process (clock, store, update, input, clear)
variable In_latch : std_logic_Vector((width - 1) downto 0);
variable Out_latch : std_logic_Vector((width - 1) downto 0);
variable out_var : std_logic_Vector((width - 1) downto 0);
variable sig_stable : std_logic;
variable sig_quiet : std_logic;
begin
if (clock = '1' and not clock'STABLE and store = '1') then
In_latch := Input;
sig_quiet := '0';
end if;
if (clock = '1' and not clock'STABLE and update = '1') then
sig_stable := '1';
L1 : for I in width - 1 downto 0 loop
if not (In_latch(I) = Out_latch(I)) then
sig_stable := '0';
exit L1;
end if;
end loop L1;
Out_latch := In_latch;
output((width - 1) downto 0) <= Out_latch;
output(width) <= sig_stable;
output(width + 1) <= sig_quiet;
sig_quiet := '1';
end if;
if (clear = '1') then
L2 : for I in (width - 1) downto 0 loop
In_latch(I) := '0';
Out_latch(I) := '0';
end loop L2;
output((width - 1) downto 0) <= Out_latch;
output(width) <= '1';
output(width + 1) <= '1';
sig_quiet := '1';
end if;
end process P0;
end behavior; | mit | 37a39c17cc33d5865316efb81b143c09 | 0.606613 | 2.724265 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/modulo_display.vhd | 1 | 1,796 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:03:07 11/04/2014
-- Design Name:
-- Module Name: modulo_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity modulo_display is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
entrada_s : in STD_LOGIC_VECTOR (15 downto 0);
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0));
end modulo_display;
architecture Behavioral of modulo_display is
signal display_s : STD_LOGIC_VECTOR (15 downto 0);
begin
bcd2hex_p : entity work.hex2bcd
port map ( clk => clock,
sw0 => entrada_s(3 downto 0),
sw1 => entrada_s(7 downto 4),
sw2 => entrada_s(11 downto 8),
sw3 => entrada_s(15 downto 12),
bcd0 => display_s(3 downto 0),
bcd1 => display_s(7 downto 4),
bcd2 => display_s(11 downto 8),
bcd3 => display_s(15 downto 12));
display1 : entity work.disp7segx4
port map ( entrada => display_s,
clock => clock,
reset => reset,
saida_8segmentos => saida_8segmentos,
disp_sel_o => disp_sel_o );
end Behavioral;
| mit | 5f1eaca373bced84aa31361285a2260f | 0.579621 | 3.344507 | false | false | false | false |
mbgh/aes128-hdl | src/vhdl/cipherRound.vhd | 1 | 3,670 | -------------------------------------------------------------------------------
--! @file cipherRound.vhd
--! @brief AES-128 single cipher round
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-06-05
--! @platform Simulation: ModelSim; Synthesis: Synopsys, Xilinx XST/Vivado
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: cipherRound.vhd 6 2014-06-12 12:49:55Z u59323933 $
-- Revision : $Revision: 6 $
-- Local Date : $Date: 2014-06-12 14:49:55 +0200 (Thu, 12 Jun 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES-128 single cipher round
--!
--! Implements a single cipher round of the AES-128 encryption algorithm, which
--! can then be instantiated multiple times in order to create a high-throughput
--! architecture.
-------------------------------------------------------------------------------
entity cipherRound is
port (
--! @brief The internal state of AES being applied to this round.
StateIn_DI : in Matrix;
--! @brief The roundkey to be used for the current AES round.
Roundkey_DI : in std_logic_vector(127 downto 0);
--! @brief The resulting state of AES after applying this round.
StateOut_DO : out Matrix);
end entity cipherRound;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture description of a single AES round.
-------------------------------------------------------------------------------
architecture Behavioral of cipherRound is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component subMatrix is
port (
In_DI : in Matrix;
Out_DO : out Matrix);
end component subMatrix;
component mixMatrix is
port (
In_DI : in Matrix;
Out_DO : out Matrix);
end component mixMatrix;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal SubMatrixOut_D : Matrix; -- State after "SubMatrix".
signal ShiftRowsOut_D : Matrix; -- State after "ShiftRows".
signal MixMatrixOut_D : Matrix; -- State after "MixColumns".
begin -- architecture Behavioral
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
subMatrix_1 : subMatrix
port map (
In_DI => StateIn_DI,
Out_DO => SubMatrixOut_D);
mixMatrix_1 : entity work.mixMatrix
port map (
In_DI => ShiftRowsOut_D,
Out_DO => MixMatrixOut_D);
ShiftRowsOut_D <= shift_rows(SubMatrixOut_D);
StateOut_DO <= MixMatrixOut_D xor Roundkey_DI;
end architecture Behavioral;
| gpl-2.0 | 2d15258c47d1d3f7b1e50fea461a3b08 | 0.465123 | 5 | false | false | false | false |
jdryg/tis100cpu | next_pc.vhd | 1 | 2,789 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity next_pc is
Port ( I_srcA_isPort : in STD_LOGIC;
I_dst_isPort : in STD_LOGIC;
I_pr_isDataOutValid : in STD_LOGIC;
I_pw_isDataOutValid : in STD_LOGIC;
I_regB_data : in STD_LOGIC_VECTOR (15 downto 0);
I_imm : in STD_LOGIC_VECTOR (15 downto 0);
I_containsIMM : in STD_LOGIC;
I_isJump : in STD_LOGIC;
I_jmpCondition : in STD_LOGIC_VECTOR (2 downto 0);
I_isZero : in STD_LOGIC;
I_isLessThan : in STD_LOGIC;
I_PC : in STD_LOGIC_VECTOR (5 downto 0);
O_NewPC : out STD_LOGIC_VECTOR (5 downto 0));
end next_pc;
architecture Behavioral of next_pc is
signal isReadPortReady, isWritePortReady: STD_LOGIC;
signal jmpDelta: STD_LOGIC_VECTOR (5 downto 0);
signal takeJump: STD_LOGIC;
begin
srcPortProc: process (I_srcA_isPort, I_pr_isDataOutValid) begin
isReadPortReady <= (NOT I_srcA_isPort) OR (I_srcA_isPort AND I_pr_isDataOutValid);
end process;
dstPortProc: process (I_dst_isPort, I_pw_isDataOutValid) begin
isWritePortReady <= (NOT I_dst_isPort) OR (I_dst_isPort AND I_pw_isDataOutValid);
end process;
jmpDeltaProc: process (I_regB_data, I_imm, I_containsIMM) begin
if(I_containsIMM = '1') then
jmpDelta <= I_imm(5 downto 0);
else
jmpDelta <= I_regB_data(5 downto 0);
end if;
end process;
takeJumpProc: process (I_jmpCondition, I_isZero, I_isLessThan) begin
case I_jmpCondition is
when "000" => takeJump <= '1'; -- Unconditional jump
when "001" => takeJump <= NOT ((I_isZero AND '1') OR (I_isLessThan AND '1')); -- JGZ
when "010" => takeJump <= (I_isZero AND '0') OR (I_isLessThan AND '1'); -- JLZ
when "011" => takeJump <= (I_isZero AND '1') OR (I_isLessThan AND '0'); -- JEZ
when "100" => takeJump <= NOT (I_isZero AND '1') OR (I_isLessThan AND '0'); -- JNZ
when others => takeJump <= '0'; -- Unknown jump condition
end case;
end process;
newPCProc: process (I_PC, takeJump, jmpDelta, isWritePortReady, isReadPortReady) begin
-- If this is a port instruction, wait until the port is ready.
if(isReadPortReady = '0' OR isWritePortReady = '0') then
O_NewPC <= I_PC;
else
-- Otherwise, if it's not a jump or the jump condition is false, move on to the next instruction.
if(I_isJump = '0' OR takeJump = '0') then
O_NewPC <= I_PC + 1;
else
-- Finally, this is a jump instruction and the condition is true. Jump!
O_NewPC <= I_PC + jmpDelta; -- This is a signed add.
end if;
end if;
end process;
end Behavioral;
| mit | 5bb92a0c68c4d60287e9a7f1202f04ac | 0.61384 | 3.194731 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC/lpm_counter0.vhd | 1 | 5,137 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
updown : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
updown : IN STD_LOGIC
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UNUSED",
lpm_modulus => 10,
lpm_port_updown => "PORT_USED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
clk_en => clk_en,
clock => clock,
updown => updown,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "2"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "10"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_USED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL clk_en
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: updown 0 0 0 0 INPUT NODEFVAL updown
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: @updown 0 0 0 0 updown 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | 71caf6587cbaba2407b03caf8343de26 | 0.636558 | 3.530584 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_adder_bit.vhd | 15 | 11,636 | -------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder_bit.vhd
--
-- Description: Implements 1 bit of the pf_adder
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2001-09-25
-- - Added generic to allow selection of a registered output
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - CHanged the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed call out proc_common to v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
Use proc_common_v4_0.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean := true
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic; -- A operand
Bin : in std_logic; -- B operand
Add_sub_n : in std_logic; -- Function ('1' = add, '0' = A - B)
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_adder_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal lutout_AddSub : std_logic;
signal addsub_result : std_logic;
signal addsub_result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"0069"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lutout_AddSub,
--- xst wrk around I0 => Bin,
--- xst wrk around I1 => Ain,
--- xst wrk around I2 => Add_sub_n,
--- xst wrk around I3 => '0');
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"0069"
)
port map (
O => lutout_AddSub,
I0 => Bin,
I1 => Ain,
I2 => Add_sub_n,
I3 => '0');
MUXCY_I : MUXCY
port map (
DI => Ain,
CI => Carry_In,
S => lutout_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => lutout_AddSub,
CI => Carry_In,
O => addsub_result);
FDRE_I: FDRE
port map (
Q => addsub_result_Reg,
C => Clk,
CE => Clock_Enable,
D => addsub_result,
R => Rst
);
USE_REGISTERED_RESULT : if (C_REGISTERED_RESULT = true) generate
Result <= addsub_result_Reg; -- registered version
end generate USE_REGISTERED_RESULT;
USE_COMBINATIONAL_RESULT : if (C_REGISTERED_RESULT = false) generate
Result <= addsub_result; -- combinational version
end generate USE_COMBINATIONAL_RESULT;
end implementation;
| apache-2.0 | fd907216b0a3951f0aff628c24d1eeaa | 0.412427 | 4.953597 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/asap-alap-random/hal_asap.vhd | 1 | 1,831 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:57:10)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_asap_entity;
ARCHITECTURE hal_asap_description OF hal_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
WHEN "00000010" =>
IF (register1 < 6) THEN
output1 <= register1;
ELSE
output1 <= "0000000000000000000000000000110";
END IF;
register1 := register2 * register3;
register2 := register4 * 8;
output2 <= register5 + 9;
WHEN "00000011" =>
register1 := register1 - 11;
WHEN "00000100" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_asap_description; | gpl-3.0 | 981a25e8814180c05aabec4776b61854 | 0.691972 | 3.293165 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/seven_segment_display_driver.vhd | 1 | 2,366 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayDriver is
Port (entrada: in STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output8: out STD_LOGIC_VECTOR (7 downto 0));
end SevenSegmentDisplayDriver;
architecture Behavioral of SevenSegmentDisplayDriver is
type STD_HEX_VECTOR_BASE is array (0 to 15) of STD_LOGIC_VECTOR (0 to 7);
constant base : STD_HEX_VECTOR_BASE := (("00000011"),
("10011111"),
("00100101"),
("00001101"),
("10011001"),
("01001001"),
("01000001"),
("00011111"),
("00000001"),
("00001001"),
("11111101"),
("11000001"),
("01100011"),
("10000101"),
("01100001"),
("01110001"));
begin
process (clock, reset)
begin
if reset = '1' then
output8 <= "11111111";
elsif clock'event and clock = '1' then
case entrada is
when "0000" => output8 <= base(0);
when "0001" => output8 <= base(1);
when "0010" => output8 <= base(2);
when "0011" => output8 <= base(3);
when "0100" => output8 <= base(4);
when "0101" => output8 <= base(5);
when "0110" => output8 <= base(6);
when "0111" => output8 <= base(7);
when "1000" => output8 <= base(8);
when "1001" => output8 <= base(9);
when "1010" => output8 <= base(10);
when "1011" => output8 <= base(11);
when "1100" => output8 <= base(12);
when "1101" => output8 <= base(13);
when "1110" => output8 <= base(14);
when "1111" => output8 <= base(15);
when others => output8 <= "11111110"; -- dot only
end case;
end if;
end process;
end Behavioral;
| mit | 5a9a5f6c663cca4a869fcb05c1fcbe62 | 0.404903 | 4.918919 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/muxf_struct_f.vhd | 15 | 15,871 | -------------------------------------------------------------------------------
-- $Id: muxf_struct_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: muxf_struct_f.vhd
--
-- Description: Given a vector of input bits, Iv (not necessarily a
-- power of two). and a select value, Sel, this block
-- will build the multiplexing function
--
-- O <= Iv(Sel)
--
-- using the MUXF (MUXF5, MUXF6, etc.) primitives of
-- the target FPGA family, C_FAMILY, if possible and,
-- otherwise, using inferred multiplexers.
--
-- Since MUXF primitives are targeted, it is proper
-- that the Iv signals are driven by LUTs.
--
-- A help entity, muxf_struct, which is instantiated
-- recursively, is used to facilitate the implementation.
-- (So, compiling this file will add two entities,
-- muxf_struct and muxf_struct_f, to the target library.)
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- muxf_struct_f.vhd
-- muxf_struct (entity and architecture in this file)
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
--------------------------------------------------------------------------------
-- This is a helper entity. The entity declaration for muxf_struct_f is
-- further, below.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.family_support.all; -- supported, primitives_type
library unisim;
entity muxf_struct is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_NI_PO2E : positive; -- Num Inputs, Power-of-2 Envelope
C_FAMILY : string
);
port (
LO : out std_logic; -- Normally only one of
O : out std_logic; -- LO or O would be used.
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NI_PO2E)-1)
);
end entity muxf_struct;
library proc_common_v4_0;
library unisim;
use unisim.all; -- Makes unisim entities available for default binding.
--------------------------------------------------------------------------------
-- Line-length guideline purposely not followed in some places to expose parallel code structures.
--------------------------------------------------------------------------------
architecture imp of muxf_struct is
--
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
constant SIZE : natural := Iv'length;
constant PO2E : natural := C_NI_PO2E;
constant THIS_LEVEL : natural := C_START_LEVEL + clog2(PO2E);
constant K_FAMILY : families_type := str2fam(C_FAMILY);
constant S5 : boolean := supported(K_FAMILY, u_MUXF5_D) and THIS_LEVEL = 5;
constant S6 : boolean := supported(K_FAMILY, u_MUXF6_D) and THIS_LEVEL = 6;
constant S7 : boolean := supported(K_FAMILY, u_MUXF7_D) and THIS_LEVEL = 7;
constant S8 : boolean := supported(K_FAMILY, u_MUXF8_D) and THIS_LEVEL = 8;
constant INFERRED : boolean := not(S5 or S6 or S7 or S8);
--
signal s, i0, i1 : std_logic; -- If there is no i1 at a particular mux level,
-- it is left undriven and s is tied to '0'.
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF6_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF7_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF8_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Below, some generates and component instantiations are one per line
-- to show similarities and differences.
----------------------------------------------------------------------------
-- Base instance, just one or two inputs, no recursion.
----------------------------------------------------------------------------
E2_GEN : if PO2E=2 and SIZE=2 generate s <= Sel(0); i0 <= Iv(0); i1 <= Iv(1); end generate;
E1_GEN : if PO2E=2 and SIZE=1 generate s <= '0'; i0 <= Iv(0); end generate;-- No driver for i1
----------------------------------------------------------------------------
-- Use recursion to get lower-level mux structures to feed the mux at
-- this level.
----------------------------------------------------------------------------
GT2_GEN : if PO2E > 2 generate
constant NE : natural := PO2E/2; -- Next envelope.
constant BOTH : boolean := (SIZE > NE); -- Needs recursive call for
-- both the left and right sides; otherwise just a left-side
-- recursive call is needed (with C_NI_PO2E reduced by half) and Iv
-- passed down unchanged.
constant LSIZE : natural := bo2na(BOTH) * (2**(clog2(SIZE))/2)
+ bo2na(not BOTH) * SIZE;
-- 1st option above: LSIZE is next smaller power of 2
-- 2nd option above: SIZE is passed down unchanged
begin
LEFT_GEN : IF true generate
I_I0 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i0,
O => open,
Iv => Iv(0 to LSIZE-1),
Sel => Sel(1 to Sel'right)
)
;
end generate;
RIGHT_GEN : IF BOTH generate
I_I1 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => SIZE-LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i1,
O => open,
Iv => Iv(LSIZE to SIZE-1),
Sel => Sel(1 to Sel'right)
)
;
s <= Sel(0);
end generate;
LEFT_ONLY_GEN : IF not BOTH generate
s <= '0';
end generate;
end generate;
-- Instantiate the mux at this level.
--
-- Structurals
S5_GEN : if S5 generate I_F5 : component MUXF5_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S6_GEN : if S6 generate I_F6 : component MUXF6_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S7_GEN : if S7 generate I_F7 : component MUXF7_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S8_GEN : if S8 generate I_F8 : component MUXF8_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
-- Inferred
INFERRED_GEN : if INFERRED generate
signal h : std_logic;
begin
h <= i0 when s = '0' else i1 ;
LO <= h;
O <= h;
END generate;
end architecture imp;
---)
---(
--------------------------------------------------------------------------------
-- Generic descriptions
--------------------------------------------------------------------------------
-- C_START_LEVEL : natural - The size of the LUTs feeding into MUXFN network.
-- For example, for six-input LUTs,
-- C__START_LEVEL = 6 and the first level of muxes
-- are MUXF7.
-- C_NUM_INPUTS : positive - The number of inputs to be muxed.
-- C_FAMILY : string - The target FPGA family.
--------------------------------------------------------------------------------
-- Port descriptions
--------------------------------------------------------------------------------
-- O : out std_logic - Mux ouput
-- Iv : in std_logic_vector(0 to C_NUM_INPUTS-1) - Mux inputs
-- Sel: in std_logic_vector(0 to log2(C_NUM_INPUTS) - 1) - Select lines.
-- - The Iv values must be ordered such that the correct
-- - one is selected according to O <= Iv(Sel).
--------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
entity muxf_struct_f is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_FAMILY : string
);
port (
O : out std_logic;
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NUM_INPUTS) - 1)
);
end muxf_struct_f;
architecture imp of muxf_struct_f is
begin
MUXF_STRUCT_I : entity proc_common_v4_0.muxf_struct
generic map (
C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => C_NUM_INPUTS,
C_NI_PO2E => 2**clog2(C_NUM_INPUTS),
C_FAMILY => C_FAMILY
)
port map (
LO => open,
O => O,
Iv => Iv,
Sel => Sel
);
end imp;
---)
| apache-2.0 | 95c00bcbe32af65b1dca94fa4094a066 | 0.441182 | 4.590975 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/alu_bit.vhd | 1 | 31,681 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 237c0f6692dd1a864a939ef78ee603c1 | 0.947129 | 1.844492 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_adder.vhd | 15 | 10,246 | -------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
component pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic;
Bin : in std_logic;
Add_sub_n : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end component pf_adder_bit;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
--
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
-- carry_active_high <= alu_cy(0) xor not(Add_sub_n);
--
--
--
-- I_CARRY_OUT: FDRE
-- port map (
-- Q => Carry_Out, -- [out]
-- C => Clk, -- [in]
-- CE => count_clock_en, -- [in]
-- D => carry_active_high, -- [in]
-- R => Rst -- [in]
-- );
result_out <= iresult_out;
end architecture implementation;
| apache-2.0 | f49be86568514dfb556aa660043cf5e0 | 0.39147 | 5.047291 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/asap-alap-random/fir2_alap.vhd | 1 | 3,045 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:43:48)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_alap_entity;
ARCHITECTURE fir2_alap_description OF fir2_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
register3 := not input3 or input3;
register4 := not input4 or input4;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := not input5 or input5;
register4 := not input6 or input6;
WHEN "00000011" =>
register1 := register1 * 8;
register2 := register2 * 10;
register3 := register4 + register3;
register4 := not input7 or input7;
register5 := not input8 or input8;
WHEN "00000100" =>
register1 := register2 + register1;
register2 := register3 * 14;
register3 := register5 + register4;
register4 := not input9 or input9;
register5 := not input10 or input10;
WHEN "00000101" =>
register1 := register2 + register1;
register2 := register3 * 18;
register3 := register5 + register4;
register4 := not input11 or input11;
register5 := not input12 or input12;
WHEN "00000110" =>
register1 := register2 + register1;
register2 := register3 * 22;
register3 := register5 + register4;
register4 := not input13 or input13;
register5 := not input14 or input14;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register3 * 26;
register3 := register5 + register4;
register4 := not input15 or input15;
register5 := not input16 or input16;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := register3 * 30;
register3 := register5 + register4;
WHEN "00001001" =>
register1 := register2 + register1;
register2 := register3 * 32;
WHEN "00001010" =>
register1 := register2 + register1;
WHEN "00001011" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_alap_description; | gpl-3.0 | 5f15035014a6d585fd4e4122b33297b1 | 0.670608 | 3.181818 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_decryption_monte_carlo_testbench_128bits.vhd | 1 | 11,319 | -- Twofish_ecb_decryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_decryption_monte_carlo_testbench128 is
end ecb_decryption_monte_carlo_testbench128;
architecture ecb_decryption128_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round128
port (
in1_tdr128,
in2_tdr128,
in3_tdr128,
in4_tdr128,
in_Sfirst_tdr128,
in_Ssecond_tdr128,
in_key_up_tdr128,
in_key_down_tdr128 : in std_logic_vector(31 downto 0);
out1_tdr128,
out2_tdr128,
out3_tdr128,
out4_tdr128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_decryption_circuit: twofish_decryption_round128
port map (
in1_tdr128 => to_round(127 downto 96),
in2_tdr128 => to_round(95 downto 64),
in3_tdr128 => to_round(63 downto 32),
in4_tdr128 => to_round(31 downto 0),
in_Sfirst_tdr128 => Sfirst,
in_Ssecond_tdr128 => Ssecond,
in_key_up_tdr128 => key_up,
in_key_down_tdr128 => key_down,
out1_tdr128 => to_encr_reg128(127 downto 96),
out2_tdr128 => to_encr_reg128(95 downto 64),
out3_tdr128 => to_encr_reg128(63 downto 32),
out4_tdr128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_decryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_decryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_decryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Decryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process ecb_dmc_proc;
end ecb_decryption128_monte_carlo_testbench_arch;
| gpl-2.0 | ab73b3d901a5f6779803db421d4e19db | 0.652796 | 2.739351 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd | 1 | 12,949 | -------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end lmb_bram_elaborate;
architecture STRUCTURE of lmb_bram_elaborate is
component RAMB36 is
generic (
WRITE_MODE_A : string;
WRITE_MODE_B : string;
INIT_FILE : string;
READ_WIDTH_A : integer;
READ_WIDTH_B : integer;
WRITE_WIDTH_A : integer;
WRITE_WIDTH_B : integer;
RAM_EXTENSION_A : string;
RAM_EXTENSION_B : string
);
port (
ADDRA : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_logic;
CASCADEINREGA : in std_logic;
CASCADEOUTLATA : out std_logic;
CASCADEOUTREGA : out std_logic;
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATB : in std_logic;
CASCADEINREGB : in std_logic;
CASCADEOUTLATB : out std_logic;
CASCADEOUTREGB : out std_logic;
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 2);
signal pgassign3 : std_logic_vector(0 to 23);
signal pgassign4 : std_logic_vector(15 downto 0);
signal pgassign5 : std_logic_vector(31 downto 0);
signal pgassign6 : std_logic_vector(31 downto 0);
signal pgassign7 : std_logic_vector(3 downto 0);
signal pgassign8 : std_logic_vector(15 downto 0);
signal pgassign9 : std_logic_vector(31 downto 0);
signal pgassign10 : std_logic_vector(31 downto 0);
signal pgassign11 : std_logic_vector(3 downto 0);
signal pgassign12 : std_logic_vector(15 downto 0);
signal pgassign13 : std_logic_vector(31 downto 0);
signal pgassign14 : std_logic_vector(31 downto 0);
signal pgassign15 : std_logic_vector(3 downto 0);
signal pgassign16 : std_logic_vector(15 downto 0);
signal pgassign17 : std_logic_vector(31 downto 0);
signal pgassign18 : std_logic_vector(31 downto 0);
signal pgassign19 : std_logic_vector(3 downto 0);
signal pgassign20 : std_logic_vector(15 downto 0);
signal pgassign21 : std_logic_vector(31 downto 0);
signal pgassign22 : std_logic_vector(31 downto 0);
signal pgassign23 : std_logic_vector(3 downto 0);
signal pgassign24 : std_logic_vector(15 downto 0);
signal pgassign25 : std_logic_vector(31 downto 0);
signal pgassign26 : std_logic_vector(31 downto 0);
signal pgassign27 : std_logic_vector(3 downto 0);
signal pgassign28 : std_logic_vector(15 downto 0);
signal pgassign29 : std_logic_vector(31 downto 0);
signal pgassign30 : std_logic_vector(31 downto 0);
signal pgassign31 : std_logic_vector(3 downto 0);
signal pgassign32 : std_logic_vector(15 downto 0);
signal pgassign33 : std_logic_vector(31 downto 0);
signal pgassign34 : std_logic_vector(31 downto 0);
signal pgassign35 : std_logic_vector(3 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"1";
pgassign2(0 to 2) <= B"000";
pgassign3(0 to 23) <= B"000000000000000000000000";
pgassign4(15 downto 15) <= B"1";
pgassign4(14 downto 3) <= BRAM_Addr_A(18 to 29);
pgassign4(2 downto 0) <= B"000";
pgassign5(31 downto 8) <= B"000000000000000000000000";
pgassign5(7 downto 0) <= BRAM_Dout_A(0 to 7);
BRAM_Din_A(0 to 7) <= pgassign6(7 downto 0);
pgassign7(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign7(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign7(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign7(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign8(15 downto 15) <= B"1";
pgassign8(14 downto 3) <= BRAM_Addr_B(18 to 29);
pgassign8(2 downto 0) <= B"000";
pgassign9(31 downto 8) <= B"000000000000000000000000";
pgassign9(7 downto 0) <= BRAM_Dout_B(0 to 7);
BRAM_Din_B(0 to 7) <= pgassign10(7 downto 0);
pgassign11(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign11(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign11(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign11(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign12(15 downto 15) <= B"1";
pgassign12(14 downto 3) <= BRAM_Addr_A(18 to 29);
pgassign12(2 downto 0) <= B"000";
pgassign13(31 downto 8) <= B"000000000000000000000000";
pgassign13(7 downto 0) <= BRAM_Dout_A(8 to 15);
BRAM_Din_A(8 to 15) <= pgassign14(7 downto 0);
pgassign15(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign15(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign15(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign15(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign16(15 downto 15) <= B"1";
pgassign16(14 downto 3) <= BRAM_Addr_B(18 to 29);
pgassign16(2 downto 0) <= B"000";
pgassign17(31 downto 8) <= B"000000000000000000000000";
pgassign17(7 downto 0) <= BRAM_Dout_B(8 to 15);
BRAM_Din_B(8 to 15) <= pgassign18(7 downto 0);
pgassign19(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign19(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign19(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign19(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign20(15 downto 15) <= B"1";
pgassign20(14 downto 3) <= BRAM_Addr_A(18 to 29);
pgassign20(2 downto 0) <= B"000";
pgassign21(31 downto 8) <= B"000000000000000000000000";
pgassign21(7 downto 0) <= BRAM_Dout_A(16 to 23);
BRAM_Din_A(16 to 23) <= pgassign22(7 downto 0);
pgassign23(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign23(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign23(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign23(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign24(15 downto 15) <= B"1";
pgassign24(14 downto 3) <= BRAM_Addr_B(18 to 29);
pgassign24(2 downto 0) <= B"000";
pgassign25(31 downto 8) <= B"000000000000000000000000";
pgassign25(7 downto 0) <= BRAM_Dout_B(16 to 23);
BRAM_Din_B(16 to 23) <= pgassign26(7 downto 0);
pgassign27(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign27(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign27(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign27(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign28(15 downto 15) <= B"1";
pgassign28(14 downto 3) <= BRAM_Addr_A(18 to 29);
pgassign28(2 downto 0) <= B"000";
pgassign29(31 downto 8) <= B"000000000000000000000000";
pgassign29(7 downto 0) <= BRAM_Dout_A(24 to 31);
BRAM_Din_A(24 to 31) <= pgassign30(7 downto 0);
pgassign31(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign31(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign31(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign31(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign32(15 downto 15) <= B"1";
pgassign32(14 downto 3) <= BRAM_Addr_B(18 to 29);
pgassign32(2 downto 0) <= B"000";
pgassign33(31 downto 8) <= B"000000000000000000000000";
pgassign33(7 downto 0) <= BRAM_Dout_B(24 to 31);
BRAM_Din_B(24 to 31) <= pgassign34(7 downto 0);
pgassign35(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign35(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign35(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign35(0 downto 0) <= BRAM_WEN_B(3 to 3);
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb36_0 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_0.mem",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign4,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => pgassign5,
DIPA => net_gnd4,
DOA => pgassign6,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => pgassign7,
ADDRB => pgassign8,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => pgassign9,
DIPB => net_gnd4,
DOB => pgassign10,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => pgassign11
);
ramb36_1 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_1.mem",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign12,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => pgassign13,
DIPA => net_gnd4,
DOA => pgassign14,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => pgassign15,
ADDRB => pgassign16,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => pgassign17,
DIPB => net_gnd4,
DOB => pgassign18,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => pgassign19
);
ramb36_2 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_2.mem",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign20,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => pgassign21,
DIPA => net_gnd4,
DOA => pgassign22,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => pgassign23,
ADDRB => pgassign24,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => pgassign25,
DIPB => net_gnd4,
DOB => pgassign26,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => pgassign27
);
ramb36_3 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_3.mem",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign28,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => pgassign29,
DIPA => net_gnd4,
DOA => pgassign30,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => pgassign31,
ADDRB => pgassign32,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => pgassign33,
DIPB => net_gnd4,
DOB => pgassign34,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => pgassign35
);
end architecture STRUCTURE;
| lgpl-3.0 | fbedc0ebe15646a02bbb26b70f3e3d46 | 0.599815 | 3.213151 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00592.vhd | 1 | 42,845 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00592
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (15)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00592)
-- ENT00592_Test_Bench(ARCH00592_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00592 of E00000 is
begin
process
procedure p1 is
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
alias av_boolean_1 : a_boolean
is va_boolean_1 ;
alias av_bit_1 : a_bit
is va_bit_1 ;
alias av_severity_level_1 : a_severity_level
is va_severity_level_1 ;
alias av_character_1 : a_character
is va_character_1 ;
alias av_t_enum1_1 : a_t_enum1
is va_t_enum1_1 ;
alias av_st_enum1_1 : a_st_enum1
is va_st_enum1_1 ;
alias av_integer_1 : a_integer
is va_integer_1 ;
alias av_t_int1_1 : a_t_int1
is va_t_int1_1 ;
alias av_st_int1_1 : a_st_int1
is va_st_int1_1 ;
alias av_time_1 : a_time
is va_time_1 ;
alias av_t_phys1_1 : a_t_phys1
is va_t_phys1_1 ;
alias av_st_phys1_1 : a_st_phys1
is va_st_phys1_1 ;
alias av_real_1 : a_real
is va_real_1 ;
alias av_t_real1_1 : a_t_real1
is va_t_real1_1 ;
alias av_st_real1_1 : a_st_real1
is va_st_real1_1 ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
alias av_bit_vector_1 : a_bit_vector
is va_bit_vector_1 ;
alias av_string_1 : a_string
is va_string_1 ;
alias av_t_rec1_1 : a_t_rec1
is va_t_rec1_1 ;
alias av_st_rec1_1 : a_st_rec1
is va_st_rec1_1 ;
alias av_t_rec2_1 : a_t_rec2
is va_t_rec2_1 ;
alias av_st_rec2_1 : a_st_rec2
is va_st_rec2_1 ;
alias av_t_rec3_1 : a_t_rec3
is va_t_rec3_1 ;
alias av_st_rec3_1 : a_st_rec3
is va_st_rec3_1 ;
alias av_t_arr1_1 : a_t_arr1
is va_t_arr1_1 ;
alias av_st_arr1_1 : a_st_arr1
is va_st_arr1_1 ;
alias av_t_arr2_1 : a_t_arr2
is va_t_arr2_1 ;
alias av_st_arr2_1 : a_st_arr2
is va_st_arr2_1 ;
alias av_t_arr3_1 : a_t_arr3
is va_t_arr3_1 ;
alias av_st_arr3_1 : a_st_arr3
is va_st_arr3_1 ;
begin
-- test that variables denote same object
av_boolean_1 := new boolean'(c_boolean_1) ;
av_bit_1 := new bit'(c_bit_1) ;
av_severity_level_1 := new severity_level'(c_severity_level_1) ;
av_character_1 := new character'(c_character_1) ;
av_t_enum1_1 := new t_enum1'(c_t_enum1_1) ;
av_st_enum1_1 := new st_enum1'(c_st_enum1_1) ;
av_integer_1 := new integer'(c_integer_1) ;
av_t_int1_1 := new t_int1'(c_t_int1_1) ;
av_st_int1_1 := new st_int1'(c_st_int1_1) ;
av_time_1 := new time'(c_time_1) ;
av_t_phys1_1 := new t_phys1'(c_t_phys1_1) ;
av_st_phys1_1 := new st_phys1'(c_st_phys1_1) ;
av_real_1 := new real'(c_real_1) ;
av_t_real1_1 := new t_real1'(c_t_real1_1) ;
av_st_real1_1 := new st_real1'(c_st_real1_1) ;
correct := correct and av_boolean_1.all
= c_boolean_1 ;
correct := correct and av_bit_1.all
= c_bit_1 ;
correct := correct and av_severity_level_1.all
= c_severity_level_1 ;
correct := correct and av_character_1.all
= c_character_1 ;
correct := correct and av_t_enum1_1.all
= c_t_enum1_1 ;
correct := correct and av_st_enum1_1.all
= c_st_enum1_1 ;
correct := correct and av_integer_1.all
= c_integer_1 ;
correct := correct and av_t_int1_1.all
= c_t_int1_1 ;
correct := correct and av_st_int1_1.all
= c_st_int1_1 ;
correct := correct and av_time_1.all
= c_time_1 ;
correct := correct and av_t_phys1_1.all
= c_t_phys1_1 ;
correct := correct and av_st_phys1_1.all
= c_st_phys1_1 ;
correct := correct and av_real_1.all
= c_real_1 ;
correct := correct and av_t_real1_1.all
= c_t_real1_1 ;
correct := correct and av_st_real1_1.all
= c_st_real1_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00592" ,
"Variable declarations - all access subtypes" ,
correct) ;
end p1 ;
--
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
variable correct : boolean := true ;
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
alias av_bit_vector_1 : a_bit_vector
is va_bit_vector_1 ;
alias av_string_1 : a_string
is va_string_1 ;
alias av_t_rec1_1 : a_t_rec1
is va_t_rec1_1 ;
alias av_st_rec1_1 : a_st_rec1
is va_st_rec1_1 ;
alias av_t_rec2_1 : a_t_rec2
is va_t_rec2_1 ;
alias av_st_rec2_1 : a_st_rec2
is va_st_rec2_1 ;
alias av_t_rec3_1 : a_t_rec3
is va_t_rec3_1 ;
alias av_st_rec3_1 : a_st_rec3
is va_st_rec3_1 ;
alias av_t_arr1_1 : a_t_arr1
is va_t_arr1_1 ;
alias av_st_arr1_1 : a_st_arr1
is va_st_arr1_1 ;
alias av_t_arr2_1 : a_t_arr2
is va_t_arr2_1 ;
alias av_st_arr2_1 : a_st_arr2
is va_st_arr2_1 ;
alias av_t_arr3_1 : a_t_arr3
is va_t_arr3_1 ;
alias av_st_arr3_1 : a_st_arr3
is va_st_arr3_1 ;
begin
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00592" ,
"Alias declarations - composite dynamic access subtypes" ,
correct) ;
end p2 ;
begin
p1 ;
p2 ;
wait ;
end process ;
end ARCH00592 ;
--
entity ENT00592_Test_Bench is
end ENT00592_Test_Bench ;
--
architecture ARCH00592_Test_Bench of ENT00592_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00592 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00592_Test_Bench ;
| gpl-3.0 | c83523fe368bfbf019ea294fc63b76f3 | 0.52879 | 2.961568 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/indices_if_ap_fifo.vhd | 3 | 2,805 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of indices_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | 434fa1fde473aed1074f936a7be455d7 | 0.494474 | 3.68594 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/r2p_pre.vhd | 1 | 1,620 | --
-- r2p_pre.vhd
--
-- Cordic pre-processing block
--
--
-- step 1: determine quadrant and generate absolute value of X and Y
-- Q1: Xnegative
-- Q2: Ynegative
--
-- step 2: swap X and Y values if Y>X
-- Q3: swapped (Y > X)
--
-- Rev. 1.1 June 4th, 2001. Richard Herveille. Revised entire core.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity r2p_pre is
port(
clk : in std_logic;
ena : in std_logic;
Xi : in signed(15 downto 0);
Yi : in signed(15 downto 0);
Xo : out unsigned(14 downto 0);
Yo : out unsigned(14 downto 0);
Q : out std_logic_vector(2 downto 0));
end entity r2p_pre;
architecture dataflow of r2p_pre is
signal Xint1, Yint1 : unsigned(14 downto 0);
signal Xneg, Yneg, swap : std_logic;
begin
--
-- step 1: Determine absolute value of X and Y, set Xneg and Yneg
-- Loose the sign-bit.
Step1: process(clk, Xi, Yi)
begin
if (clk'event and clk = '1') then
if (ena = '1') then
Xint1 <= conv_unsigned(abs(Xi), 15);
Xneg <= Xi(Xi'left);
Yint1 <= conv_unsigned(abs(Yi), 15);
Yneg <= Yi(Yi'left);
end if;
end if;
end process Step1;
--
-- step 2: Swap X and Y if Y>X
--
Step2: process(clk, Xint1, Yint1)
variable Xint2, Yint2 : unsigned(14 downto 0);
begin
if (Yint1 > Xint1) then
swap <= '1';
Xint2 := Yint1;
Yint2 := Xint1;
else
swap <= '0';
Xint2 := Xint1;
Yint2 := Yint1;
end if;
if(clk'event and clk = '1') then
if (ena = '1') then
Xo <= Xint2;
Yo <= Yint2;
Q <= (Yneg, Xneg, swap);
end if;
end if;
end process Step2;
end architecture dataflow;
| apache-2.0 | 2827c04a8b30957bc4507629b29f46d6 | 0.609877 | 2.473282 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00257.vhd | 1 | 3,029 | -- NEED RESULT: Passive concurrent procedure call in interface shared among architectures
-- NEED RESULT: ENT00257: Passive process statement in interface shared amongarchitectures
-- NEED RESULT: Passive concurrent procedure call in interface shared among architectures
-- NEED RESULT: ENT00257: Passive process statement in interface shared amongarchitectures
-- NEED RESULT: *** Examine log file to verify that the followingtwo messages appear twice:
-- NEED RESULT: Passive concurrent procedure call in interface sharedamong architectures
-- NEED RESULT: Passive process statement in interface shared amongarchitectures
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00257
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.3 (1)
-- 1.1.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00257(ARCH00257)
-- ENT00257(ARCH00257_1)
-- ENT00257_Test_Bench(ARCH00257_Test_Bench)
--
-- REVISION HISTORY:
--
-- 16-JUL-1987 - initial revision
--
-- NOTES:
--
-- simulation log file needs to be checked for result of assertion
--
use WORK.STANDARD_TYPES.all ;
entity ENT00257 is
port ( s : out boolean ) ;
procedure proc is
begin
assert false
report "Passive concurrent procedure call in interface shared" &
" among architectures"
severity note ;
end proc ;
begin
P1 : proc ;
P2 :
process
begin
assert false
report "ENT00257: Passive process statement in interface shared among" &
"architectures"
severity note ;
wait ;
end process P2 ;
end ENT00257 ;
architecture ARCH00257 of ENT00257 is
begin
A1 : s <= true ;
end ARCH00257 ;
architecture ARCH00257_1 of ENT00257 is
begin
A1 : s <= false ;
end ARCH00257_1 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00257_Test_Bench is
end ENT00257_Test_Bench ;
architecture ARCH00257_Test_Bench of ENT00257_Test_Bench is
begin
L1:
block
signal s1, s2 : boolean := true ;
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00257 ( ARCH00257 )
port map ( s1 ) ;
for CIS2 : UUT use entity WORK.ENT00257 ( ARCH00257_1 )
port map ( s2 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
process ( s1, s2 )
begin
if s1 = true and s2 = false then
print ( "*** Examine log file to verify that the following" &
"two messages appear twice:" ) ;
print ( "Passive concurrent procedure call in interface shared" &
"among architectures" ) ;
print ( "Passive process statement in interface shared among" &
"architectures" ) ;
end if ;
end process ;
end block L1 ;
end ARCH00257_Test_Bench ;
| gpl-3.0 | 2e3bdeeb3e8fef16fae2a72de671c40c | 0.598547 | 3.758065 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/output_fifo_1/synth/output_fifo.vhd | 3 | 38,832 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
| unlicense | ee22c4adafdc078da3fdaffa5eac52ac | 0.627137 | 2.91291 | false | false | false | false |
dcliche/mdsynth | rtl/src/sound/channel.vhd | 1 | 8,515 | -- MDSynth Sound Chip
--
-- Copyright (c) 2012-2022, Daniel Cliche
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity channel is
port ( clk: in std_logic;
reset: in std_logic;
waveform: in std_logic_vector(2 downto 0); -- 0: DAC direct, 1: Square (message only), 2: Sawtooth (message only), 3: Sine (message only), 4: FM (implemented as phase modulation), 5: Noise
note_on: in std_logic;
gain_message: in unsigned(5 downto 0);
gain_modulated: in unsigned(5 downto 0);
phase_delta: in unsigned(11 downto 0);
octave_message: in unsigned(3 downto 0);
octave_carrier: in unsigned(3 downto 0);
waveform_message: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
waveform_modulated: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
attack_rate: in unsigned(3 downto 0);
release_rate: in unsigned(3 downto 0);
reset_phase: in std_logic;
dac_direct_value: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
envelope_phase: out std_logic_vector(1 downto 0));
end channel;
architecture channel_arch of channel is
component sinewave is
port ( clk: in std_logic;
gain: in unsigned(5 downto 0);
phase: in unsigned(7 downto 0);
waveform: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
data_out: out integer range -128 to 127);
end component;
component nco is
port ( clk: in std_logic;
reset_phase: in std_logic;
ena: in std_logic;
phase_delta: in unsigned(11 downto 0);
octave: in unsigned(3 downto 0);
phase: out unsigned(7 downto 0));
end component;
component envelope is
port ( clk: in std_logic;
reset: in std_logic;
note_on: in std_logic;
attack_rate: in unsigned(3 downto 0);
release_rate: in unsigned(3 downto 0);
gain: out unsigned(5 downto 0);
phase: out std_logic_vector(1 downto 0));
end component;
signal dac_in : std_logic_vector(7 downto 0);
signal phase_carrier : unsigned(7 downto 0);
signal phase_message : unsigned(7 downto 0);
signal phase_modulated : unsigned(8 downto 0);
signal sine_message : integer range -128 to 127 := 0;
signal sine_modulated : integer range -128 to 127 := 0;
type state_type is (
sinewave_message_state,
sinewave_modulated_state);
signal state : state_type := sinewave_message_state;
signal sine_gain : unsigned(5 downto 0);
signal sine_phase : unsigned(7 downto 0);
signal sine_waveform : std_logic_vector(1 downto 0);
signal sine_data : integer range -128 to 127;
signal ena_nco_carrier : std_logic;
signal ena_nco_message : std_logic;
signal envelope_reset : std_logic := '1';
signal envelope_gain : unsigned(5 downto 0);
signal lfsr_counter : unsigned(11 downto 0);
signal lfsr_data : std_logic_vector(31 downto 0);
begin
nco_carrier0 : nco port map (clk => clk, reset_phase => reset_phase, ena => ena_nco_carrier, phase_delta => phase_delta, octave => octave_carrier, phase => phase_carrier);
nco_message0 : nco port map (clk => clk, reset_phase => reset_phase, ena => ena_nco_message, phase_delta => phase_delta, octave => octave_message, phase => phase_message);
sinewave0 : sinewave port map (clk => clk, gain => sine_gain, phase => sine_phase, waveform => sine_waveform, data_out => sine_data);
envelope0 : envelope port map (clk => clk, reset => envelope_reset, note_on => note_on, attack_rate => attack_rate, release_rate => release_rate, gain => envelope_gain, phase => envelope_phase);
lfsr0 : entity work.lfsr
generic map (
g_Num_Bits => 32
)
port map (
i_Clk => std_logic(lfsr_counter(11)),
i_Enable => '1',
i_Seed_DV => '0',
i_Seed_Data => (31 downto 0 => '0'),
o_LFSR_Data => lfsr_data
);
process (clk, reset)
begin
if (reset = '1') then
dac_in <= "00000000";
sine_gain <= to_unsigned(0, 6);
sine_phase <= to_unsigned(0, 8);
sine_waveform <= "00";
envelope_reset <= '1';
elsif (rising_edge(clk)) then
lfsr_counter <= lfsr_counter + 1;
envelope_reset <= '0';
phase_modulated <= to_unsigned(to_integer(phase_carrier) + sine_message, 9);
output <= dac_in;
case state is
when sinewave_message_state =>
-- We calculate the message waveform
ena_nco_message <= '1';
ena_nco_carrier <= '0';
sine_phase <= phase_message;
sine_gain <= gain_message;
sine_waveform <= waveform_message;
sine_message <= sine_data;
state <= sinewave_modulated_state;
when sinewave_modulated_state =>
-- We calculate the modulated waveform
ena_nco_message <= '0';
ena_nco_carrier <= '1';
if waveform = "101" then
-- noise
sine_phase <= unsigned(lfsr_data(7 downto 0));
else
sine_phase <= phase_modulated(7 downto 0);
end if;
--sine_gain <= gain_modulated;
sine_gain <= envelope_gain;
sine_waveform <= waveform_modulated;
sine_modulated <= sine_data;
state <= sinewave_message_state;
end case;
-- We update the DAC
case waveform is
when "001" =>
-- Square wave
if (phase_message(7) = '1') then
dac_in(7 downto 0) <= (others => '1');
else
dac_in(7 downto 0) <= (others => '0');
end if;
when "010" =>
-- Sawtooth wave
dac_in <= std_logic_vector(phase_message);
when "011" =>
-- Sine wave
dac_in <= std_logic_vector(to_unsigned(128 + sine_message, 8));
when "100" =>
-- PM
dac_in <= std_logic_vector(to_unsigned(128 + sine_modulated, 8));
when "101" =>
-- Noise
dac_in <= std_logic_vector(to_unsigned(128 + sine_modulated, 8));
when others =>
-- DAC direct
dac_in <= dac_direct_value;
end case;
end if;
end process;
end channel_arch;
| gpl-3.0 | bc05dcd6b28ace3ea6efc0953122f008 | 0.568526 | 4.048978 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00179.vhd | 1 | 41,142 | -- NEED RESULT: ARCH00179.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00179
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00179
-- PKG00179/BODY
-- E00000(ARCH00179)
-- ENT00179_Test_Bench(ARCH00179_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00179 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00179 ;
--
package body PKG00179 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00179 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00179.all ;
architecture ARCH00179 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00179 ;
--
entity ENT00179_Test_Bench is
end ENT00179_Test_Bench ;
--
architecture ARCH00179_Test_Bench of ENT00179_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00179 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00179_Test_Bench ;
| gpl-3.0 | 6f8dbac92e1db966d9ed1f154bf123c2 | 0.502017 | 3.224042 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/frontend.vhd | 1 | 11,270 | --*****************************************************************************
-- @Copyright All rights reserved.
-- Module name : frontend
-- Call by :
-- Description :
-- IC :
-- Version : 1.0
-- Note: :
-- Author : QIU Weibao
-- Date : 2013.08.06
-- Update :
--
--
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity frontend is
port
(
I_reset_n : in std_logic;
I_sys_clk : in std_logic;
I_scan_trig : in std_logic; --scan triger
I_reg_csr : in std_logic_vector(31 downto 0);
--ADC
I_adc_d : in std_logic_vector(11 downto 0);
I_adc_or : in std_logic;
I_f2pc_full : in std_logic;
O_pixel_symbol : out std_logic;
O_pixel_en : out std_logic;
O_pixel_data : out std_logic_vector(15 downto 0);
O_pulse_trig : out std_logic;
O_shake_start : out std_logic
);
end frontend;
architecture rtl of frontend is
--component fir_band_pass is
--PORT
--(
-- clk : IN STD_LOGIC;
-- reset_n : IN STD_LOGIC;
-- ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- ast_sink_valid : IN STD_LOGIC;
-- ast_source_ready: IN STD_LOGIC;
-- ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-- ast_sink_ready : OUT STD_LOGIC;
-- ast_source_valid: OUT STD_LOGIC;
-- ast_source_error: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
--);
--end component;
component analytic_filter_h_a1 is -- component hilbert tansform
generic(
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7 --delay of hilbert filter (including pipeline delay)
);
port(
clk_i : in std_logic;
rst_i : in std_logic; --high level reset
data_str_i : in std_logic; --hilbert tranform enable
data_i : in std_logic_vector(input_data_width-1 downto 0);
data_i_o : out std_logic_vector(output_data_width-1 downto 0);
data_q_o : out std_logic_vector(output_data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
component r2p_corproc
port(
clk : in std_logic;
ena : in std_logic;
Xin : in STD_LOGIC_VECTOR(15 downto 0);
Yin : in STD_LOGIC_VECTOR(15 downto 0);
Rout : out STD_LOGIC_VECTOR(19 downto 0);
Aout : out STD_LOGIC_VECTOR(19 downto 0)
);
end component;
--constant C_FILTER_DELAY : integer := 17; --filter delay 15, adc buffer 2
constant C_CORDIC_DELAY : integer := 1000;--20;
signal s_scan_trig : std_logic:='0';
signal s_work_start : std_logic;
signal S_fir_sink_valid : std_logic; --filter input data valid
signal S_fir_sink_ready : std_logic; --filter is able to accept data
signal S_fir_source_valid : std_logic; --assert by fir filter when there is valid data to output
signal S_fir_source_error : std_logic_vector(1 downto 0); --"00" no error
signal S_fir_source_data : std_logic_vector(15 downto 0); --filter output data
signal S_hilbert_reset : std_logic; --high level reset
signal S_hilbert_data_str_i : std_logic;
signal S_hilbert_data_io : std_logic_vector(15 downto 0);
signal S_hilbert_data_qo : std_logic_vector(15 downto 0);
signal S_hilbert_data_str_o : std_logic;
signal S_cordic_rout : std_logic_vector(19 downto 0):=x"00000";
signal S_cordic_aout : std_logic_vector(19 downto 0);
signal S_ad_buf : std_logic_vector(11 downto 0);
signal S_ocnt : std_logic_vector(19 downto 0):="00000000000000000000";
signal S_state : std_logic_vector(2 downto 0);
signal s_oen : std_logic;
signal s_den : std_logic;
signal s_scan_start : std_logic;
signal S_scan_state : std_logic_vector(1 downto 0);
signal s_work_start_buf : std_logic;
signal S_line_num : std_logic_vector(9 downto 0);
constant C_line_delay : integer := 17000;--4700;--181250;--40000;
signal S_line_delay : std_logic_vector(19 downto 0):="00000000000000000000";
signal S_hilbert_data_i_0 : std_logic_vector(15 downto 0);
signal S_hilbert_data_i_1 : std_logic_vector(15 downto 0);
signal S_hilbert_data_i : std_logic_vector(15 downto 0);
signal S_hilbert_data_i_temp : std_logic_vector(15 downto 0);
signal S_pulse_trig : std_logic;
signal S_data_type : std_logic_vector(1 downto 0);
signal S_delay_cnt : std_logic_vector(20 downto 0);
begin
s_work_start <= '1';--I_reg_csr(0);
S_hilbert_data_i_temp <= I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d;
O_pixel_symbol <= s_den;
O_pixel_data <= S_hilbert_data_i; -- 将AD9230采集到的数据未经任何处理，直接上传上位机。
O_pixel_en <= s_oen;
O_pulse_trig <= S_pulse_trig;
--------------------RF DATA--------------------
S_data_type <= "01";--I_reg_csr(5 downto 4);
process(I_sys_clk, I_reset_n) -- 打拍，把AD9230的数据读进来。
begin
if (I_reset_n='0') then
S_hilbert_data_i_0 <= (others=>'0');
S_hilbert_data_i_1 <= (others=>'0');
S_hilbert_data_i <= (others=>'0');
elsif(I_sys_clk'event and I_sys_clk='1') then
S_hilbert_data_i_0 <= S_hilbert_data_i_temp;
S_hilbert_data_i_1 <= S_hilbert_data_i_0;
S_hilbert_data_i <= S_hilbert_data_i_1;
end if;
end process;
process(I_sys_clk,I_reset_n)
begin
if (I_reset_n = '0') then
S_state <= (others=>'0');
S_ocnt <= (others=>'0');
s_oen <= '0';
s_den <= '0';
S_pulse_trig <= '0';
S_hilbert_reset <= '1';
S_hilbert_data_str_i <= '0';
S_delay_cnt <= (others=>'0');
S_line_num <= (others => '0');
S_line_delay <= (others => '0');
elsif rising_edge(I_sys_clk) then
s_work_start_buf <= s_work_start;
s_scan_trig <= I_scan_trig;
S_hilbert_data_str_i <= '1';
S_hilbert_reset <= '0';
case S_state is
when "000" => -- 等待开始。
if (s_scan_trig = '0' and I_scan_trig = '1' and s_work_start_buf = '1')then
S_state <= "001";
s_oen <= '1';
S_line_num <= (others => '0');
S_line_delay <= (others => '0');
else
S_ocnt <= (others=>'0');
s_oen <= '0';
s_den <= '0';
S_line_num <= (others => '0');
S_line_delay <= (others => '0');
S_pulse_trig <= '0';
end if;
when "001" =>
if S_delay_cnt >= 1000 then -- 丢掉测试前的1000个点，此处没特殊意义，调试遗留，不影响使用，可删除。
S_state <= "010";
S_delay_cnt <= (others=>'0');
else
S_delay_cnt <= S_delay_cnt +1;
end if;
when "010" =>
S_pulse_trig <= '1'; -- 超声发射使能有效，开始超声激励。 --start trans--
S_delay_cnt <= (others=>'0');
if (S_ocnt >= C_CORDIC_DELAY) then -- 每条线丢掉前1000个点，因为离表面太近，数据不参与计算。 --recive delay time--
S_state <= "011";
s_den <= '1'; -- start receive --
S_ocnt <= (others=>'0');
else
S_ocnt <= S_ocnt + 1;
end if;
when "011" =>
if (S_ocnt >= 4095) then -- 每条线采集4096点
S_state <= "100";
S_ocnt <= (others=>'0');
s_den <= '0'; -- stop receive--
S_line_num <= S_line_num + 1;
S_pulse_trig <= '0'; -- stop trans ---
else
S_ocnt <= S_ocnt + 1;
end if;
S_line_delay <= S_line_delay + 1;
when "100" =>
if S_line_num > 299 then -- 采集300条线
S_state <= "101";
else
if S_line_delay > C_line_delay then
S_state <= "010";
S_line_delay <= (others => '0');
else
S_line_delay <= S_line_delay + 1;
end if;
end if;
when "101" =>
S_state <= (others=>'0');
S_ocnt <= (others=>'0');
s_oen <= '0';
s_den <= '0';
S_pulse_trig <= '0';
S_line_num <= (others => '0');
when others=>
S_state <= (others=>'0');
S_ocnt <= (others=>'0');
s_oen <= '0';
s_den <= '0';
S_pulse_trig <= '0';
S_line_num <= (others => '0');
end case ;
end if;
if S_line_num > 33 then -- 在采集第33条线时，电磁铁开始振动，此数值需结合算法修改，不能随意变动。
O_shake_start <= '1';
else
O_shake_start <= '0';
end if;
end process;
U2_analytic_filter_h_a1_inst:analytic_filter_h_a1 -- 未使用
generic map(
input_data_width => 16,
output_data_width => 16,
filter_delay_in_clks => 7 --delay of hilbert filter (including pipeline delay)
)
port map(
clk_i => I_sys_clk,--I_sys_clk,
rst_i => S_hilbert_reset, --high reset
data_str_i => S_hilbert_data_str_i,
data_i => S_hilbert_data_i,--S_fir_source_data,
data_i_o => S_hilbert_data_io,
data_q_o => S_hilbert_data_qo,
data_str_o => S_hilbert_data_str_o -- delay 7 clock than data_str_i
);
U6_r2p_corproc_inst:r2p_corproc -- 未使用
port map
(
clk => I_sys_clk,--I_sys_clk,
ena => '1',
Xin => S_hilbert_data_io,
Yin => S_hilbert_data_qo,
Rout => S_cordic_rout,
Aout => S_cordic_aout
);
--
end rtl; | apache-2.0 | c4876d61a03a37224c3865ff41febef4 | 0.454604 | 3.031847 | false | false | false | false |
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