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BBN-Q/APS2-Comms | test/IPv4_packet_pkg.vhd | 1 | 8,164 | -- Package for handling IPv4 headers, UDP and TCP packets
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_frame_pkg.byte_array;
package IPv4_packet_pkg is
subtype IPv4_addr_t is byte_array(0 to 3);
function header_checksum(header : byte_array) return std_logic_vector;
function ipv4_header(
protocol : std_logic_vector(7 downto 0);
packet_length : natural;
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t
) return byte_array;
function udp_checksum(packet : byte_array) return std_logic_vector;
function udp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
payload : byte_array
) return byte_array;
function tcp_checksum(packet : byte_array) return std_logic_vector;
function tcp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
seq_num : natural;
ack_num : natural;
syn : std_logic;
ack : std_logic;
payload : byte_array
) return byte_array;
end IPv4_packet_pkg;
package body IPv4_packet_pkg is
function header_checksum(header : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
begin
--Sum header
for ct in 0 to 9 loop
--For some reason Vivado can't infer this as one line
-- sum := sum + unsigned(header(2*ct) & header(2*ct+1))
tmp := header(2*ct) & header(2*ct+1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in the carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--Return one's complement
return not checksum;
end header_checksum;
function ipv4_header(
protocol : std_logic_vector(7 downto 0);
packet_length : natural;
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t
) return byte_array is
variable header : byte_array(0 to 19);
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable idx : natural := 0;
begin
header(0) := x"45"; --version and header length
header(1) := x"00"; --type of service
len := to_unsigned(packet_length, 16);
header(2) := std_logic_vector(len(15 downto 8));
header(3) := std_logic_vector(len(7 downto 0));
header(4) := x"ba"; header(5) := x"ad"; -- identification
header(6) := x"00"; header(7) := x"00"; --flags and fragment
header(8) := x"80"; --time to live
header(9) := protocol; --protocol
header(10) := x"00"; header(11) := x"00"; --checksum
idx := 12;
--source IP
for ct in 0 to 3 loop
header(idx) := src_IP(ct);
idx := idx + 1;
end loop;
--destination IP
for ct in 0 to 3 loop
header(idx) := dest_IP(ct);
idx := idx + 1;
end loop;
--Calculate checksum and insert it
checksum := header_checksum(header);
header(10) := checksum(15 downto 8);
header(11) := checksum(7 downto 0);
return header;
end ipv4_header;
function udp_checksum(packet : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
variable udp_length : natural;
begin
--Extract pseudo packet header
--source and dest IP
for ct in 0 to 3 loop
tmp := packet(12 + 2*ct) & packet(12 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Protocol 0x0011
sum := sum + to_unsigned(17, 32);
--UDP length
tmp := packet(24) & packet(25);
sum := sum + unsigned(tmp);
udp_length := to_integer(unsigned(tmp));
for ct in 0 to udp_length/2 - 1 loop
tmp := packet(20 + 2*ct) & packet(20 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--return one's complement
return not checksum;
end udp_checksum;
function udp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
payload : byte_array
) return byte_array is
variable packet_length : natural := 20 + 8 + payload'length; --IPv4 header + UDP header
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable packet : byte_array(0 to packet_length-1);
begin
--IPv4 header
packet(0 to 19) := ipv4_header(x"11", packet_length, src_IP, dest_IP);
--UDP source and destination port
packet(20) := src_port(15 downto 8);
packet(21) := src_port(7 downto 0);
packet(22) := dest_port(15 downto 8);
packet(23) := dest_port(7 downto 0);
--UDP packet length
len := to_unsigned(8 + payload'length, 16);
packet(24) := std_logic_vector(len(15 downto 8));
packet(25) := std_logic_vector(len(7 downto 0));
--checksum
packet(26) := x"00";
packet(27) := x"00";
--start after IPv4 + UDP header
for ct in 0 to payload'high loop
packet(28+ct) := payload(ct);
end loop;
--Go back and fill in checksum
checksum := udp_checksum(packet);
packet(26) := checksum(15 downto 8);
packet(27) := checksum(7 downto 0);
return packet;
end udp_packet;
function tcp_checksum(packet : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
variable tcp_length : natural;
begin
--Extract pseudo packet header
--source and dest IP
for ct in 0 to 3 loop
tmp := packet(12 + 2*ct) & packet(12 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Protocol 0x0006
sum := sum + to_unsigned(6, 32);
--tcp length - subtract off ipv4 header (20 bytes)
tcp_length := packet'length - 20;
sum := sum + to_unsigned(tcp_length, 32);
for ct in 0 to tcp_length/2 - 1 loop
tmp := packet(20 + 2*ct) & packet(20 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--return one's complement
return not checksum;
end tcp_checksum;
function tcp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
seq_num : natural;
ack_num : natural;
syn : std_logic;
ack : std_logic;
payload : byte_array
) return byte_array is
variable packet_length : natural := 20 + 20 + payload'length; --IPv4 header + TCP header
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable packet : byte_array(0 to packet_length-1);
variable num : std_logic_vector(31 downto 0);
begin
--IPv4 header
packet(0 to 19) := ipv4_header(x"06", packet_length, src_IP, dest_IP);
--TCP source and destination port
packet(20) := src_port(15 downto 8);
packet(21) := src_port(7 downto 0);
packet(22) := dest_port(15 downto 8);
packet(23) := dest_port(7 downto 0);
--sequence number
num := std_logic_vector(to_unsigned(seq_num, 32));
packet(24) := num(31 downto 24);
packet(25) := num(23 downto 16);
packet(26) := num(15 downto 8);
packet(27) := num(7 downto 0);
--ack number
num := std_logic_vector(to_unsigned(ack_num, 32));
packet(28) := num(31 downto 24);
packet(29) := num(23 downto 16);
packet(30) := num(15 downto 8);
packet(31) := num(7 downto 0);
packet(32) := x"50"; --data offset
--flags
if payload'length > 0 then
packet(33) := "000" & ack & "00" & syn & "0";
else
packet(33) := "000" & ack & "10" & syn & "0";
end if;
--window size
packet(34) := x"08";
packet(35) := x"00";
--checksum
packet(36) := x"00";
packet(37) := x"00";
--urgent pointer
packet(38) := x"00"; packet(39) := x"00";
for ct in 0 to payload'high loop
packet(40+ct) := payload(ct);
end loop;
--Go back and fill in checksum
checksum := tcp_checksum(packet);
packet(36) := checksum(15 downto 8);
packet(37) := checksum(7 downto 0);
return packet;
end tcp_packet;
end package body;
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`protect end_protected
| apache-2.0 | a7c88b755c3babdbd8675005dee67783 | 0.952134 | 1.812249 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug_stat.vhd | 1 | 76,313 | `protect begin_protected
`protect version = 1
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`protect key_block
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`protect key_block
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`protect key_block
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`protect end_protected
| apache-2.0 | ead8caca3cfe08916844bab566c1da77 | 0.951162 | 1.811628 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/uartlite_rx.vhd | 1 | 25,186 | -------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- ~~~~~~
-- 20/09/20 SK
-- - Updated the version as AXI Lite IPIF version is updated.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library proc_common_v4_0;
-- dynshreg_i_f refered from proc_common_v4_0
use proc_common_v4_0.dynshreg_i_f;
-- srl_fifo_f refered from proc_common_v4_0
use proc_common_v4_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity proc_common_v4_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity proc_common_v4_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
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`protect end_protected
| apache-2.0 | 8d0dca5b5427df0619f9135c1c8071df | 0.937058 | 1.875822 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/metaheurísticas/mpegmv_wsga.vhd | 1 | 2,687 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:32)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_wsga_entity;
ARCHITECTURE mpegmv_wsga_description OF mpegmv_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register4 := register4 + 6;
register5 := input5 * 7;
register6 := input6 * 8;
register3 := register3 + 10;
register2 := register2 + 12;
WHEN "00000011" =>
register1 := register1 + register2;
register2 := register6 + register3;
register3 := input7 * 13;
register4 := register5 + register4;
register5 := input8 * 14;
WHEN "00000100" =>
register1 := register5 + register1;
register5 := input9 * 15;
register2 := register3 + register2;
register3 := input10 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register6 := input11 * 19;
register3 := register3 + 21;
WHEN "00000110" =>
output1 <= register5 + register3;
register3 := input12 * 23;
register5 := register6 + 25;
WHEN "00000111" =>
register3 := register3 + register5;
register5 := input13 * 26;
output2 <= register1(0 TO 1) & register2(0 TO 2);
WHEN "00001000" =>
register1 := register5 + register3;
register2 := input14 * 28;
WHEN "00001001" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + register4;
WHEN "00001010" =>
output3 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_wsga_description; | gpl-3.0 | 3cfb3ee0a771310725e03868103f2c5c | 0.655006 | 3.060364 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/logic_sshft.vhd | 5 | 30,599 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
| apache-2.0 | ba890bb7ba952f6e72bc03083417a8c3 | 0.94539 | 1.825171 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/metaheurísticas/mesahb_femo.vhd | 1 | 1,966 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_femo_entity;
ARCHITECTURE mesahb_femo_description OF mesahb_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
output1 <= input1 + 1;
register1 := input2 * 2;
WHEN "00000010" =>
register2 := input3 * 3;
register1 := register1 + 5;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + 9;
WHEN "00000100" =>
register2 := register2 * 11;
WHEN "00000101" =>
register3 := input4 * 12;
register2 := register2 + 14;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
register1 := register3 * register1;
WHEN "00000111" =>
register2 := register2 * 18;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input5 * 19;
WHEN "00001001" =>
register2 := register2 + 21;
WHEN "00001010" =>
register2 := register2 * 23;
WHEN "00001011" =>
register2 := register2 + 25;
WHEN "00001100" =>
output2 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_femo_description; | gpl-3.0 | 6757e37d64cf4453d249cc2f09d44d9f | 0.651068 | 3.029276 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/zero_detect_gti.vhd | 1 | 15,057 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9408)
`protect data_block
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`protect end_protected
| apache-2.0 | 1ae135353629cb18fb38296e4b222f36 | 0.935645 | 1.864644 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sim_1/new/tb_hack.vhd | 1 | 454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_hack is
end tb_hack;
architecture Behavioral of tb_hack is
signal clock : std_ulogic := '0';
signal reset : std_ulogic := '0';
begin
clock <= not clock after 7.57575757 ns;
uut : entity work.Hack(Behavioral)
port map (
clock => clock,
reset => reset
);
stimuli : process
begin
reset <= '1';
wait for 10 us;
reset <= '0';
wait for 1000 ms;
wait;
end process;
end Behavioral;
| agpl-3.0 | c141d37ddf0e1ede5d4763a7eab3a58f | 0.660793 | 2.873418 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rdmux.vhd | 1 | 27,755 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rdmux.vhd
--
-- Description:
-- This file implements the AXi Master Burst Read Data Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_rdmux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.1.2.3 $
-- Date: $10/26/2009$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover V2_00_a axi_datamover_rdmux.vhd
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
--
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_rdmux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32
);
port (
-- AXI MMap Data Channel Input -------------------------------
mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0);
-- AXI Read data input
-- AXI Master Stream -----------------------------------
mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
--Mux data output
-- Command Calculator Interface --------------------------
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0)
-- The next command start address LSbs to use for the read data
-- mux (only used if Stream data width is less than the MMap Data
-- Width).
);
end entity axi_master_burst_rdmux;
architecture implementation of axi_master_burst_rdmux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
-- coverage off
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
-- coverage on
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (channel_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case channel_width is
-- coverage off
when 16 =>
var_sel_ls_index := 1;
-- coverage on
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
-- coverage off
when 256 =>
var_sel_ls_index := 5;
when others => -- 8-bit channel case
var_sel_ls_index := 0;
-- coverage on
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH;
Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
mux_data_out <= sig_rdmux_dout;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate
begin
sig_rdmux_dout <= mmap_read_data_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel input mux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer range 0 to 31 := 0;
signal sig_mux_sel_int_local : integer range 0 to 31 := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_NUX
--
-- Process Description:
-- Implement the 2XN Mux
--
-------------------------------------------------------------
DO_2XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when others =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
end case;
end process DO_2XN_NUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel input mux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer range 0 to 31 := 0;
signal sig_mux_sel_int_local : integer range 0 to 31 := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_NUX
--
-- Process Description:
-- Implement the 4XN Mux
--
-------------------------------------------------------------
DO_4XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when others =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
end case;
end process DO_4XN_NUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel input mux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer range 0 to 31 := 0;
signal sig_mux_sel_int_local : integer range 0 to 31 := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_NUX
--
-- Process Description:
-- Implement the 8XN Mux
--
-------------------------------------------------------------
DO_8XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when others =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
end case;
end process DO_8XN_NUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel input mux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer range 0 to 31 := 0;
signal sig_mux_sel_int_local : integer range 0 to 31 := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_NUX
--
-- Process Description:
-- Implement the 16XN Mux
--
-------------------------------------------------------------
DO_16XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when others =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
end case;
end process DO_16XN_NUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel input mux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer range 0 to 31 := 0;
signal sig_mux_sel_int_local : integer range 0 to 31 := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_NUX
--
-- Process Description:
-- Implement the 32XN Mux
--
-------------------------------------------------------------
DO_32XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when others =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
end case;
end process DO_32XN_NUX;
end generate GEN_32XN;
end implementation;
| apache-2.0 | 198380ed832a4e94185409df1e4fe665 | 0.474581 | 4.451484 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/Tri_state_buf.vhd | 1 | 478 | Library ieee;
use ieee.std_logic_1164.all;
entity tri_state_buf is
generic (width : integer := 4);
port (input : std_logic_vector((width-1) downto 0);
enable : std_logic;
output : out std_logic_vector((width-1) downto 0));
end tri_state_buf;
architecture behavior of tri_state_buf is
begin
process(input,enable)
begin
if (enable = '1')
then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavior;
| mit | 11f3b77b79dc09baf12288b658042682 | 0.631799 | 3.319444 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo_f.vhd | 15 | 9,654 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity proc_common_v4_0.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
| apache-2.0 | ff8d2408d3eed33ea4162fd6dae8ef05 | 0.436607 | 5.089088 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/disp7segx4.vhd | 1 | 2,430 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:01 06/13/2012
-- Design Name:
-- Module Name: disp7segx4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
entity disp7segx4 is
Port ( entrada : in STD_LOGIC_VECTOR (15 downto 0);
clock : in std_logic;
clk_1k : out std_logic;
reset : in std_logic;
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
-- disp_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0));
end disp7segx4;
architecture Behavioral of disp7segx4 is
type vetor_de_std_logic_vector is array (3 downto 0) of std_logic_vector (7 downto 0);
type vetor_de_10_std_logic_vector is array (9 downto 0) of std_logic_vector (7 downto 0);
signal display : vetor_de_std_logic_vector;
signal cont : integer range 0 to 3 := 0;
signal disp_sel : std_logic_vector (3 downto 0) := "1110";
signal clk_1k_sgn : std_logic:='0';
signal clock_1k : integer range 0 to 26000 :=0;
begin
clock_div : process (reset, clock)
begin
if reset = '1' then
clock_1k <= 0;
elsif clock'event and clock ='1' then
if(clock_1k > 25000) then
clk_1k_sgn <= not clk_1k_sgn;
clock_1k <= 0;
else
clock_1k <= clock_1k +1;
end if;
else
clock_1k <= clock_1k;
end if;
end process;
process (clk_1k_sgn, reset)
begin
if reset = '1' then
disp_sel <= "1110";
cont <= 0;
elsif clk_1k_sgn'event and clk_1k_sgn = '1' then
disp_sel(3 downto 1) <= disp_sel(2 downto 0);
disp_sel(0) <= disp_sel(3);
cont <= cont +1;
else
disp_sel <= disp_sel;
cont <= cont;
end if;
end process;
disp_sel_o <= disp_sel;
laco_for : for i in 0 to 3 generate
display1 : entity work.disp7seg
port map ( entrada => entrada((i+1)*4 -1 downto i*4),
clock => clock,
reset => reset,
saida_8segmentos => display(i));
saida_8segmentos <= display(cont REM 4);
end generate;
clk_1k <= clk_1k_sgn;
end Behavioral;
| mit | 11d8177616587caf3a9dd6249ce654f0 | 0.567901 | 2.87574 | false | false | false | false |
marceloboeira/vhdl-examples | 005-button-ledbar/test-bench.vhd | 1 | 885 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_exe2a4 IS
END TB_exe2a4;
ARCHITECTURE behavior OF TB_btn_led IS
COMPONENT btn_led
PORT(
btn : IN std_logic;
reset : IN std_logic;
ledA : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal btn : std_logic := '0';
signal reset : std_logic := '1';
--Outputs
signal ledA : std_logic_vector(7 downto 0);
constant btn_period : time := 1 ms;
BEGIN
uut: TB_btn_led PORT MAP (
btn => btn,
reset => reset,
ledA => ledA
);
btn_process :process
begin
btn <= '0';
wait for btn_period/2;
btn <= '1';
wait for btn_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
reset <= '0';
-- insert stimulus here
wait;
end process;
END;
| mit | 2041b24dad03a9719f9e35d4bdf8e115 | 0.543503 | 3.430233 | false | false | false | false |
rcls/sdr | vhdl/audio.vhd | 1 | 2,179 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
-- Sample rate is 250MHz / 6400 = 39062.5Hz.
-- sample rate * 256 is 250MHz / 25 = 10M.
-- sample rate * 128 is 5M.
-- Let's extend samples to 32 bits.
-- Bck = 250MHz / 100 = lrck * 64, sck = 250Mhz / 50 = lrck * 128
-- The incoming sample rate is one every 400 cycles, each channel has one
-- every 1600 cycles.
entity audio is
-- So lrck is bit/(2*lcrk_divider).
generic (bits_per_sample : integer);
port (left, right : in signed(bits_per_sample-1 downto 0);
channel : in unsigned2;
last : in std_logic;
scki, lrck, data, bck : out std_logic;
clk : in std_logic);
end audio;
architecture audio of audio is
signal divider : unsigned (12 downto 0);
signal sample_hold : signed(63 downto 0);
signal shift_reg : signed(63 downto 0);
signal sample_shift, sample_load, shift_load : boolean;
signal prev_last : std_logic;
constant repeat_end : integer := 2 * bits_per_sample - 32;
begin
data <= shift_reg(63);
process
begin
wait until rising_edge(clk);
prev_last <= last;
-- In the bottom 5 bits, do /25 instead of /31. We maintain phase with
-- last by slipping a cycle if shift/load is asserted incorrectly.
if sample_shift and shift_load and not (prev_last='1' and last='0') then
else
if divider(4 downto 3) = "11" then
divider <= divider + 8;
else
divider <= divider + 1;
end if;
end if;
lrck <= divider(12);
bck <= divider(6);
scki <= divider(4);
sample_shift <= divider(6 downto 3) = "1111";
shift_load <= divider(12 downto 7) = "111111";
sample_load <= divider(12 downto 7) = "11" & (channel - "01") & "11";
if sample_shift then
if shift_load then
--shift_reg <= left & left(bits_per_sample - 1 downto repeat_end)
-- & right & right(bits_per_sample - 1 downto repeat_end);
shift_reg <= sample_hold;
else
shift_reg <= shift_reg sll 1;
end if;
if sample_load then
sample_hold <= left & right;
end if;
end if;
end process;
end audio;
| gpl-3.0 | e6e6d87d9768c1069a615d30a31e0124 | 0.61542 | 3.399376 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/fifo_generator_v12_0_comps_builtin.vhd | 5 | 32,006 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21952)
`protect data_block
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`protect end_protected
| apache-2.0 | ce7223c5a3efd9ca0e82036aaad04a6e | 0.94426 | 1.837419 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_logic_pkt_fifo.vhd | 5 | 31,831 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
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`protect end_protected
| apache-2.0 | 45d4abd1f208521cb879a8f185fba7f7 | 0.94653 | 1.837499 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd | 15 | 11,429 | -------------------------------------------------------------------------------
-- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** code and therefore cannot answer specific questions related **
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-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library proc_common_v4_0;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
use proc_common_v4_0.family_support;
use family_support.all; -- primitives_type, primitive_array_type, supported
constant COUNTER_PRIMS_AVAIL : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate
signal hsum_A : std_logic_vector(Cnt'range);
signal cry : std_logic_vector(Cnt'length downto 0);
begin
---(
cry(0) <= Incr;
Addr_Counters : for I in cnt_i'range generate
hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I));
MUXCY_L_I : component MUXCY_L
port map (
DI => cnt_i(I),
CI => cry(I),
S => hsum_A(I),
LO => cry(I+1));
XORCY_I : component XORCY
port map (
LI => hsum_A(I),
CI => cry(I),
O => cnt_i_p1(I));
FDS_I : component FDS
port map (
Q => cnt_i(I),
C => Clk,
D => cnt_i_p1(I),
S => Reset);
end generate Addr_Counters;
---)
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
| apache-2.0 | 5da3cfaa6e0c7186172442eebd58c72c | 0.436959 | 4.748234 | false | false | false | false |
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`protect end_protected
| apache-2.0 | c92a6db39648135176f966962c327d8a | 0.936156 | 1.881419 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/parity.vhd | 1 | 20,484 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| apache-2.0 | 5b9337e58c7e214f0686f01ffb780c71 | 0.940881 | 1.846237 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/register_file_gti.vhd | 1 | 16,140 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | 140d817b2055e2967dda47d9fd16f8e9 | 0.938228 | 1.867191 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_13.vhd | 1 | 57,555 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_13x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A74: buffer std_logic
);
end x25_13x;
architecture x25_13x_behav of x25_13x is
signal a1a,a2a,a3a,a4a,a5a,a6a,a7a,a8a,a9a,a10a,a11a,a12a,a13a,a14a,a15a,a16a,a17a,a18a,a19a,a20a,a21a,a22a,a23a,a24a,a25a,a26a,a27a,a28a,a29a,a30a,a31a,a32a,a33a,a34a,a35a,a36a,a37a,a38a,a39a,a40a,a41a,a42a,a43a,a44a,a45a,a46a,a47a,a48a,a49a,a50a,a51a,a52a,a53a,a54a,a55a,a56a,a57a,a58a,a59a,a60a,a61a,a62a,a63a,a64a,a65a,a66a,a67a,a68a,a69a,a70a,a71a,a72a,a73a,a74a,a75a,a76a,a77a,a78a,a79a,a80a,a81a,a82a,a83a,a84a,a85a,a86a,a87a,a88a,a89a,a90a,a91a,a92a,a93a,a94a,a95a,a96a,a97a,a98a,a99a,a100a,a101a,a102a,a103a,a104a,a105a,a106a,a107a,a108a,a109a,a110a,a111a,a112a,a113a,a114a,a115a,a116a,a117a,a118a,a119a,a120a,a121a,a122a,a123a,a124a,a125a,a126a,a127a,a128a,a129a,a130a,a131a,a132a,a133a,a134a,a135a,a136a,a137a,a138a,a139a,a140a,a141a,a142a,a143a,a144a,a145a,a146a,a147a,a148a,a149a,a150a,a151a,a152a,a153a,a154a,a155a,a156a,a157a,a158a,a159a,a160a,a161a,a162a,a163a,a164a,a165a,a166a,a167a,a168a,a169a,a170a,a171a,a172a,a173a,a174a,a175a,a176a,a177a,a178a,a179a,a180a,a181a,a182a,a183a,a184a,a185a,a186a,a187a,a188a,a189a,a190a,a191a,a192a,a193a,a194a,a195a,a196a,a197a,a198a,a199a,a200a,a201a,a202a,a203a,a204a,a209a,a210a,a214a,a215a,a216a,a220a,a221a,a225a,a226a,a227a,a228a,a232a,a233a,a237a,a238a,a239a,a243a,a244a,a247a,a250a,a251a,a252a,a253a,a254a,a258a,a259a,a263a,a264a,a265a,a269a,a270a,a273a,a276a,a277a,a278a,a279a,a283a,a284a,a288a,a289a,a290a,a294a,a295a,a298a,a301a,a302a,a303a,a304a,a305a,a306a,a310a,a311a,a315a,a316a,a317a,a321a,a322a,a326a,a327a,a328a,a329a,a333a,a334a,a338a,a339a,a340a,a344a,a345a,a348a,a351a,a352a,a353a,a354a,a355a,a359a,a360a,a364a,a365a,a366a,a370a,a371a,a374a,a377a,a378a,a379a,a380a,a384a,a385a,a389a,a390a,a391a,a395a,a396a,a399a,a402a,a403a,a404a,a405a,a406a,a407a,a408a,a412a,a413a,a417a,a418a,a419a,a423a,a424a,a428a,a429a,a430a,a431a,a435a,a436a,a440a,a441a,a442a,a446a,a447a,a450a,a453a,a454a,a455a,a456a,a457a,a461a,a462a,a466a,a467a,a468a,a472a,a473a,a476a,a479a,a480a,a481a,a482a,a486a,a487a,a491a,a492a,a493a,a497a,a498a,a501a,a504a,a505a,a506a,a507a,a508a,a509a,a513a,a514a,a518a,a519a,a520a,a524a,a525a,a528a,a531a,a532a,a533a,a534a,a538a,a539a,a543a,a544a,a545a,a549a,a550a,a553a,a556a,a557a,a558a,a559a,a560a,a564a,a565a,a569a,a570a,a571a,a575a,a576a,a579a,a582a,a583a,a584a,a585a,a589a,a590a,a594a,a595a,a596a,a600a,a601a,a604a,a607a,a608a,a609a,a610a,a611a,a612a,a613a,a625a,a629a,a633a,a637a,a641a,a645a,a649a,a653a,a657a,a661a,a664a,a667a,a670a,a673a,a676a,a679a,a682a,a685a,a688a,a691a,a694a,a697a,a700a,a703a,a706a,a709a,a712a,a715a,a718a,a721a,a724a,a727a,a730a,a733a,a736a,a739a,a742a,a745a,a748a,a751a,a754a,a757a,a760a,a764a,a765a,a768a,a772a,a773a,a776a,a780a,a781a,a784a,a788a,a789a,a792a,a796a,a797a,a800a,a804a,a805a,a808a,a812a,a813a,a816a,a820a,a821a,a824a,a828a,a829a,a832a,a836a,a837a,a840a,a844a,a845a,a848a,a852a,a853a,a856a,a860a,a861a,a864a,a868a,a869a,a872a,a876a,a877a,a880a,a884a,a885a,a888a,a892a,a893a,a896a,a900a,a901a,a904a,a908a,a909a,a912a,a916a,a917a,a921a,a922a,a926a,a927a,a931a,a932a,a936a,a937a,a941a,a942a,a946a,a947a,a951a,a952a,a956a,a957a,a961a,a962a,a966a,a967a,a971a,a972a,a976a,a977a,a981a,a982a,a986a,a987a,a991a,a992a,a996a,a997a,a1001a,a1002a,a1006a,a1007a,a1011a,a1012a,a1016a,a1017a,a1021a,a1022a,a1026a,a1027a,a1031a,a1032a,a1036a,a1037a,a1041a,a1042a,a1046a,a1047a,a1051a,a1052a,a1056a,a1057a,a1061a,a1062a,a1066a,a1067a,a1071a,a1072a,a1076a,a1077a,a1081a,a1082a,a1086a,a1087a,a1091a,a1092a,a1096a,a1097a,a1101a,a1102a,a1106a,a1107a,a1111a,a1112a,a1116a,a1117a,a1121a,a1122a,a1126a,a1127a,a1131a,a1132a,a1136a,a1137a,a1141a,a1142a,a1146a,a1147a,a1151a,a1152a,a1156a,a1157a,a1161a,a1162a,a1166a,a1167a,a1171a,a1172a,a1176a,a1177a,a1181a,a1182a,a1185a,a1188a,a1189a,a1193a,a1194a,a1197a,a1200a,a1201a,a1205a,a1206a,a1209a,a1212a,a1213a,a1217a,a1218a,a1221a,a1224a,a1225a,a1229a,a1230a,a1233a,a1236a,a1237a,a1241a,a1242a,a1245a,a1248a,a1249a,a1253a,a1254a,a1257a,a1260a,a1261a,a1265a,a1266a,a1269a,a1272a,a1273a,a1277a,a1278a,a1281a,a1284a,a1285a,a1289a,a1290a,a1293a,a1296a,a1297a,a1301a,a1302a,a1305a,a1308a,a1309a,a1313a,a1314a,a1317a,a1320a,a1321a,a1325a,a1326a,a1329a,a1332a,a1333a,a1337a,a1338a,a1341a,a1344a,a1345a,a1349a,a1350a,a1353a,a1356a,a1357a,a1361a,a1362a,a1365a,a1368a,a1369a,a1373a,a1374a,a1377a,a1380a,a1381a,a1385a,a1386a,a1389a,a1392a,a1393a,a1397a,a1398a,a1401a,a1404a,a1405a,a1409a,a1410a,a1413a,a1416a,a1417a,a1421a,a1422a,a1425a,a1428a,a1429a,a1433a,a1434a,a1437a,a1440a,a1441a,a1445a,a1446a,a1449a,a1452a,a1453a,a1457a,a1458a,a1461a,a1464a,a1465a,a1469a,a1470a,a1473a,a1476a,a1477a,a1481a,a1482a,a1485a,a1488a,a1489a,a1493a,a1494a,a1497a,a1500a,a1501a,a1505a,a1506a,a1509a,a1512a,a1513a,a1517a,a1518a,a1521a,a1524a,a1525a,a1529a,a1530a,a1533a,a1536a,a1537a,a1541a,a1542a,a1545a,a1548a,a1549a,a1553a,a1554a,a1557a,a1560a,a1561a,a1565a,a1566a,a1569a,a1572a,a1573a,a1577a,a1578a,a1581a,a1584a,a1585a,a1589a,a1590a,a1593a,a1596a,a1597a,a1601a,a1602a,a1605a,a1608a,a1609a,a1613a,a1614a,a1617a,a1620a,a1621a,a1625a,a1626a,a1629a,a1632a,a1633a,a1637a,a1638a,a1641a,a1644a,a1645a,a1649a,a1650a,a1653a,a1656a,a1657a,a1660a,a1663a,a1664a,a1667a,a1670a,a1671a,a1674a,a1677a,a1678a,a1681a,a1684a,a1685a,a1688a,a1691a,a1692a,a1695a,a1698a,a1699a,a1702a,a1705a,a1706a,a1709a,a1712a,a1713a,a1716a,a1719a,a1720a,a1723a,a1726a,a1727a,a1730a,a1733a,a1734a,a1737a,a1740a,a1741a,a1744a,a1747a,a1748a,a1751a,a1754a,a1755a,a1758a,a1761a,a1762a,a1765a,a1768a,a1769a,a1772a,a1775a,a1776a,a1779a,a1782a,a1783a,a1786a,a1789a,a1790a,a1793a,a1796a,a1797a,a1800a,a1803a,a1804a,a1807a,a1810a,a1811a,a1814a,a1817a,a1818a,a1821a,a1824a,a1825a,a1828a,a1831a,a1832a,a1835a,a1838a,a1839a,a1842a,a1845a,a1846a,a1849a,a1852a,a1853a,a1856a,a1859a,a1860a,a1863a,a1866a,a1867a,a1870a,a1873a,a1874a,a1877a,a1880a,a1881a,a1884a,a1887a,a1888a,a1891a,a1894a,a1895a,a1898a,a1901a,a1902a,a1905a,a1908a,a1909a,a1912a,a1915a,a1916a,a1919a,a1922a,a1923a,a1926a,a1929a,a1930a,a1933a,a1936a,a1937a,a1940a,a1943a,a1944a,a1947a,a1950a,a1951a,a1954a,a1957a,a1958a,a1961a,a1964a,a1965a,a1968a,a1971a,a1972a,a1975a,a1978a,a1979a,a1982a,a1985a,a1986a,a1989a,a1992a,a1993a,a1996a,a1999a,a2000a,a2003a,a2006a,a2007a,a2010a,a2013a,a2014a,a2017a,a2020a,a2021a,a2024a,a2027a,a2028a,a2031a,a2034a,a2035a,a2038a,a2041a,a2042a,a2045a,a2048a,a2049a,a2052a,a2055a,a2056a,a2059a,a2062a,a2063a,a2066a,a2069a,a2070a,a2073a,a2076a,a2077a,a2080a,a2083a,a2084a,a2087a,a2090a,a2091a,a2094a,a2097a,a2098a,a2101a,a2104a,a2105a,a2108a,a2111a,a2112a,a2115a,a2118a,a2119a,a2122a,a2125a,a2126a,a2129a,a2132a,a2133a,a2136a,a2139a,a2140a,a2143a,a2146a,a2147a,a2150a,a2153a,a2154a,a2157a,a2160a,a2161a,a2164a,a2167a,a2168a,a2171a,a2174a,a2175a,a2178a,a2181a,a2182a,a2185a,a2188a,a2189a,a2192a,a2195a,a2196a,a2199a,a2202a,a2203a,a2206a,a2209a,a2210a,a2213a,a2216a,a2217a,a2220a,a2223a,a2224a,a2227a,a2230a,a2231a,a2234a,a2237a,a2238a,a2241a,a2244a,a2245a,a2248a,a2251a,a2252a,a2255a,a2258a,a2259a,a2262a,a2265a,a2266a,a2269a,a2272a,a2273a,a2276a,a2279a,a2280a,a2283a,a2286a,a2287a,a2290a,a2293a,a2294a,a2297a,a2300a,a2301a,a2304a,a2307a,a2308a,a2311a,a2314a,a2315a,a2318a,a2321a,a2322a,a2325a,a2328a,a2329a,a2332a,a2335a,a2336a,a2339a,a2343a,a2344a,a2345a,a2348a,a2351a,a2352a,a2355a,a2359a,a2360a,a2361a,a2364a,a2367a,a2368a,a2371a,a2375a,a2376a,a2377a,a2380a,a2383a,a2384a,a2387a,a2391a,a2392a,a2393a,a2396a,a2399a,a2400a,a2403a,a2407a,a2408a,a2409a,a2412a,a2415a,a2416a,a2419a,a2423a,a2424a,a2425a,a2428a,a2431a,a2432a,a2435a,a2439a,a2440a,a2441a,a2444a,a2447a,a2448a,a2451a,a2455a,a2456a,a2457a,a2460a,a2463a,a2464a,a2467a,a2471a,a2472a,a2473a,a2476a,a2479a,a2480a,a2483a,a2487a,a2488a,a2489a,a2492a,a2495a,a2496a,a2499a,a2503a,a2504a,a2505a,a2508a,a2511a,a2512a,a2515a,a2519a,a2520a,a2521a,a2524a,a2527a,a2528a,a2531a,a2535a,a2536a,a2537a,a2540a,a2543a,a2544a,a2547a,a2551a,a2552a,a2553a,a2556a,a2559a,a2560a,a2563a,a2567a,a2568a,a2569a,a2572a,a2575a,a2576a,a2579a,a2583a,a2584a,a2585a,a2588a,a2591a,a2592a,a2595a,a2599a,a2600a,a2601a,a2604a,a2607a,a2608a,a2611a,a2615a,a2616a,a2617a,a2620a,a2623a,a2624a,a2627a,a2631a,a2632a,a2633a,a2636a,a2639a,a2640a,a2643a,a2647a,a2648a,a2649a,a2652a,a2655a,a2656a,a2659a,a2663a,a2664a,a2665a,a2668a,a2671a,a2672a,a2675a,a2679a,a2680a,a2681a,a2684a,a2687a,a2688a,a2691a,a2695a,a2696a,a2697a,a2700a,a2703a,a2704a,a2707a,a2711a,a2712a,a2713a,a2716a,a2719a,a2720a,a2723a,a2727a,a2728a,a2729a,a2732a,a2735a,a2736a,a2739a,a2743a,a2744a,a2745a,a2748a,a2751a,a2752a,a2755a,a2759a,a2760a,a2761a,a2764a,a2767a,a2768a,a2771a,a2775a,a2776a,a2777a,a2780a,a2783a,a2784a,a2787a,a2791a,a2792a,a2793a,a2796a,a2799a,a2800a,a2803a,a2807a,a2808a,a2809a,a2812a,a2815a,a2816a,a2819a,a2823a,a2824a,a2825a,a2828a,a2831a,a2832a,a2835a,a2839a,a2840a,a2841a,a2844a,a2848a,a2849a,a2850a,a2853a,a2857a,a2858a,a2859a,a2862a,a2866a,a2867a,a2868a,a2871a,a2875a,a2876a,a2877a,a2880a,a2884a,a2885a,a2886a,a2889a,a2893a,a2894a,a2895a,a2898a,a2902a,a2903a,a2904a,a2907a,a2911a,a2912a,a2913a,a2916a,a2920a,a2921a,a2922a,a2925a,a2929a,a2930a,a2931a,a2934a,a2938a,a2939a,a2940a,a2943a,a2947a,a2948a,a2949a,a2952a,a2956a,a2957a,a2958a,a2961a,a2965a,a2966a,a2967a,a2970a,a2974a,a2975a,a2976a,a2979a,a2983a,a2984a,a2985a: std_logic;
begin
A74 <=( a613a ) or ( a408a );
a1a <=( a2985a and a2976a );
a2a <=( a2967a and a2958a );
a3a <=( a2949a and a2940a );
a4a <=( a2931a and a2922a );
a5a <=( a2913a and a2904a );
a6a <=( a2895a and a2886a );
a7a <=( a2877a and a2868a );
a8a <=( a2859a and a2850a );
a9a <=( a2841a and a2832a );
a10a <=( a2825a and a2816a );
a11a <=( a2809a and a2800a );
a12a <=( a2793a and a2784a );
a13a <=( a2777a and a2768a );
a14a <=( a2761a and a2752a );
a15a <=( a2745a and a2736a );
a16a <=( a2729a and a2720a );
a17a <=( a2713a and a2704a );
a18a <=( a2697a and a2688a );
a19a <=( a2681a and a2672a );
a20a <=( a2665a and a2656a );
a21a <=( a2649a and a2640a );
a22a <=( a2633a and a2624a );
a23a <=( a2617a and a2608a );
a24a <=( a2601a and a2592a );
a25a <=( a2585a and a2576a );
a26a <=( a2569a and a2560a );
a27a <=( a2553a and a2544a );
a28a <=( a2537a and a2528a );
a29a <=( a2521a and a2512a );
a30a <=( a2505a and a2496a );
a31a <=( a2489a and a2480a );
a32a <=( a2473a and a2464a );
a33a <=( a2457a and a2448a );
a34a <=( a2441a and a2432a );
a35a <=( a2425a and a2416a );
a36a <=( a2409a and a2400a );
a37a <=( a2393a and a2384a );
a38a <=( a2377a and a2368a );
a39a <=( a2361a and a2352a );
a40a <=( a2345a and a2336a );
a41a <=( a2329a and a2322a );
a42a <=( a2315a and a2308a );
a43a <=( a2301a and a2294a );
a44a <=( a2287a and a2280a );
a45a <=( a2273a and a2266a );
a46a <=( a2259a and a2252a );
a47a <=( a2245a and a2238a );
a48a <=( a2231a and a2224a );
a49a <=( a2217a and a2210a );
a50a <=( a2203a and a2196a );
a51a <=( a2189a and a2182a );
a52a <=( a2175a and a2168a );
a53a <=( a2161a and a2154a );
a54a <=( a2147a and a2140a );
a55a <=( a2133a and a2126a );
a56a <=( a2119a and a2112a );
a57a <=( a2105a and a2098a );
a58a <=( a2091a and a2084a );
a59a <=( a2077a and a2070a );
a60a <=( a2063a and a2056a );
a61a <=( a2049a and a2042a );
a62a <=( a2035a and a2028a );
a63a <=( a2021a and a2014a );
a64a <=( a2007a and a2000a );
a65a <=( a1993a and a1986a );
a66a <=( a1979a and a1972a );
a67a <=( a1965a and a1958a );
a68a <=( a1951a and a1944a );
a69a <=( a1937a and a1930a );
a70a <=( a1923a and a1916a );
a71a <=( a1909a and a1902a );
a72a <=( a1895a and a1888a );
a73a <=( a1881a and a1874a );
a74a <=( a1867a and a1860a );
a75a <=( a1853a and a1846a );
a76a <=( a1839a and a1832a );
a77a <=( a1825a and a1818a );
a78a <=( a1811a and a1804a );
a79a <=( a1797a and a1790a );
a80a <=( a1783a and a1776a );
a81a <=( a1769a and a1762a );
a82a <=( a1755a and a1748a );
a83a <=( a1741a and a1734a );
a84a <=( a1727a and a1720a );
a85a <=( a1713a and a1706a );
a86a <=( a1699a and a1692a );
a87a <=( a1685a and a1678a );
a88a <=( a1671a and a1664a );
a89a <=( a1657a and a1650a );
a90a <=( a1645a and a1638a );
a91a <=( a1633a and a1626a );
a92a <=( a1621a and a1614a );
a93a <=( a1609a and a1602a );
a94a <=( a1597a and a1590a );
a95a <=( a1585a and a1578a );
a96a <=( a1573a and a1566a );
a97a <=( a1561a and a1554a );
a98a <=( a1549a and a1542a );
a99a <=( a1537a and a1530a );
a100a <=( a1525a and a1518a );
a101a <=( a1513a and a1506a );
a102a <=( a1501a and a1494a );
a103a <=( a1489a and a1482a );
a104a <=( a1477a and a1470a );
a105a <=( a1465a and a1458a );
a106a <=( a1453a and a1446a );
a107a <=( a1441a and a1434a );
a108a <=( a1429a and a1422a );
a109a <=( a1417a and a1410a );
a110a <=( a1405a and a1398a );
a111a <=( a1393a and a1386a );
a112a <=( a1381a and a1374a );
a113a <=( a1369a and a1362a );
a114a <=( a1357a and a1350a );
a115a <=( a1345a and a1338a );
a116a <=( a1333a and a1326a );
a117a <=( a1321a and a1314a );
a118a <=( a1309a and a1302a );
a119a <=( a1297a and a1290a );
a120a <=( a1285a and a1278a );
a121a <=( a1273a and a1266a );
a122a <=( a1261a and a1254a );
a123a <=( a1249a and a1242a );
a124a <=( a1237a and a1230a );
a125a <=( a1225a and a1218a );
a126a <=( a1213a and a1206a );
a127a <=( a1201a and a1194a );
a128a <=( a1189a and a1182a );
a129a <=( a1177a and a1172a );
a130a <=( a1167a and a1162a );
a131a <=( a1157a and a1152a );
a132a <=( a1147a and a1142a );
a133a <=( a1137a and a1132a );
a134a <=( a1127a and a1122a );
a135a <=( a1117a and a1112a );
a136a <=( a1107a and a1102a );
a137a <=( a1097a and a1092a );
a138a <=( a1087a and a1082a );
a139a <=( a1077a and a1072a );
a140a <=( a1067a and a1062a );
a141a <=( a1057a and a1052a );
a142a <=( a1047a and a1042a );
a143a <=( a1037a and a1032a );
a144a <=( a1027a and a1022a );
a145a <=( a1017a and a1012a );
a146a <=( a1007a and a1002a );
a147a <=( a997a and a992a );
a148a <=( a987a and a982a );
a149a <=( a977a and a972a );
a150a <=( a967a and a962a );
a151a <=( a957a and a952a );
a152a <=( a947a and a942a );
a153a <=( a937a and a932a );
a154a <=( a927a and a922a );
a155a <=( a917a and a912a );
a156a <=( a909a and a904a );
a157a <=( a901a and a896a );
a158a <=( a893a and a888a );
a159a <=( a885a and a880a );
a160a <=( a877a and a872a );
a161a <=( a869a and a864a );
a162a <=( a861a and a856a );
a163a <=( a853a and a848a );
a164a <=( a845a and a840a );
a165a <=( a837a and a832a );
a166a <=( a829a and a824a );
a167a <=( a821a and a816a );
a168a <=( a813a and a808a );
a169a <=( a805a and a800a );
a170a <=( a797a and a792a );
a171a <=( a789a and a784a );
a172a <=( a781a and a776a );
a173a <=( a773a and a768a );
a174a <=( a765a and a760a );
a175a <=( a757a and a754a );
a176a <=( a751a and a748a );
a177a <=( a745a and a742a );
a178a <=( a739a and a736a );
a179a <=( a733a and a730a );
a180a <=( a727a and a724a );
a181a <=( a721a and a718a );
a182a <=( a715a and a712a );
a183a <=( a709a and a706a );
a184a <=( a703a and a700a );
a185a <=( a697a and a694a );
a186a <=( a691a and a688a );
a187a <=( a685a and a682a );
a188a <=( a679a and a676a );
a189a <=( a673a and a670a );
a190a <=( a667a and a664a );
a191a <=( A169 and a661a );
a192a <=( A169 and a657a );
a193a <=( A168 and a653a );
a194a <=( A168 and a649a );
a195a <=( A200 and a645a );
a196a <=( A199 and a641a );
a197a <=( A202 and a637a );
a198a <=( A202 and a633a );
a199a <=( A265 and a629a );
a200a <=( (not A265) and a625a );
a201a <=( A235 and A169 );
a202a <=( A235 and A202 );
a203a <=( A267 and A266 );
a204a <=( A267 and A265 );
a209a <=( a203a ) or ( a204a );
a210a <=( A268 ) or ( a209a );
a214a <=( a200a ) or ( a201a );
a215a <=( a202a ) or ( a214a );
a216a <=( a215a ) or ( a210a );
a220a <=( a197a ) or ( a198a );
a221a <=( a199a ) or ( a220a );
a225a <=( a194a ) or ( a195a );
a226a <=( a196a ) or ( a225a );
a227a <=( a226a ) or ( a221a );
a228a <=( a227a ) or ( a216a );
a232a <=( a191a ) or ( a192a );
a233a <=( a193a ) or ( a232a );
a237a <=( a188a ) or ( a189a );
a238a <=( a190a ) or ( a237a );
a239a <=( a238a ) or ( a233a );
a243a <=( a185a ) or ( a186a );
a244a <=( a187a ) or ( a243a );
a247a <=( a183a ) or ( a184a );
a250a <=( a181a ) or ( a182a );
a251a <=( a250a ) or ( a247a );
a252a <=( a251a ) or ( a244a );
a253a <=( a252a ) or ( a239a );
a254a <=( a253a ) or ( a228a );
a258a <=( a178a ) or ( a179a );
a259a <=( a180a ) or ( a258a );
a263a <=( a175a ) or ( a176a );
a264a <=( a177a ) or ( a263a );
a265a <=( a264a ) or ( a259a );
a269a <=( a172a ) or ( a173a );
a270a <=( a174a ) or ( a269a );
a273a <=( a170a ) or ( a171a );
a276a <=( a168a ) or ( a169a );
a277a <=( a276a ) or ( a273a );
a278a <=( a277a ) or ( a270a );
a279a <=( a278a ) or ( a265a );
a283a <=( a165a ) or ( a166a );
a284a <=( a167a ) or ( a283a );
a288a <=( a162a ) or ( a163a );
a289a <=( a164a ) or ( a288a );
a290a <=( a289a ) or ( a284a );
a294a <=( a159a ) or ( a160a );
a295a <=( a161a ) or ( a294a );
a298a <=( a157a ) or ( a158a );
a301a <=( a155a ) or ( a156a );
a302a <=( a301a ) or ( a298a );
a303a <=( a302a ) or ( a295a );
a304a <=( a303a ) or ( a290a );
a305a <=( a304a ) or ( a279a );
a306a <=( a305a ) or ( a254a );
a310a <=( a152a ) or ( a153a );
a311a <=( a154a ) or ( a310a );
a315a <=( a149a ) or ( a150a );
a316a <=( a151a ) or ( a315a );
a317a <=( a316a ) or ( a311a );
a321a <=( a146a ) or ( a147a );
a322a <=( a148a ) or ( a321a );
a326a <=( a143a ) or ( a144a );
a327a <=( a145a ) or ( a326a );
a328a <=( a327a ) or ( a322a );
a329a <=( a328a ) or ( a317a );
a333a <=( a140a ) or ( a141a );
a334a <=( a142a ) or ( a333a );
a338a <=( a137a ) or ( a138a );
a339a <=( a139a ) or ( a338a );
a340a <=( a339a ) or ( a334a );
a344a <=( a134a ) or ( a135a );
a345a <=( a136a ) or ( a344a );
a348a <=( a132a ) or ( a133a );
a351a <=( a130a ) or ( a131a );
a352a <=( a351a ) or ( a348a );
a353a <=( a352a ) or ( a345a );
a354a <=( a353a ) or ( a340a );
a355a <=( a354a ) or ( a329a );
a359a <=( a127a ) or ( a128a );
a360a <=( a129a ) or ( a359a );
a364a <=( a124a ) or ( a125a );
a365a <=( a126a ) or ( a364a );
a366a <=( a365a ) or ( a360a );
a370a <=( a121a ) or ( a122a );
a371a <=( a123a ) or ( a370a );
a374a <=( a119a ) or ( a120a );
a377a <=( a117a ) or ( a118a );
a378a <=( a377a ) or ( a374a );
a379a <=( a378a ) or ( a371a );
a380a <=( a379a ) or ( a366a );
a384a <=( a114a ) or ( a115a );
a385a <=( a116a ) or ( a384a );
a389a <=( a111a ) or ( a112a );
a390a <=( a113a ) or ( a389a );
a391a <=( a390a ) or ( a385a );
a395a <=( a108a ) or ( a109a );
a396a <=( a110a ) or ( a395a );
a399a <=( a106a ) or ( a107a );
a402a <=( a104a ) or ( a105a );
a403a <=( a402a ) or ( a399a );
a404a <=( a403a ) or ( a396a );
a405a <=( a404a ) or ( a391a );
a406a <=( a405a ) or ( a380a );
a407a <=( a406a ) or ( a355a );
a408a <=( a407a ) or ( a306a );
a412a <=( a101a ) or ( a102a );
a413a <=( a103a ) or ( a412a );
a417a <=( a98a ) or ( a99a );
a418a <=( a100a ) or ( a417a );
a419a <=( a418a ) or ( a413a );
a423a <=( a95a ) or ( a96a );
a424a <=( a97a ) or ( a423a );
a428a <=( a92a ) or ( a93a );
a429a <=( a94a ) or ( a428a );
a430a <=( a429a ) or ( a424a );
a431a <=( a430a ) or ( a419a );
a435a <=( a89a ) or ( a90a );
a436a <=( a91a ) or ( a435a );
a440a <=( a86a ) or ( a87a );
a441a <=( a88a ) or ( a440a );
a442a <=( a441a ) or ( a436a );
a446a <=( a83a ) or ( a84a );
a447a <=( a85a ) or ( a446a );
a450a <=( a81a ) or ( a82a );
a453a <=( a79a ) or ( a80a );
a454a <=( a453a ) or ( a450a );
a455a <=( a454a ) or ( a447a );
a456a <=( a455a ) or ( a442a );
a457a <=( a456a ) or ( a431a );
a461a <=( a76a ) or ( a77a );
a462a <=( a78a ) or ( a461a );
a466a <=( a73a ) or ( a74a );
a467a <=( a75a ) or ( a466a );
a468a <=( a467a ) or ( a462a );
a472a <=( a70a ) or ( a71a );
a473a <=( a72a ) or ( a472a );
a476a <=( a68a ) or ( a69a );
a479a <=( a66a ) or ( a67a );
a480a <=( a479a ) or ( a476a );
a481a <=( a480a ) or ( a473a );
a482a <=( a481a ) or ( a468a );
a486a <=( a63a ) or ( a64a );
a487a <=( a65a ) or ( a486a );
a491a <=( a60a ) or ( a61a );
a492a <=( a62a ) or ( a491a );
a493a <=( a492a ) or ( a487a );
a497a <=( a57a ) or ( a58a );
a498a <=( a59a ) or ( a497a );
a501a <=( a55a ) or ( a56a );
a504a <=( a53a ) or ( a54a );
a505a <=( a504a ) or ( a501a );
a506a <=( a505a ) or ( a498a );
a507a <=( a506a ) or ( a493a );
a508a <=( a507a ) or ( a482a );
a509a <=( a508a ) or ( a457a );
a513a <=( a50a ) or ( a51a );
a514a <=( a52a ) or ( a513a );
a518a <=( a47a ) or ( a48a );
a519a <=( a49a ) or ( a518a );
a520a <=( a519a ) or ( a514a );
a524a <=( a44a ) or ( a45a );
a525a <=( a46a ) or ( a524a );
a528a <=( a42a ) or ( a43a );
a531a <=( a40a ) or ( a41a );
a532a <=( a531a ) or ( a528a );
a533a <=( a532a ) or ( a525a );
a534a <=( a533a ) or ( a520a );
a538a <=( a37a ) or ( a38a );
a539a <=( a39a ) or ( a538a );
a543a <=( a34a ) or ( a35a );
a544a <=( a36a ) or ( a543a );
a545a <=( a544a ) or ( a539a );
a549a <=( a31a ) or ( a32a );
a550a <=( a33a ) or ( a549a );
a553a <=( a29a ) or ( a30a );
a556a <=( a27a ) or ( a28a );
a557a <=( a556a ) or ( a553a );
a558a <=( a557a ) or ( a550a );
a559a <=( a558a ) or ( a545a );
a560a <=( a559a ) or ( a534a );
a564a <=( a24a ) or ( a25a );
a565a <=( a26a ) or ( a564a );
a569a <=( a21a ) or ( a22a );
a570a <=( a23a ) or ( a569a );
a571a <=( a570a ) or ( a565a );
a575a <=( a18a ) or ( a19a );
a576a <=( a20a ) or ( a575a );
a579a <=( a16a ) or ( a17a );
a582a <=( a14a ) or ( a15a );
a583a <=( a582a ) or ( a579a );
a584a <=( a583a ) or ( a576a );
a585a <=( a584a ) or ( a571a );
a589a <=( a11a ) or ( a12a );
a590a <=( a13a ) or ( a589a );
a594a <=( a8a ) or ( a9a );
a595a <=( a10a ) or ( a594a );
a596a <=( a595a ) or ( a590a );
a600a <=( a5a ) or ( a6a );
a601a <=( a7a ) or ( a600a );
a604a <=( a3a ) or ( a4a );
a607a <=( a1a ) or ( a2a );
a608a <=( a607a ) or ( a604a );
a609a <=( a608a ) or ( a601a );
a610a <=( a609a ) or ( a596a );
a611a <=( a610a ) or ( a585a );
a612a <=( a611a ) or ( a560a );
a613a <=( a612a ) or ( a509a );
a625a <=( A269 and A266 );
a629a <=( A269 and (not A266) );
a633a <=( A234 and A232 );
a637a <=( A234 and A233 );
a641a <=( A235 and A201 );
a645a <=( A235 and A201 );
a649a <=( A235 and A166 );
a653a <=( A235 and A167 );
a657a <=( A234 and A232 );
a661a <=( A234 and A233 );
a664a <=( (not A232) and A202 );
a667a <=( A236 and A233 );
a670a <=( A232 and A202 );
a673a <=( A236 and (not A233) );
a676a <=( A201 and A199 );
a679a <=( A234 and A232 );
a682a <=( A201 and A199 );
a685a <=( A234 and A233 );
a688a <=( A201 and A200 );
a691a <=( A234 and A232 );
a694a <=( A201 and A200 );
a697a <=( A234 and A233 );
a700a <=( A200 and (not A199) );
a703a <=( A235 and A203 );
a706a <=( (not A200) and A199 );
a709a <=( A235 and A203 );
a712a <=( A166 and A168 );
a715a <=( A234 and A232 );
a718a <=( A166 and A168 );
a721a <=( A234 and A233 );
a724a <=( A167 and A168 );
a727a <=( A234 and A232 );
a730a <=( A167 and A168 );
a733a <=( A234 and A233 );
a736a <=( A167 and A170 );
a739a <=( A235 and (not A166) );
a742a <=( (not A167) and A170 );
a745a <=( A235 and A166 );
a748a <=( (not A232) and A169 );
a751a <=( A236 and A233 );
a754a <=( A232 and A169 );
a757a <=( A236 and (not A233) );
a760a <=( A201 and A199 );
a764a <=( A236 and A233 );
a765a <=( (not A232) and a764a );
a768a <=( A201 and A199 );
a772a <=( A236 and (not A233) );
a773a <=( A232 and a772a );
a776a <=( A201 and A200 );
a780a <=( A236 and A233 );
a781a <=( (not A232) and a780a );
a784a <=( A201 and A200 );
a788a <=( A236 and (not A233) );
a789a <=( A232 and a788a );
a792a <=( A200 and (not A199) );
a796a <=( A234 and A232 );
a797a <=( A203 and a796a );
a800a <=( A200 and (not A199) );
a804a <=( A234 and A233 );
a805a <=( A203 and a804a );
a808a <=( (not A200) and A199 );
a812a <=( A234 and A232 );
a813a <=( A203 and a812a );
a816a <=( (not A200) and A199 );
a820a <=( A234 and A233 );
a821a <=( A203 and a820a );
a824a <=( A166 and A168 );
a828a <=( A236 and A233 );
a829a <=( (not A232) and a828a );
a832a <=( A166 and A168 );
a836a <=( A236 and (not A233) );
a837a <=( A232 and a836a );
a840a <=( A167 and A168 );
a844a <=( A236 and A233 );
a845a <=( (not A232) and a844a );
a848a <=( A167 and A168 );
a852a <=( A236 and (not A233) );
a853a <=( A232 and a852a );
a856a <=( A167 and A170 );
a860a <=( A234 and A232 );
a861a <=( (not A166) and a860a );
a864a <=( A167 and A170 );
a868a <=( A234 and A233 );
a869a <=( (not A166) and a868a );
a872a <=( (not A167) and A170 );
a876a <=( A234 and A232 );
a877a <=( A166 and a876a );
a880a <=( (not A167) and A170 );
a884a <=( A234 and A233 );
a885a <=( A166 and a884a );
a888a <=( (not A201) and A169 );
a892a <=( A301 and (not A203) );
a893a <=( (not A202) and a892a );
a896a <=( (not A199) and A169 );
a900a <=( A301 and (not A202) );
a901a <=( (not A200) and a900a );
a904a <=( (not A167) and (not A169) );
a908a <=( A301 and A202 );
a909a <=( (not A166) and a908a );
a912a <=( (not A169) and (not A170) );
a916a <=( A301 and A202 );
a917a <=( (not A168) and a916a );
a921a <=( A203 and A200 );
a922a <=( (not A199) and a921a );
a926a <=( A236 and A233 );
a927a <=( (not A232) and a926a );
a931a <=( A203 and A200 );
a932a <=( (not A199) and a931a );
a936a <=( A236 and (not A233) );
a937a <=( A232 and a936a );
a941a <=( A203 and (not A200) );
a942a <=( A199 and a941a );
a946a <=( A236 and A233 );
a947a <=( (not A232) and a946a );
a951a <=( A203 and (not A200) );
a952a <=( A199 and a951a );
a956a <=( A236 and (not A233) );
a957a <=( A232 and a956a );
a961a <=( (not A201) and A166 );
a962a <=( A168 and a961a );
a966a <=( A301 and (not A203) );
a967a <=( (not A202) and a966a );
a971a <=( (not A199) and A166 );
a972a <=( A168 and a971a );
a976a <=( A301 and (not A202) );
a977a <=( (not A200) and a976a );
a981a <=( (not A201) and A167 );
a982a <=( A168 and a981a );
a986a <=( A301 and (not A203) );
a987a <=( (not A202) and a986a );
a991a <=( (not A199) and A167 );
a992a <=( A168 and a991a );
a996a <=( A301 and (not A202) );
a997a <=( (not A200) and a996a );
a1001a <=( (not A166) and A167 );
a1002a <=( A170 and a1001a );
a1006a <=( A236 and A233 );
a1007a <=( (not A232) and a1006a );
a1011a <=( (not A166) and A167 );
a1012a <=( A170 and a1011a );
a1016a <=( A236 and (not A233) );
a1017a <=( A232 and a1016a );
a1021a <=( A166 and (not A167) );
a1022a <=( A170 and a1021a );
a1026a <=( A236 and A233 );
a1027a <=( (not A232) and a1026a );
a1031a <=( A166 and (not A167) );
a1032a <=( A170 and a1031a );
a1036a <=( A236 and (not A233) );
a1037a <=( A232 and a1036a );
a1041a <=( (not A202) and (not A201) );
a1042a <=( A169 and a1041a );
a1046a <=( A300 and A299 );
a1047a <=( (not A203) and a1046a );
a1051a <=( (not A202) and (not A201) );
a1052a <=( A169 and a1051a );
a1056a <=( A300 and A298 );
a1057a <=( (not A203) and a1056a );
a1061a <=( A200 and A199 );
a1062a <=( A169 and a1061a );
a1066a <=( A301 and (not A202) );
a1067a <=( (not A201) and a1066a );
a1071a <=( (not A200) and (not A199) );
a1072a <=( A169 and a1071a );
a1076a <=( A300 and A299 );
a1077a <=( (not A202) and a1076a );
a1081a <=( (not A200) and (not A199) );
a1082a <=( A169 and a1081a );
a1086a <=( A300 and A298 );
a1087a <=( (not A202) and a1086a );
a1091a <=( (not A166) and (not A167) );
a1092a <=( (not A169) and a1091a );
a1096a <=( A300 and A299 );
a1097a <=( A202 and a1096a );
a1101a <=( (not A166) and (not A167) );
a1102a <=( (not A169) and a1101a );
a1106a <=( A300 and A298 );
a1107a <=( A202 and a1106a );
a1111a <=( (not A166) and (not A167) );
a1112a <=( (not A169) and a1111a );
a1116a <=( A301 and A201 );
a1117a <=( A199 and a1116a );
a1121a <=( (not A166) and (not A167) );
a1122a <=( (not A169) and a1121a );
a1126a <=( A301 and A201 );
a1127a <=( A200 and a1126a );
a1131a <=( A167 and (not A168) );
a1132a <=( (not A169) and a1131a );
a1136a <=( A301 and A202 );
a1137a <=( A166 and a1136a );
a1141a <=( (not A168) and (not A169) );
a1142a <=( (not A170) and a1141a );
a1146a <=( A300 and A299 );
a1147a <=( A202 and a1146a );
a1151a <=( (not A168) and (not A169) );
a1152a <=( (not A170) and a1151a );
a1156a <=( A300 and A298 );
a1157a <=( A202 and a1156a );
a1161a <=( (not A168) and (not A169) );
a1162a <=( (not A170) and a1161a );
a1166a <=( A301 and A201 );
a1167a <=( A199 and a1166a );
a1171a <=( (not A168) and (not A169) );
a1172a <=( (not A170) and a1171a );
a1176a <=( A301 and A201 );
a1177a <=( A200 and a1176a );
a1181a <=( (not A201) and A166 );
a1182a <=( A168 and a1181a );
a1185a <=( (not A203) and (not A202) );
a1188a <=( A300 and A299 );
a1189a <=( a1188a and a1185a );
a1193a <=( (not A201) and A166 );
a1194a <=( A168 and a1193a );
a1197a <=( (not A203) and (not A202) );
a1200a <=( A300 and A298 );
a1201a <=( a1200a and a1197a );
a1205a <=( A199 and A166 );
a1206a <=( A168 and a1205a );
a1209a <=( (not A201) and A200 );
a1212a <=( A301 and (not A202) );
a1213a <=( a1212a and a1209a );
a1217a <=( (not A199) and A166 );
a1218a <=( A168 and a1217a );
a1221a <=( (not A202) and (not A200) );
a1224a <=( A300 and A299 );
a1225a <=( a1224a and a1221a );
a1229a <=( (not A199) and A166 );
a1230a <=( A168 and a1229a );
a1233a <=( (not A202) and (not A200) );
a1236a <=( A300 and A298 );
a1237a <=( a1236a and a1233a );
a1241a <=( (not A201) and A167 );
a1242a <=( A168 and a1241a );
a1245a <=( (not A203) and (not A202) );
a1248a <=( A300 and A299 );
a1249a <=( a1248a and a1245a );
a1253a <=( (not A201) and A167 );
a1254a <=( A168 and a1253a );
a1257a <=( (not A203) and (not A202) );
a1260a <=( A300 and A298 );
a1261a <=( a1260a and a1257a );
a1265a <=( A199 and A167 );
a1266a <=( A168 and a1265a );
a1269a <=( (not A201) and A200 );
a1272a <=( A301 and (not A202) );
a1273a <=( a1272a and a1269a );
a1277a <=( (not A199) and A167 );
a1278a <=( A168 and a1277a );
a1281a <=( (not A202) and (not A200) );
a1284a <=( A300 and A299 );
a1285a <=( a1284a and a1281a );
a1289a <=( (not A199) and A167 );
a1290a <=( A168 and a1289a );
a1293a <=( (not A202) and (not A200) );
a1296a <=( A300 and A298 );
a1297a <=( a1296a and a1293a );
a1301a <=( (not A166) and A167 );
a1302a <=( A170 and a1301a );
a1305a <=( (not A202) and (not A201) );
a1308a <=( A301 and (not A203) );
a1309a <=( a1308a and a1305a );
a1313a <=( (not A166) and A167 );
a1314a <=( A170 and a1313a );
a1317a <=( (not A200) and (not A199) );
a1320a <=( A301 and (not A202) );
a1321a <=( a1320a and a1317a );
a1325a <=( A166 and (not A167) );
a1326a <=( A170 and a1325a );
a1329a <=( (not A202) and (not A201) );
a1332a <=( A301 and (not A203) );
a1333a <=( a1332a and a1329a );
a1337a <=( A166 and (not A167) );
a1338a <=( A170 and a1337a );
a1341a <=( (not A200) and (not A199) );
a1344a <=( A301 and (not A202) );
a1345a <=( a1344a and a1341a );
a1349a <=( (not A202) and (not A201) );
a1350a <=( A169 and a1349a );
a1353a <=( A298 and (not A203) );
a1356a <=( A302 and (not A299) );
a1357a <=( a1356a and a1353a );
a1361a <=( (not A202) and (not A201) );
a1362a <=( A169 and a1361a );
a1365a <=( (not A298) and (not A203) );
a1368a <=( A302 and A299 );
a1369a <=( a1368a and a1365a );
a1373a <=( A200 and A199 );
a1374a <=( A169 and a1373a );
a1377a <=( (not A202) and (not A201) );
a1380a <=( A300 and A299 );
a1381a <=( a1380a and a1377a );
a1385a <=( A200 and A199 );
a1386a <=( A169 and a1385a );
a1389a <=( (not A202) and (not A201) );
a1392a <=( A300 and A298 );
a1393a <=( a1392a and a1389a );
a1397a <=( (not A200) and (not A199) );
a1398a <=( A169 and a1397a );
a1401a <=( A298 and (not A202) );
a1404a <=( A302 and (not A299) );
a1405a <=( a1404a and a1401a );
a1409a <=( (not A200) and (not A199) );
a1410a <=( A169 and a1409a );
a1413a <=( (not A298) and (not A202) );
a1416a <=( A302 and A299 );
a1417a <=( a1416a and a1413a );
a1421a <=( (not A166) and (not A167) );
a1422a <=( (not A169) and a1421a );
a1425a <=( A298 and A202 );
a1428a <=( A302 and (not A299) );
a1429a <=( a1428a and a1425a );
a1433a <=( (not A166) and (not A167) );
a1434a <=( (not A169) and a1433a );
a1437a <=( (not A298) and A202 );
a1440a <=( A302 and A299 );
a1441a <=( a1440a and a1437a );
a1445a <=( (not A166) and (not A167) );
a1446a <=( (not A169) and a1445a );
a1449a <=( A201 and A199 );
a1452a <=( A300 and A299 );
a1453a <=( a1452a and a1449a );
a1457a <=( (not A166) and (not A167) );
a1458a <=( (not A169) and a1457a );
a1461a <=( A201 and A199 );
a1464a <=( A300 and A298 );
a1465a <=( a1464a and a1461a );
a1469a <=( (not A166) and (not A167) );
a1470a <=( (not A169) and a1469a );
a1473a <=( A201 and A200 );
a1476a <=( A300 and A299 );
a1477a <=( a1476a and a1473a );
a1481a <=( (not A166) and (not A167) );
a1482a <=( (not A169) and a1481a );
a1485a <=( A201 and A200 );
a1488a <=( A300 and A298 );
a1489a <=( a1488a and a1485a );
a1493a <=( (not A166) and (not A167) );
a1494a <=( (not A169) and a1493a );
a1497a <=( A200 and (not A199) );
a1500a <=( A301 and A203 );
a1501a <=( a1500a and a1497a );
a1505a <=( (not A166) and (not A167) );
a1506a <=( (not A169) and a1505a );
a1509a <=( (not A200) and A199 );
a1512a <=( A301 and A203 );
a1513a <=( a1512a and a1509a );
a1517a <=( A167 and (not A168) );
a1518a <=( (not A169) and a1517a );
a1521a <=( A202 and A166 );
a1524a <=( A300 and A299 );
a1525a <=( a1524a and a1521a );
a1529a <=( A167 and (not A168) );
a1530a <=( (not A169) and a1529a );
a1533a <=( A202 and A166 );
a1536a <=( A300 and A298 );
a1537a <=( a1536a and a1533a );
a1541a <=( A167 and (not A168) );
a1542a <=( (not A169) and a1541a );
a1545a <=( A199 and A166 );
a1548a <=( A301 and A201 );
a1549a <=( a1548a and a1545a );
a1553a <=( A167 and (not A168) );
a1554a <=( (not A169) and a1553a );
a1557a <=( A200 and A166 );
a1560a <=( A301 and A201 );
a1561a <=( a1560a and a1557a );
a1565a <=( (not A168) and (not A169) );
a1566a <=( (not A170) and a1565a );
a1569a <=( A298 and A202 );
a1572a <=( A302 and (not A299) );
a1573a <=( a1572a and a1569a );
a1577a <=( (not A168) and (not A169) );
a1578a <=( (not A170) and a1577a );
a1581a <=( (not A298) and A202 );
a1584a <=( A302 and A299 );
a1585a <=( a1584a and a1581a );
a1589a <=( (not A168) and (not A169) );
a1590a <=( (not A170) and a1589a );
a1593a <=( A201 and A199 );
a1596a <=( A300 and A299 );
a1597a <=( a1596a and a1593a );
a1601a <=( (not A168) and (not A169) );
a1602a <=( (not A170) and a1601a );
a1605a <=( A201 and A199 );
a1608a <=( A300 and A298 );
a1609a <=( a1608a and a1605a );
a1613a <=( (not A168) and (not A169) );
a1614a <=( (not A170) and a1613a );
a1617a <=( A201 and A200 );
a1620a <=( A300 and A299 );
a1621a <=( a1620a and a1617a );
a1625a <=( (not A168) and (not A169) );
a1626a <=( (not A170) and a1625a );
a1629a <=( A201 and A200 );
a1632a <=( A300 and A298 );
a1633a <=( a1632a and a1629a );
a1637a <=( (not A168) and (not A169) );
a1638a <=( (not A170) and a1637a );
a1641a <=( A200 and (not A199) );
a1644a <=( A301 and A203 );
a1645a <=( a1644a and a1641a );
a1649a <=( (not A168) and (not A169) );
a1650a <=( (not A170) and a1649a );
a1653a <=( (not A200) and A199 );
a1656a <=( A301 and A203 );
a1657a <=( a1656a and a1653a );
a1660a <=( A166 and A168 );
a1663a <=( (not A202) and (not A201) );
a1664a <=( a1663a and a1660a );
a1667a <=( A298 and (not A203) );
a1670a <=( A302 and (not A299) );
a1671a <=( a1670a and a1667a );
a1674a <=( A166 and A168 );
a1677a <=( (not A202) and (not A201) );
a1678a <=( a1677a and a1674a );
a1681a <=( (not A298) and (not A203) );
a1684a <=( A302 and A299 );
a1685a <=( a1684a and a1681a );
a1688a <=( A166 and A168 );
a1691a <=( A200 and A199 );
a1692a <=( a1691a and a1688a );
a1695a <=( (not A202) and (not A201) );
a1698a <=( A300 and A299 );
a1699a <=( a1698a and a1695a );
a1702a <=( A166 and A168 );
a1705a <=( A200 and A199 );
a1706a <=( a1705a and a1702a );
a1709a <=( (not A202) and (not A201) );
a1712a <=( A300 and A298 );
a1713a <=( a1712a and a1709a );
a1716a <=( A166 and A168 );
a1719a <=( (not A200) and (not A199) );
a1720a <=( a1719a and a1716a );
a1723a <=( A298 and (not A202) );
a1726a <=( A302 and (not A299) );
a1727a <=( a1726a and a1723a );
a1730a <=( A166 and A168 );
a1733a <=( (not A200) and (not A199) );
a1734a <=( a1733a and a1730a );
a1737a <=( (not A298) and (not A202) );
a1740a <=( A302 and A299 );
a1741a <=( a1740a and a1737a );
a1744a <=( A167 and A168 );
a1747a <=( (not A202) and (not A201) );
a1748a <=( a1747a and a1744a );
a1751a <=( A298 and (not A203) );
a1754a <=( A302 and (not A299) );
a1755a <=( a1754a and a1751a );
a1758a <=( A167 and A168 );
a1761a <=( (not A202) and (not A201) );
a1762a <=( a1761a and a1758a );
a1765a <=( (not A298) and (not A203) );
a1768a <=( A302 and A299 );
a1769a <=( a1768a and a1765a );
a1772a <=( A167 and A168 );
a1775a <=( A200 and A199 );
a1776a <=( a1775a and a1772a );
a1779a <=( (not A202) and (not A201) );
a1782a <=( A300 and A299 );
a1783a <=( a1782a and a1779a );
a1786a <=( A167 and A168 );
a1789a <=( A200 and A199 );
a1790a <=( a1789a and a1786a );
a1793a <=( (not A202) and (not A201) );
a1796a <=( A300 and A298 );
a1797a <=( a1796a and a1793a );
a1800a <=( A167 and A168 );
a1803a <=( (not A200) and (not A199) );
a1804a <=( a1803a and a1800a );
a1807a <=( A298 and (not A202) );
a1810a <=( A302 and (not A299) );
a1811a <=( a1810a and a1807a );
a1814a <=( A167 and A168 );
a1817a <=( (not A200) and (not A199) );
a1818a <=( a1817a and a1814a );
a1821a <=( (not A298) and (not A202) );
a1824a <=( A302 and A299 );
a1825a <=( a1824a and a1821a );
a1828a <=( A167 and A170 );
a1831a <=( (not A201) and (not A166) );
a1832a <=( a1831a and a1828a );
a1835a <=( (not A203) and (not A202) );
a1838a <=( A300 and A299 );
a1839a <=( a1838a and a1835a );
a1842a <=( A167 and A170 );
a1845a <=( (not A201) and (not A166) );
a1846a <=( a1845a and a1842a );
a1849a <=( (not A203) and (not A202) );
a1852a <=( A300 and A298 );
a1853a <=( a1852a and a1849a );
a1856a <=( A167 and A170 );
a1859a <=( A199 and (not A166) );
a1860a <=( a1859a and a1856a );
a1863a <=( (not A201) and A200 );
a1866a <=( A301 and (not A202) );
a1867a <=( a1866a and a1863a );
a1870a <=( A167 and A170 );
a1873a <=( (not A199) and (not A166) );
a1874a <=( a1873a and a1870a );
a1877a <=( (not A202) and (not A200) );
a1880a <=( A300 and A299 );
a1881a <=( a1880a and a1877a );
a1884a <=( A167 and A170 );
a1887a <=( (not A199) and (not A166) );
a1888a <=( a1887a and a1884a );
a1891a <=( (not A202) and (not A200) );
a1894a <=( A300 and A298 );
a1895a <=( a1894a and a1891a );
a1898a <=( (not A167) and A170 );
a1901a <=( (not A201) and A166 );
a1902a <=( a1901a and a1898a );
a1905a <=( (not A203) and (not A202) );
a1908a <=( A300 and A299 );
a1909a <=( a1908a and a1905a );
a1912a <=( (not A167) and A170 );
a1915a <=( (not A201) and A166 );
a1916a <=( a1915a and a1912a );
a1919a <=( (not A203) and (not A202) );
a1922a <=( A300 and A298 );
a1923a <=( a1922a and a1919a );
a1926a <=( (not A167) and A170 );
a1929a <=( A199 and A166 );
a1930a <=( a1929a and a1926a );
a1933a <=( (not A201) and A200 );
a1936a <=( A301 and (not A202) );
a1937a <=( a1936a and a1933a );
a1940a <=( (not A167) and A170 );
a1943a <=( (not A199) and A166 );
a1944a <=( a1943a and a1940a );
a1947a <=( (not A202) and (not A200) );
a1950a <=( A300 and A299 );
a1951a <=( a1950a and a1947a );
a1954a <=( (not A167) and A170 );
a1957a <=( (not A199) and A166 );
a1958a <=( a1957a and a1954a );
a1961a <=( (not A202) and (not A200) );
a1964a <=( A300 and A298 );
a1965a <=( a1964a and a1961a );
a1968a <=( A199 and A169 );
a1971a <=( (not A201) and A200 );
a1972a <=( a1971a and a1968a );
a1975a <=( A298 and (not A202) );
a1978a <=( A302 and (not A299) );
a1979a <=( a1978a and a1975a );
a1982a <=( A199 and A169 );
a1985a <=( (not A201) and A200 );
a1986a <=( a1985a and a1982a );
a1989a <=( (not A298) and (not A202) );
a1992a <=( A302 and A299 );
a1993a <=( a1992a and a1989a );
a1996a <=( (not A167) and (not A169) );
a1999a <=( A199 and (not A166) );
a2000a <=( a1999a and a1996a );
a2003a <=( A298 and A201 );
a2006a <=( A302 and (not A299) );
a2007a <=( a2006a and a2003a );
a2010a <=( (not A167) and (not A169) );
a2013a <=( A199 and (not A166) );
a2014a <=( a2013a and a2010a );
a2017a <=( (not A298) and A201 );
a2020a <=( A302 and A299 );
a2021a <=( a2020a and a2017a );
a2024a <=( (not A167) and (not A169) );
a2027a <=( A200 and (not A166) );
a2028a <=( a2027a and a2024a );
a2031a <=( A298 and A201 );
a2034a <=( A302 and (not A299) );
a2035a <=( a2034a and a2031a );
a2038a <=( (not A167) and (not A169) );
a2041a <=( A200 and (not A166) );
a2042a <=( a2041a and a2038a );
a2045a <=( (not A298) and A201 );
a2048a <=( A302 and A299 );
a2049a <=( a2048a and a2045a );
a2052a <=( (not A167) and (not A169) );
a2055a <=( (not A199) and (not A166) );
a2056a <=( a2055a and a2052a );
a2059a <=( A203 and A200 );
a2062a <=( A300 and A299 );
a2063a <=( a2062a and a2059a );
a2066a <=( (not A167) and (not A169) );
a2069a <=( (not A199) and (not A166) );
a2070a <=( a2069a and a2066a );
a2073a <=( A203 and A200 );
a2076a <=( A300 and A298 );
a2077a <=( a2076a and a2073a );
a2080a <=( (not A167) and (not A169) );
a2083a <=( A199 and (not A166) );
a2084a <=( a2083a and a2080a );
a2087a <=( A203 and (not A200) );
a2090a <=( A300 and A299 );
a2091a <=( a2090a and a2087a );
a2094a <=( (not A167) and (not A169) );
a2097a <=( A199 and (not A166) );
a2098a <=( a2097a and a2094a );
a2101a <=( A203 and (not A200) );
a2104a <=( A300 and A298 );
a2105a <=( a2104a and a2101a );
a2108a <=( (not A168) and (not A169) );
a2111a <=( A166 and A167 );
a2112a <=( a2111a and a2108a );
a2115a <=( A298 and A202 );
a2118a <=( A302 and (not A299) );
a2119a <=( a2118a and a2115a );
a2122a <=( (not A168) and (not A169) );
a2125a <=( A166 and A167 );
a2126a <=( a2125a and a2122a );
a2129a <=( (not A298) and A202 );
a2132a <=( A302 and A299 );
a2133a <=( a2132a and a2129a );
a2136a <=( (not A168) and (not A169) );
a2139a <=( A166 and A167 );
a2140a <=( a2139a and a2136a );
a2143a <=( A201 and A199 );
a2146a <=( A300 and A299 );
a2147a <=( a2146a and a2143a );
a2150a <=( (not A168) and (not A169) );
a2153a <=( A166 and A167 );
a2154a <=( a2153a and a2150a );
a2157a <=( A201 and A199 );
a2160a <=( A300 and A298 );
a2161a <=( a2160a and a2157a );
a2164a <=( (not A168) and (not A169) );
a2167a <=( A166 and A167 );
a2168a <=( a2167a and a2164a );
a2171a <=( A201 and A200 );
a2174a <=( A300 and A299 );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A168) and (not A169) );
a2181a <=( A166 and A167 );
a2182a <=( a2181a and a2178a );
a2185a <=( A201 and A200 );
a2188a <=( A300 and A298 );
a2189a <=( a2188a and a2185a );
a2192a <=( (not A168) and (not A169) );
a2195a <=( A166 and A167 );
a2196a <=( a2195a and a2192a );
a2199a <=( A200 and (not A199) );
a2202a <=( A301 and A203 );
a2203a <=( a2202a and a2199a );
a2206a <=( (not A168) and (not A169) );
a2209a <=( A166 and A167 );
a2210a <=( a2209a and a2206a );
a2213a <=( (not A200) and A199 );
a2216a <=( A301 and A203 );
a2217a <=( a2216a and a2213a );
a2220a <=( (not A169) and (not A170) );
a2223a <=( A199 and (not A168) );
a2224a <=( a2223a and a2220a );
a2227a <=( A298 and A201 );
a2230a <=( A302 and (not A299) );
a2231a <=( a2230a and a2227a );
a2234a <=( (not A169) and (not A170) );
a2237a <=( A199 and (not A168) );
a2238a <=( a2237a and a2234a );
a2241a <=( (not A298) and A201 );
a2244a <=( A302 and A299 );
a2245a <=( a2244a and a2241a );
a2248a <=( (not A169) and (not A170) );
a2251a <=( A200 and (not A168) );
a2252a <=( a2251a and a2248a );
a2255a <=( A298 and A201 );
a2258a <=( A302 and (not A299) );
a2259a <=( a2258a and a2255a );
a2262a <=( (not A169) and (not A170) );
a2265a <=( A200 and (not A168) );
a2266a <=( a2265a and a2262a );
a2269a <=( (not A298) and A201 );
a2272a <=( A302 and A299 );
a2273a <=( a2272a and a2269a );
a2276a <=( (not A169) and (not A170) );
a2279a <=( (not A199) and (not A168) );
a2280a <=( a2279a and a2276a );
a2283a <=( A203 and A200 );
a2286a <=( A300 and A299 );
a2287a <=( a2286a and a2283a );
a2290a <=( (not A169) and (not A170) );
a2293a <=( (not A199) and (not A168) );
a2294a <=( a2293a and a2290a );
a2297a <=( A203 and A200 );
a2300a <=( A300 and A298 );
a2301a <=( a2300a and a2297a );
a2304a <=( (not A169) and (not A170) );
a2307a <=( A199 and (not A168) );
a2308a <=( a2307a and a2304a );
a2311a <=( A203 and (not A200) );
a2314a <=( A300 and A299 );
a2315a <=( a2314a and a2311a );
a2318a <=( (not A169) and (not A170) );
a2321a <=( A199 and (not A168) );
a2322a <=( a2321a and a2318a );
a2325a <=( A203 and (not A200) );
a2328a <=( A300 and A298 );
a2329a <=( a2328a and a2325a );
a2332a <=( A166 and A168 );
a2335a <=( A200 and A199 );
a2336a <=( a2335a and a2332a );
a2339a <=( (not A202) and (not A201) );
a2343a <=( A302 and (not A299) );
a2344a <=( A298 and a2343a );
a2345a <=( a2344a and a2339a );
a2348a <=( A166 and A168 );
a2351a <=( A200 and A199 );
a2352a <=( a2351a and a2348a );
a2355a <=( (not A202) and (not A201) );
a2359a <=( A302 and A299 );
a2360a <=( (not A298) and a2359a );
a2361a <=( a2360a and a2355a );
a2364a <=( A167 and A168 );
a2367a <=( A200 and A199 );
a2368a <=( a2367a and a2364a );
a2371a <=( (not A202) and (not A201) );
a2375a <=( A302 and (not A299) );
a2376a <=( A298 and a2375a );
a2377a <=( a2376a and a2371a );
a2380a <=( A167 and A168 );
a2383a <=( A200 and A199 );
a2384a <=( a2383a and a2380a );
a2387a <=( (not A202) and (not A201) );
a2391a <=( A302 and A299 );
a2392a <=( (not A298) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( A167 and A170 );
a2399a <=( (not A201) and (not A166) );
a2400a <=( a2399a and a2396a );
a2403a <=( (not A203) and (not A202) );
a2407a <=( A302 and (not A299) );
a2408a <=( A298 and a2407a );
a2409a <=( a2408a and a2403a );
a2412a <=( A167 and A170 );
a2415a <=( (not A201) and (not A166) );
a2416a <=( a2415a and a2412a );
a2419a <=( (not A203) and (not A202) );
a2423a <=( A302 and A299 );
a2424a <=( (not A298) and a2423a );
a2425a <=( a2424a and a2419a );
a2428a <=( A167 and A170 );
a2431a <=( A199 and (not A166) );
a2432a <=( a2431a and a2428a );
a2435a <=( (not A201) and A200 );
a2439a <=( A300 and A299 );
a2440a <=( (not A202) and a2439a );
a2441a <=( a2440a and a2435a );
a2444a <=( A167 and A170 );
a2447a <=( A199 and (not A166) );
a2448a <=( a2447a and a2444a );
a2451a <=( (not A201) and A200 );
a2455a <=( A300 and A298 );
a2456a <=( (not A202) and a2455a );
a2457a <=( a2456a and a2451a );
a2460a <=( A167 and A170 );
a2463a <=( (not A199) and (not A166) );
a2464a <=( a2463a and a2460a );
a2467a <=( (not A202) and (not A200) );
a2471a <=( A302 and (not A299) );
a2472a <=( A298 and a2471a );
a2473a <=( a2472a and a2467a );
a2476a <=( A167 and A170 );
a2479a <=( (not A199) and (not A166) );
a2480a <=( a2479a and a2476a );
a2483a <=( (not A202) and (not A200) );
a2487a <=( A302 and A299 );
a2488a <=( (not A298) and a2487a );
a2489a <=( a2488a and a2483a );
a2492a <=( (not A167) and A170 );
a2495a <=( (not A201) and A166 );
a2496a <=( a2495a and a2492a );
a2499a <=( (not A203) and (not A202) );
a2503a <=( A302 and (not A299) );
a2504a <=( A298 and a2503a );
a2505a <=( a2504a and a2499a );
a2508a <=( (not A167) and A170 );
a2511a <=( (not A201) and A166 );
a2512a <=( a2511a and a2508a );
a2515a <=( (not A203) and (not A202) );
a2519a <=( A302 and A299 );
a2520a <=( (not A298) and a2519a );
a2521a <=( a2520a and a2515a );
a2524a <=( (not A167) and A170 );
a2527a <=( A199 and A166 );
a2528a <=( a2527a and a2524a );
a2531a <=( (not A201) and A200 );
a2535a <=( A300 and A299 );
a2536a <=( (not A202) and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( (not A167) and A170 );
a2543a <=( A199 and A166 );
a2544a <=( a2543a and a2540a );
a2547a <=( (not A201) and A200 );
a2551a <=( A300 and A298 );
a2552a <=( (not A202) and a2551a );
a2553a <=( a2552a and a2547a );
a2556a <=( (not A167) and A170 );
a2559a <=( (not A199) and A166 );
a2560a <=( a2559a and a2556a );
a2563a <=( (not A202) and (not A200) );
a2567a <=( A302 and (not A299) );
a2568a <=( A298 and a2567a );
a2569a <=( a2568a and a2563a );
a2572a <=( (not A167) and A170 );
a2575a <=( (not A199) and A166 );
a2576a <=( a2575a and a2572a );
a2579a <=( (not A202) and (not A200) );
a2583a <=( A302 and A299 );
a2584a <=( (not A298) and a2583a );
a2585a <=( a2584a and a2579a );
a2588a <=( (not A167) and (not A169) );
a2591a <=( (not A199) and (not A166) );
a2592a <=( a2591a and a2588a );
a2595a <=( A203 and A200 );
a2599a <=( A302 and (not A299) );
a2600a <=( A298 and a2599a );
a2601a <=( a2600a and a2595a );
a2604a <=( (not A167) and (not A169) );
a2607a <=( (not A199) and (not A166) );
a2608a <=( a2607a and a2604a );
a2611a <=( A203 and A200 );
a2615a <=( A302 and A299 );
a2616a <=( (not A298) and a2615a );
a2617a <=( a2616a and a2611a );
a2620a <=( (not A167) and (not A169) );
a2623a <=( A199 and (not A166) );
a2624a <=( a2623a and a2620a );
a2627a <=( A203 and (not A200) );
a2631a <=( A302 and (not A299) );
a2632a <=( A298 and a2631a );
a2633a <=( a2632a and a2627a );
a2636a <=( (not A167) and (not A169) );
a2639a <=( A199 and (not A166) );
a2640a <=( a2639a and a2636a );
a2643a <=( A203 and (not A200) );
a2647a <=( A302 and A299 );
a2648a <=( (not A298) and a2647a );
a2649a <=( a2648a and a2643a );
a2652a <=( (not A168) and (not A169) );
a2655a <=( A166 and A167 );
a2656a <=( a2655a and a2652a );
a2659a <=( A201 and A199 );
a2663a <=( A302 and (not A299) );
a2664a <=( A298 and a2663a );
a2665a <=( a2664a and a2659a );
a2668a <=( (not A168) and (not A169) );
a2671a <=( A166 and A167 );
a2672a <=( a2671a and a2668a );
a2675a <=( A201 and A199 );
a2679a <=( A302 and A299 );
a2680a <=( (not A298) and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( (not A168) and (not A169) );
a2687a <=( A166 and A167 );
a2688a <=( a2687a and a2684a );
a2691a <=( A201 and A200 );
a2695a <=( A302 and (not A299) );
a2696a <=( A298 and a2695a );
a2697a <=( a2696a and a2691a );
a2700a <=( (not A168) and (not A169) );
a2703a <=( A166 and A167 );
a2704a <=( a2703a and a2700a );
a2707a <=( A201 and A200 );
a2711a <=( A302 and A299 );
a2712a <=( (not A298) and a2711a );
a2713a <=( a2712a and a2707a );
a2716a <=( (not A168) and (not A169) );
a2719a <=( A166 and A167 );
a2720a <=( a2719a and a2716a );
a2723a <=( A200 and (not A199) );
a2727a <=( A300 and A299 );
a2728a <=( A203 and a2727a );
a2729a <=( a2728a and a2723a );
a2732a <=( (not A168) and (not A169) );
a2735a <=( A166 and A167 );
a2736a <=( a2735a and a2732a );
a2739a <=( A200 and (not A199) );
a2743a <=( A300 and A298 );
a2744a <=( A203 and a2743a );
a2745a <=( a2744a and a2739a );
a2748a <=( (not A168) and (not A169) );
a2751a <=( A166 and A167 );
a2752a <=( a2751a and a2748a );
a2755a <=( (not A200) and A199 );
a2759a <=( A300 and A299 );
a2760a <=( A203 and a2759a );
a2761a <=( a2760a and a2755a );
a2764a <=( (not A168) and (not A169) );
a2767a <=( A166 and A167 );
a2768a <=( a2767a and a2764a );
a2771a <=( (not A200) and A199 );
a2775a <=( A300 and A298 );
a2776a <=( A203 and a2775a );
a2777a <=( a2776a and a2771a );
a2780a <=( (not A169) and (not A170) );
a2783a <=( (not A199) and (not A168) );
a2784a <=( a2783a and a2780a );
a2787a <=( A203 and A200 );
a2791a <=( A302 and (not A299) );
a2792a <=( A298 and a2791a );
a2793a <=( a2792a and a2787a );
a2796a <=( (not A169) and (not A170) );
a2799a <=( (not A199) and (not A168) );
a2800a <=( a2799a and a2796a );
a2803a <=( A203 and A200 );
a2807a <=( A302 and A299 );
a2808a <=( (not A298) and a2807a );
a2809a <=( a2808a and a2803a );
a2812a <=( (not A169) and (not A170) );
a2815a <=( A199 and (not A168) );
a2816a <=( a2815a and a2812a );
a2819a <=( A203 and (not A200) );
a2823a <=( A302 and (not A299) );
a2824a <=( A298 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( (not A169) and (not A170) );
a2831a <=( A199 and (not A168) );
a2832a <=( a2831a and a2828a );
a2835a <=( A203 and (not A200) );
a2839a <=( A302 and A299 );
a2840a <=( (not A298) and a2839a );
a2841a <=( a2840a and a2835a );
a2844a <=( A167 and A170 );
a2848a <=( A200 and A199 );
a2849a <=( (not A166) and a2848a );
a2850a <=( a2849a and a2844a );
a2853a <=( (not A202) and (not A201) );
a2857a <=( A302 and (not A299) );
a2858a <=( A298 and a2857a );
a2859a <=( a2858a and a2853a );
a2862a <=( A167 and A170 );
a2866a <=( A200 and A199 );
a2867a <=( (not A166) and a2866a );
a2868a <=( a2867a and a2862a );
a2871a <=( (not A202) and (not A201) );
a2875a <=( A302 and A299 );
a2876a <=( (not A298) and a2875a );
a2877a <=( a2876a and a2871a );
a2880a <=( (not A167) and A170 );
a2884a <=( A200 and A199 );
a2885a <=( A166 and a2884a );
a2886a <=( a2885a and a2880a );
a2889a <=( (not A202) and (not A201) );
a2893a <=( A302 and (not A299) );
a2894a <=( A298 and a2893a );
a2895a <=( a2894a and a2889a );
a2898a <=( (not A167) and A170 );
a2902a <=( A200 and A199 );
a2903a <=( A166 and a2902a );
a2904a <=( a2903a and a2898a );
a2907a <=( (not A202) and (not A201) );
a2911a <=( A302 and A299 );
a2912a <=( (not A298) and a2911a );
a2913a <=( a2912a and a2907a );
a2916a <=( (not A168) and (not A169) );
a2920a <=( (not A199) and A166 );
a2921a <=( A167 and a2920a );
a2922a <=( a2921a and a2916a );
a2925a <=( A203 and A200 );
a2929a <=( A302 and (not A299) );
a2930a <=( A298 and a2929a );
a2931a <=( a2930a and a2925a );
a2934a <=( (not A168) and (not A169) );
a2938a <=( (not A199) and A166 );
a2939a <=( A167 and a2938a );
a2940a <=( a2939a and a2934a );
a2943a <=( A203 and A200 );
a2947a <=( A302 and A299 );
a2948a <=( (not A298) and a2947a );
a2949a <=( a2948a and a2943a );
a2952a <=( (not A168) and (not A169) );
a2956a <=( A199 and A166 );
a2957a <=( A167 and a2956a );
a2958a <=( a2957a and a2952a );
a2961a <=( A203 and (not A200) );
a2965a <=( A302 and (not A299) );
a2966a <=( A298 and a2965a );
a2967a <=( a2966a and a2961a );
a2970a <=( (not A168) and (not A169) );
a2974a <=( A199 and A166 );
a2975a <=( A167 and a2974a );
a2976a <=( a2975a and a2970a );
a2979a <=( A203 and (not A200) );
a2983a <=( A302 and A299 );
a2984a <=( (not A298) and a2983a );
a2985a <=( a2984a and a2979a );
end x25_13x_behav;
| gpl-3.0 | 59e3dc110c03478491040247e8defe57 | 0.599896 | 2.140546 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/count_leading_zero.vhd | 1 | 10,951 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 79965388fa724b8f718ae5f133456e1b | 0.927587 | 1.889081 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/decode.vhd | 1 | 282,467 | `protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 207360)
`protect data_block
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| apache-2.0 | a89302ec354963a0a8f5bf569a83219d | 0.954713 | 1.811812 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/debounce.vhd | 1 | 1,458 |
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
entity Debounce is
port (clock: in STD_LOGIC;
input_h: in STD_LOGIC;
output_h: out STD_LOGIC;
--internal structure
input_temp1_h: out STD_LOGIC;
input_temp2_h: out STD_LOGIC;
count_h: out STD_LOGIC_VECTOR(19 downto 0));
end Debounce;
architecture Behavioral of Debounce is
constant delay : INTEGER := 500000;
signal count : INTEGER := 0;
signal input_temp1, input_temp2 : STD_LOGIC :='0';
signal output_temp : STD_LOGIC;
begin
contar: process (input_h, clock, input_temp1)
begin
if input_h /= input_temp1 then
count <= 0;
input_temp1 <= input_h;
elsif clock'event and clock = '1' then
input_temp1 <= input_h;
input_temp2 <= input_temp1;
count <= count +1;
else
count <= count;
end if;
end process;
avaliar: process (clock, input_temp1, input_temp2, count)
begin
if clock'event and clock='1' then
if count >= delay and input_temp1 = input_temp2 then
output_temp <= input_h;
else
output_temp <= output_temp;
end if;
else
output_temp <= output_temp;
end if;
end process;
output_h <= output_temp;
count_h <= conv_std_logic_vector(count, 20);
input_temp1_h <= input_temp1;
input_temp2_h <= input_temp2;
end Behavioral;
| mit | 2106e3e8a80d9100bfa6511ac971439b | 0.589163 | 3.438679 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_nsga2.vhd | 1 | 3,143 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:30:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_nsga2_entity;
ARCHITECTURE ewf_nsga2_description OF ewf_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
WHEN "00001000" =>
register3 := register3 * 12;
register4 := register4 + register5;
register6 := register1 + register6;
WHEN "00001001" =>
register1 := register1 + register6;
output1 <= register6 + register4;
WHEN "00001010" =>
register1 := register1 * 15;
register3 := register2 + register3;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register5 + register3;
WHEN "00001111" =>
register2 := register2 + 22;
WHEN "00010000" =>
register3 := register2 * 24;
WHEN "00010001" =>
register3 := register3 + 26;
WHEN "00010010" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010011" =>
register2 := register1 + 31;
WHEN "00010100" =>
register2 := register2 * 33;
WHEN "00010101" =>
output4 <= register1 + register2;
register1 := register6 + register1;
WHEN "00010110" =>
register1 := register1 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_nsga2_description; | gpl-3.0 | 4c42b7df8da5c439874d8d05d9395910 | 0.66497 | 3.325926 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic.vhd | 1 | 36,111 | `protect begin_protected
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`protect end_protected
| apache-2.0 | bf2028d67e69a174660d0285ccd2b5dc | 0.946969 | 1.838365 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_occ_counter.vhd | 15 | 10,945 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| apache-2.0 | b3fc4c676bc9c39c3958b969bb9f5cf7 | 0.437825 | 4.610362 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_23.vhd | 1 | 193,761 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_23x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A8: buffer std_logic
);
end x25_23x;
architecture x25_23x_behav of x25_23x is
signal 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7647a,a7648a,a7649a,a7653a,a7654a,a7658a,a7659a,a7660a,a7663a,a7667a,a7668a,a7669a,a7673a,a7674a,a7678a,a7679a,a7680a,a7683a,a7687a,a7688a,a7689a,a7693a,a7694a,a7698a,a7699a,a7700a,a7703a,a7707a,a7708a,a7709a,a7713a,a7714a,a7718a,a7719a,a7720a,a7723a,a7727a,a7728a,a7729a,a7733a,a7734a,a7738a,a7739a,a7740a,a7743a,a7747a,a7748a,a7749a,a7753a,a7754a,a7758a,a7759a,a7760a,a7763a,a7767a,a7768a,a7769a,a7773a,a7774a,a7778a,a7779a,a7780a,a7783a,a7787a,a7788a,a7789a,a7793a,a7794a,a7798a,a7799a,a7800a,a7803a,a7807a,a7808a,a7809a,a7813a,a7814a,a7818a,a7819a,a7820a,a7823a,a7827a,a7828a,a7829a,a7833a,a7834a,a7838a,a7839a,a7840a,a7843a,a7847a,a7848a,a7849a,a7853a,a7854a,a7858a,a7859a,a7860a,a7863a,a7867a,a7868a,a7869a,a7873a,a7874a,a7878a,a7879a,a7880a,a7883a,a7887a,a7888a,a7889a,a7893a,a7894a,a7898a,a7899a,a7900a,a7903a,a7907a,a7908a,a7909a,a7913a,a7914a,a7918a,a7919a,a7920a,a7923a,a7927a,a7928a,a7929a,a7933a,a7934a,a7938a,a7939a,a7940a,a7943a,a7947a,a7948a,a7949a,a7953a,a7954a,a7958a,a7959a,a7960a,a7964a,a7965a,a7969a,a7970a,a7971a,a7975a,a7976a,a7980a,a7981a,a7982a,a7986a,a7987a,a7991a,a7992a,a7993a,a7997a,a7998a,a8002a,a8003a,a8004a,a8008a,a8009a,a8013a,a8014a,a8015a,a8019a,a8020a,a8024a,a8025a,a8026a,a8030a,a8031a,a8035a,a8036a,a8037a,a8041a,a8042a,a8046a,a8047a,a8048a,a8052a,a8053a,a8057a,a8058a,a8059a,a8063a,a8064a,a8068a,a8069a,a8070a,a8074a,a8075a,a8079a,a8080a,a8081a,a8085a,a8086a,a8090a,a8091a,a8092a,a8096a,a8097a,a8101a,a8102a,a8103a,a8107a,a8108a,a8112a,a8113a,a8114a,a8118a,a8119a,a8123a,a8124a,a8125a,a8129a,a8130a,a8134a,a8135a,a8136a,a8140a,a8141a,a8145a,a8146a,a8147a,a8151a,a8152a,a8156a,a8157a,a8158a,a8162a,a8163a,a8167a,a8168a,a8169a,a8173a,a8174a,a8178a,a8179a,a8180a,a8184a,a8185a,a8189a,a8190a,a8191a,a8195a,a8196a,a8200a,a8201a,a8202a,a8206a,a8207a,a8211a,a8212a,a8213a,a8217a,a8218a,a8222a,a8223a,a8224a,a8228a,a8229a,a8233a,a8234a,a8235a,a8239a,a8240a,a8244a,a8245a,a8246a,a8250a,a8251a,a8255a,a8256a,a8257a,a8261a,a8262a,a8266a,a8267a,a8268a,a8272a,a8273a,a8277a,a8278a,a8279a,a8283a,a8284a,a8288a,a8289a,a8290a,a8294a,a8295a,a8299a,a8300a,a8301a,a8305a,a8306a,a8310a,a8311a,a8312a,a8316a,a8317a,a8321a,a8322a,a8323a,a8327a,a8328a,a8332a,a8333a,a8334a,a8338a,a8339a,a8343a,a8344a,a8345a,a8349a,a8350a,a8354a,a8355a,a8356a,a8360a,a8361a,a8365a,a8366a,a8367a,a8371a,a8372a,a8376a,a8377a,a8378a,a8382a,a8383a,a8387a,a8388a,a8389a,a8393a,a8394a,a8398a,a8399a,a8400a,a8404a,a8405a,a8409a,a8410a,a8411a,a8415a,a8416a,a8420a,a8421a,a8422a,a8426a,a8427a,a8431a,a8432a,a8433a,a8437a,a8438a,a8442a,a8443a,a8444a,a8448a,a8449a,a8453a,a8454a,a8455a,a8459a,a8460a,a8464a,a8465a,a8466a,a8470a,a8471a,a8475a,a8476a,a8477a,a8481a,a8482a,a8486a,a8487a,a8488a,a8492a,a8493a,a8497a,a8498a,a8499a,a8503a,a8504a,a8508a,a8509a,a8510a,a8514a,a8515a,a8519a,a8520a,a8521a,a8525a,a8526a,a8530a,a8531a,a8532a,a8536a,a8537a,a8541a,a8542a,a8543a,a8547a,a8548a,a8552a,a8553a,a8554a,a8558a,a8559a,a8563a,a8564a,a8565a,a8569a,a8570a,a8574a,a8575a,a8576a,a8580a,a8581a,a8585a,a8586a,a8587a,a8591a,a8592a,a8596a,a8597a,a8598a,a8602a,a8603a,a8607a,a8608a,a8609a,a8613a,a8614a,a8618a,a8619a,a8620a,a8624a,a8625a,a8629a,a8630a,a8631a,a8635a,a8636a,a8640a,a8641a,a8642a,a8646a,a8647a,a8651a,a8652a,a8653a,a8657a,a8658a,a8662a,a8663a,a8664a,a8668a,a8669a,a8673a,a8674a,a8675a,a8679a,a8680a,a8684a,a8685a,a8686a,a8690a,a8691a,a8695a,a8696a,a8697a,a8701a,a8702a,a8706a,a8707a,a8708a,a8712a,a8713a,a8717a,a8718a,a8719a,a8723a,a8724a,a8728a,a8729a,a8730a,a8734a,a8735a,a8739a,a8740a,a8741a,a8745a,a8746a,a8750a,a8751a,a8752a,a8756a,a8757a,a8761a,a8762a,a8763a,a8767a,a8768a,a8772a,a8773a,a8774a,a8778a,a8779a,a8783a,a8784a,a8785a,a8789a,a8790a,a8794a,a8795a,a8796a,a8800a,a8801a,a8805a,a8806a,a8807a,a8811a,a8812a,a8816a,a8817a,a8818a,a8822a,a8823a,a8827a,a8828a,a8829a,a8833a,a8834a,a8838a,a8839a,a8840a,a8844a,a8845a,a8849a,a8850a,a8851a,a8855a,a8856a,a8860a,a8861a,a8862a,a8866a,a8867a,a8871a,a8872a,a8873a,a8877a,a8878a,a8882a,a8883a,a8884a,a8888a,a8889a,a8893a,a8894a,a8895a,a8899a,a8900a,a8904a,a8905a,a8906a,a8910a,a8911a,a8915a,a8916a,a8917a,a8921a,a8922a,a8926a,a8927a,a8928a,a8932a,a8933a,a8937a,a8938a,a8939a,a8943a,a8944a,a8948a,a8949a,a8950a,a8954a,a8955a,a8959a,a8960a,a8961a,a8965a,a8966a,a8970a,a8971a,a8972a,a8976a,a8977a,a8981a,a8982a,a8983a,a8987a,a8988a,a8992a,a8993a,a8994a,a8998a,a8999a,a9003a,a9004a,a9005a,a9009a,a9010a,a9014a,a9015a,a9016a,a9020a,a9021a,a9025a,a9026a,a9027a,a9031a,a9032a,a9036a,a9037a,a9038a,a9042a,a9043a,a9047a,a9048a,a9049a,a9053a,a9054a,a9058a,a9059a,a9060a,a9064a,a9065a,a9069a,a9070a,a9071a,a9075a,a9076a,a9080a,a9081a,a9082a,a9086a,a9087a,a9091a,a9092a,a9093a,a9097a,a9098a,a9102a,a9103a,a9104a,a9108a,a9109a,a9113a,a9114a,a9115a,a9119a,a9120a,a9124a,a9125a,a9126a,a9130a,a9131a,a9135a,a9136a,a9137a,a9141a,a9142a,a9146a,a9147a,a9148a,a9152a,a9153a,a9157a,a9158a,a9159a,a9163a,a9164a,a9168a,a9169a,a9170a,a9174a,a9175a,a9179a,a9180a,a9181a,a9185a,a9186a,a9190a,a9191a,a9192a,a9196a,a9197a,a9201a,a9202a,a9203a,a9207a,a9208a,a9212a,a9213a,a9214a,a9218a,a9219a,a9223a,a9224a,a9225a,a9229a,a9230a,a9234a,a9235a,a9236a,a9240a,a9241a,a9245a,a9246a,a9247a,a9251a,a9252a,a9256a,a9257a,a9258a,a9262a,a9263a,a9267a,a9268a,a9269a,a9273a,a9274a,a9278a,a9279a,a9280a,a9284a,a9285a,a9289a,a9290a,a9291a,a9295a,a9296a,a9300a,a9301a,a9302a,a9306a,a9307a,a9311a,a9312a,a9313a,a9317a,a9318a,a9322a,a9323a,a9324a,a9328a,a9329a,a9333a,a9334a,a9335a,a9339a,a9340a,a9344a,a9345a,a9346a,a9350a,a9351a,a9355a,a9356a,a9357a,a9361a,a9362a,a9366a,a9367a,a9368a,a9372a,a9373a,a9377a,a9378a,a9379a,a9383a,a9384a,a9387a,a9390a,a9391a,a9392a,a9396a,a9397a,a9401a,a9402a,a9403a,a9407a,a9408a,a9411a,a9414a,a9415a,a9416a,a9420a,a9421a,a9425a,a9426a,a9427a,a9431a,a9432a,a9435a,a9438a,a9439a,a9440a,a9444a,a9445a,a9449a,a9450a,a9451a,a9455a,a9456a,a9459a,a9462a,a9463a,a9464a,a9468a,a9469a,a9473a,a9474a,a9475a,a9479a,a9480a,a9483a,a9486a,a9487a,a9488a,a9492a,a9493a,a9497a,a9498a,a9499a,a9503a,a9504a,a9507a,a9510a,a9511a,a9512a,a9516a,a9517a,a9521a,a9522a,a9523a,a9527a,a9528a,a9531a,a9534a,a9535a,a9536a,a9540a,a9541a,a9545a,a9546a,a9547a,a9551a,a9552a,a9555a,a9558a,a9559a,a9560a: std_logic;
begin
A8 <=( a1312a ) or ( a875a );
a1a <=( a9560a and a9547a );
a2a <=( a9536a and a9523a );
a3a <=( a9512a and a9499a );
a4a <=( a9488a and a9475a );
a5a <=( a9464a and a9451a );
a6a <=( a9440a and a9427a );
a7a <=( a9416a and a9403a );
a8a <=( a9392a and a9379a );
a9a <=( a9368a and a9357a );
a10a <=( a9346a and a9335a );
a11a <=( a9324a and a9313a );
a12a <=( a9302a and a9291a );
a13a <=( a9280a and a9269a );
a14a <=( a9258a and a9247a );
a15a <=( a9236a and a9225a );
a16a <=( a9214a and a9203a );
a17a <=( a9192a and a9181a );
a18a <=( a9170a and a9159a );
a19a <=( a9148a and a9137a );
a20a <=( a9126a and a9115a );
a21a <=( a9104a and a9093a );
a22a <=( a9082a and a9071a );
a23a <=( a9060a and a9049a );
a24a <=( a9038a and a9027a );
a25a <=( a9016a and a9005a );
a26a <=( a8994a and a8983a );
a27a <=( a8972a and a8961a );
a28a <=( a8950a and a8939a );
a29a <=( a8928a and a8917a );
a30a <=( a8906a and a8895a );
a31a <=( a8884a and a8873a );
a32a <=( a8862a and a8851a );
a33a <=( a8840a and a8829a );
a34a <=( a8818a and a8807a );
a35a <=( a8796a and a8785a );
a36a <=( a8774a and a8763a );
a37a <=( a8752a and a8741a );
a38a <=( a8730a and a8719a );
a39a <=( a8708a and a8697a );
a40a <=( a8686a and a8675a );
a41a <=( a8664a and a8653a );
a42a <=( a8642a and a8631a );
a43a <=( a8620a and a8609a );
a44a <=( a8598a and a8587a );
a45a <=( a8576a and a8565a );
a46a <=( a8554a and a8543a );
a47a <=( a8532a and a8521a );
a48a <=( a8510a and a8499a );
a49a <=( a8488a and a8477a );
a50a <=( a8466a and a8455a );
a51a <=( a8444a and a8433a );
a52a <=( a8422a and a8411a );
a53a <=( a8400a and a8389a );
a54a <=( a8378a and a8367a );
a55a <=( a8356a and a8345a );
a56a <=( a8334a and a8323a );
a57a <=( a8312a and a8301a );
a58a <=( a8290a and a8279a );
a59a <=( a8268a and a8257a );
a60a <=( a8246a and a8235a );
a61a <=( a8224a and a8213a );
a62a <=( a8202a and a8191a );
a63a <=( a8180a and a8169a );
a64a <=( a8158a and a8147a );
a65a <=( a8136a and a8125a );
a66a <=( a8114a and a8103a );
a67a <=( a8092a and a8081a );
a68a <=( a8070a and a8059a );
a69a <=( a8048a and a8037a );
a70a <=( a8026a and a8015a );
a71a <=( a8004a and a7993a );
a72a <=( a7982a and a7971a );
a73a <=( a7960a and a7949a );
a74a <=( a7940a and a7929a );
a75a <=( a7920a and a7909a );
a76a <=( a7900a and a7889a );
a77a <=( a7880a and a7869a );
a78a <=( a7860a and a7849a );
a79a <=( a7840a and a7829a );
a80a <=( a7820a and a7809a );
a81a <=( a7800a and a7789a );
a82a <=( a7780a and a7769a );
a83a <=( a7760a and a7749a );
a84a <=( a7740a and a7729a );
a85a <=( a7720a and a7709a );
a86a <=( a7700a and a7689a );
a87a <=( a7680a and a7669a );
a88a <=( a7660a and a7649a );
a89a <=( a7640a and a7629a );
a90a <=( a7620a and a7609a );
a91a <=( a7600a and a7589a );
a92a <=( a7580a and a7569a );
a93a <=( a7560a and a7549a );
a94a <=( a7540a and a7529a );
a95a <=( a7520a and a7509a );
a96a <=( a7500a and a7489a );
a97a <=( a7480a and a7469a );
a98a <=( a7460a and a7449a );
a99a <=( a7440a and a7429a );
a100a <=( a7420a and a7409a );
a101a <=( a7400a and a7389a );
a102a <=( a7380a and a7369a );
a103a <=( a7360a and a7349a );
a104a <=( a7340a and a7329a );
a105a <=( a7320a and a7309a );
a106a <=( a7300a and a7289a );
a107a <=( a7280a and a7269a );
a108a <=( a7260a and a7249a );
a109a <=( a7240a and a7229a );
a110a <=( a7220a and a7209a );
a111a <=( a7200a and a7189a );
a112a <=( a7180a and a7169a );
a113a <=( a7160a and a7149a );
a114a <=( a7140a and a7129a );
a115a <=( a7120a and a7109a );
a116a <=( a7100a and a7089a );
a117a <=( a7080a and a7069a );
a118a <=( a7060a and a7049a );
a119a <=( a7040a and a7029a );
a120a <=( a7020a and a7009a );
a121a <=( a7000a and a6989a );
a122a <=( a6980a and a6969a );
a123a <=( a6960a and a6949a );
a124a <=( a6940a and a6929a );
a125a <=( a6920a and a6909a );
a126a <=( a6900a and a6889a );
a127a <=( a6880a and a6869a );
a128a <=( a6860a and a6849a );
a129a <=( a6840a and a6829a );
a130a <=( a6820a and a6809a );
a131a <=( a6800a and a6789a );
a132a <=( a6780a and a6769a );
a133a <=( a6760a and a6749a );
a134a <=( a6740a and a6729a );
a135a <=( a6720a and a6709a );
a136a <=( a6700a and a6689a );
a137a <=( a6680a and a6669a );
a138a <=( a6660a and a6649a );
a139a <=( a6640a and a6629a );
a140a <=( a6620a and a6609a );
a141a <=( a6600a and a6589a );
a142a <=( a6580a and a6569a );
a143a <=( a6560a and a6549a );
a144a <=( a6540a and a6529a );
a145a <=( a6520a and a6509a );
a146a <=( a6500a and a6489a );
a147a <=( a6480a and a6469a );
a148a <=( a6460a and a6449a );
a149a <=( a6440a and a6429a );
a150a <=( a6420a and a6409a );
a151a <=( a6400a and a6389a );
a152a <=( a6380a and a6369a );
a153a <=( a6360a and a6349a );
a154a <=( a6340a and a6329a );
a155a <=( a6320a and a6309a );
a156a <=( a6300a and a6289a );
a157a <=( a6280a and a6269a );
a158a <=( a6260a and a6249a );
a159a <=( a6240a and a6229a );
a160a <=( a6220a and a6209a );
a161a <=( a6200a and a6189a );
a162a <=( a6180a and a6169a );
a163a <=( a6160a and a6149a );
a164a <=( a6140a and a6129a );
a165a <=( a6120a and a6109a );
a166a <=( a6100a and a6089a );
a167a <=( a6080a and a6069a );
a168a <=( a6060a and a6049a );
a169a <=( a6040a and a6029a );
a170a <=( a6020a and a6009a );
a171a <=( a6000a and a5989a );
a172a <=( a5980a and a5969a );
a173a <=( a5960a and a5949a );
a174a <=( a5940a and a5929a );
a175a <=( a5920a and a5909a );
a176a <=( a5900a and a5889a );
a177a <=( a5880a and a5869a );
a178a <=( a5860a and a5849a );
a179a <=( a5840a and a5829a );
a180a <=( a5820a and a5809a );
a181a <=( a5800a and a5789a );
a182a <=( a5780a and a5769a );
a183a <=( a5760a and a5749a );
a184a <=( a5740a and a5729a );
a185a <=( a5720a and a5709a );
a186a <=( a5700a and a5689a );
a187a <=( a5680a and a5669a );
a188a <=( a5660a and a5649a );
a189a <=( a5640a and a5629a );
a190a <=( a5620a and a5609a );
a191a <=( a5600a and a5589a );
a192a <=( a5580a and a5569a );
a193a <=( a5560a and a5549a );
a194a <=( a5540a and a5529a );
a195a <=( a5520a and a5509a );
a196a <=( a5500a and a5489a );
a197a <=( a5480a and a5469a );
a198a <=( a5460a and a5449a );
a199a <=( a5440a and a5429a );
a200a <=( a5420a and a5409a );
a201a <=( a5400a and a5389a );
a202a <=( a5380a and a5369a );
a203a <=( a5360a and a5349a );
a204a <=( a5340a and a5329a );
a205a <=( a5320a and a5309a );
a206a <=( a5300a and a5289a );
a207a <=( a5280a and a5269a );
a208a <=( a5260a and a5249a );
a209a <=( a5240a and a5229a );
a210a <=( a5220a and a5209a );
a211a <=( a5200a and a5189a );
a212a <=( a5180a and a5169a );
a213a <=( a5160a and a5149a );
a214a <=( a5140a and a5129a );
a215a <=( a5120a and a5109a );
a216a <=( a5100a and a5089a );
a217a <=( a5080a and a5069a );
a218a <=( a5060a and a5049a );
a219a <=( a5040a and a5029a );
a220a <=( a5020a and a5009a );
a221a <=( a5000a and a4989a );
a222a <=( a4980a and a4969a );
a223a <=( a4960a and a4949a );
a224a <=( a4940a and a4929a );
a225a <=( a4920a and a4909a );
a226a <=( a4900a and a4889a );
a227a <=( a4880a and a4869a );
a228a <=( a4860a and a4849a );
a229a <=( a4840a and a4829a );
a230a <=( a4820a and a4809a );
a231a <=( a4800a and a4789a );
a232a <=( a4780a and a4769a );
a233a <=( a4760a and a4751a );
a234a <=( a4742a and a4733a );
a235a <=( a4724a and a4715a );
a236a <=( a4706a and a4697a );
a237a <=( a4688a and a4679a );
a238a <=( a4670a and a4661a );
a239a <=( a4652a and a4643a );
a240a <=( a4634a and a4625a );
a241a <=( a4616a and a4607a );
a242a <=( a4598a and a4589a );
a243a <=( a4580a and a4571a );
a244a <=( a4562a and a4553a );
a245a <=( a4544a and a4535a );
a246a <=( a4526a and a4517a );
a247a <=( a4508a and a4499a );
a248a <=( a4490a and a4481a );
a249a <=( a4472a and a4463a );
a250a <=( a4454a and a4445a );
a251a <=( a4436a and a4427a );
a252a <=( a4418a and a4409a );
a253a <=( a4400a and a4391a );
a254a <=( a4382a and a4373a );
a255a <=( a4364a and a4355a );
a256a <=( a4346a and a4337a );
a257a <=( a4328a and a4319a );
a258a <=( a4310a and a4301a );
a259a <=( a4292a and a4283a );
a260a <=( a4274a and a4265a );
a261a <=( a4256a and a4247a );
a262a <=( a4238a and a4229a );
a263a <=( a4220a and a4211a );
a264a <=( a4202a and a4193a );
a265a <=( a4184a and a4175a );
a266a <=( a4166a and a4157a );
a267a <=( a4148a and a4139a );
a268a <=( a4130a and a4121a );
a269a <=( a4112a and a4103a );
a270a <=( a4094a and a4085a );
a271a <=( a4076a and a4067a );
a272a <=( a4058a and a4049a );
a273a <=( a4040a and a4031a );
a274a <=( a4022a and a4013a );
a275a <=( a4004a and a3995a );
a276a <=( a3986a and a3977a );
a277a <=( a3968a and a3959a );
a278a <=( a3950a and a3941a );
a279a <=( a3932a and a3923a );
a280a <=( a3914a and a3905a );
a281a <=( a3896a and a3887a );
a282a <=( a3878a and a3869a );
a283a <=( a3860a and a3851a );
a284a <=( a3842a and a3833a );
a285a <=( a3824a and a3815a );
a286a <=( a3806a and a3797a );
a287a <=( a3788a and a3779a );
a288a <=( a3770a and a3761a );
a289a <=( a3752a and a3743a );
a290a <=( a3734a and a3725a );
a291a <=( a3716a and a3707a );
a292a <=( a3698a and a3689a );
a293a <=( a3680a and a3671a );
a294a <=( a3662a and a3653a );
a295a <=( a3644a and a3635a );
a296a <=( a3626a and a3617a );
a297a <=( a3608a and a3599a );
a298a <=( a3590a and a3581a );
a299a <=( a3572a and a3563a );
a300a <=( a3554a and a3545a );
a301a <=( a3536a and a3527a );
a302a <=( a3518a and a3509a );
a303a <=( a3500a and a3491a );
a304a <=( a3482a and a3473a );
a305a <=( a3464a and a3455a );
a306a <=( a3446a and a3437a );
a307a <=( a3428a and a3419a );
a308a <=( a3410a and a3401a );
a309a <=( a3392a and a3383a );
a310a <=( a3374a and a3365a );
a311a <=( a3356a and a3347a );
a312a <=( a3338a and a3329a );
a313a <=( a3320a and a3311a );
a314a <=( a3302a and a3293a );
a315a <=( a3284a and a3275a );
a316a <=( a3266a and a3257a );
a317a <=( a3248a and a3239a );
a318a <=( a3230a and a3221a );
a319a <=( a3212a and a3203a );
a320a <=( a3194a and a3185a );
a321a <=( a3176a and a3167a );
a322a <=( a3158a and a3149a );
a323a <=( a3140a and a3131a );
a324a <=( a3122a and a3113a );
a325a <=( a3104a and a3095a );
a326a <=( a3086a and a3077a );
a327a <=( a3068a and a3059a );
a328a <=( a3050a and a3041a );
a329a <=( a3032a and a3023a );
a330a <=( a3014a and a3005a );
a331a <=( a2996a and a2987a );
a332a <=( a2978a and a2969a );
a333a <=( a2960a and a2951a );
a334a <=( a2942a and a2933a );
a335a <=( a2924a and a2915a );
a336a <=( a2906a and a2897a );
a337a <=( a2888a and a2879a );
a338a <=( a2870a and a2861a );
a339a <=( a2852a and a2843a );
a340a <=( a2834a and a2825a );
a341a <=( a2816a and a2807a );
a342a <=( a2798a and a2789a );
a343a <=( a2780a and a2771a );
a344a <=( a2762a and a2753a );
a345a <=( a2744a and a2735a );
a346a <=( a2726a and a2717a );
a347a <=( a2708a and a2699a );
a348a <=( a2690a and a2681a );
a349a <=( a2672a and a2663a );
a350a <=( a2654a and a2645a );
a351a <=( a2636a and a2627a );
a352a <=( a2618a and a2609a );
a353a <=( a2600a and a2591a );
a354a <=( a2582a and a2573a );
a355a <=( a2564a and a2555a );
a356a <=( a2546a and a2537a );
a357a <=( a2528a and a2519a );
a358a <=( a2510a and a2501a );
a359a <=( a2492a and a2483a );
a360a <=( a2474a and a2465a );
a361a <=( a2456a and a2447a );
a362a <=( a2438a and a2429a );
a363a <=( a2420a and a2411a );
a364a <=( a2402a and a2393a );
a365a <=( a2384a and a2375a );
a366a <=( a2366a and a2357a );
a367a <=( a2348a and a2339a );
a368a <=( a2330a and a2321a );
a369a <=( a2312a and a2303a );
a370a <=( a2296a and a2287a );
a371a <=( a2280a and a2271a );
a372a <=( a2264a and a2255a );
a373a <=( a2248a and a2239a );
a374a <=( a2232a and a2223a );
a375a <=( a2216a and a2207a );
a376a <=( a2200a and a2191a );
a377a <=( a2184a and a2175a );
a378a <=( a2168a and a2159a );
a379a <=( a2152a and a2143a );
a380a <=( a2136a and a2127a );
a381a <=( a2120a and a2111a );
a382a <=( a2104a and a2095a );
a383a <=( a2088a and a2079a );
a384a <=( a2072a and a2063a );
a385a <=( a2056a and a2047a );
a386a <=( a2040a and a2031a );
a387a <=( a2024a and a2015a );
a388a <=( a2008a and a1999a );
a389a <=( a1992a and a1983a );
a390a <=( a1976a and a1967a );
a391a <=( a1960a and a1951a );
a392a <=( a1944a and a1935a );
a393a <=( a1928a and a1919a );
a394a <=( a1912a and a1903a );
a395a <=( a1896a and a1887a );
a396a <=( a1880a and a1871a );
a397a <=( a1864a and a1855a );
a398a <=( a1848a and a1839a );
a399a <=( a1832a and a1823a );
a400a <=( a1816a and a1807a );
a401a <=( a1800a and a1793a );
a402a <=( a1786a and a1779a );
a403a <=( a1772a and a1765a );
a404a <=( a1758a and a1751a );
a405a <=( a1744a and a1737a );
a406a <=( a1730a and a1723a );
a407a <=( a1716a and a1709a );
a408a <=( a1702a and a1695a );
a409a <=( a1688a and a1681a );
a410a <=( a1674a and a1667a );
a411a <=( a1660a and a1653a );
a412a <=( a1646a and a1639a );
a413a <=( a1632a and a1625a );
a414a <=( a1618a and a1611a );
a415a <=( a1604a and a1597a );
a416a <=( a1590a and a1583a );
a417a <=( a1576a and a1569a );
a418a <=( a1562a and a1555a );
a419a <=( a1548a and a1541a );
a420a <=( a1534a and a1527a );
a421a <=( a1520a and a1513a );
a422a <=( a1506a and a1499a );
a423a <=( a1492a and a1485a );
a424a <=( a1478a and a1471a );
a425a <=( a1464a and a1457a );
a426a <=( a1450a and a1443a );
a427a <=( a1436a and a1429a );
a428a <=( a1422a and a1415a );
a429a <=( a1408a and a1401a );
a430a <=( a1394a and a1387a );
a431a <=( a1380a and a1373a );
a432a <=( a1366a and a1359a );
a433a <=( a1352a and a1347a );
a434a <=( a1344a and a1339a );
a435a <=( a1336a and a1333a );
a436a <=( a1330a and a1327a );
a437a <=( a1324a and a1321a );
a438a <=( a1318a and a1315a );
a442a <=( a436a ) or ( a437a );
a443a <=( a438a ) or ( a442a );
a447a <=( a433a ) or ( a434a );
a448a <=( a435a ) or ( a447a );
a449a <=( a448a ) or ( a443a );
a453a <=( a430a ) or ( a431a );
a454a <=( a432a ) or ( a453a );
a457a <=( a428a ) or ( a429a );
a460a <=( a426a ) or ( a427a );
a461a <=( a460a ) or ( a457a );
a462a <=( a461a ) or ( a454a );
a463a <=( a462a ) or ( a449a );
a467a <=( a423a ) or ( a424a );
a468a <=( a425a ) or ( a467a );
a471a <=( a421a ) or ( a422a );
a474a <=( a419a ) or ( a420a );
a475a <=( a474a ) or ( a471a );
a476a <=( a475a ) or ( a468a );
a480a <=( a416a ) or ( a417a );
a481a <=( a418a ) or ( a480a );
a484a <=( a414a ) or ( a415a );
a487a <=( a412a ) or ( a413a );
a488a <=( a487a ) or ( a484a );
a489a <=( a488a ) or ( a481a );
a490a <=( a489a ) or ( a476a );
a491a <=( a490a ) or ( a463a );
a495a <=( a409a ) or ( a410a );
a496a <=( a411a ) or ( a495a );
a500a <=( a406a ) or ( a407a );
a501a <=( a408a ) or ( a500a );
a502a <=( a501a ) or ( a496a );
a506a <=( a403a ) or ( a404a );
a507a <=( a405a ) or ( a506a );
a510a <=( a401a ) or ( a402a );
a513a <=( a399a ) or ( a400a );
a514a <=( a513a ) or ( a510a );
a515a <=( a514a ) or ( a507a );
a516a <=( a515a ) or ( a502a );
a520a <=( a396a ) or ( a397a );
a521a <=( a398a ) or ( a520a );
a524a <=( a394a ) or ( a395a );
a527a <=( a392a ) or ( a393a );
a528a <=( a527a ) or ( a524a );
a529a <=( a528a ) or ( a521a );
a533a <=( a389a ) or ( a390a );
a534a <=( a391a ) or ( a533a );
a537a <=( a387a ) or ( a388a );
a540a <=( a385a ) or ( a386a );
a541a <=( a540a ) or ( a537a );
a542a <=( a541a ) or ( a534a );
a543a <=( a542a ) or ( a529a );
a544a <=( a543a ) or ( a516a );
a545a <=( a544a ) or ( a491a );
a549a <=( a382a ) or ( a383a );
a550a <=( a384a ) or ( a549a );
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a555a <=( a381a ) or ( a554a );
a556a <=( a555a ) or ( a550a );
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a564a <=( a374a ) or ( a375a );
a567a <=( a372a ) or ( a373a );
a568a <=( a567a ) or ( a564a );
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a575a <=( a371a ) or ( a574a );
a578a <=( a367a ) or ( a368a );
a581a <=( a365a ) or ( a366a );
a582a <=( a581a ) or ( a578a );
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a588a <=( a364a ) or ( a587a );
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a595a <=( a594a ) or ( a591a );
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a597a <=( a596a ) or ( a583a );
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a602a <=( a355a ) or ( a356a );
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a611a <=( a610a ) or ( a603a );
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a616a <=( a350a ) or ( a615a );
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a624a <=( a623a ) or ( a616a );
a625a <=( a624a ) or ( a611a );
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a630a <=( a343a ) or ( a629a );
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a650a <=( a649a ) or ( a646a );
a651a <=( a650a ) or ( a643a );
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a655a <=( a654a ) or ( a545a );
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a665a <=( a326a ) or ( a664a );
a666a <=( a665a ) or ( a660a );
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a671a <=( a323a ) or ( a670a );
a674a <=( a319a ) or ( a320a );
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a678a <=( a677a ) or ( a674a );
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a680a <=( a679a ) or ( a666a );
a684a <=( a314a ) or ( a315a );
a685a <=( a316a ) or ( a684a );
a688a <=( a312a ) or ( a313a );
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a692a <=( a691a ) or ( a688a );
a693a <=( a692a ) or ( a685a );
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a698a <=( a309a ) or ( a697a );
a701a <=( a305a ) or ( a306a );
a704a <=( a303a ) or ( a304a );
a705a <=( a704a ) or ( a701a );
a706a <=( a705a ) or ( a698a );
a707a <=( a706a ) or ( a693a );
a708a <=( a707a ) or ( a680a );
a712a <=( a300a ) or ( a301a );
a713a <=( a302a ) or ( a712a );
a716a <=( a298a ) or ( a299a );
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a720a <=( a719a ) or ( a716a );
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a725a <=( a293a ) or ( a294a );
a726a <=( a295a ) or ( a725a );
a729a <=( a291a ) or ( a292a );
a732a <=( a289a ) or ( a290a );
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a735a <=( a734a ) or ( a721a );
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a740a <=( a288a ) or ( a739a );
a743a <=( a284a ) or ( a285a );
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a747a <=( a746a ) or ( a743a );
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a752a <=( a279a ) or ( a280a );
a753a <=( a281a ) or ( a752a );
a756a <=( a277a ) or ( a278a );
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a760a <=( a759a ) or ( a756a );
a761a <=( a760a ) or ( a753a );
a762a <=( a761a ) or ( a748a );
a763a <=( a762a ) or ( a735a );
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a768a <=( a272a ) or ( a273a );
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a773a <=( a269a ) or ( a270a );
a774a <=( a271a ) or ( a773a );
a775a <=( a774a ) or ( a769a );
a779a <=( a266a ) or ( a267a );
a780a <=( a268a ) or ( a779a );
a783a <=( a264a ) or ( a265a );
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a787a <=( a786a ) or ( a783a );
a788a <=( a787a ) or ( a780a );
a789a <=( a788a ) or ( a775a );
a793a <=( a259a ) or ( a260a );
a794a <=( a261a ) or ( a793a );
a797a <=( a257a ) or ( a258a );
a800a <=( a255a ) or ( a256a );
a801a <=( a800a ) or ( a797a );
a802a <=( a801a ) or ( a794a );
a806a <=( a252a ) or ( a253a );
a807a <=( a254a ) or ( a806a );
a810a <=( a250a ) or ( a251a );
a813a <=( a248a ) or ( a249a );
a814a <=( a813a ) or ( a810a );
a815a <=( a814a ) or ( a807a );
a816a <=( a815a ) or ( a802a );
a817a <=( a816a ) or ( a789a );
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a825a <=( a243a ) or ( a244a );
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a829a <=( a828a ) or ( a825a );
a830a <=( a829a ) or ( a822a );
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a835a <=( a240a ) or ( a834a );
a838a <=( a236a ) or ( a237a );
a841a <=( a234a ) or ( a235a );
a842a <=( a841a ) or ( a838a );
a843a <=( a842a ) or ( a835a );
a844a <=( a843a ) or ( a830a );
a848a <=( a231a ) or ( a232a );
a849a <=( a233a ) or ( a848a );
a852a <=( a229a ) or ( a230a );
a855a <=( a227a ) or ( a228a );
a856a <=( a855a ) or ( a852a );
a857a <=( a856a ) or ( a849a );
a861a <=( a224a ) or ( a225a );
a862a <=( a226a ) or ( a861a );
a865a <=( a222a ) or ( a223a );
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a869a <=( a868a ) or ( a865a );
a870a <=( a869a ) or ( a862a );
a871a <=( a870a ) or ( a857a );
a872a <=( a871a ) or ( a844a );
a873a <=( a872a ) or ( a817a );
a874a <=( a873a ) or ( a764a );
a875a <=( a874a ) or ( a655a );
a879a <=( a217a ) or ( a218a );
a880a <=( a219a ) or ( a879a );
a884a <=( a214a ) or ( a215a );
a885a <=( a216a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
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a891a <=( a213a ) or ( a890a );
a894a <=( a209a ) or ( a210a );
a897a <=( a207a ) or ( a208a );
a898a <=( a897a ) or ( a894a );
a899a <=( a898a ) or ( a891a );
a900a <=( a899a ) or ( a886a );
a904a <=( a204a ) or ( a205a );
a905a <=( a206a ) or ( a904a );
a908a <=( a202a ) or ( a203a );
a911a <=( a200a ) or ( a201a );
a912a <=( a911a ) or ( a908a );
a913a <=( a912a ) or ( a905a );
a917a <=( a197a ) or ( a198a );
a918a <=( a199a ) or ( a917a );
a921a <=( a195a ) or ( a196a );
a924a <=( a193a ) or ( a194a );
a925a <=( a924a ) or ( a921a );
a926a <=( a925a ) or ( a918a );
a927a <=( a926a ) or ( a913a );
a928a <=( a927a ) or ( a900a );
a932a <=( a190a ) or ( a191a );
a933a <=( a192a ) or ( a932a );
a937a <=( a187a ) or ( a188a );
a938a <=( a189a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a184a ) or ( a185a );
a944a <=( a186a ) or ( a943a );
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a950a <=( a180a ) or ( a181a );
a951a <=( a950a ) or ( a947a );
a952a <=( a951a ) or ( a944a );
a953a <=( a952a ) or ( a939a );
a957a <=( a177a ) or ( a178a );
a958a <=( a179a ) or ( a957a );
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a964a <=( a173a ) or ( a174a );
a965a <=( a964a ) or ( a961a );
a966a <=( a965a ) or ( a958a );
a970a <=( a170a ) or ( a171a );
a971a <=( a172a ) or ( a970a );
a974a <=( a168a ) or ( a169a );
a977a <=( a166a ) or ( a167a );
a978a <=( a977a ) or ( a974a );
a979a <=( a978a ) or ( a971a );
a980a <=( a979a ) or ( a966a );
a981a <=( a980a ) or ( a953a );
a982a <=( a981a ) or ( a928a );
a986a <=( a163a ) or ( a164a );
a987a <=( a165a ) or ( a986a );
a991a <=( a160a ) or ( a161a );
a992a <=( a162a ) or ( a991a );
a993a <=( a992a ) or ( a987a );
a997a <=( a157a ) or ( a158a );
a998a <=( a159a ) or ( a997a );
a1001a <=( a155a ) or ( a156a );
a1004a <=( a153a ) or ( a154a );
a1005a <=( a1004a ) or ( a1001a );
a1006a <=( a1005a ) or ( a998a );
a1007a <=( a1006a ) or ( a993a );
a1011a <=( a150a ) or ( a151a );
a1012a <=( a152a ) or ( a1011a );
a1015a <=( a148a ) or ( a149a );
a1018a <=( a146a ) or ( a147a );
a1019a <=( a1018a ) or ( a1015a );
a1020a <=( a1019a ) or ( a1012a );
a1024a <=( a143a ) or ( a144a );
a1025a <=( a145a ) or ( a1024a );
a1028a <=( a141a ) or ( a142a );
a1031a <=( a139a ) or ( a140a );
a1032a <=( a1031a ) or ( a1028a );
a1033a <=( a1032a ) or ( a1025a );
a1034a <=( a1033a ) or ( a1020a );
a1035a <=( a1034a ) or ( a1007a );
a1039a <=( a136a ) or ( a137a );
a1040a <=( a138a ) or ( a1039a );
a1043a <=( a134a ) or ( a135a );
a1046a <=( a132a ) or ( a133a );
a1047a <=( a1046a ) or ( a1043a );
a1048a <=( a1047a ) or ( a1040a );
a1052a <=( a129a ) or ( a130a );
a1053a <=( a131a ) or ( a1052a );
a1056a <=( a127a ) or ( a128a );
a1059a <=( a125a ) or ( a126a );
a1060a <=( a1059a ) or ( a1056a );
a1061a <=( a1060a ) or ( a1053a );
a1062a <=( a1061a ) or ( a1048a );
a1066a <=( a122a ) or ( a123a );
a1067a <=( a124a ) or ( a1066a );
a1070a <=( a120a ) or ( a121a );
a1073a <=( a118a ) or ( a119a );
a1074a <=( a1073a ) or ( a1070a );
a1075a <=( a1074a ) or ( a1067a );
a1079a <=( a115a ) or ( a116a );
a1080a <=( a117a ) or ( a1079a );
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a1086a <=( a111a ) or ( a112a );
a1087a <=( a1086a ) or ( a1083a );
a1088a <=( a1087a ) or ( a1080a );
a1089a <=( a1088a ) or ( a1075a );
a1090a <=( a1089a ) or ( a1062a );
a1091a <=( a1090a ) or ( a1035a );
a1092a <=( a1091a ) or ( a982a );
a1096a <=( a108a ) or ( a109a );
a1097a <=( a110a ) or ( a1096a );
a1101a <=( a105a ) or ( a106a );
a1102a <=( a107a ) or ( a1101a );
a1103a <=( a1102a ) or ( a1097a );
a1107a <=( a102a ) or ( a103a );
a1108a <=( a104a ) or ( a1107a );
a1111a <=( a100a ) or ( a101a );
a1114a <=( a98a ) or ( a99a );
a1115a <=( a1114a ) or ( a1111a );
a1116a <=( a1115a ) or ( a1108a );
a1117a <=( a1116a ) or ( a1103a );
a1121a <=( a95a ) or ( a96a );
a1122a <=( a97a ) or ( a1121a );
a1125a <=( a93a ) or ( a94a );
a1128a <=( a91a ) or ( a92a );
a1129a <=( a1128a ) or ( a1125a );
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a1135a <=( a90a ) or ( a1134a );
a1138a <=( a86a ) or ( a87a );
a1141a <=( a84a ) or ( a85a );
a1142a <=( a1141a ) or ( a1138a );
a1143a <=( a1142a ) or ( a1135a );
a1144a <=( a1143a ) or ( a1130a );
a1145a <=( a1144a ) or ( a1117a );
a1149a <=( a81a ) or ( a82a );
a1150a <=( a83a ) or ( a1149a );
a1153a <=( a79a ) or ( a80a );
a1156a <=( a77a ) or ( a78a );
a1157a <=( a1156a ) or ( a1153a );
a1158a <=( a1157a ) or ( a1150a );
a1162a <=( a74a ) or ( a75a );
a1163a <=( a76a ) or ( a1162a );
a1166a <=( a72a ) or ( a73a );
a1169a <=( a70a ) or ( a71a );
a1170a <=( a1169a ) or ( a1166a );
a1171a <=( a1170a ) or ( a1163a );
a1172a <=( a1171a ) or ( a1158a );
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a1177a <=( a69a ) or ( a1176a );
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a1183a <=( a63a ) or ( a64a );
a1184a <=( a1183a ) or ( a1180a );
a1185a <=( a1184a ) or ( a1177a );
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a1190a <=( a62a ) or ( a1189a );
a1193a <=( a58a ) or ( a59a );
a1196a <=( a56a ) or ( a57a );
a1197a <=( a1196a ) or ( a1193a );
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a1200a <=( a1199a ) or ( a1172a );
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a1206a <=( a55a ) or ( a1205a );
a1210a <=( a50a ) or ( a51a );
a1211a <=( a52a ) or ( a1210a );
a1212a <=( a1211a ) or ( a1206a );
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a1217a <=( a49a ) or ( a1216a );
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a1225a <=( a1224a ) or ( a1217a );
a1226a <=( a1225a ) or ( a1212a );
a1230a <=( a40a ) or ( a41a );
a1231a <=( a42a ) or ( a1230a );
a1234a <=( a38a ) or ( a39a );
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a1238a <=( a1237a ) or ( a1234a );
a1239a <=( a1238a ) or ( a1231a );
a1243a <=( a33a ) or ( a34a );
a1244a <=( a35a ) or ( a1243a );
a1247a <=( a31a ) or ( a32a );
a1250a <=( a29a ) or ( a30a );
a1251a <=( a1250a ) or ( a1247a );
a1252a <=( a1251a ) or ( a1244a );
a1253a <=( a1252a ) or ( a1239a );
a1254a <=( a1253a ) or ( a1226a );
a1258a <=( a26a ) or ( a27a );
a1259a <=( a28a ) or ( a1258a );
a1262a <=( a24a ) or ( a25a );
a1265a <=( a22a ) or ( a23a );
a1266a <=( a1265a ) or ( a1262a );
a1267a <=( a1266a ) or ( a1259a );
a1271a <=( a19a ) or ( a20a );
a1272a <=( a21a ) or ( a1271a );
a1275a <=( a17a ) or ( a18a );
a1278a <=( a15a ) or ( a16a );
a1279a <=( a1278a ) or ( a1275a );
a1280a <=( a1279a ) or ( a1272a );
a1281a <=( a1280a ) or ( a1267a );
a1285a <=( a12a ) or ( a13a );
a1286a <=( a14a ) or ( a1285a );
a1289a <=( a10a ) or ( a11a );
a1292a <=( a8a ) or ( a9a );
a1293a <=( a1292a ) or ( a1289a );
a1294a <=( a1293a ) or ( a1286a );
a1298a <=( a5a ) or ( a6a );
a1299a <=( a7a ) or ( a1298a );
a1302a <=( a3a ) or ( a4a );
a1305a <=( a1a ) or ( a2a );
a1306a <=( a1305a ) or ( a1302a );
a1307a <=( a1306a ) or ( a1299a );
a1308a <=( a1307a ) or ( a1294a );
a1309a <=( a1308a ) or ( a1281a );
a1310a <=( a1309a ) or ( a1254a );
a1311a <=( a1310a ) or ( a1201a );
a1312a <=( a1311a ) or ( a1092a );
a1315a <=( A200 and (not A199) );
a1318a <=( A202 and A201 );
a1321a <=( A200 and (not A199) );
a1324a <=( (not A203) and A201 );
a1327a <=( (not A200) and A199 );
a1330a <=( A202 and A201 );
a1333a <=( (not A200) and A199 );
a1336a <=( (not A203) and A201 );
a1339a <=( A200 and (not A199) );
a1343a <=( A203 and (not A202) );
a1344a <=( (not A201) and a1343a );
a1347a <=( (not A200) and A199 );
a1351a <=( A203 and (not A202) );
a1352a <=( (not A201) and a1351a );
a1355a <=( A233 and (not A232) );
a1358a <=( A235 and A234 );
a1359a <=( a1358a and a1355a );
a1362a <=( (not A299) and A298 );
a1365a <=( A301 and A300 );
a1366a <=( a1365a and a1362a );
a1369a <=( A233 and (not A232) );
a1372a <=( A235 and A234 );
a1373a <=( a1372a and a1369a );
a1376a <=( (not A299) and A298 );
a1379a <=( (not A302) and A300 );
a1380a <=( a1379a and a1376a );
a1383a <=( A233 and (not A232) );
a1386a <=( A235 and A234 );
a1387a <=( a1386a and a1383a );
a1390a <=( A299 and (not A298) );
a1393a <=( A301 and A300 );
a1394a <=( a1393a and a1390a );
a1397a <=( A233 and (not A232) );
a1400a <=( A235 and A234 );
a1401a <=( a1400a and a1397a );
a1404a <=( A299 and (not A298) );
a1407a <=( (not A302) and A300 );
a1408a <=( a1407a and a1404a );
a1411a <=( A233 and (not A232) );
a1414a <=( A235 and A234 );
a1415a <=( a1414a and a1411a );
a1418a <=( A266 and (not A265) );
a1421a <=( A268 and A267 );
a1422a <=( a1421a and a1418a );
a1425a <=( A233 and (not A232) );
a1428a <=( A235 and A234 );
a1429a <=( a1428a and a1425a );
a1432a <=( A266 and (not A265) );
a1435a <=( (not A269) and A267 );
a1436a <=( a1435a and a1432a );
a1439a <=( A233 and (not A232) );
a1442a <=( A235 and A234 );
a1443a <=( a1442a and a1439a );
a1446a <=( (not A266) and A265 );
a1449a <=( A268 and A267 );
a1450a <=( a1449a and a1446a );
a1453a <=( A233 and (not A232) );
a1456a <=( A235 and A234 );
a1457a <=( a1456a and a1453a );
a1460a <=( (not A266) and A265 );
a1463a <=( (not A269) and A267 );
a1464a <=( a1463a and a1460a );
a1467a <=( A233 and (not A232) );
a1470a <=( (not A236) and A234 );
a1471a <=( a1470a and a1467a );
a1474a <=( (not A299) and A298 );
a1477a <=( A301 and A300 );
a1478a <=( a1477a and a1474a );
a1481a <=( A233 and (not A232) );
a1484a <=( (not A236) and A234 );
a1485a <=( a1484a and a1481a );
a1488a <=( (not A299) and A298 );
a1491a <=( (not A302) and A300 );
a1492a <=( a1491a and a1488a );
a1495a <=( A233 and (not A232) );
a1498a <=( (not A236) and A234 );
a1499a <=( a1498a and a1495a );
a1502a <=( A299 and (not A298) );
a1505a <=( A301 and A300 );
a1506a <=( a1505a and a1502a );
a1509a <=( A233 and (not A232) );
a1512a <=( (not A236) and A234 );
a1513a <=( a1512a and a1509a );
a1516a <=( A299 and (not A298) );
a1519a <=( (not A302) and A300 );
a1520a <=( a1519a and a1516a );
a1523a <=( A233 and (not A232) );
a1526a <=( (not A236) and A234 );
a1527a <=( a1526a and a1523a );
a1530a <=( A266 and (not A265) );
a1533a <=( A268 and A267 );
a1534a <=( a1533a and a1530a );
a1537a <=( A233 and (not A232) );
a1540a <=( (not A236) and A234 );
a1541a <=( a1540a and a1537a );
a1544a <=( A266 and (not A265) );
a1547a <=( (not A269) and A267 );
a1548a <=( a1547a and a1544a );
a1551a <=( A233 and (not A232) );
a1554a <=( (not A236) and A234 );
a1555a <=( a1554a and a1551a );
a1558a <=( (not A266) and A265 );
a1561a <=( A268 and A267 );
a1562a <=( a1561a and a1558a );
a1565a <=( A233 and (not A232) );
a1568a <=( (not A236) and A234 );
a1569a <=( a1568a and a1565a );
a1572a <=( (not A266) and A265 );
a1575a <=( (not A269) and A267 );
a1576a <=( a1575a and a1572a );
a1579a <=( (not A233) and A232 );
a1582a <=( A235 and A234 );
a1583a <=( a1582a and a1579a );
a1586a <=( (not A299) and A298 );
a1589a <=( A301 and A300 );
a1590a <=( a1589a and a1586a );
a1593a <=( (not A233) and A232 );
a1596a <=( A235 and A234 );
a1597a <=( a1596a and a1593a );
a1600a <=( (not A299) and A298 );
a1603a <=( (not A302) and A300 );
a1604a <=( a1603a and a1600a );
a1607a <=( (not A233) and A232 );
a1610a <=( A235 and A234 );
a1611a <=( a1610a and a1607a );
a1614a <=( A299 and (not A298) );
a1617a <=( A301 and A300 );
a1618a <=( a1617a and a1614a );
a1621a <=( (not A233) and A232 );
a1624a <=( A235 and A234 );
a1625a <=( a1624a and a1621a );
a1628a <=( A299 and (not A298) );
a1631a <=( (not A302) and A300 );
a1632a <=( a1631a and a1628a );
a1635a <=( (not A233) and A232 );
a1638a <=( A235 and A234 );
a1639a <=( a1638a and a1635a );
a1642a <=( A266 and (not A265) );
a1645a <=( A268 and A267 );
a1646a <=( a1645a and a1642a );
a1649a <=( (not A233) and A232 );
a1652a <=( A235 and A234 );
a1653a <=( a1652a and a1649a );
a1656a <=( A266 and (not A265) );
a1659a <=( (not A269) and A267 );
a1660a <=( a1659a and a1656a );
a1663a <=( (not A233) and A232 );
a1666a <=( A235 and A234 );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A266) and A265 );
a1673a <=( A268 and A267 );
a1674a <=( a1673a and a1670a );
a1677a <=( (not A233) and A232 );
a1680a <=( A235 and A234 );
a1681a <=( a1680a and a1677a );
a1684a <=( (not A266) and A265 );
a1687a <=( (not A269) and A267 );
a1688a <=( a1687a and a1684a );
a1691a <=( (not A233) and A232 );
a1694a <=( (not A236) and A234 );
a1695a <=( a1694a and a1691a );
a1698a <=( (not A299) and A298 );
a1701a <=( A301 and A300 );
a1702a <=( a1701a and a1698a );
a1705a <=( (not A233) and A232 );
a1708a <=( (not A236) and A234 );
a1709a <=( a1708a and a1705a );
a1712a <=( (not A299) and A298 );
a1715a <=( (not A302) and A300 );
a1716a <=( a1715a and a1712a );
a1719a <=( (not A233) and A232 );
a1722a <=( (not A236) and A234 );
a1723a <=( a1722a and a1719a );
a1726a <=( A299 and (not A298) );
a1729a <=( A301 and A300 );
a1730a <=( a1729a and a1726a );
a1733a <=( (not A233) and A232 );
a1736a <=( (not A236) and A234 );
a1737a <=( a1736a and a1733a );
a1740a <=( A299 and (not A298) );
a1743a <=( (not A302) and A300 );
a1744a <=( a1743a and a1740a );
a1747a <=( (not A233) and A232 );
a1750a <=( (not A236) and A234 );
a1751a <=( a1750a and a1747a );
a1754a <=( A266 and (not A265) );
a1757a <=( A268 and A267 );
a1758a <=( a1757a and a1754a );
a1761a <=( (not A233) and A232 );
a1764a <=( (not A236) and A234 );
a1765a <=( a1764a and a1761a );
a1768a <=( A266 and (not A265) );
a1771a <=( (not A269) and A267 );
a1772a <=( a1771a and a1768a );
a1775a <=( (not A233) and A232 );
a1778a <=( (not A236) and A234 );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A266) and A265 );
a1785a <=( A268 and A267 );
a1786a <=( a1785a and a1782a );
a1789a <=( (not A233) and A232 );
a1792a <=( (not A236) and A234 );
a1793a <=( a1792a and a1789a );
a1796a <=( (not A266) and A265 );
a1799a <=( (not A269) and A267 );
a1800a <=( a1799a and a1796a );
a1803a <=( A233 and (not A232) );
a1806a <=( A235 and A234 );
a1807a <=( a1806a and a1803a );
a1810a <=( (not A299) and A298 );
a1814a <=( A302 and (not A301) );
a1815a <=( (not A300) and a1814a );
a1816a <=( a1815a and a1810a );
a1819a <=( A233 and (not A232) );
a1822a <=( A235 and A234 );
a1823a <=( a1822a and a1819a );
a1826a <=( A299 and (not A298) );
a1830a <=( A302 and (not A301) );
a1831a <=( (not A300) and a1830a );
a1832a <=( a1831a and a1826a );
a1835a <=( A233 and (not A232) );
a1838a <=( A235 and A234 );
a1839a <=( a1838a and a1835a );
a1842a <=( A266 and (not A265) );
a1846a <=( A269 and (not A268) );
a1847a <=( (not A267) and a1846a );
a1848a <=( a1847a and a1842a );
a1851a <=( A233 and (not A232) );
a1854a <=( A235 and A234 );
a1855a <=( a1854a and a1851a );
a1858a <=( (not A266) and A265 );
a1862a <=( A269 and (not A268) );
a1863a <=( (not A267) and a1862a );
a1864a <=( a1863a and a1858a );
a1867a <=( A233 and (not A232) );
a1870a <=( (not A236) and A234 );
a1871a <=( a1870a and a1867a );
a1874a <=( (not A299) and A298 );
a1878a <=( A302 and (not A301) );
a1879a <=( (not A300) and a1878a );
a1880a <=( a1879a and a1874a );
a1883a <=( A233 and (not A232) );
a1886a <=( (not A236) and A234 );
a1887a <=( a1886a and a1883a );
a1890a <=( A299 and (not A298) );
a1894a <=( A302 and (not A301) );
a1895a <=( (not A300) and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A233 and (not A232) );
a1902a <=( (not A236) and A234 );
a1903a <=( a1902a and a1899a );
a1906a <=( A266 and (not A265) );
a1910a <=( A269 and (not A268) );
a1911a <=( (not A267) and a1910a );
a1912a <=( a1911a and a1906a );
a1915a <=( A233 and (not A232) );
a1918a <=( (not A236) and A234 );
a1919a <=( a1918a and a1915a );
a1922a <=( (not A266) and A265 );
a1926a <=( A269 and (not A268) );
a1927a <=( (not A267) and a1926a );
a1928a <=( a1927a and a1922a );
a1931a <=( A233 and (not A232) );
a1934a <=( (not A235) and (not A234) );
a1935a <=( a1934a and a1931a );
a1938a <=( A298 and A236 );
a1942a <=( A301 and A300 );
a1943a <=( (not A299) and a1942a );
a1944a <=( a1943a and a1938a );
a1947a <=( A233 and (not A232) );
a1950a <=( (not A235) and (not A234) );
a1951a <=( a1950a and a1947a );
a1954a <=( A298 and A236 );
a1958a <=( (not A302) and A300 );
a1959a <=( (not A299) and a1958a );
a1960a <=( a1959a and a1954a );
a1963a <=( A233 and (not A232) );
a1966a <=( (not A235) and (not A234) );
a1967a <=( a1966a and a1963a );
a1970a <=( (not A298) and A236 );
a1974a <=( A301 and A300 );
a1975a <=( A299 and a1974a );
a1976a <=( a1975a and a1970a );
a1979a <=( A233 and (not A232) );
a1982a <=( (not A235) and (not A234) );
a1983a <=( a1982a and a1979a );
a1986a <=( (not A298) and A236 );
a1990a <=( (not A302) and A300 );
a1991a <=( A299 and a1990a );
a1992a <=( a1991a and a1986a );
a1995a <=( A233 and (not A232) );
a1998a <=( (not A235) and (not A234) );
a1999a <=( a1998a and a1995a );
a2002a <=( (not A265) and A236 );
a2006a <=( A268 and A267 );
a2007a <=( A266 and a2006a );
a2008a <=( a2007a and a2002a );
a2011a <=( A233 and (not A232) );
a2014a <=( (not A235) and (not A234) );
a2015a <=( a2014a and a2011a );
a2018a <=( (not A265) and A236 );
a2022a <=( (not A269) and A267 );
a2023a <=( A266 and a2022a );
a2024a <=( a2023a and a2018a );
a2027a <=( A233 and (not A232) );
a2030a <=( (not A235) and (not A234) );
a2031a <=( a2030a and a2027a );
a2034a <=( A265 and A236 );
a2038a <=( A268 and A267 );
a2039a <=( (not A266) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( A233 and (not A232) );
a2046a <=( (not A235) and (not A234) );
a2047a <=( a2046a and a2043a );
a2050a <=( A265 and A236 );
a2054a <=( (not A269) and A267 );
a2055a <=( (not A266) and a2054a );
a2056a <=( a2055a and a2050a );
a2059a <=( (not A233) and A232 );
a2062a <=( A235 and A234 );
a2063a <=( a2062a and a2059a );
a2066a <=( (not A299) and A298 );
a2070a <=( A302 and (not A301) );
a2071a <=( (not A300) and a2070a );
a2072a <=( a2071a and a2066a );
a2075a <=( (not A233) and A232 );
a2078a <=( A235 and A234 );
a2079a <=( a2078a and a2075a );
a2082a <=( A299 and (not A298) );
a2086a <=( A302 and (not A301) );
a2087a <=( (not A300) and a2086a );
a2088a <=( a2087a and a2082a );
a2091a <=( (not A233) and A232 );
a2094a <=( A235 and A234 );
a2095a <=( a2094a and a2091a );
a2098a <=( A266 and (not A265) );
a2102a <=( A269 and (not A268) );
a2103a <=( (not A267) and a2102a );
a2104a <=( a2103a and a2098a );
a2107a <=( (not A233) and A232 );
a2110a <=( A235 and A234 );
a2111a <=( a2110a and a2107a );
a2114a <=( (not A266) and A265 );
a2118a <=( A269 and (not A268) );
a2119a <=( (not A267) and a2118a );
a2120a <=( a2119a and a2114a );
a2123a <=( (not A233) and A232 );
a2126a <=( (not A236) and A234 );
a2127a <=( a2126a and a2123a );
a2130a <=( (not A299) and A298 );
a2134a <=( A302 and (not A301) );
a2135a <=( (not A300) and a2134a );
a2136a <=( a2135a and a2130a );
a2139a <=( (not A233) and A232 );
a2142a <=( (not A236) and A234 );
a2143a <=( a2142a and a2139a );
a2146a <=( A299 and (not A298) );
a2150a <=( A302 and (not A301) );
a2151a <=( (not A300) and a2150a );
a2152a <=( a2151a and a2146a );
a2155a <=( (not A233) and A232 );
a2158a <=( (not A236) and A234 );
a2159a <=( a2158a and a2155a );
a2162a <=( A266 and (not A265) );
a2166a <=( A269 and (not A268) );
a2167a <=( (not A267) and a2166a );
a2168a <=( a2167a and a2162a );
a2171a <=( (not A233) and A232 );
a2174a <=( (not A236) and A234 );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A266) and A265 );
a2182a <=( A269 and (not A268) );
a2183a <=( (not A267) and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( (not A233) and A232 );
a2190a <=( (not A235) and (not A234) );
a2191a <=( a2190a and a2187a );
a2194a <=( A298 and A236 );
a2198a <=( A301 and A300 );
a2199a <=( (not A299) and a2198a );
a2200a <=( a2199a and a2194a );
a2203a <=( (not A233) and A232 );
a2206a <=( (not A235) and (not A234) );
a2207a <=( a2206a and a2203a );
a2210a <=( A298 and A236 );
a2214a <=( (not A302) and A300 );
a2215a <=( (not A299) and a2214a );
a2216a <=( a2215a and a2210a );
a2219a <=( (not A233) and A232 );
a2222a <=( (not A235) and (not A234) );
a2223a <=( a2222a and a2219a );
a2226a <=( (not A298) and A236 );
a2230a <=( A301 and A300 );
a2231a <=( A299 and a2230a );
a2232a <=( a2231a and a2226a );
a2235a <=( (not A233) and A232 );
a2238a <=( (not A235) and (not A234) );
a2239a <=( a2238a and a2235a );
a2242a <=( (not A298) and A236 );
a2246a <=( (not A302) and A300 );
a2247a <=( A299 and a2246a );
a2248a <=( a2247a and a2242a );
a2251a <=( (not A233) and A232 );
a2254a <=( (not A235) and (not A234) );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A265) and A236 );
a2262a <=( A268 and A267 );
a2263a <=( A266 and a2262a );
a2264a <=( a2263a and a2258a );
a2267a <=( (not A233) and A232 );
a2270a <=( (not A235) and (not A234) );
a2271a <=( a2270a and a2267a );
a2274a <=( (not A265) and A236 );
a2278a <=( (not A269) and A267 );
a2279a <=( A266 and a2278a );
a2280a <=( a2279a and a2274a );
a2283a <=( (not A233) and A232 );
a2286a <=( (not A235) and (not A234) );
a2287a <=( a2286a and a2283a );
a2290a <=( A265 and A236 );
a2294a <=( A268 and A267 );
a2295a <=( (not A266) and a2294a );
a2296a <=( a2295a and a2290a );
a2299a <=( (not A233) and A232 );
a2302a <=( (not A235) and (not A234) );
a2303a <=( a2302a and a2299a );
a2306a <=( A265 and A236 );
a2310a <=( (not A269) and A267 );
a2311a <=( (not A266) and a2310a );
a2312a <=( a2311a and a2306a );
a2315a <=( A233 and (not A232) );
a2319a <=( A236 and (not A235) );
a2320a <=( (not A234) and a2319a );
a2321a <=( a2320a and a2315a );
a2324a <=( (not A299) and A298 );
a2328a <=( A302 and (not A301) );
a2329a <=( (not A300) and a2328a );
a2330a <=( a2329a and a2324a );
a2333a <=( A233 and (not A232) );
a2337a <=( A236 and (not A235) );
a2338a <=( (not A234) and a2337a );
a2339a <=( a2338a and a2333a );
a2342a <=( A299 and (not A298) );
a2346a <=( A302 and (not A301) );
a2347a <=( (not A300) and a2346a );
a2348a <=( a2347a and a2342a );
a2351a <=( A233 and (not A232) );
a2355a <=( A236 and (not A235) );
a2356a <=( (not A234) and a2355a );
a2357a <=( a2356a and a2351a );
a2360a <=( A266 and (not A265) );
a2364a <=( A269 and (not A268) );
a2365a <=( (not A267) and a2364a );
a2366a <=( a2365a and a2360a );
a2369a <=( A233 and (not A232) );
a2373a <=( A236 and (not A235) );
a2374a <=( (not A234) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A266) and A265 );
a2382a <=( A269 and (not A268) );
a2383a <=( (not A267) and a2382a );
a2384a <=( a2383a and a2378a );
a2387a <=( (not A233) and A232 );
a2391a <=( A236 and (not A235) );
a2392a <=( (not A234) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( (not A299) and A298 );
a2400a <=( A302 and (not A301) );
a2401a <=( (not A300) and a2400a );
a2402a <=( a2401a and a2396a );
a2405a <=( (not A233) and A232 );
a2409a <=( A236 and (not A235) );
a2410a <=( (not A234) and a2409a );
a2411a <=( a2410a and a2405a );
a2414a <=( A299 and (not A298) );
a2418a <=( A302 and (not A301) );
a2419a <=( (not A300) and a2418a );
a2420a <=( a2419a and a2414a );
a2423a <=( (not A233) and A232 );
a2427a <=( A236 and (not A235) );
a2428a <=( (not A234) and a2427a );
a2429a <=( a2428a and a2423a );
a2432a <=( A266 and (not A265) );
a2436a <=( A269 and (not A268) );
a2437a <=( (not A267) and a2436a );
a2438a <=( a2437a and a2432a );
a2441a <=( (not A233) and A232 );
a2445a <=( A236 and (not A235) );
a2446a <=( (not A234) and a2445a );
a2447a <=( a2446a and a2441a );
a2450a <=( (not A266) and A265 );
a2454a <=( A269 and (not A268) );
a2455a <=( (not A267) and a2454a );
a2456a <=( a2455a and a2450a );
a2459a <=( A168 and A170 );
a2463a <=( (not A267) and (not A166) );
a2464a <=( A167 and a2463a );
a2465a <=( a2464a and a2459a );
a2468a <=( A298 and A268 );
a2472a <=( A301 and A300 );
a2473a <=( (not A299) and a2472a );
a2474a <=( a2473a and a2468a );
a2477a <=( A168 and A170 );
a2481a <=( (not A267) and (not A166) );
a2482a <=( A167 and a2481a );
a2483a <=( a2482a and a2477a );
a2486a <=( A298 and A268 );
a2490a <=( (not A302) and A300 );
a2491a <=( (not A299) and a2490a );
a2492a <=( a2491a and a2486a );
a2495a <=( A168 and A170 );
a2499a <=( (not A267) and (not A166) );
a2500a <=( A167 and a2499a );
a2501a <=( a2500a and a2495a );
a2504a <=( (not A298) and A268 );
a2508a <=( A301 and A300 );
a2509a <=( A299 and a2508a );
a2510a <=( a2509a and a2504a );
a2513a <=( A168 and A170 );
a2517a <=( (not A267) and (not A166) );
a2518a <=( A167 and a2517a );
a2519a <=( a2518a and a2513a );
a2522a <=( (not A298) and A268 );
a2526a <=( (not A302) and A300 );
a2527a <=( A299 and a2526a );
a2528a <=( a2527a and a2522a );
a2531a <=( A168 and A170 );
a2535a <=( (not A267) and (not A166) );
a2536a <=( A167 and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( A298 and (not A269) );
a2544a <=( A301 and A300 );
a2545a <=( (not A299) and a2544a );
a2546a <=( a2545a and a2540a );
a2549a <=( A168 and A170 );
a2553a <=( (not A267) and (not A166) );
a2554a <=( A167 and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A298 and (not A269) );
a2562a <=( (not A302) and A300 );
a2563a <=( (not A299) and a2562a );
a2564a <=( a2563a and a2558a );
a2567a <=( A168 and A170 );
a2571a <=( (not A267) and (not A166) );
a2572a <=( A167 and a2571a );
a2573a <=( a2572a and a2567a );
a2576a <=( (not A298) and (not A269) );
a2580a <=( A301 and A300 );
a2581a <=( A299 and a2580a );
a2582a <=( a2581a and a2576a );
a2585a <=( A168 and A170 );
a2589a <=( (not A267) and (not A166) );
a2590a <=( A167 and a2589a );
a2591a <=( a2590a and a2585a );
a2594a <=( (not A298) and (not A269) );
a2598a <=( (not A302) and A300 );
a2599a <=( A299 and a2598a );
a2600a <=( a2599a and a2594a );
a2603a <=( A168 and A170 );
a2607a <=( A265 and (not A166) );
a2608a <=( A167 and a2607a );
a2609a <=( a2608a and a2603a );
a2612a <=( A298 and A266 );
a2616a <=( A301 and A300 );
a2617a <=( (not A299) and a2616a );
a2618a <=( a2617a and a2612a );
a2621a <=( A168 and A170 );
a2625a <=( A265 and (not A166) );
a2626a <=( A167 and a2625a );
a2627a <=( a2626a and a2621a );
a2630a <=( A298 and A266 );
a2634a <=( (not A302) and A300 );
a2635a <=( (not A299) and a2634a );
a2636a <=( a2635a and a2630a );
a2639a <=( A168 and A170 );
a2643a <=( A265 and (not A166) );
a2644a <=( A167 and a2643a );
a2645a <=( a2644a and a2639a );
a2648a <=( (not A298) and A266 );
a2652a <=( A301 and A300 );
a2653a <=( A299 and a2652a );
a2654a <=( a2653a and a2648a );
a2657a <=( A168 and A170 );
a2661a <=( A265 and (not A166) );
a2662a <=( A167 and a2661a );
a2663a <=( a2662a and a2657a );
a2666a <=( (not A298) and A266 );
a2670a <=( (not A302) and A300 );
a2671a <=( A299 and a2670a );
a2672a <=( a2671a and a2666a );
a2675a <=( A168 and A170 );
a2679a <=( (not A265) and (not A166) );
a2680a <=( A167 and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( A267 and A266 );
a2688a <=( A301 and (not A300) );
a2689a <=( A268 and a2688a );
a2690a <=( a2689a and a2684a );
a2693a <=( A168 and A170 );
a2697a <=( (not A265) and (not A166) );
a2698a <=( A167 and a2697a );
a2699a <=( a2698a and a2693a );
a2702a <=( A267 and A266 );
a2706a <=( (not A302) and (not A300) );
a2707a <=( A268 and a2706a );
a2708a <=( a2707a and a2702a );
a2711a <=( A168 and A170 );
a2715a <=( (not A265) and (not A166) );
a2716a <=( A167 and a2715a );
a2717a <=( a2716a and a2711a );
a2720a <=( A267 and A266 );
a2724a <=( A299 and A298 );
a2725a <=( A268 and a2724a );
a2726a <=( a2725a and a2720a );
a2729a <=( A168 and A170 );
a2733a <=( (not A265) and (not A166) );
a2734a <=( A167 and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( A267 and A266 );
a2742a <=( (not A299) and (not A298) );
a2743a <=( A268 and a2742a );
a2744a <=( a2743a and a2738a );
a2747a <=( A168 and A170 );
a2751a <=( (not A265) and (not A166) );
a2752a <=( A167 and a2751a );
a2753a <=( a2752a and a2747a );
a2756a <=( A267 and A266 );
a2760a <=( A301 and (not A300) );
a2761a <=( (not A269) and a2760a );
a2762a <=( a2761a and a2756a );
a2765a <=( A168 and A170 );
a2769a <=( (not A265) and (not A166) );
a2770a <=( A167 and a2769a );
a2771a <=( a2770a and a2765a );
a2774a <=( A267 and A266 );
a2778a <=( (not A302) and (not A300) );
a2779a <=( (not A269) and a2778a );
a2780a <=( a2779a and a2774a );
a2783a <=( A168 and A170 );
a2787a <=( (not A265) and (not A166) );
a2788a <=( A167 and a2787a );
a2789a <=( a2788a and a2783a );
a2792a <=( A267 and A266 );
a2796a <=( A299 and A298 );
a2797a <=( (not A269) and a2796a );
a2798a <=( a2797a and a2792a );
a2801a <=( A168 and A170 );
a2805a <=( (not A265) and (not A166) );
a2806a <=( A167 and a2805a );
a2807a <=( a2806a and a2801a );
a2810a <=( A267 and A266 );
a2814a <=( (not A299) and (not A298) );
a2815a <=( (not A269) and a2814a );
a2816a <=( a2815a and a2810a );
a2819a <=( A168 and A170 );
a2823a <=( A265 and (not A166) );
a2824a <=( A167 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( A267 and (not A266) );
a2832a <=( A301 and (not A300) );
a2833a <=( A268 and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( A168 and A170 );
a2841a <=( A265 and (not A166) );
a2842a <=( A167 and a2841a );
a2843a <=( a2842a and a2837a );
a2846a <=( A267 and (not A266) );
a2850a <=( (not A302) and (not A300) );
a2851a <=( A268 and a2850a );
a2852a <=( a2851a and a2846a );
a2855a <=( A168 and A170 );
a2859a <=( A265 and (not A166) );
a2860a <=( A167 and a2859a );
a2861a <=( a2860a and a2855a );
a2864a <=( A267 and (not A266) );
a2868a <=( A299 and A298 );
a2869a <=( A268 and a2868a );
a2870a <=( a2869a and a2864a );
a2873a <=( A168 and A170 );
a2877a <=( A265 and (not A166) );
a2878a <=( A167 and a2877a );
a2879a <=( a2878a and a2873a );
a2882a <=( A267 and (not A266) );
a2886a <=( (not A299) and (not A298) );
a2887a <=( A268 and a2886a );
a2888a <=( a2887a and a2882a );
a2891a <=( A168 and A170 );
a2895a <=( A265 and (not A166) );
a2896a <=( A167 and a2895a );
a2897a <=( a2896a and a2891a );
a2900a <=( A267 and (not A266) );
a2904a <=( A301 and (not A300) );
a2905a <=( (not A269) and a2904a );
a2906a <=( a2905a and a2900a );
a2909a <=( A168 and A170 );
a2913a <=( A265 and (not A166) );
a2914a <=( A167 and a2913a );
a2915a <=( a2914a and a2909a );
a2918a <=( A267 and (not A266) );
a2922a <=( (not A302) and (not A300) );
a2923a <=( (not A269) and a2922a );
a2924a <=( a2923a and a2918a );
a2927a <=( A168 and A170 );
a2931a <=( A265 and (not A166) );
a2932a <=( A167 and a2931a );
a2933a <=( a2932a and a2927a );
a2936a <=( A267 and (not A266) );
a2940a <=( A299 and A298 );
a2941a <=( (not A269) and a2940a );
a2942a <=( a2941a and a2936a );
a2945a <=( A168 and A170 );
a2949a <=( A265 and (not A166) );
a2950a <=( A167 and a2949a );
a2951a <=( a2950a and a2945a );
a2954a <=( A267 and (not A266) );
a2958a <=( (not A299) and (not A298) );
a2959a <=( (not A269) and a2958a );
a2960a <=( a2959a and a2954a );
a2963a <=( A168 and A170 );
a2967a <=( (not A265) and (not A166) );
a2968a <=( A167 and a2967a );
a2969a <=( a2968a and a2963a );
a2972a <=( A298 and (not A266) );
a2976a <=( A301 and A300 );
a2977a <=( (not A299) and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and A170 );
a2985a <=( (not A265) and (not A166) );
a2986a <=( A167 and a2985a );
a2987a <=( a2986a and a2981a );
a2990a <=( A298 and (not A266) );
a2994a <=( (not A302) and A300 );
a2995a <=( (not A299) and a2994a );
a2996a <=( a2995a and a2990a );
a2999a <=( A168 and A170 );
a3003a <=( (not A265) and (not A166) );
a3004a <=( A167 and a3003a );
a3005a <=( a3004a and a2999a );
a3008a <=( (not A298) and (not A266) );
a3012a <=( A301 and A300 );
a3013a <=( A299 and a3012a );
a3014a <=( a3013a and a3008a );
a3017a <=( A168 and A170 );
a3021a <=( (not A265) and (not A166) );
a3022a <=( A167 and a3021a );
a3023a <=( a3022a and a3017a );
a3026a <=( (not A298) and (not A266) );
a3030a <=( (not A302) and A300 );
a3031a <=( A299 and a3030a );
a3032a <=( a3031a and a3026a );
a3035a <=( A168 and A170 );
a3039a <=( (not A267) and A166 );
a3040a <=( (not A167) and a3039a );
a3041a <=( a3040a and a3035a );
a3044a <=( A298 and A268 );
a3048a <=( A301 and A300 );
a3049a <=( (not A299) and a3048a );
a3050a <=( a3049a and a3044a );
a3053a <=( A168 and A170 );
a3057a <=( (not A267) and A166 );
a3058a <=( (not A167) and a3057a );
a3059a <=( a3058a and a3053a );
a3062a <=( A298 and A268 );
a3066a <=( (not A302) and A300 );
a3067a <=( (not A299) and a3066a );
a3068a <=( a3067a and a3062a );
a3071a <=( A168 and A170 );
a3075a <=( (not A267) and A166 );
a3076a <=( (not A167) and a3075a );
a3077a <=( a3076a and a3071a );
a3080a <=( (not A298) and A268 );
a3084a <=( A301 and A300 );
a3085a <=( A299 and a3084a );
a3086a <=( a3085a and a3080a );
a3089a <=( A168 and A170 );
a3093a <=( (not A267) and A166 );
a3094a <=( (not A167) and a3093a );
a3095a <=( a3094a and a3089a );
a3098a <=( (not A298) and A268 );
a3102a <=( (not A302) and A300 );
a3103a <=( A299 and a3102a );
a3104a <=( a3103a and a3098a );
a3107a <=( A168 and A170 );
a3111a <=( (not A267) and A166 );
a3112a <=( (not A167) and a3111a );
a3113a <=( a3112a and a3107a );
a3116a <=( A298 and (not A269) );
a3120a <=( A301 and A300 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( A168 and A170 );
a3129a <=( (not A267) and A166 );
a3130a <=( (not A167) and a3129a );
a3131a <=( a3130a and a3125a );
a3134a <=( A298 and (not A269) );
a3138a <=( (not A302) and A300 );
a3139a <=( (not A299) and a3138a );
a3140a <=( a3139a and a3134a );
a3143a <=( A168 and A170 );
a3147a <=( (not A267) and A166 );
a3148a <=( (not A167) and a3147a );
a3149a <=( a3148a and a3143a );
a3152a <=( (not A298) and (not A269) );
a3156a <=( A301 and A300 );
a3157a <=( A299 and a3156a );
a3158a <=( a3157a and a3152a );
a3161a <=( A168 and A170 );
a3165a <=( (not A267) and A166 );
a3166a <=( (not A167) and a3165a );
a3167a <=( a3166a and a3161a );
a3170a <=( (not A298) and (not A269) );
a3174a <=( (not A302) and A300 );
a3175a <=( A299 and a3174a );
a3176a <=( a3175a and a3170a );
a3179a <=( A168 and A170 );
a3183a <=( A265 and A166 );
a3184a <=( (not A167) and a3183a );
a3185a <=( a3184a and a3179a );
a3188a <=( A298 and A266 );
a3192a <=( A301 and A300 );
a3193a <=( (not A299) and a3192a );
a3194a <=( a3193a and a3188a );
a3197a <=( A168 and A170 );
a3201a <=( A265 and A166 );
a3202a <=( (not A167) and a3201a );
a3203a <=( a3202a and a3197a );
a3206a <=( A298 and A266 );
a3210a <=( (not A302) and A300 );
a3211a <=( (not A299) and a3210a );
a3212a <=( a3211a and a3206a );
a3215a <=( A168 and A170 );
a3219a <=( A265 and A166 );
a3220a <=( (not A167) and a3219a );
a3221a <=( a3220a and a3215a );
a3224a <=( (not A298) and A266 );
a3228a <=( A301 and A300 );
a3229a <=( A299 and a3228a );
a3230a <=( a3229a and a3224a );
a3233a <=( A168 and A170 );
a3237a <=( A265 and A166 );
a3238a <=( (not A167) and a3237a );
a3239a <=( a3238a and a3233a );
a3242a <=( (not A298) and A266 );
a3246a <=( (not A302) and A300 );
a3247a <=( A299 and a3246a );
a3248a <=( a3247a and a3242a );
a3251a <=( A168 and A170 );
a3255a <=( (not A265) and A166 );
a3256a <=( (not A167) and a3255a );
a3257a <=( a3256a and a3251a );
a3260a <=( A267 and A266 );
a3264a <=( A301 and (not A300) );
a3265a <=( A268 and a3264a );
a3266a <=( a3265a and a3260a );
a3269a <=( A168 and A170 );
a3273a <=( (not A265) and A166 );
a3274a <=( (not A167) and a3273a );
a3275a <=( a3274a and a3269a );
a3278a <=( A267 and A266 );
a3282a <=( (not A302) and (not A300) );
a3283a <=( A268 and a3282a );
a3284a <=( a3283a and a3278a );
a3287a <=( A168 and A170 );
a3291a <=( (not A265) and A166 );
a3292a <=( (not A167) and a3291a );
a3293a <=( a3292a and a3287a );
a3296a <=( A267 and A266 );
a3300a <=( A299 and A298 );
a3301a <=( A268 and a3300a );
a3302a <=( a3301a and a3296a );
a3305a <=( A168 and A170 );
a3309a <=( (not A265) and A166 );
a3310a <=( (not A167) and a3309a );
a3311a <=( a3310a and a3305a );
a3314a <=( A267 and A266 );
a3318a <=( (not A299) and (not A298) );
a3319a <=( A268 and a3318a );
a3320a <=( a3319a and a3314a );
a3323a <=( A168 and A170 );
a3327a <=( (not A265) and A166 );
a3328a <=( (not A167) and a3327a );
a3329a <=( a3328a and a3323a );
a3332a <=( A267 and A266 );
a3336a <=( A301 and (not A300) );
a3337a <=( (not A269) and a3336a );
a3338a <=( a3337a and a3332a );
a3341a <=( A168 and A170 );
a3345a <=( (not A265) and A166 );
a3346a <=( (not A167) and a3345a );
a3347a <=( a3346a and a3341a );
a3350a <=( A267 and A266 );
a3354a <=( (not A302) and (not A300) );
a3355a <=( (not A269) and a3354a );
a3356a <=( a3355a and a3350a );
a3359a <=( A168 and A170 );
a3363a <=( (not A265) and A166 );
a3364a <=( (not A167) and a3363a );
a3365a <=( a3364a and a3359a );
a3368a <=( A267 and A266 );
a3372a <=( A299 and A298 );
a3373a <=( (not A269) and a3372a );
a3374a <=( a3373a and a3368a );
a3377a <=( A168 and A170 );
a3381a <=( (not A265) and A166 );
a3382a <=( (not A167) and a3381a );
a3383a <=( a3382a and a3377a );
a3386a <=( A267 and A266 );
a3390a <=( (not A299) and (not A298) );
a3391a <=( (not A269) and a3390a );
a3392a <=( a3391a and a3386a );
a3395a <=( A168 and A170 );
a3399a <=( A265 and A166 );
a3400a <=( (not A167) and a3399a );
a3401a <=( a3400a and a3395a );
a3404a <=( A267 and (not A266) );
a3408a <=( A301 and (not A300) );
a3409a <=( A268 and a3408a );
a3410a <=( a3409a and a3404a );
a3413a <=( A168 and A170 );
a3417a <=( A265 and A166 );
a3418a <=( (not A167) and a3417a );
a3419a <=( a3418a and a3413a );
a3422a <=( A267 and (not A266) );
a3426a <=( (not A302) and (not A300) );
a3427a <=( A268 and a3426a );
a3428a <=( a3427a and a3422a );
a3431a <=( A168 and A170 );
a3435a <=( A265 and A166 );
a3436a <=( (not A167) and a3435a );
a3437a <=( a3436a and a3431a );
a3440a <=( A267 and (not A266) );
a3444a <=( A299 and A298 );
a3445a <=( A268 and a3444a );
a3446a <=( a3445a and a3440a );
a3449a <=( A168 and A170 );
a3453a <=( A265 and A166 );
a3454a <=( (not A167) and a3453a );
a3455a <=( a3454a and a3449a );
a3458a <=( A267 and (not A266) );
a3462a <=( (not A299) and (not A298) );
a3463a <=( A268 and a3462a );
a3464a <=( a3463a and a3458a );
a3467a <=( A168 and A170 );
a3471a <=( A265 and A166 );
a3472a <=( (not A167) and a3471a );
a3473a <=( a3472a and a3467a );
a3476a <=( A267 and (not A266) );
a3480a <=( A301 and (not A300) );
a3481a <=( (not A269) and a3480a );
a3482a <=( a3481a and a3476a );
a3485a <=( A168 and A170 );
a3489a <=( A265 and A166 );
a3490a <=( (not A167) and a3489a );
a3491a <=( a3490a and a3485a );
a3494a <=( A267 and (not A266) );
a3498a <=( (not A302) and (not A300) );
a3499a <=( (not A269) and a3498a );
a3500a <=( a3499a and a3494a );
a3503a <=( A168 and A170 );
a3507a <=( A265 and A166 );
a3508a <=( (not A167) and a3507a );
a3509a <=( a3508a and a3503a );
a3512a <=( A267 and (not A266) );
a3516a <=( A299 and A298 );
a3517a <=( (not A269) and a3516a );
a3518a <=( a3517a and a3512a );
a3521a <=( A168 and A170 );
a3525a <=( A265 and A166 );
a3526a <=( (not A167) and a3525a );
a3527a <=( a3526a and a3521a );
a3530a <=( A267 and (not A266) );
a3534a <=( (not A299) and (not A298) );
a3535a <=( (not A269) and a3534a );
a3536a <=( a3535a and a3530a );
a3539a <=( A168 and A170 );
a3543a <=( (not A265) and A166 );
a3544a <=( (not A167) and a3543a );
a3545a <=( a3544a and a3539a );
a3548a <=( A298 and (not A266) );
a3552a <=( A301 and A300 );
a3553a <=( (not A299) and a3552a );
a3554a <=( a3553a and a3548a );
a3557a <=( A168 and A170 );
a3561a <=( (not A265) and A166 );
a3562a <=( (not A167) and a3561a );
a3563a <=( a3562a and a3557a );
a3566a <=( A298 and (not A266) );
a3570a <=( (not A302) and A300 );
a3571a <=( (not A299) and a3570a );
a3572a <=( a3571a and a3566a );
a3575a <=( A168 and A170 );
a3579a <=( (not A265) and A166 );
a3580a <=( (not A167) and a3579a );
a3581a <=( a3580a and a3575a );
a3584a <=( (not A298) and (not A266) );
a3588a <=( A301 and A300 );
a3589a <=( A299 and a3588a );
a3590a <=( a3589a and a3584a );
a3593a <=( A168 and A170 );
a3597a <=( (not A265) and A166 );
a3598a <=( (not A167) and a3597a );
a3599a <=( a3598a and a3593a );
a3602a <=( (not A298) and (not A266) );
a3606a <=( (not A302) and A300 );
a3607a <=( A299 and a3606a );
a3608a <=( a3607a and a3602a );
a3611a <=( A168 and A169 );
a3615a <=( (not A267) and (not A166) );
a3616a <=( A167 and a3615a );
a3617a <=( a3616a and a3611a );
a3620a <=( A298 and A268 );
a3624a <=( A301 and A300 );
a3625a <=( (not A299) and a3624a );
a3626a <=( a3625a and a3620a );
a3629a <=( A168 and A169 );
a3633a <=( (not A267) and (not A166) );
a3634a <=( A167 and a3633a );
a3635a <=( a3634a and a3629a );
a3638a <=( A298 and A268 );
a3642a <=( (not A302) and A300 );
a3643a <=( (not A299) and a3642a );
a3644a <=( a3643a and a3638a );
a3647a <=( A168 and A169 );
a3651a <=( (not A267) and (not A166) );
a3652a <=( A167 and a3651a );
a3653a <=( a3652a and a3647a );
a3656a <=( (not A298) and A268 );
a3660a <=( A301 and A300 );
a3661a <=( A299 and a3660a );
a3662a <=( a3661a and a3656a );
a3665a <=( A168 and A169 );
a3669a <=( (not A267) and (not A166) );
a3670a <=( A167 and a3669a );
a3671a <=( a3670a and a3665a );
a3674a <=( (not A298) and A268 );
a3678a <=( (not A302) and A300 );
a3679a <=( A299 and a3678a );
a3680a <=( a3679a and a3674a );
a3683a <=( A168 and A169 );
a3687a <=( (not A267) and (not A166) );
a3688a <=( A167 and a3687a );
a3689a <=( a3688a and a3683a );
a3692a <=( A298 and (not A269) );
a3696a <=( A301 and A300 );
a3697a <=( (not A299) and a3696a );
a3698a <=( a3697a and a3692a );
a3701a <=( A168 and A169 );
a3705a <=( (not A267) and (not A166) );
a3706a <=( A167 and a3705a );
a3707a <=( a3706a and a3701a );
a3710a <=( A298 and (not A269) );
a3714a <=( (not A302) and A300 );
a3715a <=( (not A299) and a3714a );
a3716a <=( a3715a and a3710a );
a3719a <=( A168 and A169 );
a3723a <=( (not A267) and (not A166) );
a3724a <=( A167 and a3723a );
a3725a <=( a3724a and a3719a );
a3728a <=( (not A298) and (not A269) );
a3732a <=( A301 and A300 );
a3733a <=( A299 and a3732a );
a3734a <=( a3733a and a3728a );
a3737a <=( A168 and A169 );
a3741a <=( (not A267) and (not A166) );
a3742a <=( A167 and a3741a );
a3743a <=( a3742a and a3737a );
a3746a <=( (not A298) and (not A269) );
a3750a <=( (not A302) and A300 );
a3751a <=( A299 and a3750a );
a3752a <=( a3751a and a3746a );
a3755a <=( A168 and A169 );
a3759a <=( A265 and (not A166) );
a3760a <=( A167 and a3759a );
a3761a <=( a3760a and a3755a );
a3764a <=( A298 and A266 );
a3768a <=( A301 and A300 );
a3769a <=( (not A299) and a3768a );
a3770a <=( a3769a and a3764a );
a3773a <=( A168 and A169 );
a3777a <=( A265 and (not A166) );
a3778a <=( A167 and a3777a );
a3779a <=( a3778a and a3773a );
a3782a <=( A298 and A266 );
a3786a <=( (not A302) and A300 );
a3787a <=( (not A299) and a3786a );
a3788a <=( a3787a and a3782a );
a3791a <=( A168 and A169 );
a3795a <=( A265 and (not A166) );
a3796a <=( A167 and a3795a );
a3797a <=( a3796a and a3791a );
a3800a <=( (not A298) and A266 );
a3804a <=( A301 and A300 );
a3805a <=( A299 and a3804a );
a3806a <=( a3805a and a3800a );
a3809a <=( A168 and A169 );
a3813a <=( A265 and (not A166) );
a3814a <=( A167 and a3813a );
a3815a <=( a3814a and a3809a );
a3818a <=( (not A298) and A266 );
a3822a <=( (not A302) and A300 );
a3823a <=( A299 and a3822a );
a3824a <=( a3823a and a3818a );
a3827a <=( A168 and A169 );
a3831a <=( (not A265) and (not A166) );
a3832a <=( A167 and a3831a );
a3833a <=( a3832a and a3827a );
a3836a <=( A267 and A266 );
a3840a <=( A301 and (not A300) );
a3841a <=( A268 and a3840a );
a3842a <=( a3841a and a3836a );
a3845a <=( A168 and A169 );
a3849a <=( (not A265) and (not A166) );
a3850a <=( A167 and a3849a );
a3851a <=( a3850a and a3845a );
a3854a <=( A267 and A266 );
a3858a <=( (not A302) and (not A300) );
a3859a <=( A268 and a3858a );
a3860a <=( a3859a and a3854a );
a3863a <=( A168 and A169 );
a3867a <=( (not A265) and (not A166) );
a3868a <=( A167 and a3867a );
a3869a <=( a3868a and a3863a );
a3872a <=( A267 and A266 );
a3876a <=( A299 and A298 );
a3877a <=( A268 and a3876a );
a3878a <=( a3877a and a3872a );
a3881a <=( A168 and A169 );
a3885a <=( (not A265) and (not A166) );
a3886a <=( A167 and a3885a );
a3887a <=( a3886a and a3881a );
a3890a <=( A267 and A266 );
a3894a <=( (not A299) and (not A298) );
a3895a <=( A268 and a3894a );
a3896a <=( a3895a and a3890a );
a3899a <=( A168 and A169 );
a3903a <=( (not A265) and (not A166) );
a3904a <=( A167 and a3903a );
a3905a <=( a3904a and a3899a );
a3908a <=( A267 and A266 );
a3912a <=( A301 and (not A300) );
a3913a <=( (not A269) and a3912a );
a3914a <=( a3913a and a3908a );
a3917a <=( A168 and A169 );
a3921a <=( (not A265) and (not A166) );
a3922a <=( A167 and a3921a );
a3923a <=( a3922a and a3917a );
a3926a <=( A267 and A266 );
a3930a <=( (not A302) and (not A300) );
a3931a <=( (not A269) and a3930a );
a3932a <=( a3931a and a3926a );
a3935a <=( A168 and A169 );
a3939a <=( (not A265) and (not A166) );
a3940a <=( A167 and a3939a );
a3941a <=( a3940a and a3935a );
a3944a <=( A267 and A266 );
a3948a <=( A299 and A298 );
a3949a <=( (not A269) and a3948a );
a3950a <=( a3949a and a3944a );
a3953a <=( A168 and A169 );
a3957a <=( (not A265) and (not A166) );
a3958a <=( A167 and a3957a );
a3959a <=( a3958a and a3953a );
a3962a <=( A267 and A266 );
a3966a <=( (not A299) and (not A298) );
a3967a <=( (not A269) and a3966a );
a3968a <=( a3967a and a3962a );
a3971a <=( A168 and A169 );
a3975a <=( A265 and (not A166) );
a3976a <=( A167 and a3975a );
a3977a <=( a3976a and a3971a );
a3980a <=( A267 and (not A266) );
a3984a <=( A301 and (not A300) );
a3985a <=( A268 and a3984a );
a3986a <=( a3985a and a3980a );
a3989a <=( A168 and A169 );
a3993a <=( A265 and (not A166) );
a3994a <=( A167 and a3993a );
a3995a <=( a3994a and a3989a );
a3998a <=( A267 and (not A266) );
a4002a <=( (not A302) and (not A300) );
a4003a <=( A268 and a4002a );
a4004a <=( a4003a and a3998a );
a4007a <=( A168 and A169 );
a4011a <=( A265 and (not A166) );
a4012a <=( A167 and a4011a );
a4013a <=( a4012a and a4007a );
a4016a <=( A267 and (not A266) );
a4020a <=( A299 and A298 );
a4021a <=( A268 and a4020a );
a4022a <=( a4021a and a4016a );
a4025a <=( A168 and A169 );
a4029a <=( A265 and (not A166) );
a4030a <=( A167 and a4029a );
a4031a <=( a4030a and a4025a );
a4034a <=( A267 and (not A266) );
a4038a <=( (not A299) and (not A298) );
a4039a <=( A268 and a4038a );
a4040a <=( a4039a and a4034a );
a4043a <=( A168 and A169 );
a4047a <=( A265 and (not A166) );
a4048a <=( A167 and a4047a );
a4049a <=( a4048a and a4043a );
a4052a <=( A267 and (not A266) );
a4056a <=( A301 and (not A300) );
a4057a <=( (not A269) and a4056a );
a4058a <=( a4057a and a4052a );
a4061a <=( A168 and A169 );
a4065a <=( A265 and (not A166) );
a4066a <=( A167 and a4065a );
a4067a <=( a4066a and a4061a );
a4070a <=( A267 and (not A266) );
a4074a <=( (not A302) and (not A300) );
a4075a <=( (not A269) and a4074a );
a4076a <=( a4075a and a4070a );
a4079a <=( A168 and A169 );
a4083a <=( A265 and (not A166) );
a4084a <=( A167 and a4083a );
a4085a <=( a4084a and a4079a );
a4088a <=( A267 and (not A266) );
a4092a <=( A299 and A298 );
a4093a <=( (not A269) and a4092a );
a4094a <=( a4093a and a4088a );
a4097a <=( A168 and A169 );
a4101a <=( A265 and (not A166) );
a4102a <=( A167 and a4101a );
a4103a <=( a4102a and a4097a );
a4106a <=( A267 and (not A266) );
a4110a <=( (not A299) and (not A298) );
a4111a <=( (not A269) and a4110a );
a4112a <=( a4111a and a4106a );
a4115a <=( A168 and A169 );
a4119a <=( (not A265) and (not A166) );
a4120a <=( A167 and a4119a );
a4121a <=( a4120a and a4115a );
a4124a <=( A298 and (not A266) );
a4128a <=( A301 and A300 );
a4129a <=( (not A299) and a4128a );
a4130a <=( a4129a and a4124a );
a4133a <=( A168 and A169 );
a4137a <=( (not A265) and (not A166) );
a4138a <=( A167 and a4137a );
a4139a <=( a4138a and a4133a );
a4142a <=( A298 and (not A266) );
a4146a <=( (not A302) and A300 );
a4147a <=( (not A299) and a4146a );
a4148a <=( a4147a and a4142a );
a4151a <=( A168 and A169 );
a4155a <=( (not A265) and (not A166) );
a4156a <=( A167 and a4155a );
a4157a <=( a4156a and a4151a );
a4160a <=( (not A298) and (not A266) );
a4164a <=( A301 and A300 );
a4165a <=( A299 and a4164a );
a4166a <=( a4165a and a4160a );
a4169a <=( A168 and A169 );
a4173a <=( (not A265) and (not A166) );
a4174a <=( A167 and a4173a );
a4175a <=( a4174a and a4169a );
a4178a <=( (not A298) and (not A266) );
a4182a <=( (not A302) and A300 );
a4183a <=( A299 and a4182a );
a4184a <=( a4183a and a4178a );
a4187a <=( A168 and A169 );
a4191a <=( (not A267) and A166 );
a4192a <=( (not A167) and a4191a );
a4193a <=( a4192a and a4187a );
a4196a <=( A298 and A268 );
a4200a <=( A301 and A300 );
a4201a <=( (not A299) and a4200a );
a4202a <=( a4201a and a4196a );
a4205a <=( A168 and A169 );
a4209a <=( (not A267) and A166 );
a4210a <=( (not A167) and a4209a );
a4211a <=( a4210a and a4205a );
a4214a <=( A298 and A268 );
a4218a <=( (not A302) and A300 );
a4219a <=( (not A299) and a4218a );
a4220a <=( a4219a and a4214a );
a4223a <=( A168 and A169 );
a4227a <=( (not A267) and A166 );
a4228a <=( (not A167) and a4227a );
a4229a <=( a4228a and a4223a );
a4232a <=( (not A298) and A268 );
a4236a <=( A301 and A300 );
a4237a <=( A299 and a4236a );
a4238a <=( a4237a and a4232a );
a4241a <=( A168 and A169 );
a4245a <=( (not A267) and A166 );
a4246a <=( (not A167) and a4245a );
a4247a <=( a4246a and a4241a );
a4250a <=( (not A298) and A268 );
a4254a <=( (not A302) and A300 );
a4255a <=( A299 and a4254a );
a4256a <=( a4255a and a4250a );
a4259a <=( A168 and A169 );
a4263a <=( (not A267) and A166 );
a4264a <=( (not A167) and a4263a );
a4265a <=( a4264a and a4259a );
a4268a <=( A298 and (not A269) );
a4272a <=( A301 and A300 );
a4273a <=( (not A299) and a4272a );
a4274a <=( a4273a and a4268a );
a4277a <=( A168 and A169 );
a4281a <=( (not A267) and A166 );
a4282a <=( (not A167) and a4281a );
a4283a <=( a4282a and a4277a );
a4286a <=( A298 and (not A269) );
a4290a <=( (not A302) and A300 );
a4291a <=( (not A299) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A168 and A169 );
a4299a <=( (not A267) and A166 );
a4300a <=( (not A167) and a4299a );
a4301a <=( a4300a and a4295a );
a4304a <=( (not A298) and (not A269) );
a4308a <=( A301 and A300 );
a4309a <=( A299 and a4308a );
a4310a <=( a4309a and a4304a );
a4313a <=( A168 and A169 );
a4317a <=( (not A267) and A166 );
a4318a <=( (not A167) and a4317a );
a4319a <=( a4318a and a4313a );
a4322a <=( (not A298) and (not A269) );
a4326a <=( (not A302) and A300 );
a4327a <=( A299 and a4326a );
a4328a <=( a4327a and a4322a );
a4331a <=( A168 and A169 );
a4335a <=( A265 and A166 );
a4336a <=( (not A167) and a4335a );
a4337a <=( a4336a and a4331a );
a4340a <=( A298 and A266 );
a4344a <=( A301 and A300 );
a4345a <=( (not A299) and a4344a );
a4346a <=( a4345a and a4340a );
a4349a <=( A168 and A169 );
a4353a <=( A265 and A166 );
a4354a <=( (not A167) and a4353a );
a4355a <=( a4354a and a4349a );
a4358a <=( A298 and A266 );
a4362a <=( (not A302) and A300 );
a4363a <=( (not A299) and a4362a );
a4364a <=( a4363a and a4358a );
a4367a <=( A168 and A169 );
a4371a <=( A265 and A166 );
a4372a <=( (not A167) and a4371a );
a4373a <=( a4372a and a4367a );
a4376a <=( (not A298) and A266 );
a4380a <=( A301 and A300 );
a4381a <=( A299 and a4380a );
a4382a <=( a4381a and a4376a );
a4385a <=( A168 and A169 );
a4389a <=( A265 and A166 );
a4390a <=( (not A167) and a4389a );
a4391a <=( a4390a and a4385a );
a4394a <=( (not A298) and A266 );
a4398a <=( (not A302) and A300 );
a4399a <=( A299 and a4398a );
a4400a <=( a4399a and a4394a );
a4403a <=( A168 and A169 );
a4407a <=( (not A265) and A166 );
a4408a <=( (not A167) and a4407a );
a4409a <=( a4408a and a4403a );
a4412a <=( A267 and A266 );
a4416a <=( A301 and (not A300) );
a4417a <=( A268 and a4416a );
a4418a <=( a4417a and a4412a );
a4421a <=( A168 and A169 );
a4425a <=( (not A265) and A166 );
a4426a <=( (not A167) and a4425a );
a4427a <=( a4426a and a4421a );
a4430a <=( A267 and A266 );
a4434a <=( (not A302) and (not A300) );
a4435a <=( A268 and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( A168 and A169 );
a4443a <=( (not A265) and A166 );
a4444a <=( (not A167) and a4443a );
a4445a <=( a4444a and a4439a );
a4448a <=( A267 and A266 );
a4452a <=( A299 and A298 );
a4453a <=( A268 and a4452a );
a4454a <=( a4453a and a4448a );
a4457a <=( A168 and A169 );
a4461a <=( (not A265) and A166 );
a4462a <=( (not A167) and a4461a );
a4463a <=( a4462a and a4457a );
a4466a <=( A267 and A266 );
a4470a <=( (not A299) and (not A298) );
a4471a <=( A268 and a4470a );
a4472a <=( a4471a and a4466a );
a4475a <=( A168 and A169 );
a4479a <=( (not A265) and A166 );
a4480a <=( (not A167) and a4479a );
a4481a <=( a4480a and a4475a );
a4484a <=( A267 and A266 );
a4488a <=( A301 and (not A300) );
a4489a <=( (not A269) and a4488a );
a4490a <=( a4489a and a4484a );
a4493a <=( A168 and A169 );
a4497a <=( (not A265) and A166 );
a4498a <=( (not A167) and a4497a );
a4499a <=( a4498a and a4493a );
a4502a <=( A267 and A266 );
a4506a <=( (not A302) and (not A300) );
a4507a <=( (not A269) and a4506a );
a4508a <=( a4507a and a4502a );
a4511a <=( A168 and A169 );
a4515a <=( (not A265) and A166 );
a4516a <=( (not A167) and a4515a );
a4517a <=( a4516a and a4511a );
a4520a <=( A267 and A266 );
a4524a <=( A299 and A298 );
a4525a <=( (not A269) and a4524a );
a4526a <=( a4525a and a4520a );
a4529a <=( A168 and A169 );
a4533a <=( (not A265) and A166 );
a4534a <=( (not A167) and a4533a );
a4535a <=( a4534a and a4529a );
a4538a <=( A267 and A266 );
a4542a <=( (not A299) and (not A298) );
a4543a <=( (not A269) and a4542a );
a4544a <=( a4543a and a4538a );
a4547a <=( A168 and A169 );
a4551a <=( A265 and A166 );
a4552a <=( (not A167) and a4551a );
a4553a <=( a4552a and a4547a );
a4556a <=( A267 and (not A266) );
a4560a <=( A301 and (not A300) );
a4561a <=( A268 and a4560a );
a4562a <=( a4561a and a4556a );
a4565a <=( A168 and A169 );
a4569a <=( A265 and A166 );
a4570a <=( (not A167) and a4569a );
a4571a <=( a4570a and a4565a );
a4574a <=( A267 and (not A266) );
a4578a <=( (not A302) and (not A300) );
a4579a <=( A268 and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( A168 and A169 );
a4587a <=( A265 and A166 );
a4588a <=( (not A167) and a4587a );
a4589a <=( a4588a and a4583a );
a4592a <=( A267 and (not A266) );
a4596a <=( A299 and A298 );
a4597a <=( A268 and a4596a );
a4598a <=( a4597a and a4592a );
a4601a <=( A168 and A169 );
a4605a <=( A265 and A166 );
a4606a <=( (not A167) and a4605a );
a4607a <=( a4606a and a4601a );
a4610a <=( A267 and (not A266) );
a4614a <=( (not A299) and (not A298) );
a4615a <=( A268 and a4614a );
a4616a <=( a4615a and a4610a );
a4619a <=( A168 and A169 );
a4623a <=( A265 and A166 );
a4624a <=( (not A167) and a4623a );
a4625a <=( a4624a and a4619a );
a4628a <=( A267 and (not A266) );
a4632a <=( A301 and (not A300) );
a4633a <=( (not A269) and a4632a );
a4634a <=( a4633a and a4628a );
a4637a <=( A168 and A169 );
a4641a <=( A265 and A166 );
a4642a <=( (not A167) and a4641a );
a4643a <=( a4642a and a4637a );
a4646a <=( A267 and (not A266) );
a4650a <=( (not A302) and (not A300) );
a4651a <=( (not A269) and a4650a );
a4652a <=( a4651a and a4646a );
a4655a <=( A168 and A169 );
a4659a <=( A265 and A166 );
a4660a <=( (not A167) and a4659a );
a4661a <=( a4660a and a4655a );
a4664a <=( A267 and (not A266) );
a4668a <=( A299 and A298 );
a4669a <=( (not A269) and a4668a );
a4670a <=( a4669a and a4664a );
a4673a <=( A168 and A169 );
a4677a <=( A265 and A166 );
a4678a <=( (not A167) and a4677a );
a4679a <=( a4678a and a4673a );
a4682a <=( A267 and (not A266) );
a4686a <=( (not A299) and (not A298) );
a4687a <=( (not A269) and a4686a );
a4688a <=( a4687a and a4682a );
a4691a <=( A168 and A169 );
a4695a <=( (not A265) and A166 );
a4696a <=( (not A167) and a4695a );
a4697a <=( a4696a and a4691a );
a4700a <=( A298 and (not A266) );
a4704a <=( A301 and A300 );
a4705a <=( (not A299) and a4704a );
a4706a <=( a4705a and a4700a );
a4709a <=( A168 and A169 );
a4713a <=( (not A265) and A166 );
a4714a <=( (not A167) and a4713a );
a4715a <=( a4714a and a4709a );
a4718a <=( A298 and (not A266) );
a4722a <=( (not A302) and A300 );
a4723a <=( (not A299) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( A168 and A169 );
a4731a <=( (not A265) and A166 );
a4732a <=( (not A167) and a4731a );
a4733a <=( a4732a and a4727a );
a4736a <=( (not A298) and (not A266) );
a4740a <=( A301 and A300 );
a4741a <=( A299 and a4740a );
a4742a <=( a4741a and a4736a );
a4745a <=( A168 and A169 );
a4749a <=( (not A265) and A166 );
a4750a <=( (not A167) and a4749a );
a4751a <=( a4750a and a4745a );
a4754a <=( (not A298) and (not A266) );
a4758a <=( (not A302) and A300 );
a4759a <=( A299 and a4758a );
a4760a <=( a4759a and a4754a );
a4763a <=( A168 and A170 );
a4767a <=( A267 and (not A166) );
a4768a <=( A167 and a4767a );
a4769a <=( a4768a and a4763a );
a4773a <=( A298 and A269 );
a4774a <=( (not A268) and a4773a );
a4778a <=( A301 and A300 );
a4779a <=( (not A299) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A168 and A170 );
a4787a <=( A267 and (not A166) );
a4788a <=( A167 and a4787a );
a4789a <=( a4788a and a4783a );
a4793a <=( A298 and A269 );
a4794a <=( (not A268) and a4793a );
a4798a <=( (not A302) and A300 );
a4799a <=( (not A299) and a4798a );
a4800a <=( a4799a and a4794a );
a4803a <=( A168 and A170 );
a4807a <=( A267 and (not A166) );
a4808a <=( A167 and a4807a );
a4809a <=( a4808a and a4803a );
a4813a <=( (not A298) and A269 );
a4814a <=( (not A268) and a4813a );
a4818a <=( A301 and A300 );
a4819a <=( A299 and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A168 and A170 );
a4827a <=( A267 and (not A166) );
a4828a <=( A167 and a4827a );
a4829a <=( a4828a and a4823a );
a4833a <=( (not A298) and A269 );
a4834a <=( (not A268) and a4833a );
a4838a <=( (not A302) and A300 );
a4839a <=( A299 and a4838a );
a4840a <=( a4839a and a4834a );
a4843a <=( A168 and A170 );
a4847a <=( (not A267) and (not A166) );
a4848a <=( A167 and a4847a );
a4849a <=( a4848a and a4843a );
a4853a <=( (not A299) and A298 );
a4854a <=( A268 and a4853a );
a4858a <=( A302 and (not A301) );
a4859a <=( (not A300) and a4858a );
a4860a <=( a4859a and a4854a );
a4863a <=( A168 and A170 );
a4867a <=( (not A267) and (not A166) );
a4868a <=( A167 and a4867a );
a4869a <=( a4868a and a4863a );
a4873a <=( A299 and (not A298) );
a4874a <=( A268 and a4873a );
a4878a <=( A302 and (not A301) );
a4879a <=( (not A300) and a4878a );
a4880a <=( a4879a and a4874a );
a4883a <=( A168 and A170 );
a4887a <=( (not A267) and (not A166) );
a4888a <=( A167 and a4887a );
a4889a <=( a4888a and a4883a );
a4893a <=( (not A299) and A298 );
a4894a <=( (not A269) and a4893a );
a4898a <=( A302 and (not A301) );
a4899a <=( (not A300) and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A168 and A170 );
a4907a <=( (not A267) and (not A166) );
a4908a <=( A167 and a4907a );
a4909a <=( a4908a and a4903a );
a4913a <=( A299 and (not A298) );
a4914a <=( (not A269) and a4913a );
a4918a <=( A302 and (not A301) );
a4919a <=( (not A300) and a4918a );
a4920a <=( a4919a and a4914a );
a4923a <=( A168 and A170 );
a4927a <=( A265 and (not A166) );
a4928a <=( A167 and a4927a );
a4929a <=( a4928a and a4923a );
a4933a <=( (not A299) and A298 );
a4934a <=( A266 and a4933a );
a4938a <=( A302 and (not A301) );
a4939a <=( (not A300) and a4938a );
a4940a <=( a4939a and a4934a );
a4943a <=( A168 and A170 );
a4947a <=( A265 and (not A166) );
a4948a <=( A167 and a4947a );
a4949a <=( a4948a and a4943a );
a4953a <=( A299 and (not A298) );
a4954a <=( A266 and a4953a );
a4958a <=( A302 and (not A301) );
a4959a <=( (not A300) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A168 and A170 );
a4967a <=( (not A265) and (not A166) );
a4968a <=( A167 and a4967a );
a4969a <=( a4968a and a4963a );
a4973a <=( A268 and A267 );
a4974a <=( A266 and a4973a );
a4978a <=( A302 and (not A301) );
a4979a <=( A300 and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A168 and A170 );
a4987a <=( (not A265) and (not A166) );
a4988a <=( A167 and a4987a );
a4989a <=( a4988a and a4983a );
a4993a <=( (not A269) and A267 );
a4994a <=( A266 and a4993a );
a4998a <=( A302 and (not A301) );
a4999a <=( A300 and a4998a );
a5000a <=( a4999a and a4994a );
a5003a <=( A168 and A170 );
a5007a <=( (not A265) and (not A166) );
a5008a <=( A167 and a5007a );
a5009a <=( a5008a and a5003a );
a5013a <=( (not A268) and (not A267) );
a5014a <=( A266 and a5013a );
a5018a <=( A301 and (not A300) );
a5019a <=( A269 and a5018a );
a5020a <=( a5019a and a5014a );
a5023a <=( A168 and A170 );
a5027a <=( (not A265) and (not A166) );
a5028a <=( A167 and a5027a );
a5029a <=( a5028a and a5023a );
a5033a <=( (not A268) and (not A267) );
a5034a <=( A266 and a5033a );
a5038a <=( (not A302) and (not A300) );
a5039a <=( A269 and a5038a );
a5040a <=( a5039a and a5034a );
a5043a <=( A168 and A170 );
a5047a <=( (not A265) and (not A166) );
a5048a <=( A167 and a5047a );
a5049a <=( a5048a and a5043a );
a5053a <=( (not A268) and (not A267) );
a5054a <=( A266 and a5053a );
a5058a <=( A299 and A298 );
a5059a <=( A269 and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A168 and A170 );
a5067a <=( (not A265) and (not A166) );
a5068a <=( A167 and a5067a );
a5069a <=( a5068a and a5063a );
a5073a <=( (not A268) and (not A267) );
a5074a <=( A266 and a5073a );
a5078a <=( (not A299) and (not A298) );
a5079a <=( A269 and a5078a );
a5080a <=( a5079a and a5074a );
a5083a <=( A168 and A170 );
a5087a <=( A265 and (not A166) );
a5088a <=( A167 and a5087a );
a5089a <=( a5088a and a5083a );
a5093a <=( A268 and A267 );
a5094a <=( (not A266) and a5093a );
a5098a <=( A302 and (not A301) );
a5099a <=( A300 and a5098a );
a5100a <=( a5099a and a5094a );
a5103a <=( A168 and A170 );
a5107a <=( A265 and (not A166) );
a5108a <=( A167 and a5107a );
a5109a <=( a5108a and a5103a );
a5113a <=( (not A269) and A267 );
a5114a <=( (not A266) and a5113a );
a5118a <=( A302 and (not A301) );
a5119a <=( A300 and a5118a );
a5120a <=( a5119a and a5114a );
a5123a <=( A168 and A170 );
a5127a <=( A265 and (not A166) );
a5128a <=( A167 and a5127a );
a5129a <=( a5128a and a5123a );
a5133a <=( (not A268) and (not A267) );
a5134a <=( (not A266) and a5133a );
a5138a <=( A301 and (not A300) );
a5139a <=( A269 and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( A168 and A170 );
a5147a <=( A265 and (not A166) );
a5148a <=( A167 and a5147a );
a5149a <=( a5148a and a5143a );
a5153a <=( (not A268) and (not A267) );
a5154a <=( (not A266) and a5153a );
a5158a <=( (not A302) and (not A300) );
a5159a <=( A269 and a5158a );
a5160a <=( a5159a and a5154a );
a5163a <=( A168 and A170 );
a5167a <=( A265 and (not A166) );
a5168a <=( A167 and a5167a );
a5169a <=( a5168a and a5163a );
a5173a <=( (not A268) and (not A267) );
a5174a <=( (not A266) and a5173a );
a5178a <=( A299 and A298 );
a5179a <=( A269 and a5178a );
a5180a <=( a5179a and a5174a );
a5183a <=( A168 and A170 );
a5187a <=( A265 and (not A166) );
a5188a <=( A167 and a5187a );
a5189a <=( a5188a and a5183a );
a5193a <=( (not A268) and (not A267) );
a5194a <=( (not A266) and a5193a );
a5198a <=( (not A299) and (not A298) );
a5199a <=( A269 and a5198a );
a5200a <=( a5199a and a5194a );
a5203a <=( A168 and A170 );
a5207a <=( (not A265) and (not A166) );
a5208a <=( A167 and a5207a );
a5209a <=( a5208a and a5203a );
a5213a <=( (not A299) and A298 );
a5214a <=( (not A266) and a5213a );
a5218a <=( A302 and (not A301) );
a5219a <=( (not A300) and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( A168 and A170 );
a5227a <=( (not A265) and (not A166) );
a5228a <=( A167 and a5227a );
a5229a <=( a5228a and a5223a );
a5233a <=( A299 and (not A298) );
a5234a <=( (not A266) and a5233a );
a5238a <=( A302 and (not A301) );
a5239a <=( (not A300) and a5238a );
a5240a <=( a5239a and a5234a );
a5243a <=( A168 and A170 );
a5247a <=( A267 and A166 );
a5248a <=( (not A167) and a5247a );
a5249a <=( a5248a and a5243a );
a5253a <=( A298 and A269 );
a5254a <=( (not A268) and a5253a );
a5258a <=( A301 and A300 );
a5259a <=( (not A299) and a5258a );
a5260a <=( a5259a and a5254a );
a5263a <=( A168 and A170 );
a5267a <=( A267 and A166 );
a5268a <=( (not A167) and a5267a );
a5269a <=( a5268a and a5263a );
a5273a <=( A298 and A269 );
a5274a <=( (not A268) and a5273a );
a5278a <=( (not A302) and A300 );
a5279a <=( (not A299) and a5278a );
a5280a <=( a5279a and a5274a );
a5283a <=( A168 and A170 );
a5287a <=( A267 and A166 );
a5288a <=( (not A167) and a5287a );
a5289a <=( a5288a and a5283a );
a5293a <=( (not A298) and A269 );
a5294a <=( (not A268) and a5293a );
a5298a <=( A301 and A300 );
a5299a <=( A299 and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( A168 and A170 );
a5307a <=( A267 and A166 );
a5308a <=( (not A167) and a5307a );
a5309a <=( a5308a and a5303a );
a5313a <=( (not A298) and A269 );
a5314a <=( (not A268) and a5313a );
a5318a <=( (not A302) and A300 );
a5319a <=( A299 and a5318a );
a5320a <=( a5319a and a5314a );
a5323a <=( A168 and A170 );
a5327a <=( (not A267) and A166 );
a5328a <=( (not A167) and a5327a );
a5329a <=( a5328a and a5323a );
a5333a <=( (not A299) and A298 );
a5334a <=( A268 and a5333a );
a5338a <=( A302 and (not A301) );
a5339a <=( (not A300) and a5338a );
a5340a <=( a5339a and a5334a );
a5343a <=( A168 and A170 );
a5347a <=( (not A267) and A166 );
a5348a <=( (not A167) and a5347a );
a5349a <=( a5348a and a5343a );
a5353a <=( A299 and (not A298) );
a5354a <=( A268 and a5353a );
a5358a <=( A302 and (not A301) );
a5359a <=( (not A300) and a5358a );
a5360a <=( a5359a and a5354a );
a5363a <=( A168 and A170 );
a5367a <=( (not A267) and A166 );
a5368a <=( (not A167) and a5367a );
a5369a <=( a5368a and a5363a );
a5373a <=( (not A299) and A298 );
a5374a <=( (not A269) and a5373a );
a5378a <=( A302 and (not A301) );
a5379a <=( (not A300) and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( A168 and A170 );
a5387a <=( (not A267) and A166 );
a5388a <=( (not A167) and a5387a );
a5389a <=( a5388a and a5383a );
a5393a <=( A299 and (not A298) );
a5394a <=( (not A269) and a5393a );
a5398a <=( A302 and (not A301) );
a5399a <=( (not A300) and a5398a );
a5400a <=( a5399a and a5394a );
a5403a <=( A168 and A170 );
a5407a <=( A265 and A166 );
a5408a <=( (not A167) and a5407a );
a5409a <=( a5408a and a5403a );
a5413a <=( (not A299) and A298 );
a5414a <=( A266 and a5413a );
a5418a <=( A302 and (not A301) );
a5419a <=( (not A300) and a5418a );
a5420a <=( a5419a and a5414a );
a5423a <=( A168 and A170 );
a5427a <=( A265 and A166 );
a5428a <=( (not A167) and a5427a );
a5429a <=( a5428a and a5423a );
a5433a <=( A299 and (not A298) );
a5434a <=( A266 and a5433a );
a5438a <=( A302 and (not A301) );
a5439a <=( (not A300) and a5438a );
a5440a <=( a5439a and a5434a );
a5443a <=( A168 and A170 );
a5447a <=( (not A265) and A166 );
a5448a <=( (not A167) and a5447a );
a5449a <=( a5448a and a5443a );
a5453a <=( A268 and A267 );
a5454a <=( A266 and a5453a );
a5458a <=( A302 and (not A301) );
a5459a <=( A300 and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A168 and A170 );
a5467a <=( (not A265) and A166 );
a5468a <=( (not A167) and a5467a );
a5469a <=( a5468a and a5463a );
a5473a <=( (not A269) and A267 );
a5474a <=( A266 and a5473a );
a5478a <=( A302 and (not A301) );
a5479a <=( A300 and a5478a );
a5480a <=( a5479a and a5474a );
a5483a <=( A168 and A170 );
a5487a <=( (not A265) and A166 );
a5488a <=( (not A167) and a5487a );
a5489a <=( a5488a and a5483a );
a5493a <=( (not A268) and (not A267) );
a5494a <=( A266 and a5493a );
a5498a <=( A301 and (not A300) );
a5499a <=( A269 and a5498a );
a5500a <=( a5499a and a5494a );
a5503a <=( A168 and A170 );
a5507a <=( (not A265) and A166 );
a5508a <=( (not A167) and a5507a );
a5509a <=( a5508a and a5503a );
a5513a <=( (not A268) and (not A267) );
a5514a <=( A266 and a5513a );
a5518a <=( (not A302) and (not A300) );
a5519a <=( A269 and a5518a );
a5520a <=( a5519a and a5514a );
a5523a <=( A168 and A170 );
a5527a <=( (not A265) and A166 );
a5528a <=( (not A167) and a5527a );
a5529a <=( a5528a and a5523a );
a5533a <=( (not A268) and (not A267) );
a5534a <=( A266 and a5533a );
a5538a <=( A299 and A298 );
a5539a <=( A269 and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A168 and A170 );
a5547a <=( (not A265) and A166 );
a5548a <=( (not A167) and a5547a );
a5549a <=( a5548a and a5543a );
a5553a <=( (not A268) and (not A267) );
a5554a <=( A266 and a5553a );
a5558a <=( (not A299) and (not A298) );
a5559a <=( A269 and a5558a );
a5560a <=( a5559a and a5554a );
a5563a <=( A168 and A170 );
a5567a <=( A265 and A166 );
a5568a <=( (not A167) and a5567a );
a5569a <=( a5568a and a5563a );
a5573a <=( A268 and A267 );
a5574a <=( (not A266) and a5573a );
a5578a <=( A302 and (not A301) );
a5579a <=( A300 and a5578a );
a5580a <=( a5579a and a5574a );
a5583a <=( A168 and A170 );
a5587a <=( A265 and A166 );
a5588a <=( (not A167) and a5587a );
a5589a <=( a5588a and a5583a );
a5593a <=( (not A269) and A267 );
a5594a <=( (not A266) and a5593a );
a5598a <=( A302 and (not A301) );
a5599a <=( A300 and a5598a );
a5600a <=( a5599a and a5594a );
a5603a <=( A168 and A170 );
a5607a <=( A265 and A166 );
a5608a <=( (not A167) and a5607a );
a5609a <=( a5608a and a5603a );
a5613a <=( (not A268) and (not A267) );
a5614a <=( (not A266) and a5613a );
a5618a <=( A301 and (not A300) );
a5619a <=( A269 and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A168 and A170 );
a5627a <=( A265 and A166 );
a5628a <=( (not A167) and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( (not A268) and (not A267) );
a5634a <=( (not A266) and a5633a );
a5638a <=( (not A302) and (not A300) );
a5639a <=( A269 and a5638a );
a5640a <=( a5639a and a5634a );
a5643a <=( A168 and A170 );
a5647a <=( A265 and A166 );
a5648a <=( (not A167) and a5647a );
a5649a <=( a5648a and a5643a );
a5653a <=( (not A268) and (not A267) );
a5654a <=( (not A266) and a5653a );
a5658a <=( A299 and A298 );
a5659a <=( A269 and a5658a );
a5660a <=( a5659a and a5654a );
a5663a <=( A168 and A170 );
a5667a <=( A265 and A166 );
a5668a <=( (not A167) and a5667a );
a5669a <=( a5668a and a5663a );
a5673a <=( (not A268) and (not A267) );
a5674a <=( (not A266) and a5673a );
a5678a <=( (not A299) and (not A298) );
a5679a <=( A269 and a5678a );
a5680a <=( a5679a and a5674a );
a5683a <=( A168 and A170 );
a5687a <=( (not A265) and A166 );
a5688a <=( (not A167) and a5687a );
a5689a <=( a5688a and a5683a );
a5693a <=( (not A299) and A298 );
a5694a <=( (not A266) and a5693a );
a5698a <=( A302 and (not A301) );
a5699a <=( (not A300) and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( A168 and A170 );
a5707a <=( (not A265) and A166 );
a5708a <=( (not A167) and a5707a );
a5709a <=( a5708a and a5703a );
a5713a <=( A299 and (not A298) );
a5714a <=( (not A266) and a5713a );
a5718a <=( A302 and (not A301) );
a5719a <=( (not A300) and a5718a );
a5720a <=( a5719a and a5714a );
a5723a <=( A168 and A169 );
a5727a <=( A267 and (not A166) );
a5728a <=( A167 and a5727a );
a5729a <=( a5728a and a5723a );
a5733a <=( A298 and A269 );
a5734a <=( (not A268) and a5733a );
a5738a <=( A301 and A300 );
a5739a <=( (not A299) and a5738a );
a5740a <=( a5739a and a5734a );
a5743a <=( A168 and A169 );
a5747a <=( A267 and (not A166) );
a5748a <=( A167 and a5747a );
a5749a <=( a5748a and a5743a );
a5753a <=( A298 and A269 );
a5754a <=( (not A268) and a5753a );
a5758a <=( (not A302) and A300 );
a5759a <=( (not A299) and a5758a );
a5760a <=( a5759a and a5754a );
a5763a <=( A168 and A169 );
a5767a <=( A267 and (not A166) );
a5768a <=( A167 and a5767a );
a5769a <=( a5768a and a5763a );
a5773a <=( (not A298) and A269 );
a5774a <=( (not A268) and a5773a );
a5778a <=( A301 and A300 );
a5779a <=( A299 and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A168 and A169 );
a5787a <=( A267 and (not A166) );
a5788a <=( A167 and a5787a );
a5789a <=( a5788a and a5783a );
a5793a <=( (not A298) and A269 );
a5794a <=( (not A268) and a5793a );
a5798a <=( (not A302) and A300 );
a5799a <=( A299 and a5798a );
a5800a <=( a5799a and a5794a );
a5803a <=( A168 and A169 );
a5807a <=( (not A267) and (not A166) );
a5808a <=( A167 and a5807a );
a5809a <=( a5808a and a5803a );
a5813a <=( (not A299) and A298 );
a5814a <=( A268 and a5813a );
a5818a <=( A302 and (not A301) );
a5819a <=( (not A300) and a5818a );
a5820a <=( a5819a and a5814a );
a5823a <=( A168 and A169 );
a5827a <=( (not A267) and (not A166) );
a5828a <=( A167 and a5827a );
a5829a <=( a5828a and a5823a );
a5833a <=( A299 and (not A298) );
a5834a <=( A268 and a5833a );
a5838a <=( A302 and (not A301) );
a5839a <=( (not A300) and a5838a );
a5840a <=( a5839a and a5834a );
a5843a <=( A168 and A169 );
a5847a <=( (not A267) and (not A166) );
a5848a <=( A167 and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A299) and A298 );
a5854a <=( (not A269) and a5853a );
a5858a <=( A302 and (not A301) );
a5859a <=( (not A300) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( A168 and A169 );
a5867a <=( (not A267) and (not A166) );
a5868a <=( A167 and a5867a );
a5869a <=( a5868a and a5863a );
a5873a <=( A299 and (not A298) );
a5874a <=( (not A269) and a5873a );
a5878a <=( A302 and (not A301) );
a5879a <=( (not A300) and a5878a );
a5880a <=( a5879a and a5874a );
a5883a <=( A168 and A169 );
a5887a <=( A265 and (not A166) );
a5888a <=( A167 and a5887a );
a5889a <=( a5888a and a5883a );
a5893a <=( (not A299) and A298 );
a5894a <=( A266 and a5893a );
a5898a <=( A302 and (not A301) );
a5899a <=( (not A300) and a5898a );
a5900a <=( a5899a and a5894a );
a5903a <=( A168 and A169 );
a5907a <=( A265 and (not A166) );
a5908a <=( A167 and a5907a );
a5909a <=( a5908a and a5903a );
a5913a <=( A299 and (not A298) );
a5914a <=( A266 and a5913a );
a5918a <=( A302 and (not A301) );
a5919a <=( (not A300) and a5918a );
a5920a <=( a5919a and a5914a );
a5923a <=( A168 and A169 );
a5927a <=( (not A265) and (not A166) );
a5928a <=( A167 and a5927a );
a5929a <=( a5928a and a5923a );
a5933a <=( A268 and A267 );
a5934a <=( A266 and a5933a );
a5938a <=( A302 and (not A301) );
a5939a <=( A300 and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( A168 and A169 );
a5947a <=( (not A265) and (not A166) );
a5948a <=( A167 and a5947a );
a5949a <=( a5948a and a5943a );
a5953a <=( (not A269) and A267 );
a5954a <=( A266 and a5953a );
a5958a <=( A302 and (not A301) );
a5959a <=( A300 and a5958a );
a5960a <=( a5959a and a5954a );
a5963a <=( A168 and A169 );
a5967a <=( (not A265) and (not A166) );
a5968a <=( A167 and a5967a );
a5969a <=( a5968a and a5963a );
a5973a <=( (not A268) and (not A267) );
a5974a <=( A266 and a5973a );
a5978a <=( A301 and (not A300) );
a5979a <=( A269 and a5978a );
a5980a <=( a5979a and a5974a );
a5983a <=( A168 and A169 );
a5987a <=( (not A265) and (not A166) );
a5988a <=( A167 and a5987a );
a5989a <=( a5988a and a5983a );
a5993a <=( (not A268) and (not A267) );
a5994a <=( A266 and a5993a );
a5998a <=( (not A302) and (not A300) );
a5999a <=( A269 and a5998a );
a6000a <=( a5999a and a5994a );
a6003a <=( A168 and A169 );
a6007a <=( (not A265) and (not A166) );
a6008a <=( A167 and a6007a );
a6009a <=( a6008a and a6003a );
a6013a <=( (not A268) and (not A267) );
a6014a <=( A266 and a6013a );
a6018a <=( A299 and A298 );
a6019a <=( A269 and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( A168 and A169 );
a6027a <=( (not A265) and (not A166) );
a6028a <=( A167 and a6027a );
a6029a <=( a6028a and a6023a );
a6033a <=( (not A268) and (not A267) );
a6034a <=( A266 and a6033a );
a6038a <=( (not A299) and (not A298) );
a6039a <=( A269 and a6038a );
a6040a <=( a6039a and a6034a );
a6043a <=( A168 and A169 );
a6047a <=( A265 and (not A166) );
a6048a <=( A167 and a6047a );
a6049a <=( a6048a and a6043a );
a6053a <=( A268 and A267 );
a6054a <=( (not A266) and a6053a );
a6058a <=( A302 and (not A301) );
a6059a <=( A300 and a6058a );
a6060a <=( a6059a and a6054a );
a6063a <=( A168 and A169 );
a6067a <=( A265 and (not A166) );
a6068a <=( A167 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( (not A269) and A267 );
a6074a <=( (not A266) and a6073a );
a6078a <=( A302 and (not A301) );
a6079a <=( A300 and a6078a );
a6080a <=( a6079a and a6074a );
a6083a <=( A168 and A169 );
a6087a <=( A265 and (not A166) );
a6088a <=( A167 and a6087a );
a6089a <=( a6088a and a6083a );
a6093a <=( (not A268) and (not A267) );
a6094a <=( (not A266) and a6093a );
a6098a <=( A301 and (not A300) );
a6099a <=( A269 and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( A168 and A169 );
a6107a <=( A265 and (not A166) );
a6108a <=( A167 and a6107a );
a6109a <=( a6108a and a6103a );
a6113a <=( (not A268) and (not A267) );
a6114a <=( (not A266) and a6113a );
a6118a <=( (not A302) and (not A300) );
a6119a <=( A269 and a6118a );
a6120a <=( a6119a and a6114a );
a6123a <=( A168 and A169 );
a6127a <=( A265 and (not A166) );
a6128a <=( A167 and a6127a );
a6129a <=( a6128a and a6123a );
a6133a <=( (not A268) and (not A267) );
a6134a <=( (not A266) and a6133a );
a6138a <=( A299 and A298 );
a6139a <=( A269 and a6138a );
a6140a <=( a6139a and a6134a );
a6143a <=( A168 and A169 );
a6147a <=( A265 and (not A166) );
a6148a <=( A167 and a6147a );
a6149a <=( a6148a and a6143a );
a6153a <=( (not A268) and (not A267) );
a6154a <=( (not A266) and a6153a );
a6158a <=( (not A299) and (not A298) );
a6159a <=( A269 and a6158a );
a6160a <=( a6159a and a6154a );
a6163a <=( A168 and A169 );
a6167a <=( (not A265) and (not A166) );
a6168a <=( A167 and a6167a );
a6169a <=( a6168a and a6163a );
a6173a <=( (not A299) and A298 );
a6174a <=( (not A266) and a6173a );
a6178a <=( A302 and (not A301) );
a6179a <=( (not A300) and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( A168 and A169 );
a6187a <=( (not A265) and (not A166) );
a6188a <=( A167 and a6187a );
a6189a <=( a6188a and a6183a );
a6193a <=( A299 and (not A298) );
a6194a <=( (not A266) and a6193a );
a6198a <=( A302 and (not A301) );
a6199a <=( (not A300) and a6198a );
a6200a <=( a6199a and a6194a );
a6203a <=( A168 and A169 );
a6207a <=( A267 and A166 );
a6208a <=( (not A167) and a6207a );
a6209a <=( a6208a and a6203a );
a6213a <=( A298 and A269 );
a6214a <=( (not A268) and a6213a );
a6218a <=( A301 and A300 );
a6219a <=( (not A299) and a6218a );
a6220a <=( a6219a and a6214a );
a6223a <=( A168 and A169 );
a6227a <=( A267 and A166 );
a6228a <=( (not A167) and a6227a );
a6229a <=( a6228a and a6223a );
a6233a <=( A298 and A269 );
a6234a <=( (not A268) and a6233a );
a6238a <=( (not A302) and A300 );
a6239a <=( (not A299) and a6238a );
a6240a <=( a6239a and a6234a );
a6243a <=( A168 and A169 );
a6247a <=( A267 and A166 );
a6248a <=( (not A167) and a6247a );
a6249a <=( a6248a and a6243a );
a6253a <=( (not A298) and A269 );
a6254a <=( (not A268) and a6253a );
a6258a <=( A301 and A300 );
a6259a <=( A299 and a6258a );
a6260a <=( a6259a and a6254a );
a6263a <=( A168 and A169 );
a6267a <=( A267 and A166 );
a6268a <=( (not A167) and a6267a );
a6269a <=( a6268a and a6263a );
a6273a <=( (not A298) and A269 );
a6274a <=( (not A268) and a6273a );
a6278a <=( (not A302) and A300 );
a6279a <=( A299 and a6278a );
a6280a <=( a6279a and a6274a );
a6283a <=( A168 and A169 );
a6287a <=( (not A267) and A166 );
a6288a <=( (not A167) and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A299) and A298 );
a6294a <=( A268 and a6293a );
a6298a <=( A302 and (not A301) );
a6299a <=( (not A300) and a6298a );
a6300a <=( a6299a and a6294a );
a6303a <=( A168 and A169 );
a6307a <=( (not A267) and A166 );
a6308a <=( (not A167) and a6307a );
a6309a <=( a6308a and a6303a );
a6313a <=( A299 and (not A298) );
a6314a <=( A268 and a6313a );
a6318a <=( A302 and (not A301) );
a6319a <=( (not A300) and a6318a );
a6320a <=( a6319a and a6314a );
a6323a <=( A168 and A169 );
a6327a <=( (not A267) and A166 );
a6328a <=( (not A167) and a6327a );
a6329a <=( a6328a and a6323a );
a6333a <=( (not A299) and A298 );
a6334a <=( (not A269) and a6333a );
a6338a <=( A302 and (not A301) );
a6339a <=( (not A300) and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A168 and A169 );
a6347a <=( (not A267) and A166 );
a6348a <=( (not A167) and a6347a );
a6349a <=( a6348a and a6343a );
a6353a <=( A299 and (not A298) );
a6354a <=( (not A269) and a6353a );
a6358a <=( A302 and (not A301) );
a6359a <=( (not A300) and a6358a );
a6360a <=( a6359a and a6354a );
a6363a <=( A168 and A169 );
a6367a <=( A265 and A166 );
a6368a <=( (not A167) and a6367a );
a6369a <=( a6368a and a6363a );
a6373a <=( (not A299) and A298 );
a6374a <=( A266 and a6373a );
a6378a <=( A302 and (not A301) );
a6379a <=( (not A300) and a6378a );
a6380a <=( a6379a and a6374a );
a6383a <=( A168 and A169 );
a6387a <=( A265 and A166 );
a6388a <=( (not A167) and a6387a );
a6389a <=( a6388a and a6383a );
a6393a <=( A299 and (not A298) );
a6394a <=( A266 and a6393a );
a6398a <=( A302 and (not A301) );
a6399a <=( (not A300) and a6398a );
a6400a <=( a6399a and a6394a );
a6403a <=( A168 and A169 );
a6407a <=( (not A265) and A166 );
a6408a <=( (not A167) and a6407a );
a6409a <=( a6408a and a6403a );
a6413a <=( A268 and A267 );
a6414a <=( A266 and a6413a );
a6418a <=( A302 and (not A301) );
a6419a <=( A300 and a6418a );
a6420a <=( a6419a and a6414a );
a6423a <=( A168 and A169 );
a6427a <=( (not A265) and A166 );
a6428a <=( (not A167) and a6427a );
a6429a <=( a6428a and a6423a );
a6433a <=( (not A269) and A267 );
a6434a <=( A266 and a6433a );
a6438a <=( A302 and (not A301) );
a6439a <=( A300 and a6438a );
a6440a <=( a6439a and a6434a );
a6443a <=( A168 and A169 );
a6447a <=( (not A265) and A166 );
a6448a <=( (not A167) and a6447a );
a6449a <=( a6448a and a6443a );
a6453a <=( (not A268) and (not A267) );
a6454a <=( A266 and a6453a );
a6458a <=( A301 and (not A300) );
a6459a <=( A269 and a6458a );
a6460a <=( a6459a and a6454a );
a6463a <=( A168 and A169 );
a6467a <=( (not A265) and A166 );
a6468a <=( (not A167) and a6467a );
a6469a <=( a6468a and a6463a );
a6473a <=( (not A268) and (not A267) );
a6474a <=( A266 and a6473a );
a6478a <=( (not A302) and (not A300) );
a6479a <=( A269 and a6478a );
a6480a <=( a6479a and a6474a );
a6483a <=( A168 and A169 );
a6487a <=( (not A265) and A166 );
a6488a <=( (not A167) and a6487a );
a6489a <=( a6488a and a6483a );
a6493a <=( (not A268) and (not A267) );
a6494a <=( A266 and a6493a );
a6498a <=( A299 and A298 );
a6499a <=( A269 and a6498a );
a6500a <=( a6499a and a6494a );
a6503a <=( A168 and A169 );
a6507a <=( (not A265) and A166 );
a6508a <=( (not A167) and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( (not A268) and (not A267) );
a6514a <=( A266 and a6513a );
a6518a <=( (not A299) and (not A298) );
a6519a <=( A269 and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A168 and A169 );
a6527a <=( A265 and A166 );
a6528a <=( (not A167) and a6527a );
a6529a <=( a6528a and a6523a );
a6533a <=( A268 and A267 );
a6534a <=( (not A266) and a6533a );
a6538a <=( A302 and (not A301) );
a6539a <=( A300 and a6538a );
a6540a <=( a6539a and a6534a );
a6543a <=( A168 and A169 );
a6547a <=( A265 and A166 );
a6548a <=( (not A167) and a6547a );
a6549a <=( a6548a and a6543a );
a6553a <=( (not A269) and A267 );
a6554a <=( (not A266) and a6553a );
a6558a <=( A302 and (not A301) );
a6559a <=( A300 and a6558a );
a6560a <=( a6559a and a6554a );
a6563a <=( A168 and A169 );
a6567a <=( A265 and A166 );
a6568a <=( (not A167) and a6567a );
a6569a <=( a6568a and a6563a );
a6573a <=( (not A268) and (not A267) );
a6574a <=( (not A266) and a6573a );
a6578a <=( A301 and (not A300) );
a6579a <=( A269 and a6578a );
a6580a <=( a6579a and a6574a );
a6583a <=( A168 and A169 );
a6587a <=( A265 and A166 );
a6588a <=( (not A167) and a6587a );
a6589a <=( a6588a and a6583a );
a6593a <=( (not A268) and (not A267) );
a6594a <=( (not A266) and a6593a );
a6598a <=( (not A302) and (not A300) );
a6599a <=( A269 and a6598a );
a6600a <=( a6599a and a6594a );
a6603a <=( A168 and A169 );
a6607a <=( A265 and A166 );
a6608a <=( (not A167) and a6607a );
a6609a <=( a6608a and a6603a );
a6613a <=( (not A268) and (not A267) );
a6614a <=( (not A266) and a6613a );
a6618a <=( A299 and A298 );
a6619a <=( A269 and a6618a );
a6620a <=( a6619a and a6614a );
a6623a <=( A168 and A169 );
a6627a <=( A265 and A166 );
a6628a <=( (not A167) and a6627a );
a6629a <=( a6628a and a6623a );
a6633a <=( (not A268) and (not A267) );
a6634a <=( (not A266) and a6633a );
a6638a <=( (not A299) and (not A298) );
a6639a <=( A269 and a6638a );
a6640a <=( a6639a and a6634a );
a6643a <=( A168 and A169 );
a6647a <=( (not A265) and A166 );
a6648a <=( (not A167) and a6647a );
a6649a <=( a6648a and a6643a );
a6653a <=( (not A299) and A298 );
a6654a <=( (not A266) and a6653a );
a6658a <=( A302 and (not A301) );
a6659a <=( (not A300) and a6658a );
a6660a <=( a6659a and a6654a );
a6663a <=( A168 and A169 );
a6667a <=( (not A265) and A166 );
a6668a <=( (not A167) and a6667a );
a6669a <=( a6668a and a6663a );
a6673a <=( A299 and (not A298) );
a6674a <=( (not A266) and a6673a );
a6678a <=( A302 and (not A301) );
a6679a <=( (not A300) and a6678a );
a6680a <=( a6679a and a6674a );
a6683a <=( (not A169) and (not A170) );
a6687a <=( (not A166) and A167 );
a6688a <=( (not A168) and a6687a );
a6689a <=( a6688a and a6683a );
a6693a <=( A298 and A268 );
a6694a <=( (not A267) and a6693a );
a6698a <=( A301 and A300 );
a6699a <=( (not A299) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( (not A169) and (not A170) );
a6707a <=( (not A166) and A167 );
a6708a <=( (not A168) and a6707a );
a6709a <=( a6708a and a6703a );
a6713a <=( A298 and A268 );
a6714a <=( (not A267) and a6713a );
a6718a <=( (not A302) and A300 );
a6719a <=( (not A299) and a6718a );
a6720a <=( a6719a and a6714a );
a6723a <=( (not A169) and (not A170) );
a6727a <=( (not A166) and A167 );
a6728a <=( (not A168) and a6727a );
a6729a <=( a6728a and a6723a );
a6733a <=( (not A298) and A268 );
a6734a <=( (not A267) and a6733a );
a6738a <=( A301 and A300 );
a6739a <=( A299 and a6738a );
a6740a <=( a6739a and a6734a );
a6743a <=( (not A169) and (not A170) );
a6747a <=( (not A166) and A167 );
a6748a <=( (not A168) and a6747a );
a6749a <=( a6748a and a6743a );
a6753a <=( (not A298) and A268 );
a6754a <=( (not A267) and a6753a );
a6758a <=( (not A302) and A300 );
a6759a <=( A299 and a6758a );
a6760a <=( a6759a and a6754a );
a6763a <=( (not A169) and (not A170) );
a6767a <=( (not A166) and A167 );
a6768a <=( (not A168) and a6767a );
a6769a <=( a6768a and a6763a );
a6773a <=( A298 and (not A269) );
a6774a <=( (not A267) and a6773a );
a6778a <=( A301 and A300 );
a6779a <=( (not A299) and a6778a );
a6780a <=( a6779a and a6774a );
a6783a <=( (not A169) and (not A170) );
a6787a <=( (not A166) and A167 );
a6788a <=( (not A168) and a6787a );
a6789a <=( a6788a and a6783a );
a6793a <=( A298 and (not A269) );
a6794a <=( (not A267) and a6793a );
a6798a <=( (not A302) and A300 );
a6799a <=( (not A299) and a6798a );
a6800a <=( a6799a and a6794a );
a6803a <=( (not A169) and (not A170) );
a6807a <=( (not A166) and A167 );
a6808a <=( (not A168) and a6807a );
a6809a <=( a6808a and a6803a );
a6813a <=( (not A298) and (not A269) );
a6814a <=( (not A267) and a6813a );
a6818a <=( A301 and A300 );
a6819a <=( A299 and a6818a );
a6820a <=( a6819a and a6814a );
a6823a <=( (not A169) and (not A170) );
a6827a <=( (not A166) and A167 );
a6828a <=( (not A168) and a6827a );
a6829a <=( a6828a and a6823a );
a6833a <=( (not A298) and (not A269) );
a6834a <=( (not A267) and a6833a );
a6838a <=( (not A302) and A300 );
a6839a <=( A299 and a6838a );
a6840a <=( a6839a and a6834a );
a6843a <=( (not A169) and (not A170) );
a6847a <=( (not A166) and A167 );
a6848a <=( (not A168) and a6847a );
a6849a <=( a6848a and a6843a );
a6853a <=( A298 and A266 );
a6854a <=( A265 and a6853a );
a6858a <=( A301 and A300 );
a6859a <=( (not A299) and a6858a );
a6860a <=( a6859a and a6854a );
a6863a <=( (not A169) and (not A170) );
a6867a <=( (not A166) and A167 );
a6868a <=( (not A168) and a6867a );
a6869a <=( a6868a and a6863a );
a6873a <=( A298 and A266 );
a6874a <=( A265 and a6873a );
a6878a <=( (not A302) and A300 );
a6879a <=( (not A299) and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( (not A169) and (not A170) );
a6887a <=( (not A166) and A167 );
a6888a <=( (not A168) and a6887a );
a6889a <=( a6888a and a6883a );
a6893a <=( (not A298) and A266 );
a6894a <=( A265 and a6893a );
a6898a <=( A301 and A300 );
a6899a <=( A299 and a6898a );
a6900a <=( a6899a and a6894a );
a6903a <=( (not A169) and (not A170) );
a6907a <=( (not A166) and A167 );
a6908a <=( (not A168) and a6907a );
a6909a <=( a6908a and a6903a );
a6913a <=( (not A298) and A266 );
a6914a <=( A265 and a6913a );
a6918a <=( (not A302) and A300 );
a6919a <=( A299 and a6918a );
a6920a <=( a6919a and a6914a );
a6923a <=( (not A169) and (not A170) );
a6927a <=( (not A166) and A167 );
a6928a <=( (not A168) and a6927a );
a6929a <=( a6928a and a6923a );
a6933a <=( A267 and A266 );
a6934a <=( (not A265) and a6933a );
a6938a <=( A301 and (not A300) );
a6939a <=( A268 and a6938a );
a6940a <=( a6939a and a6934a );
a6943a <=( (not A169) and (not A170) );
a6947a <=( (not A166) and A167 );
a6948a <=( (not A168) and a6947a );
a6949a <=( a6948a and a6943a );
a6953a <=( A267 and A266 );
a6954a <=( (not A265) and a6953a );
a6958a <=( (not A302) and (not A300) );
a6959a <=( A268 and a6958a );
a6960a <=( a6959a and a6954a );
a6963a <=( (not A169) and (not A170) );
a6967a <=( (not A166) and A167 );
a6968a <=( (not A168) and a6967a );
a6969a <=( a6968a and a6963a );
a6973a <=( A267 and A266 );
a6974a <=( (not A265) and a6973a );
a6978a <=( A299 and A298 );
a6979a <=( A268 and a6978a );
a6980a <=( a6979a and a6974a );
a6983a <=( (not A169) and (not A170) );
a6987a <=( (not A166) and A167 );
a6988a <=( (not A168) and a6987a );
a6989a <=( a6988a and a6983a );
a6993a <=( A267 and A266 );
a6994a <=( (not A265) and a6993a );
a6998a <=( (not A299) and (not A298) );
a6999a <=( A268 and a6998a );
a7000a <=( a6999a and a6994a );
a7003a <=( (not A169) and (not A170) );
a7007a <=( (not A166) and A167 );
a7008a <=( (not A168) and a7007a );
a7009a <=( a7008a and a7003a );
a7013a <=( A267 and A266 );
a7014a <=( (not A265) and a7013a );
a7018a <=( A301 and (not A300) );
a7019a <=( (not A269) and a7018a );
a7020a <=( a7019a and a7014a );
a7023a <=( (not A169) and (not A170) );
a7027a <=( (not A166) and A167 );
a7028a <=( (not A168) and a7027a );
a7029a <=( a7028a and a7023a );
a7033a <=( A267 and A266 );
a7034a <=( (not A265) and a7033a );
a7038a <=( (not A302) and (not A300) );
a7039a <=( (not A269) and a7038a );
a7040a <=( a7039a and a7034a );
a7043a <=( (not A169) and (not A170) );
a7047a <=( (not A166) and A167 );
a7048a <=( (not A168) and a7047a );
a7049a <=( a7048a and a7043a );
a7053a <=( A267 and A266 );
a7054a <=( (not A265) and a7053a );
a7058a <=( A299 and A298 );
a7059a <=( (not A269) and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( (not A169) and (not A170) );
a7067a <=( (not A166) and A167 );
a7068a <=( (not A168) and a7067a );
a7069a <=( a7068a and a7063a );
a7073a <=( A267 and A266 );
a7074a <=( (not A265) and a7073a );
a7078a <=( (not A299) and (not A298) );
a7079a <=( (not A269) and a7078a );
a7080a <=( a7079a and a7074a );
a7083a <=( (not A169) and (not A170) );
a7087a <=( (not A166) and A167 );
a7088a <=( (not A168) and a7087a );
a7089a <=( a7088a and a7083a );
a7093a <=( A267 and (not A266) );
a7094a <=( A265 and a7093a );
a7098a <=( A301 and (not A300) );
a7099a <=( A268 and a7098a );
a7100a <=( a7099a and a7094a );
a7103a <=( (not A169) and (not A170) );
a7107a <=( (not A166) and A167 );
a7108a <=( (not A168) and a7107a );
a7109a <=( a7108a and a7103a );
a7113a <=( A267 and (not A266) );
a7114a <=( A265 and a7113a );
a7118a <=( (not A302) and (not A300) );
a7119a <=( A268 and a7118a );
a7120a <=( a7119a and a7114a );
a7123a <=( (not A169) and (not A170) );
a7127a <=( (not A166) and A167 );
a7128a <=( (not A168) and a7127a );
a7129a <=( a7128a and a7123a );
a7133a <=( A267 and (not A266) );
a7134a <=( A265 and a7133a );
a7138a <=( A299 and A298 );
a7139a <=( A268 and a7138a );
a7140a <=( a7139a and a7134a );
a7143a <=( (not A169) and (not A170) );
a7147a <=( (not A166) and A167 );
a7148a <=( (not A168) and a7147a );
a7149a <=( a7148a and a7143a );
a7153a <=( A267 and (not A266) );
a7154a <=( A265 and a7153a );
a7158a <=( (not A299) and (not A298) );
a7159a <=( A268 and a7158a );
a7160a <=( a7159a and a7154a );
a7163a <=( (not A169) and (not A170) );
a7167a <=( (not A166) and A167 );
a7168a <=( (not A168) and a7167a );
a7169a <=( a7168a and a7163a );
a7173a <=( A267 and (not A266) );
a7174a <=( A265 and a7173a );
a7178a <=( A301 and (not A300) );
a7179a <=( (not A269) and a7178a );
a7180a <=( a7179a and a7174a );
a7183a <=( (not A169) and (not A170) );
a7187a <=( (not A166) and A167 );
a7188a <=( (not A168) and a7187a );
a7189a <=( a7188a and a7183a );
a7193a <=( A267 and (not A266) );
a7194a <=( A265 and a7193a );
a7198a <=( (not A302) and (not A300) );
a7199a <=( (not A269) and a7198a );
a7200a <=( a7199a and a7194a );
a7203a <=( (not A169) and (not A170) );
a7207a <=( (not A166) and A167 );
a7208a <=( (not A168) and a7207a );
a7209a <=( a7208a and a7203a );
a7213a <=( A267 and (not A266) );
a7214a <=( A265 and a7213a );
a7218a <=( A299 and A298 );
a7219a <=( (not A269) and a7218a );
a7220a <=( a7219a and a7214a );
a7223a <=( (not A169) and (not A170) );
a7227a <=( (not A166) and A167 );
a7228a <=( (not A168) and a7227a );
a7229a <=( a7228a and a7223a );
a7233a <=( A267 and (not A266) );
a7234a <=( A265 and a7233a );
a7238a <=( (not A299) and (not A298) );
a7239a <=( (not A269) and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( (not A169) and (not A170) );
a7247a <=( (not A166) and A167 );
a7248a <=( (not A168) and a7247a );
a7249a <=( a7248a and a7243a );
a7253a <=( A298 and (not A266) );
a7254a <=( (not A265) and a7253a );
a7258a <=( A301 and A300 );
a7259a <=( (not A299) and a7258a );
a7260a <=( a7259a and a7254a );
a7263a <=( (not A169) and (not A170) );
a7267a <=( (not A166) and A167 );
a7268a <=( (not A168) and a7267a );
a7269a <=( a7268a and a7263a );
a7273a <=( A298 and (not A266) );
a7274a <=( (not A265) and a7273a );
a7278a <=( (not A302) and A300 );
a7279a <=( (not A299) and a7278a );
a7280a <=( a7279a and a7274a );
a7283a <=( (not A169) and (not A170) );
a7287a <=( (not A166) and A167 );
a7288a <=( (not A168) and a7287a );
a7289a <=( a7288a and a7283a );
a7293a <=( (not A298) and (not A266) );
a7294a <=( (not A265) and a7293a );
a7298a <=( A301 and A300 );
a7299a <=( A299 and a7298a );
a7300a <=( a7299a and a7294a );
a7303a <=( (not A169) and (not A170) );
a7307a <=( (not A166) and A167 );
a7308a <=( (not A168) and a7307a );
a7309a <=( a7308a and a7303a );
a7313a <=( (not A298) and (not A266) );
a7314a <=( (not A265) and a7313a );
a7318a <=( (not A302) and A300 );
a7319a <=( A299 and a7318a );
a7320a <=( a7319a and a7314a );
a7323a <=( (not A169) and (not A170) );
a7327a <=( A166 and (not A167) );
a7328a <=( (not A168) and a7327a );
a7329a <=( a7328a and a7323a );
a7333a <=( A298 and A268 );
a7334a <=( (not A267) and a7333a );
a7338a <=( A301 and A300 );
a7339a <=( (not A299) and a7338a );
a7340a <=( a7339a and a7334a );
a7343a <=( (not A169) and (not A170) );
a7347a <=( A166 and (not A167) );
a7348a <=( (not A168) and a7347a );
a7349a <=( a7348a and a7343a );
a7353a <=( A298 and A268 );
a7354a <=( (not A267) and a7353a );
a7358a <=( (not A302) and A300 );
a7359a <=( (not A299) and a7358a );
a7360a <=( a7359a and a7354a );
a7363a <=( (not A169) and (not A170) );
a7367a <=( A166 and (not A167) );
a7368a <=( (not A168) and a7367a );
a7369a <=( a7368a and a7363a );
a7373a <=( (not A298) and A268 );
a7374a <=( (not A267) and a7373a );
a7378a <=( A301 and A300 );
a7379a <=( A299 and a7378a );
a7380a <=( a7379a and a7374a );
a7383a <=( (not A169) and (not A170) );
a7387a <=( A166 and (not A167) );
a7388a <=( (not A168) and a7387a );
a7389a <=( a7388a and a7383a );
a7393a <=( (not A298) and A268 );
a7394a <=( (not A267) and a7393a );
a7398a <=( (not A302) and A300 );
a7399a <=( A299 and a7398a );
a7400a <=( a7399a and a7394a );
a7403a <=( (not A169) and (not A170) );
a7407a <=( A166 and (not A167) );
a7408a <=( (not A168) and a7407a );
a7409a <=( a7408a and a7403a );
a7413a <=( A298 and (not A269) );
a7414a <=( (not A267) and a7413a );
a7418a <=( A301 and A300 );
a7419a <=( (not A299) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( (not A169) and (not A170) );
a7427a <=( A166 and (not A167) );
a7428a <=( (not A168) and a7427a );
a7429a <=( a7428a and a7423a );
a7433a <=( A298 and (not A269) );
a7434a <=( (not A267) and a7433a );
a7438a <=( (not A302) and A300 );
a7439a <=( (not A299) and a7438a );
a7440a <=( a7439a and a7434a );
a7443a <=( (not A169) and (not A170) );
a7447a <=( A166 and (not A167) );
a7448a <=( (not A168) and a7447a );
a7449a <=( a7448a and a7443a );
a7453a <=( (not A298) and (not A269) );
a7454a <=( (not A267) and a7453a );
a7458a <=( A301 and A300 );
a7459a <=( A299 and a7458a );
a7460a <=( a7459a and a7454a );
a7463a <=( (not A169) and (not A170) );
a7467a <=( A166 and (not A167) );
a7468a <=( (not A168) and a7467a );
a7469a <=( a7468a and a7463a );
a7473a <=( (not A298) and (not A269) );
a7474a <=( (not A267) and a7473a );
a7478a <=( (not A302) and A300 );
a7479a <=( A299 and a7478a );
a7480a <=( a7479a and a7474a );
a7483a <=( (not A169) and (not A170) );
a7487a <=( A166 and (not A167) );
a7488a <=( (not A168) and a7487a );
a7489a <=( a7488a and a7483a );
a7493a <=( A298 and A266 );
a7494a <=( A265 and a7493a );
a7498a <=( A301 and A300 );
a7499a <=( (not A299) and a7498a );
a7500a <=( a7499a and a7494a );
a7503a <=( (not A169) and (not A170) );
a7507a <=( A166 and (not A167) );
a7508a <=( (not A168) and a7507a );
a7509a <=( a7508a and a7503a );
a7513a <=( A298 and A266 );
a7514a <=( A265 and a7513a );
a7518a <=( (not A302) and A300 );
a7519a <=( (not A299) and a7518a );
a7520a <=( a7519a and a7514a );
a7523a <=( (not A169) and (not A170) );
a7527a <=( A166 and (not A167) );
a7528a <=( (not A168) and a7527a );
a7529a <=( a7528a and a7523a );
a7533a <=( (not A298) and A266 );
a7534a <=( A265 and a7533a );
a7538a <=( A301 and A300 );
a7539a <=( A299 and a7538a );
a7540a <=( a7539a and a7534a );
a7543a <=( (not A169) and (not A170) );
a7547a <=( A166 and (not A167) );
a7548a <=( (not A168) and a7547a );
a7549a <=( a7548a and a7543a );
a7553a <=( (not A298) and A266 );
a7554a <=( A265 and a7553a );
a7558a <=( (not A302) and A300 );
a7559a <=( A299 and a7558a );
a7560a <=( a7559a and a7554a );
a7563a <=( (not A169) and (not A170) );
a7567a <=( A166 and (not A167) );
a7568a <=( (not A168) and a7567a );
a7569a <=( a7568a and a7563a );
a7573a <=( A267 and A266 );
a7574a <=( (not A265) and a7573a );
a7578a <=( A301 and (not A300) );
a7579a <=( A268 and a7578a );
a7580a <=( a7579a and a7574a );
a7583a <=( (not A169) and (not A170) );
a7587a <=( A166 and (not A167) );
a7588a <=( (not A168) and a7587a );
a7589a <=( a7588a and a7583a );
a7593a <=( A267 and A266 );
a7594a <=( (not A265) and a7593a );
a7598a <=( (not A302) and (not A300) );
a7599a <=( A268 and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( (not A169) and (not A170) );
a7607a <=( A166 and (not A167) );
a7608a <=( (not A168) and a7607a );
a7609a <=( a7608a and a7603a );
a7613a <=( A267 and A266 );
a7614a <=( (not A265) and a7613a );
a7618a <=( A299 and A298 );
a7619a <=( A268 and a7618a );
a7620a <=( a7619a and a7614a );
a7623a <=( (not A169) and (not A170) );
a7627a <=( A166 and (not A167) );
a7628a <=( (not A168) and a7627a );
a7629a <=( a7628a and a7623a );
a7633a <=( A267 and A266 );
a7634a <=( (not A265) and a7633a );
a7638a <=( (not A299) and (not A298) );
a7639a <=( A268 and a7638a );
a7640a <=( a7639a and a7634a );
a7643a <=( (not A169) and (not A170) );
a7647a <=( A166 and (not A167) );
a7648a <=( (not A168) and a7647a );
a7649a <=( a7648a and a7643a );
a7653a <=( A267 and A266 );
a7654a <=( (not A265) and a7653a );
a7658a <=( A301 and (not A300) );
a7659a <=( (not A269) and a7658a );
a7660a <=( a7659a and a7654a );
a7663a <=( (not A169) and (not A170) );
a7667a <=( A166 and (not A167) );
a7668a <=( (not A168) and a7667a );
a7669a <=( a7668a and a7663a );
a7673a <=( A267 and A266 );
a7674a <=( (not A265) and a7673a );
a7678a <=( (not A302) and (not A300) );
a7679a <=( (not A269) and a7678a );
a7680a <=( a7679a and a7674a );
a7683a <=( (not A169) and (not A170) );
a7687a <=( A166 and (not A167) );
a7688a <=( (not A168) and a7687a );
a7689a <=( a7688a and a7683a );
a7693a <=( A267 and A266 );
a7694a <=( (not A265) and a7693a );
a7698a <=( A299 and A298 );
a7699a <=( (not A269) and a7698a );
a7700a <=( a7699a and a7694a );
a7703a <=( (not A169) and (not A170) );
a7707a <=( A166 and (not A167) );
a7708a <=( (not A168) and a7707a );
a7709a <=( a7708a and a7703a );
a7713a <=( A267 and A266 );
a7714a <=( (not A265) and a7713a );
a7718a <=( (not A299) and (not A298) );
a7719a <=( (not A269) and a7718a );
a7720a <=( a7719a and a7714a );
a7723a <=( (not A169) and (not A170) );
a7727a <=( A166 and (not A167) );
a7728a <=( (not A168) and a7727a );
a7729a <=( a7728a and a7723a );
a7733a <=( A267 and (not A266) );
a7734a <=( A265 and a7733a );
a7738a <=( A301 and (not A300) );
a7739a <=( A268 and a7738a );
a7740a <=( a7739a and a7734a );
a7743a <=( (not A169) and (not A170) );
a7747a <=( A166 and (not A167) );
a7748a <=( (not A168) and a7747a );
a7749a <=( a7748a and a7743a );
a7753a <=( A267 and (not A266) );
a7754a <=( A265 and a7753a );
a7758a <=( (not A302) and (not A300) );
a7759a <=( A268 and a7758a );
a7760a <=( a7759a and a7754a );
a7763a <=( (not A169) and (not A170) );
a7767a <=( A166 and (not A167) );
a7768a <=( (not A168) and a7767a );
a7769a <=( a7768a and a7763a );
a7773a <=( A267 and (not A266) );
a7774a <=( A265 and a7773a );
a7778a <=( A299 and A298 );
a7779a <=( A268 and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( (not A169) and (not A170) );
a7787a <=( A166 and (not A167) );
a7788a <=( (not A168) and a7787a );
a7789a <=( a7788a and a7783a );
a7793a <=( A267 and (not A266) );
a7794a <=( A265 and a7793a );
a7798a <=( (not A299) and (not A298) );
a7799a <=( A268 and a7798a );
a7800a <=( a7799a and a7794a );
a7803a <=( (not A169) and (not A170) );
a7807a <=( A166 and (not A167) );
a7808a <=( (not A168) and a7807a );
a7809a <=( a7808a and a7803a );
a7813a <=( A267 and (not A266) );
a7814a <=( A265 and a7813a );
a7818a <=( A301 and (not A300) );
a7819a <=( (not A269) and a7818a );
a7820a <=( a7819a and a7814a );
a7823a <=( (not A169) and (not A170) );
a7827a <=( A166 and (not A167) );
a7828a <=( (not A168) and a7827a );
a7829a <=( a7828a and a7823a );
a7833a <=( A267 and (not A266) );
a7834a <=( A265 and a7833a );
a7838a <=( (not A302) and (not A300) );
a7839a <=( (not A269) and a7838a );
a7840a <=( a7839a and a7834a );
a7843a <=( (not A169) and (not A170) );
a7847a <=( A166 and (not A167) );
a7848a <=( (not A168) and a7847a );
a7849a <=( a7848a and a7843a );
a7853a <=( A267 and (not A266) );
a7854a <=( A265 and a7853a );
a7858a <=( A299 and A298 );
a7859a <=( (not A269) and a7858a );
a7860a <=( a7859a and a7854a );
a7863a <=( (not A169) and (not A170) );
a7867a <=( A166 and (not A167) );
a7868a <=( (not A168) and a7867a );
a7869a <=( a7868a and a7863a );
a7873a <=( A267 and (not A266) );
a7874a <=( A265 and a7873a );
a7878a <=( (not A299) and (not A298) );
a7879a <=( (not A269) and a7878a );
a7880a <=( a7879a and a7874a );
a7883a <=( (not A169) and (not A170) );
a7887a <=( A166 and (not A167) );
a7888a <=( (not A168) and a7887a );
a7889a <=( a7888a and a7883a );
a7893a <=( A298 and (not A266) );
a7894a <=( (not A265) and a7893a );
a7898a <=( A301 and A300 );
a7899a <=( (not A299) and a7898a );
a7900a <=( a7899a and a7894a );
a7903a <=( (not A169) and (not A170) );
a7907a <=( A166 and (not A167) );
a7908a <=( (not A168) and a7907a );
a7909a <=( a7908a and a7903a );
a7913a <=( A298 and (not A266) );
a7914a <=( (not A265) and a7913a );
a7918a <=( (not A302) and A300 );
a7919a <=( (not A299) and a7918a );
a7920a <=( a7919a and a7914a );
a7923a <=( (not A169) and (not A170) );
a7927a <=( A166 and (not A167) );
a7928a <=( (not A168) and a7927a );
a7929a <=( a7928a and a7923a );
a7933a <=( (not A298) and (not A266) );
a7934a <=( (not A265) and a7933a );
a7938a <=( A301 and A300 );
a7939a <=( A299 and a7938a );
a7940a <=( a7939a and a7934a );
a7943a <=( (not A169) and (not A170) );
a7947a <=( A166 and (not A167) );
a7948a <=( (not A168) and a7947a );
a7949a <=( a7948a and a7943a );
a7953a <=( (not A298) and (not A266) );
a7954a <=( (not A265) and a7953a );
a7958a <=( (not A302) and A300 );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7964a <=( A167 and A168 );
a7965a <=( A170 and a7964a );
a7969a <=( (not A268) and A267 );
a7970a <=( (not A166) and a7969a );
a7971a <=( a7970a and a7965a );
a7975a <=( (not A299) and A298 );
a7976a <=( A269 and a7975a );
a7980a <=( A302 and (not A301) );
a7981a <=( (not A300) and a7980a );
a7982a <=( a7981a and a7976a );
a7986a <=( A167 and A168 );
a7987a <=( A170 and a7986a );
a7991a <=( (not A268) and A267 );
a7992a <=( (not A166) and a7991a );
a7993a <=( a7992a and a7987a );
a7997a <=( A299 and (not A298) );
a7998a <=( A269 and a7997a );
a8002a <=( A302 and (not A301) );
a8003a <=( (not A300) and a8002a );
a8004a <=( a8003a and a7998a );
a8008a <=( A167 and A168 );
a8009a <=( A170 and a8008a );
a8013a <=( A266 and (not A265) );
a8014a <=( (not A166) and a8013a );
a8015a <=( a8014a and a8009a );
a8019a <=( A269 and (not A268) );
a8020a <=( (not A267) and a8019a );
a8024a <=( A302 and (not A301) );
a8025a <=( A300 and a8024a );
a8026a <=( a8025a and a8020a );
a8030a <=( A167 and A168 );
a8031a <=( A170 and a8030a );
a8035a <=( (not A266) and A265 );
a8036a <=( (not A166) and a8035a );
a8037a <=( a8036a and a8031a );
a8041a <=( A269 and (not A268) );
a8042a <=( (not A267) and a8041a );
a8046a <=( A302 and (not A301) );
a8047a <=( A300 and a8046a );
a8048a <=( a8047a and a8042a );
a8052a <=( (not A167) and A168 );
a8053a <=( A170 and a8052a );
a8057a <=( (not A268) and A267 );
a8058a <=( A166 and a8057a );
a8059a <=( a8058a and a8053a );
a8063a <=( (not A299) and A298 );
a8064a <=( A269 and a8063a );
a8068a <=( A302 and (not A301) );
a8069a <=( (not A300) and a8068a );
a8070a <=( a8069a and a8064a );
a8074a <=( (not A167) and A168 );
a8075a <=( A170 and a8074a );
a8079a <=( (not A268) and A267 );
a8080a <=( A166 and a8079a );
a8081a <=( a8080a and a8075a );
a8085a <=( A299 and (not A298) );
a8086a <=( A269 and a8085a );
a8090a <=( A302 and (not A301) );
a8091a <=( (not A300) and a8090a );
a8092a <=( a8091a and a8086a );
a8096a <=( (not A167) and A168 );
a8097a <=( A170 and a8096a );
a8101a <=( A266 and (not A265) );
a8102a <=( A166 and a8101a );
a8103a <=( a8102a and a8097a );
a8107a <=( A269 and (not A268) );
a8108a <=( (not A267) and a8107a );
a8112a <=( A302 and (not A301) );
a8113a <=( A300 and a8112a );
a8114a <=( a8113a and a8108a );
a8118a <=( (not A167) and A168 );
a8119a <=( A170 and a8118a );
a8123a <=( (not A266) and A265 );
a8124a <=( A166 and a8123a );
a8125a <=( a8124a and a8119a );
a8129a <=( A269 and (not A268) );
a8130a <=( (not A267) and a8129a );
a8134a <=( A302 and (not A301) );
a8135a <=( A300 and a8134a );
a8136a <=( a8135a and a8130a );
a8140a <=( A167 and A168 );
a8141a <=( A169 and a8140a );
a8145a <=( (not A268) and A267 );
a8146a <=( (not A166) and a8145a );
a8147a <=( a8146a and a8141a );
a8151a <=( (not A299) and A298 );
a8152a <=( A269 and a8151a );
a8156a <=( A302 and (not A301) );
a8157a <=( (not A300) and a8156a );
a8158a <=( a8157a and a8152a );
a8162a <=( A167 and A168 );
a8163a <=( A169 and a8162a );
a8167a <=( (not A268) and A267 );
a8168a <=( (not A166) and a8167a );
a8169a <=( a8168a and a8163a );
a8173a <=( A299 and (not A298) );
a8174a <=( A269 and a8173a );
a8178a <=( A302 and (not A301) );
a8179a <=( (not A300) and a8178a );
a8180a <=( a8179a and a8174a );
a8184a <=( A167 and A168 );
a8185a <=( A169 and a8184a );
a8189a <=( A266 and (not A265) );
a8190a <=( (not A166) and a8189a );
a8191a <=( a8190a and a8185a );
a8195a <=( A269 and (not A268) );
a8196a <=( (not A267) and a8195a );
a8200a <=( A302 and (not A301) );
a8201a <=( A300 and a8200a );
a8202a <=( a8201a and a8196a );
a8206a <=( A167 and A168 );
a8207a <=( A169 and a8206a );
a8211a <=( (not A266) and A265 );
a8212a <=( (not A166) and a8211a );
a8213a <=( a8212a and a8207a );
a8217a <=( A269 and (not A268) );
a8218a <=( (not A267) and a8217a );
a8222a <=( A302 and (not A301) );
a8223a <=( A300 and a8222a );
a8224a <=( a8223a and a8218a );
a8228a <=( (not A167) and A168 );
a8229a <=( A169 and a8228a );
a8233a <=( (not A268) and A267 );
a8234a <=( A166 and a8233a );
a8235a <=( a8234a and a8229a );
a8239a <=( (not A299) and A298 );
a8240a <=( A269 and a8239a );
a8244a <=( A302 and (not A301) );
a8245a <=( (not A300) and a8244a );
a8246a <=( a8245a and a8240a );
a8250a <=( (not A167) and A168 );
a8251a <=( A169 and a8250a );
a8255a <=( (not A268) and A267 );
a8256a <=( A166 and a8255a );
a8257a <=( a8256a and a8251a );
a8261a <=( A299 and (not A298) );
a8262a <=( A269 and a8261a );
a8266a <=( A302 and (not A301) );
a8267a <=( (not A300) and a8266a );
a8268a <=( a8267a and a8262a );
a8272a <=( (not A167) and A168 );
a8273a <=( A169 and a8272a );
a8277a <=( A266 and (not A265) );
a8278a <=( A166 and a8277a );
a8279a <=( a8278a and a8273a );
a8283a <=( A269 and (not A268) );
a8284a <=( (not A267) and a8283a );
a8288a <=( A302 and (not A301) );
a8289a <=( A300 and a8288a );
a8290a <=( a8289a and a8284a );
a8294a <=( (not A167) and A168 );
a8295a <=( A169 and a8294a );
a8299a <=( (not A266) and A265 );
a8300a <=( A166 and a8299a );
a8301a <=( a8300a and a8295a );
a8305a <=( A269 and (not A268) );
a8306a <=( (not A267) and a8305a );
a8310a <=( A302 and (not A301) );
a8311a <=( A300 and a8310a );
a8312a <=( a8311a and a8306a );
a8316a <=( (not A168) and (not A169) );
a8317a <=( (not A170) and a8316a );
a8321a <=( A267 and (not A166) );
a8322a <=( A167 and a8321a );
a8323a <=( a8322a and a8317a );
a8327a <=( A298 and A269 );
a8328a <=( (not A268) and a8327a );
a8332a <=( A301 and A300 );
a8333a <=( (not A299) and a8332a );
a8334a <=( a8333a and a8328a );
a8338a <=( (not A168) and (not A169) );
a8339a <=( (not A170) and a8338a );
a8343a <=( A267 and (not A166) );
a8344a <=( A167 and a8343a );
a8345a <=( a8344a and a8339a );
a8349a <=( A298 and A269 );
a8350a <=( (not A268) and a8349a );
a8354a <=( (not A302) and A300 );
a8355a <=( (not A299) and a8354a );
a8356a <=( a8355a and a8350a );
a8360a <=( (not A168) and (not A169) );
a8361a <=( (not A170) and a8360a );
a8365a <=( A267 and (not A166) );
a8366a <=( A167 and a8365a );
a8367a <=( a8366a and a8361a );
a8371a <=( (not A298) and A269 );
a8372a <=( (not A268) and a8371a );
a8376a <=( A301 and A300 );
a8377a <=( A299 and a8376a );
a8378a <=( a8377a and a8372a );
a8382a <=( (not A168) and (not A169) );
a8383a <=( (not A170) and a8382a );
a8387a <=( A267 and (not A166) );
a8388a <=( A167 and a8387a );
a8389a <=( a8388a and a8383a );
a8393a <=( (not A298) and A269 );
a8394a <=( (not A268) and a8393a );
a8398a <=( (not A302) and A300 );
a8399a <=( A299 and a8398a );
a8400a <=( a8399a and a8394a );
a8404a <=( (not A168) and (not A169) );
a8405a <=( (not A170) and a8404a );
a8409a <=( (not A267) and (not A166) );
a8410a <=( A167 and a8409a );
a8411a <=( a8410a and a8405a );
a8415a <=( (not A299) and A298 );
a8416a <=( A268 and a8415a );
a8420a <=( A302 and (not A301) );
a8421a <=( (not A300) and a8420a );
a8422a <=( a8421a and a8416a );
a8426a <=( (not A168) and (not A169) );
a8427a <=( (not A170) and a8426a );
a8431a <=( (not A267) and (not A166) );
a8432a <=( A167 and a8431a );
a8433a <=( a8432a and a8427a );
a8437a <=( A299 and (not A298) );
a8438a <=( A268 and a8437a );
a8442a <=( A302 and (not A301) );
a8443a <=( (not A300) and a8442a );
a8444a <=( a8443a and a8438a );
a8448a <=( (not A168) and (not A169) );
a8449a <=( (not A170) and a8448a );
a8453a <=( (not A267) and (not A166) );
a8454a <=( A167 and a8453a );
a8455a <=( a8454a and a8449a );
a8459a <=( (not A299) and A298 );
a8460a <=( (not A269) and a8459a );
a8464a <=( A302 and (not A301) );
a8465a <=( (not A300) and a8464a );
a8466a <=( a8465a and a8460a );
a8470a <=( (not A168) and (not A169) );
a8471a <=( (not A170) and a8470a );
a8475a <=( (not A267) and (not A166) );
a8476a <=( A167 and a8475a );
a8477a <=( a8476a and a8471a );
a8481a <=( A299 and (not A298) );
a8482a <=( (not A269) and a8481a );
a8486a <=( A302 and (not A301) );
a8487a <=( (not A300) and a8486a );
a8488a <=( a8487a and a8482a );
a8492a <=( (not A168) and (not A169) );
a8493a <=( (not A170) and a8492a );
a8497a <=( A265 and (not A166) );
a8498a <=( A167 and a8497a );
a8499a <=( a8498a and a8493a );
a8503a <=( (not A299) and A298 );
a8504a <=( A266 and a8503a );
a8508a <=( A302 and (not A301) );
a8509a <=( (not A300) and a8508a );
a8510a <=( a8509a and a8504a );
a8514a <=( (not A168) and (not A169) );
a8515a <=( (not A170) and a8514a );
a8519a <=( A265 and (not A166) );
a8520a <=( A167 and a8519a );
a8521a <=( a8520a and a8515a );
a8525a <=( A299 and (not A298) );
a8526a <=( A266 and a8525a );
a8530a <=( A302 and (not A301) );
a8531a <=( (not A300) and a8530a );
a8532a <=( a8531a and a8526a );
a8536a <=( (not A168) and (not A169) );
a8537a <=( (not A170) and a8536a );
a8541a <=( (not A265) and (not A166) );
a8542a <=( A167 and a8541a );
a8543a <=( a8542a and a8537a );
a8547a <=( A268 and A267 );
a8548a <=( A266 and a8547a );
a8552a <=( A302 and (not A301) );
a8553a <=( A300 and a8552a );
a8554a <=( a8553a and a8548a );
a8558a <=( (not A168) and (not A169) );
a8559a <=( (not A170) and a8558a );
a8563a <=( (not A265) and (not A166) );
a8564a <=( A167 and a8563a );
a8565a <=( a8564a and a8559a );
a8569a <=( (not A269) and A267 );
a8570a <=( A266 and a8569a );
a8574a <=( A302 and (not A301) );
a8575a <=( A300 and a8574a );
a8576a <=( a8575a and a8570a );
a8580a <=( (not A168) and (not A169) );
a8581a <=( (not A170) and a8580a );
a8585a <=( (not A265) and (not A166) );
a8586a <=( A167 and a8585a );
a8587a <=( a8586a and a8581a );
a8591a <=( (not A268) and (not A267) );
a8592a <=( A266 and a8591a );
a8596a <=( A301 and (not A300) );
a8597a <=( A269 and a8596a );
a8598a <=( a8597a and a8592a );
a8602a <=( (not A168) and (not A169) );
a8603a <=( (not A170) and a8602a );
a8607a <=( (not A265) and (not A166) );
a8608a <=( A167 and a8607a );
a8609a <=( a8608a and a8603a );
a8613a <=( (not A268) and (not A267) );
a8614a <=( A266 and a8613a );
a8618a <=( (not A302) and (not A300) );
a8619a <=( A269 and a8618a );
a8620a <=( a8619a and a8614a );
a8624a <=( (not A168) and (not A169) );
a8625a <=( (not A170) and a8624a );
a8629a <=( (not A265) and (not A166) );
a8630a <=( A167 and a8629a );
a8631a <=( a8630a and a8625a );
a8635a <=( (not A268) and (not A267) );
a8636a <=( A266 and a8635a );
a8640a <=( A299 and A298 );
a8641a <=( A269 and a8640a );
a8642a <=( a8641a and a8636a );
a8646a <=( (not A168) and (not A169) );
a8647a <=( (not A170) and a8646a );
a8651a <=( (not A265) and (not A166) );
a8652a <=( A167 and a8651a );
a8653a <=( a8652a and a8647a );
a8657a <=( (not A268) and (not A267) );
a8658a <=( A266 and a8657a );
a8662a <=( (not A299) and (not A298) );
a8663a <=( A269 and a8662a );
a8664a <=( a8663a and a8658a );
a8668a <=( (not A168) and (not A169) );
a8669a <=( (not A170) and a8668a );
a8673a <=( A265 and (not A166) );
a8674a <=( A167 and a8673a );
a8675a <=( a8674a and a8669a );
a8679a <=( A268 and A267 );
a8680a <=( (not A266) and a8679a );
a8684a <=( A302 and (not A301) );
a8685a <=( A300 and a8684a );
a8686a <=( a8685a and a8680a );
a8690a <=( (not A168) and (not A169) );
a8691a <=( (not A170) and a8690a );
a8695a <=( A265 and (not A166) );
a8696a <=( A167 and a8695a );
a8697a <=( a8696a and a8691a );
a8701a <=( (not A269) and A267 );
a8702a <=( (not A266) and a8701a );
a8706a <=( A302 and (not A301) );
a8707a <=( A300 and a8706a );
a8708a <=( a8707a and a8702a );
a8712a <=( (not A168) and (not A169) );
a8713a <=( (not A170) and a8712a );
a8717a <=( A265 and (not A166) );
a8718a <=( A167 and a8717a );
a8719a <=( a8718a and a8713a );
a8723a <=( (not A268) and (not A267) );
a8724a <=( (not A266) and a8723a );
a8728a <=( A301 and (not A300) );
a8729a <=( A269 and a8728a );
a8730a <=( a8729a and a8724a );
a8734a <=( (not A168) and (not A169) );
a8735a <=( (not A170) and a8734a );
a8739a <=( A265 and (not A166) );
a8740a <=( A167 and a8739a );
a8741a <=( a8740a and a8735a );
a8745a <=( (not A268) and (not A267) );
a8746a <=( (not A266) and a8745a );
a8750a <=( (not A302) and (not A300) );
a8751a <=( A269 and a8750a );
a8752a <=( a8751a and a8746a );
a8756a <=( (not A168) and (not A169) );
a8757a <=( (not A170) and a8756a );
a8761a <=( A265 and (not A166) );
a8762a <=( A167 and a8761a );
a8763a <=( a8762a and a8757a );
a8767a <=( (not A268) and (not A267) );
a8768a <=( (not A266) and a8767a );
a8772a <=( A299 and A298 );
a8773a <=( A269 and a8772a );
a8774a <=( a8773a and a8768a );
a8778a <=( (not A168) and (not A169) );
a8779a <=( (not A170) and a8778a );
a8783a <=( A265 and (not A166) );
a8784a <=( A167 and a8783a );
a8785a <=( a8784a and a8779a );
a8789a <=( (not A268) and (not A267) );
a8790a <=( (not A266) and a8789a );
a8794a <=( (not A299) and (not A298) );
a8795a <=( A269 and a8794a );
a8796a <=( a8795a and a8790a );
a8800a <=( (not A168) and (not A169) );
a8801a <=( (not A170) and a8800a );
a8805a <=( (not A265) and (not A166) );
a8806a <=( A167 and a8805a );
a8807a <=( a8806a and a8801a );
a8811a <=( (not A299) and A298 );
a8812a <=( (not A266) and a8811a );
a8816a <=( A302 and (not A301) );
a8817a <=( (not A300) and a8816a );
a8818a <=( a8817a and a8812a );
a8822a <=( (not A168) and (not A169) );
a8823a <=( (not A170) and a8822a );
a8827a <=( (not A265) and (not A166) );
a8828a <=( A167 and a8827a );
a8829a <=( a8828a and a8823a );
a8833a <=( A299 and (not A298) );
a8834a <=( (not A266) and a8833a );
a8838a <=( A302 and (not A301) );
a8839a <=( (not A300) and a8838a );
a8840a <=( a8839a and a8834a );
a8844a <=( (not A168) and (not A169) );
a8845a <=( (not A170) and a8844a );
a8849a <=( A267 and A166 );
a8850a <=( (not A167) and a8849a );
a8851a <=( a8850a and a8845a );
a8855a <=( A298 and A269 );
a8856a <=( (not A268) and a8855a );
a8860a <=( A301 and A300 );
a8861a <=( (not A299) and a8860a );
a8862a <=( a8861a and a8856a );
a8866a <=( (not A168) and (not A169) );
a8867a <=( (not A170) and a8866a );
a8871a <=( A267 and A166 );
a8872a <=( (not A167) and a8871a );
a8873a <=( a8872a and a8867a );
a8877a <=( A298 and A269 );
a8878a <=( (not A268) and a8877a );
a8882a <=( (not A302) and A300 );
a8883a <=( (not A299) and a8882a );
a8884a <=( a8883a and a8878a );
a8888a <=( (not A168) and (not A169) );
a8889a <=( (not A170) and a8888a );
a8893a <=( A267 and A166 );
a8894a <=( (not A167) and a8893a );
a8895a <=( a8894a and a8889a );
a8899a <=( (not A298) and A269 );
a8900a <=( (not A268) and a8899a );
a8904a <=( A301 and A300 );
a8905a <=( A299 and a8904a );
a8906a <=( a8905a and a8900a );
a8910a <=( (not A168) and (not A169) );
a8911a <=( (not A170) and a8910a );
a8915a <=( A267 and A166 );
a8916a <=( (not A167) and a8915a );
a8917a <=( a8916a and a8911a );
a8921a <=( (not A298) and A269 );
a8922a <=( (not A268) and a8921a );
a8926a <=( (not A302) and A300 );
a8927a <=( A299 and a8926a );
a8928a <=( a8927a and a8922a );
a8932a <=( (not A168) and (not A169) );
a8933a <=( (not A170) and a8932a );
a8937a <=( (not A267) and A166 );
a8938a <=( (not A167) and a8937a );
a8939a <=( a8938a and a8933a );
a8943a <=( (not A299) and A298 );
a8944a <=( A268 and a8943a );
a8948a <=( A302 and (not A301) );
a8949a <=( (not A300) and a8948a );
a8950a <=( a8949a and a8944a );
a8954a <=( (not A168) and (not A169) );
a8955a <=( (not A170) and a8954a );
a8959a <=( (not A267) and A166 );
a8960a <=( (not A167) and a8959a );
a8961a <=( a8960a and a8955a );
a8965a <=( A299 and (not A298) );
a8966a <=( A268 and a8965a );
a8970a <=( A302 and (not A301) );
a8971a <=( (not A300) and a8970a );
a8972a <=( a8971a and a8966a );
a8976a <=( (not A168) and (not A169) );
a8977a <=( (not A170) and a8976a );
a8981a <=( (not A267) and A166 );
a8982a <=( (not A167) and a8981a );
a8983a <=( a8982a and a8977a );
a8987a <=( (not A299) and A298 );
a8988a <=( (not A269) and a8987a );
a8992a <=( A302 and (not A301) );
a8993a <=( (not A300) and a8992a );
a8994a <=( a8993a and a8988a );
a8998a <=( (not A168) and (not A169) );
a8999a <=( (not A170) and a8998a );
a9003a <=( (not A267) and A166 );
a9004a <=( (not A167) and a9003a );
a9005a <=( a9004a and a8999a );
a9009a <=( A299 and (not A298) );
a9010a <=( (not A269) and a9009a );
a9014a <=( A302 and (not A301) );
a9015a <=( (not A300) and a9014a );
a9016a <=( a9015a and a9010a );
a9020a <=( (not A168) and (not A169) );
a9021a <=( (not A170) and a9020a );
a9025a <=( A265 and A166 );
a9026a <=( (not A167) and a9025a );
a9027a <=( a9026a and a9021a );
a9031a <=( (not A299) and A298 );
a9032a <=( A266 and a9031a );
a9036a <=( A302 and (not A301) );
a9037a <=( (not A300) and a9036a );
a9038a <=( a9037a and a9032a );
a9042a <=( (not A168) and (not A169) );
a9043a <=( (not A170) and a9042a );
a9047a <=( A265 and A166 );
a9048a <=( (not A167) and a9047a );
a9049a <=( a9048a and a9043a );
a9053a <=( A299 and (not A298) );
a9054a <=( A266 and a9053a );
a9058a <=( A302 and (not A301) );
a9059a <=( (not A300) and a9058a );
a9060a <=( a9059a and a9054a );
a9064a <=( (not A168) and (not A169) );
a9065a <=( (not A170) and a9064a );
a9069a <=( (not A265) and A166 );
a9070a <=( (not A167) and a9069a );
a9071a <=( a9070a and a9065a );
a9075a <=( A268 and A267 );
a9076a <=( A266 and a9075a );
a9080a <=( A302 and (not A301) );
a9081a <=( A300 and a9080a );
a9082a <=( a9081a and a9076a );
a9086a <=( (not A168) and (not A169) );
a9087a <=( (not A170) and a9086a );
a9091a <=( (not A265) and A166 );
a9092a <=( (not A167) and a9091a );
a9093a <=( a9092a and a9087a );
a9097a <=( (not A269) and A267 );
a9098a <=( A266 and a9097a );
a9102a <=( A302 and (not A301) );
a9103a <=( A300 and a9102a );
a9104a <=( a9103a and a9098a );
a9108a <=( (not A168) and (not A169) );
a9109a <=( (not A170) and a9108a );
a9113a <=( (not A265) and A166 );
a9114a <=( (not A167) and a9113a );
a9115a <=( a9114a and a9109a );
a9119a <=( (not A268) and (not A267) );
a9120a <=( A266 and a9119a );
a9124a <=( A301 and (not A300) );
a9125a <=( A269 and a9124a );
a9126a <=( a9125a and a9120a );
a9130a <=( (not A168) and (not A169) );
a9131a <=( (not A170) and a9130a );
a9135a <=( (not A265) and A166 );
a9136a <=( (not A167) and a9135a );
a9137a <=( a9136a and a9131a );
a9141a <=( (not A268) and (not A267) );
a9142a <=( A266 and a9141a );
a9146a <=( (not A302) and (not A300) );
a9147a <=( A269 and a9146a );
a9148a <=( a9147a and a9142a );
a9152a <=( (not A168) and (not A169) );
a9153a <=( (not A170) and a9152a );
a9157a <=( (not A265) and A166 );
a9158a <=( (not A167) and a9157a );
a9159a <=( a9158a and a9153a );
a9163a <=( (not A268) and (not A267) );
a9164a <=( A266 and a9163a );
a9168a <=( A299 and A298 );
a9169a <=( A269 and a9168a );
a9170a <=( a9169a and a9164a );
a9174a <=( (not A168) and (not A169) );
a9175a <=( (not A170) and a9174a );
a9179a <=( (not A265) and A166 );
a9180a <=( (not A167) and a9179a );
a9181a <=( a9180a and a9175a );
a9185a <=( (not A268) and (not A267) );
a9186a <=( A266 and a9185a );
a9190a <=( (not A299) and (not A298) );
a9191a <=( A269 and a9190a );
a9192a <=( a9191a and a9186a );
a9196a <=( (not A168) and (not A169) );
a9197a <=( (not A170) and a9196a );
a9201a <=( A265 and A166 );
a9202a <=( (not A167) and a9201a );
a9203a <=( a9202a and a9197a );
a9207a <=( A268 and A267 );
a9208a <=( (not A266) and a9207a );
a9212a <=( A302 and (not A301) );
a9213a <=( A300 and a9212a );
a9214a <=( a9213a and a9208a );
a9218a <=( (not A168) and (not A169) );
a9219a <=( (not A170) and a9218a );
a9223a <=( A265 and A166 );
a9224a <=( (not A167) and a9223a );
a9225a <=( a9224a and a9219a );
a9229a <=( (not A269) and A267 );
a9230a <=( (not A266) and a9229a );
a9234a <=( A302 and (not A301) );
a9235a <=( A300 and a9234a );
a9236a <=( a9235a and a9230a );
a9240a <=( (not A168) and (not A169) );
a9241a <=( (not A170) and a9240a );
a9245a <=( A265 and A166 );
a9246a <=( (not A167) and a9245a );
a9247a <=( a9246a and a9241a );
a9251a <=( (not A268) and (not A267) );
a9252a <=( (not A266) and a9251a );
a9256a <=( A301 and (not A300) );
a9257a <=( A269 and a9256a );
a9258a <=( a9257a and a9252a );
a9262a <=( (not A168) and (not A169) );
a9263a <=( (not A170) and a9262a );
a9267a <=( A265 and A166 );
a9268a <=( (not A167) and a9267a );
a9269a <=( a9268a and a9263a );
a9273a <=( (not A268) and (not A267) );
a9274a <=( (not A266) and a9273a );
a9278a <=( (not A302) and (not A300) );
a9279a <=( A269 and a9278a );
a9280a <=( a9279a and a9274a );
a9284a <=( (not A168) and (not A169) );
a9285a <=( (not A170) and a9284a );
a9289a <=( A265 and A166 );
a9290a <=( (not A167) and a9289a );
a9291a <=( a9290a and a9285a );
a9295a <=( (not A268) and (not A267) );
a9296a <=( (not A266) and a9295a );
a9300a <=( A299 and A298 );
a9301a <=( A269 and a9300a );
a9302a <=( a9301a and a9296a );
a9306a <=( (not A168) and (not A169) );
a9307a <=( (not A170) and a9306a );
a9311a <=( A265 and A166 );
a9312a <=( (not A167) and a9311a );
a9313a <=( a9312a and a9307a );
a9317a <=( (not A268) and (not A267) );
a9318a <=( (not A266) and a9317a );
a9322a <=( (not A299) and (not A298) );
a9323a <=( A269 and a9322a );
a9324a <=( a9323a and a9318a );
a9328a <=( (not A168) and (not A169) );
a9329a <=( (not A170) and a9328a );
a9333a <=( (not A265) and A166 );
a9334a <=( (not A167) and a9333a );
a9335a <=( a9334a and a9329a );
a9339a <=( (not A299) and A298 );
a9340a <=( (not A266) and a9339a );
a9344a <=( A302 and (not A301) );
a9345a <=( (not A300) and a9344a );
a9346a <=( a9345a and a9340a );
a9350a <=( (not A168) and (not A169) );
a9351a <=( (not A170) and a9350a );
a9355a <=( (not A265) and A166 );
a9356a <=( (not A167) and a9355a );
a9357a <=( a9356a and a9351a );
a9361a <=( A299 and (not A298) );
a9362a <=( (not A266) and a9361a );
a9366a <=( A302 and (not A301) );
a9367a <=( (not A300) and a9366a );
a9368a <=( a9367a and a9362a );
a9372a <=( (not A168) and (not A169) );
a9373a <=( (not A170) and a9372a );
a9377a <=( A267 and (not A166) );
a9378a <=( A167 and a9377a );
a9379a <=( a9378a and a9373a );
a9383a <=( A298 and A269 );
a9384a <=( (not A268) and a9383a );
a9387a <=( (not A300) and (not A299) );
a9390a <=( A302 and (not A301) );
a9391a <=( a9390a and a9387a );
a9392a <=( a9391a and a9384a );
a9396a <=( (not A168) and (not A169) );
a9397a <=( (not A170) and a9396a );
a9401a <=( A267 and (not A166) );
a9402a <=( A167 and a9401a );
a9403a <=( a9402a and a9397a );
a9407a <=( (not A298) and A269 );
a9408a <=( (not A268) and a9407a );
a9411a <=( (not A300) and A299 );
a9414a <=( A302 and (not A301) );
a9415a <=( a9414a and a9411a );
a9416a <=( a9415a and a9408a );
a9420a <=( (not A168) and (not A169) );
a9421a <=( (not A170) and a9420a );
a9425a <=( (not A265) and (not A166) );
a9426a <=( A167 and a9425a );
a9427a <=( a9426a and a9421a );
a9431a <=( (not A268) and (not A267) );
a9432a <=( A266 and a9431a );
a9435a <=( A300 and A269 );
a9438a <=( A302 and (not A301) );
a9439a <=( a9438a and a9435a );
a9440a <=( a9439a and a9432a );
a9444a <=( (not A168) and (not A169) );
a9445a <=( (not A170) and a9444a );
a9449a <=( A265 and (not A166) );
a9450a <=( A167 and a9449a );
a9451a <=( a9450a and a9445a );
a9455a <=( (not A268) and (not A267) );
a9456a <=( (not A266) and a9455a );
a9459a <=( A300 and A269 );
a9462a <=( A302 and (not A301) );
a9463a <=( a9462a and a9459a );
a9464a <=( a9463a and a9456a );
a9468a <=( (not A168) and (not A169) );
a9469a <=( (not A170) and a9468a );
a9473a <=( A267 and A166 );
a9474a <=( (not A167) and a9473a );
a9475a <=( a9474a and a9469a );
a9479a <=( A298 and A269 );
a9480a <=( (not A268) and a9479a );
a9483a <=( (not A300) and (not A299) );
a9486a <=( A302 and (not A301) );
a9487a <=( a9486a and a9483a );
a9488a <=( a9487a and a9480a );
a9492a <=( (not A168) and (not A169) );
a9493a <=( (not A170) and a9492a );
a9497a <=( A267 and A166 );
a9498a <=( (not A167) and a9497a );
a9499a <=( a9498a and a9493a );
a9503a <=( (not A298) and A269 );
a9504a <=( (not A268) and a9503a );
a9507a <=( (not A300) and A299 );
a9510a <=( A302 and (not A301) );
a9511a <=( a9510a and a9507a );
a9512a <=( a9511a and a9504a );
a9516a <=( (not A168) and (not A169) );
a9517a <=( (not A170) and a9516a );
a9521a <=( (not A265) and A166 );
a9522a <=( (not A167) and a9521a );
a9523a <=( a9522a and a9517a );
a9527a <=( (not A268) and (not A267) );
a9528a <=( A266 and a9527a );
a9531a <=( A300 and A269 );
a9534a <=( A302 and (not A301) );
a9535a <=( a9534a and a9531a );
a9536a <=( a9535a and a9528a );
a9540a <=( (not A168) and (not A169) );
a9541a <=( (not A170) and a9540a );
a9545a <=( A265 and A166 );
a9546a <=( (not A167) and a9545a );
a9547a <=( a9546a and a9541a );
a9551a <=( (not A268) and (not A267) );
a9552a <=( (not A266) and a9551a );
a9555a <=( A300 and A269 );
a9558a <=( A302 and (not A301) );
a9559a <=( a9558a and a9555a );
a9560a <=( a9559a and a9552a );
end x25_23x_behav;
| gpl-3.0 | b11c46904ead3050f6d26902b0894d53 | 0.608337 | 2.137251 | false | false | false | false |
jdryg/tis100cpu | node_port_tb.vhd | 1 | 2,047 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY node_port_tb IS
END node_port_tb;
ARCHITECTURE behavior OF node_port_tb IS
constant PORT_SIZE: integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT node_port
GENERIC (WIDTH: integer := PORT_SIZE);
PORT(
I_clk : IN std_logic;
I_reset : IN std_logic;
I_writeEnable : IN std_logic;
I_readEnable : IN std_logic;
I_dataIn : IN std_logic_vector(WIDTH-1 downto 0);
O_dataOut : OUT std_logic_vector(WIDTH-1 downto 0);
O_dataOutValid : OUT std_logic
);
END COMPONENT;
--Inputs
signal I_clk : std_logic := '0';
signal I_reset : std_logic := '0';
signal I_writeEnable : std_logic := '0';
signal I_readEnable : std_logic := '0';
signal I_dataIn : std_logic_vector(PORT_SIZE-1 downto 0) := (others => '0');
--Outputs
signal O_dataOut : std_logic_vector(PORT_SIZE-1 downto 0);
signal O_dataOutValid : std_logic;
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: node_port
GENERIC MAP (WIDTH => PORT_SIZE)
PORT MAP (
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => I_writeEnable,
I_readEnable => I_readEnable,
I_dataIn => I_dataIn,
O_dataOut => O_dataOut,
O_dataOutValid => O_dataOutValid
);
-- Clock process definitions
I_clk_process :process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- Reset FSM
I_reset <= '1';
wait for I_clk_period;
I_reset <= '0';
wait for I_clk_period/2;
I_writeEnable <= '1';
I_readEnable <= '1';
I_dataIn <= X"0001";
wait for I_clk_period;
I_writeEnable <= '0';
wait for I_clk_period;
I_writeEnable <= '1';
wait;
end process;
END;
| mit | 6ee15e510d68117eaf3923f16d68d0d5 | 0.574988 | 3.389073 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_ibea.vhd | 1 | 2,902 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_ibea_entity;
ARCHITECTURE ewf_ibea_description OF ewf_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
WHEN "00000011" =>
register3 := register2 + 5;
register4 := input2 + 6;
WHEN "00000100" =>
register3 := register4 + register3;
WHEN "00000101" =>
register5 := register3 * 8;
WHEN "00000110" =>
register6 := register3 * 10;
register5 := register2 + register5;
WHEN "00000111" =>
register3 := register3 + register5;
register2 := register2 + register5;
WHEN "00001000" =>
register6 := register4 + register6;
register2 := register2 * 12;
WHEN "00001001" =>
register4 := register4 + register6;
output1 <= register6 + register3;
WHEN "00001010" =>
register3 := register4 * 15;
register2 := register1 + register2;
WHEN "00001011" =>
register1 := register1 + register2;
WHEN "00001100" =>
register1 := register1 * 17;
register4 := register5 + register2;
WHEN "00001101" =>
register1 := register1 + 19;
WHEN "00001110" =>
output2 <= register2 + register1;
register1 := register4 + 22;
WHEN "00001111" =>
register2 := register1 * 24;
WHEN "00010000" =>
register2 := register2 + 26;
WHEN "00010001" =>
output3 <= register1 + register2;
register1 := register3 + 29;
WHEN "00010010" =>
register2 := register6 + register1;
WHEN "00010011" =>
register2 := register2 + 31;
WHEN "00010100" =>
register3 := register2 * 33;
register4 := register1 + 35;
WHEN "00010101" =>
register3 := register3 + 37;
register4 := register4 * 39;
WHEN "00010110" =>
output4 <= register2 + register3;
output5 <= register1 + register4;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_ibea_description; | gpl-3.0 | 26e4ce894a50e39fd8b11303ba118ed7 | 0.647484 | 3.15778 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_con.vhd | 1 | 5,845 | ---------------------------------------------------------------------
--
-- Functional Unit Multiplexers:
--
-- MX_MULT00 = {00: [a, b], 01: [e, f], 10: [g, t2]}
-- MX_MULT01 = {0: [c, d], 1: [t0, t1]}
-- MX_SUB00 = {0: [t3, h], 1: [t5, t4]}
--
-- Register Multiplexers:
--
-- MX_REG00 = {0: i, 1: t0}
-- MX_REG01 = {0: t1, 1: t5}
-- MX_REG02 = {0: e, 1: t4}
-- MX_REG03 = {0: a, 1: t3}
-- MX_REG04 = {0: b, 1: t2}
--
-- Order of Operations:
--
-- Cycle 0: MULT.op1(a, b), MULT.op2(c, d)
-- Cycle 1: MULT.op4(t0, t1), MULT.op3(e, f)
-- Cycle 2: SUB.op6(t3, h), MULT.op5(g, t2)
-- Cycle 3: SUB.op7(t5, t4)
--
-- Expressions:
--
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity input_controller is
port
(
clock, reset, s_tart : IN std_logic;
finish : OUT std_logic;
control_out : OUT std_logic_vector(0 to 18)
);
end input_controller;
architecture moore of input_controller is
signal current_state, next_state : integer := 0;
signal internal_finish : std_logic := '0';
signal control_bus : std_logic_vector(0 to 18) := "0000000000000000000";
begin
process(current_state)
begin
case current_state is
when 0 =>
control_bus(0) <= '1'; -- REG00: store output from operation op1
control_bus(1) <= '1'; -- REG01: store output from operation op2
control_bus(2) <= '1'; -- REG02: store input e
control_bus(3) <= '1'; -- REG03: store input a
control_bus(4) <= '1'; -- REG04: store input b
control_bus(5) <= '1'; -- REG05: store input h
control_bus(6) <= '1'; -- REG06: store input g
control_bus(7) <= '1'; -- REG07: store input f
control_bus(8) <= '1'; -- REG08: store input d
control_bus(9) <= '1'; -- REG09: store input c
control_bus(10 to 11) <= "00"; -- 00 MX_MULT00: select op1
control_bus(12) <= '0'; -- 0 MX_MULT01: select op2
control_bus(13) <= 'X'; -- X MX_SUB00
control_bus(14) <= '1'; -- 1 MX_REG00: select t0
control_bus(15) <= '0'; -- 0 MX_REG01: select t1
control_bus(16) <= '0'; -- 0 MX_REG02: select e
control_bus(17) <= '0'; -- 0 MX_REG03: select a
control_bus(18) <= '0'; -- 0 MX_REG04: select b
-- Binary: 1111111111000X10000
-- Hex: ffe10
internal_finish <= '0';
next_state <= 1;
when 1 =>
control_bus(0) <= '0'; -- REG00: keep value
control_bus(1) <= '0'; -- REG01: keep value
control_bus(2) <= '0'; -- REG02: keep value
control_bus(3) <= '1'; -- REG03: store output from operation op4
control_bus(4) <= '1'; -- REG04: store output from operation op3
control_bus(5) <= '0'; -- REG05: keep value
control_bus(6) <= '0'; -- REG06: keep value
control_bus(7) <= '0'; -- REG07: keep value
control_bus(8) <= '0'; -- REG08: keep value
control_bus(9) <= '0'; -- REG09: keep value
control_bus(10 to 11) <= "01"; -- 01 MX_MULT00: select op3
control_bus(12) <= '1'; -- 1 MX_MULT01: select op4
control_bus(13) <= 'X'; -- X MX_SUB00
control_bus(14) <= '1'; -- 1 MX_REG00: select t0
control_bus(15) <= '0'; -- 0 MX_REG01: select t1
control_bus(16) <= '0'; -- 0 MX_REG02: select e
control_bus(17) <= '1'; -- 1 MX_REG03: select t3
control_bus(18) <= '1'; -- 1 MX_REG04: select t2
-- Binary: 0001100000011X10011
-- Hex: 1c0d3
internal_finish <= '0';
next_state <= 2;
when 2 =>
control_bus(0) <= '0'; -- REG00: keep value
control_bus(1) <= '1'; -- REG01: store output from operation op6
control_bus(2) <= '1'; -- REG02: store output from operation op5
control_bus(3) <= '0'; -- REG03: keep value
control_bus(4) <= '0'; -- REG04: keep value
control_bus(5) <= '0'; -- REG05: keep value
control_bus(6) <= '0'; -- REG06: keep value
control_bus(7) <= '0'; -- REG07: keep value
control_bus(8) <= '0'; -- REG08: keep value
control_bus(9) <= '0'; -- REG09: keep value
control_bus(10 to 11) <= "10"; -- 10 MX_MULT00: select op5
control_bus(12) <= 'X'; -- X MX_MULT01
control_bus(13) <= '0'; -- 0 MX_SUB00: select op6
control_bus(14) <= 'X'; -- X MX_REG00
control_bus(15) <= '1'; -- 1 MX_REG01: select t5
control_bus(16) <= '1'; -- 1 MX_REG02: select t4
control_bus(17) <= '1'; -- 1 MX_REG03: select t3
control_bus(18) <= '1'; -- 1 MX_REG04: select t2
-- Binary: 011000000010X0X1111
-- Hex: 6010f
internal_finish <= '0';
next_state <= 3;
when 3 =>
control_bus(0) <= '1'; -- REG00: store output from operation op7
control_bus(1) <= '0'; -- REG01: keep value
control_bus(2) <= '0'; -- REG02: keep value
control_bus(3) <= '0'; -- REG03: keep value
control_bus(4) <= '0'; -- REG04: keep value
control_bus(5) <= '0'; -- REG05: keep value
control_bus(6) <= '0'; -- REG06: keep value
control_bus(7) <= '0'; -- REG07: keep value
control_bus(8) <= '0'; -- REG08: keep value
control_bus(9) <= '0'; -- REG09: keep value
control_bus(10 to 11) <= "XX"; -- XX MX_MULT00
control_bus(12) <= 'X'; -- X MX_MULT01
control_bus(13) <= '1'; -- 1 MX_SUB00: select op7
control_bus(14) <= '0'; -- 0 MX_REG00: select i
control_bus(15) <= '1'; -- 1 MX_REG01: select t5
control_bus(16) <= '1'; -- 1 MX_REG02: select t4
control_bus(17) <= 'X'; -- X MX_REG03
control_bus(18) <= 'X'; -- X MX_REG04
-- Binary: 1000000000XXX1011XX
-- Hex: 8002c
internal_finish <= '1';
next_state <= 0;
when others => null;
end case;
end process;
process(clock, reset)
begin
if (reset = '1' and reset'event) then
current_state <= 0;
control_out <= control_bus;
finish <= internal_finish;
elsif (clock = '1' and clock'event) then
current_state <= next_state;
control_out <= control_bus;
finish <= internal_finish;
end if;
end process;
end moore;
| mit | f5626f386b32fbb1bde278232fee29c4 | 0.551754 | 2.617555 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/metaheurísticas/hal_nsga2.vhd | 1 | 1,546 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:04:40)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_nsga2_entity;
ARCHITECTURE hal_nsga2_description OF hal_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "00101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_nsga2_description; | gpl-3.0 | 4e9e44ed128abf028a0cb93e14ba3063 | 0.655239 | 2.956023 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/ram_module.vhd | 1 | 76,228 | `protect begin_protected
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| apache-2.0 | 2e0bd052bfcb3d1d7ec54bb73bf6dd6c | 0.952629 | 1.823593 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/BUFFER_DATA.vhd | 2 | 2,672 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.CONSTANTS.all;
entity DATA_BUFFER is
port(
rst : in std_logic;
row_0 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- First line of the buffer. Must be read constantly by the ip manager
--PORT_0
data_cpu : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address_cpu : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_CPU : in std_logic;
RE_CPU : in std_logic;
GE_CPU : in std_logic;
--PORT_1
data_in_ip : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_out_ip : out std_logic_vector (DATA_WIDTH-1 downto 0);
address_ip : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_IP : in std_logic;
RE_IP : in std_logic;
GE_IP : in std_logic
);
end entity DATA_BUFFER;
architecture BEHAVIOURAL of DATA_BUFFER is
-- 64 x 16 buffer
type mem_type is array (0 to (2**ADD_WIDTH)-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : mem_type;
signal tmp_cpu : std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- Memory Write Block
MEM_WRITE: process (rst, data_cpu, address_cpu, WE_CPU, GE_CPU, data_in_ip, address_ip, WE_IP, GE_IP ) begin
if rst ='1' then
mem <= (others => (others => '0' ));
else
-- In case of simultaneus write from both CPU and IP, CPU has priority
if (GE_CPU = '1' and WE_CPU = '1') then
mem(conv_integer(address_cpu)) <= data_cpu;
elsif (GE_IP = '1' and WE_IP = '1') then
mem(conv_integer(address_ip)) <= data_in_ip;
end if;
end if;
end process;
-- Tri-State Buffer control
data_cpu <= tmp_cpu when (GE_CPU = '1' and RE_CPU = '1' and WE_CPU = '0') else (others=>'Z');
-- Memory Read Block
row_0 <= mem(0);
-- In case of simultaneus write and read, write has priority
-- Simultaneous read from both CPU and IP is possible
tmp_cpu <= mem(conv_integer(address_cpu));
data_out_ip <= mem(conv_integer(address_ip)) when (GE_IP = '1' and RE_IP = '1' and WE_IP = '0');
-- MEM_READ: process (address_cpu, GE_CPU, RE_CPU, WE_CPU, address_ip, GE_IP, RE_IP, WE_IP, mem) begin
-- -- In case of simultaneus write and read, write has priority
-- -- Simultaneous read from both CPU and IP is possible
-- if (GE_CPU = '1' and RE_CPU = '1' and WE_CPU = '0') then
-- tmp_cpu <= mem(conv_integer(address_cpu));
-- end if;
-- if (GE_IP = '1' and RE_IP = '1' and WE_IP = '0') then
-- data_out_ip <= mem(conv_integer(address_ip));
-- end if;
-- end process;
end architecture BEHAVIOURAL; | lgpl-3.0 | 030470f71a9a05c1075a7f5539e74f3b | 0.607784 | 2.815595 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_types_pkg.vhd | 1 | 10,388 | `protect begin_protected
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| apache-2.0 | 3b11f88083be27c2a555b0db0cc8132c | 0.926454 | 1.912723 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/direct_path_cntr.vhd | 15 | 12,275 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr.vhd
--
-- Description: This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n is false,
-- Dout increments by one each time Cnt_en is true at
-- the positive edge of Clk.
--
-- The implementation has a one-LUT delay (via the XORCY)
-- in direct pass-through mode and the same delay plus
-- carry-chain propogation in count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/30/2003 -- First version
--
-- <initials> <date>
-- ^^^^^^
-- Description of changes. If multiple lines are needed to fully describe
-- the changes made to the design, these lines should align with each other.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end direct_path_cntr;
library unisim;
use unisim.all;
architecture imp of direct_path_cntr is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
component FDE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component FDE;
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
begin
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
signal gen_cry: std_logic;
begin
gen_cry <= '1' when j = C_WIDTH-1 else '0'; -- cntrl increments
-- at LSB
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
LSB_LUT_GEN: if j = C_WIDTH-1 generate
begin
lut_out(j) <= not q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
--
NON_LSB_LUT_GEN: if j /= C_WIDTH-1 generate
begin
lut_out(j) <= q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
------------------------------------------------------------------------
-- Propagate the carry out.
------------------------------------------------------------------------
LSB_MUXCY_GEN: if j = C_WIDTH-1 generate
signal sel_cntr_and_Load_n : std_logic;
begin
I_MULT_AND : MULT_AND
port map (
LO => sel_cntr_and_Load_n,
I1 => sel_cntr,
I0 => Load_n
);
MUXCY_i1: MUXCY
port map (
DI => sel_cntr_and_Load_n,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
NON_LSB_MUXCY_GEN: if j /= C_WIDTH-1 generate
begin
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDRE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| apache-2.0 | cc3b205002d1363dee26a2ef2ed4a48a | 0.421589 | 4.874901 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/delay.vhd | 5 | 10,088 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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| apache-2.0 | 0d383dd11ef5ced115fcf219722bb7d6 | 0.925059 | 1.916413 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/lmb_bram_if_cntlr.vhd | 1 | 50,495 | -------------------------------------------------------------------------------
-- $Id: lmb_bram_if_cntlr.vhd,v 1.1.2.13 2010/11/25 12:28:48 stefana Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.13 $
-- Date: $Date: 2010/11/25 12:28:48 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_ENCODE : boolean;
C_USE_LUT6 : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_USE_LUT6 : boolean;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_USE_LUT6 : boolean := Family_To_LUT_Size(String_To_Family(C_FAMILY,false)) = 6;
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
| apache-2.0 | fcb29d98222f25d4f5df82dd1bfba9c3 | 0.536251 | 3.59933 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/lmb_bram_if_funcs.vhd | 1 | 8,246 | -------------------------------------------------------------------------------
-- $Id: lmb_bram_if_funcs.vhd,v 1.1.2.4 2010/09/28 11:56:10 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.4 $
-- Date: $Date: 2010/09/28 11:56:10 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ARTIXU,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "artixu") or Equal_String(S, "artixul") or Equal_String(S, "aartixu") or
Equal_String(S, "qartixu") or Equal_String(S, "qartixul") then
return ARTIXU;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
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`protect end_protected
| apache-2.0 | e41e846b7c8659f291743dd95fafb362 | 0.925375 | 1.913568 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sim_1/new/testeverything.vhd | 1 | 737 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity testeverything_tb is
end testeverything_tb;
architecture Behavioral of testeverything_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
signal SDA, SCL, USER_RESET: std_logic;
begin
SDA <= 'H';
SCL <= 'H';
clock <= not clock after 7.57575757 ns;
i2cclient : entity work.ADS7830(RTL)
port map (
SDA => SDA,
SCL => SCL
);
united : entity work.unite(Behavioral)
port map (
LED => led,
CLK_66MHZ => clock,
SDA => SDA,
SCL => SCL,
USER_RESET => USER_RESET
);
stimuli : process
begin
USER_RESET <= '1';
wait for 10us;
USER_RESET <= '0';
wait for 1000ms;
wait;
end process;
end Behavioral;
| agpl-3.0 | 0b57b270b0c569fce911e6a215f66730 | 0.660787 | 2.739777 | false | true | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/asap-alap-random/fir2_asap.vhd | 1 | 3,694 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:42:49)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_asap_entity;
ARCHITECTURE fir2_asap_description OF fir2_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
register3 := not input3 or input3;
register4 := not input4 or input4;
register5 := not input5 or input5;
register6 := not input6 or input6;
register7 := not input7 or input7;
register8 := not input8 or input8;
register9 := not input9 or input9;
register10 := not input10 or input10;
register11 := not input11 or input11;
register12 := not input12 or input12;
register13 := not input13 or input13;
register14 := not input14 or input14;
register15 := not input15 or input15;
register16 := not input16 or input16;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := register3 + register6;
register3 := register4 + register5;
register4 := register7 + register8;
register5 := register10 + register9;
register6 := register11 + register12;
register7 := register14 + register13;
register8 := register16 + register15;
WHEN "00000011" =>
register1 := register1 * 18;
register2 := register2 * 20;
register3 := register3 * 22;
register4 := register4 * 24;
register5 := register5 * 26;
register6 := register6 * 28;
register7 := register7 * 30;
register8 := register8 * 32;
WHEN "00000100" =>
register4 := register4 + register5;
WHEN "00000101" =>
register4 := register6 + register4;
WHEN "00000110" =>
register4 := register7 + register4;
WHEN "00000111" =>
register3 := register3 + register4;
WHEN "00001000" =>
register1 := register1 + register3;
WHEN "00001001" =>
register1 := register2 + register1;
WHEN "00001010" =>
register1 := register8 + register1;
WHEN "00001011" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_asap_description; | gpl-3.0 | a4a7bb1054d1b8b3b0dce15d353a8095 | 0.677856 | 3.229021 | false | false | false | false |
sils1297/HWPrak14 | task_2/project_2/project_2.srcs/sim_1/new/LEDPWM_tb.vhd | 1 | 476 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM_tb is
end LEDPWM_tb;
architecture Behavioral of LEDPWM_tb is
signal led : std_ulogic_vector(3 downto 0);
signal clock : std_ulogic := '0';
begin
uut : entity work.Dimmer(DimmerArchitecture)
generic map (WIDTH => 25)
port map (
LED => led,
CLK_66MHZ => clock
);
clock <= not clock after 7.57575757 ns;
stimuli : process
begin
wait for 5 sec;
end process;
end Behavioral;
| agpl-3.0 | 23158bd2202ba68fefecac94deed6d7d | 0.701681 | 2.884848 | false | false | false | false |
BBN-Q/APS2-Comms | src/ip/cpld_bridge/cpld_bridge_pkg.vhd | 1 | 6,952 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package CPLD_bridge_pkg is
--Sort out whether we are in simulation or synthesis
constant in_simulation : boolean := false
--pragma synthesis_off
or true
--pragma synthesis_on
;
constant in_synthesis : boolean := not in_simulation;
function byte_swap(word_in : std_logic_vector) return std_logic_vector;
component axis_frame_length_adjust
generic (
DATA_WIDTH : natural := 8;
KEEP_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
--AXIS input
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tkeep : in std_logic_vector(KEEP_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
--AXIS output
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tkeep : out std_logic_vector(KEEP_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic;
--status
status_valid : out std_logic;
status_ready : in std_logic;
status_frame_pad : out std_logic;
status_frame_truncate : out std_logic;
status_frame_length : out std_logic_vector(15 downto 0);
status_frame_original_length : out std_logic_vector(15 downto 0);
--control
length_min : in std_logic_vector(15 downto 0);
length_max : in std_logic_vector(15 downto 0)
);
end component;
component axis_adapter
generic (
INPUT_DATA_WIDTH : natural := 8;
INPUT_KEEP_WIDTH : natural := 1;
OUTPUT_DATA_WIDTH : natural := 8;
OUTPUT_KEEP_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
--AXIS input
input_axis_tdata : in std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
input_axis_tkeep : in std_logic_vector(INPUT_KEEP_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
--AXIS input
output_axis_tdata : out std_logic_vector(OUTPUT_DATA_WIDTH-1 downto 0);
output_axis_tkeep : out std_logic_vector(OUTPUT_KEEP_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
-- comment out this component declaration for simulation
component ApsMsgProc
port
(
-- Interface to MAC to get Ethernet packets
MAC_CLK : in std_logic; -- Clock for command FIFO interface
RESET : in std_logic; -- Reset for Command Interface
MAC_RXD : in std_logic_vector(7 downto 0); -- Data read from input FIFO
MAC_RX_VALID : in std_logic; -- Set when input fifo empty
MAC_RX_EOP : in std_logic; -- Marks the end of a receive packet in Ethernet RX FIFO
MAC_BAD_FCS : in std_logic; -- Set during EOP/VALID received packet had CRC error
MAC_TXD : out std_logic_vector(7 downto 0); -- Data to write to output FIFO
MAC_TX_RDY : in std_logic; -- Set when MAC can accept data
MAC_TX_VALID : out std_logic; -- Set to write the Ethernet TX FIFO
MAC_TX_EOP : out std_logic; -- Marks the end of a transmit packet to the Ethernet TX FIFO
-- Non-volatile Data
NV_DATA : out std_logic_vector(63 downto 0); -- NV Data from Multicast Address Words
MAC_ADDRESS : out std_logic_vector(47 downto 0); -- MAC Address from EPROM
BOARD_TYPE : in std_logic_vector(7 downto 0); -- x"00" for APS2 and x"01" for TDM
-- User Logic Connections
USER_CLK : in std_logic; -- Clock for User side of FIFO interface
USER_RST : out std_logic; -- User Logic global reset, synchronous to USER_CLK
USER_VERSION : in std_logic_vector(31 downto 0); -- User Logic Firmware Version. Passed back in status packets
USER_STATUS : in std_logic_vector(31 downto 0); -- User Status Word. Passed back in status packets
USER_DIF : out std_logic_vector(31 downto 0); -- User Data Input FIFO output
USER_DIF_RD : in std_logic; -- User Data Onput FIFO Read Enable
USER_CIF_EMPTY : out std_logic; -- Low when there is data available
USER_CIF_RD : in std_logic; -- Command Input FIFO Read Enable
USER_CIF_RW : out std_logic; -- High for read, low for write
USER_CIF_MODE : out std_logic_vector(7 downto 0); -- MODE field from current User I/O command
USER_CIF_CNT : out std_logic_vector(15 downto 0); -- CNT field from current User I/O command
USER_CIF_ADDR : out std_logic_vector(31 downto 0); -- Address for the current command
USER_DOF : in std_logic_vector(31 downto 0); -- User Data Onput FIFO input
USER_DOF_WR : in std_logic; -- User Data Onput FIFO Write Enable
USER_COF_STAT : in std_logic_vector(7 downto 0); -- STAT value to return for current User I/O command
USER_COF_CNT : in std_logic_vector(15 downto 0); -- Number of words written to DOF for current User I/O command
USER_COF_AFULL : out std_logic; -- User Control Output FIFO Almost Full
USER_COF_WR : in std_logic; -- User Control Onput FIFO Write Enable
-- Config CPLD Data Bus for reading status when STAT_OE is asserted
CFG_CLK : in STD_LOGIC; -- 100 MHZ clock from the Config CPLD
CFGD : inout std_logic_vector(15 downto 0); -- Config Data bus from CPLD
FPGA_CMDL : out STD_LOGIC; -- Command strobe from FPGA
FPGA_RDYL : out STD_LOGIC; -- Ready Strobe from FPGA
CFG_RDY : in STD_LOGIC; -- Ready to complete current transfer
CFG_ERR : in STD_LOGIC; -- Error during current command
CFG_ACT : in STD_LOGIC; -- Current transaction is complete
STAT_OEL : out std_logic; -- Enable CPLD to drive status onto CFGD
-- Status to top level
GOOD_TOGGLE : out std_logic;
BAD_TOGGLE : out std_logic
);
end component;
end CPLD_bridge_pkg;
package body cpld_bridge_pkg is
function byte_swap(word_in : std_logic_vector) return std_logic_vector is
variable word_out : std_logic_vector(word_in'range);
variable num_bytes : natural := word_in'length/8;
begin
for ct in 0 to num_bytes-1 loop
word_out(8*(ct+1)-1 downto 8*ct) := word_in(8*(num_bytes-ct)-1 downto 8*(num_bytes-ct-1));
end loop;
return word_out;
end function byte_swap;
end package body;
| mpl-2.0 | b47b4937b20c15985f9b33c9cd3b1022 | 0.627158 | 3.448413 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/async_fifo_fg.vhd | 2 | 122,643 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
--use proc_common_v4_0.coregen_comp_defs.all;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising wr clock edge to issue assertion
Wait until Wr_clk = '1';
wait until Wr_clk = '0';
Wait until Wr_clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Almost_full <= '0' ; -- : out std_logic;
Almost_empty <= '0' ; -- : out std_logic;
Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| apache-2.0 | 67dbfec60be8de0dc47435e5d4008c6a | 0.399256 | 3.943251 | false | false | false | false |
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`protect end_protected
| apache-2.0 | ddc2ea460c78e3f63e0344f53aeb2817 | 0.930821 | 1.872843 | false | false | false | false |
rhexsel/xinu-cMIPS | xinu/zSrc/memory.vhd | 1 | 11,907 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable loaded into ROM at CPU reset, wd-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
use work.p_memory.all;
entity simul_ROM is
generic (LOAD_FILE_NAME : string := "prog.bin");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
end entity simul_ROM;
architecture behavioral of simul_ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := (NUM_MAX_W_STS - ROM_WAIT_STATES);
constant WAIT_FOR : reg10 := std_logic_vector(to_signed(WAIT_COUNT, 10));
signal waiting, do_wait : std_logic;
begin -- behavioral
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
U_ROM: process (rst, sel, strobe, addr)
subtype t_address is unsigned((INST_ADDRS_BITS - 1) downto 0);
variable u_addr : t_address;
subtype word is std_logic_vector(data'length - 1 downto 0);
type storage_array is
array( natural range 0 to (INST_MEM_SZ - 1) ) of word;
variable storage : storage_array;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable instr: integer; -- := to_integer(unsigned(NULL_INSTRUCTION));
variable s_instr : signed(31 downto 0);
begin
if rst = '0' then -- reset, read binary executable
index := 0; -- indexed by word
for i in 0 to (INST_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, instr);
s_instr := to_signed(instr, 32);
-- assert false report "romINIT["& natural'image(index*4) &"]= " &
-- SLV32HEX(std_logic_vector(s_instr)); -- DEBUG
storage(index) := std_logic_vector(s_instr);
index := index + 1;
end if;
end loop; -- i
else -- normal operation
u_addr := unsigned(addr((2+(INST_ADDRS_BITS-1)) downto 2)); -- >>2 = /4
index := to_integer(u_addr); -- indexed by word, not by byte
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "romRDindex out of bounds: " & SLV32HEX(addr) & " = " &
natural'image(index) severity failure;
if sel = '0' and rising_edge(strobe) then
latched := index;
end if;
if sel = '0' then
data <= storage(latched);
-- assert false -- DEBUG
-- report "romRD["& natural'image(index) &"]="& SLV32HEX(storage(index));
else
data <= (others => 'X');
end if;
end if;
end process;
end behavioral;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
use work.p_memory.all;
entity simul_RAM is
generic (LOAD_FILE_NAME : string := "data.bin";
DUMP_FILE_NAME : string := "dump.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic;
strobe : in std_logic;
addr : in reg32;
data_inp : in reg32;
data_out : out reg32;
byte_sel : in reg4;
dump_ram : in std_logic); -- dump RAM contents
constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
end entity simul_RAM;
architecture behavioral of simul_RAM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
signal wait_counter, ram_current : integer;
subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
subtype word is std_logic_vector(7 downto 0);
type storage_array is
array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
signal storage : storage_array;
signal enable, waiting, do_wait : std_logic;
begin -- behavioral
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel); -- and not(waiting);
accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
variable u_addr : t_address;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable datum: integer;
variable s_datum: signed(31 downto 0);
file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
variable d : reg32 := (others => 'X');
variable val, i : integer;
begin
if rst = '0' then -- reset, read-in binary initialized data
index := 0; -- byte indexed
for i in 0 to (DATA_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, datum);
s_datum := to_signed(datum, 32);
-- assert false report "ramINIT["& natural'image(index*4)&"]= " &
-- SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
index := index + 4;
end if;
end loop;
data_out <= (others=>'X');
else -- (rst = '1'), normal operation
-- to simplify (and accelerate) internal address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address that is larger the RAM capacity. Otherwise, the
-- base must be subtracted from the address on every reference,
-- which means having an adder in the critical path. Bad idea.
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
if sel = '0' and wr = '0' and rising_edge(strobe) then
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramWR index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- SW
storage(index+3) <= data_inp(31 downto 24);
storage(index+2) <= data_inp(23 downto 16);
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"1100" | b"0011" => -- SH
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
storage(index+0) <= data_inp(7 downto 0);
when others => null;
end case;
-- assert false report "ramWR["& natural'image(index) &"] "
-- & SLV32HEX(data) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
end if; -- is write?
if sel = '0' and wr = '1' then
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramRD index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- LW
d(31 downto 24) := storage(index+3);
d(23 downto 16) := storage(index+2);
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"1100" => -- LH top-half
d(31 downto 24) := storage(index+1);
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"0011" => -- LH bottom-half
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"0001" => -- LB top byte
d(31 downto 8) := (others => 'X');
d(7 downto 0) := storage(index+0);
when b"0010" => -- LB mid-top byte
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+0);
d(7 downto 0) := (others => 'X');
when b"0100" => -- LB mid-bot byte
d(31 downto 24) := (others => 'X');
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"1000" => -- LB bottom byte
d(31 downto 24) := storage(index+0);
d(23 downto 0) := (others => 'X');
when others => d := (others => 'X');
end case;
-- assert false report "ramRD["& natural'image(index) &"] "
-- & SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
elsif rising_edge(dump_ram) then
i := 0;
while i < DATA_MEM_SZ-4 loop
d(31 downto 24) := storage(i+3);
d(23 downto 16) := storage(i+2);
d(15 downto 8) := storage(i+1);
d(7 downto 0) := storage(i+0);
write( dump_file, to_integer(signed(d)) );
i := i+4;
end loop; -- i
else
d := (others=>'X');
end if; -- is read?
data_out <= d;
end if; -- is reset?
end process accessRAM; -- ---------------------------------------------
end behavioral;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 7582c5a45ed7c2f01638aa9ff34092e3 | 0.515075 | 3.770424 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/14-MESA-IA/asap-alap-random/mesaia_asap.vhd | 1 | 8,428 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:53:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 3);
output1, output2, output3, output4: OUT unsigned(0 TO 4));
END mesaia_asap_entity;
ARCHITECTURE mesaia_asap_description OF mesaia_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register22: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register23: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register24: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register25: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register26: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register27: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register28: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register29: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register30: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register31: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register32: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register33: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register34: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register35: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register36: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register37: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register38: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register39: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register40: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register41: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register42: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register43: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register44: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register45: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register46: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register47: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register48: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 + 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
register25 := input25 * 25;
register26 := input26 * 26;
register27 := input27 * 27;
register28 := input28 * 28;
register29 := input29 + 29;
register30 := input30 * 30;
register31 := input31 * 31;
register32 := input32 + 32;
register33 := input33 * 33;
register34 := input34 * 34;
register35 := input35 * 35;
register36 := input36 + 36;
register37 := input37 * 37;
register38 := input38 * 38;
register39 := input39 + 39;
register40 := input40 * 40;
register41 := input41 * 41;
register42 := input42 * 42;
register43 := input43 + 43;
register44 := input44 * 44;
register45 := input45 + 45;
register46 := input46 + 46;
register47 := input47 * 47;
register48 := input48 + 48;
WHEN "00000010" =>
register1 := register24 + register1;
register2 := register2 + register32;
register3 := register3 + register39;
register5 := register38 + register5;
register6 := register10 + register6;
register7 := register40 + register7;
register9 := register9 + register48;
register10 := register22 + register11;
register11 := register12 + register45;
register12 := register14 + register36;
register14 := register27 + register15;
register15 := register17 + register43;
register17 := register28 + register18;
register18 := register19 + register23;
register19 := register34 + register29;
register22 := register44 + register46;
WHEN "00000011" =>
register1 := register25 + register1;
register2 := register33 + register2;
register3 := register4 + register3;
register4 := register37 + register5;
register5 := register30 + register6;
register6 := register41 + register7;
register7 := register8 + register9;
register8 := register21 + register10;
register9 := register31 + register11;
register10 := register13 + register12;
register11 := register26 + register14;
register12 := register16 + register15;
register13 := register42 + register17;
register14 := register20 + register18;
register15 := register35 + register19;
register16 := register47 + register22;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register6 := ((NOT register6) + 1) XOR register6;
register7 := ((NOT register7) + 1) XOR register7;
register8 := ((NOT register8) + 1) XOR register8;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000101" =>
register1 := register6 - register1;
register4 := register16 - register4;
register6 := register7 - register12;
register7 := register13 - register14;
WHEN "00000110" =>
register1 := register1 * 74;
register4 := register4 * 76;
register6 := register6 * 78;
register7 := register7 * 80;
WHEN "00000111" =>
register1 := register15 + register1;
register3 := register3 + register4;
register4 := register11 + register6;
register6 := register8 + register7;
WHEN "00001000" =>
output1 <= register1(0 TO 1) & register9(0 TO 2);
output2 <= register3(0 TO 1) & register5(0 TO 2);
output3 <= register4(0 TO 1) & register2(0 TO 2);
output4 <= register6(0 TO 1) & register10(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_asap_description; | gpl-3.0 | 9318906acfd72ad0d4d71916ddc931cd | 0.671927 | 3.287051 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_nsga2.vhd | 1 | 2,996 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:45:24)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_nsga2_entity;
ARCHITECTURE mpegmv_nsga2_description OF mpegmv_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
register3 := register3 + 7;
register2 := register2 + 9;
register4 := input4 * 10;
register5 := input5 * 11;
WHEN "00000100" =>
register4 := register4 + 13;
register6 := input6 * 14;
register1 := register5 + register1;
register5 := input7 * 15;
register7 := input8 * 16;
WHEN "00000101" =>
register1 := register7 + register1;
register7 := input9 * 17;
WHEN "00000110" =>
output1 <= register7 + register3;
register3 := input10 * 19;
register4 := register6 + register4;
register2 := register5 + register2;
register1 := ((NOT register1) + 1) XOR register1;
register5 := input11 * 22;
WHEN "00000111" =>
register4 := register5 + register4;
register5 := input12 * 23;
WHEN "00001000" =>
output2 <= register1(0 TO 15) & register4(0 TO 15);
register1 := input13 * 25;
register2 := register5 + register2;
WHEN "00001001" =>
register2 := ((NOT register2) + 1) XOR register2;
register4 := input14 * 28;
register1 := register1 + 30;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register3 + register1;
WHEN "00001100" =>
output3 <= register2(0 TO 15) & register1(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_nsga2_description; | gpl-3.0 | fb17d68bb1e2175c17907d32d32c39ff | 0.678238 | 3.277899 | false | false | false | false |
rhexsel/xinu-cMIPS | xinu/zSrc/rom.vhd | 1 | 13,152 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable defined as constant, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity fpga_ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
end entity fpga_ROM;
architecture rtl of fpga_ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component single_port_rom is
generic (N_WORDS : integer);
port (address : in rom_address;
clken : in std_logic;
clock : in std_logic;
q : out std_logic_vector);
end component single_port_rom;
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1) downto 2)));
U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
port map (index, clken, strobe, instrn);
U_ROM_ACCESS: process (strobe,instrn,sel)
begin
if sel = '0' then
data <= instrn;
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "rom index out of bounds: " & natural'image(index)
severity failure;
-- assert false -- DEBUG
-- report "romRD["& natural'image(index) &"]="& SLV32HEX(data);
else
data <= (others => 'X');
end if;
end process U_ROM_ACCESS;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Adapted from Altera's design for a ROM that may be synthesized
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity single_port_rom is
generic (N_WORDS : integer := 32);
port (address : in natural range 0 to (N_WORDS - 1);
clken : in std_logic;
clock : in std_logic;
q : out reg32);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to (N_WORDS-1)) of word_t;
-- assemble.sh -v mac_lcd.s |\
-- sed -e '1,6d' -e '/^$/d' -e '/^ /!d' -e 's:\t: :g' \
-- -e 's#\(^ *[a-f0-9]*:\) *\(........\) *\(.*\)$#x"\2", -- \1 \3#' \
-- -e '$s:,: :'
constant test_prog : memory_t := (
x"00000000", -- 0: nop
x"3c0f0f00", -- 4: lui $15,0xf00
x"35ef0120", -- 8: ori $15,$15,0x120
x"24100001", -- c: li $16,1
x"adf00000", -- 10: sw $16,0($15)
x"3c040009", -- 14: lui $4,0x9
x"34848968", -- 18: ori $4,$4,0x8968
x"0c0000b7", -- 1c: jal 2dc <delay>
x"00000000", -- 20: nop
x"3c1a0f00", -- 24: lui $26,0xf00
x"375a0160", -- 28: ori $26,$26,0x160
x"24130030", -- 2c: li $19,48
x"af530000", -- 30: sw $19,0($26)
x"24040177", -- 34: li $4,375
x"0c0000b7", -- 38: jal 2dc <delay>
x"00000000", -- 3c: nop
x"24130030", -- 40: li $19,48
x"af530000", -- 44: sw $19,0($26)
x"24040177", -- 48: li $4,375
x"0c0000b7", -- 4c: jal 2dc <delay>
x"00000000", -- 50: nop
x"24130039", -- 54: li $19,57
x"af530000", -- 58: sw $19,0($26)
x"24040177", -- 5c: li $4,375
x"0c0000b7", -- 60: jal 2dc <delay>
x"00000000", -- 64: nop
x"24130014", -- 68: li $19,20
x"af530000", -- 6c: sw $19,0($26)
x"24040177", -- 70: li $4,375
x"0c0000b7", -- 74: jal 2dc <delay>
x"00000000", -- 78: nop
x"24130070", -- 7c: li $19,112
x"af530000", -- 80: sw $19,0($26)
x"24040177", -- 84: li $4,375
x"0c0000b7", -- 88: jal 2dc <delay>
x"00000000", -- 8c: nop
x"24130056", -- 90: li $19,86
x"af530000", -- 94: sw $19,0($26)
x"24040177", -- 98: li $4,375
x"0c0000b7", -- 9c: jal 2dc <delay>
x"00000000", -- a0: nop
x"2413006d", -- a4: li $19,109
x"af530000", -- a8: sw $19,0($26)
x"24040177", -- ac: li $4,375
x"0c0000b7", -- b0: jal 2dc <delay>
x"00000000", -- b4: nop
x"24100002", -- b8: li $16,2
x"adf00000", -- bc: sw $16,0($15)
x"3c0400be", -- c0: lui $4,0xbe
x"3484bc20", -- c4: ori $4,$4,0xbc20
x"0c0000b7", -- c8: jal 2dc <delay>
x"00000000", -- cc: nop
x"3c040026", -- d0: lui $4,0x26
x"348425a0", -- d4: ori $4,$4,0x25a0
x"0c0000b7", -- d8: jal 2dc <delay>
x"00000000", -- dc: nop
x"24100003", -- e0: li $16,3
x"adf00000", -- e4: sw $16,0($15)
x"3c0400be", -- e8: lui $4,0xbe
x"3484bc20", -- ec: ori $4,$4,0xbc20
x"0c0000b7", -- f0: jal 2dc <delay>
x"00000000", -- f4: nop
x"3c1a0f00", -- f8: lui $26,0xf00
x"375a0160", -- fc: ori $26,$26,0x160
x"2413000f", -- 100: li $19,15
x"af530000", -- 104: sw $19,0($26)
x"24040177", -- 108: li $4,375
x"0c0000b7", -- 10c: jal 2dc <delay>
x"00000000", -- 110: nop
x"24130006", -- 114: li $19,6
x"af530000", -- 118: sw $19,0($26)
x"24040177", -- 11c: li $4,375
x"0c0000b7", -- 120: jal 2dc <delay>
x"00000000", -- 124: nop
x"24100004", -- 128: li $16,4
x"adf00000", -- 12c: sw $16,0($15)
x"3c0400be", -- 130: lui $4,0xbe
x"3484bc20", -- 134: ori $4,$4,0xbc20
x"0c0000b7", -- 138: jal 2dc <delay>
x"00000000", -- 13c: nop
x"24130001", -- 140: li $19,1
x"af530000", -- 144: sw $19,0($26)
x"24040177", -- 148: li $4,375
x"0c0000b7", -- 14c: jal 2dc <delay>
x"00000000", -- 150: nop
x"24130080", -- 154: li $19,128
x"af530000", -- 158: sw $19,0($26)
x"24040177", -- 15c: li $4,375
x"0c0000b7", -- 160: jal 2dc <delay>
x"00000000", -- 164: nop
x"24100005", -- 168: li $16,5
x"adf00000", -- 16c: sw $16,0($15)
x"3c0400be", -- 170: lui $4,0xbe
x"3484bc20", -- 174: ori $4,$4,0xbc20
x"0c0000b7", -- 178: jal 2dc <delay>
x"00000000", -- 17c: nop
x"8f530000", -- 180: lw $19,0($26)
x"00000000", -- 184: nop
x"32730080", -- 188: andi $19,$19,0x80
x"1660fffc", -- 18c: bnez $19,180 <check>
x"00000000", -- 190: nop
x"02608021", -- 194: move $16,$19
x"adf00000", -- 198: sw $16,0($15)
x"3c0400be", -- 19c: lui $4,0xbe
x"3484bc20", -- 1a0: ori $4,$4,0xbc20
x"0c0000b7", -- 1a4: jal 2dc <delay>
x"00000000", -- 1a8: nop
x"24130080", -- 1ac: li $19,128
x"af530000", -- 1b0: sw $19,0($26)
x"24040177", -- 1b4: li $4,375
x"0c0000b7", -- 1b8: jal 2dc <delay>
x"00000000", -- 1bc: nop
x"3c046c6c", -- 1c0: lui $4,0x6c6c
x"34846548", -- 1c4: ori $4,$4,0x6548
x"0c000097", -- 1c8: jal 25c <send>
x"00000000", -- 1cc: nop
x"3c046f77", -- 1d0: lui $4,0x6f77
x"3484206f", -- 1d4: ori $4,$4,0x206f
x"0c000097", -- 1d8: jal 25c <send>
x"00000000", -- 1dc: nop
x"3c042164", -- 1e0: lui $4,0x2164
x"34846c72", -- 1e4: ori $4,$4,0x6c72
x"0c000097", -- 1e8: jal 25c <send>
x"00000000", -- 1ec: nop
x"24100007", -- 1f0: li $16,7
x"adf00000", -- 1f4: sw $16,0($15)
x"3c0400be", -- 1f8: lui $4,0xbe
x"3484bc20", -- 1fc: ori $4,$4,0xbc20
x"0c0000b7", -- 200: jal 2dc <delay>
x"00000000", -- 204: nop
x"241300c0", -- 208: li $19,192
x"af530000", -- 20c: sw $19,0($26)
x"24040177", -- 210: li $4,375
x"0c0000b7", -- 214: jal 2dc <delay>
x"00000000", -- 218: nop
x"3c046961", -- 21c: lui $4,0x6961
x"34847320", -- 220: ori $4,$4,0x7320
x"0c000097", -- 224: jal 25c <send>
x"00000000", -- 228: nop
x"3c044d63", -- 22c: lui $4,0x4d63
x"34842064", -- 230: ori $4,$4,0x2064
x"0c000097", -- 234: jal 25c <send>
x"00000000", -- 238: nop
x"3c042053", -- 23c: lui $4,0x2053
x"34845049", -- 240: ori $4,$4,0x5049
x"0c000097", -- 244: jal 25c <send>
x"00000000", -- 248: nop
x"24100008", -- 24c: li $16,8
x"adf00000", -- 250: sw $16,0($15)
x"08000095", -- 254: j 254 <end>
x"00000000", -- 258: nop
x"3c1a0f00", -- 25c: lui $26,0xf00
x"375a0160", -- 260: ori $26,$26,0x160
x"af440004", -- 264: sw $4,4($26)
x"00042202", -- 268: srl $4,$4,0x8
x"240500fa", -- 26c: li $5,250
x"24a5ffff", -- 270: addiu $5,$5,-1
x"00000000", -- 274: nop
x"14a0fffd", -- 278: bnez $5,270 <delay0>
x"00000000", -- 27c: nop
x"af440004", -- 280: sw $4,4($26)
x"00042202", -- 284: srl $4,$4,0x8
x"240500fa", -- 288: li $5,250
x"24a5ffff", -- 28c: addiu $5,$5,-1
x"00000000", -- 290: nop
x"14a0fffd", -- 294: bnez $5,28c <delay1>
x"00000000", -- 298: nop
x"af440004", -- 29c: sw $4,4($26)
x"00042202", -- 2a0: srl $4,$4,0x8
x"240500fa", -- 2a4: li $5,250
x"24a5ffff", -- 2a8: addiu $5,$5,-1
x"00000000", -- 2ac: nop
x"14a0fffd", -- 2b0: bnez $5,2a8 <delay2>
x"00000000", -- 2b4: nop
x"af440004", -- 2b8: sw $4,4($26)
x"00000000", -- 2bc: nop
x"240500fa", -- 2c0: li $5,250
x"24a5ffff", -- 2c4: addiu $5,$5,-1
x"00000000", -- 2c8: nop
x"14a0fffd", -- 2cc: bnez $5,2c4 <delay3>
x"00000000", -- 2d0: nop
x"03e00008", -- 2d4: jr $31
x"00000000", -- 2d8: nop
x"2484ffff", -- 2dc: addiu $4,$4,-1
x"00000000", -- 2e0: nop
x"1480fffd", -- 2e4: bnez $4,2dc <delay>
x"00000000", -- 2e8: nop
x"03e00008", -- 2ec: jr $31
x"00000000", -- 2f0: nop
x"00000000", -- 2f4: nop
x"00000000", -- 2f8: nop
x"00000000", -- 2fc: nop
x"00000000", -- 300: nop
x"00000000", -- 304: nop
x"00000000", -- 308: nop
x"00000000", -- 30c: nop
x"00000000", -- 310: nop
x"00000000", -- 314: nop
x"00000000", -- 318: nop
x"00000000", -- 31c: nop
x"00000000", -- 320: nop
x"00000000", -- 324: nop
x"00000000", -- 328: nop
x"00000000", -- 32c: nop
x"00000000", -- 330: nop
x"00000000", -- 334: nop
x"00000000", -- 338: nop
x"00000000", -- 33c: nop
x"00000000", -- 340: nop
x"00000000", -- 344: nop
x"00000000", -- 348: nop
x"00000000", -- 34c: nop
x"00000000", -- 350: nop
x"00000000", -- 354: nop
x"00000000", -- 358: nop
x"00000000", -- 35c: nop
x"00000000", -- 360: nop
x"00000000", -- 364: nop
x"00000000", -- 368: nop
x"00000000", -- 36c: nop
x"00000000", -- 370: nop
x"00000000", -- 374: nop
x"00000000", -- 378: nop
x"00000000", -- 37c: nop
x"00000000", -- 380: nop
x"00000000", -- 384: nop
x"00000000", -- 388: nop
x"00000000", -- 38c: nop
x"00000000", -- 390: nop
x"00000000", -- 394: nop
x"00000000", -- 398: nop
x"00000000", -- 39c: nop
x"00000000", -- 3a0: nop
x"00000000", -- 3a4: nop
x"00000000", -- 3a8: nop
x"00000000", -- 3ac: nop
x"00000000", -- 3b0: nop
x"00000000", -- 3b4: nop
x"00000000", -- 3b8: nop
x"00000000", -- 3bc: nop
x"00000000", -- 3c0: nop
x"00000000", -- 3c4: nop
x"00000000", -- 3c8: nop
x"00000000", -- 3cc: nop
x"00000000", -- 3d0: nop
x"00000000", -- 3d4: nop
x"00000000", -- 3d8: nop
x"00000000", -- 3dc: nop
x"00000000", -- 3e0: nop
x"00000000", -- 3e4: nop
x"00000000", -- 3e8: nop
x"00000000", -- 3ec: nop
x"00000000", -- 3f0: nop
x"00000000", -- 3f4: nop
x"00000000", -- 3f8: nop
x"00000000" -- 3fc: nop
);
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
variable i_addr : integer;
begin
for addr_pos in test_prog'range loop
tmp(addr_pos) := test_prog(addr_pos);
-- i_addr := addr_pos;
end loop;
for addr_pos in test_prog'high to (N_WORDS - 1) loop
tmp(addr_pos) := x"00000000"; -- nop
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (ROM.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clock,clken)
begin
if(clken = '1' and rising_edge(clock)) then
q <= rom(address);
end if;
end process;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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`protect end_protected
| apache-2.0 | 81c8e998b5f1418c1cd8f61e8db12470 | 0.926518 | 1.905234 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/temp_divider.vhd | 1 | 2,022 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_divider is
generic
(
width : integer := 4;
const : integer := 16
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_divider;
architecture behavior of c_divider is
function twocomp_bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if (i < input'HIGH) then
if (input(input'HIGH) = '0') then
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
else
if input(i) = '0' then
ret_val := 2 ** i + ret_val;
end if;
end if;
end if;
end loop;
if (input(input'HIGH) = '1') then
ret_val := ret_val + 1;
ret_val := 0 - ret_val;
end if; return ret_val;
end twocomp_bits_to_int;
function twocomp_int_to_bin (INPUT, wid : integer)return STD_LOGIC_VECTOR is
variable TEMP_A, TEMP_B : integer := 0;
variable OUTPUT : STD_LOGIC_VECTOR((wid - 1) downto 0);
variable comp_input, abs_val : integer;
begin
if (input < 0) then
abs_val := 0 - input;
comp_input := (2 ** (wid - 1)) - abs_val;
assert(comp_input >= 0);
else
comp_input := input;
end if;
TEMP_A := comp_input;
for I in (wid - 2) downto 0 loop
TEMP_B := TEMP_A/(2 ** I);
TEMP_A := TEMP_A rem (2 ** I);
if (TEMP_B = 1) then
OUTPUT(I) := '1';
else
OUTPUT(I) := '0';
end if;
end loop;
if (input < 0) then
OUTPUT(wid - 1) := '1';
else
OUTPUT(wid - 1) := '0';
end if; return OUTPUT;
end twocomp_int_to_bin;
begin
P0 : process (input1, input2)
variable l_val, r_val, value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
l_val := twocomp_bits_to_int(input1);
r_val := twocomp_bits_to_int(input2);
if not (r_val = 0) then
value := l_val / r_val;
result := twocomp_int_to_bin(value, width);
output <= result;
end if;
end process P0;
end behavior; | mit | 0cce9db73509dda5993f55195b6bf53f | 0.598417 | 2.639687 | false | false | false | false |
BBN-Q/APS2-Comms | src/udp_responder.vhd | 1 | 7,570 | -- Respond to APS2 UDP packets on port x"bb4e"
-- Implements an eumerate response; tcp port reset
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.udp_responder_pkg.all;
entity UDP_responder is
port (
clk : in std_logic;
rst : in std_logic;
udp_rx_tdata : in std_logic_vector(7 downto 0);
udp_rx_tvalid : in std_logic;
udp_rx_tlast : in std_logic;
udp_src_port: in std_logic_vector(15 downto 0);
src_ip_addr : in std_logic_vector(31 downto 0);
dest_ip_addr : out std_logic_vector(31 downto 0);
udp_tx_tdata : out std_logic_vector(7 downto 0);
udp_tx_tvalid : out std_logic;
udp_tx_tlast : out std_logic;
udp_tx_tready : in std_logic;
udp_tx_ack : in std_logic;
udp_tx_nack : in std_logic;
rst_tcp : out std_logic
);
end entity;
architecture arch of UDP_responder is
signal packet_in_error : std_logic := '0';
signal packet_in_tvalid : std_logic := '0';
signal packet_out_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal packet_out_tvalid, packet_out_tready, packet_out_tlast : std_logic := '0';
signal overflow, good_frame, bad_frame : std_logic;
signal is_bbn_packet : boolean := false;
signal cur_cmd_vld : boolean := false;
signal cur_cmd : std_logic_vector(7 downto 0) := (others => '0');
type packet_processing_state_t is (IDLE, LATCH_COMMAND, DRAIN_PACKET);
signal packet_processing_state : packet_processing_state_t;
signal start_enumerate_resp, start_tcp_rst : std_logic := '0';
type byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
-- "I am an APS2"
constant ENUMERATE_RESPONSE : byte_array(0 to 11) :=
(x"49", x"20", x"61", x"6d", x"20", x"61", x"6e", x"20", x"41", x"50", x"53", x"32");
type enumerate_response_state_t is (IDLE, SEND_RESPONSE, WAIT_FOR_ACK, ARP_DELAY);
signal enumerate_response_state : enumerate_response_state_t;
signal enumerate_response_ct : integer range 0 to ENUMERATE_RESPONSE'length;
begin
--Convert from ComBlock error indicator (last high but valid low)
--and more conventional AXIS style with a tuser signal
packet_in_error <= udp_rx_tlast and not udp_rx_tvalid;
packet_in_tvalid <= udp_rx_tvalid or udp_rx_tlast;
--Store the packet in a FIFO to make sure we have a valid UDP packet
packet_fifo : axis_frame_fifo
generic map (
ADDR_WIDTH => 12,
DATA_WIDTH => 8,
DROP_WHEN_FULL => true
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => udp_rx_tdata,
input_axis_tvalid => packet_in_tvalid,
input_axis_tready => open,
input_axis_tlast => udp_rx_tlast,
input_axis_tuser => packet_in_error,
output_axis_tdata => packet_out_tdata,
output_axis_tvalid => packet_out_tvalid,
output_axis_tready => packet_out_tready,
output_axis_tlast => packet_out_tlast,
overflow => overflow,
bad_frame => bad_frame,
good_frame => good_frame
);
udp_src_port_check : process(clk)
variable udp_src_port_l : std_logic_vector(15 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
udp_src_port_l := (others => '0');
is_bbn_packet <= false;
else
is_bbn_packet <= (udp_src_port_l = x"bb4f");
if udp_rx_tlast = '1' then
udp_src_port_l := udp_src_port;
end if;
end if;
end if;
end process;
--Process packet and register command
packet_processing : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
packet_processing_state <= IDLE;
cur_cmd_vld <= false;
cur_cmd <= (others => '0');
else
cur_cmd_vld <= false;
case( packet_processing_state ) is
when IDLE =>
--Wait for a valid packet
if packet_out_tvalid = '1' then
if is_bbn_packet then
packet_processing_state <= LATCH_COMMAND;
else
packet_processing_state <= DRAIN_PACKET;
end if;
end if;
when LATCH_COMMAND =>
cur_cmd <= packet_out_tdata;
dest_ip_addr <= src_ip_addr;
packet_processing_state <= DRAIN_PACKET;
cur_cmd_vld <= true;
when DRAIN_PACKET =>
if packet_out_tlast = '1' then
packet_processing_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
packet_out_tready <= '1' when packet_processing_state = DRAIN_PACKET else '0';
--Process commands
command_processing : process(clk)
type cmd_state_t is (IDLE, DECODE_CMD);
variable cmd_state : cmd_state_t;
begin
if rising_edge(clk) then
if rst = '1' then
cmd_state := IDLE;
start_enumerate_resp <= '0';
start_tcp_rst <= '0';
else
case( cmd_state ) is
when IDLE =>
start_enumerate_resp <= '0';
start_tcp_rst <= '0';
if cur_cmd_vld then
cmd_state := DECODE_CMD;
end if;
when DECODE_CMD =>
cmd_state := IDLE;
case( cur_cmd ) is
when x"01" =>
start_enumerate_resp <= '1';
when x"02" =>
start_tcp_rst <= '1';
when others =>
null;
end case;
end case;
end if;
end if;
end process;
--Send enumerate response when start flag goes high
--If we get back a nack presumably the destination is not in the ARP table
--so wait 10ms from the ARP query-response and try again
enumerate_resp_pro : process(clk)
constant NUM_TRIES : natural := 3;
variable try_ct : natural range 0 to NUM_TRIES-1;
constant ARP_DELAY_CLOCKS : natural := 1_250_000
--pragma synthesis_off
/1000
--pragma synthesis_on
; --10ms at 125 MHz - shorten to 10 us for simulation
variable arp_delay_ct : unsigned(integer(ceil(log2(real(ARP_DELAY_CLOCKS)))) downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
enumerate_response_ct <= 0;
try_ct := 0;
arp_delay_ct := to_unsigned(ARP_DELAY_CLOCKS, arp_delay_ct'length);
else
enumerate_response_ct <= 0;
case( enumerate_response_state ) is
when IDLE =>
try_ct := 0;
if start_enumerate_resp = '1' then
enumerate_response_state <= SEND_RESPONSE;
end if;
when SEND_RESPONSE =>
if udp_tx_tready = '1' then
if enumerate_response_ct = ENUMERATE_RESPONSE'high then
enumerate_response_state <= WAIT_FOR_ACK;
else
enumerate_response_ct <= enumerate_response_ct + 1;
end if;
end if;
when WAIT_FOR_ACK =>
arp_delay_ct := to_unsigned(ARP_DELAY_CLOCKS, arp_delay_ct'length);
if udp_tx_ack = '1' then
enumerate_response_state <= IDLE;
elsif udp_tx_nack = '1' then
if try_ct = NUM_TRIES-1 then
enumerate_response_state <= IDLE;
else
try_ct := try_ct + 1;
enumerate_response_state <= ARP_DELAY;
end if;
end if;
when ARP_DELAY =>
if arp_delay_ct(arp_delay_ct'high) = '1' then
enumerate_response_state <= SEND_RESPONSE;
else
arp_delay_ct := arp_delay_ct - 1;
end if;
end case;
end if;
end if;
end process;
udp_tx_tdata <= ENUMERATE_RESPONSE(enumerate_response_ct);
udp_tx_tvalid <= '1' when enumerate_response_state = SEND_RESPONSE else '0';
udp_tx_tlast <= '1' when (enumerate_response_state = SEND_RESPONSE) and
(enumerate_response_ct = ENUMERATE_RESPONSE'high) else '0';
--Hold tcp reset high for a couple clocks when start flag goes high
tcp_reset_pro : process(clk)
variable reset_line : std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
reset_line := (others => '1');
else
if start_tcp_rst = '1' then
reset_line := (others => '1');
else
reset_line := reset_line(reset_line'high-1 downto 0) & '0';
end if;
end if;
rst_tcp <= reset_line(reset_line'high);
end if;
end process;
end architecture;
| mpl-2.0 | 11616f69df785f58f72cb062046a8171 | 0.65033 | 2.903721 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/asap-alap-random/mesahb_asap.vhd | 1 | 1,933 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:14:48)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_asap_entity;
ARCHITECTURE mesahb_asap_description OF mesahb_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
output1 <= input5 + 5;
WHEN "00000010" =>
register2 := register2 + 7;
register3 := register3 + 9;
register4 := register4 + 11;
WHEN "00000011" =>
register2 := register2 * 13;
register3 := ((NOT register3) + 1) XOR register3;
register4 := register4 * 17;
WHEN "00000100" =>
register2 := register2 + 19;
register1 := register1 * register3;
register3 := register4 + 21;
WHEN "00000101" =>
register2 := ((NOT register2) + 1) XOR register2;
WHEN "00000110" =>
register2 := register2 * 25;
WHEN "00000111" =>
register1 := register2 + register1;
WHEN "00001000" =>
output2 <= register1(0 TO 1) & register3(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_asap_description; | gpl-3.0 | 3bb28b98d6c5adabce1463d40f328df5 | 0.65701 | 3.029781 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_wsga.vhd | 1 | 3,673 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:58)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_wsga_entity;
ARCHITECTURE fir1_wsga_description OF fir1_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
WHEN "00000010" =>
register5 := input5 and input5;
register6 := input6 and input6;
register7 := input7 and input7;
register1 := register1 * register4;
register4 := input8 and input8;
register2 := register3 * register2;
WHEN "00000011" =>
register3 := register6 * register4;
register4 := input9 and input9;
register6 := input10 and input10;
register5 := register7 * register5;
register7 := input11 and input11;
WHEN "00000100" =>
register6 := register6 * register7;
register7 := input12 and input12;
WHEN "00000101" =>
register4 := register4 * register7;
register3 := register6 + register3;
WHEN "00000110" =>
register2 := register3 + register2;
register3 := input13 and input13;
register6 := input14 and input14;
register7 := input15 and input15;
register8 := input16 and input16;
WHEN "00000111" =>
register3 := register8 * register3;
register8 := input17 and input17;
register9 := input18 and input18;
register10 := input19 and input19;
register11 := input20 and input20;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := input21 and input21;
register6 := register10 * register6;
register9 := register11 * register9;
register7 := register8 * register7;
WHEN "00001001" =>
register5 := register5 + register9;
register8 := input22 and input22;
register6 := register7 + register6;
WHEN "00001010" =>
register1 := register6 + register1;
WHEN "00001011" =>
register1 := register1 + register4;
register2 := register2 * register8;
WHEN "00001100" =>
register1 := register5 + register1;
WHEN "00001101" =>
register1 := register1 + register2;
WHEN "00001110" =>
register1 := register3 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_wsga_description; | gpl-3.0 | 721dfe51d99459c6ecb1695ce9465960 | 0.679553 | 3.2447 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/asap-alap-random/ewf_asap.vhd | 1 | 2,840 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_asap_entity;
ARCHITECTURE ewf_asap_description OF ewf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register3 := register3 * 12;
output1 <= register6 + register4;
register2 := register2 * 15;
WHEN "00001001" =>
register3 := register1 + register3;
register2 := register2 + 17;
WHEN "00001010" =>
register1 := register1 + register3;
register4 := register5 + register3;
register5 := register6 + register2;
register6 := register2 + 19;
WHEN "00001011" =>
register1 := register1 * 21;
register4 := register4 + 23;
register5 := register5 + 25;
register6 := register6 * 27;
WHEN "00001100" =>
register1 := register1 + 29;
register7 := register4 * 31;
register8 := register5 * 33;
output2 <= register2 + register6;
WHEN "00001101" =>
output3 <= register3 + register1;
register1 := register7 + 37;
register2 := register8 + 39;
WHEN "00001110" =>
output4 <= register4 + register1;
output5 <= register5 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_asap_description; | gpl-3.0 | 5d5b441b27d2a85e9024c20e635aa58c | 0.655986 | 3.166109 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/exception.vhd | 2 | 7,500 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------------------
-- Interrupt/exception pipeline registers
-------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception IF-RF
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_IF_RF is
port(clk, rst, ld: in std_logic;
IF_excp_type: in exception_type;
RF_excp_type: out exception_type;
PC_abort: in boolean;
RF_PC_abort: out boolean;
IF_PC: in reg32;
RF_PC: out reg32);
end reg_excp_IF_RF;
architecture funcional of reg_excp_IF_RF is
begin
process(clk, rst, ld)
begin
if rising_edge(clk) then
if ld = '0' then
RF_excp_type <= IF_excp_type ;
RF_PC_abort <= PC_abort ;
RF_PC <= IF_PC ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception RF-EX
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_RF_EX is
port(clk, rst, ld: in std_logic;
RF_cop0_reg: in reg5;
EX_cop0_reg: out reg5;
RF_cop0_sel: in reg3;
EX_cop0_sel: out reg3;
RF_can_trap: in reg2;
EX_can_trap: out reg2;
RF_exception: in exception_type;
EX_exception: out exception_type;
RF_is_delayslot: in std_logic;
EX_is_delayslot: out std_logic;
RF_PC_abort: in boolean;
EX_PC_abort: out boolean;
RF_PC: in reg32;
EX_PC: out reg32;
RF_trap_taken: in boolean;
EX_trapped: out boolean);
end reg_excp_RF_EX;
architecture funcional of reg_excp_RF_EX is
begin
process(clk, rst, ld)
begin
if rst = '0' then
EX_can_trap <= b"00";
EX_is_delayslot <= '0';
EX_trapped <= FALSE;
elsif rising_edge(clk) then
if ld = '0' then
EX_cop0_reg <= RF_cop0_reg ;
EX_cop0_sel <= RF_cop0_sel ;
EX_can_trap <= RF_can_trap ;
EX_exception <= RF_exception ;
EX_is_delayslot <= RF_is_delayslot ;
EX_PC_abort <= RF_PC_abort ;
EX_PC <= RF_PC ;
EX_trapped <= RF_trap_taken ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception EX-MEM
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_EX_MM is
port(clk, rst, ld: in std_logic;
EX_cop0_reg: in reg5;
MM_cop0_reg: out reg5;
EX_cop0_sel: in reg3;
MM_cop0_sel: out reg3;
EX_PC: in reg32;
MM_PC: out reg32;
EX_v_addr: in reg32;
MM_v_addr: out reg32;
EX_nullify: in boolean;
MM_nullify: out boolean;
EX_addrError: in boolean;
MM_addrError: out boolean;
EX_addrErr_stage_mm: in boolean;
MM_addrErr_stage_mm: out boolean;
EX_is_delayslot: in std_logic;
MM_is_delayslot: out std_logic;
EX_trapped: in boolean;
MM_trapped: out boolean;
EX_ll_sc_abort: in boolean;
MM_ll_sc_abort: out boolean;
EX_tlb_exception: in boolean;
MM_tlb_exception: out boolean;
EX_tlb_stage_mm: in boolean;
MM_tlb_stage_mm: out boolean;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
MM_is_MFC0: out boolean;
EX_is_exception: in exception_type;
MM_is_exception: out exception_type);
end reg_excp_EX_MM;
architecture funcional of reg_excp_EX_MM is
begin
process(clk, rst, ld)
begin
if rst = '0' then
MM_trapped <= FALSE;
MM_nullify <= FALSE;
MM_addrError <= FALSE;
MM_trapped <= FALSE;
MM_tlb_exception <= FALSE;
MM_is_exception <= exNOP;
elsif rising_edge(clk) then
if ld = '0' then
MM_cop0_reg <= EX_cop0_reg ;
MM_cop0_sel <= EX_cop0_sel ;
MM_PC <= EX_PC ;
MM_v_addr <= EX_v_addr ;
MM_nullify <= EX_nullify ;
MM_addrError <= EX_addrError ;
MM_addrErr_stage_mm <= EX_addrErr_stage_mm;
MM_is_delayslot <= EX_is_delayslot;
MM_trapped <= EX_trapped ;
MM_ll_sc_abort <= EX_ll_sc_abort ;
MM_tlb_exception <= EX_tlb_exception;
MM_tlb_stage_MM <= EX_tlb_stage_MM;
MM_int_req <= EX_int_req ;
MM_is_SC <= EX_is_SC ;
MM_is_MFC0 <= EX_is_MFC0 ;
MM_is_exception <= EX_is_exception;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception MEM-WB
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_MM_WB is
port(clk, rst, ld: in std_logic;
MM_PC: in reg32;
WB_PC: out reg32;
MM_cop0_LLbit: in std_logic;
WB_cop0_LLbit: out std_logic;
MM_is_delayslot: in std_logic;
WB_is_delayslot: out std_logic;
MM_cop0_val: in reg32;
WB_cop0_val: out reg32);
end reg_excp_MM_WB;
architecture funcional of reg_excp_MM_WB is
begin
process(clk, rst, ld)
begin
if rst = '0' then
WB_cop0_LLbit <= '0';
elsif rising_edge(clk) then
if ld = '0' then
WB_PC <= MM_PC ;
WB_cop0_LLbit <= MM_cop0_LLbit ;
WB_is_delayslot <= MM_is_delayslot;
WB_cop0_val <= MM_cop0_val ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 3d88b0dc9127cca296188b4463eb2238 | 0.468933 | 3.595398 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/InstructionMemory.vhd | 1 | 807 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity InstructionMemory is
generic(
WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 10
);
Port(
instruction : out std_ulogic_vector(WIDTH-1 downto 0);
pc : in std_ulogic_vector(ADDRESS_WIDTH-1 downto 0);
clock : in std_ulogic
);
end InstructionMemory;
architecture Behavioral of InstructionMemory is
begin
BRAM_inst : entity work.BRAM(Behavioral)
generic map(MEM_ADDR_WIDTH => 10,
MEM_DATA_WIDTH => 16,
EDGE_TYPE => false,
MEM_NAME => "H:\hwprak\task_4\PWM1_short.hack")
port map(Clock => clock,
WriteEnable => '0',
Address => pc,
WriteData => "0000000000000000",
ReadData => instruction);
end Behavioral;
| agpl-3.0 | bdfaadfa29c5b5f8dde795388edf9619 | 0.61834 | 3.524017 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/b8comp2tohex_converter.vhd | 1 | 1,008 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity b8comp2tohex_converter is
port( in_string: IN std_logic_vector(7 downto 0);
out1: OUT std_logic_vector(3 downto 0);
out0: OUT std_logic_vector(3 downto 0));
end b8comp2tohex_converter;
architecture behavior of b8comp2tohex_converter is
signal module: std_logic_vector(7 downto 0);
signal temp: unsigned (7 downto 0);
begin
temp<=unsigned(in_string);
process (temp)
begin
if (temp(7) = '0') then
module<= std_logic_vector(temp);
else
module<=std_logic_vector((not(temp) + 1));
end if;
out1<= module(7 downto 4);
out0<= module(3 downto 0);
end process;
end behavior; | lgpl-3.0 | f0bf051262461cc740bd022463a62302 | 0.472222 | 3.98419 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/pc_bit.vhd | 1 | 15,425 | `protect begin_protected
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9680)
`protect data_block
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`protect end_protected
| apache-2.0 | e955d703f6b87f341c18724e269accf1 | 0.9353 | 1.881786 | false | false | false | false |
jdryg/tis100cpu | instruction_memory_tb.vhd | 1 | 1,413 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY instruction_memory_tb IS
END instruction_memory_tb;
ARCHITECTURE behavior OF instruction_memory_tb IS
constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\multiply.prg";
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT instruction_memory
GENERIC(filename : string := PROGRAM_FILENAME);
PORT(
I_addr : IN std_logic_vector(5 downto 0);
O_instr : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal I_addr : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal O_instr : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: instruction_memory
GENERIC MAP (filename => PROGRAM_FILENAME)
PORT MAP (
I_addr => I_addr,
O_instr => O_instr
);
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
I_addr <= "000000";
wait for 10 ns;
assert O_instr = X"80800005" report "Invalid instruction @ addr 0" severity error;
I_addr <= "000001";
wait for 10 ns;
assert O_instr = X"01100000" report "Invalid instruction @ addr 1" severity error;
I_addr <= "000100";
wait for 10ns;
assert O_instr = X"10000000" report "Invalid instruction @ addr 4" severity error;
wait;
end process;
END;
| mit | 6607eb975d25df88c29213644c016fb7 | 0.641897 | 3.748011 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/register.vhd | 1 | 851 | library IEEE;
use ieee.std_logic_1164.all;
entity c_register is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
WR : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end c_register;
architecture behavior of c_register is
begin
P0 : process (clock, input, WR, clear)
variable out_var : std_logic_vector((width - 1) downto 0);
variable Interim_Val : std_logic_vector((width - 1) downto 0);
begin
Interim_Val := input;
if (clear = '1') then
for I in width - 1 downto 0 loop
out_var(I) := '0';
end loop;
output <= out_var;
end if;
if (clear = '0') then
if ((clock = '1') and (clock'EVENT = TRUE) and (WR = '1')) then
output <= Interim_Val;
end if;
end if;
end process P0;
end behavior; | mit | 4fecb5e143f4a1a6cc47f65f7ebb1621 | 0.623972 | 2.736334 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst.vhd | 1 | 43,553 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst.vhd
--
-- Description:
--
-- AXI Master interface utilizing Xilinx LocalLink interface for User Logic
-- Side (IPIC) data transfer interface
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_burst.vhd
-- |
-- |-- proc_common_v4_0 (helper library)
-- |
-- |-- axi_master_burst_reset.vhd
-- |
-- |-- axi_master_rd_llink.vhd
-- |
-- |-- axi_master_wr_llink.vhd
-- |
-- |
-- |-- axi_master_burst_cmd_status.vhd
-- | |-- axi_master_burst_first_stb_offset.vhd
-- | |-- axi_master_burst_stbs_set.vhd
-- |
-- |-- axi_master_burst_rd_wr_cntlr.vhd
-- |-- axi_master_burst_pcc.vhd
-- | |-- axi_master_burst_strb_gen.vhd
-- |-- axi_master_burst_addr_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_rddata_cntl.vhd
-- | |-- axi_master_burst_rdmux.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_wrdata_cntl.vhd
-- | |-- axi_master_burst_strb_gen
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_rd_status_cntl.vhd
-- |-- axi_master_burst_wr_status_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- |-- axi_master_burst_skid_buf.vhd
-- |-- axi_master_burst_skid2mm_buf.vhd
--
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $$
--
-- History:
-- DET 01/18/2011 Version 1_00_a
--
-- DET 2/10/2011 Initial for EDK 13.1
-- ~~~~~~
-- -- Per CR593346
-- - Connected md_error output to the axi_master_burst_cmd_status rw_error
-- output.
-- ^^^^^^
--
-- DET 2/17/2011 Initial for 13.2
-- ~~~~~~
-- -- Per CR593967
-- - Added the port rdwr2llink_int_err to the Cmd/Status Module.
-- This output is now used to initiate a Locallink discontinue
-- when an internal error is detected.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_master_burst_v2_0;
Use axi_master_burst_v2_0.axi_master_burst_reset ;
Use axi_master_burst_v2_0.axi_master_burst_cmd_status ;
Use axi_master_burst_v2_0.axi_master_burst_rd_wr_cntlr ;
Use axi_master_burst_v2_0.axi_master_burst_rd_llink ;
Use axi_master_burst_v2_0.axi_master_burst_wr_llink ;
-------------------------------------------------------------------------------
entity axi_master_burst is
generic (
----------------------------------------------------------------------------
-- AXI4 Related Parameters
----------------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for each AXI MMap
-- transfer by the AXI Master Burst
C_ADDR_PIPE_DEPTH : Integer range 1 to 14 := 1;
-- Specifies the address pipeline depth for the AXI Master Burst
-- when submitting transfer requests to the AXI4 Read and Write
-- Address Channels.
----------------------------------------------------------------------------
-- IPIC Related Parameters
----------------------------------------------------------------------------
C_NATIVE_DATA_WIDTH : INTEGER range 32 to 128 := 32;
-- Set this equal to desired data bus width needed by IPIC
-- LocalLink Data Channels.
C_LENGTH_WIDTH : INTEGER range 12 to 20 := 12;
-- Set this to the desired bit width for the ip2bus_mst_length
-- input port required to specify the maximimum transfer byte
-- count needed for any one command by the User logic.
-- 12 bits = 4095 bytes max per command
-- 13 bits = 8191 bytes max per command
-- 14 bits = 16383 bytes max per command
-- 15 bits = 32767 bytes max per command
-- 16 bits = 65535 bytes max per command
-- 17 bits = 131071 bytes max per command
-- 18 bits = 262143 bytes max per command
-- 19 bits = 524287 bytes max per command
-- 20 bits = 1048575 bytes max per command
----------------------------------------------------------------------------
-- Target FPGA Family Parameter
----------------------------------------------------------------------------
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
----------------------------------------------------------------------------
-- Primary Clock
----------------------------------------------------------------------------
m_axi_aclk : in std_logic ;-- AXI4
----------------------------------------------------------------------------
-- Primary Reset Input (active low)
----------------------------------------------------------------------------
m_axi_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Master Detected Error output
-----------------------------------------------------------------------
md_error : out std_logic ;-- Error output discrete
----------------------------------------------------------------------------
-- AXI4 Master Read Channel
----------------------------------------------------------------------------
-- MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI4 Master Write Channel
-----------------------------------------------------------------------------
-- Write Address Channel -- AXI4
m_axi_awready : in std_logic ; -- AXI4
m_axi_awvalid : out std_logic ; -- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; -- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ; -- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ; -- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ; -- AXI4
-- AXI4
-- Write Data Channel -- AXI4
m_axi_wready : in std_logic ; -- AXI4
m_axi_wvalid : out std_logic ; -- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0); -- AXI4
m_axi_wlast : out std_logic ; -- AXI4
-- AXI4
-- Write Response Channel -- AXI4
m_axi_bready : out std_logic ; -- AXI4
m_axi_bvalid : in std_logic ; -- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------------------
-- IPIC Request/Qualifiers
-----------------------------------------------------------------------------------------
ip2bus_mstrd_req : In std_logic ;-- IPIC CMD
ip2bus_mstwr_req : In std_logic ;-- IPIC CMD
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- IPIC CMD
ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0) ;-- IPIC CMD
ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC CMD
ip2bus_mst_type : in std_logic ;-- IPIC CMD
ip2bus_mst_lock : In std_logic ;-- IPIC CMD
ip2bus_mst_reset : In std_logic ;-- IPIC CMD
-----------------------------------------------------------------------------------------
-- IPIC Request Status Reply
-----------------------------------------------------------------------------------------
bus2ip_mst_cmdack : Out std_logic ;-- IPIC Stat
bus2ip_mst_cmplt : Out std_logic ;-- IPIC Stat
bus2ip_mst_error : Out std_logic ;-- IPIC Stat
bus2ip_mst_rearbitrate : Out std_logic ;-- IPIC Stat
bus2ip_mst_cmd_timeout : out std_logic ;-- IPIC Stat
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel
-----------------------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0 ) ;-- IPIC RD LLink
bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC RD LLink
bus2ip_mstrd_sof_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_eof_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_src_rdy_n : Out std_logic ;-- IPIC RD LLink
bus2ip_mstrd_src_dsc_n : Out std_logic ;-- IPIC RD LLink
ip2bus_mstrd_dst_rdy_n : In std_logic ;-- IPIC RD LLink
ip2bus_mstrd_dst_dsc_n : In std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel
-----------------------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0) ;-- IPIC WR LLink
ip2bus_mstwr_rem : In std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC WR LLink
ip2bus_mstwr_sof_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_eof_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_src_rdy_n : In std_logic ;-- IPIC WR LLink
ip2bus_mstwr_src_dsc_n : In std_logic ;-- IPIC WR LLink
bus2ip_mstwr_dst_rdy_n : Out std_logic ;-- IPIC WR LLink
bus2ip_mstwr_dst_dsc_n : Out std_logic -- IPIC WR LLink
);
end entity axi_master_burst;
architecture implementation of axi_master_burst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant LLINK_DWIDTH : integer := C_NATIVE_DATA_WIDTH;
Constant LENGTH_WIDTH : integer := C_LENGTH_WIDTH;
Constant PCC_CMD_WIDTH : integer := 68; -- in bits
Constant STATUS_WIDTH : integer := 8; -- in bits
Constant RDWR_ID_WIDTH : integer := 4; -- in bits
Constant RDWR_ID : integer := 0; -- in bits
Constant RDWR_MAX_BURST_LEN : integer := C_MAX_BURST_LEN; -- in data beats
Constant RDWR_BTT_USED : integer := LENGTH_WIDTH;
Constant RDWR_ADDR_PIPE_DEPTH : integer := C_ADDR_PIPE_DEPTH;
-- Signal Declarations
signal sig_ipic_reset : std_logic := '0';
signal sig_rst2cmd_stat_reset : std_logic := '0';
signal sig_rst2rdwr_cntlr_reset : std_logic := '0';
signal sig_rst2llink_reset : std_logic := '0';
signal sig_rw_error : std_logic := '0';
signal sig_rdwr2llink_int_err : std_logic := '0';
signal sig_ip2bus_mstrd_req : std_logic := '0';
signal sig_ip2bus_mstwr_req : std_logic := '0';
signal sig_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_ADDR_WIDTH-1) := (others => '0');
signal sig_ip2bus_mst_length : std_logic_vector(0 to LENGTH_WIDTH-1) := (others => '0');
signal sig_ip2bus_mst_be : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) := (others => '0');
signal sig_ip2bus_mst_type : std_logic := '0';
signal sig_ip2bus_mst_lock : std_logic := '0';
signal sig_bus2ip_mst_cmdack : std_logic := '0';
signal sig_bus2ip_mst_cmplt : std_logic := '0';
signal sig_bus2ip_mst_error : std_logic := '0';
signal sig_bus2ip_mst_rearbitrate : std_logic := '0';
signal sig_bus2ip_mst_cmd_timeout : std_logic := '0';
signal sig_llink2cmd_rd_busy : std_logic := '0';
signal sig_llink2cmd_wr_busy : std_logic := '0';
signal sig_pcc2cmd_cmd_ready : std_logic := '0';
signal sig_cmd2pcc_cmd_valid : std_logic := '0';
signal sig_cmd2pcc_command : std_logic_vector(PCC_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2all_doing_read : std_logic := '0';
signal sig_cmd2all_doing_write : std_logic := '0';
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_llink2rd_allow_addr_req : std_logic := '0';
signal sig_rd2llink_addr_req_posted : std_logic := '0';
signal sig_rd2llink_xfer_cmplt : std_logic := '0';
signal sig_llink2wr_allow_addr_req : std_logic := '0';
signal sig_wr2llink_addr_req_posted : std_logic := '0';
signal sig_wr2llink_xfer_cmplt : std_logic := '0';
signal sig_rd2llink_strm_tdata : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal sig_rd2llink_strm_tstrb : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
signal sig_rd2llink_strm_tlast : std_logic := '0';
signal sig_rd2llink_strm_tvalid : std_logic := '0';
signal sig_llink2rd_strm_tready : std_logic := '0';
signal sig_llink2wr_strm_tdata : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal sig_llink2wr_strm_tstrb : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
signal sig_llink2wr_strm_tlast : std_logic := '0';
signal sig_llink2wr_strm_tvalid : std_logic := '0';
signal sig_llink2wr_strm_tready : std_logic := '0';
signal sig_rd_llink_enable : std_logic := '0';
signal sig_wr_llink_enable : std_logic := '0';
signal sig_md_error : std_logic := '0';
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel (Little Endian bit ordering)
-----------------------------------------------------------------------------------------
-- signal sig_bus2ip_mstrd_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0 ) ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_rem : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_sof_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_eof_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_src_rdy_n : std_logic ;-- IPIC RD LLink
-- signal sig_bus2ip_mstrd_src_dsc_n : std_logic ;-- IPIC RD LLink
--
-- signal sig_ip2bus_mstrd_dst_rdy_n : std_logic ;-- IPIC RD LLink
-- signal sig_ip2bus_mstrd_dst_dsc_n : std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Read LocalLink Channel (Big Endian bit ordering)
-----------------------------------------------------------------------------------------
signal sig_bus2ip_mstrd_d : std_logic_vector(0 to C_NATIVE_DATA_WIDTH-1) ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_rem : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_sof_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_eof_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_src_rdy_n : std_logic ;-- IPIC RD LLink
signal sig_bus2ip_mstrd_src_dsc_n : std_logic ;-- IPIC RD LLink
signal sig_ip2bus_mstrd_dst_rdy_n : std_logic ;-- IPIC RD LLink
signal sig_ip2bus_mstrd_dst_dsc_n : std_logic ;-- IPIC RD LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel (Little Endian bit ordering)
-----------------------------------------------------------------------------------------
-- signal sig_ip2bus_mstwr_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0) ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_rem : std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_sof_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_eof_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_src_rdy_n : std_logic ;-- IPIC WR LLink
-- signal sig_ip2bus_mstwr_src_dsc_n : std_logic ;-- IPIC WR LLink
--
-- signal sig_bus2ip_mstwr_dst_rdy_n : std_logic ;-- IPIC WR LLink
-- signal sig_bus2ip_mstwr_dst_dsc_n : std_logic ;-- IPIC WR LLink
-----------------------------------------------------------------------------------------
-- IPIC Write LocalLink Channel (Big Endian bit ordering)
-----------------------------------------------------------------------------------------
signal sig_ip2bus_mstwr_d : std_logic_vector(0 to C_NATIVE_DATA_WIDTH-1) ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_rem : std_logic_vector(0 to (C_NATIVE_DATA_WIDTH/8)-1) ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_sof_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_eof_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_src_rdy_n : std_logic ;-- IPIC WR LLink
signal sig_ip2bus_mstwr_src_dsc_n : std_logic ;-- IPIC WR LLink
signal sig_bus2ip_mstwr_dst_rdy_n : std_logic ;-- IPIC WR LLink
signal sig_bus2ip_mstwr_dst_dsc_n : std_logic ;-- IPIC WR LLink
begin --(architecture implementation)
-- Master detected Error output discrete
-- md_error <= sig_md_error ;
md_error <= sig_rw_error ;
-- Assign IPIC Command Inputs
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
sig_ip2bus_mstrd_req <= ip2bus_mstrd_req ;
sig_ip2bus_mstwr_req <= ip2bus_mstwr_req ;
sig_ip2bus_mst_addr <= ip2bus_mst_addr ;
sig_ip2bus_mst_length <= ip2bus_mst_length ;
sig_ip2bus_mst_be <= ip2bus_mst_be ;
sig_ip2bus_mst_type <= ip2bus_mst_type ;
sig_ip2bus_mst_lock <= ip2bus_mst_lock ;
sig_ipic_reset <= ip2bus_mst_reset ;
-- Assign IPIC Status Outputs
bus2ip_mst_cmdack <= sig_bus2ip_mst_cmdack ;
bus2ip_mst_cmplt <= sig_bus2ip_mst_cmplt ;
bus2ip_mst_error <= sig_bus2ip_mst_error ;
bus2ip_mst_rearbitrate <= sig_bus2ip_mst_rearbitrate ;
bus2ip_mst_cmd_timeout <= sig_bus2ip_mst_cmd_timeout ;
-- Assign Read LocalLink Ports
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
bus2ip_mstrd_d <= sig_bus2ip_mstrd_d ;
bus2ip_mstrd_rem <= sig_bus2ip_mstrd_rem ;
bus2ip_mstrd_sof_n <= sig_bus2ip_mstrd_sof_n ;
bus2ip_mstrd_eof_n <= sig_bus2ip_mstrd_eof_n ;
bus2ip_mstrd_src_rdy_n <= sig_bus2ip_mstrd_src_rdy_n ;
bus2ip_mstrd_src_dsc_n <= sig_bus2ip_mstrd_src_dsc_n ;
sig_ip2bus_mstrd_dst_rdy_n <= ip2bus_mstrd_dst_rdy_n ;
sig_ip2bus_mstrd_dst_dsc_n <= ip2bus_mstrd_dst_dsc_n ;
-- Assign Write LocalLink Ports
-- Note that this also changes the bit ordering
-- from Little Endian to big endian for vectors.
sig_ip2bus_mstwr_d <= ip2bus_mstwr_d ;
sig_ip2bus_mstwr_rem <= ip2bus_mstwr_rem ;
sig_ip2bus_mstwr_sof_n <= ip2bus_mstwr_sof_n ;
sig_ip2bus_mstwr_eof_n <= ip2bus_mstwr_eof_n ;
sig_ip2bus_mstwr_src_rdy_n <= ip2bus_mstwr_src_rdy_n ;
sig_ip2bus_mstwr_src_dsc_n <= ip2bus_mstwr_src_dsc_n ;
bus2ip_mstwr_dst_rdy_n <= sig_bus2ip_mstwr_dst_rdy_n ;
bus2ip_mstwr_dst_dsc_n <= sig_bus2ip_mstwr_dst_dsc_n ;
------------------------------------------------------------
-- Instance: I_RESET_MODULE
--
-- Description:
-- Reset Module instance.
--
------------------------------------------------------------
I_RESET_MODULE : entity axi_master_burst_v2_0.axi_master_burst_reset
port map (
-- Clock Input
axi_aclk => m_axi_aclk ,
-- Reset Input (active low)
axi_aresetn => m_axi_aresetn ,
-- IPIC Reset Input
ip2bus_mst_reset => sig_ipic_reset ,
-- HW Reset to internal reset groups --------------------------
rst2cmd_reset_out => sig_rst2cmd_stat_reset ,
rst2rdwr_reset_out => sig_rst2rdwr_cntlr_reset ,
rst2llink_reset_out => sig_rst2llink_reset
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS_MODULE
--
-- Description:
-- Instance of the Command and Status Module
--
------------------------------------------------------------
I_CMD_STATUS_MODULE : entity axi_master_burst_v2_0.axi_master_burst_cmd_status
generic map (
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH,
C_CMD_WIDTH => PCC_CMD_WIDTH ,
C_CMD_BTT_USED_WIDTH => LENGTH_WIDTH ,
C_STS_WIDTH => STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock inputs
axi_aclk => m_axi_aclk ,
-- Reset inputs
axi_reset => sig_rst2cmd_stat_reset ,
-- RW_ERROR Output Discrete
rw_error => sig_rw_error ,
-- Internal error Output Discrete to LocalLink backends
-- (Asserted until Pertinent LocalLink IF is not busy)
rdwr2llink_int_err => sig_rdwr2llink_int_err ,
-- IPIC Request/Qualifiers
ip2bus_mstrd_req => sig_ip2bus_mstrd_req ,
ip2bus_mstwr_req => sig_ip2bus_mstwr_req ,
ip2bus_mst_addr => sig_ip2bus_mst_addr ,
ip2bus_mst_length => sig_ip2bus_mst_length ,
ip2bus_mst_be => sig_ip2bus_mst_be ,
ip2bus_mst_type => sig_ip2bus_mst_type ,
ip2bus_mst_lock => sig_ip2bus_mst_lock ,
ip2bus_mst_reset => LOGIC_LOW ,
-- IPIC Request Status Reply
bus2ip_mst_cmdack => sig_bus2ip_mst_cmdack ,
bus2ip_mst_cmplt => sig_bus2ip_mst_cmplt ,
bus2ip_mst_error => sig_bus2ip_mst_error ,
bus2ip_mst_rearbitrate => sig_bus2ip_mst_rearbitrate ,
bus2ip_mst_cmd_timeout => sig_bus2ip_mst_cmd_timeout ,
-- IPIC LocalLink Busy Flag
mstrd_llink_busy => sig_llink2cmd_rd_busy ,
mstwr_llink_busy => sig_llink2cmd_wr_busy ,
-- PCC Command Interface
pcc2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
cmd2pcc_cmd_valid => sig_cmd2pcc_cmd_valid ,
cmd2pcc_command => sig_cmd2pcc_command ,
-- Read/Write Command Indicator Interface
cmd2all_doing_read => sig_cmd2all_doing_read ,
cmd2all_doing_write => sig_cmd2all_doing_write ,
-- Read Status Controller Interface
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2stat_status => sig_rsc2stat_status ,
-- Write Status Controller Interface
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2stat_status => sig_wsc2stat_status
);
------------------------------------------------------------
-- Instance: I_RD_WR_CNTRL_MODULE
--
-- Description:
-- Instance of the Read and Write Controller Module
--
------------------------------------------------------------
I_RD_WR_CNTRL_MODULE : entity axi_master_burst_v2_0.axi_master_burst_rd_wr_cntlr
generic map (
C_RDWR_ID_WIDTH => RDWR_ID_WIDTH ,
C_RDWR_ARID => RDWR_ID ,
C_RDWR_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_RDWR_MDATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_RDWR_SDATA_WIDTH => C_NATIVE_DATA_WIDTH ,
C_RDWR_MAX_BURST_LEN => RDWR_MAX_BURST_LEN ,
C_RDWR_BTT_USED => RDWR_BTT_USED ,
C_RDWR_ADDR_PIPE_DEPTH => RDWR_ADDR_PIPE_DEPTH ,
C_RDWR_PCC_CMD_WIDTH => PCC_CMD_WIDTH ,
C_RDWR_STATUS_WIDTH => STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- RDWR Primary Clock input
rdwr_aclk => m_axi_aclk ,
-- RDWR Primary Reset input
rdwr_areset => sig_rst2rdwr_cntlr_reset ,
-- RDWR Master detected Error Output Discrete
rdwr_md_error => sig_md_error ,
-- Command/Status Module PCC Command Interface (AXI Stream Like)
cmd2rdwr_cmd_valid => sig_cmd2pcc_cmd_valid ,
rdwr2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
cmd2rdwr_cmd_data => sig_cmd2pcc_command ,
-- Command/Status Module Type Interface
cmd2rdwr_doing_read => sig_cmd2all_doing_read ,
cmd2rdwr_doing_write => sig_cmd2all_doing_write ,
-- Command/Status Module Read Status Ports (AXI Stream Like)
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2stat_status => sig_rsc2stat_status ,
-- Command/Status Module Write Status Ports (AXI Stream Like)
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2stat_status => sig_wsc2stat_status ,
-- Read Address Posting Contols/Status
rd_allow_addr_req => sig_llink2rd_allow_addr_req ,
rd_addr_req_posted => sig_rd2llink_addr_req_posted ,
rd_xfer_cmplt => sig_rd2llink_xfer_cmplt ,
-- Write Address Posting Contols/Status
wr_allow_addr_req => sig_llink2wr_allow_addr_req ,
wr_addr_req_posted => sig_wr2llink_addr_req_posted ,
wr_xfer_cmplt => sig_wr2llink_xfer_cmplt ,
-- LocalLink Enable Outputs (1 clock pulse)
rd_llink_enable => sig_rd_llink_enable ,
wr_llink_enable => sig_wr_llink_enable ,
-- AXI Read Address Channel I/O
rd_arid => open ,
rd_araddr => m_axi_araddr ,
rd_arlen => m_axi_arlen ,
rd_arsize => m_axi_arsize ,
rd_arburst => m_axi_arburst ,
rd_arprot => m_axi_arprot ,
rd_arcache => m_axi_arcache ,
rd_arvalid => m_axi_arvalid ,
rd_arready => m_axi_arready ,
-- AXI Read Data Channel I/O
rd_rdata => m_axi_rdata ,
rd_rresp => m_axi_rresp ,
rd_rlast => m_axi_rlast ,
rd_rvalid => m_axi_rvalid ,
rd_rready => m_axi_rready ,
-- AXI Read Master Stream Channel I/O
rd_strm_tdata => sig_rd2llink_strm_tdata ,
rd_strm_tstrb => sig_rd2llink_strm_tstrb ,
rd_strm_tlast => sig_rd2llink_strm_tlast ,
rd_strm_tvalid => sig_rd2llink_strm_tvalid ,
rd_strm_tready => sig_llink2rd_strm_tready ,
-- AXI Write Address Channel I/O
wr_awid => open ,
wr_awaddr => m_axi_awaddr ,
wr_awlen => m_axi_awlen ,
wr_awsize => m_axi_awsize ,
wr_awburst => m_axi_awburst ,
wr_awprot => m_axi_awprot ,
wr_awcache => m_axi_awcache ,
wr_awvalid => m_axi_awvalid ,
wr_awready => m_axi_awready ,
-- RDWR AXI Write Data Channel I/O
wr_wdata => m_axi_wdata ,
wr_wstrb => m_axi_wstrb ,
wr_wlast => m_axi_wlast ,
wr_wvalid => m_axi_wvalid ,
wr_wready => m_axi_wready ,
-- RDWR AXI Write response Channel I/O
wr_bresp => m_axi_bresp ,
wr_bvalid => m_axi_bvalid ,
wr_bready => m_axi_bready ,
-- RDWR AXI Slave Stream Channel I/O
wr_strm_tdata => sig_llink2wr_strm_tdata ,
wr_strm_tstrb => sig_llink2wr_strm_tstrb ,
wr_strm_tlast => sig_llink2wr_strm_tlast ,
wr_strm_tvalid => sig_llink2wr_strm_tvalid ,
wr_strm_tready => sig_llink2wr_strm_tready
);
------------------------------------------------------------
-- Instance: I_RD_LLINK_ADAPTER
--
-- Description:
-- Instance for the Read AXI Stream to Read LocalLink Adapter
--
------------------------------------------------------------
I_RD_LLINK_ADAPTER : entity axi_master_burst_v2_0.axi_master_burst_rd_llink
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH
)
port map (
-- Read LocalLink Clock input
rdllink_aclk => m_axi_aclk ,
-- Read LocalLink Reset input
rdllink_areset => sig_rst2llink_reset ,
-- Read Cntlr Internal Error Indication
rdllink_rd_error => sig_rdwr2llink_int_err ,
-- LocalLink Enable Control (1 Clock wide pulse)
rdllink_llink_enable => sig_rd_llink_enable ,
-- IPIC LocalLink Busy Flag
rdllink_llink_busy => sig_llink2cmd_rd_busy ,
-- Read Address Posting Contols/Status
rdllink_allow_addr_req => sig_llink2rd_allow_addr_req ,
rdllink_addr_req_posted => sig_rd2llink_addr_req_posted ,
rdllink_xfer_cmplt => sig_rd2llink_xfer_cmplt ,
-- Read AXI Slave Master Channel
rdllink_strm_tdata => sig_rd2llink_strm_tdata ,
rdllink_strm_tstrb => sig_rd2llink_strm_tstrb ,
rdllink_strm_tlast => sig_rd2llink_strm_tlast ,
rdllink_strm_tvalid => sig_rd2llink_strm_tvalid ,
rdllink_strm_tready => sig_llink2rd_strm_tready ,
-- IPIC Read LocalLink Channel
bus2ip_mstrd_d => sig_bus2ip_mstrd_d ,
bus2ip_mstrd_rem => sig_bus2ip_mstrd_rem ,
bus2ip_mstrd_sof_n => sig_bus2ip_mstrd_sof_n ,
bus2ip_mstrd_eof_n => sig_bus2ip_mstrd_eof_n ,
bus2ip_mstrd_src_rdy_n => sig_bus2ip_mstrd_src_rdy_n ,
bus2ip_mstrd_src_dsc_n => sig_bus2ip_mstrd_src_dsc_n ,
ip2bus_mstrd_dst_rdy_n => sig_ip2bus_mstrd_dst_rdy_n ,
ip2bus_mstrd_dst_dsc_n => sig_ip2bus_mstrd_dst_dsc_n
);
------------------------------------------------------------
-- Instance: I_WR_LLINK_ADAPTER
--
-- Description:
-- Instance for the Write LocalLink to AXI Stream Adapter
--
------------------------------------------------------------
I_WR_LLINK_ADAPTER : entity axi_master_burst_v2_0.axi_master_burst_wr_llink
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DATA_WIDTH
)
port map (
-- Write LocalLink Clock input
wrllink_aclk => m_axi_aclk ,
-- Write LocalLink Reset input
wrllink_areset => sig_rst2llink_reset ,
-- RDWR Cntlr Internal Error Indication
wrllink_wr_error => sig_rdwr2llink_int_err ,
-- LocalLink Enable Control (1 Clock wide pulse)
wrllink_llink_enable => sig_wr_llink_enable ,
-- IPIC LocalLink Busy Flag
wrllink_llink_busy => sig_llink2cmd_wr_busy ,
-- Write Address Posting Contols/Status
wrllink_allow_addr_req => sig_llink2wr_allow_addr_req ,
wrllink_addr_req_posted => sig_wr2llink_addr_req_posted ,
wrllink_xfer_cmplt => sig_wr2llink_xfer_cmplt ,
-- Write AXI Slave Master Channel
wrllink_strm_tdata => sig_llink2wr_strm_tdata ,
wrllink_strm_tstrb => sig_llink2wr_strm_tstrb ,
wrllink_strm_tlast => sig_llink2wr_strm_tlast ,
wrllink_strm_tvalid => sig_llink2wr_strm_tvalid ,
wrllink_strm_tready => sig_llink2wr_strm_tready ,
-- IPIC Write LocalLink Channel
ip2bus_mstwr_d => sig_ip2bus_mstwr_d ,
ip2bus_mstwr_rem => sig_ip2bus_mstwr_rem ,
ip2bus_mstwr_sof_n => sig_ip2bus_mstwr_sof_n ,
ip2bus_mstwr_eof_n => sig_ip2bus_mstwr_eof_n ,
ip2bus_mstwr_src_rdy_n => sig_ip2bus_mstwr_src_rdy_n ,
ip2bus_mstwr_src_dsc_n => sig_ip2bus_mstwr_src_dsc_n ,
bus2ip_mstwr_dst_rdy_n => sig_bus2ip_mstwr_dst_rdy_n ,
bus2ip_mstwr_dst_dsc_n => sig_bus2ip_mstwr_dst_dsc_n
);
end implementation;
| apache-2.0 | 070c5a766145663368a846a47de418f5 | 0.458889 | 4.072658 | false | false | false | false |
jdryg/tis100cpu | instruction_decoder_tb.vhd | 1 | 6,668 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY instruction_decoder_tb IS
END instruction_decoder_tb;
ARCHITECTURE behavior OF instruction_decoder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT instruction_decoder
PORT(
I_instr : IN std_logic_vector(31 downto 0);
O_dst : OUT std_logic_vector(2 downto 0);
O_srcA : OUT std_logic_vector(2 downto 0);
O_srcB : OUT std_logic_vector(1 downto 0);
O_imm : OUT std_logic_vector(15 downto 0);
O_aluOp : OUT std_logic_vector(2 downto 0);
O_srcA_isPort : OUT std_logic;
O_dst_isPort : OUT std_logic;
O_enableWrite : OUT std_logic;
O_containsIMM : OUT std_logic;
O_isJmp : OUT std_logic;
O_jmpCondition : OUT std_logic_vector(2 downto 0);
O_isSWP : OUT std_logic
);
END COMPONENT;
--Inputs
signal I_instr : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal O_dst : std_logic_vector(2 downto 0);
signal O_srcA : std_logic_vector(2 downto 0);
signal O_srcB : std_logic_vector(1 downto 0);
signal O_imm : std_logic_vector(15 downto 0);
signal O_aluOp : std_logic_vector(2 downto 0);
signal O_srcA_isPort : std_logic;
signal O_dst_isPort : std_logic;
signal O_enableWrite : std_logic;
signal O_containsIMM : std_logic;
signal O_isJmp : std_logic;
signal O_jmpCondition : std_logic_vector(2 downto 0);
signal O_isSWP : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: instruction_decoder PORT MAP (
I_instr => I_instr,
O_dst => O_dst,
O_srcA => O_srcA,
O_srcB => O_srcB,
O_imm => O_imm,
O_aluOp => O_aluOp,
O_srcA_isPort => O_srcA_isPort,
O_dst_isPort => O_dst_isPort,
O_enableWrite => O_enableWrite,
O_containsIMM => O_containsIMM,
O_isJmp => O_isJmp,
O_jmpCondition => O_jmpCondition,
O_isSWP => O_isSWP
);
-- Stimulus process
stim_proc: process
begin
I_instr <= X"80800005";
wait for 10 ns;
assert O_dst = "001" report "(1) Invalid dst value" severity error;
assert O_srcA = "000" report "(1) Invalid srcA value" severity error;
assert O_srcB = "00" report "(1) Invalid srcB value" severity error;
assert O_imm = X"0005" report "(1) Invalid immediate operand value" severity error;
assert O_aluOp = "000" report "(1) Invalid ALU operation" severity error;
assert O_srcA_isPort = '0' report "(1) Invalid srcA_isPort flag" severity error;
assert O_dst_isPort = '0' report "(1) Invalid dst_isPort flag" severity error;
assert O_enableWrite = '1' report "(1) Invalid enableWrite flag" severity error;
assert O_containsIMM = '1' report "(1) Invalid containsIMM flag" severity error;
assert O_isJmp = '0' report "(1) Invalid isJmp flag" severity error;
assert O_jmpCondition = "111" report "(1) Invalid jump condition" severity error;
assert O_isSWP = '0' report "(1) Invalid SWP flag" severity error;
report "Finished decoding 'ADD ACC, NIL, 5'";
I_instr <= X"84900001";
wait for 10 ns;
assert O_dst = "001" report "(2) Invalid dst value" severity error;
assert O_srcA = "001" report "(2) Invalid srcA value" severity error;
assert O_srcB = "00" report "(2) Invalid srcB value" severity error;
assert O_imm = X"0001" report "(2) Invalid immediate operand value" severity error;
assert O_aluOp = "001" report "(2) Invalid ALU operation" severity error;
assert O_srcA_isPort = '0' report "(2) Invalid srcA_isPort flag" severity error;
assert O_dst_isPort = '0' report "(2) Invalid dst_isPort flag" severity error;
assert O_enableWrite = '1' report "(2) Invalid enableWrite flag" severity error;
assert O_containsIMM = '1' report "(2) Invalid containsIMM flag" severity error;
assert O_isJmp = '0' report "(2) Invalid isJmp flag" severity error;
assert O_jmpCondition = "111" report "(2) Invalid jump condition" severity error;
assert O_isSWP = '0' report "(2) Invalid SWP flag" severity error;
report "Finished decoding 'SUB ACC, ACC, 1'";
I_instr <= X"CC100005";
wait for 10 ns;
assert O_dst = "000" report "(3) Invalid dst value" severity error;
assert O_srcA = "001" report "(3) Invalid srcA value" severity error;
assert O_srcB = "00" report "(3) Invalid srcB value" severity error;
assert O_imm = X"0005" report "(3) Invalid immediate operand value" severity error;
assert O_aluOp = "011" report "(3) Invalid ALU operation" severity error;
assert O_srcA_isPort = '0' report "(3) Invalid srcA_isPort flag" severity error;
assert O_dst_isPort = '0' report "(3) Invalid dst_isPort flag" severity error;
assert O_enableWrite = '0' report "(3) Invalid enableWrite flag" severity error;
assert O_containsIMM = '1' report "(3) Invalid containsIMM flag" severity error;
assert O_isJmp = '1' report "(3) Invalid isJmp flag" severity error;
assert O_jmpCondition = "011" report "(3) Invalid jump condition" severity error;
assert O_isSWP = '0' report "(3) Invalid SWP flag" severity error;
report "Finished decoding 'JMP EQUAL, 5'";
I_instr <= X"10000000";
wait for 10 ns;
assert O_dst = "000" report "(3) Invalid dst value" severity error;
assert O_srcA = "000" report "(3) Invalid srcA value" severity error;
assert O_srcB = "00" report "(3) Invalid srcB value" severity error;
assert O_imm = X"0000" report "(3) Invalid immediate operand value" severity error;
assert O_aluOp = "000" report "(3) Invalid ALU operation" severity error;
assert O_srcA_isPort = '0' report "(3) Invalid srcA_isPort flag" severity error;
assert O_dst_isPort = '0' report "(3) Invalid dst_isPort flag" severity error;
assert O_enableWrite = '1' report "(3) Invalid enableWrite flag" severity error;
assert O_containsIMM = '0' report "(3) Invalid containsIMM flag" severity error;
assert O_isJmp = '0' report "(3) Invalid isJmp flag" severity error;
assert O_jmpCondition = "111" report "(3) Invalid jump condition" severity error;
assert O_isSWP = '1' report "(3) Invalid SWP flag" severity error;
report "Finished decoding 'SWP'";
wait;
end process;
END;
| mit | a08fc79897974f144c8411f7a746f146 | 0.620276 | 3.494759 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/seven_segment_display_mux.vhd | 1 | 1,839 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayMux is
Port (entrada: in STD_LOGIC_VECTOR (15 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output_h: out STD_LOGIC_VECTOR (7 downto 0);
current_display: out STD_LOGIC_VECTOR (3 downto 0);
clk_1k: out STD_LOGIC);
end SevenSegmentDisplayMux;
architecture Behavioral of SevenSegmentDisplayMux is
type STD_LOGIC_ARRAY_4 is array (3 downto 0) of STD_LOGIC_VECTOR (7 downto 0);
signal display : STD_LOGIC_ARRAY_4;
signal cont : INTEGER range 0 to 3 := 0;
signal disp_sel : STD_LOGIC_VECTOR (3 downto 0) := "1110";
signal clk_1k_sgn : STD_LOGIC := '0';
signal clock_1k : INTEGER range 0 to 26000 :=0;
begin
clock_div : process (reset, clock)
begin
if reset = '1' then
clock_1k <= 0;
elsif clock'event and clock ='1' then
if(clock_1k > 25000) then
clk_1k_sgn <= not clk_1k_sgn;
clock_1k <= 0;
else
clock_1k <= clock_1k +1;
end if;
else
clock_1k <= clock_1k;
end if;
end process;
process(clk_1k_sgn, reset)
begin
if reset = '1' then
disp_sel <= "1110";
cont <= 0;
elsif clk_1k_sgn'event and clk_1k_sgn = '1' then
disp_sel(3 downto 1) <= disp_sel(2 downto 0);
disp_sel(0) <= disp_sel(3);
cont <= cont +1;
else
disp_sel <= disp_sel;
cont <= cont;
end if;
end process;
current_display <= disp_sel;
laco_for : for i in 0 to 3 generate
display1 : entity work.SevenSegmentDisplayDriver
port map (entrada((i+1)*4 -1 downto i*4),
clock,
reset,
display(i));
output_h <= display(cont REM 4);
end generate;
clk_1k <= clk_1k_sgn;
end Behavioral;
| mit | cd10668dc9c2777ae10317056baab049 | 0.597607 | 3.116949 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/asap-alap-random/ewf_asap.vhd | 1 | 3,066 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_asap_entity;
ARCHITECTURE ewf_asap_description OF ewf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register3 := register3 * 12;
output1 <= register6 + register4;
register2 := register2 * 15;
WHEN "00001001" =>
register3 := register1 + register3;
register2 := register2 + 17;
WHEN "00001010" =>
register1 := register1 + register3;
register4 := register5 + register3;
register5 := register6 + register2;
register6 := register2 + 19;
WHEN "00001011" =>
register1 := register1 * 21;
register4 := register4 + 23;
register5 := register5 + 25;
register6 := register6 * 27;
WHEN "00001100" =>
register1 := register1 + 29;
register7 := register4 * 31;
register8 := register5 * 33;
output2 <= register2 + register6;
WHEN "00001101" =>
output3 <= register3 + register1;
register1 := register7 + 37;
register2 := register8 + 39;
WHEN "00001110" =>
output4 <= register4 + register1;
output5 <= register5 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_asap_description; | gpl-3.0 | e646ce047171cda53c7107b073a91cf6 | 0.681344 | 3.41806 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/fifo_generator_v12_0_top.vhd | 5 | 607,545 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 0cb1c85f2c9f7b8856195b31c4e5a748 | 0.955672 | 1.80639 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/metaheurísticas/hal_hype.vhd | 1 | 1,541 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:29)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_hype_entity;
ARCHITECTURE hal_hype_description OF hal_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "00101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_hype_description; | gpl-3.0 | 0396ff322f5191837fb30e27b1dc9cf5 | 0.654121 | 2.974903 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/fake.vhd | 2 | 839 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Shifter2 is
generic (N : integer := 16);
port (A1 : in std_logic_vector(N-1 downto 0);
A2 : in std_logic_vector(N-1 downto 0);
A3 : in std_logic_vector(N-1 downto 0);
A4 : in std_logic_vector(N-1 downto 0);
B : out std_logic_vector(N-1 downto 0);
C : out std_logic_vector(N-1 downto 0);
D : out std_logic_vector(N-1 downto 0);
E : out std_logic_vector(N-1 downto 0));
end Shifter2;
architecture Behavioral of Shifter2 is
begin
B(N-1 downto 2) <= A1(N-3 downto 0);
B(1) <= '0';
B(0) <= '0';
C(N-1 downto 2) <= A2(N-3 downto 0);
C(1) <= '0';
C(0) <= '0';
D(N-1 downto 2) <= A3(N-3 downto 0);
D(1) <= '0';
D(0) <= '0';
E(N-1 downto 2) <= A4(N-3 downto 0);
E(1) <= '0';
E(0) <= '0';
end Behavioral;
| lgpl-3.0 | 5c5c28ce96986f79258c0782bf23bf07 | 0.544696 | 2.397143 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/counter_bit.vhd | 15 | 8,803 | -------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
| apache-2.0 | 6d774eb24282c17350f0e23b566c5146 | 0.403385 | 5.007395 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_status_flags_as.vhd | 5 | 15,251 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 124f5e460631f96d3856346570252e3e | 0.935742 | 1.882142 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_3.vhd | 1 | 193,760 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_3x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A140: buffer std_logic
);
end x25_3x;
architecture x25_3x_behav of x25_3x is
signal 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7647a,a7648a,a7649a,a7653a,a7654a,a7658a,a7659a,a7660a,a7663a,a7667a,a7668a,a7669a,a7673a,a7674a,a7678a,a7679a,a7680a,a7683a,a7687a,a7688a,a7689a,a7693a,a7694a,a7698a,a7699a,a7700a,a7703a,a7707a,a7708a,a7709a,a7713a,a7714a,a7718a,a7719a,a7720a,a7723a,a7727a,a7728a,a7729a,a7733a,a7734a,a7738a,a7739a,a7740a,a7743a,a7747a,a7748a,a7749a,a7753a,a7754a,a7758a,a7759a,a7760a,a7763a,a7767a,a7768a,a7769a,a7773a,a7774a,a7778a,a7779a,a7780a,a7783a,a7787a,a7788a,a7789a,a7793a,a7794a,a7798a,a7799a,a7800a,a7803a,a7807a,a7808a,a7809a,a7813a,a7814a,a7818a,a7819a,a7820a,a7823a,a7827a,a7828a,a7829a,a7833a,a7834a,a7838a,a7839a,a7840a,a7843a,a7847a,a7848a,a7849a,a7853a,a7854a,a7858a,a7859a,a7860a,a7863a,a7867a,a7868a,a7869a,a7873a,a7874a,a7878a,a7879a,a7880a,a7883a,a7887a,a7888a,a7889a,a7893a,a7894a,a7898a,a7899a,a7900a,a7903a,a7907a,a7908a,a7909a,a7913a,a7914a,a7918a,a7919a,a7920a,a7923a,a7927a,a7928a,a7929a,a7933a,a7934a,a7938a,a7939a,a7940a,a7943a,a7947a,a7948a,a7949a,a7953a,a7954a,a7958a,a7959a,a7960a,a7964a,a7965a,a7969a,a7970a,a7971a,a7975a,a7976a,a7980a,a7981a,a7982a,a7986a,a7987a,a7991a,a7992a,a7993a,a7997a,a7998a,a8002a,a8003a,a8004a,a8008a,a8009a,a8013a,a8014a,a8015a,a8019a,a8020a,a8024a,a8025a,a8026a,a8030a,a8031a,a8035a,a8036a,a8037a,a8041a,a8042a,a8046a,a8047a,a8048a,a8052a,a8053a,a8057a,a8058a,a8059a,a8063a,a8064a,a8068a,a8069a,a8070a,a8074a,a8075a,a8079a,a8080a,a8081a,a8085a,a8086a,a8090a,a8091a,a8092a,a8096a,a8097a,a8101a,a8102a,a8103a,a8107a,a8108a,a8112a,a8113a,a8114a,a8118a,a8119a,a8123a,a8124a,a8125a,a8129a,a8130a,a8134a,a8135a,a8136a,a8140a,a8141a,a8145a,a8146a,a8147a,a8151a,a8152a,a8156a,a8157a,a8158a,a8162a,a8163a,a8167a,a8168a,a8169a,a8173a,a8174a,a8178a,a8179a,a8180a,a8184a,a8185a,a8189a,a8190a,a8191a,a8195a,a8196a,a8200a,a8201a,a8202a,a8206a,a8207a,a8211a,a8212a,a8213a,a8217a,a8218a,a8222a,a8223a,a8224a,a8228a,a8229a,a8233a,a8234a,a8235a,a8239a,a8240a,a8244a,a8245a,a8246a,a8250a,a8251a,a8255a,a8256a,a8257a,a8261a,a8262a,a8266a,a8267a,a8268a,a8272a,a8273a,a8277a,a8278a,a8279a,a8283a,a8284a,a8288a,a8289a,a8290a,a8294a,a8295a,a8299a,a8300a,a8301a,a8305a,a8306a,a8310a,a8311a,a8312a,a8316a,a8317a,a8321a,a8322a,a8323a,a8327a,a8328a,a8332a,a8333a,a8334a,a8338a,a8339a,a8343a,a8344a,a8345a,a8349a,a8350a,a8354a,a8355a,a8356a,a8360a,a8361a,a8365a,a8366a,a8367a,a8371a,a8372a,a8376a,a8377a,a8378a,a8382a,a8383a,a8387a,a8388a,a8389a,a8393a,a8394a,a8398a,a8399a,a8400a,a8404a,a8405a,a8409a,a8410a,a8411a,a8415a,a8416a,a8420a,a8421a,a8422a,a8426a,a8427a,a8431a,a8432a,a8433a,a8437a,a8438a,a8442a,a8443a,a8444a,a8448a,a8449a,a8453a,a8454a,a8455a,a8459a,a8460a,a8464a,a8465a,a8466a,a8470a,a8471a,a8475a,a8476a,a8477a,a8481a,a8482a,a8486a,a8487a,a8488a,a8492a,a8493a,a8497a,a8498a,a8499a,a8503a,a8504a,a8508a,a8509a,a8510a,a8514a,a8515a,a8519a,a8520a,a8521a,a8525a,a8526a,a8530a,a8531a,a8532a,a8536a,a8537a,a8541a,a8542a,a8543a,a8547a,a8548a,a8552a,a8553a,a8554a,a8558a,a8559a,a8563a,a8564a,a8565a,a8569a,a8570a,a8574a,a8575a,a8576a,a8580a,a8581a,a8585a,a8586a,a8587a,a8591a,a8592a,a8596a,a8597a,a8598a,a8602a,a8603a,a8607a,a8608a,a8609a,a8613a,a8614a,a8618a,a8619a,a8620a,a8624a,a8625a,a8629a,a8630a,a8631a,a8635a,a8636a,a8640a,a8641a,a8642a,a8646a,a8647a,a8651a,a8652a,a8653a,a8657a,a8658a,a8662a,a8663a,a8664a,a8668a,a8669a,a8673a,a8674a,a8675a,a8679a,a8680a,a8684a,a8685a,a8686a,a8690a,a8691a,a8695a,a8696a,a8697a,a8701a,a8702a,a8706a,a8707a,a8708a,a8712a,a8713a,a8717a,a8718a,a8719a,a8723a,a8724a,a8728a,a8729a,a8730a,a8734a,a8735a,a8739a,a8740a,a8741a,a8745a,a8746a,a8750a,a8751a,a8752a,a8756a,a8757a,a8761a,a8762a,a8763a,a8767a,a8768a,a8772a,a8773a,a8774a,a8778a,a8779a,a8783a,a8784a,a8785a,a8789a,a8790a,a8794a,a8795a,a8796a,a8800a,a8801a,a8805a,a8806a,a8807a,a8811a,a8812a,a8816a,a8817a,a8818a,a8822a,a8823a,a8827a,a8828a,a8829a,a8833a,a8834a,a8838a,a8839a,a8840a,a8844a,a8845a,a8849a,a8850a,a8851a,a8855a,a8856a,a8860a,a8861a,a8862a,a8866a,a8867a,a8871a,a8872a,a8873a,a8877a,a8878a,a8882a,a8883a,a8884a,a8888a,a8889a,a8893a,a8894a,a8895a,a8899a,a8900a,a8904a,a8905a,a8906a,a8910a,a8911a,a8915a,a8916a,a8917a,a8921a,a8922a,a8926a,a8927a,a8928a,a8932a,a8933a,a8937a,a8938a,a8939a,a8943a,a8944a,a8948a,a8949a,a8950a,a8954a,a8955a,a8959a,a8960a,a8961a,a8965a,a8966a,a8970a,a8971a,a8972a,a8976a,a8977a,a8981a,a8982a,a8983a,a8987a,a8988a,a8992a,a8993a,a8994a,a8998a,a8999a,a9003a,a9004a,a9005a,a9009a,a9010a,a9014a,a9015a,a9016a,a9020a,a9021a,a9025a,a9026a,a9027a,a9031a,a9032a,a9036a,a9037a,a9038a,a9042a,a9043a,a9047a,a9048a,a9049a,a9053a,a9054a,a9058a,a9059a,a9060a,a9064a,a9065a,a9069a,a9070a,a9071a,a9075a,a9076a,a9080a,a9081a,a9082a,a9086a,a9087a,a9091a,a9092a,a9093a,a9097a,a9098a,a9102a,a9103a,a9104a,a9108a,a9109a,a9113a,a9114a,a9115a,a9119a,a9120a,a9124a,a9125a,a9126a,a9130a,a9131a,a9135a,a9136a,a9137a,a9141a,a9142a,a9146a,a9147a,a9148a,a9152a,a9153a,a9157a,a9158a,a9159a,a9163a,a9164a,a9168a,a9169a,a9170a,a9174a,a9175a,a9179a,a9180a,a9181a,a9185a,a9186a,a9190a,a9191a,a9192a,a9196a,a9197a,a9201a,a9202a,a9203a,a9207a,a9208a,a9212a,a9213a,a9214a,a9218a,a9219a,a9223a,a9224a,a9225a,a9229a,a9230a,a9234a,a9235a,a9236a,a9240a,a9241a,a9245a,a9246a,a9247a,a9251a,a9252a,a9256a,a9257a,a9258a,a9262a,a9263a,a9267a,a9268a,a9269a,a9273a,a9274a,a9278a,a9279a,a9280a,a9284a,a9285a,a9289a,a9290a,a9291a,a9295a,a9296a,a9300a,a9301a,a9302a,a9306a,a9307a,a9311a,a9312a,a9313a,a9317a,a9318a,a9322a,a9323a,a9324a,a9328a,a9329a,a9333a,a9334a,a9335a,a9339a,a9340a,a9344a,a9345a,a9346a,a9350a,a9351a,a9355a,a9356a,a9357a,a9361a,a9362a,a9366a,a9367a,a9368a,a9372a,a9373a,a9377a,a9378a,a9379a,a9383a,a9384a,a9387a,a9390a,a9391a,a9392a,a9396a,a9397a,a9401a,a9402a,a9403a,a9407a,a9408a,a9411a,a9414a,a9415a,a9416a,a9420a,a9421a,a9425a,a9426a,a9427a,a9431a,a9432a,a9435a,a9438a,a9439a,a9440a,a9444a,a9445a,a9449a,a9450a,a9451a,a9455a,a9456a,a9459a,a9462a,a9463a,a9464a,a9468a,a9469a,a9473a,a9474a,a9475a,a9479a,a9480a,a9483a,a9486a,a9487a,a9488a,a9492a,a9493a,a9497a,a9498a,a9499a,a9503a,a9504a,a9507a,a9510a,a9511a,a9512a,a9516a,a9517a,a9521a,a9522a,a9523a,a9527a,a9528a,a9531a,a9534a,a9535a,a9536a,a9540a,a9541a,a9545a,a9546a,a9547a,a9551a,a9552a,a9555a,a9558a,a9559a,a9560a: std_logic;
begin
A140 <=( a1312a ) or ( a875a );
a1a <=( a9560a and a9547a );
a2a <=( a9536a and a9523a );
a3a <=( a9512a and a9499a );
a4a <=( a9488a and a9475a );
a5a <=( a9464a and a9451a );
a6a <=( a9440a and a9427a );
a7a <=( a9416a and a9403a );
a8a <=( a9392a and a9379a );
a9a <=( a9368a and a9357a );
a10a <=( a9346a and a9335a );
a11a <=( a9324a and a9313a );
a12a <=( a9302a and a9291a );
a13a <=( a9280a and a9269a );
a14a <=( a9258a and a9247a );
a15a <=( a9236a and a9225a );
a16a <=( a9214a and a9203a );
a17a <=( a9192a and a9181a );
a18a <=( a9170a and a9159a );
a19a <=( a9148a and a9137a );
a20a <=( a9126a and a9115a );
a21a <=( a9104a and a9093a );
a22a <=( a9082a and a9071a );
a23a <=( a9060a and a9049a );
a24a <=( a9038a and a9027a );
a25a <=( a9016a and a9005a );
a26a <=( a8994a and a8983a );
a27a <=( a8972a and a8961a );
a28a <=( a8950a and a8939a );
a29a <=( a8928a and a8917a );
a30a <=( a8906a and a8895a );
a31a <=( a8884a and a8873a );
a32a <=( a8862a and a8851a );
a33a <=( a8840a and a8829a );
a34a <=( a8818a and a8807a );
a35a <=( a8796a and a8785a );
a36a <=( a8774a and a8763a );
a37a <=( a8752a and a8741a );
a38a <=( a8730a and a8719a );
a39a <=( a8708a and a8697a );
a40a <=( a8686a and a8675a );
a41a <=( a8664a and a8653a );
a42a <=( a8642a and a8631a );
a43a <=( a8620a and a8609a );
a44a <=( a8598a and a8587a );
a45a <=( a8576a and a8565a );
a46a <=( a8554a and a8543a );
a47a <=( a8532a and a8521a );
a48a <=( a8510a and a8499a );
a49a <=( a8488a and a8477a );
a50a <=( a8466a and a8455a );
a51a <=( a8444a and a8433a );
a52a <=( a8422a and a8411a );
a53a <=( a8400a and a8389a );
a54a <=( a8378a and a8367a );
a55a <=( a8356a and a8345a );
a56a <=( a8334a and a8323a );
a57a <=( a8312a and a8301a );
a58a <=( a8290a and a8279a );
a59a <=( a8268a and a8257a );
a60a <=( a8246a and a8235a );
a61a <=( a8224a and a8213a );
a62a <=( a8202a and a8191a );
a63a <=( a8180a and a8169a );
a64a <=( a8158a and a8147a );
a65a <=( a8136a and a8125a );
a66a <=( a8114a and a8103a );
a67a <=( a8092a and a8081a );
a68a <=( a8070a and a8059a );
a69a <=( a8048a and a8037a );
a70a <=( a8026a and a8015a );
a71a <=( a8004a and a7993a );
a72a <=( a7982a and a7971a );
a73a <=( a7960a and a7949a );
a74a <=( a7940a and a7929a );
a75a <=( a7920a and a7909a );
a76a <=( a7900a and a7889a );
a77a <=( a7880a and a7869a );
a78a <=( a7860a and a7849a );
a79a <=( a7840a and a7829a );
a80a <=( a7820a and a7809a );
a81a <=( a7800a and a7789a );
a82a <=( a7780a and a7769a );
a83a <=( a7760a and a7749a );
a84a <=( a7740a and a7729a );
a85a <=( a7720a and a7709a );
a86a <=( a7700a and a7689a );
a87a <=( a7680a and a7669a );
a88a <=( a7660a and a7649a );
a89a <=( a7640a and a7629a );
a90a <=( a7620a and a7609a );
a91a <=( a7600a and a7589a );
a92a <=( a7580a and a7569a );
a93a <=( a7560a and a7549a );
a94a <=( a7540a and a7529a );
a95a <=( a7520a and a7509a );
a96a <=( a7500a and a7489a );
a97a <=( a7480a and a7469a );
a98a <=( a7460a and a7449a );
a99a <=( a7440a and a7429a );
a100a <=( a7420a and a7409a );
a101a <=( a7400a and a7389a );
a102a <=( a7380a and a7369a );
a103a <=( a7360a and a7349a );
a104a <=( a7340a and a7329a );
a105a <=( a7320a and a7309a );
a106a <=( a7300a and a7289a );
a107a <=( a7280a and a7269a );
a108a <=( a7260a and a7249a );
a109a <=( a7240a and a7229a );
a110a <=( a7220a and a7209a );
a111a <=( a7200a and a7189a );
a112a <=( a7180a and a7169a );
a113a <=( a7160a and a7149a );
a114a <=( a7140a and a7129a );
a115a <=( a7120a and a7109a );
a116a <=( a7100a and a7089a );
a117a <=( a7080a and a7069a );
a118a <=( a7060a and a7049a );
a119a <=( a7040a and a7029a );
a120a <=( a7020a and a7009a );
a121a <=( a7000a and a6989a );
a122a <=( a6980a and a6969a );
a123a <=( a6960a and a6949a );
a124a <=( a6940a and a6929a );
a125a <=( a6920a and a6909a );
a126a <=( a6900a and a6889a );
a127a <=( a6880a and a6869a );
a128a <=( a6860a and a6849a );
a129a <=( a6840a and a6829a );
a130a <=( a6820a and a6809a );
a131a <=( a6800a and a6789a );
a132a <=( a6780a and a6769a );
a133a <=( a6760a and a6749a );
a134a <=( a6740a and a6729a );
a135a <=( a6720a and a6709a );
a136a <=( a6700a and a6689a );
a137a <=( a6680a and a6669a );
a138a <=( a6660a and a6649a );
a139a <=( a6640a and a6629a );
a140a <=( a6620a and a6609a );
a141a <=( a6600a and a6589a );
a142a <=( a6580a and a6569a );
a143a <=( a6560a and a6549a );
a144a <=( a6540a and a6529a );
a145a <=( a6520a and a6509a );
a146a <=( a6500a and a6489a );
a147a <=( a6480a and a6469a );
a148a <=( a6460a and a6449a );
a149a <=( a6440a and a6429a );
a150a <=( a6420a and a6409a );
a151a <=( a6400a and a6389a );
a152a <=( a6380a and a6369a );
a153a <=( a6360a and a6349a );
a154a <=( a6340a and a6329a );
a155a <=( a6320a and a6309a );
a156a <=( a6300a and a6289a );
a157a <=( a6280a and a6269a );
a158a <=( a6260a and a6249a );
a159a <=( a6240a and a6229a );
a160a <=( a6220a and a6209a );
a161a <=( a6200a and a6189a );
a162a <=( a6180a and a6169a );
a163a <=( a6160a and a6149a );
a164a <=( a6140a and a6129a );
a165a <=( a6120a and a6109a );
a166a <=( a6100a and a6089a );
a167a <=( a6080a and a6069a );
a168a <=( a6060a and a6049a );
a169a <=( a6040a and a6029a );
a170a <=( a6020a and a6009a );
a171a <=( a6000a and a5989a );
a172a <=( a5980a and a5969a );
a173a <=( a5960a and a5949a );
a174a <=( a5940a and a5929a );
a175a <=( a5920a and a5909a );
a176a <=( a5900a and a5889a );
a177a <=( a5880a and a5869a );
a178a <=( a5860a and a5849a );
a179a <=( a5840a and a5829a );
a180a <=( a5820a and a5809a );
a181a <=( a5800a and a5789a );
a182a <=( a5780a and a5769a );
a183a <=( a5760a and a5749a );
a184a <=( a5740a and a5729a );
a185a <=( a5720a and a5709a );
a186a <=( a5700a and a5689a );
a187a <=( a5680a and a5669a );
a188a <=( a5660a and a5649a );
a189a <=( a5640a and a5629a );
a190a <=( a5620a and a5609a );
a191a <=( a5600a and a5589a );
a192a <=( a5580a and a5569a );
a193a <=( a5560a and a5549a );
a194a <=( a5540a and a5529a );
a195a <=( a5520a and a5509a );
a196a <=( a5500a and a5489a );
a197a <=( a5480a and a5469a );
a198a <=( a5460a and a5449a );
a199a <=( a5440a and a5429a );
a200a <=( a5420a and a5409a );
a201a <=( a5400a and a5389a );
a202a <=( a5380a and a5369a );
a203a <=( a5360a and a5349a );
a204a <=( a5340a and a5329a );
a205a <=( a5320a and a5309a );
a206a <=( a5300a and a5289a );
a207a <=( a5280a and a5269a );
a208a <=( a5260a and a5249a );
a209a <=( a5240a and a5229a );
a210a <=( a5220a and a5209a );
a211a <=( a5200a and a5189a );
a212a <=( a5180a and a5169a );
a213a <=( a5160a and a5149a );
a214a <=( a5140a and a5129a );
a215a <=( a5120a and a5109a );
a216a <=( a5100a and a5089a );
a217a <=( a5080a and a5069a );
a218a <=( a5060a and a5049a );
a219a <=( a5040a and a5029a );
a220a <=( a5020a and a5009a );
a221a <=( a5000a and a4989a );
a222a <=( a4980a and a4969a );
a223a <=( a4960a and a4949a );
a224a <=( a4940a and a4929a );
a225a <=( a4920a and a4909a );
a226a <=( a4900a and a4889a );
a227a <=( a4880a and a4869a );
a228a <=( a4860a and a4849a );
a229a <=( a4840a and a4829a );
a230a <=( a4820a and a4809a );
a231a <=( a4800a and a4789a );
a232a <=( a4780a and a4769a );
a233a <=( a4760a and a4751a );
a234a <=( a4742a and a4733a );
a235a <=( a4724a and a4715a );
a236a <=( a4706a and a4697a );
a237a <=( a4688a and a4679a );
a238a <=( a4670a and a4661a );
a239a <=( a4652a and a4643a );
a240a <=( a4634a and a4625a );
a241a <=( a4616a and a4607a );
a242a <=( a4598a and a4589a );
a243a <=( a4580a and a4571a );
a244a <=( a4562a and a4553a );
a245a <=( a4544a and a4535a );
a246a <=( a4526a and a4517a );
a247a <=( a4508a and a4499a );
a248a <=( a4490a and a4481a );
a249a <=( a4472a and a4463a );
a250a <=( a4454a and a4445a );
a251a <=( a4436a and a4427a );
a252a <=( a4418a and a4409a );
a253a <=( a4400a and a4391a );
a254a <=( a4382a and a4373a );
a255a <=( a4364a and a4355a );
a256a <=( a4346a and a4337a );
a257a <=( a4328a and a4319a );
a258a <=( a4310a and a4301a );
a259a <=( a4292a and a4283a );
a260a <=( a4274a and a4265a );
a261a <=( a4256a and a4247a );
a262a <=( a4238a and a4229a );
a263a <=( a4220a and a4211a );
a264a <=( a4202a and a4193a );
a265a <=( a4184a and a4175a );
a266a <=( a4166a and a4157a );
a267a <=( a4148a and a4139a );
a268a <=( a4130a and a4121a );
a269a <=( a4112a and a4103a );
a270a <=( a4094a and a4085a );
a271a <=( a4076a and a4067a );
a272a <=( a4058a and a4049a );
a273a <=( a4040a and a4031a );
a274a <=( a4022a and a4013a );
a275a <=( a4004a and a3995a );
a276a <=( a3986a and a3977a );
a277a <=( a3968a and a3959a );
a278a <=( a3950a and a3941a );
a279a <=( a3932a and a3923a );
a280a <=( a3914a and a3905a );
a281a <=( a3896a and a3887a );
a282a <=( a3878a and a3869a );
a283a <=( a3860a and a3851a );
a284a <=( a3842a and a3833a );
a285a <=( a3824a and a3815a );
a286a <=( a3806a and a3797a );
a287a <=( a3788a and a3779a );
a288a <=( a3770a and a3761a );
a289a <=( a3752a and a3743a );
a290a <=( a3734a and a3725a );
a291a <=( a3716a and a3707a );
a292a <=( a3698a and a3689a );
a293a <=( a3680a and a3671a );
a294a <=( a3662a and a3653a );
a295a <=( a3644a and a3635a );
a296a <=( a3626a and a3617a );
a297a <=( a3608a and a3599a );
a298a <=( a3590a and a3581a );
a299a <=( a3572a and a3563a );
a300a <=( a3554a and a3545a );
a301a <=( a3536a and a3527a );
a302a <=( a3518a and a3509a );
a303a <=( a3500a and a3491a );
a304a <=( a3482a and a3473a );
a305a <=( a3464a and a3455a );
a306a <=( a3446a and a3437a );
a307a <=( a3428a and a3419a );
a308a <=( a3410a and a3401a );
a309a <=( a3392a and a3383a );
a310a <=( a3374a and a3365a );
a311a <=( a3356a and a3347a );
a312a <=( a3338a and a3329a );
a313a <=( a3320a and a3311a );
a314a <=( a3302a and a3293a );
a315a <=( a3284a and a3275a );
a316a <=( a3266a and a3257a );
a317a <=( a3248a and a3239a );
a318a <=( a3230a and a3221a );
a319a <=( a3212a and a3203a );
a320a <=( a3194a and a3185a );
a321a <=( a3176a and a3167a );
a322a <=( a3158a and a3149a );
a323a <=( a3140a and a3131a );
a324a <=( a3122a and a3113a );
a325a <=( a3104a and a3095a );
a326a <=( a3086a and a3077a );
a327a <=( a3068a and a3059a );
a328a <=( a3050a and a3041a );
a329a <=( a3032a and a3023a );
a330a <=( a3014a and a3005a );
a331a <=( a2996a and a2987a );
a332a <=( a2978a and a2969a );
a333a <=( a2960a and a2951a );
a334a <=( a2942a and a2933a );
a335a <=( a2924a and a2915a );
a336a <=( a2906a and a2897a );
a337a <=( a2888a and a2879a );
a338a <=( a2870a and a2861a );
a339a <=( a2852a and a2843a );
a340a <=( a2834a and a2825a );
a341a <=( a2816a and a2807a );
a342a <=( a2798a and a2789a );
a343a <=( a2780a and a2771a );
a344a <=( a2762a and a2753a );
a345a <=( a2744a and a2735a );
a346a <=( a2726a and a2717a );
a347a <=( a2708a and a2699a );
a348a <=( a2690a and a2681a );
a349a <=( a2672a and a2663a );
a350a <=( a2654a and a2645a );
a351a <=( a2636a and a2627a );
a352a <=( a2618a and a2609a );
a353a <=( a2600a and a2591a );
a354a <=( a2582a and a2573a );
a355a <=( a2564a and a2555a );
a356a <=( a2546a and a2537a );
a357a <=( a2528a and a2519a );
a358a <=( a2510a and a2501a );
a359a <=( a2492a and a2483a );
a360a <=( a2474a and a2465a );
a361a <=( a2456a and a2447a );
a362a <=( a2438a and a2429a );
a363a <=( a2420a and a2411a );
a364a <=( a2402a and a2393a );
a365a <=( a2384a and a2375a );
a366a <=( a2366a and a2357a );
a367a <=( a2348a and a2339a );
a368a <=( a2330a and a2321a );
a369a <=( a2312a and a2303a );
a370a <=( a2296a and a2287a );
a371a <=( a2280a and a2271a );
a372a <=( a2264a and a2255a );
a373a <=( a2248a and a2239a );
a374a <=( a2232a and a2223a );
a375a <=( a2216a and a2207a );
a376a <=( a2200a and a2191a );
a377a <=( a2184a and a2175a );
a378a <=( a2168a and a2159a );
a379a <=( a2152a and a2143a );
a380a <=( a2136a and a2127a );
a381a <=( a2120a and a2111a );
a382a <=( a2104a and a2095a );
a383a <=( a2088a and a2079a );
a384a <=( a2072a and a2063a );
a385a <=( a2056a and a2047a );
a386a <=( a2040a and a2031a );
a387a <=( a2024a and a2015a );
a388a <=( a2008a and a1999a );
a389a <=( a1992a and a1983a );
a390a <=( a1976a and a1967a );
a391a <=( a1960a and a1951a );
a392a <=( a1944a and a1935a );
a393a <=( a1928a and a1919a );
a394a <=( a1912a and a1903a );
a395a <=( a1896a and a1887a );
a396a <=( a1880a and a1871a );
a397a <=( a1864a and a1855a );
a398a <=( a1848a and a1839a );
a399a <=( a1832a and a1823a );
a400a <=( a1816a and a1807a );
a401a <=( a1800a and a1793a );
a402a <=( a1786a and a1779a );
a403a <=( a1772a and a1765a );
a404a <=( a1758a and a1751a );
a405a <=( a1744a and a1737a );
a406a <=( a1730a and a1723a );
a407a <=( a1716a and a1709a );
a408a <=( a1702a and a1695a );
a409a <=( a1688a and a1681a );
a410a <=( a1674a and a1667a );
a411a <=( a1660a and a1653a );
a412a <=( a1646a and a1639a );
a413a <=( a1632a and a1625a );
a414a <=( a1618a and a1611a );
a415a <=( a1604a and a1597a );
a416a <=( a1590a and a1583a );
a417a <=( a1576a and a1569a );
a418a <=( a1562a and a1555a );
a419a <=( a1548a and a1541a );
a420a <=( a1534a and a1527a );
a421a <=( a1520a and a1513a );
a422a <=( a1506a and a1499a );
a423a <=( a1492a and a1485a );
a424a <=( a1478a and a1471a );
a425a <=( a1464a and a1457a );
a426a <=( a1450a and a1443a );
a427a <=( a1436a and a1429a );
a428a <=( a1422a and a1415a );
a429a <=( a1408a and a1401a );
a430a <=( a1394a and a1387a );
a431a <=( a1380a and a1373a );
a432a <=( a1366a and a1359a );
a433a <=( a1352a and a1347a );
a434a <=( a1344a and a1339a );
a435a <=( a1336a and a1333a );
a436a <=( a1330a and a1327a );
a437a <=( a1324a and a1321a );
a438a <=( a1318a and a1315a );
a442a <=( a436a ) or ( a437a );
a443a <=( a438a ) or ( a442a );
a447a <=( a433a ) or ( a434a );
a448a <=( a435a ) or ( a447a );
a449a <=( a448a ) or ( a443a );
a453a <=( a430a ) or ( a431a );
a454a <=( a432a ) or ( a453a );
a457a <=( a428a ) or ( a429a );
a460a <=( a426a ) or ( a427a );
a461a <=( a460a ) or ( a457a );
a462a <=( a461a ) or ( a454a );
a463a <=( a462a ) or ( a449a );
a467a <=( a423a ) or ( a424a );
a468a <=( a425a ) or ( a467a );
a471a <=( a421a ) or ( a422a );
a474a <=( a419a ) or ( a420a );
a475a <=( a474a ) or ( a471a );
a476a <=( a475a ) or ( a468a );
a480a <=( a416a ) or ( a417a );
a481a <=( a418a ) or ( a480a );
a484a <=( a414a ) or ( a415a );
a487a <=( a412a ) or ( a413a );
a488a <=( a487a ) or ( a484a );
a489a <=( a488a ) or ( a481a );
a490a <=( a489a ) or ( a476a );
a491a <=( a490a ) or ( a463a );
a495a <=( a409a ) or ( a410a );
a496a <=( a411a ) or ( a495a );
a500a <=( a406a ) or ( a407a );
a501a <=( a408a ) or ( a500a );
a502a <=( a501a ) or ( a496a );
a506a <=( a403a ) or ( a404a );
a507a <=( a405a ) or ( a506a );
a510a <=( a401a ) or ( a402a );
a513a <=( a399a ) or ( a400a );
a514a <=( a513a ) or ( a510a );
a515a <=( a514a ) or ( a507a );
a516a <=( a515a ) or ( a502a );
a520a <=( a396a ) or ( a397a );
a521a <=( a398a ) or ( a520a );
a524a <=( a394a ) or ( a395a );
a527a <=( a392a ) or ( a393a );
a528a <=( a527a ) or ( a524a );
a529a <=( a528a ) or ( a521a );
a533a <=( a389a ) or ( a390a );
a534a <=( a391a ) or ( a533a );
a537a <=( a387a ) or ( a388a );
a540a <=( a385a ) or ( a386a );
a541a <=( a540a ) or ( a537a );
a542a <=( a541a ) or ( a534a );
a543a <=( a542a ) or ( a529a );
a544a <=( a543a ) or ( a516a );
a545a <=( a544a ) or ( a491a );
a549a <=( a382a ) or ( a383a );
a550a <=( a384a ) or ( a549a );
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a555a <=( a381a ) or ( a554a );
a556a <=( a555a ) or ( a550a );
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a564a <=( a374a ) or ( a375a );
a567a <=( a372a ) or ( a373a );
a568a <=( a567a ) or ( a564a );
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a575a <=( a371a ) or ( a574a );
a578a <=( a367a ) or ( a368a );
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a582a <=( a581a ) or ( a578a );
a583a <=( a582a ) or ( a575a );
a587a <=( a362a ) or ( a363a );
a588a <=( a364a ) or ( a587a );
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a594a <=( a358a ) or ( a359a );
a595a <=( a594a ) or ( a591a );
a596a <=( a595a ) or ( a588a );
a597a <=( a596a ) or ( a583a );
a598a <=( a597a ) or ( a570a );
a602a <=( a355a ) or ( a356a );
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a610a <=( a609a ) or ( a606a );
a611a <=( a610a ) or ( a603a );
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a616a <=( a350a ) or ( a615a );
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a624a <=( a623a ) or ( a616a );
a625a <=( a624a ) or ( a611a );
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a630a <=( a343a ) or ( a629a );
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a636a <=( a337a ) or ( a338a );
a637a <=( a636a ) or ( a633a );
a638a <=( a637a ) or ( a630a );
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a643a <=( a336a ) or ( a642a );
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a650a <=( a649a ) or ( a646a );
a651a <=( a650a ) or ( a643a );
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a653a <=( a652a ) or ( a625a );
a654a <=( a653a ) or ( a598a );
a655a <=( a654a ) or ( a545a );
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a660a <=( a329a ) or ( a659a );
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a665a <=( a326a ) or ( a664a );
a666a <=( a665a ) or ( a660a );
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a671a <=( a323a ) or ( a670a );
a674a <=( a319a ) or ( a320a );
a677a <=( a317a ) or ( a318a );
a678a <=( a677a ) or ( a674a );
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a680a <=( a679a ) or ( a666a );
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a685a <=( a316a ) or ( a684a );
a688a <=( a312a ) or ( a313a );
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a692a <=( a691a ) or ( a688a );
a693a <=( a692a ) or ( a685a );
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a698a <=( a309a ) or ( a697a );
a701a <=( a305a ) or ( a306a );
a704a <=( a303a ) or ( a304a );
a705a <=( a704a ) or ( a701a );
a706a <=( a705a ) or ( a698a );
a707a <=( a706a ) or ( a693a );
a708a <=( a707a ) or ( a680a );
a712a <=( a300a ) or ( a301a );
a713a <=( a302a ) or ( a712a );
a716a <=( a298a ) or ( a299a );
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a720a <=( a719a ) or ( a716a );
a721a <=( a720a ) or ( a713a );
a725a <=( a293a ) or ( a294a );
a726a <=( a295a ) or ( a725a );
a729a <=( a291a ) or ( a292a );
a732a <=( a289a ) or ( a290a );
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a734a <=( a733a ) or ( a726a );
a735a <=( a734a ) or ( a721a );
a739a <=( a286a ) or ( a287a );
a740a <=( a288a ) or ( a739a );
a743a <=( a284a ) or ( a285a );
a746a <=( a282a ) or ( a283a );
a747a <=( a746a ) or ( a743a );
a748a <=( a747a ) or ( a740a );
a752a <=( a279a ) or ( a280a );
a753a <=( a281a ) or ( a752a );
a756a <=( a277a ) or ( a278a );
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a760a <=( a759a ) or ( a756a );
a761a <=( a760a ) or ( a753a );
a762a <=( a761a ) or ( a748a );
a763a <=( a762a ) or ( a735a );
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a768a <=( a272a ) or ( a273a );
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a773a <=( a269a ) or ( a270a );
a774a <=( a271a ) or ( a773a );
a775a <=( a774a ) or ( a769a );
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a780a <=( a268a ) or ( a779a );
a783a <=( a264a ) or ( a265a );
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a787a <=( a786a ) or ( a783a );
a788a <=( a787a ) or ( a780a );
a789a <=( a788a ) or ( a775a );
a793a <=( a259a ) or ( a260a );
a794a <=( a261a ) or ( a793a );
a797a <=( a257a ) or ( a258a );
a800a <=( a255a ) or ( a256a );
a801a <=( a800a ) or ( a797a );
a802a <=( a801a ) or ( a794a );
a806a <=( a252a ) or ( a253a );
a807a <=( a254a ) or ( a806a );
a810a <=( a250a ) or ( a251a );
a813a <=( a248a ) or ( a249a );
a814a <=( a813a ) or ( a810a );
a815a <=( a814a ) or ( a807a );
a816a <=( a815a ) or ( a802a );
a817a <=( a816a ) or ( a789a );
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a822a <=( a247a ) or ( a821a );
a825a <=( a243a ) or ( a244a );
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a829a <=( a828a ) or ( a825a );
a830a <=( a829a ) or ( a822a );
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a835a <=( a240a ) or ( a834a );
a838a <=( a236a ) or ( a237a );
a841a <=( a234a ) or ( a235a );
a842a <=( a841a ) or ( a838a );
a843a <=( a842a ) or ( a835a );
a844a <=( a843a ) or ( a830a );
a848a <=( a231a ) or ( a232a );
a849a <=( a233a ) or ( a848a );
a852a <=( a229a ) or ( a230a );
a855a <=( a227a ) or ( a228a );
a856a <=( a855a ) or ( a852a );
a857a <=( a856a ) or ( a849a );
a861a <=( a224a ) or ( a225a );
a862a <=( a226a ) or ( a861a );
a865a <=( a222a ) or ( a223a );
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a869a <=( a868a ) or ( a865a );
a870a <=( a869a ) or ( a862a );
a871a <=( a870a ) or ( a857a );
a872a <=( a871a ) or ( a844a );
a873a <=( a872a ) or ( a817a );
a874a <=( a873a ) or ( a764a );
a875a <=( a874a ) or ( a655a );
a879a <=( a217a ) or ( a218a );
a880a <=( a219a ) or ( a879a );
a884a <=( a214a ) or ( a215a );
a885a <=( a216a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
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a891a <=( a213a ) or ( a890a );
a894a <=( a209a ) or ( a210a );
a897a <=( a207a ) or ( a208a );
a898a <=( a897a ) or ( a894a );
a899a <=( a898a ) or ( a891a );
a900a <=( a899a ) or ( a886a );
a904a <=( a204a ) or ( a205a );
a905a <=( a206a ) or ( a904a );
a908a <=( a202a ) or ( a203a );
a911a <=( a200a ) or ( a201a );
a912a <=( a911a ) or ( a908a );
a913a <=( a912a ) or ( a905a );
a917a <=( a197a ) or ( a198a );
a918a <=( a199a ) or ( a917a );
a921a <=( a195a ) or ( a196a );
a924a <=( a193a ) or ( a194a );
a925a <=( a924a ) or ( a921a );
a926a <=( a925a ) or ( a918a );
a927a <=( a926a ) or ( a913a );
a928a <=( a927a ) or ( a900a );
a932a <=( a190a ) or ( a191a );
a933a <=( a192a ) or ( a932a );
a937a <=( a187a ) or ( a188a );
a938a <=( a189a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a184a ) or ( a185a );
a944a <=( a186a ) or ( a943a );
a947a <=( a182a ) or ( a183a );
a950a <=( a180a ) or ( a181a );
a951a <=( a950a ) or ( a947a );
a952a <=( a951a ) or ( a944a );
a953a <=( a952a ) or ( a939a );
a957a <=( a177a ) or ( a178a );
a958a <=( a179a ) or ( a957a );
a961a <=( a175a ) or ( a176a );
a964a <=( a173a ) or ( a174a );
a965a <=( a964a ) or ( a961a );
a966a <=( a965a ) or ( a958a );
a970a <=( a170a ) or ( a171a );
a971a <=( a172a ) or ( a970a );
a974a <=( a168a ) or ( a169a );
a977a <=( a166a ) or ( a167a );
a978a <=( a977a ) or ( a974a );
a979a <=( a978a ) or ( a971a );
a980a <=( a979a ) or ( a966a );
a981a <=( a980a ) or ( a953a );
a982a <=( a981a ) or ( a928a );
a986a <=( a163a ) or ( a164a );
a987a <=( a165a ) or ( a986a );
a991a <=( a160a ) or ( a161a );
a992a <=( a162a ) or ( a991a );
a993a <=( a992a ) or ( a987a );
a997a <=( a157a ) or ( a158a );
a998a <=( a159a ) or ( a997a );
a1001a <=( a155a ) or ( a156a );
a1004a <=( a153a ) or ( a154a );
a1005a <=( a1004a ) or ( a1001a );
a1006a <=( a1005a ) or ( a998a );
a1007a <=( a1006a ) or ( a993a );
a1011a <=( a150a ) or ( a151a );
a1012a <=( a152a ) or ( a1011a );
a1015a <=( a148a ) or ( a149a );
a1018a <=( a146a ) or ( a147a );
a1019a <=( a1018a ) or ( a1015a );
a1020a <=( a1019a ) or ( a1012a );
a1024a <=( a143a ) or ( a144a );
a1025a <=( a145a ) or ( a1024a );
a1028a <=( a141a ) or ( a142a );
a1031a <=( a139a ) or ( a140a );
a1032a <=( a1031a ) or ( a1028a );
a1033a <=( a1032a ) or ( a1025a );
a1034a <=( a1033a ) or ( a1020a );
a1035a <=( a1034a ) or ( a1007a );
a1039a <=( a136a ) or ( a137a );
a1040a <=( a138a ) or ( a1039a );
a1043a <=( a134a ) or ( a135a );
a1046a <=( a132a ) or ( a133a );
a1047a <=( a1046a ) or ( a1043a );
a1048a <=( a1047a ) or ( a1040a );
a1052a <=( a129a ) or ( a130a );
a1053a <=( a131a ) or ( a1052a );
a1056a <=( a127a ) or ( a128a );
a1059a <=( a125a ) or ( a126a );
a1060a <=( a1059a ) or ( a1056a );
a1061a <=( a1060a ) or ( a1053a );
a1062a <=( a1061a ) or ( a1048a );
a1066a <=( a122a ) or ( a123a );
a1067a <=( a124a ) or ( a1066a );
a1070a <=( a120a ) or ( a121a );
a1073a <=( a118a ) or ( a119a );
a1074a <=( a1073a ) or ( a1070a );
a1075a <=( a1074a ) or ( a1067a );
a1079a <=( a115a ) or ( a116a );
a1080a <=( a117a ) or ( a1079a );
a1083a <=( a113a ) or ( a114a );
a1086a <=( a111a ) or ( a112a );
a1087a <=( a1086a ) or ( a1083a );
a1088a <=( a1087a ) or ( a1080a );
a1089a <=( a1088a ) or ( a1075a );
a1090a <=( a1089a ) or ( a1062a );
a1091a <=( a1090a ) or ( a1035a );
a1092a <=( a1091a ) or ( a982a );
a1096a <=( a108a ) or ( a109a );
a1097a <=( a110a ) or ( a1096a );
a1101a <=( a105a ) or ( a106a );
a1102a <=( a107a ) or ( a1101a );
a1103a <=( a1102a ) or ( a1097a );
a1107a <=( a102a ) or ( a103a );
a1108a <=( a104a ) or ( a1107a );
a1111a <=( a100a ) or ( a101a );
a1114a <=( a98a ) or ( a99a );
a1115a <=( a1114a ) or ( a1111a );
a1116a <=( a1115a ) or ( a1108a );
a1117a <=( a1116a ) or ( a1103a );
a1121a <=( a95a ) or ( a96a );
a1122a <=( a97a ) or ( a1121a );
a1125a <=( a93a ) or ( a94a );
a1128a <=( a91a ) or ( a92a );
a1129a <=( a1128a ) or ( a1125a );
a1130a <=( a1129a ) or ( a1122a );
a1134a <=( a88a ) or ( a89a );
a1135a <=( a90a ) or ( a1134a );
a1138a <=( a86a ) or ( a87a );
a1141a <=( a84a ) or ( a85a );
a1142a <=( a1141a ) or ( a1138a );
a1143a <=( a1142a ) or ( a1135a );
a1144a <=( a1143a ) or ( a1130a );
a1145a <=( a1144a ) or ( a1117a );
a1149a <=( a81a ) or ( a82a );
a1150a <=( a83a ) or ( a1149a );
a1153a <=( a79a ) or ( a80a );
a1156a <=( a77a ) or ( a78a );
a1157a <=( a1156a ) or ( a1153a );
a1158a <=( a1157a ) or ( a1150a );
a1162a <=( a74a ) or ( a75a );
a1163a <=( a76a ) or ( a1162a );
a1166a <=( a72a ) or ( a73a );
a1169a <=( a70a ) or ( a71a );
a1170a <=( a1169a ) or ( a1166a );
a1171a <=( a1170a ) or ( a1163a );
a1172a <=( a1171a ) or ( a1158a );
a1176a <=( a67a ) or ( a68a );
a1177a <=( a69a ) or ( a1176a );
a1180a <=( a65a ) or ( a66a );
a1183a <=( a63a ) or ( a64a );
a1184a <=( a1183a ) or ( a1180a );
a1185a <=( a1184a ) or ( a1177a );
a1189a <=( a60a ) or ( a61a );
a1190a <=( a62a ) or ( a1189a );
a1193a <=( a58a ) or ( a59a );
a1196a <=( a56a ) or ( a57a );
a1197a <=( a1196a ) or ( a1193a );
a1198a <=( a1197a ) or ( a1190a );
a1199a <=( a1198a ) or ( a1185a );
a1200a <=( a1199a ) or ( a1172a );
a1201a <=( a1200a ) or ( a1145a );
a1205a <=( a53a ) or ( a54a );
a1206a <=( a55a ) or ( a1205a );
a1210a <=( a50a ) or ( a51a );
a1211a <=( a52a ) or ( a1210a );
a1212a <=( a1211a ) or ( a1206a );
a1216a <=( a47a ) or ( a48a );
a1217a <=( a49a ) or ( a1216a );
a1220a <=( a45a ) or ( a46a );
a1223a <=( a43a ) or ( a44a );
a1224a <=( a1223a ) or ( a1220a );
a1225a <=( a1224a ) or ( a1217a );
a1226a <=( a1225a ) or ( a1212a );
a1230a <=( a40a ) or ( a41a );
a1231a <=( a42a ) or ( a1230a );
a1234a <=( a38a ) or ( a39a );
a1237a <=( a36a ) or ( a37a );
a1238a <=( a1237a ) or ( a1234a );
a1239a <=( a1238a ) or ( a1231a );
a1243a <=( a33a ) or ( a34a );
a1244a <=( a35a ) or ( a1243a );
a1247a <=( a31a ) or ( a32a );
a1250a <=( a29a ) or ( a30a );
a1251a <=( a1250a ) or ( a1247a );
a1252a <=( a1251a ) or ( a1244a );
a1253a <=( a1252a ) or ( a1239a );
a1254a <=( a1253a ) or ( a1226a );
a1258a <=( a26a ) or ( a27a );
a1259a <=( a28a ) or ( a1258a );
a1262a <=( a24a ) or ( a25a );
a1265a <=( a22a ) or ( a23a );
a1266a <=( a1265a ) or ( a1262a );
a1267a <=( a1266a ) or ( a1259a );
a1271a <=( a19a ) or ( a20a );
a1272a <=( a21a ) or ( a1271a );
a1275a <=( a17a ) or ( a18a );
a1278a <=( a15a ) or ( a16a );
a1279a <=( a1278a ) or ( a1275a );
a1280a <=( a1279a ) or ( a1272a );
a1281a <=( a1280a ) or ( a1267a );
a1285a <=( a12a ) or ( a13a );
a1286a <=( a14a ) or ( a1285a );
a1289a <=( a10a ) or ( a11a );
a1292a <=( a8a ) or ( a9a );
a1293a <=( a1292a ) or ( a1289a );
a1294a <=( a1293a ) or ( a1286a );
a1298a <=( a5a ) or ( a6a );
a1299a <=( a7a ) or ( a1298a );
a1302a <=( a3a ) or ( a4a );
a1305a <=( a1a ) or ( a2a );
a1306a <=( a1305a ) or ( a1302a );
a1307a <=( a1306a ) or ( a1299a );
a1308a <=( a1307a ) or ( a1294a );
a1309a <=( a1308a ) or ( a1281a );
a1310a <=( a1309a ) or ( a1254a );
a1311a <=( a1310a ) or ( a1201a );
a1312a <=( a1311a ) or ( a1092a );
a1315a <=( A266 and (not A265) );
a1318a <=( A268 and A267 );
a1321a <=( A266 and (not A265) );
a1324a <=( A269 and A267 );
a1327a <=( (not A266) and A265 );
a1330a <=( A268 and A267 );
a1333a <=( (not A266) and A265 );
a1336a <=( A269 and A267 );
a1339a <=( A266 and (not A265) );
a1343a <=( (not A269) and (not A268) );
a1344a <=( (not A267) and a1343a );
a1347a <=( (not A266) and A265 );
a1351a <=( (not A269) and (not A268) );
a1352a <=( (not A267) and a1351a );
a1355a <=( A200 and (not A199) );
a1358a <=( A202 and A201 );
a1359a <=( a1358a and a1355a );
a1362a <=( A233 and (not A232) );
a1365a <=( A235 and A234 );
a1366a <=( a1365a and a1362a );
a1369a <=( A200 and (not A199) );
a1372a <=( A202 and A201 );
a1373a <=( a1372a and a1369a );
a1376a <=( A233 and (not A232) );
a1379a <=( A236 and A234 );
a1380a <=( a1379a and a1376a );
a1383a <=( A200 and (not A199) );
a1386a <=( A202 and A201 );
a1387a <=( a1386a and a1383a );
a1390a <=( (not A233) and A232 );
a1393a <=( A235 and A234 );
a1394a <=( a1393a and a1390a );
a1397a <=( A200 and (not A199) );
a1400a <=( A202 and A201 );
a1401a <=( a1400a and a1397a );
a1404a <=( (not A233) and A232 );
a1407a <=( A236 and A234 );
a1408a <=( a1407a and a1404a );
a1411a <=( A200 and (not A199) );
a1414a <=( A203 and A201 );
a1415a <=( a1414a and a1411a );
a1418a <=( A233 and (not A232) );
a1421a <=( A235 and A234 );
a1422a <=( a1421a and a1418a );
a1425a <=( A200 and (not A199) );
a1428a <=( A203 and A201 );
a1429a <=( a1428a and a1425a );
a1432a <=( A233 and (not A232) );
a1435a <=( A236 and A234 );
a1436a <=( a1435a and a1432a );
a1439a <=( A200 and (not A199) );
a1442a <=( A203 and A201 );
a1443a <=( a1442a and a1439a );
a1446a <=( (not A233) and A232 );
a1449a <=( A235 and A234 );
a1450a <=( a1449a and a1446a );
a1453a <=( A200 and (not A199) );
a1456a <=( A203 and A201 );
a1457a <=( a1456a and a1453a );
a1460a <=( (not A233) and A232 );
a1463a <=( A236 and A234 );
a1464a <=( a1463a and a1460a );
a1467a <=( (not A200) and A199 );
a1470a <=( A202 and A201 );
a1471a <=( a1470a and a1467a );
a1474a <=( A233 and (not A232) );
a1477a <=( A235 and A234 );
a1478a <=( a1477a and a1474a );
a1481a <=( (not A200) and A199 );
a1484a <=( A202 and A201 );
a1485a <=( a1484a and a1481a );
a1488a <=( A233 and (not A232) );
a1491a <=( A236 and A234 );
a1492a <=( a1491a and a1488a );
a1495a <=( (not A200) and A199 );
a1498a <=( A202 and A201 );
a1499a <=( a1498a and a1495a );
a1502a <=( (not A233) and A232 );
a1505a <=( A235 and A234 );
a1506a <=( a1505a and a1502a );
a1509a <=( (not A200) and A199 );
a1512a <=( A202 and A201 );
a1513a <=( a1512a and a1509a );
a1516a <=( (not A233) and A232 );
a1519a <=( A236 and A234 );
a1520a <=( a1519a and a1516a );
a1523a <=( (not A200) and A199 );
a1526a <=( A203 and A201 );
a1527a <=( a1526a and a1523a );
a1530a <=( A233 and (not A232) );
a1533a <=( A235 and A234 );
a1534a <=( a1533a and a1530a );
a1537a <=( (not A200) and A199 );
a1540a <=( A203 and A201 );
a1541a <=( a1540a and a1537a );
a1544a <=( A233 and (not A232) );
a1547a <=( A236 and A234 );
a1548a <=( a1547a and a1544a );
a1551a <=( (not A200) and A199 );
a1554a <=( A203 and A201 );
a1555a <=( a1554a and a1551a );
a1558a <=( (not A233) and A232 );
a1561a <=( A235 and A234 );
a1562a <=( a1561a and a1558a );
a1565a <=( (not A200) and A199 );
a1568a <=( A203 and A201 );
a1569a <=( a1568a and a1565a );
a1572a <=( (not A233) and A232 );
a1575a <=( A236 and A234 );
a1576a <=( a1575a and a1572a );
a1579a <=( A168 and (not A170) );
a1582a <=( (not A166) and A167 );
a1583a <=( a1582a and a1579a );
a1586a <=( A233 and (not A232) );
a1589a <=( A235 and A234 );
a1590a <=( a1589a and a1586a );
a1593a <=( A168 and (not A170) );
a1596a <=( (not A166) and A167 );
a1597a <=( a1596a and a1593a );
a1600a <=( A233 and (not A232) );
a1603a <=( A236 and A234 );
a1604a <=( a1603a and a1600a );
a1607a <=( A168 and (not A170) );
a1610a <=( (not A166) and A167 );
a1611a <=( a1610a and a1607a );
a1614a <=( (not A233) and A232 );
a1617a <=( A235 and A234 );
a1618a <=( a1617a and a1614a );
a1621a <=( A168 and (not A170) );
a1624a <=( (not A166) and A167 );
a1625a <=( a1624a and a1621a );
a1628a <=( (not A233) and A232 );
a1631a <=( A236 and A234 );
a1632a <=( a1631a and a1628a );
a1635a <=( A168 and (not A170) );
a1638a <=( A166 and (not A167) );
a1639a <=( a1638a and a1635a );
a1642a <=( A233 and (not A232) );
a1645a <=( A235 and A234 );
a1646a <=( a1645a and a1642a );
a1649a <=( A168 and (not A170) );
a1652a <=( A166 and (not A167) );
a1653a <=( a1652a and a1649a );
a1656a <=( A233 and (not A232) );
a1659a <=( A236 and A234 );
a1660a <=( a1659a and a1656a );
a1663a <=( A168 and (not A170) );
a1666a <=( A166 and (not A167) );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A233) and A232 );
a1673a <=( A235 and A234 );
a1674a <=( a1673a and a1670a );
a1677a <=( A168 and (not A170) );
a1680a <=( A166 and (not A167) );
a1681a <=( a1680a and a1677a );
a1684a <=( (not A233) and A232 );
a1687a <=( A236 and A234 );
a1688a <=( a1687a and a1684a );
a1691a <=( A168 and A169 );
a1694a <=( (not A166) and A167 );
a1695a <=( a1694a and a1691a );
a1698a <=( A233 and (not A232) );
a1701a <=( A235 and A234 );
a1702a <=( a1701a and a1698a );
a1705a <=( A168 and A169 );
a1708a <=( (not A166) and A167 );
a1709a <=( a1708a and a1705a );
a1712a <=( A233 and (not A232) );
a1715a <=( A236 and A234 );
a1716a <=( a1715a and a1712a );
a1719a <=( A168 and A169 );
a1722a <=( (not A166) and A167 );
a1723a <=( a1722a and a1719a );
a1726a <=( (not A233) and A232 );
a1729a <=( A235 and A234 );
a1730a <=( a1729a and a1726a );
a1733a <=( A168 and A169 );
a1736a <=( (not A166) and A167 );
a1737a <=( a1736a and a1733a );
a1740a <=( (not A233) and A232 );
a1743a <=( A236 and A234 );
a1744a <=( a1743a and a1740a );
a1747a <=( A168 and A169 );
a1750a <=( A166 and (not A167) );
a1751a <=( a1750a and a1747a );
a1754a <=( A233 and (not A232) );
a1757a <=( A235 and A234 );
a1758a <=( a1757a and a1754a );
a1761a <=( A168 and A169 );
a1764a <=( A166 and (not A167) );
a1765a <=( a1764a and a1761a );
a1768a <=( A233 and (not A232) );
a1771a <=( A236 and A234 );
a1772a <=( a1771a and a1768a );
a1775a <=( A168 and A169 );
a1778a <=( A166 and (not A167) );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A233) and A232 );
a1785a <=( A235 and A234 );
a1786a <=( a1785a and a1782a );
a1789a <=( A168 and A169 );
a1792a <=( A166 and (not A167) );
a1793a <=( a1792a and a1789a );
a1796a <=( (not A233) and A232 );
a1799a <=( A236 and A234 );
a1800a <=( a1799a and a1796a );
a1803a <=( A200 and (not A199) );
a1806a <=( A202 and A201 );
a1807a <=( a1806a and a1803a );
a1810a <=( A233 and (not A232) );
a1814a <=( (not A236) and (not A235) );
a1815a <=( (not A234) and a1814a );
a1816a <=( a1815a and a1810a );
a1819a <=( A200 and (not A199) );
a1822a <=( A202 and A201 );
a1823a <=( a1822a and a1819a );
a1826a <=( (not A233) and A232 );
a1830a <=( (not A236) and (not A235) );
a1831a <=( (not A234) and a1830a );
a1832a <=( a1831a and a1826a );
a1835a <=( A200 and (not A199) );
a1838a <=( A203 and A201 );
a1839a <=( a1838a and a1835a );
a1842a <=( A233 and (not A232) );
a1846a <=( (not A236) and (not A235) );
a1847a <=( (not A234) and a1846a );
a1848a <=( a1847a and a1842a );
a1851a <=( A200 and (not A199) );
a1854a <=( A203 and A201 );
a1855a <=( a1854a and a1851a );
a1858a <=( (not A233) and A232 );
a1862a <=( (not A236) and (not A235) );
a1863a <=( (not A234) and a1862a );
a1864a <=( a1863a and a1858a );
a1867a <=( A200 and (not A199) );
a1870a <=( (not A202) and (not A201) );
a1871a <=( a1870a and a1867a );
a1874a <=( (not A232) and (not A203) );
a1878a <=( A235 and A234 );
a1879a <=( A233 and a1878a );
a1880a <=( a1879a and a1874a );
a1883a <=( A200 and (not A199) );
a1886a <=( (not A202) and (not A201) );
a1887a <=( a1886a and a1883a );
a1890a <=( (not A232) and (not A203) );
a1894a <=( A236 and A234 );
a1895a <=( A233 and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A200 and (not A199) );
a1902a <=( (not A202) and (not A201) );
a1903a <=( a1902a and a1899a );
a1906a <=( A232 and (not A203) );
a1910a <=( A235 and A234 );
a1911a <=( (not A233) and a1910a );
a1912a <=( a1911a and a1906a );
a1915a <=( A200 and (not A199) );
a1918a <=( (not A202) and (not A201) );
a1919a <=( a1918a and a1915a );
a1922a <=( A232 and (not A203) );
a1926a <=( A236 and A234 );
a1927a <=( (not A233) and a1926a );
a1928a <=( a1927a and a1922a );
a1931a <=( (not A200) and A199 );
a1934a <=( A202 and A201 );
a1935a <=( a1934a and a1931a );
a1938a <=( A233 and (not A232) );
a1942a <=( (not A236) and (not A235) );
a1943a <=( (not A234) and a1942a );
a1944a <=( a1943a and a1938a );
a1947a <=( (not A200) and A199 );
a1950a <=( A202 and A201 );
a1951a <=( a1950a and a1947a );
a1954a <=( (not A233) and A232 );
a1958a <=( (not A236) and (not A235) );
a1959a <=( (not A234) and a1958a );
a1960a <=( a1959a and a1954a );
a1963a <=( (not A200) and A199 );
a1966a <=( A203 and A201 );
a1967a <=( a1966a and a1963a );
a1970a <=( A233 and (not A232) );
a1974a <=( (not A236) and (not A235) );
a1975a <=( (not A234) and a1974a );
a1976a <=( a1975a and a1970a );
a1979a <=( (not A200) and A199 );
a1982a <=( A203 and A201 );
a1983a <=( a1982a and a1979a );
a1986a <=( (not A233) and A232 );
a1990a <=( (not A236) and (not A235) );
a1991a <=( (not A234) and a1990a );
a1992a <=( a1991a and a1986a );
a1995a <=( (not A200) and A199 );
a1998a <=( (not A202) and (not A201) );
a1999a <=( a1998a and a1995a );
a2002a <=( (not A232) and (not A203) );
a2006a <=( A235 and A234 );
a2007a <=( A233 and a2006a );
a2008a <=( a2007a and a2002a );
a2011a <=( (not A200) and A199 );
a2014a <=( (not A202) and (not A201) );
a2015a <=( a2014a and a2011a );
a2018a <=( (not A232) and (not A203) );
a2022a <=( A236 and A234 );
a2023a <=( A233 and a2022a );
a2024a <=( a2023a and a2018a );
a2027a <=( (not A200) and A199 );
a2030a <=( (not A202) and (not A201) );
a2031a <=( a2030a and a2027a );
a2034a <=( A232 and (not A203) );
a2038a <=( A235 and A234 );
a2039a <=( (not A233) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( (not A200) and A199 );
a2046a <=( (not A202) and (not A201) );
a2047a <=( a2046a and a2043a );
a2050a <=( A232 and (not A203) );
a2054a <=( A236 and A234 );
a2055a <=( (not A233) and a2054a );
a2056a <=( a2055a and a2050a );
a2059a <=( A168 and (not A170) );
a2062a <=( (not A166) and A167 );
a2063a <=( a2062a and a2059a );
a2066a <=( A233 and (not A232) );
a2070a <=( (not A236) and (not A235) );
a2071a <=( (not A234) and a2070a );
a2072a <=( a2071a and a2066a );
a2075a <=( A168 and (not A170) );
a2078a <=( (not A166) and A167 );
a2079a <=( a2078a and a2075a );
a2082a <=( (not A233) and A232 );
a2086a <=( (not A236) and (not A235) );
a2087a <=( (not A234) and a2086a );
a2088a <=( a2087a and a2082a );
a2091a <=( A168 and (not A170) );
a2094a <=( A166 and (not A167) );
a2095a <=( a2094a and a2091a );
a2098a <=( A233 and (not A232) );
a2102a <=( (not A236) and (not A235) );
a2103a <=( (not A234) and a2102a );
a2104a <=( a2103a and a2098a );
a2107a <=( A168 and (not A170) );
a2110a <=( A166 and (not A167) );
a2111a <=( a2110a and a2107a );
a2114a <=( (not A233) and A232 );
a2118a <=( (not A236) and (not A235) );
a2119a <=( (not A234) and a2118a );
a2120a <=( a2119a and a2114a );
a2123a <=( A168 and A169 );
a2126a <=( (not A166) and A167 );
a2127a <=( a2126a and a2123a );
a2130a <=( A233 and (not A232) );
a2134a <=( (not A236) and (not A235) );
a2135a <=( (not A234) and a2134a );
a2136a <=( a2135a and a2130a );
a2139a <=( A168 and A169 );
a2142a <=( (not A166) and A167 );
a2143a <=( a2142a and a2139a );
a2146a <=( (not A233) and A232 );
a2150a <=( (not A236) and (not A235) );
a2151a <=( (not A234) and a2150a );
a2152a <=( a2151a and a2146a );
a2155a <=( A168 and A169 );
a2158a <=( A166 and (not A167) );
a2159a <=( a2158a and a2155a );
a2162a <=( A233 and (not A232) );
a2166a <=( (not A236) and (not A235) );
a2167a <=( (not A234) and a2166a );
a2168a <=( a2167a and a2162a );
a2171a <=( A168 and A169 );
a2174a <=( A166 and (not A167) );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A233) and A232 );
a2182a <=( (not A236) and (not A235) );
a2183a <=( (not A234) and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( (not A169) and A170 );
a2190a <=( A167 and (not A168) );
a2191a <=( a2190a and a2187a );
a2194a <=( (not A232) and (not A166) );
a2198a <=( A235 and A234 );
a2199a <=( A233 and a2198a );
a2200a <=( a2199a and a2194a );
a2203a <=( (not A169) and A170 );
a2206a <=( A167 and (not A168) );
a2207a <=( a2206a and a2203a );
a2210a <=( (not A232) and (not A166) );
a2214a <=( A236 and A234 );
a2215a <=( A233 and a2214a );
a2216a <=( a2215a and a2210a );
a2219a <=( (not A169) and A170 );
a2222a <=( A167 and (not A168) );
a2223a <=( a2222a and a2219a );
a2226a <=( A232 and (not A166) );
a2230a <=( A235 and A234 );
a2231a <=( (not A233) and a2230a );
a2232a <=( a2231a and a2226a );
a2235a <=( (not A169) and A170 );
a2238a <=( A167 and (not A168) );
a2239a <=( a2238a and a2235a );
a2242a <=( A232 and (not A166) );
a2246a <=( A236 and A234 );
a2247a <=( (not A233) and a2246a );
a2248a <=( a2247a and a2242a );
a2251a <=( (not A169) and A170 );
a2254a <=( (not A167) and (not A168) );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A232) and A166 );
a2262a <=( A235 and A234 );
a2263a <=( A233 and a2262a );
a2264a <=( a2263a and a2258a );
a2267a <=( (not A169) and A170 );
a2270a <=( (not A167) and (not A168) );
a2271a <=( a2270a and a2267a );
a2274a <=( (not A232) and A166 );
a2278a <=( A236 and A234 );
a2279a <=( A233 and a2278a );
a2280a <=( a2279a and a2274a );
a2283a <=( (not A169) and A170 );
a2286a <=( (not A167) and (not A168) );
a2287a <=( a2286a and a2283a );
a2290a <=( A232 and A166 );
a2294a <=( A235 and A234 );
a2295a <=( (not A233) and a2294a );
a2296a <=( a2295a and a2290a );
a2299a <=( (not A169) and A170 );
a2302a <=( (not A167) and (not A168) );
a2303a <=( a2302a and a2299a );
a2306a <=( A232 and A166 );
a2310a <=( A236 and A234 );
a2311a <=( (not A233) and a2310a );
a2312a <=( a2311a and a2306a );
a2315a <=( A200 and (not A199) );
a2319a <=( (not A203) and (not A202) );
a2320a <=( (not A201) and a2319a );
a2321a <=( a2320a and a2315a );
a2324a <=( A233 and (not A232) );
a2328a <=( (not A236) and (not A235) );
a2329a <=( (not A234) and a2328a );
a2330a <=( a2329a and a2324a );
a2333a <=( A200 and (not A199) );
a2337a <=( (not A203) and (not A202) );
a2338a <=( (not A201) and a2337a );
a2339a <=( a2338a and a2333a );
a2342a <=( (not A233) and A232 );
a2346a <=( (not A236) and (not A235) );
a2347a <=( (not A234) and a2346a );
a2348a <=( a2347a and a2342a );
a2351a <=( (not A200) and A199 );
a2355a <=( (not A203) and (not A202) );
a2356a <=( (not A201) and a2355a );
a2357a <=( a2356a and a2351a );
a2360a <=( A233 and (not A232) );
a2364a <=( (not A236) and (not A235) );
a2365a <=( (not A234) and a2364a );
a2366a <=( a2365a and a2360a );
a2369a <=( (not A200) and A199 );
a2373a <=( (not A203) and (not A202) );
a2374a <=( (not A201) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A233) and A232 );
a2382a <=( (not A236) and (not A235) );
a2383a <=( (not A234) and a2382a );
a2384a <=( a2383a and a2378a );
a2387a <=( A166 and A167 );
a2391a <=( A201 and A200 );
a2392a <=( (not A199) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( A298 and A202 );
a2400a <=( A301 and A300 );
a2401a <=( (not A299) and a2400a );
a2402a <=( a2401a and a2396a );
a2405a <=( A166 and A167 );
a2409a <=( A201 and A200 );
a2410a <=( (not A199) and a2409a );
a2411a <=( a2410a and a2405a );
a2414a <=( A298 and A202 );
a2418a <=( A302 and A300 );
a2419a <=( (not A299) and a2418a );
a2420a <=( a2419a and a2414a );
a2423a <=( A166 and A167 );
a2427a <=( A201 and A200 );
a2428a <=( (not A199) and a2427a );
a2429a <=( a2428a and a2423a );
a2432a <=( (not A298) and A202 );
a2436a <=( A301 and A300 );
a2437a <=( A299 and a2436a );
a2438a <=( a2437a and a2432a );
a2441a <=( A166 and A167 );
a2445a <=( A201 and A200 );
a2446a <=( (not A199) and a2445a );
a2447a <=( a2446a and a2441a );
a2450a <=( (not A298) and A202 );
a2454a <=( A302 and A300 );
a2455a <=( A299 and a2454a );
a2456a <=( a2455a and a2450a );
a2459a <=( A166 and A167 );
a2463a <=( A201 and A200 );
a2464a <=( (not A199) and a2463a );
a2465a <=( a2464a and a2459a );
a2468a <=( A298 and A203 );
a2472a <=( A301 and A300 );
a2473a <=( (not A299) and a2472a );
a2474a <=( a2473a and a2468a );
a2477a <=( A166 and A167 );
a2481a <=( A201 and A200 );
a2482a <=( (not A199) and a2481a );
a2483a <=( a2482a and a2477a );
a2486a <=( A298 and A203 );
a2490a <=( A302 and A300 );
a2491a <=( (not A299) and a2490a );
a2492a <=( a2491a and a2486a );
a2495a <=( A166 and A167 );
a2499a <=( A201 and A200 );
a2500a <=( (not A199) and a2499a );
a2501a <=( a2500a and a2495a );
a2504a <=( (not A298) and A203 );
a2508a <=( A301 and A300 );
a2509a <=( A299 and a2508a );
a2510a <=( a2509a and a2504a );
a2513a <=( A166 and A167 );
a2517a <=( A201 and A200 );
a2518a <=( (not A199) and a2517a );
a2519a <=( a2518a and a2513a );
a2522a <=( (not A298) and A203 );
a2526a <=( A302 and A300 );
a2527a <=( A299 and a2526a );
a2528a <=( a2527a and a2522a );
a2531a <=( A166 and A167 );
a2535a <=( A201 and (not A200) );
a2536a <=( A199 and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( A298 and A202 );
a2544a <=( A301 and A300 );
a2545a <=( (not A299) and a2544a );
a2546a <=( a2545a and a2540a );
a2549a <=( A166 and A167 );
a2553a <=( A201 and (not A200) );
a2554a <=( A199 and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A298 and A202 );
a2562a <=( A302 and A300 );
a2563a <=( (not A299) and a2562a );
a2564a <=( a2563a and a2558a );
a2567a <=( A166 and A167 );
a2571a <=( A201 and (not A200) );
a2572a <=( A199 and a2571a );
a2573a <=( a2572a and a2567a );
a2576a <=( (not A298) and A202 );
a2580a <=( A301 and A300 );
a2581a <=( A299 and a2580a );
a2582a <=( a2581a and a2576a );
a2585a <=( A166 and A167 );
a2589a <=( A201 and (not A200) );
a2590a <=( A199 and a2589a );
a2591a <=( a2590a and a2585a );
a2594a <=( (not A298) and A202 );
a2598a <=( A302 and A300 );
a2599a <=( A299 and a2598a );
a2600a <=( a2599a and a2594a );
a2603a <=( A166 and A167 );
a2607a <=( A201 and (not A200) );
a2608a <=( A199 and a2607a );
a2609a <=( a2608a and a2603a );
a2612a <=( A298 and A203 );
a2616a <=( A301 and A300 );
a2617a <=( (not A299) and a2616a );
a2618a <=( a2617a and a2612a );
a2621a <=( A166 and A167 );
a2625a <=( A201 and (not A200) );
a2626a <=( A199 and a2625a );
a2627a <=( a2626a and a2621a );
a2630a <=( A298 and A203 );
a2634a <=( A302 and A300 );
a2635a <=( (not A299) and a2634a );
a2636a <=( a2635a and a2630a );
a2639a <=( A166 and A167 );
a2643a <=( A201 and (not A200) );
a2644a <=( A199 and a2643a );
a2645a <=( a2644a and a2639a );
a2648a <=( (not A298) and A203 );
a2652a <=( A301 and A300 );
a2653a <=( A299 and a2652a );
a2654a <=( a2653a and a2648a );
a2657a <=( A166 and A167 );
a2661a <=( A201 and (not A200) );
a2662a <=( A199 and a2661a );
a2663a <=( a2662a and a2657a );
a2666a <=( (not A298) and A203 );
a2670a <=( A302 and A300 );
a2671a <=( A299 and a2670a );
a2672a <=( a2671a and a2666a );
a2675a <=( (not A166) and (not A167) );
a2679a <=( A201 and A200 );
a2680a <=( (not A199) and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( A298 and A202 );
a2688a <=( A301 and A300 );
a2689a <=( (not A299) and a2688a );
a2690a <=( a2689a and a2684a );
a2693a <=( (not A166) and (not A167) );
a2697a <=( A201 and A200 );
a2698a <=( (not A199) and a2697a );
a2699a <=( a2698a and a2693a );
a2702a <=( A298 and A202 );
a2706a <=( A302 and A300 );
a2707a <=( (not A299) and a2706a );
a2708a <=( a2707a and a2702a );
a2711a <=( (not A166) and (not A167) );
a2715a <=( A201 and A200 );
a2716a <=( (not A199) and a2715a );
a2717a <=( a2716a and a2711a );
a2720a <=( (not A298) and A202 );
a2724a <=( A301 and A300 );
a2725a <=( A299 and a2724a );
a2726a <=( a2725a and a2720a );
a2729a <=( (not A166) and (not A167) );
a2733a <=( A201 and A200 );
a2734a <=( (not A199) and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( (not A298) and A202 );
a2742a <=( A302 and A300 );
a2743a <=( A299 and a2742a );
a2744a <=( a2743a and a2738a );
a2747a <=( (not A166) and (not A167) );
a2751a <=( A201 and A200 );
a2752a <=( (not A199) and a2751a );
a2753a <=( a2752a and a2747a );
a2756a <=( A298 and A203 );
a2760a <=( A301 and A300 );
a2761a <=( (not A299) and a2760a );
a2762a <=( a2761a and a2756a );
a2765a <=( (not A166) and (not A167) );
a2769a <=( A201 and A200 );
a2770a <=( (not A199) and a2769a );
a2771a <=( a2770a and a2765a );
a2774a <=( A298 and A203 );
a2778a <=( A302 and A300 );
a2779a <=( (not A299) and a2778a );
a2780a <=( a2779a and a2774a );
a2783a <=( (not A166) and (not A167) );
a2787a <=( A201 and A200 );
a2788a <=( (not A199) and a2787a );
a2789a <=( a2788a and a2783a );
a2792a <=( (not A298) and A203 );
a2796a <=( A301 and A300 );
a2797a <=( A299 and a2796a );
a2798a <=( a2797a and a2792a );
a2801a <=( (not A166) and (not A167) );
a2805a <=( A201 and A200 );
a2806a <=( (not A199) and a2805a );
a2807a <=( a2806a and a2801a );
a2810a <=( (not A298) and A203 );
a2814a <=( A302 and A300 );
a2815a <=( A299 and a2814a );
a2816a <=( a2815a and a2810a );
a2819a <=( (not A166) and (not A167) );
a2823a <=( A201 and (not A200) );
a2824a <=( A199 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( A298 and A202 );
a2832a <=( A301 and A300 );
a2833a <=( (not A299) and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( (not A166) and (not A167) );
a2841a <=( A201 and (not A200) );
a2842a <=( A199 and a2841a );
a2843a <=( a2842a and a2837a );
a2846a <=( A298 and A202 );
a2850a <=( A302 and A300 );
a2851a <=( (not A299) and a2850a );
a2852a <=( a2851a and a2846a );
a2855a <=( (not A166) and (not A167) );
a2859a <=( A201 and (not A200) );
a2860a <=( A199 and a2859a );
a2861a <=( a2860a and a2855a );
a2864a <=( (not A298) and A202 );
a2868a <=( A301 and A300 );
a2869a <=( A299 and a2868a );
a2870a <=( a2869a and a2864a );
a2873a <=( (not A166) and (not A167) );
a2877a <=( A201 and (not A200) );
a2878a <=( A199 and a2877a );
a2879a <=( a2878a and a2873a );
a2882a <=( (not A298) and A202 );
a2886a <=( A302 and A300 );
a2887a <=( A299 and a2886a );
a2888a <=( a2887a and a2882a );
a2891a <=( (not A166) and (not A167) );
a2895a <=( A201 and (not A200) );
a2896a <=( A199 and a2895a );
a2897a <=( a2896a and a2891a );
a2900a <=( A298 and A203 );
a2904a <=( A301 and A300 );
a2905a <=( (not A299) and a2904a );
a2906a <=( a2905a and a2900a );
a2909a <=( (not A166) and (not A167) );
a2913a <=( A201 and (not A200) );
a2914a <=( A199 and a2913a );
a2915a <=( a2914a and a2909a );
a2918a <=( A298 and A203 );
a2922a <=( A302 and A300 );
a2923a <=( (not A299) and a2922a );
a2924a <=( a2923a and a2918a );
a2927a <=( (not A166) and (not A167) );
a2931a <=( A201 and (not A200) );
a2932a <=( A199 and a2931a );
a2933a <=( a2932a and a2927a );
a2936a <=( (not A298) and A203 );
a2940a <=( A301 and A300 );
a2941a <=( A299 and a2940a );
a2942a <=( a2941a and a2936a );
a2945a <=( (not A166) and (not A167) );
a2949a <=( A201 and (not A200) );
a2950a <=( A199 and a2949a );
a2951a <=( a2950a and a2945a );
a2954a <=( (not A298) and A203 );
a2958a <=( A302 and A300 );
a2959a <=( A299 and a2958a );
a2960a <=( a2959a and a2954a );
a2963a <=( A168 and (not A170) );
a2967a <=( (not A201) and (not A166) );
a2968a <=( A167 and a2967a );
a2969a <=( a2968a and a2963a );
a2972a <=( A298 and A202 );
a2976a <=( A301 and A300 );
a2977a <=( (not A299) and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and (not A170) );
a2985a <=( (not A201) and (not A166) );
a2986a <=( A167 and a2985a );
a2987a <=( a2986a and a2981a );
a2990a <=( A298 and A202 );
a2994a <=( A302 and A300 );
a2995a <=( (not A299) and a2994a );
a2996a <=( a2995a and a2990a );
a2999a <=( A168 and (not A170) );
a3003a <=( (not A201) and (not A166) );
a3004a <=( A167 and a3003a );
a3005a <=( a3004a and a2999a );
a3008a <=( (not A298) and A202 );
a3012a <=( A301 and A300 );
a3013a <=( A299 and a3012a );
a3014a <=( a3013a and a3008a );
a3017a <=( A168 and (not A170) );
a3021a <=( (not A201) and (not A166) );
a3022a <=( A167 and a3021a );
a3023a <=( a3022a and a3017a );
a3026a <=( (not A298) and A202 );
a3030a <=( A302 and A300 );
a3031a <=( A299 and a3030a );
a3032a <=( a3031a and a3026a );
a3035a <=( A168 and (not A170) );
a3039a <=( (not A201) and (not A166) );
a3040a <=( A167 and a3039a );
a3041a <=( a3040a and a3035a );
a3044a <=( A298 and A203 );
a3048a <=( A301 and A300 );
a3049a <=( (not A299) and a3048a );
a3050a <=( a3049a and a3044a );
a3053a <=( A168 and (not A170) );
a3057a <=( (not A201) and (not A166) );
a3058a <=( A167 and a3057a );
a3059a <=( a3058a and a3053a );
a3062a <=( A298 and A203 );
a3066a <=( A302 and A300 );
a3067a <=( (not A299) and a3066a );
a3068a <=( a3067a and a3062a );
a3071a <=( A168 and (not A170) );
a3075a <=( (not A201) and (not A166) );
a3076a <=( A167 and a3075a );
a3077a <=( a3076a and a3071a );
a3080a <=( (not A298) and A203 );
a3084a <=( A301 and A300 );
a3085a <=( A299 and a3084a );
a3086a <=( a3085a and a3080a );
a3089a <=( A168 and (not A170) );
a3093a <=( (not A201) and (not A166) );
a3094a <=( A167 and a3093a );
a3095a <=( a3094a and a3089a );
a3098a <=( (not A298) and A203 );
a3102a <=( A302 and A300 );
a3103a <=( A299 and a3102a );
a3104a <=( a3103a and a3098a );
a3107a <=( A168 and (not A170) );
a3111a <=( A199 and (not A166) );
a3112a <=( A167 and a3111a );
a3113a <=( a3112a and a3107a );
a3116a <=( A298 and A200 );
a3120a <=( A301 and A300 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( A168 and (not A170) );
a3129a <=( A199 and (not A166) );
a3130a <=( A167 and a3129a );
a3131a <=( a3130a and a3125a );
a3134a <=( A298 and A200 );
a3138a <=( A302 and A300 );
a3139a <=( (not A299) and a3138a );
a3140a <=( a3139a and a3134a );
a3143a <=( A168 and (not A170) );
a3147a <=( A199 and (not A166) );
a3148a <=( A167 and a3147a );
a3149a <=( a3148a and a3143a );
a3152a <=( (not A298) and A200 );
a3156a <=( A301 and A300 );
a3157a <=( A299 and a3156a );
a3158a <=( a3157a and a3152a );
a3161a <=( A168 and (not A170) );
a3165a <=( A199 and (not A166) );
a3166a <=( A167 and a3165a );
a3167a <=( a3166a and a3161a );
a3170a <=( (not A298) and A200 );
a3174a <=( A302 and A300 );
a3175a <=( A299 and a3174a );
a3176a <=( a3175a and a3170a );
a3179a <=( A168 and (not A170) );
a3183a <=( (not A199) and (not A166) );
a3184a <=( A167 and a3183a );
a3185a <=( a3184a and a3179a );
a3188a <=( A298 and (not A200) );
a3192a <=( A301 and A300 );
a3193a <=( (not A299) and a3192a );
a3194a <=( a3193a and a3188a );
a3197a <=( A168 and (not A170) );
a3201a <=( (not A199) and (not A166) );
a3202a <=( A167 and a3201a );
a3203a <=( a3202a and a3197a );
a3206a <=( A298 and (not A200) );
a3210a <=( A302 and A300 );
a3211a <=( (not A299) and a3210a );
a3212a <=( a3211a and a3206a );
a3215a <=( A168 and (not A170) );
a3219a <=( (not A199) and (not A166) );
a3220a <=( A167 and a3219a );
a3221a <=( a3220a and a3215a );
a3224a <=( (not A298) and (not A200) );
a3228a <=( A301 and A300 );
a3229a <=( A299 and a3228a );
a3230a <=( a3229a and a3224a );
a3233a <=( A168 and (not A170) );
a3237a <=( (not A199) and (not A166) );
a3238a <=( A167 and a3237a );
a3239a <=( a3238a and a3233a );
a3242a <=( (not A298) and (not A200) );
a3246a <=( A302 and A300 );
a3247a <=( A299 and a3246a );
a3248a <=( a3247a and a3242a );
a3251a <=( A168 and (not A170) );
a3255a <=( (not A201) and A166 );
a3256a <=( (not A167) and a3255a );
a3257a <=( a3256a and a3251a );
a3260a <=( A298 and A202 );
a3264a <=( A301 and A300 );
a3265a <=( (not A299) and a3264a );
a3266a <=( a3265a and a3260a );
a3269a <=( A168 and (not A170) );
a3273a <=( (not A201) and A166 );
a3274a <=( (not A167) and a3273a );
a3275a <=( a3274a and a3269a );
a3278a <=( A298 and A202 );
a3282a <=( A302 and A300 );
a3283a <=( (not A299) and a3282a );
a3284a <=( a3283a and a3278a );
a3287a <=( A168 and (not A170) );
a3291a <=( (not A201) and A166 );
a3292a <=( (not A167) and a3291a );
a3293a <=( a3292a and a3287a );
a3296a <=( (not A298) and A202 );
a3300a <=( A301 and A300 );
a3301a <=( A299 and a3300a );
a3302a <=( a3301a and a3296a );
a3305a <=( A168 and (not A170) );
a3309a <=( (not A201) and A166 );
a3310a <=( (not A167) and a3309a );
a3311a <=( a3310a and a3305a );
a3314a <=( (not A298) and A202 );
a3318a <=( A302 and A300 );
a3319a <=( A299 and a3318a );
a3320a <=( a3319a and a3314a );
a3323a <=( A168 and (not A170) );
a3327a <=( (not A201) and A166 );
a3328a <=( (not A167) and a3327a );
a3329a <=( a3328a and a3323a );
a3332a <=( A298 and A203 );
a3336a <=( A301 and A300 );
a3337a <=( (not A299) and a3336a );
a3338a <=( a3337a and a3332a );
a3341a <=( A168 and (not A170) );
a3345a <=( (not A201) and A166 );
a3346a <=( (not A167) and a3345a );
a3347a <=( a3346a and a3341a );
a3350a <=( A298 and A203 );
a3354a <=( A302 and A300 );
a3355a <=( (not A299) and a3354a );
a3356a <=( a3355a and a3350a );
a3359a <=( A168 and (not A170) );
a3363a <=( (not A201) and A166 );
a3364a <=( (not A167) and a3363a );
a3365a <=( a3364a and a3359a );
a3368a <=( (not A298) and A203 );
a3372a <=( A301 and A300 );
a3373a <=( A299 and a3372a );
a3374a <=( a3373a and a3368a );
a3377a <=( A168 and (not A170) );
a3381a <=( (not A201) and A166 );
a3382a <=( (not A167) and a3381a );
a3383a <=( a3382a and a3377a );
a3386a <=( (not A298) and A203 );
a3390a <=( A302 and A300 );
a3391a <=( A299 and a3390a );
a3392a <=( a3391a and a3386a );
a3395a <=( A168 and (not A170) );
a3399a <=( A199 and A166 );
a3400a <=( (not A167) and a3399a );
a3401a <=( a3400a and a3395a );
a3404a <=( A298 and A200 );
a3408a <=( A301 and A300 );
a3409a <=( (not A299) and a3408a );
a3410a <=( a3409a and a3404a );
a3413a <=( A168 and (not A170) );
a3417a <=( A199 and A166 );
a3418a <=( (not A167) and a3417a );
a3419a <=( a3418a and a3413a );
a3422a <=( A298 and A200 );
a3426a <=( A302 and A300 );
a3427a <=( (not A299) and a3426a );
a3428a <=( a3427a and a3422a );
a3431a <=( A168 and (not A170) );
a3435a <=( A199 and A166 );
a3436a <=( (not A167) and a3435a );
a3437a <=( a3436a and a3431a );
a3440a <=( (not A298) and A200 );
a3444a <=( A301 and A300 );
a3445a <=( A299 and a3444a );
a3446a <=( a3445a and a3440a );
a3449a <=( A168 and (not A170) );
a3453a <=( A199 and A166 );
a3454a <=( (not A167) and a3453a );
a3455a <=( a3454a and a3449a );
a3458a <=( (not A298) and A200 );
a3462a <=( A302 and A300 );
a3463a <=( A299 and a3462a );
a3464a <=( a3463a and a3458a );
a3467a <=( A168 and (not A170) );
a3471a <=( (not A199) and A166 );
a3472a <=( (not A167) and a3471a );
a3473a <=( a3472a and a3467a );
a3476a <=( A298 and (not A200) );
a3480a <=( A301 and A300 );
a3481a <=( (not A299) and a3480a );
a3482a <=( a3481a and a3476a );
a3485a <=( A168 and (not A170) );
a3489a <=( (not A199) and A166 );
a3490a <=( (not A167) and a3489a );
a3491a <=( a3490a and a3485a );
a3494a <=( A298 and (not A200) );
a3498a <=( A302 and A300 );
a3499a <=( (not A299) and a3498a );
a3500a <=( a3499a and a3494a );
a3503a <=( A168 and (not A170) );
a3507a <=( (not A199) and A166 );
a3508a <=( (not A167) and a3507a );
a3509a <=( a3508a and a3503a );
a3512a <=( (not A298) and (not A200) );
a3516a <=( A301 and A300 );
a3517a <=( A299 and a3516a );
a3518a <=( a3517a and a3512a );
a3521a <=( A168 and (not A170) );
a3525a <=( (not A199) and A166 );
a3526a <=( (not A167) and a3525a );
a3527a <=( a3526a and a3521a );
a3530a <=( (not A298) and (not A200) );
a3534a <=( A302 and A300 );
a3535a <=( A299 and a3534a );
a3536a <=( a3535a and a3530a );
a3539a <=( (not A168) and (not A170) );
a3543a <=( A201 and A200 );
a3544a <=( (not A199) and a3543a );
a3545a <=( a3544a and a3539a );
a3548a <=( A298 and A202 );
a3552a <=( A301 and A300 );
a3553a <=( (not A299) and a3552a );
a3554a <=( a3553a and a3548a );
a3557a <=( (not A168) and (not A170) );
a3561a <=( A201 and A200 );
a3562a <=( (not A199) and a3561a );
a3563a <=( a3562a and a3557a );
a3566a <=( A298 and A202 );
a3570a <=( A302 and A300 );
a3571a <=( (not A299) and a3570a );
a3572a <=( a3571a and a3566a );
a3575a <=( (not A168) and (not A170) );
a3579a <=( A201 and A200 );
a3580a <=( (not A199) and a3579a );
a3581a <=( a3580a and a3575a );
a3584a <=( (not A298) and A202 );
a3588a <=( A301 and A300 );
a3589a <=( A299 and a3588a );
a3590a <=( a3589a and a3584a );
a3593a <=( (not A168) and (not A170) );
a3597a <=( A201 and A200 );
a3598a <=( (not A199) and a3597a );
a3599a <=( a3598a and a3593a );
a3602a <=( (not A298) and A202 );
a3606a <=( A302 and A300 );
a3607a <=( A299 and a3606a );
a3608a <=( a3607a and a3602a );
a3611a <=( (not A168) and (not A170) );
a3615a <=( A201 and A200 );
a3616a <=( (not A199) and a3615a );
a3617a <=( a3616a and a3611a );
a3620a <=( A298 and A203 );
a3624a <=( A301 and A300 );
a3625a <=( (not A299) and a3624a );
a3626a <=( a3625a and a3620a );
a3629a <=( (not A168) and (not A170) );
a3633a <=( A201 and A200 );
a3634a <=( (not A199) and a3633a );
a3635a <=( a3634a and a3629a );
a3638a <=( A298 and A203 );
a3642a <=( A302 and A300 );
a3643a <=( (not A299) and a3642a );
a3644a <=( a3643a and a3638a );
a3647a <=( (not A168) and (not A170) );
a3651a <=( A201 and A200 );
a3652a <=( (not A199) and a3651a );
a3653a <=( a3652a and a3647a );
a3656a <=( (not A298) and A203 );
a3660a <=( A301 and A300 );
a3661a <=( A299 and a3660a );
a3662a <=( a3661a and a3656a );
a3665a <=( (not A168) and (not A170) );
a3669a <=( A201 and A200 );
a3670a <=( (not A199) and a3669a );
a3671a <=( a3670a and a3665a );
a3674a <=( (not A298) and A203 );
a3678a <=( A302 and A300 );
a3679a <=( A299 and a3678a );
a3680a <=( a3679a and a3674a );
a3683a <=( (not A168) and (not A170) );
a3687a <=( A201 and (not A200) );
a3688a <=( A199 and a3687a );
a3689a <=( a3688a and a3683a );
a3692a <=( A298 and A202 );
a3696a <=( A301 and A300 );
a3697a <=( (not A299) and a3696a );
a3698a <=( a3697a and a3692a );
a3701a <=( (not A168) and (not A170) );
a3705a <=( A201 and (not A200) );
a3706a <=( A199 and a3705a );
a3707a <=( a3706a and a3701a );
a3710a <=( A298 and A202 );
a3714a <=( A302 and A300 );
a3715a <=( (not A299) and a3714a );
a3716a <=( a3715a and a3710a );
a3719a <=( (not A168) and (not A170) );
a3723a <=( A201 and (not A200) );
a3724a <=( A199 and a3723a );
a3725a <=( a3724a and a3719a );
a3728a <=( (not A298) and A202 );
a3732a <=( A301 and A300 );
a3733a <=( A299 and a3732a );
a3734a <=( a3733a and a3728a );
a3737a <=( (not A168) and (not A170) );
a3741a <=( A201 and (not A200) );
a3742a <=( A199 and a3741a );
a3743a <=( a3742a and a3737a );
a3746a <=( (not A298) and A202 );
a3750a <=( A302 and A300 );
a3751a <=( A299 and a3750a );
a3752a <=( a3751a and a3746a );
a3755a <=( (not A168) and (not A170) );
a3759a <=( A201 and (not A200) );
a3760a <=( A199 and a3759a );
a3761a <=( a3760a and a3755a );
a3764a <=( A298 and A203 );
a3768a <=( A301 and A300 );
a3769a <=( (not A299) and a3768a );
a3770a <=( a3769a and a3764a );
a3773a <=( (not A168) and (not A170) );
a3777a <=( A201 and (not A200) );
a3778a <=( A199 and a3777a );
a3779a <=( a3778a and a3773a );
a3782a <=( A298 and A203 );
a3786a <=( A302 and A300 );
a3787a <=( (not A299) and a3786a );
a3788a <=( a3787a and a3782a );
a3791a <=( (not A168) and (not A170) );
a3795a <=( A201 and (not A200) );
a3796a <=( A199 and a3795a );
a3797a <=( a3796a and a3791a );
a3800a <=( (not A298) and A203 );
a3804a <=( A301 and A300 );
a3805a <=( A299 and a3804a );
a3806a <=( a3805a and a3800a );
a3809a <=( (not A168) and (not A170) );
a3813a <=( A201 and (not A200) );
a3814a <=( A199 and a3813a );
a3815a <=( a3814a and a3809a );
a3818a <=( (not A298) and A203 );
a3822a <=( A302 and A300 );
a3823a <=( A299 and a3822a );
a3824a <=( a3823a and a3818a );
a3827a <=( A168 and A169 );
a3831a <=( (not A201) and (not A166) );
a3832a <=( A167 and a3831a );
a3833a <=( a3832a and a3827a );
a3836a <=( A298 and A202 );
a3840a <=( A301 and A300 );
a3841a <=( (not A299) and a3840a );
a3842a <=( a3841a and a3836a );
a3845a <=( A168 and A169 );
a3849a <=( (not A201) and (not A166) );
a3850a <=( A167 and a3849a );
a3851a <=( a3850a and a3845a );
a3854a <=( A298 and A202 );
a3858a <=( A302 and A300 );
a3859a <=( (not A299) and a3858a );
a3860a <=( a3859a and a3854a );
a3863a <=( A168 and A169 );
a3867a <=( (not A201) and (not A166) );
a3868a <=( A167 and a3867a );
a3869a <=( a3868a and a3863a );
a3872a <=( (not A298) and A202 );
a3876a <=( A301 and A300 );
a3877a <=( A299 and a3876a );
a3878a <=( a3877a and a3872a );
a3881a <=( A168 and A169 );
a3885a <=( (not A201) and (not A166) );
a3886a <=( A167 and a3885a );
a3887a <=( a3886a and a3881a );
a3890a <=( (not A298) and A202 );
a3894a <=( A302 and A300 );
a3895a <=( A299 and a3894a );
a3896a <=( a3895a and a3890a );
a3899a <=( A168 and A169 );
a3903a <=( (not A201) and (not A166) );
a3904a <=( A167 and a3903a );
a3905a <=( a3904a and a3899a );
a3908a <=( A298 and A203 );
a3912a <=( A301 and A300 );
a3913a <=( (not A299) and a3912a );
a3914a <=( a3913a and a3908a );
a3917a <=( A168 and A169 );
a3921a <=( (not A201) and (not A166) );
a3922a <=( A167 and a3921a );
a3923a <=( a3922a and a3917a );
a3926a <=( A298 and A203 );
a3930a <=( A302 and A300 );
a3931a <=( (not A299) and a3930a );
a3932a <=( a3931a and a3926a );
a3935a <=( A168 and A169 );
a3939a <=( (not A201) and (not A166) );
a3940a <=( A167 and a3939a );
a3941a <=( a3940a and a3935a );
a3944a <=( (not A298) and A203 );
a3948a <=( A301 and A300 );
a3949a <=( A299 and a3948a );
a3950a <=( a3949a and a3944a );
a3953a <=( A168 and A169 );
a3957a <=( (not A201) and (not A166) );
a3958a <=( A167 and a3957a );
a3959a <=( a3958a and a3953a );
a3962a <=( (not A298) and A203 );
a3966a <=( A302 and A300 );
a3967a <=( A299 and a3966a );
a3968a <=( a3967a and a3962a );
a3971a <=( A168 and A169 );
a3975a <=( A199 and (not A166) );
a3976a <=( A167 and a3975a );
a3977a <=( a3976a and a3971a );
a3980a <=( A298 and A200 );
a3984a <=( A301 and A300 );
a3985a <=( (not A299) and a3984a );
a3986a <=( a3985a and a3980a );
a3989a <=( A168 and A169 );
a3993a <=( A199 and (not A166) );
a3994a <=( A167 and a3993a );
a3995a <=( a3994a and a3989a );
a3998a <=( A298 and A200 );
a4002a <=( A302 and A300 );
a4003a <=( (not A299) and a4002a );
a4004a <=( a4003a and a3998a );
a4007a <=( A168 and A169 );
a4011a <=( A199 and (not A166) );
a4012a <=( A167 and a4011a );
a4013a <=( a4012a and a4007a );
a4016a <=( (not A298) and A200 );
a4020a <=( A301 and A300 );
a4021a <=( A299 and a4020a );
a4022a <=( a4021a and a4016a );
a4025a <=( A168 and A169 );
a4029a <=( A199 and (not A166) );
a4030a <=( A167 and a4029a );
a4031a <=( a4030a and a4025a );
a4034a <=( (not A298) and A200 );
a4038a <=( A302 and A300 );
a4039a <=( A299 and a4038a );
a4040a <=( a4039a and a4034a );
a4043a <=( A168 and A169 );
a4047a <=( (not A199) and (not A166) );
a4048a <=( A167 and a4047a );
a4049a <=( a4048a and a4043a );
a4052a <=( A298 and (not A200) );
a4056a <=( A301 and A300 );
a4057a <=( (not A299) and a4056a );
a4058a <=( a4057a and a4052a );
a4061a <=( A168 and A169 );
a4065a <=( (not A199) and (not A166) );
a4066a <=( A167 and a4065a );
a4067a <=( a4066a and a4061a );
a4070a <=( A298 and (not A200) );
a4074a <=( A302 and A300 );
a4075a <=( (not A299) and a4074a );
a4076a <=( a4075a and a4070a );
a4079a <=( A168 and A169 );
a4083a <=( (not A199) and (not A166) );
a4084a <=( A167 and a4083a );
a4085a <=( a4084a and a4079a );
a4088a <=( (not A298) and (not A200) );
a4092a <=( A301 and A300 );
a4093a <=( A299 and a4092a );
a4094a <=( a4093a and a4088a );
a4097a <=( A168 and A169 );
a4101a <=( (not A199) and (not A166) );
a4102a <=( A167 and a4101a );
a4103a <=( a4102a and a4097a );
a4106a <=( (not A298) and (not A200) );
a4110a <=( A302 and A300 );
a4111a <=( A299 and a4110a );
a4112a <=( a4111a and a4106a );
a4115a <=( A168 and A169 );
a4119a <=( (not A201) and A166 );
a4120a <=( (not A167) and a4119a );
a4121a <=( a4120a and a4115a );
a4124a <=( A298 and A202 );
a4128a <=( A301 and A300 );
a4129a <=( (not A299) and a4128a );
a4130a <=( a4129a and a4124a );
a4133a <=( A168 and A169 );
a4137a <=( (not A201) and A166 );
a4138a <=( (not A167) and a4137a );
a4139a <=( a4138a and a4133a );
a4142a <=( A298 and A202 );
a4146a <=( A302 and A300 );
a4147a <=( (not A299) and a4146a );
a4148a <=( a4147a and a4142a );
a4151a <=( A168 and A169 );
a4155a <=( (not A201) and A166 );
a4156a <=( (not A167) and a4155a );
a4157a <=( a4156a and a4151a );
a4160a <=( (not A298) and A202 );
a4164a <=( A301 and A300 );
a4165a <=( A299 and a4164a );
a4166a <=( a4165a and a4160a );
a4169a <=( A168 and A169 );
a4173a <=( (not A201) and A166 );
a4174a <=( (not A167) and a4173a );
a4175a <=( a4174a and a4169a );
a4178a <=( (not A298) and A202 );
a4182a <=( A302 and A300 );
a4183a <=( A299 and a4182a );
a4184a <=( a4183a and a4178a );
a4187a <=( A168 and A169 );
a4191a <=( (not A201) and A166 );
a4192a <=( (not A167) and a4191a );
a4193a <=( a4192a and a4187a );
a4196a <=( A298 and A203 );
a4200a <=( A301 and A300 );
a4201a <=( (not A299) and a4200a );
a4202a <=( a4201a and a4196a );
a4205a <=( A168 and A169 );
a4209a <=( (not A201) and A166 );
a4210a <=( (not A167) and a4209a );
a4211a <=( a4210a and a4205a );
a4214a <=( A298 and A203 );
a4218a <=( A302 and A300 );
a4219a <=( (not A299) and a4218a );
a4220a <=( a4219a and a4214a );
a4223a <=( A168 and A169 );
a4227a <=( (not A201) and A166 );
a4228a <=( (not A167) and a4227a );
a4229a <=( a4228a and a4223a );
a4232a <=( (not A298) and A203 );
a4236a <=( A301 and A300 );
a4237a <=( A299 and a4236a );
a4238a <=( a4237a and a4232a );
a4241a <=( A168 and A169 );
a4245a <=( (not A201) and A166 );
a4246a <=( (not A167) and a4245a );
a4247a <=( a4246a and a4241a );
a4250a <=( (not A298) and A203 );
a4254a <=( A302 and A300 );
a4255a <=( A299 and a4254a );
a4256a <=( a4255a and a4250a );
a4259a <=( A168 and A169 );
a4263a <=( A199 and A166 );
a4264a <=( (not A167) and a4263a );
a4265a <=( a4264a and a4259a );
a4268a <=( A298 and A200 );
a4272a <=( A301 and A300 );
a4273a <=( (not A299) and a4272a );
a4274a <=( a4273a and a4268a );
a4277a <=( A168 and A169 );
a4281a <=( A199 and A166 );
a4282a <=( (not A167) and a4281a );
a4283a <=( a4282a and a4277a );
a4286a <=( A298 and A200 );
a4290a <=( A302 and A300 );
a4291a <=( (not A299) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A168 and A169 );
a4299a <=( A199 and A166 );
a4300a <=( (not A167) and a4299a );
a4301a <=( a4300a and a4295a );
a4304a <=( (not A298) and A200 );
a4308a <=( A301 and A300 );
a4309a <=( A299 and a4308a );
a4310a <=( a4309a and a4304a );
a4313a <=( A168 and A169 );
a4317a <=( A199 and A166 );
a4318a <=( (not A167) and a4317a );
a4319a <=( a4318a and a4313a );
a4322a <=( (not A298) and A200 );
a4326a <=( A302 and A300 );
a4327a <=( A299 and a4326a );
a4328a <=( a4327a and a4322a );
a4331a <=( A168 and A169 );
a4335a <=( (not A199) and A166 );
a4336a <=( (not A167) and a4335a );
a4337a <=( a4336a and a4331a );
a4340a <=( A298 and (not A200) );
a4344a <=( A301 and A300 );
a4345a <=( (not A299) and a4344a );
a4346a <=( a4345a and a4340a );
a4349a <=( A168 and A169 );
a4353a <=( (not A199) and A166 );
a4354a <=( (not A167) and a4353a );
a4355a <=( a4354a and a4349a );
a4358a <=( A298 and (not A200) );
a4362a <=( A302 and A300 );
a4363a <=( (not A299) and a4362a );
a4364a <=( a4363a and a4358a );
a4367a <=( A168 and A169 );
a4371a <=( (not A199) and A166 );
a4372a <=( (not A167) and a4371a );
a4373a <=( a4372a and a4367a );
a4376a <=( (not A298) and (not A200) );
a4380a <=( A301 and A300 );
a4381a <=( A299 and a4380a );
a4382a <=( a4381a and a4376a );
a4385a <=( A168 and A169 );
a4389a <=( (not A199) and A166 );
a4390a <=( (not A167) and a4389a );
a4391a <=( a4390a and a4385a );
a4394a <=( (not A298) and (not A200) );
a4398a <=( A302 and A300 );
a4399a <=( A299 and a4398a );
a4400a <=( a4399a and a4394a );
a4403a <=( (not A168) and A169 );
a4407a <=( A201 and A200 );
a4408a <=( (not A199) and a4407a );
a4409a <=( a4408a and a4403a );
a4412a <=( A298 and A202 );
a4416a <=( A301 and A300 );
a4417a <=( (not A299) and a4416a );
a4418a <=( a4417a and a4412a );
a4421a <=( (not A168) and A169 );
a4425a <=( A201 and A200 );
a4426a <=( (not A199) and a4425a );
a4427a <=( a4426a and a4421a );
a4430a <=( A298 and A202 );
a4434a <=( A302 and A300 );
a4435a <=( (not A299) and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( (not A168) and A169 );
a4443a <=( A201 and A200 );
a4444a <=( (not A199) and a4443a );
a4445a <=( a4444a and a4439a );
a4448a <=( (not A298) and A202 );
a4452a <=( A301 and A300 );
a4453a <=( A299 and a4452a );
a4454a <=( a4453a and a4448a );
a4457a <=( (not A168) and A169 );
a4461a <=( A201 and A200 );
a4462a <=( (not A199) and a4461a );
a4463a <=( a4462a and a4457a );
a4466a <=( (not A298) and A202 );
a4470a <=( A302 and A300 );
a4471a <=( A299 and a4470a );
a4472a <=( a4471a and a4466a );
a4475a <=( (not A168) and A169 );
a4479a <=( A201 and A200 );
a4480a <=( (not A199) and a4479a );
a4481a <=( a4480a and a4475a );
a4484a <=( A298 and A203 );
a4488a <=( A301 and A300 );
a4489a <=( (not A299) and a4488a );
a4490a <=( a4489a and a4484a );
a4493a <=( (not A168) and A169 );
a4497a <=( A201 and A200 );
a4498a <=( (not A199) and a4497a );
a4499a <=( a4498a and a4493a );
a4502a <=( A298 and A203 );
a4506a <=( A302 and A300 );
a4507a <=( (not A299) and a4506a );
a4508a <=( a4507a and a4502a );
a4511a <=( (not A168) and A169 );
a4515a <=( A201 and A200 );
a4516a <=( (not A199) and a4515a );
a4517a <=( a4516a and a4511a );
a4520a <=( (not A298) and A203 );
a4524a <=( A301 and A300 );
a4525a <=( A299 and a4524a );
a4526a <=( a4525a and a4520a );
a4529a <=( (not A168) and A169 );
a4533a <=( A201 and A200 );
a4534a <=( (not A199) and a4533a );
a4535a <=( a4534a and a4529a );
a4538a <=( (not A298) and A203 );
a4542a <=( A302 and A300 );
a4543a <=( A299 and a4542a );
a4544a <=( a4543a and a4538a );
a4547a <=( (not A168) and A169 );
a4551a <=( A201 and (not A200) );
a4552a <=( A199 and a4551a );
a4553a <=( a4552a and a4547a );
a4556a <=( A298 and A202 );
a4560a <=( A301 and A300 );
a4561a <=( (not A299) and a4560a );
a4562a <=( a4561a and a4556a );
a4565a <=( (not A168) and A169 );
a4569a <=( A201 and (not A200) );
a4570a <=( A199 and a4569a );
a4571a <=( a4570a and a4565a );
a4574a <=( A298 and A202 );
a4578a <=( A302 and A300 );
a4579a <=( (not A299) and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( (not A168) and A169 );
a4587a <=( A201 and (not A200) );
a4588a <=( A199 and a4587a );
a4589a <=( a4588a and a4583a );
a4592a <=( (not A298) and A202 );
a4596a <=( A301 and A300 );
a4597a <=( A299 and a4596a );
a4598a <=( a4597a and a4592a );
a4601a <=( (not A168) and A169 );
a4605a <=( A201 and (not A200) );
a4606a <=( A199 and a4605a );
a4607a <=( a4606a and a4601a );
a4610a <=( (not A298) and A202 );
a4614a <=( A302 and A300 );
a4615a <=( A299 and a4614a );
a4616a <=( a4615a and a4610a );
a4619a <=( (not A168) and A169 );
a4623a <=( A201 and (not A200) );
a4624a <=( A199 and a4623a );
a4625a <=( a4624a and a4619a );
a4628a <=( A298 and A203 );
a4632a <=( A301 and A300 );
a4633a <=( (not A299) and a4632a );
a4634a <=( a4633a and a4628a );
a4637a <=( (not A168) and A169 );
a4641a <=( A201 and (not A200) );
a4642a <=( A199 and a4641a );
a4643a <=( a4642a and a4637a );
a4646a <=( A298 and A203 );
a4650a <=( A302 and A300 );
a4651a <=( (not A299) and a4650a );
a4652a <=( a4651a and a4646a );
a4655a <=( (not A168) and A169 );
a4659a <=( A201 and (not A200) );
a4660a <=( A199 and a4659a );
a4661a <=( a4660a and a4655a );
a4664a <=( (not A298) and A203 );
a4668a <=( A301 and A300 );
a4669a <=( A299 and a4668a );
a4670a <=( a4669a and a4664a );
a4673a <=( (not A168) and A169 );
a4677a <=( A201 and (not A200) );
a4678a <=( A199 and a4677a );
a4679a <=( a4678a and a4673a );
a4682a <=( (not A298) and A203 );
a4686a <=( A302 and A300 );
a4687a <=( A299 and a4686a );
a4688a <=( a4687a and a4682a );
a4691a <=( (not A169) and A170 );
a4695a <=( (not A166) and A167 );
a4696a <=( (not A168) and a4695a );
a4697a <=( a4696a and a4691a );
a4700a <=( A233 and (not A232) );
a4704a <=( (not A236) and (not A235) );
a4705a <=( (not A234) and a4704a );
a4706a <=( a4705a and a4700a );
a4709a <=( (not A169) and A170 );
a4713a <=( (not A166) and A167 );
a4714a <=( (not A168) and a4713a );
a4715a <=( a4714a and a4709a );
a4718a <=( (not A233) and A232 );
a4722a <=( (not A236) and (not A235) );
a4723a <=( (not A234) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( (not A169) and A170 );
a4731a <=( A166 and (not A167) );
a4732a <=( (not A168) and a4731a );
a4733a <=( a4732a and a4727a );
a4736a <=( A233 and (not A232) );
a4740a <=( (not A236) and (not A235) );
a4741a <=( (not A234) and a4740a );
a4742a <=( a4741a and a4736a );
a4745a <=( (not A169) and A170 );
a4749a <=( A166 and (not A167) );
a4750a <=( (not A168) and a4749a );
a4751a <=( a4750a and a4745a );
a4754a <=( (not A233) and A232 );
a4758a <=( (not A236) and (not A235) );
a4759a <=( (not A234) and a4758a );
a4760a <=( a4759a and a4754a );
a4763a <=( A166 and A167 );
a4767a <=( A201 and A200 );
a4768a <=( (not A199) and a4767a );
a4769a <=( a4768a and a4763a );
a4773a <=( (not A299) and A298 );
a4774a <=( A202 and a4773a );
a4778a <=( (not A302) and (not A301) );
a4779a <=( (not A300) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A166 and A167 );
a4787a <=( A201 and A200 );
a4788a <=( (not A199) and a4787a );
a4789a <=( a4788a and a4783a );
a4793a <=( A299 and (not A298) );
a4794a <=( A202 and a4793a );
a4798a <=( (not A302) and (not A301) );
a4799a <=( (not A300) and a4798a );
a4800a <=( a4799a and a4794a );
a4803a <=( A166 and A167 );
a4807a <=( A201 and A200 );
a4808a <=( (not A199) and a4807a );
a4809a <=( a4808a and a4803a );
a4813a <=( (not A299) and A298 );
a4814a <=( A203 and a4813a );
a4818a <=( (not A302) and (not A301) );
a4819a <=( (not A300) and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A166 and A167 );
a4827a <=( A201 and A200 );
a4828a <=( (not A199) and a4827a );
a4829a <=( a4828a and a4823a );
a4833a <=( A299 and (not A298) );
a4834a <=( A203 and a4833a );
a4838a <=( (not A302) and (not A301) );
a4839a <=( (not A300) and a4838a );
a4840a <=( a4839a and a4834a );
a4843a <=( A166 and A167 );
a4847a <=( (not A201) and A200 );
a4848a <=( (not A199) and a4847a );
a4849a <=( a4848a and a4843a );
a4853a <=( A298 and (not A203) );
a4854a <=( (not A202) and a4853a );
a4858a <=( A301 and A300 );
a4859a <=( (not A299) and a4858a );
a4860a <=( a4859a and a4854a );
a4863a <=( A166 and A167 );
a4867a <=( (not A201) and A200 );
a4868a <=( (not A199) and a4867a );
a4869a <=( a4868a and a4863a );
a4873a <=( A298 and (not A203) );
a4874a <=( (not A202) and a4873a );
a4878a <=( A302 and A300 );
a4879a <=( (not A299) and a4878a );
a4880a <=( a4879a and a4874a );
a4883a <=( A166 and A167 );
a4887a <=( (not A201) and A200 );
a4888a <=( (not A199) and a4887a );
a4889a <=( a4888a and a4883a );
a4893a <=( (not A298) and (not A203) );
a4894a <=( (not A202) and a4893a );
a4898a <=( A301 and A300 );
a4899a <=( A299 and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A166 and A167 );
a4907a <=( (not A201) and A200 );
a4908a <=( (not A199) and a4907a );
a4909a <=( a4908a and a4903a );
a4913a <=( (not A298) and (not A203) );
a4914a <=( (not A202) and a4913a );
a4918a <=( A302 and A300 );
a4919a <=( A299 and a4918a );
a4920a <=( a4919a and a4914a );
a4923a <=( A166 and A167 );
a4927a <=( A201 and (not A200) );
a4928a <=( A199 and a4927a );
a4929a <=( a4928a and a4923a );
a4933a <=( (not A299) and A298 );
a4934a <=( A202 and a4933a );
a4938a <=( (not A302) and (not A301) );
a4939a <=( (not A300) and a4938a );
a4940a <=( a4939a and a4934a );
a4943a <=( A166 and A167 );
a4947a <=( A201 and (not A200) );
a4948a <=( A199 and a4947a );
a4949a <=( a4948a and a4943a );
a4953a <=( A299 and (not A298) );
a4954a <=( A202 and a4953a );
a4958a <=( (not A302) and (not A301) );
a4959a <=( (not A300) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A166 and A167 );
a4967a <=( A201 and (not A200) );
a4968a <=( A199 and a4967a );
a4969a <=( a4968a and a4963a );
a4973a <=( (not A299) and A298 );
a4974a <=( A203 and a4973a );
a4978a <=( (not A302) and (not A301) );
a4979a <=( (not A300) and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A166 and A167 );
a4987a <=( A201 and (not A200) );
a4988a <=( A199 and a4987a );
a4989a <=( a4988a and a4983a );
a4993a <=( A299 and (not A298) );
a4994a <=( A203 and a4993a );
a4998a <=( (not A302) and (not A301) );
a4999a <=( (not A300) and a4998a );
a5000a <=( a4999a and a4994a );
a5003a <=( A166 and A167 );
a5007a <=( (not A201) and (not A200) );
a5008a <=( A199 and a5007a );
a5009a <=( a5008a and a5003a );
a5013a <=( A298 and (not A203) );
a5014a <=( (not A202) and a5013a );
a5018a <=( A301 and A300 );
a5019a <=( (not A299) and a5018a );
a5020a <=( a5019a and a5014a );
a5023a <=( A166 and A167 );
a5027a <=( (not A201) and (not A200) );
a5028a <=( A199 and a5027a );
a5029a <=( a5028a and a5023a );
a5033a <=( A298 and (not A203) );
a5034a <=( (not A202) and a5033a );
a5038a <=( A302 and A300 );
a5039a <=( (not A299) and a5038a );
a5040a <=( a5039a and a5034a );
a5043a <=( A166 and A167 );
a5047a <=( (not A201) and (not A200) );
a5048a <=( A199 and a5047a );
a5049a <=( a5048a and a5043a );
a5053a <=( (not A298) and (not A203) );
a5054a <=( (not A202) and a5053a );
a5058a <=( A301 and A300 );
a5059a <=( A299 and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A166 and A167 );
a5067a <=( (not A201) and (not A200) );
a5068a <=( A199 and a5067a );
a5069a <=( a5068a and a5063a );
a5073a <=( (not A298) and (not A203) );
a5074a <=( (not A202) and a5073a );
a5078a <=( A302 and A300 );
a5079a <=( A299 and a5078a );
a5080a <=( a5079a and a5074a );
a5083a <=( (not A166) and (not A167) );
a5087a <=( A201 and A200 );
a5088a <=( (not A199) and a5087a );
a5089a <=( a5088a and a5083a );
a5093a <=( (not A299) and A298 );
a5094a <=( A202 and a5093a );
a5098a <=( (not A302) and (not A301) );
a5099a <=( (not A300) and a5098a );
a5100a <=( a5099a and a5094a );
a5103a <=( (not A166) and (not A167) );
a5107a <=( A201 and A200 );
a5108a <=( (not A199) and a5107a );
a5109a <=( a5108a and a5103a );
a5113a <=( A299 and (not A298) );
a5114a <=( A202 and a5113a );
a5118a <=( (not A302) and (not A301) );
a5119a <=( (not A300) and a5118a );
a5120a <=( a5119a and a5114a );
a5123a <=( (not A166) and (not A167) );
a5127a <=( A201 and A200 );
a5128a <=( (not A199) and a5127a );
a5129a <=( a5128a and a5123a );
a5133a <=( (not A299) and A298 );
a5134a <=( A203 and a5133a );
a5138a <=( (not A302) and (not A301) );
a5139a <=( (not A300) and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( (not A166) and (not A167) );
a5147a <=( A201 and A200 );
a5148a <=( (not A199) and a5147a );
a5149a <=( a5148a and a5143a );
a5153a <=( A299 and (not A298) );
a5154a <=( A203 and a5153a );
a5158a <=( (not A302) and (not A301) );
a5159a <=( (not A300) and a5158a );
a5160a <=( a5159a and a5154a );
a5163a <=( (not A166) and (not A167) );
a5167a <=( (not A201) and A200 );
a5168a <=( (not A199) and a5167a );
a5169a <=( a5168a and a5163a );
a5173a <=( A298 and (not A203) );
a5174a <=( (not A202) and a5173a );
a5178a <=( A301 and A300 );
a5179a <=( (not A299) and a5178a );
a5180a <=( a5179a and a5174a );
a5183a <=( (not A166) and (not A167) );
a5187a <=( (not A201) and A200 );
a5188a <=( (not A199) and a5187a );
a5189a <=( a5188a and a5183a );
a5193a <=( A298 and (not A203) );
a5194a <=( (not A202) and a5193a );
a5198a <=( A302 and A300 );
a5199a <=( (not A299) and a5198a );
a5200a <=( a5199a and a5194a );
a5203a <=( (not A166) and (not A167) );
a5207a <=( (not A201) and A200 );
a5208a <=( (not A199) and a5207a );
a5209a <=( a5208a and a5203a );
a5213a <=( (not A298) and (not A203) );
a5214a <=( (not A202) and a5213a );
a5218a <=( A301 and A300 );
a5219a <=( A299 and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( (not A166) and (not A167) );
a5227a <=( (not A201) and A200 );
a5228a <=( (not A199) and a5227a );
a5229a <=( a5228a and a5223a );
a5233a <=( (not A298) and (not A203) );
a5234a <=( (not A202) and a5233a );
a5238a <=( A302 and A300 );
a5239a <=( A299 and a5238a );
a5240a <=( a5239a and a5234a );
a5243a <=( (not A166) and (not A167) );
a5247a <=( A201 and (not A200) );
a5248a <=( A199 and a5247a );
a5249a <=( a5248a and a5243a );
a5253a <=( (not A299) and A298 );
a5254a <=( A202 and a5253a );
a5258a <=( (not A302) and (not A301) );
a5259a <=( (not A300) and a5258a );
a5260a <=( a5259a and a5254a );
a5263a <=( (not A166) and (not A167) );
a5267a <=( A201 and (not A200) );
a5268a <=( A199 and a5267a );
a5269a <=( a5268a and a5263a );
a5273a <=( A299 and (not A298) );
a5274a <=( A202 and a5273a );
a5278a <=( (not A302) and (not A301) );
a5279a <=( (not A300) and a5278a );
a5280a <=( a5279a and a5274a );
a5283a <=( (not A166) and (not A167) );
a5287a <=( A201 and (not A200) );
a5288a <=( A199 and a5287a );
a5289a <=( a5288a and a5283a );
a5293a <=( (not A299) and A298 );
a5294a <=( A203 and a5293a );
a5298a <=( (not A302) and (not A301) );
a5299a <=( (not A300) and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( (not A166) and (not A167) );
a5307a <=( A201 and (not A200) );
a5308a <=( A199 and a5307a );
a5309a <=( a5308a and a5303a );
a5313a <=( A299 and (not A298) );
a5314a <=( A203 and a5313a );
a5318a <=( (not A302) and (not A301) );
a5319a <=( (not A300) and a5318a );
a5320a <=( a5319a and a5314a );
a5323a <=( (not A166) and (not A167) );
a5327a <=( (not A201) and (not A200) );
a5328a <=( A199 and a5327a );
a5329a <=( a5328a and a5323a );
a5333a <=( A298 and (not A203) );
a5334a <=( (not A202) and a5333a );
a5338a <=( A301 and A300 );
a5339a <=( (not A299) and a5338a );
a5340a <=( a5339a and a5334a );
a5343a <=( (not A166) and (not A167) );
a5347a <=( (not A201) and (not A200) );
a5348a <=( A199 and a5347a );
a5349a <=( a5348a and a5343a );
a5353a <=( A298 and (not A203) );
a5354a <=( (not A202) and a5353a );
a5358a <=( A302 and A300 );
a5359a <=( (not A299) and a5358a );
a5360a <=( a5359a and a5354a );
a5363a <=( (not A166) and (not A167) );
a5367a <=( (not A201) and (not A200) );
a5368a <=( A199 and a5367a );
a5369a <=( a5368a and a5363a );
a5373a <=( (not A298) and (not A203) );
a5374a <=( (not A202) and a5373a );
a5378a <=( A301 and A300 );
a5379a <=( A299 and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( (not A166) and (not A167) );
a5387a <=( (not A201) and (not A200) );
a5388a <=( A199 and a5387a );
a5389a <=( a5388a and a5383a );
a5393a <=( (not A298) and (not A203) );
a5394a <=( (not A202) and a5393a );
a5398a <=( A302 and A300 );
a5399a <=( A299 and a5398a );
a5400a <=( a5399a and a5394a );
a5403a <=( A168 and (not A170) );
a5407a <=( A201 and (not A166) );
a5408a <=( A167 and a5407a );
a5409a <=( a5408a and a5403a );
a5413a <=( A298 and (not A203) );
a5414a <=( (not A202) and a5413a );
a5418a <=( A301 and A300 );
a5419a <=( (not A299) and a5418a );
a5420a <=( a5419a and a5414a );
a5423a <=( A168 and (not A170) );
a5427a <=( A201 and (not A166) );
a5428a <=( A167 and a5427a );
a5429a <=( a5428a and a5423a );
a5433a <=( A298 and (not A203) );
a5434a <=( (not A202) and a5433a );
a5438a <=( A302 and A300 );
a5439a <=( (not A299) and a5438a );
a5440a <=( a5439a and a5434a );
a5443a <=( A168 and (not A170) );
a5447a <=( A201 and (not A166) );
a5448a <=( A167 and a5447a );
a5449a <=( a5448a and a5443a );
a5453a <=( (not A298) and (not A203) );
a5454a <=( (not A202) and a5453a );
a5458a <=( A301 and A300 );
a5459a <=( A299 and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A168 and (not A170) );
a5467a <=( A201 and (not A166) );
a5468a <=( A167 and a5467a );
a5469a <=( a5468a and a5463a );
a5473a <=( (not A298) and (not A203) );
a5474a <=( (not A202) and a5473a );
a5478a <=( A302 and A300 );
a5479a <=( A299 and a5478a );
a5480a <=( a5479a and a5474a );
a5483a <=( A168 and (not A170) );
a5487a <=( (not A201) and (not A166) );
a5488a <=( A167 and a5487a );
a5489a <=( a5488a and a5483a );
a5493a <=( (not A299) and A298 );
a5494a <=( A202 and a5493a );
a5498a <=( (not A302) and (not A301) );
a5499a <=( (not A300) and a5498a );
a5500a <=( a5499a and a5494a );
a5503a <=( A168 and (not A170) );
a5507a <=( (not A201) and (not A166) );
a5508a <=( A167 and a5507a );
a5509a <=( a5508a and a5503a );
a5513a <=( A299 and (not A298) );
a5514a <=( A202 and a5513a );
a5518a <=( (not A302) and (not A301) );
a5519a <=( (not A300) and a5518a );
a5520a <=( a5519a and a5514a );
a5523a <=( A168 and (not A170) );
a5527a <=( (not A201) and (not A166) );
a5528a <=( A167 and a5527a );
a5529a <=( a5528a and a5523a );
a5533a <=( (not A299) and A298 );
a5534a <=( A203 and a5533a );
a5538a <=( (not A302) and (not A301) );
a5539a <=( (not A300) and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A168 and (not A170) );
a5547a <=( (not A201) and (not A166) );
a5548a <=( A167 and a5547a );
a5549a <=( a5548a and a5543a );
a5553a <=( A299 and (not A298) );
a5554a <=( A203 and a5553a );
a5558a <=( (not A302) and (not A301) );
a5559a <=( (not A300) and a5558a );
a5560a <=( a5559a and a5554a );
a5563a <=( A168 and (not A170) );
a5567a <=( A199 and (not A166) );
a5568a <=( A167 and a5567a );
a5569a <=( a5568a and a5563a );
a5573a <=( (not A299) and A298 );
a5574a <=( A200 and a5573a );
a5578a <=( (not A302) and (not A301) );
a5579a <=( (not A300) and a5578a );
a5580a <=( a5579a and a5574a );
a5583a <=( A168 and (not A170) );
a5587a <=( A199 and (not A166) );
a5588a <=( A167 and a5587a );
a5589a <=( a5588a and a5583a );
a5593a <=( A299 and (not A298) );
a5594a <=( A200 and a5593a );
a5598a <=( (not A302) and (not A301) );
a5599a <=( (not A300) and a5598a );
a5600a <=( a5599a and a5594a );
a5603a <=( A168 and (not A170) );
a5607a <=( (not A199) and (not A166) );
a5608a <=( A167 and a5607a );
a5609a <=( a5608a and a5603a );
a5613a <=( (not A299) and A298 );
a5614a <=( (not A200) and a5613a );
a5618a <=( (not A302) and (not A301) );
a5619a <=( (not A300) and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A168 and (not A170) );
a5627a <=( (not A199) and (not A166) );
a5628a <=( A167 and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( A299 and (not A298) );
a5634a <=( (not A200) and a5633a );
a5638a <=( (not A302) and (not A301) );
a5639a <=( (not A300) and a5638a );
a5640a <=( a5639a and a5634a );
a5643a <=( A168 and (not A170) );
a5647a <=( A201 and A166 );
a5648a <=( (not A167) and a5647a );
a5649a <=( a5648a and a5643a );
a5653a <=( A298 and (not A203) );
a5654a <=( (not A202) and a5653a );
a5658a <=( A301 and A300 );
a5659a <=( (not A299) and a5658a );
a5660a <=( a5659a and a5654a );
a5663a <=( A168 and (not A170) );
a5667a <=( A201 and A166 );
a5668a <=( (not A167) and a5667a );
a5669a <=( a5668a and a5663a );
a5673a <=( A298 and (not A203) );
a5674a <=( (not A202) and a5673a );
a5678a <=( A302 and A300 );
a5679a <=( (not A299) and a5678a );
a5680a <=( a5679a and a5674a );
a5683a <=( A168 and (not A170) );
a5687a <=( A201 and A166 );
a5688a <=( (not A167) and a5687a );
a5689a <=( a5688a and a5683a );
a5693a <=( (not A298) and (not A203) );
a5694a <=( (not A202) and a5693a );
a5698a <=( A301 and A300 );
a5699a <=( A299 and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( A168 and (not A170) );
a5707a <=( A201 and A166 );
a5708a <=( (not A167) and a5707a );
a5709a <=( a5708a and a5703a );
a5713a <=( (not A298) and (not A203) );
a5714a <=( (not A202) and a5713a );
a5718a <=( A302 and A300 );
a5719a <=( A299 and a5718a );
a5720a <=( a5719a and a5714a );
a5723a <=( A168 and (not A170) );
a5727a <=( (not A201) and A166 );
a5728a <=( (not A167) and a5727a );
a5729a <=( a5728a and a5723a );
a5733a <=( (not A299) and A298 );
a5734a <=( A202 and a5733a );
a5738a <=( (not A302) and (not A301) );
a5739a <=( (not A300) and a5738a );
a5740a <=( a5739a and a5734a );
a5743a <=( A168 and (not A170) );
a5747a <=( (not A201) and A166 );
a5748a <=( (not A167) and a5747a );
a5749a <=( a5748a and a5743a );
a5753a <=( A299 and (not A298) );
a5754a <=( A202 and a5753a );
a5758a <=( (not A302) and (not A301) );
a5759a <=( (not A300) and a5758a );
a5760a <=( a5759a and a5754a );
a5763a <=( A168 and (not A170) );
a5767a <=( (not A201) and A166 );
a5768a <=( (not A167) and a5767a );
a5769a <=( a5768a and a5763a );
a5773a <=( (not A299) and A298 );
a5774a <=( A203 and a5773a );
a5778a <=( (not A302) and (not A301) );
a5779a <=( (not A300) and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A168 and (not A170) );
a5787a <=( (not A201) and A166 );
a5788a <=( (not A167) and a5787a );
a5789a <=( a5788a and a5783a );
a5793a <=( A299 and (not A298) );
a5794a <=( A203 and a5793a );
a5798a <=( (not A302) and (not A301) );
a5799a <=( (not A300) and a5798a );
a5800a <=( a5799a and a5794a );
a5803a <=( A168 and (not A170) );
a5807a <=( A199 and A166 );
a5808a <=( (not A167) and a5807a );
a5809a <=( a5808a and a5803a );
a5813a <=( (not A299) and A298 );
a5814a <=( A200 and a5813a );
a5818a <=( (not A302) and (not A301) );
a5819a <=( (not A300) and a5818a );
a5820a <=( a5819a and a5814a );
a5823a <=( A168 and (not A170) );
a5827a <=( A199 and A166 );
a5828a <=( (not A167) and a5827a );
a5829a <=( a5828a and a5823a );
a5833a <=( A299 and (not A298) );
a5834a <=( A200 and a5833a );
a5838a <=( (not A302) and (not A301) );
a5839a <=( (not A300) and a5838a );
a5840a <=( a5839a and a5834a );
a5843a <=( A168 and (not A170) );
a5847a <=( (not A199) and A166 );
a5848a <=( (not A167) and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A299) and A298 );
a5854a <=( (not A200) and a5853a );
a5858a <=( (not A302) and (not A301) );
a5859a <=( (not A300) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( A168 and (not A170) );
a5867a <=( (not A199) and A166 );
a5868a <=( (not A167) and a5867a );
a5869a <=( a5868a and a5863a );
a5873a <=( A299 and (not A298) );
a5874a <=( (not A200) and a5873a );
a5878a <=( (not A302) and (not A301) );
a5879a <=( (not A300) and a5878a );
a5880a <=( a5879a and a5874a );
a5883a <=( (not A168) and (not A170) );
a5887a <=( A201 and A200 );
a5888a <=( (not A199) and a5887a );
a5889a <=( a5888a and a5883a );
a5893a <=( (not A299) and A298 );
a5894a <=( A202 and a5893a );
a5898a <=( (not A302) and (not A301) );
a5899a <=( (not A300) and a5898a );
a5900a <=( a5899a and a5894a );
a5903a <=( (not A168) and (not A170) );
a5907a <=( A201 and A200 );
a5908a <=( (not A199) and a5907a );
a5909a <=( a5908a and a5903a );
a5913a <=( A299 and (not A298) );
a5914a <=( A202 and a5913a );
a5918a <=( (not A302) and (not A301) );
a5919a <=( (not A300) and a5918a );
a5920a <=( a5919a and a5914a );
a5923a <=( (not A168) and (not A170) );
a5927a <=( A201 and A200 );
a5928a <=( (not A199) and a5927a );
a5929a <=( a5928a and a5923a );
a5933a <=( (not A299) and A298 );
a5934a <=( A203 and a5933a );
a5938a <=( (not A302) and (not A301) );
a5939a <=( (not A300) and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( (not A168) and (not A170) );
a5947a <=( A201 and A200 );
a5948a <=( (not A199) and a5947a );
a5949a <=( a5948a and a5943a );
a5953a <=( A299 and (not A298) );
a5954a <=( A203 and a5953a );
a5958a <=( (not A302) and (not A301) );
a5959a <=( (not A300) and a5958a );
a5960a <=( a5959a and a5954a );
a5963a <=( (not A168) and (not A170) );
a5967a <=( (not A201) and A200 );
a5968a <=( (not A199) and a5967a );
a5969a <=( a5968a and a5963a );
a5973a <=( A298 and (not A203) );
a5974a <=( (not A202) and a5973a );
a5978a <=( A301 and A300 );
a5979a <=( (not A299) and a5978a );
a5980a <=( a5979a and a5974a );
a5983a <=( (not A168) and (not A170) );
a5987a <=( (not A201) and A200 );
a5988a <=( (not A199) and a5987a );
a5989a <=( a5988a and a5983a );
a5993a <=( A298 and (not A203) );
a5994a <=( (not A202) and a5993a );
a5998a <=( A302 and A300 );
a5999a <=( (not A299) and a5998a );
a6000a <=( a5999a and a5994a );
a6003a <=( (not A168) and (not A170) );
a6007a <=( (not A201) and A200 );
a6008a <=( (not A199) and a6007a );
a6009a <=( a6008a and a6003a );
a6013a <=( (not A298) and (not A203) );
a6014a <=( (not A202) and a6013a );
a6018a <=( A301 and A300 );
a6019a <=( A299 and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( (not A168) and (not A170) );
a6027a <=( (not A201) and A200 );
a6028a <=( (not A199) and a6027a );
a6029a <=( a6028a and a6023a );
a6033a <=( (not A298) and (not A203) );
a6034a <=( (not A202) and a6033a );
a6038a <=( A302 and A300 );
a6039a <=( A299 and a6038a );
a6040a <=( a6039a and a6034a );
a6043a <=( (not A168) and (not A170) );
a6047a <=( A201 and (not A200) );
a6048a <=( A199 and a6047a );
a6049a <=( a6048a and a6043a );
a6053a <=( (not A299) and A298 );
a6054a <=( A202 and a6053a );
a6058a <=( (not A302) and (not A301) );
a6059a <=( (not A300) and a6058a );
a6060a <=( a6059a and a6054a );
a6063a <=( (not A168) and (not A170) );
a6067a <=( A201 and (not A200) );
a6068a <=( A199 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( A299 and (not A298) );
a6074a <=( A202 and a6073a );
a6078a <=( (not A302) and (not A301) );
a6079a <=( (not A300) and a6078a );
a6080a <=( a6079a and a6074a );
a6083a <=( (not A168) and (not A170) );
a6087a <=( A201 and (not A200) );
a6088a <=( A199 and a6087a );
a6089a <=( a6088a and a6083a );
a6093a <=( (not A299) and A298 );
a6094a <=( A203 and a6093a );
a6098a <=( (not A302) and (not A301) );
a6099a <=( (not A300) and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( (not A168) and (not A170) );
a6107a <=( A201 and (not A200) );
a6108a <=( A199 and a6107a );
a6109a <=( a6108a and a6103a );
a6113a <=( A299 and (not A298) );
a6114a <=( A203 and a6113a );
a6118a <=( (not A302) and (not A301) );
a6119a <=( (not A300) and a6118a );
a6120a <=( a6119a and a6114a );
a6123a <=( (not A168) and (not A170) );
a6127a <=( (not A201) and (not A200) );
a6128a <=( A199 and a6127a );
a6129a <=( a6128a and a6123a );
a6133a <=( A298 and (not A203) );
a6134a <=( (not A202) and a6133a );
a6138a <=( A301 and A300 );
a6139a <=( (not A299) and a6138a );
a6140a <=( a6139a and a6134a );
a6143a <=( (not A168) and (not A170) );
a6147a <=( (not A201) and (not A200) );
a6148a <=( A199 and a6147a );
a6149a <=( a6148a and a6143a );
a6153a <=( A298 and (not A203) );
a6154a <=( (not A202) and a6153a );
a6158a <=( A302 and A300 );
a6159a <=( (not A299) and a6158a );
a6160a <=( a6159a and a6154a );
a6163a <=( (not A168) and (not A170) );
a6167a <=( (not A201) and (not A200) );
a6168a <=( A199 and a6167a );
a6169a <=( a6168a and a6163a );
a6173a <=( (not A298) and (not A203) );
a6174a <=( (not A202) and a6173a );
a6178a <=( A301 and A300 );
a6179a <=( A299 and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( (not A168) and (not A170) );
a6187a <=( (not A201) and (not A200) );
a6188a <=( A199 and a6187a );
a6189a <=( a6188a and a6183a );
a6193a <=( (not A298) and (not A203) );
a6194a <=( (not A202) and a6193a );
a6198a <=( A302 and A300 );
a6199a <=( A299 and a6198a );
a6200a <=( a6199a and a6194a );
a6203a <=( A168 and A169 );
a6207a <=( A201 and (not A166) );
a6208a <=( A167 and a6207a );
a6209a <=( a6208a and a6203a );
a6213a <=( A298 and (not A203) );
a6214a <=( (not A202) and a6213a );
a6218a <=( A301 and A300 );
a6219a <=( (not A299) and a6218a );
a6220a <=( a6219a and a6214a );
a6223a <=( A168 and A169 );
a6227a <=( A201 and (not A166) );
a6228a <=( A167 and a6227a );
a6229a <=( a6228a and a6223a );
a6233a <=( A298 and (not A203) );
a6234a <=( (not A202) and a6233a );
a6238a <=( A302 and A300 );
a6239a <=( (not A299) and a6238a );
a6240a <=( a6239a and a6234a );
a6243a <=( A168 and A169 );
a6247a <=( A201 and (not A166) );
a6248a <=( A167 and a6247a );
a6249a <=( a6248a and a6243a );
a6253a <=( (not A298) and (not A203) );
a6254a <=( (not A202) and a6253a );
a6258a <=( A301 and A300 );
a6259a <=( A299 and a6258a );
a6260a <=( a6259a and a6254a );
a6263a <=( A168 and A169 );
a6267a <=( A201 and (not A166) );
a6268a <=( A167 and a6267a );
a6269a <=( a6268a and a6263a );
a6273a <=( (not A298) and (not A203) );
a6274a <=( (not A202) and a6273a );
a6278a <=( A302 and A300 );
a6279a <=( A299 and a6278a );
a6280a <=( a6279a and a6274a );
a6283a <=( A168 and A169 );
a6287a <=( (not A201) and (not A166) );
a6288a <=( A167 and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A299) and A298 );
a6294a <=( A202 and a6293a );
a6298a <=( (not A302) and (not A301) );
a6299a <=( (not A300) and a6298a );
a6300a <=( a6299a and a6294a );
a6303a <=( A168 and A169 );
a6307a <=( (not A201) and (not A166) );
a6308a <=( A167 and a6307a );
a6309a <=( a6308a and a6303a );
a6313a <=( A299 and (not A298) );
a6314a <=( A202 and a6313a );
a6318a <=( (not A302) and (not A301) );
a6319a <=( (not A300) and a6318a );
a6320a <=( a6319a and a6314a );
a6323a <=( A168 and A169 );
a6327a <=( (not A201) and (not A166) );
a6328a <=( A167 and a6327a );
a6329a <=( a6328a and a6323a );
a6333a <=( (not A299) and A298 );
a6334a <=( A203 and a6333a );
a6338a <=( (not A302) and (not A301) );
a6339a <=( (not A300) and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A168 and A169 );
a6347a <=( (not A201) and (not A166) );
a6348a <=( A167 and a6347a );
a6349a <=( a6348a and a6343a );
a6353a <=( A299 and (not A298) );
a6354a <=( A203 and a6353a );
a6358a <=( (not A302) and (not A301) );
a6359a <=( (not A300) and a6358a );
a6360a <=( a6359a and a6354a );
a6363a <=( A168 and A169 );
a6367a <=( A199 and (not A166) );
a6368a <=( A167 and a6367a );
a6369a <=( a6368a and a6363a );
a6373a <=( (not A299) and A298 );
a6374a <=( A200 and a6373a );
a6378a <=( (not A302) and (not A301) );
a6379a <=( (not A300) and a6378a );
a6380a <=( a6379a and a6374a );
a6383a <=( A168 and A169 );
a6387a <=( A199 and (not A166) );
a6388a <=( A167 and a6387a );
a6389a <=( a6388a and a6383a );
a6393a <=( A299 and (not A298) );
a6394a <=( A200 and a6393a );
a6398a <=( (not A302) and (not A301) );
a6399a <=( (not A300) and a6398a );
a6400a <=( a6399a and a6394a );
a6403a <=( A168 and A169 );
a6407a <=( (not A199) and (not A166) );
a6408a <=( A167 and a6407a );
a6409a <=( a6408a and a6403a );
a6413a <=( (not A299) and A298 );
a6414a <=( (not A200) and a6413a );
a6418a <=( (not A302) and (not A301) );
a6419a <=( (not A300) and a6418a );
a6420a <=( a6419a and a6414a );
a6423a <=( A168 and A169 );
a6427a <=( (not A199) and (not A166) );
a6428a <=( A167 and a6427a );
a6429a <=( a6428a and a6423a );
a6433a <=( A299 and (not A298) );
a6434a <=( (not A200) and a6433a );
a6438a <=( (not A302) and (not A301) );
a6439a <=( (not A300) and a6438a );
a6440a <=( a6439a and a6434a );
a6443a <=( A168 and A169 );
a6447a <=( A201 and A166 );
a6448a <=( (not A167) and a6447a );
a6449a <=( a6448a and a6443a );
a6453a <=( A298 and (not A203) );
a6454a <=( (not A202) and a6453a );
a6458a <=( A301 and A300 );
a6459a <=( (not A299) and a6458a );
a6460a <=( a6459a and a6454a );
a6463a <=( A168 and A169 );
a6467a <=( A201 and A166 );
a6468a <=( (not A167) and a6467a );
a6469a <=( a6468a and a6463a );
a6473a <=( A298 and (not A203) );
a6474a <=( (not A202) and a6473a );
a6478a <=( A302 and A300 );
a6479a <=( (not A299) and a6478a );
a6480a <=( a6479a and a6474a );
a6483a <=( A168 and A169 );
a6487a <=( A201 and A166 );
a6488a <=( (not A167) and a6487a );
a6489a <=( a6488a and a6483a );
a6493a <=( (not A298) and (not A203) );
a6494a <=( (not A202) and a6493a );
a6498a <=( A301 and A300 );
a6499a <=( A299 and a6498a );
a6500a <=( a6499a and a6494a );
a6503a <=( A168 and A169 );
a6507a <=( A201 and A166 );
a6508a <=( (not A167) and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( (not A298) and (not A203) );
a6514a <=( (not A202) and a6513a );
a6518a <=( A302 and A300 );
a6519a <=( A299 and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A168 and A169 );
a6527a <=( (not A201) and A166 );
a6528a <=( (not A167) and a6527a );
a6529a <=( a6528a and a6523a );
a6533a <=( (not A299) and A298 );
a6534a <=( A202 and a6533a );
a6538a <=( (not A302) and (not A301) );
a6539a <=( (not A300) and a6538a );
a6540a <=( a6539a and a6534a );
a6543a <=( A168 and A169 );
a6547a <=( (not A201) and A166 );
a6548a <=( (not A167) and a6547a );
a6549a <=( a6548a and a6543a );
a6553a <=( A299 and (not A298) );
a6554a <=( A202 and a6553a );
a6558a <=( (not A302) and (not A301) );
a6559a <=( (not A300) and a6558a );
a6560a <=( a6559a and a6554a );
a6563a <=( A168 and A169 );
a6567a <=( (not A201) and A166 );
a6568a <=( (not A167) and a6567a );
a6569a <=( a6568a and a6563a );
a6573a <=( (not A299) and A298 );
a6574a <=( A203 and a6573a );
a6578a <=( (not A302) and (not A301) );
a6579a <=( (not A300) and a6578a );
a6580a <=( a6579a and a6574a );
a6583a <=( A168 and A169 );
a6587a <=( (not A201) and A166 );
a6588a <=( (not A167) and a6587a );
a6589a <=( a6588a and a6583a );
a6593a <=( A299 and (not A298) );
a6594a <=( A203 and a6593a );
a6598a <=( (not A302) and (not A301) );
a6599a <=( (not A300) and a6598a );
a6600a <=( a6599a and a6594a );
a6603a <=( A168 and A169 );
a6607a <=( A199 and A166 );
a6608a <=( (not A167) and a6607a );
a6609a <=( a6608a and a6603a );
a6613a <=( (not A299) and A298 );
a6614a <=( A200 and a6613a );
a6618a <=( (not A302) and (not A301) );
a6619a <=( (not A300) and a6618a );
a6620a <=( a6619a and a6614a );
a6623a <=( A168 and A169 );
a6627a <=( A199 and A166 );
a6628a <=( (not A167) and a6627a );
a6629a <=( a6628a and a6623a );
a6633a <=( A299 and (not A298) );
a6634a <=( A200 and a6633a );
a6638a <=( (not A302) and (not A301) );
a6639a <=( (not A300) and a6638a );
a6640a <=( a6639a and a6634a );
a6643a <=( A168 and A169 );
a6647a <=( (not A199) and A166 );
a6648a <=( (not A167) and a6647a );
a6649a <=( a6648a and a6643a );
a6653a <=( (not A299) and A298 );
a6654a <=( (not A200) and a6653a );
a6658a <=( (not A302) and (not A301) );
a6659a <=( (not A300) and a6658a );
a6660a <=( a6659a and a6654a );
a6663a <=( A168 and A169 );
a6667a <=( (not A199) and A166 );
a6668a <=( (not A167) and a6667a );
a6669a <=( a6668a and a6663a );
a6673a <=( A299 and (not A298) );
a6674a <=( (not A200) and a6673a );
a6678a <=( (not A302) and (not A301) );
a6679a <=( (not A300) and a6678a );
a6680a <=( a6679a and a6674a );
a6683a <=( (not A168) and A169 );
a6687a <=( A201 and A200 );
a6688a <=( (not A199) and a6687a );
a6689a <=( a6688a and a6683a );
a6693a <=( (not A299) and A298 );
a6694a <=( A202 and a6693a );
a6698a <=( (not A302) and (not A301) );
a6699a <=( (not A300) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( (not A168) and A169 );
a6707a <=( A201 and A200 );
a6708a <=( (not A199) and a6707a );
a6709a <=( a6708a and a6703a );
a6713a <=( A299 and (not A298) );
a6714a <=( A202 and a6713a );
a6718a <=( (not A302) and (not A301) );
a6719a <=( (not A300) and a6718a );
a6720a <=( a6719a and a6714a );
a6723a <=( (not A168) and A169 );
a6727a <=( A201 and A200 );
a6728a <=( (not A199) and a6727a );
a6729a <=( a6728a and a6723a );
a6733a <=( (not A299) and A298 );
a6734a <=( A203 and a6733a );
a6738a <=( (not A302) and (not A301) );
a6739a <=( (not A300) and a6738a );
a6740a <=( a6739a and a6734a );
a6743a <=( (not A168) and A169 );
a6747a <=( A201 and A200 );
a6748a <=( (not A199) and a6747a );
a6749a <=( a6748a and a6743a );
a6753a <=( A299 and (not A298) );
a6754a <=( A203 and a6753a );
a6758a <=( (not A302) and (not A301) );
a6759a <=( (not A300) and a6758a );
a6760a <=( a6759a and a6754a );
a6763a <=( (not A168) and A169 );
a6767a <=( (not A201) and A200 );
a6768a <=( (not A199) and a6767a );
a6769a <=( a6768a and a6763a );
a6773a <=( A298 and (not A203) );
a6774a <=( (not A202) and a6773a );
a6778a <=( A301 and A300 );
a6779a <=( (not A299) and a6778a );
a6780a <=( a6779a and a6774a );
a6783a <=( (not A168) and A169 );
a6787a <=( (not A201) and A200 );
a6788a <=( (not A199) and a6787a );
a6789a <=( a6788a and a6783a );
a6793a <=( A298 and (not A203) );
a6794a <=( (not A202) and a6793a );
a6798a <=( A302 and A300 );
a6799a <=( (not A299) and a6798a );
a6800a <=( a6799a and a6794a );
a6803a <=( (not A168) and A169 );
a6807a <=( (not A201) and A200 );
a6808a <=( (not A199) and a6807a );
a6809a <=( a6808a and a6803a );
a6813a <=( (not A298) and (not A203) );
a6814a <=( (not A202) and a6813a );
a6818a <=( A301 and A300 );
a6819a <=( A299 and a6818a );
a6820a <=( a6819a and a6814a );
a6823a <=( (not A168) and A169 );
a6827a <=( (not A201) and A200 );
a6828a <=( (not A199) and a6827a );
a6829a <=( a6828a and a6823a );
a6833a <=( (not A298) and (not A203) );
a6834a <=( (not A202) and a6833a );
a6838a <=( A302 and A300 );
a6839a <=( A299 and a6838a );
a6840a <=( a6839a and a6834a );
a6843a <=( (not A168) and A169 );
a6847a <=( A201 and (not A200) );
a6848a <=( A199 and a6847a );
a6849a <=( a6848a and a6843a );
a6853a <=( (not A299) and A298 );
a6854a <=( A202 and a6853a );
a6858a <=( (not A302) and (not A301) );
a6859a <=( (not A300) and a6858a );
a6860a <=( a6859a and a6854a );
a6863a <=( (not A168) and A169 );
a6867a <=( A201 and (not A200) );
a6868a <=( A199 and a6867a );
a6869a <=( a6868a and a6863a );
a6873a <=( A299 and (not A298) );
a6874a <=( A202 and a6873a );
a6878a <=( (not A302) and (not A301) );
a6879a <=( (not A300) and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( (not A168) and A169 );
a6887a <=( A201 and (not A200) );
a6888a <=( A199 and a6887a );
a6889a <=( a6888a and a6883a );
a6893a <=( (not A299) and A298 );
a6894a <=( A203 and a6893a );
a6898a <=( (not A302) and (not A301) );
a6899a <=( (not A300) and a6898a );
a6900a <=( a6899a and a6894a );
a6903a <=( (not A168) and A169 );
a6907a <=( A201 and (not A200) );
a6908a <=( A199 and a6907a );
a6909a <=( a6908a and a6903a );
a6913a <=( A299 and (not A298) );
a6914a <=( A203 and a6913a );
a6918a <=( (not A302) and (not A301) );
a6919a <=( (not A300) and a6918a );
a6920a <=( a6919a and a6914a );
a6923a <=( (not A168) and A169 );
a6927a <=( (not A201) and (not A200) );
a6928a <=( A199 and a6927a );
a6929a <=( a6928a and a6923a );
a6933a <=( A298 and (not A203) );
a6934a <=( (not A202) and a6933a );
a6938a <=( A301 and A300 );
a6939a <=( (not A299) and a6938a );
a6940a <=( a6939a and a6934a );
a6943a <=( (not A168) and A169 );
a6947a <=( (not A201) and (not A200) );
a6948a <=( A199 and a6947a );
a6949a <=( a6948a and a6943a );
a6953a <=( A298 and (not A203) );
a6954a <=( (not A202) and a6953a );
a6958a <=( A302 and A300 );
a6959a <=( (not A299) and a6958a );
a6960a <=( a6959a and a6954a );
a6963a <=( (not A168) and A169 );
a6967a <=( (not A201) and (not A200) );
a6968a <=( A199 and a6967a );
a6969a <=( a6968a and a6963a );
a6973a <=( (not A298) and (not A203) );
a6974a <=( (not A202) and a6973a );
a6978a <=( A301 and A300 );
a6979a <=( A299 and a6978a );
a6980a <=( a6979a and a6974a );
a6983a <=( (not A168) and A169 );
a6987a <=( (not A201) and (not A200) );
a6988a <=( A199 and a6987a );
a6989a <=( a6988a and a6983a );
a6993a <=( (not A298) and (not A203) );
a6994a <=( (not A202) and a6993a );
a6998a <=( A302 and A300 );
a6999a <=( A299 and a6998a );
a7000a <=( a6999a and a6994a );
a7003a <=( (not A169) and A170 );
a7007a <=( A200 and (not A199) );
a7008a <=( A168 and a7007a );
a7009a <=( a7008a and a7003a );
a7013a <=( A298 and A202 );
a7014a <=( A201 and a7013a );
a7018a <=( A301 and A300 );
a7019a <=( (not A299) and a7018a );
a7020a <=( a7019a and a7014a );
a7023a <=( (not A169) and A170 );
a7027a <=( A200 and (not A199) );
a7028a <=( A168 and a7027a );
a7029a <=( a7028a and a7023a );
a7033a <=( A298 and A202 );
a7034a <=( A201 and a7033a );
a7038a <=( A302 and A300 );
a7039a <=( (not A299) and a7038a );
a7040a <=( a7039a and a7034a );
a7043a <=( (not A169) and A170 );
a7047a <=( A200 and (not A199) );
a7048a <=( A168 and a7047a );
a7049a <=( a7048a and a7043a );
a7053a <=( (not A298) and A202 );
a7054a <=( A201 and a7053a );
a7058a <=( A301 and A300 );
a7059a <=( A299 and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( (not A169) and A170 );
a7067a <=( A200 and (not A199) );
a7068a <=( A168 and a7067a );
a7069a <=( a7068a and a7063a );
a7073a <=( (not A298) and A202 );
a7074a <=( A201 and a7073a );
a7078a <=( A302 and A300 );
a7079a <=( A299 and a7078a );
a7080a <=( a7079a and a7074a );
a7083a <=( (not A169) and A170 );
a7087a <=( A200 and (not A199) );
a7088a <=( A168 and a7087a );
a7089a <=( a7088a and a7083a );
a7093a <=( A298 and A203 );
a7094a <=( A201 and a7093a );
a7098a <=( A301 and A300 );
a7099a <=( (not A299) and a7098a );
a7100a <=( a7099a and a7094a );
a7103a <=( (not A169) and A170 );
a7107a <=( A200 and (not A199) );
a7108a <=( A168 and a7107a );
a7109a <=( a7108a and a7103a );
a7113a <=( A298 and A203 );
a7114a <=( A201 and a7113a );
a7118a <=( A302 and A300 );
a7119a <=( (not A299) and a7118a );
a7120a <=( a7119a and a7114a );
a7123a <=( (not A169) and A170 );
a7127a <=( A200 and (not A199) );
a7128a <=( A168 and a7127a );
a7129a <=( a7128a and a7123a );
a7133a <=( (not A298) and A203 );
a7134a <=( A201 and a7133a );
a7138a <=( A301 and A300 );
a7139a <=( A299 and a7138a );
a7140a <=( a7139a and a7134a );
a7143a <=( (not A169) and A170 );
a7147a <=( A200 and (not A199) );
a7148a <=( A168 and a7147a );
a7149a <=( a7148a and a7143a );
a7153a <=( (not A298) and A203 );
a7154a <=( A201 and a7153a );
a7158a <=( A302 and A300 );
a7159a <=( A299 and a7158a );
a7160a <=( a7159a and a7154a );
a7163a <=( (not A169) and A170 );
a7167a <=( (not A200) and A199 );
a7168a <=( A168 and a7167a );
a7169a <=( a7168a and a7163a );
a7173a <=( A298 and A202 );
a7174a <=( A201 and a7173a );
a7178a <=( A301 and A300 );
a7179a <=( (not A299) and a7178a );
a7180a <=( a7179a and a7174a );
a7183a <=( (not A169) and A170 );
a7187a <=( (not A200) and A199 );
a7188a <=( A168 and a7187a );
a7189a <=( a7188a and a7183a );
a7193a <=( A298 and A202 );
a7194a <=( A201 and a7193a );
a7198a <=( A302 and A300 );
a7199a <=( (not A299) and a7198a );
a7200a <=( a7199a and a7194a );
a7203a <=( (not A169) and A170 );
a7207a <=( (not A200) and A199 );
a7208a <=( A168 and a7207a );
a7209a <=( a7208a and a7203a );
a7213a <=( (not A298) and A202 );
a7214a <=( A201 and a7213a );
a7218a <=( A301 and A300 );
a7219a <=( A299 and a7218a );
a7220a <=( a7219a and a7214a );
a7223a <=( (not A169) and A170 );
a7227a <=( (not A200) and A199 );
a7228a <=( A168 and a7227a );
a7229a <=( a7228a and a7223a );
a7233a <=( (not A298) and A202 );
a7234a <=( A201 and a7233a );
a7238a <=( A302 and A300 );
a7239a <=( A299 and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( (not A169) and A170 );
a7247a <=( (not A200) and A199 );
a7248a <=( A168 and a7247a );
a7249a <=( a7248a and a7243a );
a7253a <=( A298 and A203 );
a7254a <=( A201 and a7253a );
a7258a <=( A301 and A300 );
a7259a <=( (not A299) and a7258a );
a7260a <=( a7259a and a7254a );
a7263a <=( (not A169) and A170 );
a7267a <=( (not A200) and A199 );
a7268a <=( A168 and a7267a );
a7269a <=( a7268a and a7263a );
a7273a <=( A298 and A203 );
a7274a <=( A201 and a7273a );
a7278a <=( A302 and A300 );
a7279a <=( (not A299) and a7278a );
a7280a <=( a7279a and a7274a );
a7283a <=( (not A169) and A170 );
a7287a <=( (not A200) and A199 );
a7288a <=( A168 and a7287a );
a7289a <=( a7288a and a7283a );
a7293a <=( (not A298) and A203 );
a7294a <=( A201 and a7293a );
a7298a <=( A301 and A300 );
a7299a <=( A299 and a7298a );
a7300a <=( a7299a and a7294a );
a7303a <=( (not A169) and A170 );
a7307a <=( (not A200) and A199 );
a7308a <=( A168 and a7307a );
a7309a <=( a7308a and a7303a );
a7313a <=( (not A298) and A203 );
a7314a <=( A201 and a7313a );
a7318a <=( A302 and A300 );
a7319a <=( A299 and a7318a );
a7320a <=( a7319a and a7314a );
a7323a <=( (not A169) and A170 );
a7327a <=( (not A166) and A167 );
a7328a <=( (not A168) and a7327a );
a7329a <=( a7328a and a7323a );
a7333a <=( A298 and A202 );
a7334a <=( (not A201) and a7333a );
a7338a <=( A301 and A300 );
a7339a <=( (not A299) and a7338a );
a7340a <=( a7339a and a7334a );
a7343a <=( (not A169) and A170 );
a7347a <=( (not A166) and A167 );
a7348a <=( (not A168) and a7347a );
a7349a <=( a7348a and a7343a );
a7353a <=( A298 and A202 );
a7354a <=( (not A201) and a7353a );
a7358a <=( A302 and A300 );
a7359a <=( (not A299) and a7358a );
a7360a <=( a7359a and a7354a );
a7363a <=( (not A169) and A170 );
a7367a <=( (not A166) and A167 );
a7368a <=( (not A168) and a7367a );
a7369a <=( a7368a and a7363a );
a7373a <=( (not A298) and A202 );
a7374a <=( (not A201) and a7373a );
a7378a <=( A301 and A300 );
a7379a <=( A299 and a7378a );
a7380a <=( a7379a and a7374a );
a7383a <=( (not A169) and A170 );
a7387a <=( (not A166) and A167 );
a7388a <=( (not A168) and a7387a );
a7389a <=( a7388a and a7383a );
a7393a <=( (not A298) and A202 );
a7394a <=( (not A201) and a7393a );
a7398a <=( A302 and A300 );
a7399a <=( A299 and a7398a );
a7400a <=( a7399a and a7394a );
a7403a <=( (not A169) and A170 );
a7407a <=( (not A166) and A167 );
a7408a <=( (not A168) and a7407a );
a7409a <=( a7408a and a7403a );
a7413a <=( A298 and A203 );
a7414a <=( (not A201) and a7413a );
a7418a <=( A301 and A300 );
a7419a <=( (not A299) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( (not A169) and A170 );
a7427a <=( (not A166) and A167 );
a7428a <=( (not A168) and a7427a );
a7429a <=( a7428a and a7423a );
a7433a <=( A298 and A203 );
a7434a <=( (not A201) and a7433a );
a7438a <=( A302 and A300 );
a7439a <=( (not A299) and a7438a );
a7440a <=( a7439a and a7434a );
a7443a <=( (not A169) and A170 );
a7447a <=( (not A166) and A167 );
a7448a <=( (not A168) and a7447a );
a7449a <=( a7448a and a7443a );
a7453a <=( (not A298) and A203 );
a7454a <=( (not A201) and a7453a );
a7458a <=( A301 and A300 );
a7459a <=( A299 and a7458a );
a7460a <=( a7459a and a7454a );
a7463a <=( (not A169) and A170 );
a7467a <=( (not A166) and A167 );
a7468a <=( (not A168) and a7467a );
a7469a <=( a7468a and a7463a );
a7473a <=( (not A298) and A203 );
a7474a <=( (not A201) and a7473a );
a7478a <=( A302 and A300 );
a7479a <=( A299 and a7478a );
a7480a <=( a7479a and a7474a );
a7483a <=( (not A169) and A170 );
a7487a <=( (not A166) and A167 );
a7488a <=( (not A168) and a7487a );
a7489a <=( a7488a and a7483a );
a7493a <=( A298 and A200 );
a7494a <=( A199 and a7493a );
a7498a <=( A301 and A300 );
a7499a <=( (not A299) and a7498a );
a7500a <=( a7499a and a7494a );
a7503a <=( (not A169) and A170 );
a7507a <=( (not A166) and A167 );
a7508a <=( (not A168) and a7507a );
a7509a <=( a7508a and a7503a );
a7513a <=( A298 and A200 );
a7514a <=( A199 and a7513a );
a7518a <=( A302 and A300 );
a7519a <=( (not A299) and a7518a );
a7520a <=( a7519a and a7514a );
a7523a <=( (not A169) and A170 );
a7527a <=( (not A166) and A167 );
a7528a <=( (not A168) and a7527a );
a7529a <=( a7528a and a7523a );
a7533a <=( (not A298) and A200 );
a7534a <=( A199 and a7533a );
a7538a <=( A301 and A300 );
a7539a <=( A299 and a7538a );
a7540a <=( a7539a and a7534a );
a7543a <=( (not A169) and A170 );
a7547a <=( (not A166) and A167 );
a7548a <=( (not A168) and a7547a );
a7549a <=( a7548a and a7543a );
a7553a <=( (not A298) and A200 );
a7554a <=( A199 and a7553a );
a7558a <=( A302 and A300 );
a7559a <=( A299 and a7558a );
a7560a <=( a7559a and a7554a );
a7563a <=( (not A169) and A170 );
a7567a <=( (not A166) and A167 );
a7568a <=( (not A168) and a7567a );
a7569a <=( a7568a and a7563a );
a7573a <=( A298 and (not A200) );
a7574a <=( (not A199) and a7573a );
a7578a <=( A301 and A300 );
a7579a <=( (not A299) and a7578a );
a7580a <=( a7579a and a7574a );
a7583a <=( (not A169) and A170 );
a7587a <=( (not A166) and A167 );
a7588a <=( (not A168) and a7587a );
a7589a <=( a7588a and a7583a );
a7593a <=( A298 and (not A200) );
a7594a <=( (not A199) and a7593a );
a7598a <=( A302 and A300 );
a7599a <=( (not A299) and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( (not A169) and A170 );
a7607a <=( (not A166) and A167 );
a7608a <=( (not A168) and a7607a );
a7609a <=( a7608a and a7603a );
a7613a <=( (not A298) and (not A200) );
a7614a <=( (not A199) and a7613a );
a7618a <=( A301 and A300 );
a7619a <=( A299 and a7618a );
a7620a <=( a7619a and a7614a );
a7623a <=( (not A169) and A170 );
a7627a <=( (not A166) and A167 );
a7628a <=( (not A168) and a7627a );
a7629a <=( a7628a and a7623a );
a7633a <=( (not A298) and (not A200) );
a7634a <=( (not A199) and a7633a );
a7638a <=( A302 and A300 );
a7639a <=( A299 and a7638a );
a7640a <=( a7639a and a7634a );
a7643a <=( (not A169) and A170 );
a7647a <=( A166 and (not A167) );
a7648a <=( (not A168) and a7647a );
a7649a <=( a7648a and a7643a );
a7653a <=( A298 and A202 );
a7654a <=( (not A201) and a7653a );
a7658a <=( A301 and A300 );
a7659a <=( (not A299) and a7658a );
a7660a <=( a7659a and a7654a );
a7663a <=( (not A169) and A170 );
a7667a <=( A166 and (not A167) );
a7668a <=( (not A168) and a7667a );
a7669a <=( a7668a and a7663a );
a7673a <=( A298 and A202 );
a7674a <=( (not A201) and a7673a );
a7678a <=( A302 and A300 );
a7679a <=( (not A299) and a7678a );
a7680a <=( a7679a and a7674a );
a7683a <=( (not A169) and A170 );
a7687a <=( A166 and (not A167) );
a7688a <=( (not A168) and a7687a );
a7689a <=( a7688a and a7683a );
a7693a <=( (not A298) and A202 );
a7694a <=( (not A201) and a7693a );
a7698a <=( A301 and A300 );
a7699a <=( A299 and a7698a );
a7700a <=( a7699a and a7694a );
a7703a <=( (not A169) and A170 );
a7707a <=( A166 and (not A167) );
a7708a <=( (not A168) and a7707a );
a7709a <=( a7708a and a7703a );
a7713a <=( (not A298) and A202 );
a7714a <=( (not A201) and a7713a );
a7718a <=( A302 and A300 );
a7719a <=( A299 and a7718a );
a7720a <=( a7719a and a7714a );
a7723a <=( (not A169) and A170 );
a7727a <=( A166 and (not A167) );
a7728a <=( (not A168) and a7727a );
a7729a <=( a7728a and a7723a );
a7733a <=( A298 and A203 );
a7734a <=( (not A201) and a7733a );
a7738a <=( A301 and A300 );
a7739a <=( (not A299) and a7738a );
a7740a <=( a7739a and a7734a );
a7743a <=( (not A169) and A170 );
a7747a <=( A166 and (not A167) );
a7748a <=( (not A168) and a7747a );
a7749a <=( a7748a and a7743a );
a7753a <=( A298 and A203 );
a7754a <=( (not A201) and a7753a );
a7758a <=( A302 and A300 );
a7759a <=( (not A299) and a7758a );
a7760a <=( a7759a and a7754a );
a7763a <=( (not A169) and A170 );
a7767a <=( A166 and (not A167) );
a7768a <=( (not A168) and a7767a );
a7769a <=( a7768a and a7763a );
a7773a <=( (not A298) and A203 );
a7774a <=( (not A201) and a7773a );
a7778a <=( A301 and A300 );
a7779a <=( A299 and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( (not A169) and A170 );
a7787a <=( A166 and (not A167) );
a7788a <=( (not A168) and a7787a );
a7789a <=( a7788a and a7783a );
a7793a <=( (not A298) and A203 );
a7794a <=( (not A201) and a7793a );
a7798a <=( A302 and A300 );
a7799a <=( A299 and a7798a );
a7800a <=( a7799a and a7794a );
a7803a <=( (not A169) and A170 );
a7807a <=( A166 and (not A167) );
a7808a <=( (not A168) and a7807a );
a7809a <=( a7808a and a7803a );
a7813a <=( A298 and A200 );
a7814a <=( A199 and a7813a );
a7818a <=( A301 and A300 );
a7819a <=( (not A299) and a7818a );
a7820a <=( a7819a and a7814a );
a7823a <=( (not A169) and A170 );
a7827a <=( A166 and (not A167) );
a7828a <=( (not A168) and a7827a );
a7829a <=( a7828a and a7823a );
a7833a <=( A298 and A200 );
a7834a <=( A199 and a7833a );
a7838a <=( A302 and A300 );
a7839a <=( (not A299) and a7838a );
a7840a <=( a7839a and a7834a );
a7843a <=( (not A169) and A170 );
a7847a <=( A166 and (not A167) );
a7848a <=( (not A168) and a7847a );
a7849a <=( a7848a and a7843a );
a7853a <=( (not A298) and A200 );
a7854a <=( A199 and a7853a );
a7858a <=( A301 and A300 );
a7859a <=( A299 and a7858a );
a7860a <=( a7859a and a7854a );
a7863a <=( (not A169) and A170 );
a7867a <=( A166 and (not A167) );
a7868a <=( (not A168) and a7867a );
a7869a <=( a7868a and a7863a );
a7873a <=( (not A298) and A200 );
a7874a <=( A199 and a7873a );
a7878a <=( A302 and A300 );
a7879a <=( A299 and a7878a );
a7880a <=( a7879a and a7874a );
a7883a <=( (not A169) and A170 );
a7887a <=( A166 and (not A167) );
a7888a <=( (not A168) and a7887a );
a7889a <=( a7888a and a7883a );
a7893a <=( A298 and (not A200) );
a7894a <=( (not A199) and a7893a );
a7898a <=( A301 and A300 );
a7899a <=( (not A299) and a7898a );
a7900a <=( a7899a and a7894a );
a7903a <=( (not A169) and A170 );
a7907a <=( A166 and (not A167) );
a7908a <=( (not A168) and a7907a );
a7909a <=( a7908a and a7903a );
a7913a <=( A298 and (not A200) );
a7914a <=( (not A199) and a7913a );
a7918a <=( A302 and A300 );
a7919a <=( (not A299) and a7918a );
a7920a <=( a7919a and a7914a );
a7923a <=( (not A169) and A170 );
a7927a <=( A166 and (not A167) );
a7928a <=( (not A168) and a7927a );
a7929a <=( a7928a and a7923a );
a7933a <=( (not A298) and (not A200) );
a7934a <=( (not A199) and a7933a );
a7938a <=( A301 and A300 );
a7939a <=( A299 and a7938a );
a7940a <=( a7939a and a7934a );
a7943a <=( (not A169) and A170 );
a7947a <=( A166 and (not A167) );
a7948a <=( (not A168) and a7947a );
a7949a <=( a7948a and a7943a );
a7953a <=( (not A298) and (not A200) );
a7954a <=( (not A199) and a7953a );
a7958a <=( A302 and A300 );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7964a <=( (not A199) and A166 );
a7965a <=( A167 and a7964a );
a7969a <=( (not A202) and (not A201) );
a7970a <=( A200 and a7969a );
a7971a <=( a7970a and a7965a );
a7975a <=( (not A299) and A298 );
a7976a <=( (not A203) and a7975a );
a7980a <=( (not A302) and (not A301) );
a7981a <=( (not A300) and a7980a );
a7982a <=( a7981a and a7976a );
a7986a <=( (not A199) and A166 );
a7987a <=( A167 and a7986a );
a7991a <=( (not A202) and (not A201) );
a7992a <=( A200 and a7991a );
a7993a <=( a7992a and a7987a );
a7997a <=( A299 and (not A298) );
a7998a <=( (not A203) and a7997a );
a8002a <=( (not A302) and (not A301) );
a8003a <=( (not A300) and a8002a );
a8004a <=( a8003a and a7998a );
a8008a <=( A199 and A166 );
a8009a <=( A167 and a8008a );
a8013a <=( (not A202) and (not A201) );
a8014a <=( (not A200) and a8013a );
a8015a <=( a8014a and a8009a );
a8019a <=( (not A299) and A298 );
a8020a <=( (not A203) and a8019a );
a8024a <=( (not A302) and (not A301) );
a8025a <=( (not A300) and a8024a );
a8026a <=( a8025a and a8020a );
a8030a <=( A199 and A166 );
a8031a <=( A167 and a8030a );
a8035a <=( (not A202) and (not A201) );
a8036a <=( (not A200) and a8035a );
a8037a <=( a8036a and a8031a );
a8041a <=( A299 and (not A298) );
a8042a <=( (not A203) and a8041a );
a8046a <=( (not A302) and (not A301) );
a8047a <=( (not A300) and a8046a );
a8048a <=( a8047a and a8042a );
a8052a <=( (not A199) and (not A166) );
a8053a <=( (not A167) and a8052a );
a8057a <=( (not A202) and (not A201) );
a8058a <=( A200 and a8057a );
a8059a <=( a8058a and a8053a );
a8063a <=( (not A299) and A298 );
a8064a <=( (not A203) and a8063a );
a8068a <=( (not A302) and (not A301) );
a8069a <=( (not A300) and a8068a );
a8070a <=( a8069a and a8064a );
a8074a <=( (not A199) and (not A166) );
a8075a <=( (not A167) and a8074a );
a8079a <=( (not A202) and (not A201) );
a8080a <=( A200 and a8079a );
a8081a <=( a8080a and a8075a );
a8085a <=( A299 and (not A298) );
a8086a <=( (not A203) and a8085a );
a8090a <=( (not A302) and (not A301) );
a8091a <=( (not A300) and a8090a );
a8092a <=( a8091a and a8086a );
a8096a <=( A199 and (not A166) );
a8097a <=( (not A167) and a8096a );
a8101a <=( (not A202) and (not A201) );
a8102a <=( (not A200) and a8101a );
a8103a <=( a8102a and a8097a );
a8107a <=( (not A299) and A298 );
a8108a <=( (not A203) and a8107a );
a8112a <=( (not A302) and (not A301) );
a8113a <=( (not A300) and a8112a );
a8114a <=( a8113a and a8108a );
a8118a <=( A199 and (not A166) );
a8119a <=( (not A167) and a8118a );
a8123a <=( (not A202) and (not A201) );
a8124a <=( (not A200) and a8123a );
a8125a <=( a8124a and a8119a );
a8129a <=( A299 and (not A298) );
a8130a <=( (not A203) and a8129a );
a8134a <=( (not A302) and (not A301) );
a8135a <=( (not A300) and a8134a );
a8136a <=( a8135a and a8130a );
a8140a <=( A167 and A168 );
a8141a <=( (not A170) and a8140a );
a8145a <=( (not A202) and A201 );
a8146a <=( (not A166) and a8145a );
a8147a <=( a8146a and a8141a );
a8151a <=( (not A299) and A298 );
a8152a <=( (not A203) and a8151a );
a8156a <=( (not A302) and (not A301) );
a8157a <=( (not A300) and a8156a );
a8158a <=( a8157a and a8152a );
a8162a <=( A167 and A168 );
a8163a <=( (not A170) and a8162a );
a8167a <=( (not A202) and A201 );
a8168a <=( (not A166) and a8167a );
a8169a <=( a8168a and a8163a );
a8173a <=( A299 and (not A298) );
a8174a <=( (not A203) and a8173a );
a8178a <=( (not A302) and (not A301) );
a8179a <=( (not A300) and a8178a );
a8180a <=( a8179a and a8174a );
a8184a <=( (not A167) and A168 );
a8185a <=( (not A170) and a8184a );
a8189a <=( (not A202) and A201 );
a8190a <=( A166 and a8189a );
a8191a <=( a8190a and a8185a );
a8195a <=( (not A299) and A298 );
a8196a <=( (not A203) and a8195a );
a8200a <=( (not A302) and (not A301) );
a8201a <=( (not A300) and a8200a );
a8202a <=( a8201a and a8196a );
a8206a <=( (not A167) and A168 );
a8207a <=( (not A170) and a8206a );
a8211a <=( (not A202) and A201 );
a8212a <=( A166 and a8211a );
a8213a <=( a8212a and a8207a );
a8217a <=( A299 and (not A298) );
a8218a <=( (not A203) and a8217a );
a8222a <=( (not A302) and (not A301) );
a8223a <=( (not A300) and a8222a );
a8224a <=( a8223a and a8218a );
a8228a <=( (not A199) and (not A168) );
a8229a <=( (not A170) and a8228a );
a8233a <=( (not A202) and (not A201) );
a8234a <=( A200 and a8233a );
a8235a <=( a8234a and a8229a );
a8239a <=( (not A299) and A298 );
a8240a <=( (not A203) and a8239a );
a8244a <=( (not A302) and (not A301) );
a8245a <=( (not A300) and a8244a );
a8246a <=( a8245a and a8240a );
a8250a <=( (not A199) and (not A168) );
a8251a <=( (not A170) and a8250a );
a8255a <=( (not A202) and (not A201) );
a8256a <=( A200 and a8255a );
a8257a <=( a8256a and a8251a );
a8261a <=( A299 and (not A298) );
a8262a <=( (not A203) and a8261a );
a8266a <=( (not A302) and (not A301) );
a8267a <=( (not A300) and a8266a );
a8268a <=( a8267a and a8262a );
a8272a <=( A199 and (not A168) );
a8273a <=( (not A170) and a8272a );
a8277a <=( (not A202) and (not A201) );
a8278a <=( (not A200) and a8277a );
a8279a <=( a8278a and a8273a );
a8283a <=( (not A299) and A298 );
a8284a <=( (not A203) and a8283a );
a8288a <=( (not A302) and (not A301) );
a8289a <=( (not A300) and a8288a );
a8290a <=( a8289a and a8284a );
a8294a <=( A199 and (not A168) );
a8295a <=( (not A170) and a8294a );
a8299a <=( (not A202) and (not A201) );
a8300a <=( (not A200) and a8299a );
a8301a <=( a8300a and a8295a );
a8305a <=( A299 and (not A298) );
a8306a <=( (not A203) and a8305a );
a8310a <=( (not A302) and (not A301) );
a8311a <=( (not A300) and a8310a );
a8312a <=( a8311a and a8306a );
a8316a <=( A167 and A168 );
a8317a <=( A169 and a8316a );
a8321a <=( (not A202) and A201 );
a8322a <=( (not A166) and a8321a );
a8323a <=( a8322a and a8317a );
a8327a <=( (not A299) and A298 );
a8328a <=( (not A203) and a8327a );
a8332a <=( (not A302) and (not A301) );
a8333a <=( (not A300) and a8332a );
a8334a <=( a8333a and a8328a );
a8338a <=( A167 and A168 );
a8339a <=( A169 and a8338a );
a8343a <=( (not A202) and A201 );
a8344a <=( (not A166) and a8343a );
a8345a <=( a8344a and a8339a );
a8349a <=( A299 and (not A298) );
a8350a <=( (not A203) and a8349a );
a8354a <=( (not A302) and (not A301) );
a8355a <=( (not A300) and a8354a );
a8356a <=( a8355a and a8350a );
a8360a <=( (not A167) and A168 );
a8361a <=( A169 and a8360a );
a8365a <=( (not A202) and A201 );
a8366a <=( A166 and a8365a );
a8367a <=( a8366a and a8361a );
a8371a <=( (not A299) and A298 );
a8372a <=( (not A203) and a8371a );
a8376a <=( (not A302) and (not A301) );
a8377a <=( (not A300) and a8376a );
a8378a <=( a8377a and a8372a );
a8382a <=( (not A167) and A168 );
a8383a <=( A169 and a8382a );
a8387a <=( (not A202) and A201 );
a8388a <=( A166 and a8387a );
a8389a <=( a8388a and a8383a );
a8393a <=( A299 and (not A298) );
a8394a <=( (not A203) and a8393a );
a8398a <=( (not A302) and (not A301) );
a8399a <=( (not A300) and a8398a );
a8400a <=( a8399a and a8394a );
a8404a <=( (not A199) and (not A168) );
a8405a <=( A169 and a8404a );
a8409a <=( (not A202) and (not A201) );
a8410a <=( A200 and a8409a );
a8411a <=( a8410a and a8405a );
a8415a <=( (not A299) and A298 );
a8416a <=( (not A203) and a8415a );
a8420a <=( (not A302) and (not A301) );
a8421a <=( (not A300) and a8420a );
a8422a <=( a8421a and a8416a );
a8426a <=( (not A199) and (not A168) );
a8427a <=( A169 and a8426a );
a8431a <=( (not A202) and (not A201) );
a8432a <=( A200 and a8431a );
a8433a <=( a8432a and a8427a );
a8437a <=( A299 and (not A298) );
a8438a <=( (not A203) and a8437a );
a8442a <=( (not A302) and (not A301) );
a8443a <=( (not A300) and a8442a );
a8444a <=( a8443a and a8438a );
a8448a <=( A199 and (not A168) );
a8449a <=( A169 and a8448a );
a8453a <=( (not A202) and (not A201) );
a8454a <=( (not A200) and a8453a );
a8455a <=( a8454a and a8449a );
a8459a <=( (not A299) and A298 );
a8460a <=( (not A203) and a8459a );
a8464a <=( (not A302) and (not A301) );
a8465a <=( (not A300) and a8464a );
a8466a <=( a8465a and a8460a );
a8470a <=( A199 and (not A168) );
a8471a <=( A169 and a8470a );
a8475a <=( (not A202) and (not A201) );
a8476a <=( (not A200) and a8475a );
a8477a <=( a8476a and a8471a );
a8481a <=( A299 and (not A298) );
a8482a <=( (not A203) and a8481a );
a8486a <=( (not A302) and (not A301) );
a8487a <=( (not A300) and a8486a );
a8488a <=( a8487a and a8482a );
a8492a <=( A168 and (not A169) );
a8493a <=( A170 and a8492a );
a8497a <=( A201 and A200 );
a8498a <=( (not A199) and a8497a );
a8499a <=( a8498a and a8493a );
a8503a <=( (not A299) and A298 );
a8504a <=( A202 and a8503a );
a8508a <=( (not A302) and (not A301) );
a8509a <=( (not A300) and a8508a );
a8510a <=( a8509a and a8504a );
a8514a <=( A168 and (not A169) );
a8515a <=( A170 and a8514a );
a8519a <=( A201 and A200 );
a8520a <=( (not A199) and a8519a );
a8521a <=( a8520a and a8515a );
a8525a <=( A299 and (not A298) );
a8526a <=( A202 and a8525a );
a8530a <=( (not A302) and (not A301) );
a8531a <=( (not A300) and a8530a );
a8532a <=( a8531a and a8526a );
a8536a <=( A168 and (not A169) );
a8537a <=( A170 and a8536a );
a8541a <=( A201 and A200 );
a8542a <=( (not A199) and a8541a );
a8543a <=( a8542a and a8537a );
a8547a <=( (not A299) and A298 );
a8548a <=( A203 and a8547a );
a8552a <=( (not A302) and (not A301) );
a8553a <=( (not A300) and a8552a );
a8554a <=( a8553a and a8548a );
a8558a <=( A168 and (not A169) );
a8559a <=( A170 and a8558a );
a8563a <=( A201 and A200 );
a8564a <=( (not A199) and a8563a );
a8565a <=( a8564a and a8559a );
a8569a <=( A299 and (not A298) );
a8570a <=( A203 and a8569a );
a8574a <=( (not A302) and (not A301) );
a8575a <=( (not A300) and a8574a );
a8576a <=( a8575a and a8570a );
a8580a <=( A168 and (not A169) );
a8581a <=( A170 and a8580a );
a8585a <=( (not A201) and A200 );
a8586a <=( (not A199) and a8585a );
a8587a <=( a8586a and a8581a );
a8591a <=( A298 and (not A203) );
a8592a <=( (not A202) and a8591a );
a8596a <=( A301 and A300 );
a8597a <=( (not A299) and a8596a );
a8598a <=( a8597a and a8592a );
a8602a <=( A168 and (not A169) );
a8603a <=( A170 and a8602a );
a8607a <=( (not A201) and A200 );
a8608a <=( (not A199) and a8607a );
a8609a <=( a8608a and a8603a );
a8613a <=( A298 and (not A203) );
a8614a <=( (not A202) and a8613a );
a8618a <=( A302 and A300 );
a8619a <=( (not A299) and a8618a );
a8620a <=( a8619a and a8614a );
a8624a <=( A168 and (not A169) );
a8625a <=( A170 and a8624a );
a8629a <=( (not A201) and A200 );
a8630a <=( (not A199) and a8629a );
a8631a <=( a8630a and a8625a );
a8635a <=( (not A298) and (not A203) );
a8636a <=( (not A202) and a8635a );
a8640a <=( A301 and A300 );
a8641a <=( A299 and a8640a );
a8642a <=( a8641a and a8636a );
a8646a <=( A168 and (not A169) );
a8647a <=( A170 and a8646a );
a8651a <=( (not A201) and A200 );
a8652a <=( (not A199) and a8651a );
a8653a <=( a8652a and a8647a );
a8657a <=( (not A298) and (not A203) );
a8658a <=( (not A202) and a8657a );
a8662a <=( A302 and A300 );
a8663a <=( A299 and a8662a );
a8664a <=( a8663a and a8658a );
a8668a <=( A168 and (not A169) );
a8669a <=( A170 and a8668a );
a8673a <=( A201 and (not A200) );
a8674a <=( A199 and a8673a );
a8675a <=( a8674a and a8669a );
a8679a <=( (not A299) and A298 );
a8680a <=( A202 and a8679a );
a8684a <=( (not A302) and (not A301) );
a8685a <=( (not A300) and a8684a );
a8686a <=( a8685a and a8680a );
a8690a <=( A168 and (not A169) );
a8691a <=( A170 and a8690a );
a8695a <=( A201 and (not A200) );
a8696a <=( A199 and a8695a );
a8697a <=( a8696a and a8691a );
a8701a <=( A299 and (not A298) );
a8702a <=( A202 and a8701a );
a8706a <=( (not A302) and (not A301) );
a8707a <=( (not A300) and a8706a );
a8708a <=( a8707a and a8702a );
a8712a <=( A168 and (not A169) );
a8713a <=( A170 and a8712a );
a8717a <=( A201 and (not A200) );
a8718a <=( A199 and a8717a );
a8719a <=( a8718a and a8713a );
a8723a <=( (not A299) and A298 );
a8724a <=( A203 and a8723a );
a8728a <=( (not A302) and (not A301) );
a8729a <=( (not A300) and a8728a );
a8730a <=( a8729a and a8724a );
a8734a <=( A168 and (not A169) );
a8735a <=( A170 and a8734a );
a8739a <=( A201 and (not A200) );
a8740a <=( A199 and a8739a );
a8741a <=( a8740a and a8735a );
a8745a <=( A299 and (not A298) );
a8746a <=( A203 and a8745a );
a8750a <=( (not A302) and (not A301) );
a8751a <=( (not A300) and a8750a );
a8752a <=( a8751a and a8746a );
a8756a <=( A168 and (not A169) );
a8757a <=( A170 and a8756a );
a8761a <=( (not A201) and (not A200) );
a8762a <=( A199 and a8761a );
a8763a <=( a8762a and a8757a );
a8767a <=( A298 and (not A203) );
a8768a <=( (not A202) and a8767a );
a8772a <=( A301 and A300 );
a8773a <=( (not A299) and a8772a );
a8774a <=( a8773a and a8768a );
a8778a <=( A168 and (not A169) );
a8779a <=( A170 and a8778a );
a8783a <=( (not A201) and (not A200) );
a8784a <=( A199 and a8783a );
a8785a <=( a8784a and a8779a );
a8789a <=( A298 and (not A203) );
a8790a <=( (not A202) and a8789a );
a8794a <=( A302 and A300 );
a8795a <=( (not A299) and a8794a );
a8796a <=( a8795a and a8790a );
a8800a <=( A168 and (not A169) );
a8801a <=( A170 and a8800a );
a8805a <=( (not A201) and (not A200) );
a8806a <=( A199 and a8805a );
a8807a <=( a8806a and a8801a );
a8811a <=( (not A298) and (not A203) );
a8812a <=( (not A202) and a8811a );
a8816a <=( A301 and A300 );
a8817a <=( A299 and a8816a );
a8818a <=( a8817a and a8812a );
a8822a <=( A168 and (not A169) );
a8823a <=( A170 and a8822a );
a8827a <=( (not A201) and (not A200) );
a8828a <=( A199 and a8827a );
a8829a <=( a8828a and a8823a );
a8833a <=( (not A298) and (not A203) );
a8834a <=( (not A202) and a8833a );
a8838a <=( A302 and A300 );
a8839a <=( A299 and a8838a );
a8840a <=( a8839a and a8834a );
a8844a <=( (not A168) and (not A169) );
a8845a <=( A170 and a8844a );
a8849a <=( A201 and (not A166) );
a8850a <=( A167 and a8849a );
a8851a <=( a8850a and a8845a );
a8855a <=( A298 and (not A203) );
a8856a <=( (not A202) and a8855a );
a8860a <=( A301 and A300 );
a8861a <=( (not A299) and a8860a );
a8862a <=( a8861a and a8856a );
a8866a <=( (not A168) and (not A169) );
a8867a <=( A170 and a8866a );
a8871a <=( A201 and (not A166) );
a8872a <=( A167 and a8871a );
a8873a <=( a8872a and a8867a );
a8877a <=( A298 and (not A203) );
a8878a <=( (not A202) and a8877a );
a8882a <=( A302 and A300 );
a8883a <=( (not A299) and a8882a );
a8884a <=( a8883a and a8878a );
a8888a <=( (not A168) and (not A169) );
a8889a <=( A170 and a8888a );
a8893a <=( A201 and (not A166) );
a8894a <=( A167 and a8893a );
a8895a <=( a8894a and a8889a );
a8899a <=( (not A298) and (not A203) );
a8900a <=( (not A202) and a8899a );
a8904a <=( A301 and A300 );
a8905a <=( A299 and a8904a );
a8906a <=( a8905a and a8900a );
a8910a <=( (not A168) and (not A169) );
a8911a <=( A170 and a8910a );
a8915a <=( A201 and (not A166) );
a8916a <=( A167 and a8915a );
a8917a <=( a8916a and a8911a );
a8921a <=( (not A298) and (not A203) );
a8922a <=( (not A202) and a8921a );
a8926a <=( A302 and A300 );
a8927a <=( A299 and a8926a );
a8928a <=( a8927a and a8922a );
a8932a <=( (not A168) and (not A169) );
a8933a <=( A170 and a8932a );
a8937a <=( (not A201) and (not A166) );
a8938a <=( A167 and a8937a );
a8939a <=( a8938a and a8933a );
a8943a <=( (not A299) and A298 );
a8944a <=( A202 and a8943a );
a8948a <=( (not A302) and (not A301) );
a8949a <=( (not A300) and a8948a );
a8950a <=( a8949a and a8944a );
a8954a <=( (not A168) and (not A169) );
a8955a <=( A170 and a8954a );
a8959a <=( (not A201) and (not A166) );
a8960a <=( A167 and a8959a );
a8961a <=( a8960a and a8955a );
a8965a <=( A299 and (not A298) );
a8966a <=( A202 and a8965a );
a8970a <=( (not A302) and (not A301) );
a8971a <=( (not A300) and a8970a );
a8972a <=( a8971a and a8966a );
a8976a <=( (not A168) and (not A169) );
a8977a <=( A170 and a8976a );
a8981a <=( (not A201) and (not A166) );
a8982a <=( A167 and a8981a );
a8983a <=( a8982a and a8977a );
a8987a <=( (not A299) and A298 );
a8988a <=( A203 and a8987a );
a8992a <=( (not A302) and (not A301) );
a8993a <=( (not A300) and a8992a );
a8994a <=( a8993a and a8988a );
a8998a <=( (not A168) and (not A169) );
a8999a <=( A170 and a8998a );
a9003a <=( (not A201) and (not A166) );
a9004a <=( A167 and a9003a );
a9005a <=( a9004a and a8999a );
a9009a <=( A299 and (not A298) );
a9010a <=( A203 and a9009a );
a9014a <=( (not A302) and (not A301) );
a9015a <=( (not A300) and a9014a );
a9016a <=( a9015a and a9010a );
a9020a <=( (not A168) and (not A169) );
a9021a <=( A170 and a9020a );
a9025a <=( A199 and (not A166) );
a9026a <=( A167 and a9025a );
a9027a <=( a9026a and a9021a );
a9031a <=( (not A299) and A298 );
a9032a <=( A200 and a9031a );
a9036a <=( (not A302) and (not A301) );
a9037a <=( (not A300) and a9036a );
a9038a <=( a9037a and a9032a );
a9042a <=( (not A168) and (not A169) );
a9043a <=( A170 and a9042a );
a9047a <=( A199 and (not A166) );
a9048a <=( A167 and a9047a );
a9049a <=( a9048a and a9043a );
a9053a <=( A299 and (not A298) );
a9054a <=( A200 and a9053a );
a9058a <=( (not A302) and (not A301) );
a9059a <=( (not A300) and a9058a );
a9060a <=( a9059a and a9054a );
a9064a <=( (not A168) and (not A169) );
a9065a <=( A170 and a9064a );
a9069a <=( (not A199) and (not A166) );
a9070a <=( A167 and a9069a );
a9071a <=( a9070a and a9065a );
a9075a <=( (not A299) and A298 );
a9076a <=( (not A200) and a9075a );
a9080a <=( (not A302) and (not A301) );
a9081a <=( (not A300) and a9080a );
a9082a <=( a9081a and a9076a );
a9086a <=( (not A168) and (not A169) );
a9087a <=( A170 and a9086a );
a9091a <=( (not A199) and (not A166) );
a9092a <=( A167 and a9091a );
a9093a <=( a9092a and a9087a );
a9097a <=( A299 and (not A298) );
a9098a <=( (not A200) and a9097a );
a9102a <=( (not A302) and (not A301) );
a9103a <=( (not A300) and a9102a );
a9104a <=( a9103a and a9098a );
a9108a <=( (not A168) and (not A169) );
a9109a <=( A170 and a9108a );
a9113a <=( A201 and A166 );
a9114a <=( (not A167) and a9113a );
a9115a <=( a9114a and a9109a );
a9119a <=( A298 and (not A203) );
a9120a <=( (not A202) and a9119a );
a9124a <=( A301 and A300 );
a9125a <=( (not A299) and a9124a );
a9126a <=( a9125a and a9120a );
a9130a <=( (not A168) and (not A169) );
a9131a <=( A170 and a9130a );
a9135a <=( A201 and A166 );
a9136a <=( (not A167) and a9135a );
a9137a <=( a9136a and a9131a );
a9141a <=( A298 and (not A203) );
a9142a <=( (not A202) and a9141a );
a9146a <=( A302 and A300 );
a9147a <=( (not A299) and a9146a );
a9148a <=( a9147a and a9142a );
a9152a <=( (not A168) and (not A169) );
a9153a <=( A170 and a9152a );
a9157a <=( A201 and A166 );
a9158a <=( (not A167) and a9157a );
a9159a <=( a9158a and a9153a );
a9163a <=( (not A298) and (not A203) );
a9164a <=( (not A202) and a9163a );
a9168a <=( A301 and A300 );
a9169a <=( A299 and a9168a );
a9170a <=( a9169a and a9164a );
a9174a <=( (not A168) and (not A169) );
a9175a <=( A170 and a9174a );
a9179a <=( A201 and A166 );
a9180a <=( (not A167) and a9179a );
a9181a <=( a9180a and a9175a );
a9185a <=( (not A298) and (not A203) );
a9186a <=( (not A202) and a9185a );
a9190a <=( A302 and A300 );
a9191a <=( A299 and a9190a );
a9192a <=( a9191a and a9186a );
a9196a <=( (not A168) and (not A169) );
a9197a <=( A170 and a9196a );
a9201a <=( (not A201) and A166 );
a9202a <=( (not A167) and a9201a );
a9203a <=( a9202a and a9197a );
a9207a <=( (not A299) and A298 );
a9208a <=( A202 and a9207a );
a9212a <=( (not A302) and (not A301) );
a9213a <=( (not A300) and a9212a );
a9214a <=( a9213a and a9208a );
a9218a <=( (not A168) and (not A169) );
a9219a <=( A170 and a9218a );
a9223a <=( (not A201) and A166 );
a9224a <=( (not A167) and a9223a );
a9225a <=( a9224a and a9219a );
a9229a <=( A299 and (not A298) );
a9230a <=( A202 and a9229a );
a9234a <=( (not A302) and (not A301) );
a9235a <=( (not A300) and a9234a );
a9236a <=( a9235a and a9230a );
a9240a <=( (not A168) and (not A169) );
a9241a <=( A170 and a9240a );
a9245a <=( (not A201) and A166 );
a9246a <=( (not A167) and a9245a );
a9247a <=( a9246a and a9241a );
a9251a <=( (not A299) and A298 );
a9252a <=( A203 and a9251a );
a9256a <=( (not A302) and (not A301) );
a9257a <=( (not A300) and a9256a );
a9258a <=( a9257a and a9252a );
a9262a <=( (not A168) and (not A169) );
a9263a <=( A170 and a9262a );
a9267a <=( (not A201) and A166 );
a9268a <=( (not A167) and a9267a );
a9269a <=( a9268a and a9263a );
a9273a <=( A299 and (not A298) );
a9274a <=( A203 and a9273a );
a9278a <=( (not A302) and (not A301) );
a9279a <=( (not A300) and a9278a );
a9280a <=( a9279a and a9274a );
a9284a <=( (not A168) and (not A169) );
a9285a <=( A170 and a9284a );
a9289a <=( A199 and A166 );
a9290a <=( (not A167) and a9289a );
a9291a <=( a9290a and a9285a );
a9295a <=( (not A299) and A298 );
a9296a <=( A200 and a9295a );
a9300a <=( (not A302) and (not A301) );
a9301a <=( (not A300) and a9300a );
a9302a <=( a9301a and a9296a );
a9306a <=( (not A168) and (not A169) );
a9307a <=( A170 and a9306a );
a9311a <=( A199 and A166 );
a9312a <=( (not A167) and a9311a );
a9313a <=( a9312a and a9307a );
a9317a <=( A299 and (not A298) );
a9318a <=( A200 and a9317a );
a9322a <=( (not A302) and (not A301) );
a9323a <=( (not A300) and a9322a );
a9324a <=( a9323a and a9318a );
a9328a <=( (not A168) and (not A169) );
a9329a <=( A170 and a9328a );
a9333a <=( (not A199) and A166 );
a9334a <=( (not A167) and a9333a );
a9335a <=( a9334a and a9329a );
a9339a <=( (not A299) and A298 );
a9340a <=( (not A200) and a9339a );
a9344a <=( (not A302) and (not A301) );
a9345a <=( (not A300) and a9344a );
a9346a <=( a9345a and a9340a );
a9350a <=( (not A168) and (not A169) );
a9351a <=( A170 and a9350a );
a9355a <=( (not A199) and A166 );
a9356a <=( (not A167) and a9355a );
a9357a <=( a9356a and a9351a );
a9361a <=( A299 and (not A298) );
a9362a <=( (not A200) and a9361a );
a9366a <=( (not A302) and (not A301) );
a9367a <=( (not A300) and a9366a );
a9368a <=( a9367a and a9362a );
a9372a <=( A168 and (not A169) );
a9373a <=( A170 and a9372a );
a9377a <=( (not A201) and A200 );
a9378a <=( (not A199) and a9377a );
a9379a <=( a9378a and a9373a );
a9383a <=( A298 and (not A203) );
a9384a <=( (not A202) and a9383a );
a9387a <=( (not A300) and (not A299) );
a9390a <=( (not A302) and (not A301) );
a9391a <=( a9390a and a9387a );
a9392a <=( a9391a and a9384a );
a9396a <=( A168 and (not A169) );
a9397a <=( A170 and a9396a );
a9401a <=( (not A201) and A200 );
a9402a <=( (not A199) and a9401a );
a9403a <=( a9402a and a9397a );
a9407a <=( (not A298) and (not A203) );
a9408a <=( (not A202) and a9407a );
a9411a <=( (not A300) and A299 );
a9414a <=( (not A302) and (not A301) );
a9415a <=( a9414a and a9411a );
a9416a <=( a9415a and a9408a );
a9420a <=( A168 and (not A169) );
a9421a <=( A170 and a9420a );
a9425a <=( (not A201) and (not A200) );
a9426a <=( A199 and a9425a );
a9427a <=( a9426a and a9421a );
a9431a <=( A298 and (not A203) );
a9432a <=( (not A202) and a9431a );
a9435a <=( (not A300) and (not A299) );
a9438a <=( (not A302) and (not A301) );
a9439a <=( a9438a and a9435a );
a9440a <=( a9439a and a9432a );
a9444a <=( A168 and (not A169) );
a9445a <=( A170 and a9444a );
a9449a <=( (not A201) and (not A200) );
a9450a <=( A199 and a9449a );
a9451a <=( a9450a and a9445a );
a9455a <=( (not A298) and (not A203) );
a9456a <=( (not A202) and a9455a );
a9459a <=( (not A300) and A299 );
a9462a <=( (not A302) and (not A301) );
a9463a <=( a9462a and a9459a );
a9464a <=( a9463a and a9456a );
a9468a <=( (not A168) and (not A169) );
a9469a <=( A170 and a9468a );
a9473a <=( A201 and (not A166) );
a9474a <=( A167 and a9473a );
a9475a <=( a9474a and a9469a );
a9479a <=( A298 and (not A203) );
a9480a <=( (not A202) and a9479a );
a9483a <=( (not A300) and (not A299) );
a9486a <=( (not A302) and (not A301) );
a9487a <=( a9486a and a9483a );
a9488a <=( a9487a and a9480a );
a9492a <=( (not A168) and (not A169) );
a9493a <=( A170 and a9492a );
a9497a <=( A201 and (not A166) );
a9498a <=( A167 and a9497a );
a9499a <=( a9498a and a9493a );
a9503a <=( (not A298) and (not A203) );
a9504a <=( (not A202) and a9503a );
a9507a <=( (not A300) and A299 );
a9510a <=( (not A302) and (not A301) );
a9511a <=( a9510a and a9507a );
a9512a <=( a9511a and a9504a );
a9516a <=( (not A168) and (not A169) );
a9517a <=( A170 and a9516a );
a9521a <=( A201 and A166 );
a9522a <=( (not A167) and a9521a );
a9523a <=( a9522a and a9517a );
a9527a <=( A298 and (not A203) );
a9528a <=( (not A202) and a9527a );
a9531a <=( (not A300) and (not A299) );
a9534a <=( (not A302) and (not A301) );
a9535a <=( a9534a and a9531a );
a9536a <=( a9535a and a9528a );
a9540a <=( (not A168) and (not A169) );
a9541a <=( A170 and a9540a );
a9545a <=( A201 and A166 );
a9546a <=( (not A167) and a9545a );
a9547a <=( a9546a and a9541a );
a9551a <=( (not A298) and (not A203) );
a9552a <=( (not A202) and a9551a );
a9555a <=( (not A300) and A299 );
a9558a <=( (not A302) and (not A301) );
a9559a <=( a9558a and a9555a );
a9560a <=( a9559a and a9552a );
end x25_3x_behav;
| gpl-3.0 | 468478da9a203497b24e0b4e8a7d7fc7 | 0.608335 | 2.13724 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_hype.vhd | 1 | 3,613 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_hype_entity;
ARCHITECTURE fir1_hype_description OF fir1_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
WHEN "00000010" =>
register2 := register2 * register3;
register3 := input4 and input4;
register4 := input5 and input5;
register5 := input6 and input6;
register6 := input7 and input7;
WHEN "00000011" =>
register4 := register4 * register6;
register6 := input8 and input8;
register7 := input9 and input9;
register8 := input10 and input10;
register9 := input11 and input11;
register10 := input12 and input12;
register3 := register3 * register5;
WHEN "00000100" =>
register5 := register9 * register6;
register6 := input13 and input13;
register1 := register1 * register10;
register2 := register2 + register3;
register3 := register7 * register8;
register7 := input14 and input14;
register8 := input15 and input15;
WHEN "00000101" =>
register7 := register8 * register7;
register3 := register4 + register3;
register4 := input16 and input16;
WHEN "00000110" =>
register4 := register4 * register6;
register6 := input17 and input17;
register8 := input18 and input18;
register9 := input19 and input19;
register1 := register5 + register1;
register2 := register2 + register7;
register5 := input20 and input20;
WHEN "00000111" =>
register5 := register8 * register5;
register6 := register6 * register9;
register7 := input21 and input21;
register8 := input22 and input22;
WHEN "00001000" =>
register7 := register7 * register8;
WHEN "00001001" =>
register2 := register7 + register2;
WHEN "00001010" =>
register1 := register1 + register2;
WHEN "00001011" =>
register1 := register1 + register6;
WHEN "00001100" =>
register1 := register3 + register1;
WHEN "00001101" =>
register1 := register1 + register4;
WHEN "00001110" =>
register1 := register5 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_hype_description; | gpl-3.0 | 70c0cf08935ae0ef6d32805985ba01ee | 0.678937 | 3.240359 | false | false | false | false |
Abeergit/UART | uart.vhd | 1 | 2,320 | --
-- UART Top Module
-- uart_rx, uart_tx, baud_gen, parity_gen, fifo_buffer
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic(
DBIT : integer := 8; --Databits
SB_TICK : integer := 16; --Stopbit ticks (16/24/32 -> 1, 1.5, 2)
DVSR : integer := 16; -- Baud rate Divisor
FIFO_W : integer := 2; -- # of FIFO Addressbits
PARITY_EN : std_logic := '1' -- Parity enable(1) / disable(0)
);
port(
clk, reset : in std_logic;
rd_uart, wr_uart : in std_logic;
rx : in std_logic;
w_data : in std_logic_vector(7 downto 0);
tx_full, rx_empty : out std_logic;
r_data : out std_logic_vector(7 downto 0);
tx : out std_logic
);
end uart;
architecture main of uart is
signal tick : std_logic;
signal rx_done_tick : std_logic;
signal tx_fifo_out : std_logic_vector(7 downto 0);
signal rx_data_out : std_logic_vector(7 downto 0);
signal tx_empty, tx_fifo_not_empty : std_logic;
signal tx_done_tick : std_logic;
signal parity_bit : std_logic;
begin
baud_gen_unit: entity work.baud_gen
generic map(
M=>DVSR)
port map(
clk => clk, reset => reset,
max_tick => tick);
uart_rx_unit: entity work.uart_rx
generic map(
DBIT => DBIT, SB_TICK => SB_TICK,
PARITY_EN => PARITY_EN)
port map(
clk => clk, reset => reset, rx => rx,
s_tick => tick, rx_done_tick => rx_done_tick,
dout => rx_data_out, framing_error_tick => open,
parity_error => open);
fifo_rx_unit: entity work.fifo_buffer
generic map(
B => DBIT, W => FIFO_W)
port map(
clk => clk, reset => reset, rd => rd_uart,
wr => rx_done_tick, w_data => rx_data_out,
empty => rx_empty, full => open, r_data => r_data);
uart_tx_unit: entity work.uart_tx
generic map(
DBIT => DBIT, SB_TICK => SB_TICK,
PARITY_EN => PARITY_EN)
port map(
clk => clk, reset => reset, tx_start => tx_fifo_not_empty,
s_tick => tick, din => tx_fifo_out, tx_done_tick => tx_done_tick,
tx => tx, parity_bit => parity_bit);
fifo_tx_unit: entity work.fifo_buffer
generic map(
B => DBIT, W => FIFO_W)
port map(
clk => clk, reset => reset, rd => tx_done_tick,
wr => wr_uart, w_data => w_data, empty => tx_empty,
full => tx_full, r_data => tx_fifo_out);
parity_gen: entity work.parity_gen
port map(vec_in => tx_fifo_out, parity_bit => parity_bit);
tx_fifo_not_empty <= not tx_empty;
end main;
| mit | bac69294cd45f7e89165fd7600afc0cf | 0.633621 | 2.609674 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_gate128.vhd | 15 | 9,370 | -------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
| apache-2.0 | 7bb274e4626d184deaef1e3bc3d6a5d9 | 0.415902 | 4.939378 | false | false | false | false |
jdryg/tis100cpu | node_port_writedec.vhd | 1 | 1,404 | -- Added these lines on rev. 42 in order to remove the commit message saying that
-- there is a bug in the implementation, since the bug has been fixed in the same rev.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity node_port_writedec is
Generic (WIDTH : integer := 8);
Port ( I_clk : in STD_LOGIC;
I_portID : in STD_LOGIC_VECTOR (2 downto 0);
I_writeEnable : in STD_LOGIC;
I_data : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_writeEnableUp : out STD_LOGIC;
O_writeEnableDown : out STD_LOGIC;
O_writeEnableLeft : out STD_LOGIC;
O_writeEnableRight : out STD_LOGIC;
O_dataUp : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataDown : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataLeft : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataRight : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
end node_port_writedec;
architecture Behavioral of node_port_writedec is
begin
O_writeEnableUp <= I_writeEnable when I_portID = "000" else '0';
O_writeEnableDown <= I_writeEnable when I_portID = "001" else '0';
O_writeEnableLeft <= I_writeEnable when I_portID = "010" else '0';
O_writeEnableRight <= I_writeEnable when I_portID = "011" else '0';
O_dataUp <= I_data;
O_dataDown <= I_data;
O_dataLeft <= I_data;
O_dataRight <= I_data;
end Behavioral;
| mit | 0145f076bf97236ae8b1e99c83c41d54 | 0.63604 | 3.288056 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/8-JPEG-SD/asap-alap-random/jpegsd_asap.vhd | 1 | 4,395 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:39:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY jpegsd_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END jpegsd_asap_entity;
ARCHITECTURE jpegsd_asap_description OF jpegsd_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := ((NOT input1) + 1) XOR input1;
register2 := input2 + 2;
register3 := input3 + 3;
register4 := input4 + 4;
register5 := input5 + 5;
register6 := input6 + 6;
output1 <= input7 + 7;
output2 <= input8 + 8;
register7 := ((NOT input9) + 1) XOR input9;
register8 := input10 + 10;
register9 := input11 + 11;
register10 := input12 + 12;
register11 := input13 + 13;
register12 := input14 + 14;
register13 := ((NOT input15) + 1) XOR input15;
register14 := ((NOT input16) + 1) XOR input16;
register15 := input17 + 17;
register16 := input18 + 18;
WHEN "00000010" =>
register2 := ((NOT register2) + 1) XOR register2;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register8 := ((NOT register8) + 1) XOR register8;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000011" =>
register2 := register8 + register2;
register3 := register7 + register3;
register1 := register1 + register12;
WHEN "00000100" =>
register2 := register2 + register16;
register3 := register3 + register14;
register1 := register1 + register13;
WHEN "00000101" =>
register2 := register2 + register15;
register3 := register3 + register10;
register1 := register1 + register4;
WHEN "00000110" =>
register3 := register3 + register5;
register4 := register1 * 44;
WHEN "00000111" =>
register3 := register3 + register9;
WHEN "00001000" =>
register3 := register3 + register11;
WHEN "00001001" =>
register3 := register3 + register6;
WHEN "00001010" =>
register5 := register3 + 46;
WHEN "00001011" =>
register2 := register3 + register5 + register2;
WHEN "00001100" =>
register2 := register3 * register5 * register2;
WHEN "00001101" =>
register2 := register4 + register2;
WHEN "00001110" =>
register1 := register1 + register2;
WHEN "00001111" =>
register1 := register1 srl 48;
WHEN "00010000" =>
output3 <= register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END jpegsd_asap_description; | gpl-3.0 | 499c38ecd6a6c33d3d96149c451612df | 0.659613 | 3.191721 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/disp7seg.vhd | 1 | 2,504 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:01 06/13/2012
-- Design Name:
-- Module Name: disp7segx4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity disp7seg is
Port ( entrada : in STD_LOGIC_VECTOR (3 downto 0);
clock : in std_logic;
reset : in std_logic;
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0));
end disp7seg;
architecture Behavioral of disp7seg is
type vetor_de_10_std_logic_vector is array (0 to 15) of std_logic_vector (0 to 7);
constant tabela_disp7seg : vetor_de_10_std_logic_vector := (("00000011"),("10011111"),("00100101"),("00001101"),("10011001"),("01001001"),("01000001"),("00011111"),("00000001"),("00001001"),("00010011"),("11000001"),("01100011"),("10000101"),("01100001"),("01110001"));
-- abcdefgx
begin
process (clock, reset)
begin
if reset = '1' then
saida_8segmentos <= "11111111"; -- apaga tudo
elsif clock'event and clock = '1' then
case entrada is
when "0000" => saida_8segmentos <= tabela_disp7seg(0);
when "0001" => saida_8segmentos <= tabela_disp7seg(1);
when "0010" => saida_8segmentos <= tabela_disp7seg(2);
when "0011" => saida_8segmentos <= tabela_disp7seg(3);
when "0100" => saida_8segmentos <= tabela_disp7seg(4);
when "0101" => saida_8segmentos <= tabela_disp7seg(5);
when "0110" => saida_8segmentos <= tabela_disp7seg(6);
when "0111" => saida_8segmentos <= tabela_disp7seg(7);
when "1000" => saida_8segmentos <= tabela_disp7seg(8);
when "1001" => saida_8segmentos <= tabela_disp7seg(9);
when "1010" => saida_8segmentos <= tabela_disp7seg(10);
when "1011" => saida_8segmentos <= tabela_disp7seg(11);
when "1100" => saida_8segmentos <= tabela_disp7seg(12);
when "1101" => saida_8segmentos <= tabela_disp7seg(13);
when "1110" => saida_8segmentos <= tabela_disp7seg(14);
when "1111" => saida_8segmentos <= tabela_disp7seg(15);
when others => saida_8segmentos <= "11111110"; -- liga SO O PONTO
end case;
end if;
end process;
end Behavioral;
| mit | 620a7903fd54134e43742e72c87c162e | 0.579473 | 3.218509 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_wsga.vhd | 1 | 3,088 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_wsga_entity;
ARCHITECTURE ewf_wsga_description OF ewf_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
register3 := input2 + 4;
WHEN "00000011" =>
register4 := register2 + 6;
WHEN "00000100" =>
register4 := register3 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register2 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register4 := register4 + register5;
register6 := register3 + register6;
register2 := register2 + register5;
WHEN "00001000" =>
output1 <= register6 + register4;
register3 := register3 + register6;
register2 := register2 * 13;
WHEN "00001001" =>
register3 := register3 * 15;
register2 := register1 + register2;
WHEN "00001010" =>
register3 := register3 + 17;
register1 := register1 + register2;
register4 := register5 + register2;
WHEN "00001011" =>
register4 := register4 + 19;
register5 := register6 + register3;
register1 := register1 * 21;
register6 := register3 + 23;
WHEN "00001100" =>
register6 := register6 * 25;
register5 := register5 + 27;
register1 := register1 + 29;
register7 := register4 * 31;
WHEN "00001101" =>
register8 := register5 * 33;
register7 := register7 + 35;
output2 <= register3 + register6;
output3 <= register2 + register1;
WHEN "00001110" =>
register1 := register8 + 39;
output4 <= register4 + register7;
WHEN "00001111" =>
output5 <= register5 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_wsga_description; | gpl-3.0 | 6e468f8746921555f324b17518a72e46 | 0.680376 | 3.415929 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_counter_top.vhd | 15 | 8,369 | -------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
| apache-2.0 | 66b5556b16d6fcfadfcd0ec1973e3abe | 0.422273 | 4.984515 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_femo.vhd | 1 | 3,701 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_femo_entity;
ARCHITECTURE fir1_femo_description OF fir1_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
WHEN "00000010" =>
register3 := input3 and input3;
register1 := register1 * register2;
register2 := input4 and input4;
WHEN "00000011" =>
register4 := input5 and input5;
register5 := input6 and input6;
register2 := register3 * register2;
WHEN "00000100" =>
register3 := input7 and input7;
register6 := input8 and input8;
register4 := register4 * register5;
WHEN "00000101" =>
register3 := register3 * register6;
register5 := input9 and input9;
register6 := input10 and input10;
WHEN "00000110" =>
register7 := input11 and input11;
WHEN "00000111" =>
register5 := register7 * register5;
register1 := register2 + register1;
register2 := input12 and input12;
WHEN "00001000" =>
register2 := register6 * register2;
register6 := input13 and input13;
register7 := input14 and input14;
WHEN "00001001" =>
register8 := input15 and input15;
register9 := input16 and input16;
WHEN "00001010" =>
register6 := register6 * register8;
register8 := input17 and input17;
register10 := input18 and input18;
register2 := register3 + register2;
WHEN "00001011" =>
register3 := register10 * register9;
register7 := register7 * register8;
register8 := input19 and input19;
register9 := input20 and input20;
WHEN "00001100" =>
register8 := register9 * register8;
register9 := input21 and input21;
register1 := register1 + register7;
register7 := input22 and input22;
WHEN "00001101" =>
register3 := register3 + register8;
register1 := register4 + register1;
WHEN "00001110" =>
register1 := register2 + register1;
WHEN "00001111" =>
register1 := register1 + register6;
register2 := register9 * register7;
WHEN "00010000" =>
register1 := register3 + register1;
WHEN "00010001" =>
register1 := register1 + register2;
WHEN "00010010" =>
register1 := register5 + register1;
WHEN "00010011" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_femo_description; | gpl-3.0 | 19277d946fe196bfc935a0b0d7a597ad | 0.675763 | 3.23797 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo_rbu.vhd | 15 | 18,227 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
| apache-2.0 | b0ba1f6ed4fa57f59e110141fc264cdc | 0.469962 | 4.483887 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_vk_testbench_128bits.vhd | 1 | 10,287 | -- Twofish_ecb_vk_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE KEY KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity vk_testbench128 is
end vk_testbench128;
architecture vk_encryption128_testbench_arch of vk_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_vk_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_vk_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 129) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
vk_proc: process
variable key_f, -- key input from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter : integer range 1 to 129 := 1; -- counts the encryptions
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption
begin
-- plaintext stays fixed to zero
input_data <= (others => '0');
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Variable Key Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process vk_proc;
end vk_encryption128_testbench_arch;
| gpl-2.0 | a1c3f4f0aad09195bce7f8541cf57fd3 | 0.649655 | 2.692932 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_dc_as.vhd | 5 | 10,777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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| apache-2.0 | 51e5406f0038fdf5f77f1d63272c40f8 | 0.925397 | 1.881459 | false | false | false | false |
rcls/sdr | vhdl/downconvert.vhd | 1 | 16,150 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
-- This does one half of the downconverter, either real or imaginary.
entity dc1 is
generic(minus_sin : boolean; gen_product : boolean := false);
port (data : in signed14;
gain : in unsigned(3 downto 0);
product : out signed36;
q : out mf_signed;
phase : in unsigned(13 downto 0);
clk : in std_logic;
index : out unsigned(9 downto 0);
packed : in unsigned18);
end dc1;
architecture dc1 of dc1 is
constant width1 : integer := 48;
constant width2 : integer := minimum(mf_width + 10, width1);
--signal index : unsigned(9 downto 0);
signal low, low_2 : unsigned(1 downto 0);
signal minus : std_logic_vector(1 to 5);
signal main, offset : unsigned18;
signal data_3 : signed14;
signal main_4, main_5, offset_4, offset_5, trig : signed18;
signal data_4, data_5, data_6 : signed18;
signal prod : signed36;
signal buf : signed(width1 - 1 downto 0);
signal buf_9, acc : signed(width2 - 1 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of acc : signal is "no";
begin
process
begin
wait until rising_edge(clk);
-- Unpack the accumulator to the indexes and signs.
-- Maybe we should have separate tables for
-- sines and cosines...
if minus_sin then
if phase(12) = '1' then
index <= not phase(11 downto 2);
low <= not phase(1 downto 0);
else
index <= phase(11 downto 2);
low <= phase(1 downto 0);
end if;
-- We are down-converting not up converting, so we want to use -sin.
minus(1) <= not phase(13);
else
if phase(12) = '1' then
index <= phase(11 downto 2);
low <= phase(1 downto 0);
else
index <= not phase(11 downto 2);
low <= not phase(1 downto 0);
end if;
minus(1) <= phase(13) xor phase(12);
end if;
minus(2 to 5) <= minus(1 to 4);
-- Lookup the sin and cos tables. - done a level up.
--packed <= sintable(to_integer(index));
low_2 <= low;
-- Prepare the sin and cos.
main <= packed and "00" & x"3fff";
offset <= resize(sinoffset(packed, low_2), 18);
data_3 <= data;
-- Apply gain(1,0) to sin & cos, & gain(2) to data.
if gain(2) = '0' then
data_4 <= resize(data_3, 18);
else
data_4 <= data_3 & "0000";
end if;
main_4 <= signed(main) sll to_integer(gain(1 downto 0));
if minus(4) = '1' then
offset_4 <= -signed(offset) sll to_integer(gain(1 downto 0));
else
offset_4 <= signed(offset) sll to_integer(gain(1 downto 0));
end if;
-- Buffer.
main_5 <= main_4;
offset_5 <= offset_4;
data_5 <= data_4;
-- Pre-add.
if minus(5) = '1' then
trig <= offset_5 - main_5;
else
trig <= offset_5 + main_5;
end if;
data_6 <= data_5;
-- Multiply
prod <= data_6 * trig;
-- Post add (8).
buf <= buf + prod;
if gen_product then
product <= prod;
end if;
-- Buffer.
buf_9 <= buf(width1 - 1 downto width1 - width2);
-- Second order accumulate, applying gain(3).
if gain(3) = '0' then
acc <= acc + buf_9;
else
acc <= acc + (buf_9 sll 8);
end if;
q <= acc(width2 - 1 downto width2 - mf_width);
end process;
end dc1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity downconvert is
port (data : in signed14;
gain : in unsigned8;
xx, yy : out mf_signed;
freq : in unsigned24;
clk : in std_logic);
end downconvert;
architecture downconvert of downconvert is
-- For the cosine/sine lookup, we take a 14 bit quantity. The first two bits
-- determine the quadrant, the middle ten the table index, and the bottom
-- two determine the fine adjustment. For cosine, the quadrant processing is:
-- quadrant 00 : invert bottom 12 bits (rom index & fine adjust index).
-- quadrant 01 : cosine is negative.
-- quadrant 10 : invert bottom 12 bits, cosine is negative.
-- quadrant 11 : as looked up.
-- Sine is identical, except that the quadrant is processed differently:
-- quadrant 00 : as looked up.
-- quadrant 01 : invert bottom 12 bits.
-- quadrant 10 : sin is negative.
-- quadrant 11 : invert bottom 12 bits, sin is negative.
-- The (co)sines are scaled to range from 0 to 2^14/pi (and sign bit).
-- The average abs(sin) is 2/pi, after scaling 2^15/pi^2
-- Data sample is 13 bits plus sign, so worst case average multiplier
-- output is signed 2^28/pi^2, [just under] 25 bits plus sign. (Before taking
-- the shift due to 'gain' into account.)
-- e.g., accumulating over 1024 samples needs 35 bits plus sign.
-- second order accumulation needs 45 bits plus sign. Use all 48 bits...
signal phase : unsigned24 := x"000000";
signal sin_index, cos_index : unsigned(9 downto 0);
signal sin_packed, cos_packed : unsigned18;
signal sintable : sinrom_t := sinrom;
begin
cos : entity work.dc1 generic map(false)
port map(data, gain(3 downto 0), open, xx, phase(23 downto 10), clk,
cos_index, cos_packed);
sin : entity work.dc1 generic map(true)
port map(data, gain(3 downto 0), open, yy, phase(23 downto 10), clk,
sin_index, sin_packed);
process
begin
wait until rising_edge(clk);
phase <= phase + freq;
cos_packed <= sintable(to_integer(cos_index));
sin_packed <= sintable(to_integer(sin_index));
end process;
end downconvert;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity downconvertpll is
port (data : in signed14;
freq_in : in unsigned24;
gain : in unsigned8;
decay : in unsigned(3 downto 0);
freq_in_strobe : in std_logic;
xx, yy : out mf_signed;
phasor : out unsigned18;
freq_out : out unsigned(31 downto 0);
error_out : out unsigned(31 downto 0);
level_out : out unsigned(31 downto 0);
out_strobe : in std_logic;
clk : in std_logic);
end downconvertpll;
architecture downconvertpll of downconvertpll is
-- Our control loop looks like:
--
-- d/dt phase = freq + alpha error,
-- d/dt freq = error
-- d/dt error = -beta error - gamma phase
--
-- (counting t in clk cycles).
-- Eigenpolynomial is
-- lambda**3 + beta lambda**2 + alpha gamma lambda + gamma.
-- We are aiming for (lambda + beta/3)**3,
-- i.e., alpha gamma = beta**2 / 3, gamma = beta**3 / 27,
-- alpha = 9 / beta.
-- For convenience, take alpha = 8/beta so we can use bit shifts.
-- beta is 1/2 ** (beta_base + decay),
-- alpha is 2 ** (alpha_base + decay).
-- alpha_base = 14 = 3 + beta_base, beta_base = 11.
-- [so beta is in range 1/2048 to 1/262144, might want to allow lower
-- bandwidth]
-- and we want gamma around 1/27 * 1/2 ** (3*beta_base + 3*decay)
-- gamma is given by shifting and the multiplier scaling.
-- We phase to number of cycles, and t to be discrete number of clock cycles,
-- so that phase, freq and error can all be taken (mod 1).
-- Around phase=0 [and gain=0], the normalisation of our "sin" function is
-- d/dphase "sin"(phase) is 1/2 ** (-13), i.e, a step at
-- bit (-14) produces a step of 2 LSB of the "sin".
-- The overall mean multiplier of the trig multiply is halved and takes the
-- gain signal into account giving a mean multiplier of
-- 2 ** (gain + 12).
-- gamma is then composed of that, the signal strength [in units of LSB],
-- and a shift, i.e., we want
-- 1/27 * 1/2 ** (3*beta_base + 3*decay) = strength * 2 ** (gain + 12) * shift
-- 1 = 27 * strength * shift * 2 ** (gain + 12 + 3*beta_base + 3 * decay)
-- Design for gain to be set so that strength * 2**gain = 2**10
-- = 2**target_width.
-- Approximate 27 by 32, this gives
-- 1 = shift * 2 ** (3*beta_base + 3 * decay + target_width + 17)
-- shift = 1/2 ** (17 + 3*beta_base + target_width + 3 * decay), or
-- The design above gives a shift going into error.
-- It makes more sense to apply this coming out of error, than going in.
-- Fixed point, range [0,1). MSB has weight 0.5.
constant phase_width : integer := 32;
signal phase : signed(phase_width - 1 downto 0) := (others => '0');
constant beta_base : integer := 8;
constant alpha_base : integer := beta_base + 3;
constant level_base : integer := beta_base + 3;
-- Fixed point, MSB has weight 0.5.
constant freq_width : integer := 56;
constant freq_in_pad : signed(freq_width - 25 downto 0) := (others => '0');
signal freq : signed(freq_width - 1 downto 0) := x"642576" & freq_in_pad;
-- Target signal strength. The signal level should be about target_width
-- bits, after left shifting by the gain.
constant target_width : integer := 10;
-- Error (and level) are fix point with the LSB at position
-- (- 60 - 3*decay + error_drop).
constant error_width : integer := 32;
constant level_width : integer := 40;
constant error_drop : integer := 12;
constant level_drop : integer := 12;
signal error : signed(error_width - 1 downto 0);
signal level : signed(level_width - 1 downto 0);
-- These include an extra low bit for use in rounding.
signal error_1 : signed(error_width - beta_base downto 0);
signal level_1 : signed(level_width - level_base downto 0);
-- For the error scaling we need to right shift by
-- 17 + 3*beta_base + target_width + 3*decay - error_drop.
-- For the alignment with freq, left shift by freq_width.
-- We actually left shift by 33 by padding, right shift by 3*decay,
-- and right shift by 50+3*beta_base+target_width-freq_width
-- -error_drop by selecting.
constant error_f_w : integer := error_width + 33;
constant error_f_base : integer := 50 + 3 * beta_base + target_width
- freq_width - error_drop;
signal error_f1 : signed(error_f_w - 1 downto 0);
signal sin_index, cos_index : unsigned(9 downto 0);
signal sin_packed, cos_packed : unsigned18;
signal sintable : sinrom_t := sinrom;
alias cgain : unsigned(3 downto 0) is gain(3 downto 0);
alias sgain : unsigned(3 downto 0) is gain(7 downto 4);
signal sproduct, cproduct : signed36;
signal sproduct_1, sdelta : signed(error_width - 1 downto 0);
signal cproduct_1, cdelta : signed(level_width - 1 downto 0);
signal sproduct_r, cproduct_r, sproduct_r2, cproduct_r2 : std_logic;
-- For the error scaling we need to right shift by
-- 17 + 3*beta_base + target_width + 3*decay - error_drop.
-- For beta we need to left shift by alpha_base + decay.
-- For the alignment with phase, left shift by phase_width.
-- We actually pad by 22, and then right shift by 2*decay, and then
-- right shift (by selection) by
-- 39 + 3*beta_base + target_width - error_drop - alpha_base - phase_width.
constant error_p_w : integer := error_width + 22;
constant error_p_base : integer := 39 + 3*beta_base + target_width
- error_drop - alpha_base - phase_width;
constant error_p_max : integer := minimum(error_p_w,
error_p_base + phase_width);
signal error_p1 : signed(error_p_w - 1 downto 0);
signal phase_a : signed(phase_width - 1 downto 0);
signal base_phase : unsigned24;
-- For some bloody stupid reason, the sra operator doesn't work.
function ssra(val : signed; a : unsigned; m : integer := 1) return signed is
variable v : signed(val'length + 11 * m - 1 downto 0);
variable result : signed(val'length - 1 downto 0);
variable aa : unsigned(3 downto 0);
begin
v := (others => val(val'left));
v(val'length - 1 downto 0) := val;
result := (others => '0');
for i in 0 to 11 loop
if to_integer(a) = i then
result := v(val'length - 1 + i * m downto i * m);
end if;
end loop;
return result;
end ssra;
function top(val : signed; n : integer) return signed is
variable result : signed(n - 1 downto 0);
begin
result := val(val'left downto val'left + 1 - n);
return result;
end top;
function topd(val : signed; n : integer) return std_logic is
begin
return val(val'left - n);
end topd;
begin
cos : entity work.dc1 generic map(false, true)
port map(data, cgain, cproduct, xx,
unsigned(phase(phase_width - 1 downto phase_width - 14)),
clk, cos_index, cos_packed);
sin : entity work.dc1 generic map(true, true)
port map(data, sgain, sproduct, yy,
unsigned(phase(phase_width - 1 downto phase_width - 14)),
clk, sin_index, sin_packed);
process
variable error_1b : signed(error_width - beta_base downto 0);
variable level_1b : signed(level_width - level_base downto 0);
variable error_f0, error_f2 : signed(error_f_w - 1 downto 0);
variable error_p0, error_p2 : signed(error_p_w - 1 downto 0);
begin
wait until rising_edge(clk);
cos_packed <= sintable(to_integer(cos_index));
sin_packed <= sintable(to_integer(sin_index));
sproduct_1 <= top(resize(sproduct, error_width + error_drop)
sll to_integer(sgain and "1000"),
error_width);
sproduct_r <= topd(resize(sproduct, error_width + error_drop)
sll to_integer(sgain and "1000"),
error_width);
cproduct_1 <= top(resize(cproduct, level_width + level_drop)
sll to_integer(cgain and "1000"),
level_width);
cproduct_r <= topd(resize(cproduct, level_width + level_drop)
sll to_integer(cgain and "1000"),
level_width);
error_1 <= ssra(error(error_width - 1 downto beta_base - 1),
decay and "0011");
level_1 <= ssra(level(level_width - 1 downto level_base - 1),
decay and "0011");
error_1b := ssra(error_1, decay and "1100");
level_1b := ssra(level_1, decay and "1100");
sdelta <= sproduct_1 - error_1b(error_width - beta_base downto 1)
- ("0" & error_1b(0));
cdelta <= cproduct_1 - level_1b(level_width - level_base downto 1)
- ("0" & level_1b(0));
sproduct_r2 <= sproduct_r;
cproduct_r2 <= cproduct_r;
error <= error + sdelta + ("0" & sproduct_r2);
level <= level + cdelta + ("0" & cproduct_r2);
error_f0 := (others => '0');
error_f0(error_f_w - 1 downto error_f_w - error_width) := error;
error_f1 <= ssra(error_f0, decay and "0011", 3);
error_f2 := ssra(error_f1, decay and "1100", 3);
freq <= freq + error_f2(error_f_w - 1 downto error_f_base)
+ ("0" & error_f2(error_f_base - 1));
error_p0 := (others => '0');
error_p0(error_p_w - 1 downto error_p_w - error_width) := error;
error_p1 <= ssra(error_p0, decay and "0011", 2);
error_p2 := ssra(error_p1, decay and "1100", 2);
phase_a <= freq(freq_width - 1 downto freq_width - phase_width)
+ error_p2(error_p_max - 1 downto error_p_base)
+ ("0" & error_p2(error_p_base - 1));
phase <= phase + phase_a;
if freq_in_strobe = '1' then
freq <= (signed(freq_in) & freq_in_pad)
+ error_f2(error_f_w - 1 downto error_f_base)
+ ("0" & error_f2(error_f_base - 1));
error <= (others => '0');
level <= (others => '0');
error_1 <= (others => '0');
level_1 <= (others => '0');
sdelta <= (others => '0');
cdelta <= (others => '0');
error_f1 <= (others => '0');
end if;
if out_strobe = '1' then
freq_out <= unsigned(freq(freq'left downto freq'left - 31));
error_out <= unsigned(error(error'left downto error'left - 31));
level_out <= unsigned(level(level'left downto level'left - 31));
end if;
base_phase <= base_phase + freq_in;
phasor <= unsigned(phase(phase_width - 1 downto phase_width - 18))
- base_phase(23 downto 6);
end process;
end downconvertpll;
| gpl-3.0 | 2d4371b2e07d42d8ca8a51a40c815fa6 | 0.608483 | 3.382199 | false | false | false | false |
scriptum/geany | tests/ctags/test.vhd | 91 | 192,381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 | 1ec3b10fa91fb04a8bf002fc7691ad9d | 0.536539 | 3.497264 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12,722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| apache-2.0 | 4613518e30fbd0af4486402f291067b7 | 0.414164 | 5.574934 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC/mod10.vhd | 1 | 1,114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod10 is --porty we / wy
Port(outp : out std_logic_vector(3 downto 0);
dir : in std_logic;
carry: out std_logic;
clr : in std_logic;
clk : in std_logic);
end mod10;
architecture Behavioral of mod10 is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk,clr, dir)
begin -- wyzeruj licznik oraz pozyczke
if clr = '1' then
temp<="0000";
carry <= '0';
-- licz gdu narastajace zbocze na zegarze
elsif rising_edge(clk) then
--jesli dir "1" liczy do gory, oraz sprawdza stan licznika
--po przepelnieni zeruje sie i ustawia pozyczke na "1"
--analogicznie dla dir "0"
if dir = '1' then
if temp <= "1000" then
temp <= temp+1;
carry <='0';
else
temp <= "0000";
carry <= '1';
end if;
elsif dir = '0' then
if temp >= "0001" then
temp <= temp - 1;
carry <='0';
else
temp <= "1001";
carry <= '1';
end if;
end if;
end if;
outp<=temp;
end process;
end Behavioral;
| gpl-3.0 | 868b109cc1d35bfa5ce6edd842a5f3b6 | 0.598743 | 2.710462 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/dynshreg_f.vhd | 15 | 15,946 | -------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v4_0.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| apache-2.0 | e4454bbaa7af0ad21b7a90404776653e | 0.470275 | 4.546906 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_utlb.vhd | 1 | 55,025 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 6064ca79fdf4adce59f7c02e2121ca06 | 0.950822 | 1.829714 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/async_fifo.vhd | 5 | 33,343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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| apache-2.0 | 13254917cab9fe21d12d3bdc3a7f2a33 | 0.945536 | 1.835563 | false | false | false | false |
zefie/hackrf | firmware/cpld/sgpio_if/top.vhd | 1 | 4,811 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"7f";
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
dac_data_o <= (data_from_host_i xor X"7f") & "11";
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 89f6d2c33f07e66a7a22395e247e51d8 | 0.533777 | 3.782233 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/asap-alap-random/ewf_random.vhd | 1 | 3,164 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_random_entity;
ARCHITECTURE ewf_random_description OF ewf_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
WHEN "00000111" =>
register4 := register4 + register5;
register6 := register1 + register6;
register3 := register3 + register5;
WHEN "00001000" =>
register1 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
register1 := register1 * 14;
WHEN "00001010" =>
register1 := register1 + 16;
register3 := register2 + register3;
WHEN "00001011" =>
register7 := register6 + register1;
register2 := register2 + register3;
WHEN "00001100" =>
register7 := register7 + 18;
register5 := register5 + register3;
WHEN "00001101" =>
register8 := register7 * 20;
output1 <= register6 + register4;
WHEN "00001110" =>
register4 := register8 + 23;
register6 := register1 + 25;
register2 := register2 * 27;
WHEN "00001111" =>
register6 := register6 * 29;
output2 <= register7 + register4;
register4 := register5 + 32;
register2 := register2 + 34;
WHEN "00010000" =>
output3 <= register3 + register2;
output4 <= register1 + register6;
register1 := register4 * 38;
WHEN "00010001" =>
register1 := register1 + 40;
WHEN "00010010" =>
output5 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_random_description; | gpl-3.0 | 5dcc943964b1226bb9aea2e826f89826 | 0.678571 | 3.43913 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_nsga2.vhd | 1 | 1,628 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:04:40)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_nsga2_entity;
ARCHITECTURE hal_nsga2_description OF hal_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_nsga2_description; | gpl-3.0 | 059185caa203c96505db8cb7dd278adb | 0.672604 | 3.10687 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/stream_cache.vhd | 1 | 32,395 | `protect begin_protected
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| apache-2.0 | 0d29d3bc2920d5a5027421982987f2df | 0.945763 | 1.837701 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/asap-alap-random/hal_random.vhd | 1 | 1,824 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:58:13)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_random_entity;
ARCHITECTURE hal_random_description OF hal_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := input3 * 3;
WHEN "00000011" =>
register4 := input4 * 4;
output1 <= register1 + 5;
WHEN "00000100" =>
register1 := input5 * 6;
WHEN "00000101" =>
register1 := register4 * register1;
WHEN "00000110" =>
register1 := register1 - 8;
register3 := register3 * 10;
IF (register2 < 11) THEN
output2 <= register2;
ELSE
output2 <= "0000000000000000000000000001011";
END IF;
WHEN "00000111" =>
output3 <= register1 - register3;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_random_description; | gpl-3.0 | 4451dcc387dcc84ea7d5be31cae99044 | 0.683662 | 3.286486 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_prim.vhd | 5 | 111,502 | `protect begin_protected
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`protect end_protected
| apache-2.0 | e839add713550587695b6f73629aaad0 | 0.952503 | 1.812422 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/pc_module_gti.vhd | 1 | 107,632 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | b569d05534f7a3862c80f6307bc23cbc | 0.953471 | 1.814063 | false | false | false | false |
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